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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
4ff37a83 CK |
53 | /* Special value that no flush is necessary */ |
54 | #define AMDGPU_VM_NO_FLUSH (~0ll) | |
55 | ||
d38ceaf9 AD |
56 | /** |
57 | * amdgpu_vm_num_pde - return the number of page directory entries | |
58 | * | |
59 | * @adev: amdgpu_device pointer | |
60 | * | |
8843dbbb | 61 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
62 | */ |
63 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
64 | { | |
65 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
66 | } | |
67 | ||
68 | /** | |
69 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
70 | * | |
71 | * @adev: amdgpu_device pointer | |
72 | * | |
8843dbbb | 73 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
74 | */ |
75 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
76 | { | |
77 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
78 | } | |
79 | ||
80 | /** | |
56467ebf | 81 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
82 | * |
83 | * @vm: vm providing the BOs | |
3c0eea6c | 84 | * @validated: head of validation list |
56467ebf | 85 | * @entry: entry to add |
d38ceaf9 AD |
86 | * |
87 | * Add the page directory to the list of BOs to | |
56467ebf | 88 | * validate for command submission. |
d38ceaf9 | 89 | */ |
56467ebf CK |
90 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
91 | struct list_head *validated, | |
92 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 93 | { |
56467ebf | 94 | entry->robj = vm->page_directory; |
56467ebf CK |
95 | entry->priority = 0; |
96 | entry->tv.bo = &vm->page_directory->tbo; | |
97 | entry->tv.shared = true; | |
98 | list_add(&entry->tv.head, validated); | |
99 | } | |
d38ceaf9 | 100 | |
56467ebf | 101 | /** |
ee1782c3 | 102 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf CK |
103 | * |
104 | * @vm: vm providing the BOs | |
3c0eea6c | 105 | * @duplicates: head of duplicates list |
d38ceaf9 | 106 | * |
ee1782c3 CK |
107 | * Add the page directory to the BO duplicates list |
108 | * for command submission. | |
d38ceaf9 | 109 | */ |
ee1782c3 | 110 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates) |
d38ceaf9 | 111 | { |
ee1782c3 | 112 | unsigned i; |
d38ceaf9 AD |
113 | |
114 | /* add the vm page table to the list */ | |
ee1782c3 CK |
115 | for (i = 0; i <= vm->max_pde_used; ++i) { |
116 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
117 | ||
118 | if (!entry->robj) | |
d38ceaf9 AD |
119 | continue; |
120 | ||
ee1782c3 | 121 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 122 | } |
eceb8a15 CK |
123 | |
124 | } | |
125 | ||
126 | /** | |
127 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
128 | * | |
129 | * @adev: amdgpu device instance | |
130 | * @vm: vm providing the BOs | |
131 | * | |
132 | * Move the PT BOs to the tail of the LRU. | |
133 | */ | |
134 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
135 | struct amdgpu_vm *vm) | |
136 | { | |
137 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
138 | unsigned i; | |
139 | ||
140 | spin_lock(&glob->lru_lock); | |
141 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
142 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
143 | ||
144 | if (!entry->robj) | |
145 | continue; | |
146 | ||
147 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
148 | } | |
149 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
150 | } |
151 | ||
152 | /** | |
153 | * amdgpu_vm_grab_id - allocate the next free VMID | |
154 | * | |
d38ceaf9 | 155 | * @vm: vm to allocate id for |
7f8a5290 CK |
156 | * @ring: ring we want to submit job to |
157 | * @sync: sync object where we add dependencies | |
94dd0a4a | 158 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 159 | * |
7f8a5290 | 160 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 161 | */ |
7f8a5290 | 162 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 CK |
163 | struct amdgpu_sync *sync, struct fence *fence, |
164 | unsigned *vm_id, uint64_t *vm_pd_addr) | |
d38ceaf9 | 165 | { |
4ff37a83 | 166 | uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); |
d38ceaf9 | 167 | struct amdgpu_device *adev = ring->adev; |
4ff37a83 CK |
168 | struct amdgpu_vm_id *id = &vm->ids[ring->idx]; |
169 | struct fence *updates = sync->last_vm_update; | |
a9a78b32 | 170 | int r; |
d38ceaf9 | 171 | |
94dd0a4a CK |
172 | mutex_lock(&adev->vm_manager.lock); |
173 | ||
d38ceaf9 | 174 | /* check if the id is still valid */ |
4ff37a83 CK |
175 | if (id->mgr_id) { |
176 | struct fence *flushed = id->flushed_updates; | |
177 | bool is_later; | |
1c16c0a7 CK |
178 | long owner; |
179 | ||
4ff37a83 CK |
180 | if (!flushed) |
181 | is_later = true; | |
182 | else if (!updates) | |
183 | is_later = false; | |
184 | else | |
185 | is_later = fence_is_later(updates, flushed); | |
186 | ||
187 | owner = atomic_long_read(&id->mgr_id->owner); | |
188 | if (!is_later && owner == (long)id && | |
189 | pd_addr == id->pd_gpu_addr) { | |
190 | ||
191 | fence_put(id->mgr_id->active); | |
192 | id->mgr_id->active = fence_get(fence); | |
193 | ||
194 | list_move_tail(&id->mgr_id->list, | |
195 | &adev->vm_manager.ids_lru); | |
d38ceaf9 | 196 | |
4ff37a83 CK |
197 | *vm_id = id->mgr_id - adev->vm_manager.ids; |
198 | *vm_pd_addr = AMDGPU_VM_NO_FLUSH; | |
199 | trace_amdgpu_vm_grab_id(vm, *vm_id, ring->idx); | |
d38ceaf9 | 200 | |
94dd0a4a | 201 | mutex_unlock(&adev->vm_manager.lock); |
7f8a5290 | 202 | return 0; |
d38ceaf9 | 203 | } |
d38ceaf9 AD |
204 | } |
205 | ||
4ff37a83 CK |
206 | id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru, |
207 | struct amdgpu_vm_manager_id, | |
208 | list); | |
7f8a5290 | 209 | |
4ff37a83 CK |
210 | r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active); |
211 | if (!r) { | |
212 | fence_put(id->mgr_id->active); | |
213 | id->mgr_id->active = fence_get(fence); | |
94dd0a4a | 214 | |
4ff37a83 CK |
215 | fence_put(id->flushed_updates); |
216 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 217 | |
4ff37a83 | 218 | id->pd_gpu_addr = pd_addr; |
94dd0a4a | 219 | |
4ff37a83 CK |
220 | list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru); |
221 | atomic_long_set(&id->mgr_id->owner, (long)id); | |
222 | ||
223 | *vm_id = id->mgr_id - adev->vm_manager.ids; | |
224 | *vm_pd_addr = pd_addr; | |
225 | trace_amdgpu_vm_grab_id(vm, *vm_id, ring->idx); | |
d38ceaf9 AD |
226 | } |
227 | ||
94dd0a4a | 228 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 229 | return r; |
d38ceaf9 AD |
230 | } |
231 | ||
232 | /** | |
233 | * amdgpu_vm_flush - hardware flush the vm | |
234 | * | |
235 | * @ring: ring to use for flush | |
4ff37a83 CK |
236 | * @vmid: vmid number to use |
237 | * @pd_addr: address of the page directory | |
d38ceaf9 | 238 | * |
4ff37a83 | 239 | * Emit a VM flush when it is necessary. |
d38ceaf9 AD |
240 | */ |
241 | void amdgpu_vm_flush(struct amdgpu_ring *ring, | |
4ff37a83 CK |
242 | unsigned vmid, |
243 | uint64_t pd_addr) | |
d38ceaf9 | 244 | { |
4ff37a83 CK |
245 | if (pd_addr != AMDGPU_VM_NO_FLUSH) { |
246 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vmid); | |
247 | amdgpu_ring_emit_vm_flush(ring, vmid, pd_addr); | |
d38ceaf9 AD |
248 | } |
249 | } | |
250 | ||
d38ceaf9 AD |
251 | /** |
252 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
253 | * | |
254 | * @vm: requested vm | |
255 | * @bo: requested buffer object | |
256 | * | |
8843dbbb | 257 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
258 | * Search inside the @bos vm list for the requested vm |
259 | * Returns the found bo_va or NULL if none is found | |
260 | * | |
261 | * Object has to be reserved! | |
262 | */ | |
263 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
264 | struct amdgpu_bo *bo) | |
265 | { | |
266 | struct amdgpu_bo_va *bo_va; | |
267 | ||
268 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
269 | if (bo_va->vm == vm) { | |
270 | return bo_va; | |
271 | } | |
272 | } | |
273 | return NULL; | |
274 | } | |
275 | ||
276 | /** | |
277 | * amdgpu_vm_update_pages - helper to call the right asic function | |
278 | * | |
279 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
280 | * @gtt: GART instance to use for mapping |
281 | * @gtt_flags: GTT hw access flags | |
d38ceaf9 AD |
282 | * @ib: indirect buffer to fill with commands |
283 | * @pe: addr of the page entry | |
284 | * @addr: dst addr to write into pe | |
285 | * @count: number of page entries to update | |
286 | * @incr: increase next addr by incr bytes | |
287 | * @flags: hw access flags | |
d38ceaf9 AD |
288 | * |
289 | * Traces the parameters and calls the right asic functions | |
290 | * to setup the page table using the DMA. | |
291 | */ | |
292 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
9ab21462 CK |
293 | struct amdgpu_gart *gtt, |
294 | uint32_t gtt_flags, | |
d38ceaf9 AD |
295 | struct amdgpu_ib *ib, |
296 | uint64_t pe, uint64_t addr, | |
297 | unsigned count, uint32_t incr, | |
9ab21462 | 298 | uint32_t flags) |
d38ceaf9 AD |
299 | { |
300 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
301 | ||
9ab21462 CK |
302 | if ((gtt == &adev->gart) && (flags == gtt_flags)) { |
303 | uint64_t src = gtt->table_addr + (addr >> 12) * 8; | |
d38ceaf9 AD |
304 | amdgpu_vm_copy_pte(adev, ib, pe, src, count); |
305 | ||
9ab21462 CK |
306 | } else if (gtt) { |
307 | dma_addr_t *pages_addr = gtt->pages_addr; | |
b07c9d2a CK |
308 | amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr, |
309 | count, incr, flags); | |
310 | ||
311 | } else if (count < 3) { | |
312 | amdgpu_vm_write_pte(adev, ib, NULL, pe, addr, | |
313 | count, incr, flags); | |
d38ceaf9 AD |
314 | |
315 | } else { | |
316 | amdgpu_vm_set_pte_pde(adev, ib, pe, addr, | |
317 | count, incr, flags); | |
318 | } | |
319 | } | |
320 | ||
321 | /** | |
322 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
323 | * | |
324 | * @adev: amdgpu_device pointer | |
325 | * @bo: bo to clear | |
ef9f0a83 CZ |
326 | * |
327 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
328 | */ |
329 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 330 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
331 | struct amdgpu_bo *bo) |
332 | { | |
2d55e45a | 333 | struct amdgpu_ring *ring; |
4af9f07c | 334 | struct fence *fence = NULL; |
d71518b5 | 335 | struct amdgpu_job *job; |
d38ceaf9 AD |
336 | unsigned entries; |
337 | uint64_t addr; | |
338 | int r; | |
339 | ||
2d55e45a CK |
340 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
341 | ||
ca952613 | 342 | r = reservation_object_reserve_shared(bo->tbo.resv); |
343 | if (r) | |
344 | return r; | |
345 | ||
d38ceaf9 AD |
346 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
347 | if (r) | |
ef9f0a83 | 348 | goto error; |
d38ceaf9 AD |
349 | |
350 | addr = amdgpu_bo_gpu_offset(bo); | |
351 | entries = amdgpu_bo_size(bo) / 8; | |
352 | ||
d71518b5 CK |
353 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
354 | if (r) | |
ef9f0a83 | 355 | goto error; |
d38ceaf9 | 356 | |
d71518b5 CK |
357 | amdgpu_vm_update_pages(adev, NULL, 0, &job->ibs[0], addr, 0, entries, |
358 | 0, 0); | |
359 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); | |
360 | ||
361 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
362 | r = amdgpu_job_submit(job, ring, &vm->entity, |
363 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
364 | if (r) |
365 | goto error_free; | |
366 | ||
d71518b5 | 367 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 368 | fence_put(fence); |
cadf97b1 | 369 | return 0; |
ef9f0a83 | 370 | |
d38ceaf9 | 371 | error_free: |
d71518b5 | 372 | amdgpu_job_free(job); |
d38ceaf9 | 373 | |
ef9f0a83 | 374 | error: |
d38ceaf9 AD |
375 | return r; |
376 | } | |
377 | ||
378 | /** | |
b07c9d2a | 379 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 380 | * |
b07c9d2a | 381 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
382 | * @addr: the unmapped addr |
383 | * | |
384 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 385 | * to and return the pointer for the page table entry. |
d38ceaf9 | 386 | */ |
b07c9d2a | 387 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
388 | { |
389 | uint64_t result; | |
390 | ||
b07c9d2a CK |
391 | if (pages_addr) { |
392 | /* page table offset */ | |
393 | result = pages_addr[addr >> PAGE_SHIFT]; | |
394 | ||
395 | /* in case cpu page size != gpu page size*/ | |
396 | result |= addr & (~PAGE_MASK); | |
397 | ||
398 | } else { | |
399 | /* No mapping required */ | |
400 | result = addr; | |
401 | } | |
d38ceaf9 | 402 | |
b07c9d2a | 403 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
404 | |
405 | return result; | |
406 | } | |
407 | ||
408 | /** | |
409 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
410 | * | |
411 | * @adev: amdgpu_device pointer | |
412 | * @vm: requested vm | |
413 | * @start: start of GPU address range | |
414 | * @end: end of GPU address range | |
415 | * | |
416 | * Allocates new page tables if necessary | |
8843dbbb | 417 | * and updates the page directory. |
d38ceaf9 | 418 | * Returns 0 for success, error for failure. |
d38ceaf9 AD |
419 | */ |
420 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
421 | struct amdgpu_vm *vm) | |
422 | { | |
2d55e45a | 423 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
424 | struct amdgpu_bo *pd = vm->page_directory; |
425 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
426 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
427 | uint64_t last_pde = ~0, last_pt = ~0; | |
428 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 429 | struct amdgpu_job *job; |
d5fc5e82 | 430 | struct amdgpu_ib *ib; |
4af9f07c | 431 | struct fence *fence = NULL; |
d5fc5e82 | 432 | |
d38ceaf9 AD |
433 | int r; |
434 | ||
2d55e45a CK |
435 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
436 | ||
d38ceaf9 AD |
437 | /* padding, etc. */ |
438 | ndw = 64; | |
439 | ||
440 | /* assume the worst case */ | |
441 | ndw += vm->max_pde_used * 6; | |
442 | ||
d71518b5 CK |
443 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
444 | if (r) | |
d38ceaf9 | 445 | return r; |
d71518b5 CK |
446 | |
447 | ib = &job->ibs[0]; | |
d38ceaf9 AD |
448 | |
449 | /* walk over the address space and update the page directory */ | |
450 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 451 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
452 | uint64_t pde, pt; |
453 | ||
454 | if (bo == NULL) | |
455 | continue; | |
456 | ||
457 | pt = amdgpu_bo_gpu_offset(bo); | |
458 | if (vm->page_tables[pt_idx].addr == pt) | |
459 | continue; | |
460 | vm->page_tables[pt_idx].addr = pt; | |
461 | ||
462 | pde = pd_addr + pt_idx * 8; | |
463 | if (((last_pde + 8 * count) != pde) || | |
464 | ((last_pt + incr * count) != pt)) { | |
465 | ||
466 | if (count) { | |
9ab21462 CK |
467 | amdgpu_vm_update_pages(adev, NULL, 0, ib, |
468 | last_pde, last_pt, | |
469 | count, incr, | |
470 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
471 | } |
472 | ||
473 | count = 1; | |
474 | last_pde = pde; | |
475 | last_pt = pt; | |
476 | } else { | |
477 | ++count; | |
478 | } | |
479 | } | |
480 | ||
481 | if (count) | |
9ab21462 CK |
482 | amdgpu_vm_update_pages(adev, NULL, 0, ib, last_pde, last_pt, |
483 | count, incr, AMDGPU_PTE_VALID); | |
d38ceaf9 | 484 | |
d5fc5e82 | 485 | if (ib->length_dw != 0) { |
9e5d5309 | 486 | amdgpu_ring_pad_ib(ring, ib); |
e86f9cee CK |
487 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
488 | AMDGPU_FENCE_OWNER_VM); | |
d5fc5e82 | 489 | WARN_ON(ib->length_dw > ndw); |
2bd9ccfa CK |
490 | r = amdgpu_job_submit(job, ring, &vm->entity, |
491 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
492 | if (r) |
493 | goto error_free; | |
05906dec | 494 | |
4af9f07c | 495 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
496 | fence_put(vm->page_directory_fence); |
497 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 498 | fence_put(fence); |
d5fc5e82 | 499 | |
d71518b5 CK |
500 | } else { |
501 | amdgpu_job_free(job); | |
d5fc5e82 | 502 | } |
d38ceaf9 AD |
503 | |
504 | return 0; | |
d5fc5e82 CZ |
505 | |
506 | error_free: | |
d71518b5 | 507 | amdgpu_job_free(job); |
4af9f07c | 508 | return r; |
d38ceaf9 AD |
509 | } |
510 | ||
511 | /** | |
512 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
513 | * | |
514 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
515 | * @gtt: GART instance to use for mapping |
516 | * @gtt_flags: GTT hw mapping flags | |
d38ceaf9 AD |
517 | * @ib: IB for the update |
518 | * @pe_start: first PTE to handle | |
519 | * @pe_end: last PTE to handle | |
520 | * @addr: addr those PTEs should point to | |
521 | * @flags: hw mapping flags | |
d38ceaf9 AD |
522 | */ |
523 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
9ab21462 CK |
524 | struct amdgpu_gart *gtt, |
525 | uint32_t gtt_flags, | |
d38ceaf9 AD |
526 | struct amdgpu_ib *ib, |
527 | uint64_t pe_start, uint64_t pe_end, | |
9ab21462 | 528 | uint64_t addr, uint32_t flags) |
d38ceaf9 AD |
529 | { |
530 | /** | |
531 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
532 | * field in the PTE. When this field is set to a non-zero value, page | |
533 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
534 | * flags are considered valid for all PTEs within the fragment range | |
535 | * and corresponding mappings are assumed to be physically contiguous. | |
536 | * | |
537 | * The L1 TLB can store a single PTE for the whole fragment, | |
538 | * significantly increasing the space available for translation | |
539 | * caching. This leads to large improvements in throughput when the | |
540 | * TLB is under pressure. | |
541 | * | |
542 | * The L2 TLB distributes small and large fragments into two | |
543 | * asymmetric partitions. The large fragment cache is significantly | |
544 | * larger. Thus, we try to use large fragments wherever possible. | |
545 | * Userspace can support this by aligning virtual base address and | |
546 | * allocation size to the fragment size. | |
547 | */ | |
548 | ||
549 | /* SI and newer are optimized for 64KB */ | |
550 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
551 | uint64_t frag_align = 0x80; | |
552 | ||
553 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
554 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
555 | ||
556 | unsigned count; | |
557 | ||
31f6c1fe CK |
558 | /* Abort early if there isn't anything to do */ |
559 | if (pe_start == pe_end) | |
560 | return; | |
561 | ||
d38ceaf9 | 562 | /* system pages are non continuously */ |
9ab21462 | 563 | if (gtt || !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) { |
d38ceaf9 AD |
564 | |
565 | count = (pe_end - pe_start) / 8; | |
9ab21462 CK |
566 | amdgpu_vm_update_pages(adev, gtt, gtt_flags, ib, pe_start, |
567 | addr, count, AMDGPU_GPU_PAGE_SIZE, | |
568 | flags); | |
d38ceaf9 AD |
569 | return; |
570 | } | |
571 | ||
572 | /* handle the 4K area at the beginning */ | |
573 | if (pe_start != frag_start) { | |
574 | count = (frag_start - pe_start) / 8; | |
9ab21462 CK |
575 | amdgpu_vm_update_pages(adev, NULL, 0, ib, pe_start, addr, |
576 | count, AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
577 | addr += AMDGPU_GPU_PAGE_SIZE * count; |
578 | } | |
579 | ||
580 | /* handle the area in the middle */ | |
581 | count = (frag_end - frag_start) / 8; | |
9ab21462 CK |
582 | amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_start, addr, count, |
583 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags); | |
d38ceaf9 AD |
584 | |
585 | /* handle the 4K area at the end */ | |
586 | if (frag_end != pe_end) { | |
587 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
588 | count = (pe_end - frag_end) / 8; | |
9ab21462 CK |
589 | amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_end, addr, |
590 | count, AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
591 | } |
592 | } | |
593 | ||
594 | /** | |
595 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
596 | * | |
597 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
598 | * @gtt: GART instance to use for mapping |
599 | * @gtt_flags: GTT hw mapping flags | |
d38ceaf9 AD |
600 | * @vm: requested vm |
601 | * @start: start of GPU address range | |
602 | * @end: end of GPU address range | |
603 | * @dst: destination address to map to | |
604 | * @flags: mapping flags | |
605 | * | |
8843dbbb | 606 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 607 | */ |
a1e08d3b CK |
608 | static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, |
609 | struct amdgpu_gart *gtt, | |
610 | uint32_t gtt_flags, | |
611 | struct amdgpu_vm *vm, | |
612 | struct amdgpu_ib *ib, | |
613 | uint64_t start, uint64_t end, | |
614 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 615 | { |
31f6c1fe CK |
616 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
617 | ||
618 | uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0; | |
d38ceaf9 AD |
619 | uint64_t addr; |
620 | ||
621 | /* walk over the address space and update the page tables */ | |
622 | for (addr = start; addr < end; ) { | |
623 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | |
ee1782c3 | 624 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 | 625 | unsigned nptes; |
31f6c1fe | 626 | uint64_t pe_start; |
d38ceaf9 AD |
627 | |
628 | if ((addr & ~mask) == (end & ~mask)) | |
629 | nptes = end - addr; | |
630 | else | |
631 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
632 | ||
31f6c1fe CK |
633 | pe_start = amdgpu_bo_gpu_offset(pt); |
634 | pe_start += (addr & mask) * 8; | |
d38ceaf9 | 635 | |
31f6c1fe | 636 | if (last_pe_end != pe_start) { |
d38ceaf9 | 637 | |
31f6c1fe CK |
638 | amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib, |
639 | last_pe_start, last_pe_end, | |
640 | last_dst, flags); | |
d38ceaf9 | 641 | |
31f6c1fe CK |
642 | last_pe_start = pe_start; |
643 | last_pe_end = pe_start + 8 * nptes; | |
d38ceaf9 AD |
644 | last_dst = dst; |
645 | } else { | |
31f6c1fe | 646 | last_pe_end += 8 * nptes; |
d38ceaf9 AD |
647 | } |
648 | ||
649 | addr += nptes; | |
650 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
651 | } | |
652 | ||
31f6c1fe CK |
653 | amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib, |
654 | last_pe_start, last_pe_end, | |
655 | last_dst, flags); | |
d38ceaf9 AD |
656 | } |
657 | ||
d38ceaf9 AD |
658 | /** |
659 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
660 | * | |
661 | * @adev: amdgpu_device pointer | |
9ab21462 | 662 | * @gtt: GART instance to use for mapping |
a14faa65 | 663 | * @gtt_flags: flags as they are used for GTT |
d38ceaf9 | 664 | * @vm: requested vm |
a14faa65 CK |
665 | * @start: start of mapped range |
666 | * @last: last mapped entry | |
667 | * @flags: flags for the entries | |
d38ceaf9 | 668 | * @addr: addr to set the area to |
d38ceaf9 AD |
669 | * @fence: optional resulting fence |
670 | * | |
a14faa65 | 671 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 672 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
673 | */ |
674 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
9ab21462 CK |
675 | struct amdgpu_gart *gtt, |
676 | uint32_t gtt_flags, | |
d38ceaf9 | 677 | struct amdgpu_vm *vm, |
a14faa65 CK |
678 | uint64_t start, uint64_t last, |
679 | uint32_t flags, uint64_t addr, | |
680 | struct fence **fence) | |
d38ceaf9 | 681 | { |
2d55e45a | 682 | struct amdgpu_ring *ring; |
a1e08d3b | 683 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 684 | unsigned nptes, ncmds, ndw; |
d71518b5 | 685 | struct amdgpu_job *job; |
d5fc5e82 | 686 | struct amdgpu_ib *ib; |
4af9f07c | 687 | struct fence *f = NULL; |
d38ceaf9 AD |
688 | int r; |
689 | ||
2d55e45a CK |
690 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
691 | ||
a1e08d3b CK |
692 | /* sync to everything on unmapping */ |
693 | if (!(flags & AMDGPU_PTE_VALID)) | |
694 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
695 | ||
a14faa65 | 696 | nptes = last - start + 1; |
d38ceaf9 AD |
697 | |
698 | /* | |
699 | * reserve space for one command every (1 << BLOCK_SIZE) | |
700 | * entries or 2k dwords (whatever is smaller) | |
701 | */ | |
702 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
703 | ||
704 | /* padding, etc. */ | |
705 | ndw = 64; | |
706 | ||
9ab21462 | 707 | if ((gtt == &adev->gart) && (flags == gtt_flags)) { |
d38ceaf9 AD |
708 | /* only copy commands needed */ |
709 | ndw += ncmds * 7; | |
710 | ||
9ab21462 | 711 | } else if (gtt) { |
d38ceaf9 AD |
712 | /* header for write data commands */ |
713 | ndw += ncmds * 4; | |
714 | ||
715 | /* body of write data command */ | |
716 | ndw += nptes * 2; | |
717 | ||
718 | } else { | |
719 | /* set page commands needed */ | |
720 | ndw += ncmds * 10; | |
721 | ||
722 | /* two extra commands for begin/end of fragment */ | |
723 | ndw += 2 * 10; | |
724 | } | |
725 | ||
d71518b5 CK |
726 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
727 | if (r) | |
d38ceaf9 | 728 | return r; |
d71518b5 CK |
729 | |
730 | ib = &job->ibs[0]; | |
d5fc5e82 | 731 | |
e86f9cee | 732 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
733 | owner); |
734 | if (r) | |
735 | goto error_free; | |
d38ceaf9 | 736 | |
a1e08d3b CK |
737 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
738 | if (r) | |
739 | goto error_free; | |
740 | ||
741 | amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start, last + 1, | |
742 | addr, flags); | |
d38ceaf9 | 743 | |
9e5d5309 | 744 | amdgpu_ring_pad_ib(ring, ib); |
d5fc5e82 | 745 | WARN_ON(ib->length_dw > ndw); |
2bd9ccfa CK |
746 | r = amdgpu_job_submit(job, ring, &vm->entity, |
747 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
748 | if (r) |
749 | goto error_free; | |
d38ceaf9 | 750 | |
bf60efd3 | 751 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
752 | if (fence) { |
753 | fence_put(*fence); | |
754 | *fence = fence_get(f); | |
755 | } | |
281b4223 | 756 | fence_put(f); |
d38ceaf9 | 757 | return 0; |
d5fc5e82 CZ |
758 | |
759 | error_free: | |
d71518b5 | 760 | amdgpu_job_free(job); |
4af9f07c | 761 | return r; |
d38ceaf9 AD |
762 | } |
763 | ||
a14faa65 CK |
764 | /** |
765 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
766 | * | |
767 | * @adev: amdgpu_device pointer | |
768 | * @gtt: GART instance to use for mapping | |
769 | * @vm: requested vm | |
770 | * @mapping: mapped range and flags to use for the update | |
771 | * @addr: addr to set the area to | |
772 | * @gtt_flags: flags as they are used for GTT | |
773 | * @fence: optional resulting fence | |
774 | * | |
775 | * Split the mapping into smaller chunks so that each update fits | |
776 | * into a SDMA IB. | |
777 | * Returns 0 for success, -EINVAL for failure. | |
778 | */ | |
779 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
780 | struct amdgpu_gart *gtt, | |
781 | uint32_t gtt_flags, | |
782 | struct amdgpu_vm *vm, | |
783 | struct amdgpu_bo_va_mapping *mapping, | |
784 | uint64_t addr, struct fence **fence) | |
785 | { | |
786 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
787 | ||
788 | uint64_t start = mapping->it.start; | |
789 | uint32_t flags = gtt_flags; | |
790 | int r; | |
791 | ||
792 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
793 | * but in case of something, we filter the flags in first place | |
794 | */ | |
795 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
796 | flags &= ~AMDGPU_PTE_READABLE; | |
797 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
798 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
799 | ||
800 | trace_amdgpu_vm_bo_update(mapping); | |
801 | ||
802 | addr += mapping->offset; | |
803 | ||
804 | if (!gtt || ((gtt == &adev->gart) && (flags == gtt_flags))) | |
805 | return amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm, | |
806 | start, mapping->it.last, | |
807 | flags, addr, fence); | |
808 | ||
809 | while (start != mapping->it.last + 1) { | |
810 | uint64_t last; | |
811 | ||
812 | last = min((uint64_t)mapping->it.last, start + max_size); | |
813 | r = amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm, | |
814 | start, last, flags, addr, | |
815 | fence); | |
816 | if (r) | |
817 | return r; | |
818 | ||
819 | start = last + 1; | |
820 | addr += max_size; | |
821 | } | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
d38ceaf9 AD |
826 | /** |
827 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
828 | * | |
829 | * @adev: amdgpu_device pointer | |
830 | * @bo_va: requested BO and VM object | |
831 | * @mem: ttm mem | |
832 | * | |
833 | * Fill in the page table entries for @bo_va. | |
834 | * Returns 0 for success, -EINVAL for failure. | |
835 | * | |
836 | * Object have to be reserved and mutex must be locked! | |
837 | */ | |
838 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
839 | struct amdgpu_bo_va *bo_va, | |
840 | struct ttm_mem_reg *mem) | |
841 | { | |
842 | struct amdgpu_vm *vm = bo_va->vm; | |
843 | struct amdgpu_bo_va_mapping *mapping; | |
9ab21462 | 844 | struct amdgpu_gart *gtt = NULL; |
d38ceaf9 AD |
845 | uint32_t flags; |
846 | uint64_t addr; | |
847 | int r; | |
848 | ||
849 | if (mem) { | |
b7d698d7 | 850 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
851 | switch (mem->mem_type) { |
852 | case TTM_PL_TT: | |
853 | gtt = &bo_va->bo->adev->gart; | |
854 | break; | |
855 | ||
856 | case TTM_PL_VRAM: | |
d38ceaf9 | 857 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
858 | break; |
859 | ||
860 | default: | |
861 | break; | |
862 | } | |
d38ceaf9 AD |
863 | } else { |
864 | addr = 0; | |
865 | } | |
866 | ||
d38ceaf9 AD |
867 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
868 | ||
7fc11959 CK |
869 | spin_lock(&vm->status_lock); |
870 | if (!list_empty(&bo_va->vm_status)) | |
871 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
872 | spin_unlock(&vm->status_lock); | |
873 | ||
874 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a14faa65 CK |
875 | r = amdgpu_vm_bo_split_mapping(adev, gtt, flags, vm, mapping, addr, |
876 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
877 | if (r) |
878 | return r; | |
879 | } | |
880 | ||
d6c10f6b CK |
881 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
882 | list_for_each_entry(mapping, &bo_va->valids, list) | |
883 | trace_amdgpu_vm_bo_mapping(mapping); | |
884 | ||
885 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
886 | trace_amdgpu_vm_bo_mapping(mapping); | |
887 | } | |
888 | ||
d38ceaf9 | 889 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 890 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 891 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
892 | if (!mem) |
893 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
894 | spin_unlock(&vm->status_lock); |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
899 | /** | |
900 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
901 | * | |
902 | * @adev: amdgpu_device pointer | |
903 | * @vm: requested vm | |
904 | * | |
905 | * Make sure all freed BOs are cleared in the PT. | |
906 | * Returns 0 for success. | |
907 | * | |
908 | * PTs have to be reserved and mutex must be locked! | |
909 | */ | |
910 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
911 | struct amdgpu_vm *vm) | |
912 | { | |
913 | struct amdgpu_bo_va_mapping *mapping; | |
914 | int r; | |
915 | ||
81d75a30 | 916 | spin_lock(&vm->freed_lock); |
d38ceaf9 AD |
917 | while (!list_empty(&vm->freed)) { |
918 | mapping = list_first_entry(&vm->freed, | |
919 | struct amdgpu_bo_va_mapping, list); | |
920 | list_del(&mapping->list); | |
81d75a30 | 921 | spin_unlock(&vm->freed_lock); |
a14faa65 CK |
922 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, vm, mapping, |
923 | 0, NULL); | |
d38ceaf9 AD |
924 | kfree(mapping); |
925 | if (r) | |
926 | return r; | |
927 | ||
81d75a30 | 928 | spin_lock(&vm->freed_lock); |
d38ceaf9 | 929 | } |
81d75a30 | 930 | spin_unlock(&vm->freed_lock); |
931 | ||
d38ceaf9 AD |
932 | return 0; |
933 | ||
934 | } | |
935 | ||
936 | /** | |
937 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
938 | * | |
939 | * @adev: amdgpu_device pointer | |
940 | * @vm: requested vm | |
941 | * | |
942 | * Make sure all invalidated BOs are cleared in the PT. | |
943 | * Returns 0 for success. | |
944 | * | |
945 | * PTs have to be reserved and mutex must be locked! | |
946 | */ | |
947 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 948 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 949 | { |
cfe2c978 | 950 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 951 | int r = 0; |
d38ceaf9 AD |
952 | |
953 | spin_lock(&vm->status_lock); | |
954 | while (!list_empty(&vm->invalidated)) { | |
955 | bo_va = list_first_entry(&vm->invalidated, | |
956 | struct amdgpu_bo_va, vm_status); | |
957 | spin_unlock(&vm->status_lock); | |
69b576a1 | 958 | mutex_lock(&bo_va->mutex); |
d38ceaf9 | 959 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
69b576a1 | 960 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 AD |
961 | if (r) |
962 | return r; | |
963 | ||
964 | spin_lock(&vm->status_lock); | |
965 | } | |
966 | spin_unlock(&vm->status_lock); | |
967 | ||
cfe2c978 | 968 | if (bo_va) |
bb1e38a4 | 969 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
970 | |
971 | return r; | |
d38ceaf9 AD |
972 | } |
973 | ||
974 | /** | |
975 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
976 | * | |
977 | * @adev: amdgpu_device pointer | |
978 | * @vm: requested vm | |
979 | * @bo: amdgpu buffer object | |
980 | * | |
8843dbbb | 981 | * Add @bo into the requested vm. |
d38ceaf9 AD |
982 | * Add @bo to the list of bos associated with the vm |
983 | * Returns newly added bo_va or NULL for failure | |
984 | * | |
985 | * Object has to be reserved! | |
986 | */ | |
987 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
988 | struct amdgpu_vm *vm, | |
989 | struct amdgpu_bo *bo) | |
990 | { | |
991 | struct amdgpu_bo_va *bo_va; | |
992 | ||
993 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
994 | if (bo_va == NULL) { | |
995 | return NULL; | |
996 | } | |
997 | bo_va->vm = vm; | |
998 | bo_va->bo = bo; | |
d38ceaf9 AD |
999 | bo_va->ref_count = 1; |
1000 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1001 | INIT_LIST_HEAD(&bo_va->valids); |
1002 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1003 | INIT_LIST_HEAD(&bo_va->vm_status); |
69b576a1 | 1004 | mutex_init(&bo_va->mutex); |
d38ceaf9 | 1005 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1006 | |
1007 | return bo_va; | |
1008 | } | |
1009 | ||
1010 | /** | |
1011 | * amdgpu_vm_bo_map - map bo inside a vm | |
1012 | * | |
1013 | * @adev: amdgpu_device pointer | |
1014 | * @bo_va: bo_va to store the address | |
1015 | * @saddr: where to map the BO | |
1016 | * @offset: requested offset in the BO | |
1017 | * @flags: attributes of pages (read/write/valid/etc.) | |
1018 | * | |
1019 | * Add a mapping of the BO at the specefied addr into the VM. | |
1020 | * Returns 0 for success, error for failure. | |
1021 | * | |
49b02b18 | 1022 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1023 | */ |
1024 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1025 | struct amdgpu_bo_va *bo_va, | |
1026 | uint64_t saddr, uint64_t offset, | |
1027 | uint64_t size, uint32_t flags) | |
1028 | { | |
1029 | struct amdgpu_bo_va_mapping *mapping; | |
1030 | struct amdgpu_vm *vm = bo_va->vm; | |
1031 | struct interval_tree_node *it; | |
1032 | unsigned last_pfn, pt_idx; | |
1033 | uint64_t eaddr; | |
1034 | int r; | |
1035 | ||
0be52de9 CK |
1036 | /* validate the parameters */ |
1037 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1038 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1039 | return -EINVAL; |
0be52de9 | 1040 | |
d38ceaf9 | 1041 | /* make sure object fit at this offset */ |
005ae95e | 1042 | eaddr = saddr + size - 1; |
49b02b18 | 1043 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1044 | return -EINVAL; |
d38ceaf9 AD |
1045 | |
1046 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1047 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1048 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1049 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1050 | return -EINVAL; |
1051 | } | |
1052 | ||
d38ceaf9 AD |
1053 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1054 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1055 | ||
c25867df | 1056 | spin_lock(&vm->it_lock); |
005ae95e | 1057 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
c25867df | 1058 | spin_unlock(&vm->it_lock); |
d38ceaf9 AD |
1059 | if (it) { |
1060 | struct amdgpu_bo_va_mapping *tmp; | |
1061 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1062 | /* bo and tmp overlap, invalid addr */ | |
1063 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1064 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1065 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1066 | r = -EINVAL; |
f48b2659 | 1067 | goto error; |
d38ceaf9 AD |
1068 | } |
1069 | ||
1070 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1071 | if (!mapping) { | |
d38ceaf9 | 1072 | r = -ENOMEM; |
f48b2659 | 1073 | goto error; |
d38ceaf9 AD |
1074 | } |
1075 | ||
1076 | INIT_LIST_HEAD(&mapping->list); | |
1077 | mapping->it.start = saddr; | |
005ae95e | 1078 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1079 | mapping->offset = offset; |
1080 | mapping->flags = flags; | |
1081 | ||
69b576a1 | 1082 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1083 | list_add(&mapping->list, &bo_va->invalids); |
69b576a1 | 1084 | mutex_unlock(&bo_va->mutex); |
c25867df | 1085 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1086 | interval_tree_insert(&mapping->it, &vm->va); |
c25867df | 1087 | spin_unlock(&vm->it_lock); |
93e3e438 | 1088 | trace_amdgpu_vm_bo_map(bo_va, mapping); |
d38ceaf9 AD |
1089 | |
1090 | /* Make sure the page tables are allocated */ | |
1091 | saddr >>= amdgpu_vm_block_size; | |
1092 | eaddr >>= amdgpu_vm_block_size; | |
1093 | ||
1094 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1095 | ||
1096 | if (eaddr > vm->max_pde_used) | |
1097 | vm->max_pde_used = eaddr; | |
1098 | ||
d38ceaf9 AD |
1099 | /* walk over the address space and allocate the page tables */ |
1100 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1101 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1102 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1103 | struct amdgpu_bo *pt; |
1104 | ||
ee1782c3 CK |
1105 | entry = &vm->page_tables[pt_idx].entry; |
1106 | if (entry->robj) | |
d38ceaf9 AD |
1107 | continue; |
1108 | ||
d38ceaf9 AD |
1109 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1110 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1111 | AMDGPU_GEM_DOMAIN_VRAM, |
1112 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 | 1113 | NULL, resv, &pt); |
49b02b18 | 1114 | if (r) |
d38ceaf9 | 1115 | goto error_free; |
49b02b18 | 1116 | |
82b9c55b CK |
1117 | /* Keep a reference to the page table to avoid freeing |
1118 | * them up in the wrong order. | |
1119 | */ | |
1120 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1121 | ||
2bd9ccfa | 1122 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 AD |
1123 | if (r) { |
1124 | amdgpu_bo_unref(&pt); | |
1125 | goto error_free; | |
1126 | } | |
1127 | ||
ee1782c3 | 1128 | entry->robj = pt; |
ee1782c3 CK |
1129 | entry->priority = 0; |
1130 | entry->tv.bo = &entry->robj->tbo; | |
1131 | entry->tv.shared = true; | |
d38ceaf9 | 1132 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1133 | } |
1134 | ||
d38ceaf9 AD |
1135 | return 0; |
1136 | ||
1137 | error_free: | |
d38ceaf9 | 1138 | list_del(&mapping->list); |
c25867df | 1139 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1140 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1141 | spin_unlock(&vm->it_lock); |
93e3e438 | 1142 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1143 | kfree(mapping); |
1144 | ||
f48b2659 | 1145 | error: |
d38ceaf9 AD |
1146 | return r; |
1147 | } | |
1148 | ||
1149 | /** | |
1150 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1151 | * | |
1152 | * @adev: amdgpu_device pointer | |
1153 | * @bo_va: bo_va to remove the address from | |
1154 | * @saddr: where to the BO is mapped | |
1155 | * | |
1156 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1157 | * Returns 0 for success, error for failure. | |
1158 | * | |
49b02b18 | 1159 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1160 | */ |
1161 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1162 | struct amdgpu_bo_va *bo_va, | |
1163 | uint64_t saddr) | |
1164 | { | |
1165 | struct amdgpu_bo_va_mapping *mapping; | |
1166 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1167 | bool valid = true; |
d38ceaf9 | 1168 | |
6c7fc503 | 1169 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
69b576a1 | 1170 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1171 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1172 | if (mapping->it.start == saddr) |
1173 | break; | |
1174 | } | |
1175 | ||
7fc11959 CK |
1176 | if (&mapping->list == &bo_va->valids) { |
1177 | valid = false; | |
1178 | ||
1179 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1180 | if (mapping->it.start == saddr) | |
1181 | break; | |
1182 | } | |
1183 | ||
69b576a1 CZ |
1184 | if (&mapping->list == &bo_va->invalids) { |
1185 | mutex_unlock(&bo_va->mutex); | |
7fc11959 | 1186 | return -ENOENT; |
69b576a1 | 1187 | } |
d38ceaf9 | 1188 | } |
69b576a1 | 1189 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 | 1190 | list_del(&mapping->list); |
c25867df | 1191 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1192 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1193 | spin_unlock(&vm->it_lock); |
93e3e438 | 1194 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1195 | |
81d75a30 | 1196 | if (valid) { |
1197 | spin_lock(&vm->freed_lock); | |
d38ceaf9 | 1198 | list_add(&mapping->list, &vm->freed); |
81d75a30 | 1199 | spin_unlock(&vm->freed_lock); |
1200 | } else { | |
d38ceaf9 | 1201 | kfree(mapping); |
81d75a30 | 1202 | } |
d38ceaf9 AD |
1203 | |
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | /** | |
1208 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1209 | * | |
1210 | * @adev: amdgpu_device pointer | |
1211 | * @bo_va: requested bo_va | |
1212 | * | |
8843dbbb | 1213 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1214 | * |
1215 | * Object have to be reserved! | |
1216 | */ | |
1217 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1218 | struct amdgpu_bo_va *bo_va) | |
1219 | { | |
1220 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1221 | struct amdgpu_vm *vm = bo_va->vm; | |
1222 | ||
1223 | list_del(&bo_va->bo_list); | |
1224 | ||
d38ceaf9 AD |
1225 | spin_lock(&vm->status_lock); |
1226 | list_del(&bo_va->vm_status); | |
1227 | spin_unlock(&vm->status_lock); | |
1228 | ||
7fc11959 | 1229 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 1230 | list_del(&mapping->list); |
c25867df | 1231 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1232 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1233 | spin_unlock(&vm->it_lock); |
93e3e438 | 1234 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
81d75a30 | 1235 | spin_lock(&vm->freed_lock); |
7fc11959 | 1236 | list_add(&mapping->list, &vm->freed); |
81d75a30 | 1237 | spin_unlock(&vm->freed_lock); |
7fc11959 CK |
1238 | } |
1239 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1240 | list_del(&mapping->list); | |
c25867df | 1241 | spin_lock(&vm->it_lock); |
7fc11959 | 1242 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1243 | spin_unlock(&vm->it_lock); |
7fc11959 | 1244 | kfree(mapping); |
d38ceaf9 | 1245 | } |
bb1e38a4 | 1246 | fence_put(bo_va->last_pt_update); |
69b576a1 | 1247 | mutex_destroy(&bo_va->mutex); |
d38ceaf9 | 1248 | kfree(bo_va); |
d38ceaf9 AD |
1249 | } |
1250 | ||
1251 | /** | |
1252 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1253 | * | |
1254 | * @adev: amdgpu_device pointer | |
1255 | * @vm: requested vm | |
1256 | * @bo: amdgpu buffer object | |
1257 | * | |
8843dbbb | 1258 | * Mark @bo as invalid. |
d38ceaf9 AD |
1259 | */ |
1260 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1261 | struct amdgpu_bo *bo) | |
1262 | { | |
1263 | struct amdgpu_bo_va *bo_va; | |
1264 | ||
1265 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1266 | spin_lock(&bo_va->vm->status_lock); |
1267 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1268 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1269 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1270 | } |
1271 | } | |
1272 | ||
1273 | /** | |
1274 | * amdgpu_vm_init - initialize a vm instance | |
1275 | * | |
1276 | * @adev: amdgpu_device pointer | |
1277 | * @vm: requested vm | |
1278 | * | |
8843dbbb | 1279 | * Init @vm fields. |
d38ceaf9 AD |
1280 | */ |
1281 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1282 | { | |
1283 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1284 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1285 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1286 | unsigned ring_instance; |
1287 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1288 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1289 | int i, r; |
1290 | ||
1291 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4ff37a83 | 1292 | vm->ids[i].mgr_id = NULL; |
d38ceaf9 | 1293 | vm->ids[i].flushed_updates = NULL; |
d38ceaf9 | 1294 | } |
d38ceaf9 AD |
1295 | vm->va = RB_ROOT; |
1296 | spin_lock_init(&vm->status_lock); | |
1297 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1298 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1299 | INIT_LIST_HEAD(&vm->freed); |
c25867df | 1300 | spin_lock_init(&vm->it_lock); |
81d75a30 | 1301 | spin_lock_init(&vm->freed_lock); |
d38ceaf9 AD |
1302 | pd_size = amdgpu_vm_directory_size(adev); |
1303 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1304 | ||
1305 | /* allocate page table array */ | |
9571e1d8 | 1306 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1307 | if (vm->page_tables == NULL) { |
1308 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1309 | return -ENOMEM; | |
1310 | } | |
1311 | ||
2bd9ccfa | 1312 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1313 | |
1314 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1315 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1316 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1317 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1318 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1319 | rq, amdgpu_sched_jobs); | |
1320 | if (r) | |
1321 | return r; | |
1322 | ||
05906dec BN |
1323 | vm->page_directory_fence = NULL; |
1324 | ||
d38ceaf9 | 1325 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1326 | AMDGPU_GEM_DOMAIN_VRAM, |
1327 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1328 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1329 | if (r) |
2bd9ccfa CK |
1330 | goto error_free_sched_entity; |
1331 | ||
ef9f0a83 | 1332 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1333 | if (r) |
1334 | goto error_free_page_directory; | |
1335 | ||
1336 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
ef9f0a83 | 1337 | amdgpu_bo_unreserve(vm->page_directory); |
2bd9ccfa CK |
1338 | if (r) |
1339 | goto error_free_page_directory; | |
d38ceaf9 AD |
1340 | |
1341 | return 0; | |
2bd9ccfa CK |
1342 | |
1343 | error_free_page_directory: | |
1344 | amdgpu_bo_unref(&vm->page_directory); | |
1345 | vm->page_directory = NULL; | |
1346 | ||
1347 | error_free_sched_entity: | |
1348 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1349 | ||
1350 | return r; | |
d38ceaf9 AD |
1351 | } |
1352 | ||
1353 | /** | |
1354 | * amdgpu_vm_fini - tear down a vm instance | |
1355 | * | |
1356 | * @adev: amdgpu_device pointer | |
1357 | * @vm: requested vm | |
1358 | * | |
8843dbbb | 1359 | * Tear down @vm. |
d38ceaf9 AD |
1360 | * Unbind the VM and remove all bos from the vm bo list |
1361 | */ | |
1362 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1363 | { | |
1364 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1365 | int i; | |
1366 | ||
2d55e45a | 1367 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1368 | |
d38ceaf9 AD |
1369 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1370 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1371 | } | |
1372 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1373 | list_del(&mapping->list); | |
1374 | interval_tree_remove(&mapping->it, &vm->va); | |
1375 | kfree(mapping); | |
1376 | } | |
1377 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1378 | list_del(&mapping->list); | |
1379 | kfree(mapping); | |
1380 | } | |
1381 | ||
1382 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
ee1782c3 | 1383 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
9571e1d8 | 1384 | drm_free_large(vm->page_tables); |
d38ceaf9 AD |
1385 | |
1386 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1387 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1388 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4ff37a83 | 1389 | struct amdgpu_vm_id *id = &vm->ids[i]; |
1c16c0a7 | 1390 | |
4ff37a83 CK |
1391 | if (id->mgr_id) |
1392 | atomic_long_cmpxchg(&id->mgr_id->owner, | |
1393 | (long)id, 0); | |
1394 | fence_put(id->flushed_updates); | |
d38ceaf9 | 1395 | } |
d38ceaf9 | 1396 | } |
ea89f8c9 | 1397 | |
a9a78b32 CK |
1398 | /** |
1399 | * amdgpu_vm_manager_init - init the VM manager | |
1400 | * | |
1401 | * @adev: amdgpu_device pointer | |
1402 | * | |
1403 | * Initialize the VM manager structures | |
1404 | */ | |
1405 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1406 | { | |
1407 | unsigned i; | |
1408 | ||
1409 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1410 | ||
1411 | /* skip over VMID 0, since it is the system VM */ | |
1412 | for (i = 1; i < adev->vm_manager.num_ids; ++i) | |
1413 | list_add_tail(&adev->vm_manager.ids[i].list, | |
1414 | &adev->vm_manager.ids_lru); | |
2d55e45a CK |
1415 | |
1416 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); | |
a9a78b32 CK |
1417 | } |
1418 | ||
ea89f8c9 CK |
1419 | /** |
1420 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1421 | * | |
1422 | * @adev: amdgpu_device pointer | |
1423 | * | |
1424 | * Cleanup the VM manager and free resources. | |
1425 | */ | |
1426 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1427 | { | |
1428 | unsigned i; | |
1429 | ||
1430 | for (i = 0; i < AMDGPU_NUM_VM; ++i) | |
1c16c0a7 | 1431 | fence_put(adev->vm_manager.ids[i].active); |
ea89f8c9 | 1432 | } |