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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
02208441 | 30 | #include <linux/idr.h> |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "amdgpu_trace.h" | |
35 | ||
02208441 FK |
36 | /* |
37 | * PASID manager | |
38 | * | |
39 | * PASIDs are global address space identifiers that can be shared | |
40 | * between the GPU, an IOMMU and the driver. VMs on different devices | |
41 | * may use the same PASID if they share the same address | |
42 | * space. Therefore PASIDs are allocated using a global IDA. VMs are | |
43 | * looked up from the PASID per amdgpu_device. | |
44 | */ | |
45 | static DEFINE_IDA(amdgpu_vm_pasid_ida); | |
46 | ||
47 | /** | |
48 | * amdgpu_vm_alloc_pasid - Allocate a PASID | |
49 | * @bits: Maximum width of the PASID in bits, must be at least 1 | |
50 | * | |
51 | * Allocates a PASID of the given width while keeping smaller PASIDs | |
52 | * available if possible. | |
53 | * | |
54 | * Returns a positive integer on success. Returns %-EINVAL if bits==0. | |
55 | * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on | |
56 | * memory allocation failure. | |
57 | */ | |
58 | int amdgpu_vm_alloc_pasid(unsigned int bits) | |
59 | { | |
60 | int pasid = -EINVAL; | |
61 | ||
62 | for (bits = min(bits, 31U); bits > 0; bits--) { | |
63 | pasid = ida_simple_get(&amdgpu_vm_pasid_ida, | |
64 | 1U << (bits - 1), 1U << bits, | |
65 | GFP_KERNEL); | |
66 | if (pasid != -ENOSPC) | |
67 | break; | |
68 | } | |
69 | ||
70 | return pasid; | |
71 | } | |
72 | ||
73 | /** | |
74 | * amdgpu_vm_free_pasid - Free a PASID | |
75 | * @pasid: PASID to free | |
76 | */ | |
77 | void amdgpu_vm_free_pasid(unsigned int pasid) | |
78 | { | |
79 | ida_simple_remove(&amdgpu_vm_pasid_ida, pasid); | |
80 | } | |
81 | ||
d38ceaf9 AD |
82 | /* |
83 | * GPUVM | |
84 | * GPUVM is similar to the legacy gart on older asics, however | |
85 | * rather than there being a single global gart table | |
86 | * for the entire GPU, there are multiple VM page tables active | |
87 | * at any given time. The VM page tables can contain a mix | |
88 | * vram pages and system memory pages and system memory pages | |
89 | * can be mapped as snooped (cached system pages) or unsnooped | |
90 | * (uncached system pages). | |
91 | * Each VM has an ID associated with it and there is a page table | |
92 | * associated with each VMID. When execting a command buffer, | |
93 | * the kernel tells the the ring what VMID to use for that command | |
94 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
95 | * The userspace drivers maintain their own address space and the kernel | |
96 | * sets up their pages tables accordingly when they submit their | |
97 | * command buffers and a VMID is assigned. | |
98 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
99 | * SI supports 16. | |
100 | */ | |
101 | ||
a9f87f64 CK |
102 | #define START(node) ((node)->start) |
103 | #define LAST(node) ((node)->last) | |
104 | ||
105 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
106 | START, LAST, static, amdgpu_vm_it) | |
107 | ||
108 | #undef START | |
109 | #undef LAST | |
110 | ||
f4833c4f HK |
111 | /* Local structure. Encapsulate some VM table update parameters to reduce |
112 | * the number of function parameters | |
113 | */ | |
29efc4f5 | 114 | struct amdgpu_pte_update_params { |
27c5f36f CK |
115 | /* amdgpu device we do this update for */ |
116 | struct amdgpu_device *adev; | |
49ac8a24 CK |
117 | /* optional amdgpu_vm we do this update for */ |
118 | struct amdgpu_vm *vm; | |
f4833c4f HK |
119 | /* address where to copy page table entries from */ |
120 | uint64_t src; | |
f4833c4f HK |
121 | /* indirect buffer to fill with commands */ |
122 | struct amdgpu_ib *ib; | |
afef8b8f CK |
123 | /* Function which actually does the update */ |
124 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
125 | uint64_t addr, unsigned count, uint32_t incr, | |
6b777607 | 126 | uint64_t flags); |
b4d42511 HK |
127 | /* The next two are used during VM update by CPU |
128 | * DMA addresses to use for mapping | |
129 | * Kernel pointer of PD/PT BO that needs to be updated | |
130 | */ | |
131 | dma_addr_t *pages_addr; | |
132 | void *kptr; | |
f4833c4f HK |
133 | }; |
134 | ||
284710fa CK |
135 | /* Helper to disable partial resident texture feature from a fence callback */ |
136 | struct amdgpu_prt_cb { | |
137 | struct amdgpu_device *adev; | |
138 | struct dma_fence_cb cb; | |
139 | }; | |
140 | ||
50783147 CK |
141 | /** |
142 | * amdgpu_vm_level_shift - return the addr shift for each level | |
143 | * | |
144 | * @adev: amdgpu_device pointer | |
145 | * | |
146 | * Returns the number of bits the pfn needs to be right shifted for a level. | |
147 | */ | |
148 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
149 | unsigned level) | |
150 | { | |
151 | if (level != adev->vm_manager.num_level) | |
152 | return 9 * (adev->vm_manager.num_level - level - 1) + | |
153 | adev->vm_manager.block_size; | |
154 | else | |
155 | /* For the page tables on the leaves */ | |
156 | return 0; | |
157 | } | |
158 | ||
d38ceaf9 | 159 | /** |
72a7ec5c | 160 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
161 | * |
162 | * @adev: amdgpu_device pointer | |
163 | * | |
72a7ec5c | 164 | * Calculate the number of entries in a page directory or page table. |
d38ceaf9 | 165 | */ |
72a7ec5c CK |
166 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
167 | unsigned level) | |
d38ceaf9 | 168 | { |
72a7ec5c CK |
169 | if (level == 0) |
170 | /* For the root directory */ | |
171 | return adev->vm_manager.max_pfn >> | |
36b32a68 ZJ |
172 | (adev->vm_manager.block_size * |
173 | adev->vm_manager.num_level); | |
72a7ec5c CK |
174 | else if (level == adev->vm_manager.num_level) |
175 | /* For the page tables on the leaves */ | |
36b32a68 | 176 | return AMDGPU_VM_PTE_COUNT(adev); |
72a7ec5c CK |
177 | else |
178 | /* Everything in between */ | |
36b32a68 | 179 | return 1 << adev->vm_manager.block_size; |
d38ceaf9 AD |
180 | } |
181 | ||
182 | /** | |
72a7ec5c | 183 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
184 | * |
185 | * @adev: amdgpu_device pointer | |
186 | * | |
72a7ec5c | 187 | * Calculate the size of the BO for a page directory or page table in bytes. |
d38ceaf9 | 188 | */ |
72a7ec5c | 189 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 190 | { |
72a7ec5c | 191 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
192 | } |
193 | ||
194 | /** | |
56467ebf | 195 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
196 | * |
197 | * @vm: vm providing the BOs | |
3c0eea6c | 198 | * @validated: head of validation list |
56467ebf | 199 | * @entry: entry to add |
d38ceaf9 AD |
200 | * |
201 | * Add the page directory to the list of BOs to | |
56467ebf | 202 | * validate for command submission. |
d38ceaf9 | 203 | */ |
56467ebf CK |
204 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
205 | struct list_head *validated, | |
206 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 207 | { |
3f3333f8 | 208 | entry->robj = vm->root.base.bo; |
56467ebf | 209 | entry->priority = 0; |
67003a15 | 210 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 211 | entry->tv.shared = true; |
2f568dbd | 212 | entry->user_pages = NULL; |
56467ebf CK |
213 | list_add(&entry->tv.head, validated); |
214 | } | |
d38ceaf9 | 215 | |
670fecc8 | 216 | /** |
f7da30d9 | 217 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
670fecc8 | 218 | * |
5a712a87 | 219 | * @adev: amdgpu device pointer |
56467ebf | 220 | * @vm: vm providing the BOs |
670fecc8 CK |
221 | * @validate: callback to do the validation |
222 | * @param: parameter for the validation callback | |
223 | * | |
224 | * Validate the page table BOs on command submission if neccessary. | |
225 | */ | |
f7da30d9 CK |
226 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
227 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
228 | void *param) | |
670fecc8 | 229 | { |
3f3333f8 | 230 | struct ttm_bo_global *glob = adev->mman.bdev.glob; |
670fecc8 CK |
231 | int r; |
232 | ||
3f3333f8 CK |
233 | spin_lock(&vm->status_lock); |
234 | while (!list_empty(&vm->evicted)) { | |
235 | struct amdgpu_vm_bo_base *bo_base; | |
236 | struct amdgpu_bo *bo; | |
670fecc8 | 237 | |
3f3333f8 CK |
238 | bo_base = list_first_entry(&vm->evicted, |
239 | struct amdgpu_vm_bo_base, | |
240 | vm_status); | |
241 | spin_unlock(&vm->status_lock); | |
670fecc8 | 242 | |
3f3333f8 CK |
243 | bo = bo_base->bo; |
244 | BUG_ON(!bo); | |
245 | if (bo->parent) { | |
246 | r = validate(param, bo); | |
247 | if (r) | |
248 | return r; | |
670fecc8 | 249 | |
3f3333f8 CK |
250 | spin_lock(&glob->lru_lock); |
251 | ttm_bo_move_to_lru_tail(&bo->tbo); | |
252 | if (bo->shadow) | |
253 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo); | |
254 | spin_unlock(&glob->lru_lock); | |
255 | } | |
670fecc8 | 256 | |
73fb16e7 CK |
257 | if (bo->tbo.type == ttm_bo_type_kernel && |
258 | vm->use_cpu_for_update) { | |
3f3333f8 CK |
259 | r = amdgpu_bo_kmap(bo, NULL); |
260 | if (r) | |
261 | return r; | |
262 | } | |
b6369225 | 263 | |
3f3333f8 | 264 | spin_lock(&vm->status_lock); |
73fb16e7 CK |
265 | if (bo->tbo.type != ttm_bo_type_kernel) |
266 | list_move(&bo_base->vm_status, &vm->moved); | |
267 | else | |
268 | list_move(&bo_base->vm_status, &vm->relocated); | |
670fecc8 | 269 | } |
3f3333f8 | 270 | spin_unlock(&vm->status_lock); |
670fecc8 | 271 | |
34d7be5d | 272 | return 0; |
670fecc8 CK |
273 | } |
274 | ||
56467ebf | 275 | /** |
34d7be5d | 276 | * amdgpu_vm_ready - check VM is ready for updates |
56467ebf | 277 | * |
34d7be5d | 278 | * @vm: VM to check |
d38ceaf9 | 279 | * |
34d7be5d | 280 | * Check if all VM PDs/PTs are ready for updates |
d38ceaf9 | 281 | */ |
3f3333f8 | 282 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
d38ceaf9 | 283 | { |
3f3333f8 | 284 | bool ready; |
d38ceaf9 | 285 | |
3f3333f8 CK |
286 | spin_lock(&vm->status_lock); |
287 | ready = list_empty(&vm->evicted); | |
288 | spin_unlock(&vm->status_lock); | |
5a712a87 | 289 | |
3f3333f8 | 290 | return ready; |
d711e139 CK |
291 | } |
292 | ||
293 | /** | |
f566ceb1 CK |
294 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels |
295 | * | |
296 | * @adev: amdgpu_device pointer | |
297 | * @vm: requested vm | |
298 | * @saddr: start of the address range | |
299 | * @eaddr: end of the address range | |
300 | * | |
301 | * Make sure the page directories and page tables are allocated | |
302 | */ | |
303 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
304 | struct amdgpu_vm *vm, | |
305 | struct amdgpu_vm_pt *parent, | |
306 | uint64_t saddr, uint64_t eaddr, | |
307 | unsigned level) | |
308 | { | |
50783147 | 309 | unsigned shift = amdgpu_vm_level_shift(adev, level); |
f566ceb1 CK |
310 | unsigned pt_idx, from, to; |
311 | int r; | |
3c824172 | 312 | u64 flags; |
51ac7eec | 313 | uint64_t init_value = 0; |
f566ceb1 CK |
314 | |
315 | if (!parent->entries) { | |
316 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
317 | ||
2098105e MH |
318 | parent->entries = kvmalloc_array(num_entries, |
319 | sizeof(struct amdgpu_vm_pt), | |
320 | GFP_KERNEL | __GFP_ZERO); | |
f566ceb1 CK |
321 | if (!parent->entries) |
322 | return -ENOMEM; | |
323 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
324 | } | |
325 | ||
1866bac8 FK |
326 | from = saddr >> shift; |
327 | to = eaddr >> shift; | |
328 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
329 | to >= amdgpu_vm_num_entries(adev, level)) | |
330 | return -EINVAL; | |
f566ceb1 CK |
331 | |
332 | if (to > parent->last_entry_used) | |
333 | parent->last_entry_used = to; | |
334 | ||
335 | ++level; | |
1866bac8 FK |
336 | saddr = saddr & ((1 << shift) - 1); |
337 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 | 338 | |
3c824172 HK |
339 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
340 | AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
341 | if (vm->use_cpu_for_update) | |
342 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
343 | else | |
344 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
345 | AMDGPU_GEM_CREATE_SHADOW); | |
346 | ||
51ac7eec | 347 | if (vm->pte_support_ats) { |
6d16dac8 | 348 | init_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec YZ |
349 | if (level != adev->vm_manager.num_level - 1) |
350 | init_value |= AMDGPU_PDE_PTE; | |
6d16dac8 | 351 | |
51ac7eec YZ |
352 | } |
353 | ||
f566ceb1 CK |
354 | /* walk over the address space and allocate the page tables */ |
355 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
3f3333f8 | 356 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
f566ceb1 CK |
357 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
358 | struct amdgpu_bo *pt; | |
359 | ||
3f3333f8 | 360 | if (!entry->base.bo) { |
f566ceb1 CK |
361 | r = amdgpu_bo_create(adev, |
362 | amdgpu_vm_bo_size(adev, level), | |
363 | AMDGPU_GPU_PAGE_SIZE, true, | |
364 | AMDGPU_GEM_DOMAIN_VRAM, | |
3c824172 | 365 | flags, |
51ac7eec | 366 | NULL, resv, init_value, &pt); |
f566ceb1 CK |
367 | if (r) |
368 | return r; | |
369 | ||
0a096fb6 CK |
370 | if (vm->use_cpu_for_update) { |
371 | r = amdgpu_bo_kmap(pt, NULL); | |
372 | if (r) { | |
373 | amdgpu_bo_unref(&pt); | |
374 | return r; | |
375 | } | |
376 | } | |
377 | ||
f566ceb1 CK |
378 | /* Keep a reference to the root directory to avoid |
379 | * freeing them up in the wrong order. | |
380 | */ | |
0f2fc435 | 381 | pt->parent = amdgpu_bo_ref(parent->base.bo); |
f566ceb1 | 382 | |
3f3333f8 CK |
383 | entry->base.vm = vm; |
384 | entry->base.bo = pt; | |
385 | list_add_tail(&entry->base.bo_list, &pt->va); | |
ea09729c CK |
386 | spin_lock(&vm->status_lock); |
387 | list_add(&entry->base.vm_status, &vm->relocated); | |
388 | spin_unlock(&vm->status_lock); | |
f566ceb1 CK |
389 | entry->addr = 0; |
390 | } | |
391 | ||
392 | if (level < adev->vm_manager.num_level) { | |
1866bac8 FK |
393 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
394 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
395 | ((1 << shift) - 1); | |
396 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
397 | sub_eaddr, level); | |
f566ceb1 CK |
398 | if (r) |
399 | return r; | |
400 | } | |
401 | } | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
663e4577 CK |
406 | /** |
407 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
408 | * | |
409 | * @adev: amdgpu_device pointer | |
410 | * @vm: VM to allocate page tables for | |
411 | * @saddr: Start address which needs to be allocated | |
412 | * @size: Size from start address we need. | |
413 | * | |
414 | * Make sure the page tables are allocated. | |
415 | */ | |
416 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
417 | struct amdgpu_vm *vm, | |
418 | uint64_t saddr, uint64_t size) | |
419 | { | |
22770e5a | 420 | uint64_t last_pfn; |
663e4577 | 421 | uint64_t eaddr; |
663e4577 CK |
422 | |
423 | /* validate the parameters */ | |
424 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
425 | return -EINVAL; | |
426 | ||
427 | eaddr = saddr + size - 1; | |
428 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
429 | if (last_pfn >= adev->vm_manager.max_pfn) { | |
22770e5a | 430 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", |
663e4577 CK |
431 | last_pfn, adev->vm_manager.max_pfn); |
432 | return -EINVAL; | |
433 | } | |
434 | ||
435 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
436 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
437 | ||
f566ceb1 | 438 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); |
663e4577 CK |
439 | } |
440 | ||
641e9400 CK |
441 | /** |
442 | * amdgpu_vm_had_gpu_reset - check if reset occured since last use | |
443 | * | |
444 | * @adev: amdgpu_device pointer | |
445 | * @id: VMID structure | |
446 | * | |
447 | * Check if GPU reset occured since last use of the VMID. | |
448 | */ | |
449 | static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev, | |
450 | struct amdgpu_vm_id *id) | |
192b7dcb CZ |
451 | { |
452 | return id->current_gpu_reset_count != | |
641e9400 | 453 | atomic_read(&adev->gpu_reset_counter); |
192b7dcb CZ |
454 | } |
455 | ||
7a63eb23 CZ |
456 | static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub) |
457 | { | |
458 | return !!vm->reserved_vmid[vmhub]; | |
459 | } | |
460 | ||
461 | /* idr_mgr->lock must be held */ | |
462 | static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, | |
463 | struct amdgpu_ring *ring, | |
464 | struct amdgpu_sync *sync, | |
465 | struct dma_fence *fence, | |
466 | struct amdgpu_job *job) | |
467 | { | |
468 | struct amdgpu_device *adev = ring->adev; | |
469 | unsigned vmhub = ring->funcs->vmhub; | |
470 | uint64_t fence_context = adev->fence_context + ring->idx; | |
471 | struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub]; | |
472 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
473 | struct dma_fence *updates = sync->last_vm_update; | |
474 | int r = 0; | |
475 | struct dma_fence *flushed, *tmp; | |
6f1ceabb | 476 | bool needs_flush = vm->use_cpu_for_update; |
7a63eb23 CZ |
477 | |
478 | flushed = id->flushed_updates; | |
479 | if ((amdgpu_vm_had_gpu_reset(adev, id)) || | |
480 | (atomic64_read(&id->owner) != vm->client_id) || | |
481 | (job->vm_pd_addr != id->pd_gpu_addr) || | |
482 | (updates && (!flushed || updates->context != flushed->context || | |
483 | dma_fence_is_later(updates, flushed))) || | |
484 | (!id->last_flush || (id->last_flush->context != fence_context && | |
485 | !dma_fence_is_signaled(id->last_flush)))) { | |
486 | needs_flush = true; | |
487 | /* to prevent one context starved by another context */ | |
488 | id->pd_gpu_addr = 0; | |
489 | tmp = amdgpu_sync_peek_fence(&id->active, ring); | |
490 | if (tmp) { | |
491 | r = amdgpu_sync_fence(adev, sync, tmp); | |
492 | return r; | |
493 | } | |
494 | } | |
495 | ||
496 | /* Good we can use this VMID. Remember this submission as | |
497 | * user of the VMID. | |
498 | */ | |
499 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
500 | if (r) | |
501 | goto out; | |
502 | ||
503 | if (updates && (!flushed || updates->context != flushed->context || | |
504 | dma_fence_is_later(updates, flushed))) { | |
505 | dma_fence_put(id->flushed_updates); | |
506 | id->flushed_updates = dma_fence_get(updates); | |
507 | } | |
508 | id->pd_gpu_addr = job->vm_pd_addr; | |
7a63eb23 CZ |
509 | atomic64_set(&id->owner, vm->client_id); |
510 | job->vm_needs_flush = needs_flush; | |
511 | if (needs_flush) { | |
512 | dma_fence_put(id->last_flush); | |
513 | id->last_flush = NULL; | |
514 | } | |
515 | job->vm_id = id - id_mgr->ids; | |
516 | trace_amdgpu_vm_grab_id(vm, ring, job); | |
517 | out: | |
518 | return r; | |
519 | } | |
520 | ||
d38ceaf9 AD |
521 | /** |
522 | * amdgpu_vm_grab_id - allocate the next free VMID | |
523 | * | |
d38ceaf9 | 524 | * @vm: vm to allocate id for |
7f8a5290 CK |
525 | * @ring: ring we want to submit job to |
526 | * @sync: sync object where we add dependencies | |
94dd0a4a | 527 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 528 | * |
7f8a5290 | 529 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 530 | */ |
7f8a5290 | 531 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
f54d1867 | 532 | struct amdgpu_sync *sync, struct dma_fence *fence, |
fd53be30 | 533 | struct amdgpu_job *job) |
d38ceaf9 | 534 | { |
d38ceaf9 | 535 | struct amdgpu_device *adev = ring->adev; |
2e819849 | 536 | unsigned vmhub = ring->funcs->vmhub; |
7645670d | 537 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
090b767e | 538 | uint64_t fence_context = adev->fence_context + ring->idx; |
f54d1867 | 539 | struct dma_fence *updates = sync->last_vm_update; |
8d76001e | 540 | struct amdgpu_vm_id *id, *idle; |
f54d1867 | 541 | struct dma_fence **fences; |
1fbb2e92 CK |
542 | unsigned i; |
543 | int r = 0; | |
544 | ||
7a63eb23 CZ |
545 | mutex_lock(&id_mgr->lock); |
546 | if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) { | |
547 | r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job); | |
548 | mutex_unlock(&id_mgr->lock); | |
549 | return r; | |
550 | } | |
7645670d | 551 | fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); |
7a63eb23 CZ |
552 | if (!fences) { |
553 | mutex_unlock(&id_mgr->lock); | |
1fbb2e92 | 554 | return -ENOMEM; |
7a63eb23 | 555 | } |
36fd7c5c | 556 | /* Check if we have an idle VMID */ |
1fbb2e92 | 557 | i = 0; |
7645670d | 558 | list_for_each_entry(idle, &id_mgr->ids_lru, list) { |
1fbb2e92 CK |
559 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
560 | if (!fences[i]) | |
36fd7c5c | 561 | break; |
1fbb2e92 | 562 | ++i; |
36fd7c5c CK |
563 | } |
564 | ||
1fbb2e92 | 565 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
7645670d | 566 | if (&idle->list == &id_mgr->ids_lru) { |
1fbb2e92 CK |
567 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
568 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
f54d1867 | 569 | struct dma_fence_array *array; |
1fbb2e92 CK |
570 | unsigned j; |
571 | ||
572 | for (j = 0; j < i; ++j) | |
f54d1867 | 573 | dma_fence_get(fences[j]); |
1fbb2e92 | 574 | |
f54d1867 | 575 | array = dma_fence_array_create(i, fences, fence_context, |
1fbb2e92 CK |
576 | seqno, true); |
577 | if (!array) { | |
578 | for (j = 0; j < i; ++j) | |
f54d1867 | 579 | dma_fence_put(fences[j]); |
1fbb2e92 CK |
580 | kfree(fences); |
581 | r = -ENOMEM; | |
582 | goto error; | |
583 | } | |
584 | ||
585 | ||
586 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
f54d1867 | 587 | dma_fence_put(&array->base); |
1fbb2e92 CK |
588 | if (r) |
589 | goto error; | |
590 | ||
7645670d | 591 | mutex_unlock(&id_mgr->lock); |
1fbb2e92 CK |
592 | return 0; |
593 | ||
594 | } | |
595 | kfree(fences); | |
596 | ||
6f1ceabb | 597 | job->vm_needs_flush = vm->use_cpu_for_update; |
1fbb2e92 | 598 | /* Check if we can use a VMID already assigned to this VM */ |
7645670d | 599 | list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) { |
f54d1867 | 600 | struct dma_fence *flushed; |
6f1ceabb | 601 | bool needs_flush = vm->use_cpu_for_update; |
1fbb2e92 | 602 | |
1fbb2e92 | 603 | /* Check all the prerequisites to using this VMID */ |
641e9400 | 604 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
6adb0513 | 605 | continue; |
1fbb2e92 CK |
606 | |
607 | if (atomic64_read(&id->owner) != vm->client_id) | |
608 | continue; | |
609 | ||
fd53be30 | 610 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
611 | continue; |
612 | ||
87c910d8 CK |
613 | if (!id->last_flush || |
614 | (id->last_flush->context != fence_context && | |
615 | !dma_fence_is_signaled(id->last_flush))) | |
616 | needs_flush = true; | |
1fbb2e92 CK |
617 | |
618 | flushed = id->flushed_updates; | |
87c910d8 CK |
619 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) |
620 | needs_flush = true; | |
621 | ||
622 | /* Concurrent flushes are only possible starting with Vega10 */ | |
623 | if (adev->asic_type < CHIP_VEGA10 && needs_flush) | |
1fbb2e92 CK |
624 | continue; |
625 | ||
3dab83be CK |
626 | /* Good we can use this VMID. Remember this submission as |
627 | * user of the VMID. | |
628 | */ | |
1fbb2e92 CK |
629 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
630 | if (r) | |
631 | goto error; | |
8d76001e | 632 | |
87c910d8 CK |
633 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) { |
634 | dma_fence_put(id->flushed_updates); | |
635 | id->flushed_updates = dma_fence_get(updates); | |
636 | } | |
8d76001e | 637 | |
87c910d8 CK |
638 | if (needs_flush) |
639 | goto needs_flush; | |
640 | else | |
641 | goto no_flush_needed; | |
8d76001e | 642 | |
4f618e73 | 643 | }; |
8d76001e | 644 | |
1fbb2e92 CK |
645 | /* Still no ID to use? Then use the idle one found earlier */ |
646 | id = idle; | |
8e9fbeb5 | 647 | |
1fbb2e92 CK |
648 | /* Remember this submission as user of the VMID */ |
649 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
650 | if (r) |
651 | goto error; | |
94dd0a4a | 652 | |
87c910d8 | 653 | id->pd_gpu_addr = job->vm_pd_addr; |
f54d1867 CW |
654 | dma_fence_put(id->flushed_updates); |
655 | id->flushed_updates = dma_fence_get(updates); | |
0ea54b9b | 656 | atomic64_set(&id->owner, vm->client_id); |
d38ceaf9 | 657 | |
87c910d8 CK |
658 | needs_flush: |
659 | job->vm_needs_flush = true; | |
660 | dma_fence_put(id->last_flush); | |
661 | id->last_flush = NULL; | |
662 | ||
663 | no_flush_needed: | |
664 | list_move_tail(&id->list, &id_mgr->ids_lru); | |
665 | ||
7645670d | 666 | job->vm_id = id - id_mgr->ids; |
c5296d14 | 667 | trace_amdgpu_vm_grab_id(vm, ring, job); |
832a902f CK |
668 | |
669 | error: | |
7645670d | 670 | mutex_unlock(&id_mgr->lock); |
a9a78b32 | 671 | return r; |
d38ceaf9 AD |
672 | } |
673 | ||
1e9ef26f CZ |
674 | static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev, |
675 | struct amdgpu_vm *vm, | |
676 | unsigned vmhub) | |
677 | { | |
678 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
679 | ||
680 | mutex_lock(&id_mgr->lock); | |
681 | if (vm->reserved_vmid[vmhub]) { | |
682 | list_add(&vm->reserved_vmid[vmhub]->list, | |
683 | &id_mgr->ids_lru); | |
684 | vm->reserved_vmid[vmhub] = NULL; | |
c3505770 | 685 | atomic_dec(&id_mgr->reserved_vmid_num); |
1e9ef26f CZ |
686 | } |
687 | mutex_unlock(&id_mgr->lock); | |
688 | } | |
689 | ||
690 | static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev, | |
691 | struct amdgpu_vm *vm, | |
692 | unsigned vmhub) | |
693 | { | |
694 | struct amdgpu_vm_id_manager *id_mgr; | |
695 | struct amdgpu_vm_id *idle; | |
696 | int r = 0; | |
697 | ||
698 | id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
699 | mutex_lock(&id_mgr->lock); | |
700 | if (vm->reserved_vmid[vmhub]) | |
701 | goto unlock; | |
c3505770 CZ |
702 | if (atomic_inc_return(&id_mgr->reserved_vmid_num) > |
703 | AMDGPU_VM_MAX_RESERVED_VMID) { | |
704 | DRM_ERROR("Over limitation of reserved vmid\n"); | |
705 | atomic_dec(&id_mgr->reserved_vmid_num); | |
706 | r = -EINVAL; | |
707 | goto unlock; | |
708 | } | |
1e9ef26f CZ |
709 | /* Select the first entry VMID */ |
710 | idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list); | |
711 | list_del_init(&idle->list); | |
712 | vm->reserved_vmid[vmhub] = idle; | |
713 | mutex_unlock(&id_mgr->lock); | |
714 | ||
715 | return 0; | |
716 | unlock: | |
717 | mutex_unlock(&id_mgr->lock); | |
718 | return r; | |
719 | } | |
720 | ||
e59c0205 AX |
721 | /** |
722 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
723 | * | |
724 | * @adev: amdgpu_device pointer | |
725 | */ | |
726 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 727 | { |
a1255107 | 728 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
729 | bool has_compute_vm_bug; |
730 | struct amdgpu_ring *ring; | |
731 | int i; | |
93dcc37d | 732 | |
e59c0205 | 733 | has_compute_vm_bug = false; |
93dcc37d AD |
734 | |
735 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
e59c0205 AX |
736 | if (ip_block) { |
737 | /* Compute has a VM bug for GFX version < 7. | |
738 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
739 | if (ip_block->version->major <= 7) | |
740 | has_compute_vm_bug = true; | |
741 | else if (ip_block->version->major == 8) | |
742 | if (adev->gfx.mec_fw_version < 673) | |
743 | has_compute_vm_bug = true; | |
744 | } | |
93dcc37d | 745 | |
e59c0205 AX |
746 | for (i = 0; i < adev->num_rings; i++) { |
747 | ring = adev->rings[i]; | |
748 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
749 | /* only compute rings */ | |
750 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 751 | else |
e59c0205 | 752 | ring->has_compute_vm_bug = false; |
93dcc37d | 753 | } |
93dcc37d AD |
754 | } |
755 | ||
b9bf33d5 CZ |
756 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
757 | struct amdgpu_job *job) | |
e60f8db5 | 758 | { |
b9bf33d5 CZ |
759 | struct amdgpu_device *adev = ring->adev; |
760 | unsigned vmhub = ring->funcs->vmhub; | |
761 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
762 | struct amdgpu_vm_id *id; | |
763 | bool gds_switch_needed; | |
e59c0205 | 764 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 CZ |
765 | |
766 | if (job->vm_id == 0) | |
767 | return false; | |
768 | id = &id_mgr->ids[job->vm_id]; | |
769 | gds_switch_needed = ring->funcs->emit_gds_switch && ( | |
770 | id->gds_base != job->gds_base || | |
771 | id->gds_size != job->gds_size || | |
772 | id->gws_base != job->gws_base || | |
773 | id->gws_size != job->gws_size || | |
774 | id->oa_base != job->oa_base || | |
775 | id->oa_size != job->oa_size); | |
e60f8db5 | 776 | |
b9bf33d5 CZ |
777 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
778 | return true; | |
e60f8db5 | 779 | |
bb37b67d | 780 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
781 | } |
782 | ||
9a4b7d4c HK |
783 | static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) |
784 | { | |
785 | return (adev->mc.real_vram_size == adev->mc.visible_vram_size); | |
e60f8db5 AX |
786 | } |
787 | ||
d38ceaf9 AD |
788 | /** |
789 | * amdgpu_vm_flush - hardware flush the vm | |
790 | * | |
791 | * @ring: ring to use for flush | |
cffadc83 | 792 | * @vm_id: vmid number to use |
4ff37a83 | 793 | * @pd_addr: address of the page directory |
d38ceaf9 | 794 | * |
4ff37a83 | 795 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 796 | */ |
8fdf074f | 797 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 798 | { |
971fe9a9 | 799 | struct amdgpu_device *adev = ring->adev; |
7645670d CK |
800 | unsigned vmhub = ring->funcs->vmhub; |
801 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
802 | struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id]; | |
d564a06e | 803 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
804 | id->gds_base != job->gds_base || |
805 | id->gds_size != job->gds_size || | |
806 | id->gws_base != job->gws_base || | |
807 | id->gws_size != job->gws_size || | |
808 | id->oa_base != job->oa_base || | |
809 | id->oa_size != job->oa_size); | |
de37e68a | 810 | bool vm_flush_needed = job->vm_needs_flush; |
c0e51931 | 811 | unsigned patch_offset = 0; |
41d9eb2c | 812 | int r; |
d564a06e | 813 | |
f7d015b9 CK |
814 | if (amdgpu_vm_had_gpu_reset(adev, id)) { |
815 | gds_switch_needed = true; | |
816 | vm_flush_needed = true; | |
817 | } | |
971fe9a9 | 818 | |
8fdf074f | 819 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 820 | return 0; |
41d9eb2c | 821 | |
c0e51931 CK |
822 | if (ring->funcs->init_cond_exec) |
823 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 824 | |
8fdf074f ML |
825 | if (need_pipe_sync) |
826 | amdgpu_ring_emit_pipeline_sync(ring); | |
827 | ||
f7d015b9 | 828 | if (ring->funcs->emit_vm_flush && vm_flush_needed) { |
c0e51931 | 829 | struct dma_fence *fence; |
41d9eb2c | 830 | |
9a94f5a5 CK |
831 | trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr); |
832 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
e9d672b2 | 833 | |
c0e51931 CK |
834 | r = amdgpu_fence_emit(ring, &fence); |
835 | if (r) | |
836 | return r; | |
e9d672b2 | 837 | |
7645670d | 838 | mutex_lock(&id_mgr->lock); |
c0e51931 CK |
839 | dma_fence_put(id->last_flush); |
840 | id->last_flush = fence; | |
bea39672 | 841 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
7645670d | 842 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 843 | } |
e9d672b2 | 844 | |
7c4378f4 | 845 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
846 | id->gds_base = job->gds_base; |
847 | id->gds_size = job->gds_size; | |
848 | id->gws_base = job->gws_base; | |
849 | id->gws_size = job->gws_size; | |
850 | id->oa_base = job->oa_base; | |
851 | id->oa_size = job->oa_size; | |
852 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base, | |
853 | job->gds_size, job->gws_base, | |
854 | job->gws_size, job->oa_base, | |
855 | job->oa_size); | |
856 | } | |
857 | ||
858 | if (ring->funcs->patch_cond_exec) | |
859 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
860 | ||
861 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
862 | if (ring->funcs->emit_switch_buffer) { | |
863 | amdgpu_ring_emit_switch_buffer(ring); | |
864 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 865 | } |
41d9eb2c | 866 | return 0; |
971fe9a9 CK |
867 | } |
868 | ||
869 | /** | |
870 | * amdgpu_vm_reset_id - reset VMID to zero | |
871 | * | |
872 | * @adev: amdgpu device structure | |
873 | * @vm_id: vmid number to use | |
874 | * | |
875 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
876 | */ | |
7645670d CK |
877 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
878 | unsigned vmid) | |
971fe9a9 | 879 | { |
7645670d CK |
880 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
881 | struct amdgpu_vm_id *id = &id_mgr->ids[vmid]; | |
bcb1ba35 | 882 | |
b3c85a0f | 883 | atomic64_set(&id->owner, 0); |
bcb1ba35 CK |
884 | id->gds_base = 0; |
885 | id->gds_size = 0; | |
886 | id->gws_base = 0; | |
887 | id->gws_size = 0; | |
888 | id->oa_base = 0; | |
889 | id->oa_size = 0; | |
d38ceaf9 AD |
890 | } |
891 | ||
b3c85a0f CK |
892 | /** |
893 | * amdgpu_vm_reset_all_id - reset VMID to zero | |
894 | * | |
895 | * @adev: amdgpu device structure | |
896 | * | |
897 | * Reset VMID to force flush on next use | |
898 | */ | |
899 | void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev) | |
900 | { | |
901 | unsigned i, j; | |
902 | ||
903 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
904 | struct amdgpu_vm_id_manager *id_mgr = | |
905 | &adev->vm_manager.id_mgr[i]; | |
906 | ||
907 | for (j = 1; j < id_mgr->num_ids; ++j) | |
908 | amdgpu_vm_reset_id(adev, i, j); | |
909 | } | |
910 | } | |
911 | ||
d38ceaf9 AD |
912 | /** |
913 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
914 | * | |
915 | * @vm: requested vm | |
916 | * @bo: requested buffer object | |
917 | * | |
8843dbbb | 918 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
919 | * Search inside the @bos vm list for the requested vm |
920 | * Returns the found bo_va or NULL if none is found | |
921 | * | |
922 | * Object has to be reserved! | |
923 | */ | |
924 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
925 | struct amdgpu_bo *bo) | |
926 | { | |
927 | struct amdgpu_bo_va *bo_va; | |
928 | ||
ec681545 CK |
929 | list_for_each_entry(bo_va, &bo->va, base.bo_list) { |
930 | if (bo_va->base.vm == vm) { | |
d38ceaf9 AD |
931 | return bo_va; |
932 | } | |
933 | } | |
934 | return NULL; | |
935 | } | |
936 | ||
937 | /** | |
afef8b8f | 938 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 939 | * |
29efc4f5 | 940 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
941 | * @pe: addr of the page entry |
942 | * @addr: dst addr to write into pe | |
943 | * @count: number of page entries to update | |
944 | * @incr: increase next addr by incr bytes | |
945 | * @flags: hw access flags | |
d38ceaf9 AD |
946 | * |
947 | * Traces the parameters and calls the right asic functions | |
948 | * to setup the page table using the DMA. | |
949 | */ | |
afef8b8f CK |
950 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
951 | uint64_t pe, uint64_t addr, | |
952 | unsigned count, uint32_t incr, | |
6b777607 | 953 | uint64_t flags) |
d38ceaf9 | 954 | { |
ec2f05f0 | 955 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 956 | |
afef8b8f | 957 | if (count < 3) { |
de9ea7bd CK |
958 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
959 | addr | flags, count, incr); | |
d38ceaf9 AD |
960 | |
961 | } else { | |
27c5f36f | 962 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
963 | count, incr, flags); |
964 | } | |
965 | } | |
966 | ||
afef8b8f CK |
967 | /** |
968 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
969 | * | |
970 | * @params: see amdgpu_pte_update_params definition | |
971 | * @pe: addr of the page entry | |
972 | * @addr: dst addr to write into pe | |
973 | * @count: number of page entries to update | |
974 | * @incr: increase next addr by incr bytes | |
975 | * @flags: hw access flags | |
976 | * | |
977 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
978 | */ | |
979 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
980 | uint64_t pe, uint64_t addr, | |
981 | unsigned count, uint32_t incr, | |
6b777607 | 982 | uint64_t flags) |
afef8b8f | 983 | { |
ec2f05f0 | 984 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 985 | |
ec2f05f0 CK |
986 | |
987 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
988 | ||
989 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
990 | } |
991 | ||
d38ceaf9 | 992 | /** |
b07c9d2a | 993 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 994 | * |
b07c9d2a | 995 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
996 | * @addr: the unmapped addr |
997 | * | |
998 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 999 | * to and return the pointer for the page table entry. |
d38ceaf9 | 1000 | */ |
de9ea7bd | 1001 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
1002 | { |
1003 | uint64_t result; | |
1004 | ||
de9ea7bd CK |
1005 | /* page table offset */ |
1006 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 1007 | |
de9ea7bd CK |
1008 | /* in case cpu page size != gpu page size*/ |
1009 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 1010 | |
b07c9d2a | 1011 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
1012 | |
1013 | return result; | |
1014 | } | |
1015 | ||
3c824172 HK |
1016 | /** |
1017 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU | |
1018 | * | |
1019 | * @params: see amdgpu_pte_update_params definition | |
1020 | * @pe: kmap addr of the page entry | |
1021 | * @addr: dst addr to write into pe | |
1022 | * @count: number of page entries to update | |
1023 | * @incr: increase next addr by incr bytes | |
1024 | * @flags: hw access flags | |
1025 | * | |
1026 | * Write count number of PT/PD entries directly. | |
1027 | */ | |
1028 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, | |
1029 | uint64_t pe, uint64_t addr, | |
1030 | unsigned count, uint32_t incr, | |
1031 | uint64_t flags) | |
1032 | { | |
1033 | unsigned int i; | |
b4d42511 | 1034 | uint64_t value; |
3c824172 | 1035 | |
03918b36 CK |
1036 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
1037 | ||
3c824172 | 1038 | for (i = 0; i < count; i++) { |
b4d42511 HK |
1039 | value = params->pages_addr ? |
1040 | amdgpu_vm_map_gart(params->pages_addr, addr) : | |
1041 | addr; | |
a1924005 | 1042 | amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe, |
b4d42511 | 1043 | i, value, flags); |
3c824172 HK |
1044 | addr += incr; |
1045 | } | |
3c824172 HK |
1046 | } |
1047 | ||
a33cab7a CK |
1048 | static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
1049 | void *owner) | |
3c824172 HK |
1050 | { |
1051 | struct amdgpu_sync sync; | |
1052 | int r; | |
1053 | ||
1054 | amdgpu_sync_create(&sync); | |
177ae09b | 1055 | amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false); |
3c824172 HK |
1056 | r = amdgpu_sync_wait(&sync, true); |
1057 | amdgpu_sync_free(&sync); | |
1058 | ||
1059 | return r; | |
1060 | } | |
1061 | ||
f8991bab | 1062 | /* |
194d2161 | 1063 | * amdgpu_vm_update_level - update a single level in the hierarchy |
f8991bab CK |
1064 | * |
1065 | * @adev: amdgpu_device pointer | |
1066 | * @vm: requested vm | |
194d2161 | 1067 | * @parent: parent directory |
f8991bab | 1068 | * |
194d2161 | 1069 | * Makes sure all entries in @parent are up to date. |
f8991bab CK |
1070 | * Returns 0 for success, error for failure. |
1071 | */ | |
194d2161 CK |
1072 | static int amdgpu_vm_update_level(struct amdgpu_device *adev, |
1073 | struct amdgpu_vm *vm, | |
ea09729c | 1074 | struct amdgpu_vm_pt *parent) |
d38ceaf9 | 1075 | { |
f8991bab | 1076 | struct amdgpu_bo *shadow; |
a1924005 HK |
1077 | struct amdgpu_ring *ring = NULL; |
1078 | uint64_t pd_addr, shadow_addr = 0; | |
f8991bab | 1079 | uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; |
a1924005 | 1080 | unsigned count = 0, pt_idx, ndw = 0; |
d71518b5 | 1081 | struct amdgpu_job *job; |
29efc4f5 | 1082 | struct amdgpu_pte_update_params params; |
f54d1867 | 1083 | struct dma_fence *fence = NULL; |
ea09729c | 1084 | uint32_t incr; |
d5fc5e82 | 1085 | |
d38ceaf9 AD |
1086 | int r; |
1087 | ||
194d2161 CK |
1088 | if (!parent->entries) |
1089 | return 0; | |
2d55e45a | 1090 | |
3c824172 HK |
1091 | memset(¶ms, 0, sizeof(params)); |
1092 | params.adev = adev; | |
3f3333f8 | 1093 | shadow = parent->base.bo->shadow; |
d38ceaf9 | 1094 | |
69277985 | 1095 | if (vm->use_cpu_for_update) { |
3f3333f8 | 1096 | pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); |
a33cab7a | 1097 | r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); |
0a096fb6 | 1098 | if (unlikely(r)) |
3c824172 | 1099 | return r; |
0a096fb6 | 1100 | |
3c824172 HK |
1101 | params.func = amdgpu_vm_cpu_set_ptes; |
1102 | } else { | |
3c824172 HK |
1103 | ring = container_of(vm->entity.sched, struct amdgpu_ring, |
1104 | sched); | |
d38ceaf9 | 1105 | |
3c824172 HK |
1106 | /* padding, etc. */ |
1107 | ndw = 64; | |
194d2161 | 1108 | |
3c824172 HK |
1109 | /* assume the worst case */ |
1110 | ndw += parent->last_entry_used * 6; | |
1111 | ||
3f3333f8 | 1112 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); |
3c824172 HK |
1113 | |
1114 | if (shadow) { | |
1115 | shadow_addr = amdgpu_bo_gpu_offset(shadow); | |
1116 | ndw *= 2; | |
1117 | } else { | |
1118 | shadow_addr = 0; | |
1119 | } | |
1120 | ||
1121 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
f8991bab CK |
1122 | if (r) |
1123 | return r; | |
f8991bab | 1124 | |
3c824172 HK |
1125 | params.ib = &job->ibs[0]; |
1126 | params.func = amdgpu_vm_do_set_ptes; | |
1127 | } | |
d71518b5 | 1128 | |
d38ceaf9 | 1129 | |
194d2161 CK |
1130 | /* walk over the address space and update the directory */ |
1131 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
ea09729c CK |
1132 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
1133 | struct amdgpu_bo *bo = entry->base.bo; | |
d38ceaf9 AD |
1134 | uint64_t pde, pt; |
1135 | ||
1136 | if (bo == NULL) | |
1137 | continue; | |
1138 | ||
ea09729c CK |
1139 | spin_lock(&vm->status_lock); |
1140 | list_del_init(&entry->base.vm_status); | |
1141 | spin_unlock(&vm->status_lock); | |
1142 | ||
d38ceaf9 | 1143 | pt = amdgpu_bo_gpu_offset(bo); |
53e2e91d | 1144 | pt = amdgpu_gart_get_vm_pde(adev, pt); |
4ab4016a CK |
1145 | /* Don't update huge pages here */ |
1146 | if ((parent->entries[pt_idx].addr & AMDGPU_PDE_PTE) || | |
1147 | parent->entries[pt_idx].addr == (pt | AMDGPU_PTE_VALID)) | |
f8991bab CK |
1148 | continue; |
1149 | ||
4ab4016a | 1150 | parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID; |
d38ceaf9 AD |
1151 | |
1152 | pde = pd_addr + pt_idx * 8; | |
ea09729c | 1153 | incr = amdgpu_bo_size(bo); |
d38ceaf9 | 1154 | if (((last_pde + 8 * count) != pde) || |
96105e53 CK |
1155 | ((last_pt + incr * count) != pt) || |
1156 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
d38ceaf9 AD |
1157 | |
1158 | if (count) { | |
f8991bab | 1159 | if (shadow) |
3c824172 HK |
1160 | params.func(¶ms, |
1161 | last_shadow, | |
1162 | last_pt, count, | |
1163 | incr, | |
1164 | AMDGPU_PTE_VALID); | |
1165 | ||
1166 | params.func(¶ms, last_pde, | |
1167 | last_pt, count, incr, | |
1168 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
1169 | } |
1170 | ||
1171 | count = 1; | |
1172 | last_pde = pde; | |
f8991bab | 1173 | last_shadow = shadow_addr + pt_idx * 8; |
d38ceaf9 AD |
1174 | last_pt = pt; |
1175 | } else { | |
1176 | ++count; | |
1177 | } | |
1178 | } | |
1179 | ||
f8991bab | 1180 | if (count) { |
3f3333f8 | 1181 | if (vm->root.base.bo->shadow) |
3c824172 HK |
1182 | params.func(¶ms, last_shadow, last_pt, |
1183 | count, incr, AMDGPU_PTE_VALID); | |
f8991bab | 1184 | |
3c824172 HK |
1185 | params.func(¶ms, last_pde, last_pt, |
1186 | count, incr, AMDGPU_PTE_VALID); | |
f8991bab | 1187 | } |
d38ceaf9 | 1188 | |
0a096fb6 CK |
1189 | if (!vm->use_cpu_for_update) { |
1190 | if (params.ib->length_dw == 0) { | |
1191 | amdgpu_job_free(job); | |
1192 | } else { | |
1193 | amdgpu_ring_pad_ib(ring, params.ib); | |
3f3333f8 CK |
1194 | amdgpu_sync_resv(adev, &job->sync, |
1195 | parent->base.bo->tbo.resv, | |
177ae09b | 1196 | AMDGPU_FENCE_OWNER_VM, false); |
0a096fb6 CK |
1197 | if (shadow) |
1198 | amdgpu_sync_resv(adev, &job->sync, | |
1199 | shadow->tbo.resv, | |
177ae09b | 1200 | AMDGPU_FENCE_OWNER_VM, false); |
0a096fb6 CK |
1201 | |
1202 | WARN_ON(params.ib->length_dw > ndw); | |
1203 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
1204 | AMDGPU_FENCE_OWNER_VM, &fence); | |
1205 | if (r) | |
1206 | goto error_free; | |
05906dec | 1207 | |
3f3333f8 | 1208 | amdgpu_bo_fence(parent->base.bo, fence, true); |
d5884513 CK |
1209 | dma_fence_put(vm->last_update); |
1210 | vm->last_update = fence; | |
0a096fb6 | 1211 | } |
194d2161 | 1212 | } |
d38ceaf9 AD |
1213 | |
1214 | return 0; | |
d5fc5e82 CZ |
1215 | |
1216 | error_free: | |
d71518b5 | 1217 | amdgpu_job_free(job); |
4af9f07c | 1218 | return r; |
d38ceaf9 AD |
1219 | } |
1220 | ||
92456b93 CK |
1221 | /* |
1222 | * amdgpu_vm_invalidate_level - mark all PD levels as invalid | |
1223 | * | |
1224 | * @parent: parent PD | |
1225 | * | |
1226 | * Mark all PD level as invalid after an error. | |
1227 | */ | |
ea09729c CK |
1228 | static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm, |
1229 | struct amdgpu_vm_pt *parent) | |
92456b93 CK |
1230 | { |
1231 | unsigned pt_idx; | |
1232 | ||
1233 | /* | |
1234 | * Recurse into the subdirectories. This recursion is harmless because | |
1235 | * we only have a maximum of 5 layers. | |
1236 | */ | |
1237 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
1238 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
1239 | ||
3f3333f8 | 1240 | if (!entry->base.bo) |
92456b93 CK |
1241 | continue; |
1242 | ||
1243 | entry->addr = ~0ULL; | |
ea09729c | 1244 | spin_lock(&vm->status_lock); |
481c2e94 CK |
1245 | if (list_empty(&entry->base.vm_status)) |
1246 | list_add(&entry->base.vm_status, &vm->relocated); | |
ea09729c CK |
1247 | spin_unlock(&vm->status_lock); |
1248 | amdgpu_vm_invalidate_level(vm, entry); | |
92456b93 CK |
1249 | } |
1250 | } | |
1251 | ||
194d2161 CK |
1252 | /* |
1253 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1254 | * | |
1255 | * @adev: amdgpu_device pointer | |
1256 | * @vm: requested vm | |
1257 | * | |
1258 | * Makes sure all directories are up to date. | |
1259 | * Returns 0 for success, error for failure. | |
1260 | */ | |
1261 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1262 | struct amdgpu_vm *vm) | |
1263 | { | |
78aa02c7 | 1264 | int r = 0; |
92456b93 | 1265 | |
ea09729c CK |
1266 | spin_lock(&vm->status_lock); |
1267 | while (!list_empty(&vm->relocated)) { | |
1268 | struct amdgpu_vm_bo_base *bo_base; | |
1269 | struct amdgpu_bo *bo; | |
1270 | ||
1271 | bo_base = list_first_entry(&vm->relocated, | |
1272 | struct amdgpu_vm_bo_base, | |
1273 | vm_status); | |
1274 | spin_unlock(&vm->status_lock); | |
1275 | ||
1276 | bo = bo_base->bo->parent; | |
1277 | if (bo) { | |
1278 | struct amdgpu_vm_bo_base *parent; | |
1279 | struct amdgpu_vm_pt *pt; | |
1280 | ||
1281 | parent = list_first_entry(&bo->va, | |
1282 | struct amdgpu_vm_bo_base, | |
1283 | bo_list); | |
1284 | pt = container_of(parent, struct amdgpu_vm_pt, base); | |
1285 | ||
1286 | r = amdgpu_vm_update_level(adev, vm, pt); | |
1287 | if (r) { | |
1288 | amdgpu_vm_invalidate_level(vm, &vm->root); | |
1289 | return r; | |
1290 | } | |
1291 | spin_lock(&vm->status_lock); | |
1292 | } else { | |
1293 | spin_lock(&vm->status_lock); | |
1294 | list_del_init(&bo_base->vm_status); | |
1295 | } | |
1296 | } | |
1297 | spin_unlock(&vm->status_lock); | |
92456b93 | 1298 | |
68c62306 CK |
1299 | if (vm->use_cpu_for_update) { |
1300 | /* Flush HDP */ | |
1301 | mb(); | |
1302 | amdgpu_gart_flush_gpu_tlb(adev, 0); | |
1303 | } | |
1304 | ||
92456b93 | 1305 | return r; |
194d2161 CK |
1306 | } |
1307 | ||
4e2cb640 | 1308 | /** |
cf2f0a37 | 1309 | * amdgpu_vm_find_entry - find the entry for an address |
4e2cb640 CK |
1310 | * |
1311 | * @p: see amdgpu_pte_update_params definition | |
1312 | * @addr: virtual address in question | |
cf2f0a37 AD |
1313 | * @entry: resulting entry or NULL |
1314 | * @parent: parent entry | |
4e2cb640 | 1315 | * |
cf2f0a37 | 1316 | * Find the vm_pt entry and it's parent for the given address. |
4e2cb640 | 1317 | */ |
cf2f0a37 AD |
1318 | void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, |
1319 | struct amdgpu_vm_pt **entry, | |
1320 | struct amdgpu_vm_pt **parent) | |
4e2cb640 | 1321 | { |
50783147 | 1322 | unsigned level = 0; |
4e2cb640 | 1323 | |
cf2f0a37 AD |
1324 | *parent = NULL; |
1325 | *entry = &p->vm->root; | |
1326 | while ((*entry)->entries) { | |
50783147 CK |
1327 | unsigned idx = addr >> amdgpu_vm_level_shift(p->adev, level++); |
1328 | ||
3f3333f8 | 1329 | idx %= amdgpu_bo_size((*entry)->base.bo) / 8; |
cf2f0a37 AD |
1330 | *parent = *entry; |
1331 | *entry = &(*entry)->entries[idx]; | |
4e2cb640 CK |
1332 | } |
1333 | ||
50783147 | 1334 | if (level != p->adev->vm_manager.num_level) |
cf2f0a37 AD |
1335 | *entry = NULL; |
1336 | } | |
1337 | ||
1338 | /** | |
1339 | * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages | |
1340 | * | |
1341 | * @p: see amdgpu_pte_update_params definition | |
1342 | * @entry: vm_pt entry to check | |
1343 | * @parent: parent entry | |
1344 | * @nptes: number of PTEs updated with this operation | |
1345 | * @dst: destination address where the PTEs should point to | |
1346 | * @flags: access flags fro the PTEs | |
1347 | * | |
1348 | * Check if we can update the PD with a huge page. | |
1349 | */ | |
ec5207c9 CK |
1350 | static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, |
1351 | struct amdgpu_vm_pt *entry, | |
1352 | struct amdgpu_vm_pt *parent, | |
1353 | unsigned nptes, uint64_t dst, | |
1354 | uint64_t flags) | |
cf2f0a37 AD |
1355 | { |
1356 | bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes); | |
1357 | uint64_t pd_addr, pde; | |
cf2f0a37 AD |
1358 | |
1359 | /* In the case of a mixed PT the PDE must point to it*/ | |
1360 | if (p->adev->asic_type < CHIP_VEGA10 || | |
1361 | nptes != AMDGPU_VM_PTE_COUNT(p->adev) || | |
b252903a | 1362 | p->src || |
cf2f0a37 AD |
1363 | !(flags & AMDGPU_PTE_VALID)) { |
1364 | ||
3f3333f8 | 1365 | dst = amdgpu_bo_gpu_offset(entry->base.bo); |
cf2f0a37 AD |
1366 | dst = amdgpu_gart_get_vm_pde(p->adev, dst); |
1367 | flags = AMDGPU_PTE_VALID; | |
1368 | } else { | |
4ab4016a | 1369 | /* Set the huge page flag to stop scanning at this PDE */ |
cf2f0a37 AD |
1370 | flags |= AMDGPU_PDE_PTE; |
1371 | } | |
1372 | ||
4ab4016a | 1373 | if (entry->addr == (dst | flags)) |
ec5207c9 | 1374 | return; |
cf2f0a37 | 1375 | |
4ab4016a | 1376 | entry->addr = (dst | flags); |
cf2f0a37 AD |
1377 | |
1378 | if (use_cpu_update) { | |
b252903a FK |
1379 | /* In case a huge page is replaced with a system |
1380 | * memory mapping, p->pages_addr != NULL and | |
1381 | * amdgpu_vm_cpu_set_ptes would try to translate dst | |
1382 | * through amdgpu_vm_map_gart. But dst is already a | |
1383 | * GPU address (of the page table). Disable | |
1384 | * amdgpu_vm_map_gart temporarily. | |
1385 | */ | |
1386 | dma_addr_t *tmp; | |
1387 | ||
1388 | tmp = p->pages_addr; | |
1389 | p->pages_addr = NULL; | |
1390 | ||
3f3333f8 | 1391 | pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); |
cf2f0a37 AD |
1392 | pde = pd_addr + (entry - parent->entries) * 8; |
1393 | amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags); | |
b252903a FK |
1394 | |
1395 | p->pages_addr = tmp; | |
cf2f0a37 | 1396 | } else { |
3f3333f8 CK |
1397 | if (parent->base.bo->shadow) { |
1398 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow); | |
cf2f0a37 AD |
1399 | pde = pd_addr + (entry - parent->entries) * 8; |
1400 | amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); | |
1401 | } | |
3f3333f8 | 1402 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); |
cf2f0a37 AD |
1403 | pde = pd_addr + (entry - parent->entries) * 8; |
1404 | amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); | |
1405 | } | |
4e2cb640 CK |
1406 | } |
1407 | ||
d38ceaf9 AD |
1408 | /** |
1409 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1410 | * | |
29efc4f5 | 1411 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1412 | * @vm: requested vm |
1413 | * @start: start of GPU address range | |
1414 | * @end: end of GPU address range | |
677131a1 | 1415 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1416 | * @flags: mapping flags |
1417 | * | |
8843dbbb | 1418 | * Update the page tables in the range @start - @end. |
cc28c4ed | 1419 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 | 1420 | */ |
cc28c4ed | 1421 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1422 | uint64_t start, uint64_t end, |
6b777607 | 1423 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1424 | { |
36b32a68 ZJ |
1425 | struct amdgpu_device *adev = params->adev; |
1426 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1427 | |
301654a4 | 1428 | uint64_t addr, pe_start; |
21718497 | 1429 | struct amdgpu_bo *pt; |
301654a4 | 1430 | unsigned nptes; |
370f092f | 1431 | bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes); |
d38ceaf9 AD |
1432 | |
1433 | /* walk over the address space and update the page tables */ | |
cf2f0a37 AD |
1434 | for (addr = start; addr < end; addr += nptes, |
1435 | dst += nptes * AMDGPU_GPU_PAGE_SIZE) { | |
1436 | struct amdgpu_vm_pt *entry, *parent; | |
1437 | ||
1438 | amdgpu_vm_get_entry(params, addr, &entry, &parent); | |
1439 | if (!entry) | |
1440 | return -ENOENT; | |
4e2cb640 | 1441 | |
d38ceaf9 AD |
1442 | if ((addr & ~mask) == (end & ~mask)) |
1443 | nptes = end - addr; | |
1444 | else | |
36b32a68 | 1445 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1446 | |
ec5207c9 CK |
1447 | amdgpu_vm_handle_huge_pages(params, entry, parent, |
1448 | nptes, dst, flags); | |
4ab4016a CK |
1449 | /* We don't need to update PTEs for huge pages */ |
1450 | if (entry->addr & AMDGPU_PDE_PTE) | |
cf2f0a37 AD |
1451 | continue; |
1452 | ||
3f3333f8 | 1453 | pt = entry->base.bo; |
370f092f | 1454 | if (use_cpu_update) { |
f5e1c740 | 1455 | pe_start = (unsigned long)amdgpu_bo_kptr(pt); |
dd0792c1 CK |
1456 | } else { |
1457 | if (pt->shadow) { | |
1458 | pe_start = amdgpu_bo_gpu_offset(pt->shadow); | |
1459 | pe_start += (addr & mask) * 8; | |
1460 | params->func(params, pe_start, dst, nptes, | |
1461 | AMDGPU_GPU_PAGE_SIZE, flags); | |
1462 | } | |
370f092f | 1463 | pe_start = amdgpu_bo_gpu_offset(pt); |
dd0792c1 | 1464 | } |
d38ceaf9 | 1465 | |
301654a4 | 1466 | pe_start += (addr & mask) * 8; |
301654a4 CK |
1467 | params->func(params, pe_start, dst, nptes, |
1468 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
1469 | } |
1470 | ||
cc28c4ed | 1471 | return 0; |
92696dd5 CK |
1472 | } |
1473 | ||
1474 | /* | |
1475 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1476 | * | |
1477 | * @params: see amdgpu_pte_update_params definition | |
1478 | * @vm: requested vm | |
1479 | * @start: first PTE to handle | |
1480 | * @end: last PTE to handle | |
1481 | * @dst: addr those PTEs should point to | |
1482 | * @flags: hw mapping flags | |
cc28c4ed | 1483 | * Returns 0 for success, -EINVAL for failure. |
92696dd5 | 1484 | */ |
cc28c4ed | 1485 | static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, |
92696dd5 | 1486 | uint64_t start, uint64_t end, |
6b777607 | 1487 | uint64_t dst, uint64_t flags) |
92696dd5 CK |
1488 | { |
1489 | /** | |
1490 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1491 | * field in the PTE. When this field is set to a non-zero value, page | |
1492 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1493 | * flags are considered valid for all PTEs within the fragment range | |
1494 | * and corresponding mappings are assumed to be physically contiguous. | |
1495 | * | |
1496 | * The L1 TLB can store a single PTE for the whole fragment, | |
1497 | * significantly increasing the space available for translation | |
1498 | * caching. This leads to large improvements in throughput when the | |
1499 | * TLB is under pressure. | |
1500 | * | |
1501 | * The L2 TLB distributes small and large fragments into two | |
1502 | * asymmetric partitions. The large fragment cache is significantly | |
1503 | * larger. Thus, we try to use large fragments wherever possible. | |
1504 | * Userspace can support this by aligning virtual base address and | |
1505 | * allocation size to the fragment size. | |
1506 | */ | |
6849d47c RH |
1507 | unsigned max_frag = params->adev->vm_manager.fragment_size; |
1508 | int r; | |
92696dd5 CK |
1509 | |
1510 | /* system pages are non continuously */ | |
6849d47c | 1511 | if (params->src || !(flags & AMDGPU_PTE_VALID)) |
cc28c4ed | 1512 | return amdgpu_vm_update_ptes(params, start, end, dst, flags); |
92696dd5 | 1513 | |
6849d47c RH |
1514 | while (start != end) { |
1515 | uint64_t frag_flags, frag_end; | |
1516 | unsigned frag; | |
1517 | ||
1518 | /* This intentionally wraps around if no bit is set */ | |
1519 | frag = min((unsigned)ffs(start) - 1, | |
1520 | (unsigned)fls64(end - start) - 1); | |
1521 | if (frag >= max_frag) { | |
1522 | frag_flags = AMDGPU_PTE_FRAG(max_frag); | |
1523 | frag_end = end & ~((1ULL << max_frag) - 1); | |
1524 | } else { | |
1525 | frag_flags = AMDGPU_PTE_FRAG(frag); | |
1526 | frag_end = start + (1 << frag); | |
1527 | } | |
1528 | ||
1529 | r = amdgpu_vm_update_ptes(params, start, frag_end, dst, | |
1530 | flags | frag_flags); | |
cc28c4ed HK |
1531 | if (r) |
1532 | return r; | |
92696dd5 | 1533 | |
6849d47c RH |
1534 | dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE; |
1535 | start = frag_end; | |
92696dd5 | 1536 | } |
6849d47c RH |
1537 | |
1538 | return 0; | |
d38ceaf9 AD |
1539 | } |
1540 | ||
d38ceaf9 AD |
1541 | /** |
1542 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1543 | * | |
1544 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1545 | * @exclusive: fence we need to sync to |
fa3ab3c7 | 1546 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 | 1547 | * @vm: requested vm |
a14faa65 CK |
1548 | * @start: start of mapped range |
1549 | * @last: last mapped entry | |
1550 | * @flags: flags for the entries | |
d38ceaf9 | 1551 | * @addr: addr to set the area to |
d38ceaf9 AD |
1552 | * @fence: optional resulting fence |
1553 | * | |
a14faa65 | 1554 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 1555 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
1556 | */ |
1557 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1558 | struct dma_fence *exclusive, |
fa3ab3c7 | 1559 | dma_addr_t *pages_addr, |
d38ceaf9 | 1560 | struct amdgpu_vm *vm, |
a14faa65 | 1561 | uint64_t start, uint64_t last, |
6b777607 | 1562 | uint64_t flags, uint64_t addr, |
f54d1867 | 1563 | struct dma_fence **fence) |
d38ceaf9 | 1564 | { |
2d55e45a | 1565 | struct amdgpu_ring *ring; |
a1e08d3b | 1566 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1567 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1568 | struct amdgpu_job *job; |
29efc4f5 | 1569 | struct amdgpu_pte_update_params params; |
f54d1867 | 1570 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1571 | int r; |
1572 | ||
afef8b8f CK |
1573 | memset(¶ms, 0, sizeof(params)); |
1574 | params.adev = adev; | |
49ac8a24 | 1575 | params.vm = vm; |
afef8b8f | 1576 | |
a33cab7a CK |
1577 | /* sync to everything on unmapping */ |
1578 | if (!(flags & AMDGPU_PTE_VALID)) | |
1579 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1580 | ||
b4d42511 HK |
1581 | if (vm->use_cpu_for_update) { |
1582 | /* params.src is used as flag to indicate system Memory */ | |
1583 | if (pages_addr) | |
1584 | params.src = ~0; | |
1585 | ||
1586 | /* Wait for PT BOs to be free. PTs share the same resv. object | |
1587 | * as the root PD BO | |
1588 | */ | |
a33cab7a | 1589 | r = amdgpu_vm_wait_pd(adev, vm, owner); |
b4d42511 HK |
1590 | if (unlikely(r)) |
1591 | return r; | |
1592 | ||
1593 | params.func = amdgpu_vm_cpu_set_ptes; | |
1594 | params.pages_addr = pages_addr; | |
b4d42511 HK |
1595 | return amdgpu_vm_frag_ptes(¶ms, start, last + 1, |
1596 | addr, flags); | |
1597 | } | |
1598 | ||
2d55e45a | 1599 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 1600 | |
a14faa65 | 1601 | nptes = last - start + 1; |
d38ceaf9 AD |
1602 | |
1603 | /* | |
86209523 | 1604 | * reserve space for two commands every (1 << BLOCK_SIZE) |
d38ceaf9 | 1605 | * entries or 2k dwords (whatever is smaller) |
86209523 BN |
1606 | * |
1607 | * The second command is for the shadow pagetables. | |
d38ceaf9 | 1608 | */ |
86209523 | 1609 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2; |
d38ceaf9 AD |
1610 | |
1611 | /* padding, etc. */ | |
1612 | ndw = 64; | |
1613 | ||
cf2f0a37 AD |
1614 | /* one PDE write for each huge page */ |
1615 | ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6; | |
1616 | ||
570144c6 | 1617 | if (pages_addr) { |
b0456f93 | 1618 | /* copy commands needed */ |
e6d92197 | 1619 | ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; |
d38ceaf9 | 1620 | |
b0456f93 | 1621 | /* and also PTEs */ |
d38ceaf9 AD |
1622 | ndw += nptes * 2; |
1623 | ||
afef8b8f CK |
1624 | params.func = amdgpu_vm_do_copy_ptes; |
1625 | ||
d38ceaf9 AD |
1626 | } else { |
1627 | /* set page commands needed */ | |
7bdc53f9 | 1628 | ndw += ncmds * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw; |
d38ceaf9 | 1629 | |
6849d47c | 1630 | /* extra commands for begin/end fragments */ |
7bdc53f9 YZ |
1631 | ndw += 2 * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw |
1632 | * adev->vm_manager.fragment_size; | |
afef8b8f CK |
1633 | |
1634 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1635 | } |
1636 | ||
d71518b5 CK |
1637 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1638 | if (r) | |
d38ceaf9 | 1639 | return r; |
d71518b5 | 1640 | |
29efc4f5 | 1641 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1642 | |
570144c6 | 1643 | if (pages_addr) { |
b0456f93 CK |
1644 | uint64_t *pte; |
1645 | unsigned i; | |
1646 | ||
1647 | /* Put the PTEs at the end of the IB. */ | |
1648 | i = ndw - nptes * 2; | |
1649 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1650 | params.src = job->ibs->gpu_addr + i * 4; | |
1651 | ||
1652 | for (i = 0; i < nptes; ++i) { | |
1653 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1654 | AMDGPU_GPU_PAGE_SIZE); | |
1655 | pte[i] |= flags; | |
1656 | } | |
d7a4ac66 | 1657 | addr = 0; |
b0456f93 CK |
1658 | } |
1659 | ||
3cabaa54 CK |
1660 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
1661 | if (r) | |
1662 | goto error_free; | |
1663 | ||
3f3333f8 | 1664 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, |
177ae09b | 1665 | owner, false); |
a1e08d3b CK |
1666 | if (r) |
1667 | goto error_free; | |
d38ceaf9 | 1668 | |
3f3333f8 | 1669 | r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv); |
a1e08d3b CK |
1670 | if (r) |
1671 | goto error_free; | |
1672 | ||
cc28c4ed HK |
1673 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
1674 | if (r) | |
1675 | goto error_free; | |
d38ceaf9 | 1676 | |
29efc4f5 CK |
1677 | amdgpu_ring_pad_ib(ring, params.ib); |
1678 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1679 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1680 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1681 | if (r) |
1682 | goto error_free; | |
d38ceaf9 | 1683 | |
3f3333f8 | 1684 | amdgpu_bo_fence(vm->root.base.bo, f, true); |
284710fa CK |
1685 | dma_fence_put(*fence); |
1686 | *fence = f; | |
d38ceaf9 | 1687 | return 0; |
d5fc5e82 CZ |
1688 | |
1689 | error_free: | |
d71518b5 | 1690 | amdgpu_job_free(job); |
ea09729c | 1691 | amdgpu_vm_invalidate_level(vm, &vm->root); |
4af9f07c | 1692 | return r; |
d38ceaf9 AD |
1693 | } |
1694 | ||
a14faa65 CK |
1695 | /** |
1696 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1697 | * | |
1698 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1699 | * @exclusive: fence we need to sync to |
8358dcee | 1700 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1701 | * @vm: requested vm |
1702 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1703 | * @flags: HW flags for the mapping |
63e0ba40 | 1704 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1705 | * @fence: optional resulting fence |
1706 | * | |
1707 | * Split the mapping into smaller chunks so that each update fits | |
1708 | * into a SDMA IB. | |
1709 | * Returns 0 for success, -EINVAL for failure. | |
1710 | */ | |
1711 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1712 | struct dma_fence *exclusive, |
8358dcee | 1713 | dma_addr_t *pages_addr, |
a14faa65 CK |
1714 | struct amdgpu_vm *vm, |
1715 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1716 | uint64_t flags, |
63e0ba40 | 1717 | struct drm_mm_node *nodes, |
f54d1867 | 1718 | struct dma_fence **fence) |
a14faa65 | 1719 | { |
9fc8fc70 | 1720 | unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; |
570144c6 | 1721 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1722 | int r; |
1723 | ||
1724 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1725 | * but in case of something, we filter the flags in first place | |
1726 | */ | |
1727 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1728 | flags &= ~AMDGPU_PTE_READABLE; | |
1729 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1730 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1731 | ||
15b31c59 AX |
1732 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1733 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1734 | ||
b0fd18b0 AX |
1735 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1736 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1737 | ||
d0766e98 ZJ |
1738 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1739 | (adev->asic_type >= CHIP_VEGA10)) { | |
1740 | flags |= AMDGPU_PTE_PRT; | |
1741 | flags &= ~AMDGPU_PTE_VALID; | |
1742 | } | |
1743 | ||
a14faa65 CK |
1744 | trace_amdgpu_vm_bo_update(mapping); |
1745 | ||
63e0ba40 CK |
1746 | pfn = mapping->offset >> PAGE_SHIFT; |
1747 | if (nodes) { | |
1748 | while (pfn >= nodes->size) { | |
1749 | pfn -= nodes->size; | |
1750 | ++nodes; | |
1751 | } | |
fa3ab3c7 | 1752 | } |
a14faa65 | 1753 | |
63e0ba40 | 1754 | do { |
9fc8fc70 | 1755 | dma_addr_t *dma_addr = NULL; |
63e0ba40 CK |
1756 | uint64_t max_entries; |
1757 | uint64_t addr, last; | |
a14faa65 | 1758 | |
63e0ba40 CK |
1759 | if (nodes) { |
1760 | addr = nodes->start << PAGE_SHIFT; | |
1761 | max_entries = (nodes->size - pfn) * | |
1762 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1763 | } else { | |
1764 | addr = 0; | |
1765 | max_entries = S64_MAX; | |
1766 | } | |
a14faa65 | 1767 | |
63e0ba40 | 1768 | if (pages_addr) { |
9fc8fc70 CK |
1769 | uint64_t count; |
1770 | ||
457e0fee | 1771 | max_entries = min(max_entries, 16ull * 1024ull); |
9fc8fc70 CK |
1772 | for (count = 1; count < max_entries; ++count) { |
1773 | uint64_t idx = pfn + count; | |
1774 | ||
1775 | if (pages_addr[idx] != | |
1776 | (pages_addr[idx - 1] + PAGE_SIZE)) | |
1777 | break; | |
1778 | } | |
1779 | ||
1780 | if (count < min_linear_pages) { | |
1781 | addr = pfn << PAGE_SHIFT; | |
1782 | dma_addr = pages_addr; | |
1783 | } else { | |
1784 | addr = pages_addr[pfn]; | |
1785 | max_entries = count; | |
1786 | } | |
1787 | ||
63e0ba40 CK |
1788 | } else if (flags & AMDGPU_PTE_VALID) { |
1789 | addr += adev->vm_manager.vram_base_offset; | |
9fc8fc70 | 1790 | addr += pfn << PAGE_SHIFT; |
63e0ba40 | 1791 | } |
63e0ba40 | 1792 | |
a9f87f64 | 1793 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
9fc8fc70 | 1794 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, |
a14faa65 CK |
1795 | start, last, flags, addr, |
1796 | fence); | |
1797 | if (r) | |
1798 | return r; | |
1799 | ||
63e0ba40 CK |
1800 | pfn += last - start + 1; |
1801 | if (nodes && nodes->size == pfn) { | |
1802 | pfn = 0; | |
1803 | ++nodes; | |
1804 | } | |
a14faa65 | 1805 | start = last + 1; |
63e0ba40 | 1806 | |
a9f87f64 | 1807 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1808 | |
1809 | return 0; | |
1810 | } | |
1811 | ||
d38ceaf9 AD |
1812 | /** |
1813 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1814 | * | |
1815 | * @adev: amdgpu_device pointer | |
1816 | * @bo_va: requested BO and VM object | |
99e124f4 | 1817 | * @clear: if true clear the entries |
d38ceaf9 AD |
1818 | * |
1819 | * Fill in the page table entries for @bo_va. | |
1820 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1821 | */ |
1822 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1823 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1824 | bool clear) |
d38ceaf9 | 1825 | { |
ec681545 CK |
1826 | struct amdgpu_bo *bo = bo_va->base.bo; |
1827 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1828 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1829 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 1830 | struct ttm_mem_reg *mem; |
63e0ba40 | 1831 | struct drm_mm_node *nodes; |
4e55eb38 | 1832 | struct dma_fence *exclusive, **last_update; |
457e0fee | 1833 | uint64_t flags; |
d38ceaf9 AD |
1834 | int r; |
1835 | ||
ec681545 | 1836 | if (clear || !bo_va->base.bo) { |
99e124f4 | 1837 | mem = NULL; |
63e0ba40 | 1838 | nodes = NULL; |
99e124f4 CK |
1839 | exclusive = NULL; |
1840 | } else { | |
8358dcee CK |
1841 | struct ttm_dma_tt *ttm; |
1842 | ||
ec681545 | 1843 | mem = &bo_va->base.bo->tbo.mem; |
63e0ba40 CK |
1844 | nodes = mem->mm_node; |
1845 | if (mem->mem_type == TTM_PL_TT) { | |
ec681545 CK |
1846 | ttm = container_of(bo_va->base.bo->tbo.ttm, |
1847 | struct ttm_dma_tt, ttm); | |
8358dcee | 1848 | pages_addr = ttm->dma_address; |
9ab21462 | 1849 | } |
ec681545 | 1850 | exclusive = reservation_object_get_excl(bo->tbo.resv); |
d38ceaf9 AD |
1851 | } |
1852 | ||
457e0fee | 1853 | if (bo) |
ec681545 | 1854 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
457e0fee | 1855 | else |
a5f6b5b1 | 1856 | flags = 0x0; |
d38ceaf9 | 1857 | |
4e55eb38 CK |
1858 | if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) |
1859 | last_update = &vm->last_update; | |
1860 | else | |
1861 | last_update = &bo_va->last_pt_update; | |
1862 | ||
3d7d4d3a CK |
1863 | if (!clear && bo_va->base.moved) { |
1864 | bo_va->base.moved = false; | |
7fc11959 | 1865 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1866 | |
cb7b6ec2 CK |
1867 | } else if (bo_va->cleared != clear) { |
1868 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1869 | } |
7fc11959 CK |
1870 | |
1871 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
457e0fee | 1872 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
63e0ba40 | 1873 | mapping, flags, nodes, |
4e55eb38 | 1874 | last_update); |
d38ceaf9 AD |
1875 | if (r) |
1876 | return r; | |
1877 | } | |
1878 | ||
cb7b6ec2 CK |
1879 | if (vm->use_cpu_for_update) { |
1880 | /* Flush HDP */ | |
1881 | mb(); | |
1882 | amdgpu_gart_flush_gpu_tlb(adev, 0); | |
d6c10f6b CK |
1883 | } |
1884 | ||
d38ceaf9 | 1885 | spin_lock(&vm->status_lock); |
ec681545 | 1886 | list_del_init(&bo_va->base.vm_status); |
d38ceaf9 AD |
1887 | spin_unlock(&vm->status_lock); |
1888 | ||
cb7b6ec2 CK |
1889 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1890 | bo_va->cleared = clear; | |
1891 | ||
1892 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1893 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1894 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1895 | } |
1896 | ||
d38ceaf9 AD |
1897 | return 0; |
1898 | } | |
1899 | ||
284710fa CK |
1900 | /** |
1901 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1902 | */ | |
1903 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1904 | { | |
1905 | unsigned long flags; | |
1906 | bool enable; | |
1907 | ||
1908 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1909 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
284710fa CK |
1910 | adev->gart.gart_funcs->set_prt(adev, enable); |
1911 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
1912 | } | |
1913 | ||
451bc8eb | 1914 | /** |
4388fc2a | 1915 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1916 | */ |
1917 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1918 | { | |
4388fc2a CK |
1919 | if (!adev->gart.gart_funcs->set_prt) |
1920 | return; | |
1921 | ||
451bc8eb CK |
1922 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1923 | amdgpu_vm_update_prt_state(adev); | |
1924 | } | |
1925 | ||
0b15f2fc CK |
1926 | /** |
1927 | * amdgpu_vm_prt_put - drop a PRT user | |
1928 | */ | |
1929 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1930 | { | |
451bc8eb | 1931 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1932 | amdgpu_vm_update_prt_state(adev); |
1933 | } | |
1934 | ||
284710fa | 1935 | /** |
451bc8eb | 1936 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1937 | */ |
1938 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1939 | { | |
1940 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1941 | ||
0b15f2fc | 1942 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1943 | kfree(cb); |
1944 | } | |
1945 | ||
451bc8eb CK |
1946 | /** |
1947 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1948 | */ | |
1949 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1950 | struct dma_fence *fence) | |
1951 | { | |
4388fc2a | 1952 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1953 | |
4388fc2a CK |
1954 | if (!adev->gart.gart_funcs->set_prt) |
1955 | return; | |
1956 | ||
1957 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1958 | if (!cb) { |
1959 | /* Last resort when we are OOM */ | |
1960 | if (fence) | |
1961 | dma_fence_wait(fence, false); | |
1962 | ||
486a68f5 | 1963 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1964 | } else { |
1965 | cb->adev = adev; | |
1966 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1967 | amdgpu_vm_prt_cb)) | |
1968 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1969 | } | |
1970 | } | |
1971 | ||
284710fa CK |
1972 | /** |
1973 | * amdgpu_vm_free_mapping - free a mapping | |
1974 | * | |
1975 | * @adev: amdgpu_device pointer | |
1976 | * @vm: requested vm | |
1977 | * @mapping: mapping to be freed | |
1978 | * @fence: fence of the unmap operation | |
1979 | * | |
1980 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1981 | */ | |
1982 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1983 | struct amdgpu_vm *vm, | |
1984 | struct amdgpu_bo_va_mapping *mapping, | |
1985 | struct dma_fence *fence) | |
1986 | { | |
451bc8eb CK |
1987 | if (mapping->flags & AMDGPU_PTE_PRT) |
1988 | amdgpu_vm_add_prt_cb(adev, fence); | |
1989 | kfree(mapping); | |
1990 | } | |
284710fa | 1991 | |
451bc8eb CK |
1992 | /** |
1993 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1994 | * | |
1995 | * @adev: amdgpu_device pointer | |
1996 | * @vm: requested vm | |
1997 | * | |
1998 | * Register a cleanup callback to disable PRT support after VM dies. | |
1999 | */ | |
2000 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2001 | { | |
3f3333f8 | 2002 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
451bc8eb CK |
2003 | struct dma_fence *excl, **shared; |
2004 | unsigned i, shared_count; | |
2005 | int r; | |
0b15f2fc | 2006 | |
451bc8eb CK |
2007 | r = reservation_object_get_fences_rcu(resv, &excl, |
2008 | &shared_count, &shared); | |
2009 | if (r) { | |
2010 | /* Not enough memory to grab the fence list, as last resort | |
2011 | * block for all the fences to complete. | |
2012 | */ | |
2013 | reservation_object_wait_timeout_rcu(resv, true, false, | |
2014 | MAX_SCHEDULE_TIMEOUT); | |
2015 | return; | |
284710fa | 2016 | } |
451bc8eb CK |
2017 | |
2018 | /* Add a callback for each fence in the reservation object */ | |
2019 | amdgpu_vm_prt_get(adev); | |
2020 | amdgpu_vm_add_prt_cb(adev, excl); | |
2021 | ||
2022 | for (i = 0; i < shared_count; ++i) { | |
2023 | amdgpu_vm_prt_get(adev); | |
2024 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
2025 | } | |
2026 | ||
2027 | kfree(shared); | |
284710fa CK |
2028 | } |
2029 | ||
d38ceaf9 AD |
2030 | /** |
2031 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
2032 | * | |
2033 | * @adev: amdgpu_device pointer | |
2034 | * @vm: requested vm | |
f3467818 NH |
2035 | * @fence: optional resulting fence (unchanged if no work needed to be done |
2036 | * or if an error occurred) | |
d38ceaf9 AD |
2037 | * |
2038 | * Make sure all freed BOs are cleared in the PT. | |
2039 | * Returns 0 for success. | |
2040 | * | |
2041 | * PTs have to be reserved and mutex must be locked! | |
2042 | */ | |
2043 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
2044 | struct amdgpu_vm *vm, |
2045 | struct dma_fence **fence) | |
d38ceaf9 AD |
2046 | { |
2047 | struct amdgpu_bo_va_mapping *mapping; | |
f3467818 | 2048 | struct dma_fence *f = NULL; |
d38ceaf9 | 2049 | int r; |
51ac7eec | 2050 | uint64_t init_pte_value = 0; |
d38ceaf9 AD |
2051 | |
2052 | while (!list_empty(&vm->freed)) { | |
2053 | mapping = list_first_entry(&vm->freed, | |
2054 | struct amdgpu_bo_va_mapping, list); | |
2055 | list_del(&mapping->list); | |
e17841b9 | 2056 | |
51ac7eec | 2057 | if (vm->pte_support_ats) |
6d16dac8 | 2058 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec | 2059 | |
570144c6 | 2060 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, |
fc6aa33d | 2061 | mapping->start, mapping->last, |
51ac7eec | 2062 | init_pte_value, 0, &f); |
f3467818 | 2063 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 2064 | if (r) { |
f3467818 | 2065 | dma_fence_put(f); |
d38ceaf9 | 2066 | return r; |
284710fa | 2067 | } |
f3467818 | 2068 | } |
d38ceaf9 | 2069 | |
f3467818 NH |
2070 | if (fence && f) { |
2071 | dma_fence_put(*fence); | |
2072 | *fence = f; | |
2073 | } else { | |
2074 | dma_fence_put(f); | |
d38ceaf9 | 2075 | } |
f3467818 | 2076 | |
d38ceaf9 AD |
2077 | return 0; |
2078 | ||
2079 | } | |
2080 | ||
2081 | /** | |
73fb16e7 | 2082 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
2083 | * |
2084 | * @adev: amdgpu_device pointer | |
2085 | * @vm: requested vm | |
73fb16e7 | 2086 | * @sync: sync object to add fences to |
d38ceaf9 | 2087 | * |
73fb16e7 | 2088 | * Make sure all BOs which are moved are updated in the PTs. |
d38ceaf9 AD |
2089 | * Returns 0 for success. |
2090 | * | |
73fb16e7 | 2091 | * PTs have to be reserved! |
d38ceaf9 | 2092 | */ |
73fb16e7 | 2093 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 2094 | struct amdgpu_vm *vm) |
d38ceaf9 | 2095 | { |
73fb16e7 | 2096 | bool clear; |
91e1a520 | 2097 | int r = 0; |
d38ceaf9 AD |
2098 | |
2099 | spin_lock(&vm->status_lock); | |
27c7b9ae | 2100 | while (!list_empty(&vm->moved)) { |
4e55eb38 CK |
2101 | struct amdgpu_bo_va *bo_va; |
2102 | ||
27c7b9ae | 2103 | bo_va = list_first_entry(&vm->moved, |
ec681545 | 2104 | struct amdgpu_bo_va, base.vm_status); |
d38ceaf9 | 2105 | spin_unlock(&vm->status_lock); |
32b41ac2 | 2106 | |
73fb16e7 CK |
2107 | /* Per VM BOs never need to bo cleared in the page tables */ |
2108 | clear = bo_va->base.bo->tbo.resv != vm->root.base.bo->tbo.resv; | |
2109 | ||
2110 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
d38ceaf9 AD |
2111 | if (r) |
2112 | return r; | |
2113 | ||
2114 | spin_lock(&vm->status_lock); | |
2115 | } | |
2116 | spin_unlock(&vm->status_lock); | |
2117 | ||
91e1a520 | 2118 | return r; |
d38ceaf9 AD |
2119 | } |
2120 | ||
2121 | /** | |
2122 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
2123 | * | |
2124 | * @adev: amdgpu_device pointer | |
2125 | * @vm: requested vm | |
2126 | * @bo: amdgpu buffer object | |
2127 | * | |
8843dbbb | 2128 | * Add @bo into the requested vm. |
d38ceaf9 AD |
2129 | * Add @bo to the list of bos associated with the vm |
2130 | * Returns newly added bo_va or NULL for failure | |
2131 | * | |
2132 | * Object has to be reserved! | |
2133 | */ | |
2134 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
2135 | struct amdgpu_vm *vm, | |
2136 | struct amdgpu_bo *bo) | |
2137 | { | |
2138 | struct amdgpu_bo_va *bo_va; | |
2139 | ||
2140 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2141 | if (bo_va == NULL) { | |
2142 | return NULL; | |
2143 | } | |
ec681545 CK |
2144 | bo_va->base.vm = vm; |
2145 | bo_va->base.bo = bo; | |
2146 | INIT_LIST_HEAD(&bo_va->base.bo_list); | |
2147 | INIT_LIST_HEAD(&bo_va->base.vm_status); | |
2148 | ||
d38ceaf9 | 2149 | bo_va->ref_count = 1; |
7fc11959 CK |
2150 | INIT_LIST_HEAD(&bo_va->valids); |
2151 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2152 | |
a5f6b5b1 | 2153 | if (bo) |
ec681545 | 2154 | list_add_tail(&bo_va->base.bo_list, &bo->va); |
d38ceaf9 AD |
2155 | |
2156 | return bo_va; | |
2157 | } | |
2158 | ||
73fb16e7 CK |
2159 | |
2160 | /** | |
2161 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
2162 | * | |
2163 | * @adev: amdgpu_device pointer | |
2164 | * @bo_va: bo_va to store the address | |
2165 | * @mapping: the mapping to insert | |
2166 | * | |
2167 | * Insert a new mapping into all structures. | |
2168 | */ | |
2169 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2170 | struct amdgpu_bo_va *bo_va, | |
2171 | struct amdgpu_bo_va_mapping *mapping) | |
2172 | { | |
2173 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2174 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2175 | ||
aebc5e6f | 2176 | mapping->bo_va = bo_va; |
73fb16e7 CK |
2177 | list_add(&mapping->list, &bo_va->invalids); |
2178 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2179 | ||
2180 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2181 | amdgpu_vm_prt_get(adev); | |
2182 | ||
2183 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { | |
2184 | spin_lock(&vm->status_lock); | |
481c2e94 CK |
2185 | if (list_empty(&bo_va->base.vm_status)) |
2186 | list_add(&bo_va->base.vm_status, &vm->moved); | |
73fb16e7 CK |
2187 | spin_unlock(&vm->status_lock); |
2188 | } | |
2189 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2190 | } | |
2191 | ||
d38ceaf9 AD |
2192 | /** |
2193 | * amdgpu_vm_bo_map - map bo inside a vm | |
2194 | * | |
2195 | * @adev: amdgpu_device pointer | |
2196 | * @bo_va: bo_va to store the address | |
2197 | * @saddr: where to map the BO | |
2198 | * @offset: requested offset in the BO | |
2199 | * @flags: attributes of pages (read/write/valid/etc.) | |
2200 | * | |
2201 | * Add a mapping of the BO at the specefied addr into the VM. | |
2202 | * Returns 0 for success, error for failure. | |
2203 | * | |
49b02b18 | 2204 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2205 | */ |
2206 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2207 | struct amdgpu_bo_va *bo_va, | |
2208 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2209 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2210 | { |
a9f87f64 | 2211 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2212 | struct amdgpu_bo *bo = bo_va->base.bo; |
2213 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2214 | uint64_t eaddr; |
d38ceaf9 | 2215 | |
0be52de9 CK |
2216 | /* validate the parameters */ |
2217 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2218 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2219 | return -EINVAL; |
0be52de9 | 2220 | |
d38ceaf9 | 2221 | /* make sure object fit at this offset */ |
005ae95e | 2222 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2223 | if (saddr >= eaddr || |
ec681545 | 2224 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 2225 | return -EINVAL; |
d38ceaf9 | 2226 | |
d38ceaf9 AD |
2227 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2228 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2229 | ||
a9f87f64 CK |
2230 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2231 | if (tmp) { | |
d38ceaf9 AD |
2232 | /* bo and tmp overlap, invalid addr */ |
2233 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2234 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2235 | tmp->start, tmp->last + 1); |
663e4577 | 2236 | return -EINVAL; |
d38ceaf9 AD |
2237 | } |
2238 | ||
2239 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2240 | if (!mapping) |
2241 | return -ENOMEM; | |
d38ceaf9 | 2242 | |
a9f87f64 CK |
2243 | mapping->start = saddr; |
2244 | mapping->last = eaddr; | |
d38ceaf9 AD |
2245 | mapping->offset = offset; |
2246 | mapping->flags = flags; | |
2247 | ||
73fb16e7 | 2248 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
2249 | |
2250 | return 0; | |
2251 | } | |
2252 | ||
2253 | /** | |
2254 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2255 | * | |
2256 | * @adev: amdgpu_device pointer | |
2257 | * @bo_va: bo_va to store the address | |
2258 | * @saddr: where to map the BO | |
2259 | * @offset: requested offset in the BO | |
2260 | * @flags: attributes of pages (read/write/valid/etc.) | |
2261 | * | |
2262 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2263 | * mappings as we do so. | |
2264 | * Returns 0 for success, error for failure. | |
2265 | * | |
2266 | * Object has to be reserved and unreserved outside! | |
2267 | */ | |
2268 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2269 | struct amdgpu_bo_va *bo_va, | |
2270 | uint64_t saddr, uint64_t offset, | |
2271 | uint64_t size, uint64_t flags) | |
2272 | { | |
2273 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2274 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
2275 | uint64_t eaddr; |
2276 | int r; | |
2277 | ||
2278 | /* validate the parameters */ | |
2279 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2280 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2281 | return -EINVAL; | |
2282 | ||
2283 | /* make sure object fit at this offset */ | |
2284 | eaddr = saddr + size - 1; | |
2285 | if (saddr >= eaddr || | |
ec681545 | 2286 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
2287 | return -EINVAL; |
2288 | ||
2289 | /* Allocate all the needed memory */ | |
2290 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2291 | if (!mapping) | |
2292 | return -ENOMEM; | |
2293 | ||
ec681545 | 2294 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2295 | if (r) { |
2296 | kfree(mapping); | |
2297 | return r; | |
2298 | } | |
2299 | ||
2300 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2301 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2302 | ||
a9f87f64 CK |
2303 | mapping->start = saddr; |
2304 | mapping->last = eaddr; | |
80f95c57 CK |
2305 | mapping->offset = offset; |
2306 | mapping->flags = flags; | |
2307 | ||
73fb16e7 | 2308 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 2309 | |
d38ceaf9 | 2310 | return 0; |
d38ceaf9 AD |
2311 | } |
2312 | ||
2313 | /** | |
2314 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2315 | * | |
2316 | * @adev: amdgpu_device pointer | |
2317 | * @bo_va: bo_va to remove the address from | |
2318 | * @saddr: where to the BO is mapped | |
2319 | * | |
2320 | * Remove a mapping of the BO at the specefied addr from the VM. | |
2321 | * Returns 0 for success, error for failure. | |
2322 | * | |
49b02b18 | 2323 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2324 | */ |
2325 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2326 | struct amdgpu_bo_va *bo_va, | |
2327 | uint64_t saddr) | |
2328 | { | |
2329 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2330 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2331 | bool valid = true; |
d38ceaf9 | 2332 | |
6c7fc503 | 2333 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2334 | |
7fc11959 | 2335 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2336 | if (mapping->start == saddr) |
d38ceaf9 AD |
2337 | break; |
2338 | } | |
2339 | ||
7fc11959 CK |
2340 | if (&mapping->list == &bo_va->valids) { |
2341 | valid = false; | |
2342 | ||
2343 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2344 | if (mapping->start == saddr) |
7fc11959 CK |
2345 | break; |
2346 | } | |
2347 | ||
32b41ac2 | 2348 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2349 | return -ENOENT; |
d38ceaf9 | 2350 | } |
32b41ac2 | 2351 | |
d38ceaf9 | 2352 | list_del(&mapping->list); |
a9f87f64 | 2353 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2354 | mapping->bo_va = NULL; |
93e3e438 | 2355 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2356 | |
e17841b9 | 2357 | if (valid) |
d38ceaf9 | 2358 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2359 | else |
284710fa CK |
2360 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2361 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2362 | |
2363 | return 0; | |
2364 | } | |
2365 | ||
dc54d3d1 CK |
2366 | /** |
2367 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2368 | * | |
2369 | * @adev: amdgpu_device pointer | |
2370 | * @vm: VM structure to use | |
2371 | * @saddr: start of the range | |
2372 | * @size: size of the range | |
2373 | * | |
2374 | * Remove all mappings in a range, split them as appropriate. | |
2375 | * Returns 0 for success, error for failure. | |
2376 | */ | |
2377 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2378 | struct amdgpu_vm *vm, | |
2379 | uint64_t saddr, uint64_t size) | |
2380 | { | |
2381 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2382 | LIST_HEAD(removed); |
2383 | uint64_t eaddr; | |
2384 | ||
2385 | eaddr = saddr + size - 1; | |
2386 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2387 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2388 | ||
2389 | /* Allocate all the needed memory */ | |
2390 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2391 | if (!before) | |
2392 | return -ENOMEM; | |
27f6d610 | 2393 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2394 | |
2395 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2396 | if (!after) { | |
2397 | kfree(before); | |
2398 | return -ENOMEM; | |
2399 | } | |
27f6d610 | 2400 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2401 | |
2402 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2403 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2404 | while (tmp) { | |
dc54d3d1 | 2405 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2406 | if (tmp->start < saddr) { |
2407 | before->start = tmp->start; | |
2408 | before->last = saddr - 1; | |
dc54d3d1 CK |
2409 | before->offset = tmp->offset; |
2410 | before->flags = tmp->flags; | |
2411 | list_add(&before->list, &tmp->list); | |
2412 | } | |
2413 | ||
2414 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2415 | if (tmp->last > eaddr) { |
2416 | after->start = eaddr + 1; | |
2417 | after->last = tmp->last; | |
dc54d3d1 | 2418 | after->offset = tmp->offset; |
a9f87f64 | 2419 | after->offset += after->start - tmp->start; |
dc54d3d1 CK |
2420 | after->flags = tmp->flags; |
2421 | list_add(&after->list, &tmp->list); | |
2422 | } | |
2423 | ||
2424 | list_del(&tmp->list); | |
2425 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2426 | |
2427 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2428 | } |
2429 | ||
2430 | /* And free them up */ | |
2431 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2432 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2433 | list_del(&tmp->list); |
2434 | ||
a9f87f64 CK |
2435 | if (tmp->start < saddr) |
2436 | tmp->start = saddr; | |
2437 | if (tmp->last > eaddr) | |
2438 | tmp->last = eaddr; | |
dc54d3d1 | 2439 | |
aebc5e6f | 2440 | tmp->bo_va = NULL; |
dc54d3d1 CK |
2441 | list_add(&tmp->list, &vm->freed); |
2442 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2443 | } | |
2444 | ||
27f6d610 JZ |
2445 | /* Insert partial mapping before the range */ |
2446 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2447 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2448 | if (before->flags & AMDGPU_PTE_PRT) |
2449 | amdgpu_vm_prt_get(adev); | |
2450 | } else { | |
2451 | kfree(before); | |
2452 | } | |
2453 | ||
2454 | /* Insert partial mapping after the range */ | |
27f6d610 | 2455 | if (!list_empty(&after->list)) { |
a9f87f64 | 2456 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2457 | if (after->flags & AMDGPU_PTE_PRT) |
2458 | amdgpu_vm_prt_get(adev); | |
2459 | } else { | |
2460 | kfree(after); | |
2461 | } | |
2462 | ||
2463 | return 0; | |
2464 | } | |
2465 | ||
aebc5e6f CK |
2466 | /** |
2467 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2468 | * | |
2469 | * @vm: the requested VM | |
2470 | * | |
2471 | * Find a mapping by it's address. | |
2472 | */ | |
2473 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2474 | uint64_t addr) | |
2475 | { | |
2476 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2477 | } | |
2478 | ||
d38ceaf9 AD |
2479 | /** |
2480 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2481 | * | |
2482 | * @adev: amdgpu_device pointer | |
2483 | * @bo_va: requested bo_va | |
2484 | * | |
8843dbbb | 2485 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2486 | * |
2487 | * Object have to be reserved! | |
2488 | */ | |
2489 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2490 | struct amdgpu_bo_va *bo_va) | |
2491 | { | |
2492 | struct amdgpu_bo_va_mapping *mapping, *next; | |
ec681545 | 2493 | struct amdgpu_vm *vm = bo_va->base.vm; |
d38ceaf9 | 2494 | |
ec681545 | 2495 | list_del(&bo_va->base.bo_list); |
d38ceaf9 | 2496 | |
d38ceaf9 | 2497 | spin_lock(&vm->status_lock); |
ec681545 | 2498 | list_del(&bo_va->base.vm_status); |
d38ceaf9 AD |
2499 | spin_unlock(&vm->status_lock); |
2500 | ||
7fc11959 | 2501 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2502 | list_del(&mapping->list); |
a9f87f64 | 2503 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2504 | mapping->bo_va = NULL; |
93e3e438 | 2505 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2506 | list_add(&mapping->list, &vm->freed); |
2507 | } | |
2508 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2509 | list_del(&mapping->list); | |
a9f87f64 | 2510 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2511 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2512 | bo_va->last_pt_update); | |
d38ceaf9 | 2513 | } |
32b41ac2 | 2514 | |
f54d1867 | 2515 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2516 | kfree(bo_va); |
d38ceaf9 AD |
2517 | } |
2518 | ||
2519 | /** | |
2520 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2521 | * | |
2522 | * @adev: amdgpu_device pointer | |
2523 | * @vm: requested vm | |
2524 | * @bo: amdgpu buffer object | |
2525 | * | |
8843dbbb | 2526 | * Mark @bo as invalid. |
d38ceaf9 AD |
2527 | */ |
2528 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2529 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2530 | { |
ec681545 CK |
2531 | struct amdgpu_vm_bo_base *bo_base; |
2532 | ||
2533 | list_for_each_entry(bo_base, &bo->va, bo_list) { | |
3f3333f8 CK |
2534 | struct amdgpu_vm *vm = bo_base->vm; |
2535 | ||
3d7d4d3a | 2536 | bo_base->moved = true; |
3f3333f8 CK |
2537 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
2538 | spin_lock(&bo_base->vm->status_lock); | |
73fb16e7 CK |
2539 | if (bo->tbo.type == ttm_bo_type_kernel) |
2540 | list_move(&bo_base->vm_status, &vm->evicted); | |
2541 | else | |
2542 | list_move_tail(&bo_base->vm_status, | |
2543 | &vm->evicted); | |
3f3333f8 CK |
2544 | spin_unlock(&bo_base->vm->status_lock); |
2545 | continue; | |
2546 | } | |
2547 | ||
ea09729c CK |
2548 | if (bo->tbo.type == ttm_bo_type_kernel) { |
2549 | spin_lock(&bo_base->vm->status_lock); | |
2550 | if (list_empty(&bo_base->vm_status)) | |
2551 | list_add(&bo_base->vm_status, &vm->relocated); | |
2552 | spin_unlock(&bo_base->vm->status_lock); | |
3f3333f8 | 2553 | continue; |
ea09729c | 2554 | } |
3f3333f8 | 2555 | |
ec681545 CK |
2556 | spin_lock(&bo_base->vm->status_lock); |
2557 | if (list_empty(&bo_base->vm_status)) | |
481c2e94 | 2558 | list_add(&bo_base->vm_status, &vm->moved); |
ec681545 | 2559 | spin_unlock(&bo_base->vm->status_lock); |
d38ceaf9 AD |
2560 | } |
2561 | } | |
2562 | ||
bab4fee7 JZ |
2563 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2564 | { | |
2565 | /* Total bits covered by PD + PTs */ | |
2566 | unsigned bits = ilog2(vm_size) + 18; | |
2567 | ||
2568 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2569 | Above that split equal between PD and PTs */ | |
2570 | if (vm_size <= 8) | |
2571 | return (bits - 9); | |
2572 | else | |
2573 | return ((bits + 3) / 2); | |
2574 | } | |
2575 | ||
2576 | /** | |
d07f14be RH |
2577 | * amdgpu_vm_set_fragment_size - adjust fragment size in PTE |
2578 | * | |
2579 | * @adev: amdgpu_device pointer | |
2580 | * @fragment_size_default: the default fragment size if it's set auto | |
2581 | */ | |
c38e0691 CK |
2582 | void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, |
2583 | uint32_t fragment_size_default) | |
d07f14be RH |
2584 | { |
2585 | if (amdgpu_vm_fragment_size == -1) | |
2586 | adev->vm_manager.fragment_size = fragment_size_default; | |
2587 | else | |
2588 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
2589 | } | |
2590 | ||
2591 | /** | |
2592 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2593 | * |
2594 | * @adev: amdgpu_device pointer | |
2595 | * @vm_size: the default vm size if it's set auto | |
2596 | */ | |
fdd5faaa | 2597 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, |
c38e0691 | 2598 | uint32_t fragment_size_default) |
bab4fee7 JZ |
2599 | { |
2600 | /* adjust vm size firstly */ | |
fdd5faaa CK |
2601 | if (amdgpu_vm_size != -1) |
2602 | vm_size = amdgpu_vm_size; | |
2603 | ||
2604 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
bab4fee7 JZ |
2605 | |
2606 | /* block size depends on vm size */ | |
2607 | if (amdgpu_vm_block_size == -1) | |
2608 | adev->vm_manager.block_size = | |
fdd5faaa | 2609 | amdgpu_vm_get_block_size(vm_size); |
bab4fee7 JZ |
2610 | else |
2611 | adev->vm_manager.block_size = amdgpu_vm_block_size; | |
2612 | ||
d07f14be RH |
2613 | amdgpu_vm_set_fragment_size(adev, fragment_size_default); |
2614 | ||
fdd5faaa CK |
2615 | DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n", |
2616 | vm_size, adev->vm_manager.block_size, | |
2617 | adev->vm_manager.fragment_size); | |
bab4fee7 JZ |
2618 | } |
2619 | ||
d38ceaf9 AD |
2620 | /** |
2621 | * amdgpu_vm_init - initialize a vm instance | |
2622 | * | |
2623 | * @adev: amdgpu_device pointer | |
2624 | * @vm: requested vm | |
9a4b7d4c | 2625 | * @vm_context: Indicates if it GFX or Compute context |
d38ceaf9 | 2626 | * |
8843dbbb | 2627 | * Init @vm fields. |
d38ceaf9 | 2628 | */ |
9a4b7d4c | 2629 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 2630 | int vm_context, unsigned int pasid) |
d38ceaf9 AD |
2631 | { |
2632 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
36b32a68 | 2633 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2634 | unsigned ring_instance; |
2635 | struct amdgpu_ring *ring; | |
2bd9ccfa | 2636 | struct amd_sched_rq *rq; |
36bbf3bf | 2637 | int r, i; |
3c824172 | 2638 | u64 flags; |
51ac7eec | 2639 | uint64_t init_pde_value = 0; |
d38ceaf9 | 2640 | |
f808c13f | 2641 | vm->va = RB_ROOT_CACHED; |
031e2983 | 2642 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
36bbf3bf CZ |
2643 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2644 | vm->reserved_vmid[i] = NULL; | |
d38ceaf9 | 2645 | spin_lock_init(&vm->status_lock); |
3f3333f8 | 2646 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2647 | INIT_LIST_HEAD(&vm->relocated); |
27c7b9ae | 2648 | INIT_LIST_HEAD(&vm->moved); |
d38ceaf9 | 2649 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2650 | |
2bd9ccfa | 2651 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2652 | |
2653 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2654 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2655 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
2656 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
2657 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
b3eebe3d | 2658 | rq, amdgpu_sched_jobs, NULL); |
2bd9ccfa | 2659 | if (r) |
f566ceb1 | 2660 | return r; |
2bd9ccfa | 2661 | |
51ac7eec YZ |
2662 | vm->pte_support_ats = false; |
2663 | ||
2664 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2665 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2666 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec YZ |
2667 | |
2668 | if (adev->asic_type == CHIP_RAVEN) { | |
2669 | vm->pte_support_ats = true; | |
6d16dac8 YZ |
2670 | init_pde_value = AMDGPU_PTE_DEFAULT_ATC |
2671 | | AMDGPU_PDE_PTE; | |
2672 | ||
51ac7eec YZ |
2673 | } |
2674 | } else | |
9a4b7d4c HK |
2675 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2676 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
2677 | DRM_DEBUG_DRIVER("VM update mode is %s\n", | |
2678 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
2679 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), | |
2680 | "CPU update of VM recommended only for large BAR system\n"); | |
d5884513 | 2681 | vm->last_update = NULL; |
05906dec | 2682 | |
3c824172 HK |
2683 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
2684 | AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
2685 | if (vm->use_cpu_for_update) | |
2686 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
2687 | else | |
2688 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
2689 | AMDGPU_GEM_CREATE_SHADOW); | |
2690 | ||
f566ceb1 | 2691 | r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, |
857d913d | 2692 | AMDGPU_GEM_DOMAIN_VRAM, |
3c824172 | 2693 | flags, |
3f3333f8 | 2694 | NULL, NULL, init_pde_value, &vm->root.base.bo); |
d38ceaf9 | 2695 | if (r) |
2bd9ccfa CK |
2696 | goto error_free_sched_entity; |
2697 | ||
3f3333f8 CK |
2698 | vm->root.base.vm = vm; |
2699 | list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va); | |
2700 | INIT_LIST_HEAD(&vm->root.base.vm_status); | |
0a096fb6 CK |
2701 | |
2702 | if (vm->use_cpu_for_update) { | |
3f3333f8 | 2703 | r = amdgpu_bo_reserve(vm->root.base.bo, false); |
0a096fb6 CK |
2704 | if (r) |
2705 | goto error_free_root; | |
0a096fb6 | 2706 | |
3f3333f8 | 2707 | r = amdgpu_bo_kmap(vm->root.base.bo, NULL); |
ca290da8 | 2708 | amdgpu_bo_unreserve(vm->root.base.bo); |
3f3333f8 CK |
2709 | if (r) |
2710 | goto error_free_root; | |
3f3333f8 | 2711 | } |
d38ceaf9 | 2712 | |
02208441 FK |
2713 | if (pasid) { |
2714 | unsigned long flags; | |
2715 | ||
2716 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2717 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2718 | GFP_ATOMIC); | |
2719 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2720 | if (r < 0) | |
2721 | goto error_free_root; | |
2722 | ||
2723 | vm->pasid = pasid; | |
0a096fb6 CK |
2724 | } |
2725 | ||
a2f14820 | 2726 | INIT_KFIFO(vm->faults); |
c98171cc | 2727 | vm->fault_credit = 16; |
d38ceaf9 AD |
2728 | |
2729 | return 0; | |
2bd9ccfa | 2730 | |
67003a15 | 2731 | error_free_root: |
3f3333f8 CK |
2732 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2733 | amdgpu_bo_unref(&vm->root.base.bo); | |
2734 | vm->root.base.bo = NULL; | |
2bd9ccfa CK |
2735 | |
2736 | error_free_sched_entity: | |
2737 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
2738 | ||
2739 | return r; | |
d38ceaf9 AD |
2740 | } |
2741 | ||
f566ceb1 CK |
2742 | /** |
2743 | * amdgpu_vm_free_levels - free PD/PT levels | |
2744 | * | |
2745 | * @level: PD/PT starting level to free | |
2746 | * | |
2747 | * Free the page directory or page table level and all sub levels. | |
2748 | */ | |
2749 | static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) | |
2750 | { | |
2751 | unsigned i; | |
2752 | ||
3f3333f8 CK |
2753 | if (level->base.bo) { |
2754 | list_del(&level->base.bo_list); | |
2755 | list_del(&level->base.vm_status); | |
2756 | amdgpu_bo_unref(&level->base.bo->shadow); | |
2757 | amdgpu_bo_unref(&level->base.bo); | |
f566ceb1 CK |
2758 | } |
2759 | ||
2760 | if (level->entries) | |
2761 | for (i = 0; i <= level->last_entry_used; i++) | |
2762 | amdgpu_vm_free_levels(&level->entries[i]); | |
2763 | ||
2098105e | 2764 | kvfree(level->entries); |
f566ceb1 CK |
2765 | } |
2766 | ||
d38ceaf9 AD |
2767 | /** |
2768 | * amdgpu_vm_fini - tear down a vm instance | |
2769 | * | |
2770 | * @adev: amdgpu_device pointer | |
2771 | * @vm: requested vm | |
2772 | * | |
8843dbbb | 2773 | * Tear down @vm. |
d38ceaf9 AD |
2774 | * Unbind the VM and remove all bos from the vm bo list |
2775 | */ | |
2776 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2777 | { | |
2778 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
4388fc2a | 2779 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
2642cf11 | 2780 | struct amdgpu_bo *root; |
a2f14820 | 2781 | u64 fault; |
2642cf11 | 2782 | int i, r; |
d38ceaf9 | 2783 | |
a2f14820 FK |
2784 | /* Clear pending page faults from IH when the VM is destroyed */ |
2785 | while (kfifo_get(&vm->faults, &fault)) | |
2786 | amdgpu_ih_clear_fault(adev, fault); | |
2787 | ||
02208441 FK |
2788 | if (vm->pasid) { |
2789 | unsigned long flags; | |
2790 | ||
2791 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2792 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2793 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2794 | } | |
2795 | ||
2d55e45a | 2796 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 2797 | |
f808c13f | 2798 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
d38ceaf9 AD |
2799 | dev_err(adev->dev, "still active bo inside vm\n"); |
2800 | } | |
f808c13f DB |
2801 | rbtree_postorder_for_each_entry_safe(mapping, tmp, |
2802 | &vm->va.rb_root, rb) { | |
d38ceaf9 | 2803 | list_del(&mapping->list); |
a9f87f64 | 2804 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2805 | kfree(mapping); |
2806 | } | |
2807 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2808 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2809 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2810 | prt_fini_needed = false; |
451bc8eb | 2811 | } |
284710fa | 2812 | |
d38ceaf9 | 2813 | list_del(&mapping->list); |
451bc8eb | 2814 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2815 | } |
2816 | ||
2642cf11 CK |
2817 | root = amdgpu_bo_ref(vm->root.base.bo); |
2818 | r = amdgpu_bo_reserve(root, true); | |
2819 | if (r) { | |
2820 | dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); | |
2821 | } else { | |
2822 | amdgpu_vm_free_levels(&vm->root); | |
2823 | amdgpu_bo_unreserve(root); | |
2824 | } | |
2825 | amdgpu_bo_unref(&root); | |
d5884513 | 2826 | dma_fence_put(vm->last_update); |
1e9ef26f CZ |
2827 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2828 | amdgpu_vm_free_reserved_vmid(adev, vm, i); | |
d38ceaf9 | 2829 | } |
ea89f8c9 | 2830 | |
c98171cc FK |
2831 | /** |
2832 | * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID | |
2833 | * | |
2834 | * @adev: amdgpu_device pointer | |
2835 | * @pasid: PASID do identify the VM | |
2836 | * | |
2837 | * This function is expected to be called in interrupt context. Returns | |
2838 | * true if there was fault credit, false otherwise | |
2839 | */ | |
2840 | bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, | |
2841 | unsigned int pasid) | |
2842 | { | |
2843 | struct amdgpu_vm *vm; | |
2844 | ||
2845 | spin_lock(&adev->vm_manager.pasid_lock); | |
2846 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
2847 | spin_unlock(&adev->vm_manager.pasid_lock); | |
2848 | if (!vm) | |
2849 | /* VM not found, can't track fault credit */ | |
2850 | return true; | |
2851 | ||
2852 | /* No lock needed. only accessed by IRQ handler */ | |
2853 | if (!vm->fault_credit) | |
2854 | /* Too many faults in this VM */ | |
2855 | return false; | |
2856 | ||
2857 | vm->fault_credit--; | |
2858 | return true; | |
2859 | } | |
2860 | ||
a9a78b32 CK |
2861 | /** |
2862 | * amdgpu_vm_manager_init - init the VM manager | |
2863 | * | |
2864 | * @adev: amdgpu_device pointer | |
2865 | * | |
2866 | * Initialize the VM manager structures | |
2867 | */ | |
2868 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2869 | { | |
7645670d CK |
2870 | unsigned i, j; |
2871 | ||
2872 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
2873 | struct amdgpu_vm_id_manager *id_mgr = | |
2874 | &adev->vm_manager.id_mgr[i]; | |
a9a78b32 | 2875 | |
7645670d CK |
2876 | mutex_init(&id_mgr->lock); |
2877 | INIT_LIST_HEAD(&id_mgr->ids_lru); | |
c3505770 | 2878 | atomic_set(&id_mgr->reserved_vmid_num, 0); |
a9a78b32 | 2879 | |
7645670d CK |
2880 | /* skip over VMID 0, since it is the system VM */ |
2881 | for (j = 1; j < id_mgr->num_ids; ++j) { | |
2882 | amdgpu_vm_reset_id(adev, i, j); | |
2883 | amdgpu_sync_create(&id_mgr->ids[i].active); | |
2884 | list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); | |
2885 | } | |
971fe9a9 | 2886 | } |
2d55e45a | 2887 | |
f54d1867 CW |
2888 | adev->vm_manager.fence_context = |
2889 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2890 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2891 | adev->vm_manager.seqno[i] = 0; | |
2892 | ||
2d55e45a | 2893 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 2894 | atomic64_set(&adev->vm_manager.client_counter, 0); |
284710fa | 2895 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2896 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
2897 | |
2898 | /* If not overridden by the user, by default, only in large BAR systems | |
2899 | * Compute VM tables will be updated by CPU | |
2900 | */ | |
2901 | #ifdef CONFIG_X86_64 | |
2902 | if (amdgpu_vm_update_mode == -1) { | |
2903 | if (amdgpu_vm_is_large_bar(adev)) | |
2904 | adev->vm_manager.vm_update_mode = | |
2905 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
2906 | else | |
2907 | adev->vm_manager.vm_update_mode = 0; | |
2908 | } else | |
2909 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
2910 | #else | |
2911 | adev->vm_manager.vm_update_mode = 0; | |
2912 | #endif | |
2913 | ||
02208441 FK |
2914 | idr_init(&adev->vm_manager.pasid_idr); |
2915 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
a9a78b32 CK |
2916 | } |
2917 | ||
ea89f8c9 CK |
2918 | /** |
2919 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2920 | * | |
2921 | * @adev: amdgpu_device pointer | |
2922 | * | |
2923 | * Cleanup the VM manager and free resources. | |
2924 | */ | |
2925 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2926 | { | |
7645670d | 2927 | unsigned i, j; |
ea89f8c9 | 2928 | |
02208441 FK |
2929 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); |
2930 | idr_destroy(&adev->vm_manager.pasid_idr); | |
2931 | ||
7645670d CK |
2932 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
2933 | struct amdgpu_vm_id_manager *id_mgr = | |
2934 | &adev->vm_manager.id_mgr[i]; | |
bcb1ba35 | 2935 | |
7645670d CK |
2936 | mutex_destroy(&id_mgr->lock); |
2937 | for (j = 0; j < AMDGPU_NUM_VM; ++j) { | |
2938 | struct amdgpu_vm_id *id = &id_mgr->ids[j]; | |
2939 | ||
2940 | amdgpu_sync_free(&id->active); | |
2941 | dma_fence_put(id->flushed_updates); | |
2942 | dma_fence_put(id->last_flush); | |
2943 | } | |
bcb1ba35 | 2944 | } |
ea89f8c9 | 2945 | } |
cfbcacf4 CZ |
2946 | |
2947 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
2948 | { | |
2949 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
2950 | struct amdgpu_device *adev = dev->dev_private; |
2951 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
2952 | int r; | |
cfbcacf4 CZ |
2953 | |
2954 | switch (args->in.op) { | |
2955 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f CZ |
2956 | /* current, we only have requirement to reserve vmid from gfxhub */ |
2957 | r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm, | |
2958 | AMDGPU_GFXHUB); | |
2959 | if (r) | |
2960 | return r; | |
2961 | break; | |
cfbcacf4 | 2962 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
1e9ef26f | 2963 | amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
2964 | break; |
2965 | default: | |
2966 | return -EINVAL; | |
2967 | } | |
2968 | ||
2969 | return 0; | |
2970 | } |