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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
d38ceaf9 AD |
30 | #include <drm/drmP.h> |
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
33 | #include "amdgpu_trace.h" | |
34 | ||
35 | /* | |
36 | * GPUVM | |
37 | * GPUVM is similar to the legacy gart on older asics, however | |
38 | * rather than there being a single global gart table | |
39 | * for the entire GPU, there are multiple VM page tables active | |
40 | * at any given time. The VM page tables can contain a mix | |
41 | * vram pages and system memory pages and system memory pages | |
42 | * can be mapped as snooped (cached system pages) or unsnooped | |
43 | * (uncached system pages). | |
44 | * Each VM has an ID associated with it and there is a page table | |
45 | * associated with each VMID. When execting a command buffer, | |
46 | * the kernel tells the the ring what VMID to use for that command | |
47 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
48 | * The userspace drivers maintain their own address space and the kernel | |
49 | * sets up their pages tables accordingly when they submit their | |
50 | * command buffers and a VMID is assigned. | |
51 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
52 | * SI supports 16. | |
53 | */ | |
54 | ||
a9f87f64 CK |
55 | #define START(node) ((node)->start) |
56 | #define LAST(node) ((node)->last) | |
57 | ||
58 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
59 | START, LAST, static, amdgpu_vm_it) | |
60 | ||
61 | #undef START | |
62 | #undef LAST | |
63 | ||
f4833c4f HK |
64 | /* Local structure. Encapsulate some VM table update parameters to reduce |
65 | * the number of function parameters | |
66 | */ | |
29efc4f5 | 67 | struct amdgpu_pte_update_params { |
27c5f36f CK |
68 | /* amdgpu device we do this update for */ |
69 | struct amdgpu_device *adev; | |
49ac8a24 CK |
70 | /* optional amdgpu_vm we do this update for */ |
71 | struct amdgpu_vm *vm; | |
f4833c4f HK |
72 | /* address where to copy page table entries from */ |
73 | uint64_t src; | |
f4833c4f HK |
74 | /* indirect buffer to fill with commands */ |
75 | struct amdgpu_ib *ib; | |
afef8b8f CK |
76 | /* Function which actually does the update */ |
77 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
78 | uint64_t addr, unsigned count, uint32_t incr, | |
6b777607 | 79 | uint64_t flags); |
4c7e8855 CZ |
80 | /* indicate update pt or its shadow */ |
81 | bool shadow; | |
f4833c4f HK |
82 | }; |
83 | ||
284710fa CK |
84 | /* Helper to disable partial resident texture feature from a fence callback */ |
85 | struct amdgpu_prt_cb { | |
86 | struct amdgpu_device *adev; | |
87 | struct dma_fence_cb cb; | |
88 | }; | |
89 | ||
d38ceaf9 | 90 | /** |
72a7ec5c | 91 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
92 | * |
93 | * @adev: amdgpu_device pointer | |
94 | * | |
72a7ec5c | 95 | * Calculate the number of entries in a page directory or page table. |
d38ceaf9 | 96 | */ |
72a7ec5c CK |
97 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
98 | unsigned level) | |
d38ceaf9 | 99 | { |
72a7ec5c CK |
100 | if (level == 0) |
101 | /* For the root directory */ | |
102 | return adev->vm_manager.max_pfn >> | |
36b32a68 ZJ |
103 | (adev->vm_manager.block_size * |
104 | adev->vm_manager.num_level); | |
72a7ec5c CK |
105 | else if (level == adev->vm_manager.num_level) |
106 | /* For the page tables on the leaves */ | |
36b32a68 | 107 | return AMDGPU_VM_PTE_COUNT(adev); |
72a7ec5c CK |
108 | else |
109 | /* Everything in between */ | |
36b32a68 | 110 | return 1 << adev->vm_manager.block_size; |
d38ceaf9 AD |
111 | } |
112 | ||
113 | /** | |
72a7ec5c | 114 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
115 | * |
116 | * @adev: amdgpu_device pointer | |
117 | * | |
72a7ec5c | 118 | * Calculate the size of the BO for a page directory or page table in bytes. |
d38ceaf9 | 119 | */ |
72a7ec5c | 120 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 121 | { |
72a7ec5c | 122 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
123 | } |
124 | ||
125 | /** | |
56467ebf | 126 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
127 | * |
128 | * @vm: vm providing the BOs | |
3c0eea6c | 129 | * @validated: head of validation list |
56467ebf | 130 | * @entry: entry to add |
d38ceaf9 AD |
131 | * |
132 | * Add the page directory to the list of BOs to | |
56467ebf | 133 | * validate for command submission. |
d38ceaf9 | 134 | */ |
56467ebf CK |
135 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
136 | struct list_head *validated, | |
137 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 138 | { |
67003a15 | 139 | entry->robj = vm->root.bo; |
56467ebf | 140 | entry->priority = 0; |
67003a15 | 141 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 142 | entry->tv.shared = true; |
2f568dbd | 143 | entry->user_pages = NULL; |
56467ebf CK |
144 | list_add(&entry->tv.head, validated); |
145 | } | |
d38ceaf9 | 146 | |
670fecc8 CK |
147 | /** |
148 | * amdgpu_vm_validate_layer - validate a single page table level | |
149 | * | |
150 | * @parent: parent page table level | |
151 | * @validate: callback to do the validation | |
152 | * @param: parameter for the validation callback | |
153 | * | |
154 | * Validate the page table BOs on command submission if neccessary. | |
155 | */ | |
156 | static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent, | |
157 | int (*validate)(void *, struct amdgpu_bo *), | |
158 | void *param) | |
159 | { | |
160 | unsigned i; | |
161 | int r; | |
162 | ||
163 | if (!parent->entries) | |
164 | return 0; | |
165 | ||
166 | for (i = 0; i <= parent->last_entry_used; ++i) { | |
167 | struct amdgpu_vm_pt *entry = &parent->entries[i]; | |
168 | ||
169 | if (!entry->bo) | |
170 | continue; | |
171 | ||
172 | r = validate(param, entry->bo); | |
173 | if (r) | |
174 | return r; | |
175 | ||
176 | /* | |
177 | * Recurse into the sub directory. This is harmless because we | |
178 | * have only a maximum of 5 layers. | |
179 | */ | |
180 | r = amdgpu_vm_validate_level(entry, validate, param); | |
181 | if (r) | |
182 | return r; | |
183 | } | |
184 | ||
185 | return r; | |
186 | } | |
187 | ||
56467ebf | 188 | /** |
f7da30d9 | 189 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
56467ebf | 190 | * |
5a712a87 | 191 | * @adev: amdgpu device pointer |
56467ebf | 192 | * @vm: vm providing the BOs |
f7da30d9 CK |
193 | * @validate: callback to do the validation |
194 | * @param: parameter for the validation callback | |
d38ceaf9 | 195 | * |
f7da30d9 | 196 | * Validate the page table BOs on command submission if neccessary. |
d38ceaf9 | 197 | */ |
f7da30d9 CK |
198 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
199 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
200 | void *param) | |
d38ceaf9 | 201 | { |
5a712a87 | 202 | uint64_t num_evictions; |
d38ceaf9 | 203 | |
5a712a87 CK |
204 | /* We only need to validate the page tables |
205 | * if they aren't already valid. | |
206 | */ | |
207 | num_evictions = atomic64_read(&adev->num_evictions); | |
208 | if (num_evictions == vm->last_eviction_counter) | |
f7da30d9 | 209 | return 0; |
5a712a87 | 210 | |
670fecc8 | 211 | return amdgpu_vm_validate_level(&vm->root, validate, param); |
eceb8a15 CK |
212 | } |
213 | ||
214 | /** | |
d711e139 | 215 | * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail |
eceb8a15 CK |
216 | * |
217 | * @adev: amdgpu device instance | |
218 | * @vm: vm providing the BOs | |
219 | * | |
220 | * Move the PT BOs to the tail of the LRU. | |
221 | */ | |
d711e139 | 222 | static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent) |
eceb8a15 | 223 | { |
eceb8a15 CK |
224 | unsigned i; |
225 | ||
d711e139 CK |
226 | if (!parent->entries) |
227 | return; | |
eceb8a15 | 228 | |
d711e139 CK |
229 | for (i = 0; i <= parent->last_entry_used; ++i) { |
230 | struct amdgpu_vm_pt *entry = &parent->entries[i]; | |
231 | ||
232 | if (!entry->bo) | |
eceb8a15 CK |
233 | continue; |
234 | ||
d711e139 CK |
235 | ttm_bo_move_to_lru_tail(&entry->bo->tbo); |
236 | amdgpu_vm_move_level_in_lru(entry); | |
eceb8a15 | 237 | } |
d711e139 CK |
238 | } |
239 | ||
240 | /** | |
241 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
242 | * | |
243 | * @adev: amdgpu device instance | |
244 | * @vm: vm providing the BOs | |
245 | * | |
246 | * Move the PT BOs to the tail of the LRU. | |
247 | */ | |
248 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
249 | struct amdgpu_vm *vm) | |
250 | { | |
251 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
252 | ||
253 | spin_lock(&glob->lru_lock); | |
254 | amdgpu_vm_move_level_in_lru(&vm->root); | |
eceb8a15 | 255 | spin_unlock(&glob->lru_lock); |
d38ceaf9 AD |
256 | } |
257 | ||
f566ceb1 CK |
258 | /** |
259 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels | |
260 | * | |
261 | * @adev: amdgpu_device pointer | |
262 | * @vm: requested vm | |
263 | * @saddr: start of the address range | |
264 | * @eaddr: end of the address range | |
265 | * | |
266 | * Make sure the page directories and page tables are allocated | |
267 | */ | |
268 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
269 | struct amdgpu_vm *vm, | |
270 | struct amdgpu_vm_pt *parent, | |
271 | uint64_t saddr, uint64_t eaddr, | |
272 | unsigned level) | |
273 | { | |
274 | unsigned shift = (adev->vm_manager.num_level - level) * | |
36b32a68 | 275 | adev->vm_manager.block_size; |
f566ceb1 CK |
276 | unsigned pt_idx, from, to; |
277 | int r; | |
278 | ||
279 | if (!parent->entries) { | |
280 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
281 | ||
282 | parent->entries = drm_calloc_large(num_entries, | |
283 | sizeof(struct amdgpu_vm_pt)); | |
284 | if (!parent->entries) | |
285 | return -ENOMEM; | |
286 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
287 | } | |
288 | ||
1866bac8 FK |
289 | from = saddr >> shift; |
290 | to = eaddr >> shift; | |
291 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
292 | to >= amdgpu_vm_num_entries(adev, level)) | |
293 | return -EINVAL; | |
f566ceb1 CK |
294 | |
295 | if (to > parent->last_entry_used) | |
296 | parent->last_entry_used = to; | |
297 | ||
298 | ++level; | |
1866bac8 FK |
299 | saddr = saddr & ((1 << shift) - 1); |
300 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 CK |
301 | |
302 | /* walk over the address space and allocate the page tables */ | |
303 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
304 | struct reservation_object *resv = vm->root.bo->tbo.resv; | |
305 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
306 | struct amdgpu_bo *pt; | |
307 | ||
308 | if (!entry->bo) { | |
309 | r = amdgpu_bo_create(adev, | |
310 | amdgpu_vm_bo_size(adev, level), | |
311 | AMDGPU_GPU_PAGE_SIZE, true, | |
312 | AMDGPU_GEM_DOMAIN_VRAM, | |
313 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
314 | AMDGPU_GEM_CREATE_SHADOW | | |
315 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
316 | AMDGPU_GEM_CREATE_VRAM_CLEARED, | |
317 | NULL, resv, &pt); | |
318 | if (r) | |
319 | return r; | |
320 | ||
321 | /* Keep a reference to the root directory to avoid | |
322 | * freeing them up in the wrong order. | |
323 | */ | |
324 | pt->parent = amdgpu_bo_ref(vm->root.bo); | |
325 | ||
326 | entry->bo = pt; | |
327 | entry->addr = 0; | |
328 | } | |
329 | ||
330 | if (level < adev->vm_manager.num_level) { | |
1866bac8 FK |
331 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
332 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
333 | ((1 << shift) - 1); | |
334 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
335 | sub_eaddr, level); | |
f566ceb1 CK |
336 | if (r) |
337 | return r; | |
338 | } | |
339 | } | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
663e4577 CK |
344 | /** |
345 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
346 | * | |
347 | * @adev: amdgpu_device pointer | |
348 | * @vm: VM to allocate page tables for | |
349 | * @saddr: Start address which needs to be allocated | |
350 | * @size: Size from start address we need. | |
351 | * | |
352 | * Make sure the page tables are allocated. | |
353 | */ | |
354 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
355 | struct amdgpu_vm *vm, | |
356 | uint64_t saddr, uint64_t size) | |
357 | { | |
22770e5a | 358 | uint64_t last_pfn; |
663e4577 | 359 | uint64_t eaddr; |
663e4577 CK |
360 | |
361 | /* validate the parameters */ | |
362 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
363 | return -EINVAL; | |
364 | ||
365 | eaddr = saddr + size - 1; | |
366 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
367 | if (last_pfn >= adev->vm_manager.max_pfn) { | |
22770e5a | 368 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", |
663e4577 CK |
369 | last_pfn, adev->vm_manager.max_pfn); |
370 | return -EINVAL; | |
371 | } | |
372 | ||
373 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
374 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
375 | ||
f566ceb1 | 376 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); |
663e4577 CK |
377 | } |
378 | ||
641e9400 CK |
379 | /** |
380 | * amdgpu_vm_had_gpu_reset - check if reset occured since last use | |
381 | * | |
382 | * @adev: amdgpu_device pointer | |
383 | * @id: VMID structure | |
384 | * | |
385 | * Check if GPU reset occured since last use of the VMID. | |
386 | */ | |
387 | static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev, | |
388 | struct amdgpu_vm_id *id) | |
192b7dcb CZ |
389 | { |
390 | return id->current_gpu_reset_count != | |
641e9400 | 391 | atomic_read(&adev->gpu_reset_counter); |
192b7dcb CZ |
392 | } |
393 | ||
7a63eb23 CZ |
394 | static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub) |
395 | { | |
396 | return !!vm->reserved_vmid[vmhub]; | |
397 | } | |
398 | ||
399 | /* idr_mgr->lock must be held */ | |
400 | static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, | |
401 | struct amdgpu_ring *ring, | |
402 | struct amdgpu_sync *sync, | |
403 | struct dma_fence *fence, | |
404 | struct amdgpu_job *job) | |
405 | { | |
406 | struct amdgpu_device *adev = ring->adev; | |
407 | unsigned vmhub = ring->funcs->vmhub; | |
408 | uint64_t fence_context = adev->fence_context + ring->idx; | |
409 | struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub]; | |
410 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
411 | struct dma_fence *updates = sync->last_vm_update; | |
412 | int r = 0; | |
413 | struct dma_fence *flushed, *tmp; | |
414 | bool needs_flush = false; | |
415 | ||
416 | flushed = id->flushed_updates; | |
417 | if ((amdgpu_vm_had_gpu_reset(adev, id)) || | |
418 | (atomic64_read(&id->owner) != vm->client_id) || | |
419 | (job->vm_pd_addr != id->pd_gpu_addr) || | |
420 | (updates && (!flushed || updates->context != flushed->context || | |
421 | dma_fence_is_later(updates, flushed))) || | |
422 | (!id->last_flush || (id->last_flush->context != fence_context && | |
423 | !dma_fence_is_signaled(id->last_flush)))) { | |
424 | needs_flush = true; | |
425 | /* to prevent one context starved by another context */ | |
426 | id->pd_gpu_addr = 0; | |
427 | tmp = amdgpu_sync_peek_fence(&id->active, ring); | |
428 | if (tmp) { | |
429 | r = amdgpu_sync_fence(adev, sync, tmp); | |
430 | return r; | |
431 | } | |
432 | } | |
433 | ||
434 | /* Good we can use this VMID. Remember this submission as | |
435 | * user of the VMID. | |
436 | */ | |
437 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
438 | if (r) | |
439 | goto out; | |
440 | ||
441 | if (updates && (!flushed || updates->context != flushed->context || | |
442 | dma_fence_is_later(updates, flushed))) { | |
443 | dma_fence_put(id->flushed_updates); | |
444 | id->flushed_updates = dma_fence_get(updates); | |
445 | } | |
446 | id->pd_gpu_addr = job->vm_pd_addr; | |
7a63eb23 CZ |
447 | atomic64_set(&id->owner, vm->client_id); |
448 | job->vm_needs_flush = needs_flush; | |
449 | if (needs_flush) { | |
450 | dma_fence_put(id->last_flush); | |
451 | id->last_flush = NULL; | |
452 | } | |
453 | job->vm_id = id - id_mgr->ids; | |
454 | trace_amdgpu_vm_grab_id(vm, ring, job); | |
455 | out: | |
456 | return r; | |
457 | } | |
458 | ||
d38ceaf9 AD |
459 | /** |
460 | * amdgpu_vm_grab_id - allocate the next free VMID | |
461 | * | |
d38ceaf9 | 462 | * @vm: vm to allocate id for |
7f8a5290 CK |
463 | * @ring: ring we want to submit job to |
464 | * @sync: sync object where we add dependencies | |
94dd0a4a | 465 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 466 | * |
7f8a5290 | 467 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 468 | */ |
7f8a5290 | 469 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
f54d1867 | 470 | struct amdgpu_sync *sync, struct dma_fence *fence, |
fd53be30 | 471 | struct amdgpu_job *job) |
d38ceaf9 | 472 | { |
d38ceaf9 | 473 | struct amdgpu_device *adev = ring->adev; |
2e819849 | 474 | unsigned vmhub = ring->funcs->vmhub; |
7645670d | 475 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
090b767e | 476 | uint64_t fence_context = adev->fence_context + ring->idx; |
f54d1867 | 477 | struct dma_fence *updates = sync->last_vm_update; |
8d76001e | 478 | struct amdgpu_vm_id *id, *idle; |
f54d1867 | 479 | struct dma_fence **fences; |
1fbb2e92 CK |
480 | unsigned i; |
481 | int r = 0; | |
482 | ||
7a63eb23 CZ |
483 | mutex_lock(&id_mgr->lock); |
484 | if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) { | |
485 | r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job); | |
486 | mutex_unlock(&id_mgr->lock); | |
487 | return r; | |
488 | } | |
7645670d | 489 | fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); |
7a63eb23 CZ |
490 | if (!fences) { |
491 | mutex_unlock(&id_mgr->lock); | |
1fbb2e92 | 492 | return -ENOMEM; |
7a63eb23 | 493 | } |
36fd7c5c | 494 | /* Check if we have an idle VMID */ |
1fbb2e92 | 495 | i = 0; |
7645670d | 496 | list_for_each_entry(idle, &id_mgr->ids_lru, list) { |
1fbb2e92 CK |
497 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
498 | if (!fences[i]) | |
36fd7c5c | 499 | break; |
1fbb2e92 | 500 | ++i; |
36fd7c5c CK |
501 | } |
502 | ||
1fbb2e92 | 503 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
7645670d | 504 | if (&idle->list == &id_mgr->ids_lru) { |
1fbb2e92 CK |
505 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
506 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
f54d1867 | 507 | struct dma_fence_array *array; |
1fbb2e92 CK |
508 | unsigned j; |
509 | ||
510 | for (j = 0; j < i; ++j) | |
f54d1867 | 511 | dma_fence_get(fences[j]); |
1fbb2e92 | 512 | |
f54d1867 | 513 | array = dma_fence_array_create(i, fences, fence_context, |
1fbb2e92 CK |
514 | seqno, true); |
515 | if (!array) { | |
516 | for (j = 0; j < i; ++j) | |
f54d1867 | 517 | dma_fence_put(fences[j]); |
1fbb2e92 CK |
518 | kfree(fences); |
519 | r = -ENOMEM; | |
520 | goto error; | |
521 | } | |
522 | ||
523 | ||
524 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
f54d1867 | 525 | dma_fence_put(&array->base); |
1fbb2e92 CK |
526 | if (r) |
527 | goto error; | |
528 | ||
7645670d | 529 | mutex_unlock(&id_mgr->lock); |
1fbb2e92 CK |
530 | return 0; |
531 | ||
532 | } | |
533 | kfree(fences); | |
534 | ||
87c910d8 | 535 | job->vm_needs_flush = false; |
1fbb2e92 | 536 | /* Check if we can use a VMID already assigned to this VM */ |
7645670d | 537 | list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) { |
f54d1867 | 538 | struct dma_fence *flushed; |
87c910d8 | 539 | bool needs_flush = false; |
1fbb2e92 | 540 | |
1fbb2e92 | 541 | /* Check all the prerequisites to using this VMID */ |
641e9400 | 542 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
6adb0513 | 543 | continue; |
1fbb2e92 CK |
544 | |
545 | if (atomic64_read(&id->owner) != vm->client_id) | |
546 | continue; | |
547 | ||
fd53be30 | 548 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
549 | continue; |
550 | ||
87c910d8 CK |
551 | if (!id->last_flush || |
552 | (id->last_flush->context != fence_context && | |
553 | !dma_fence_is_signaled(id->last_flush))) | |
554 | needs_flush = true; | |
1fbb2e92 CK |
555 | |
556 | flushed = id->flushed_updates; | |
87c910d8 CK |
557 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) |
558 | needs_flush = true; | |
559 | ||
560 | /* Concurrent flushes are only possible starting with Vega10 */ | |
561 | if (adev->asic_type < CHIP_VEGA10 && needs_flush) | |
1fbb2e92 CK |
562 | continue; |
563 | ||
3dab83be CK |
564 | /* Good we can use this VMID. Remember this submission as |
565 | * user of the VMID. | |
566 | */ | |
1fbb2e92 CK |
567 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
568 | if (r) | |
569 | goto error; | |
8d76001e | 570 | |
87c910d8 CK |
571 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) { |
572 | dma_fence_put(id->flushed_updates); | |
573 | id->flushed_updates = dma_fence_get(updates); | |
574 | } | |
8d76001e | 575 | |
87c910d8 CK |
576 | if (needs_flush) |
577 | goto needs_flush; | |
578 | else | |
579 | goto no_flush_needed; | |
8d76001e | 580 | |
4f618e73 | 581 | }; |
8d76001e | 582 | |
1fbb2e92 CK |
583 | /* Still no ID to use? Then use the idle one found earlier */ |
584 | id = idle; | |
8e9fbeb5 | 585 | |
1fbb2e92 CK |
586 | /* Remember this submission as user of the VMID */ |
587 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
588 | if (r) |
589 | goto error; | |
94dd0a4a | 590 | |
87c910d8 | 591 | id->pd_gpu_addr = job->vm_pd_addr; |
f54d1867 CW |
592 | dma_fence_put(id->flushed_updates); |
593 | id->flushed_updates = dma_fence_get(updates); | |
0ea54b9b | 594 | atomic64_set(&id->owner, vm->client_id); |
d38ceaf9 | 595 | |
87c910d8 CK |
596 | needs_flush: |
597 | job->vm_needs_flush = true; | |
598 | dma_fence_put(id->last_flush); | |
599 | id->last_flush = NULL; | |
600 | ||
601 | no_flush_needed: | |
602 | list_move_tail(&id->list, &id_mgr->ids_lru); | |
603 | ||
7645670d | 604 | job->vm_id = id - id_mgr->ids; |
c5296d14 | 605 | trace_amdgpu_vm_grab_id(vm, ring, job); |
832a902f CK |
606 | |
607 | error: | |
7645670d | 608 | mutex_unlock(&id_mgr->lock); |
a9a78b32 | 609 | return r; |
d38ceaf9 AD |
610 | } |
611 | ||
1e9ef26f CZ |
612 | static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev, |
613 | struct amdgpu_vm *vm, | |
614 | unsigned vmhub) | |
615 | { | |
616 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
617 | ||
618 | mutex_lock(&id_mgr->lock); | |
619 | if (vm->reserved_vmid[vmhub]) { | |
620 | list_add(&vm->reserved_vmid[vmhub]->list, | |
621 | &id_mgr->ids_lru); | |
622 | vm->reserved_vmid[vmhub] = NULL; | |
c3505770 | 623 | atomic_dec(&id_mgr->reserved_vmid_num); |
1e9ef26f CZ |
624 | } |
625 | mutex_unlock(&id_mgr->lock); | |
626 | } | |
627 | ||
628 | static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev, | |
629 | struct amdgpu_vm *vm, | |
630 | unsigned vmhub) | |
631 | { | |
632 | struct amdgpu_vm_id_manager *id_mgr; | |
633 | struct amdgpu_vm_id *idle; | |
634 | int r = 0; | |
635 | ||
636 | id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
637 | mutex_lock(&id_mgr->lock); | |
638 | if (vm->reserved_vmid[vmhub]) | |
639 | goto unlock; | |
c3505770 CZ |
640 | if (atomic_inc_return(&id_mgr->reserved_vmid_num) > |
641 | AMDGPU_VM_MAX_RESERVED_VMID) { | |
642 | DRM_ERROR("Over limitation of reserved vmid\n"); | |
643 | atomic_dec(&id_mgr->reserved_vmid_num); | |
644 | r = -EINVAL; | |
645 | goto unlock; | |
646 | } | |
1e9ef26f CZ |
647 | /* Select the first entry VMID */ |
648 | idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list); | |
649 | list_del_init(&idle->list); | |
650 | vm->reserved_vmid[vmhub] = idle; | |
651 | mutex_unlock(&id_mgr->lock); | |
652 | ||
653 | return 0; | |
654 | unlock: | |
655 | mutex_unlock(&id_mgr->lock); | |
656 | return r; | |
657 | } | |
658 | ||
93dcc37d AD |
659 | static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) |
660 | { | |
661 | struct amdgpu_device *adev = ring->adev; | |
a1255107 | 662 | const struct amdgpu_ip_block *ip_block; |
93dcc37d | 663 | |
21cd942e | 664 | if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) |
93dcc37d AD |
665 | /* only compute rings */ |
666 | return false; | |
667 | ||
668 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
669 | if (!ip_block) | |
670 | return false; | |
671 | ||
a1255107 | 672 | if (ip_block->version->major <= 7) { |
93dcc37d AD |
673 | /* gfx7 has no workaround */ |
674 | return true; | |
a1255107 | 675 | } else if (ip_block->version->major == 8) { |
93dcc37d AD |
676 | if (adev->gfx.mec_fw_version >= 673) |
677 | /* gfx8 is fixed in MEC firmware 673 */ | |
678 | return false; | |
679 | else | |
680 | return true; | |
681 | } | |
682 | return false; | |
683 | } | |
684 | ||
e60f8db5 AX |
685 | static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) |
686 | { | |
687 | u64 addr = mc_addr; | |
688 | ||
f75e237c CK |
689 | if (adev->gart.gart_funcs->adjust_mc_addr) |
690 | addr = adev->gart.gart_funcs->adjust_mc_addr(adev, addr); | |
e60f8db5 AX |
691 | |
692 | return addr; | |
693 | } | |
694 | ||
b9bf33d5 CZ |
695 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
696 | struct amdgpu_job *job) | |
697 | { | |
698 | struct amdgpu_device *adev = ring->adev; | |
699 | unsigned vmhub = ring->funcs->vmhub; | |
700 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
701 | struct amdgpu_vm_id *id; | |
702 | bool gds_switch_needed; | |
703 | bool vm_flush_needed = job->vm_needs_flush || | |
704 | amdgpu_vm_ring_has_compute_vm_bug(ring); | |
705 | ||
706 | if (job->vm_id == 0) | |
707 | return false; | |
708 | id = &id_mgr->ids[job->vm_id]; | |
709 | gds_switch_needed = ring->funcs->emit_gds_switch && ( | |
710 | id->gds_base != job->gds_base || | |
711 | id->gds_size != job->gds_size || | |
712 | id->gws_base != job->gws_base || | |
713 | id->gws_size != job->gws_size || | |
714 | id->oa_base != job->oa_base || | |
715 | id->oa_size != job->oa_size); | |
716 | ||
717 | if (amdgpu_vm_had_gpu_reset(adev, id)) | |
718 | return true; | |
719 | if (!vm_flush_needed && !gds_switch_needed) | |
720 | return false; | |
721 | return true; | |
722 | } | |
723 | ||
d38ceaf9 AD |
724 | /** |
725 | * amdgpu_vm_flush - hardware flush the vm | |
726 | * | |
727 | * @ring: ring to use for flush | |
cffadc83 | 728 | * @vm_id: vmid number to use |
4ff37a83 | 729 | * @pd_addr: address of the page directory |
d38ceaf9 | 730 | * |
4ff37a83 | 731 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 732 | */ |
fd53be30 | 733 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) |
d38ceaf9 | 734 | { |
971fe9a9 | 735 | struct amdgpu_device *adev = ring->adev; |
7645670d CK |
736 | unsigned vmhub = ring->funcs->vmhub; |
737 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
738 | struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id]; | |
d564a06e | 739 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
740 | id->gds_base != job->gds_base || |
741 | id->gds_size != job->gds_size || | |
742 | id->gws_base != job->gws_base || | |
743 | id->gws_size != job->gws_size || | |
744 | id->oa_base != job->oa_base || | |
745 | id->oa_size != job->oa_size); | |
de37e68a | 746 | bool vm_flush_needed = job->vm_needs_flush; |
c0e51931 | 747 | unsigned patch_offset = 0; |
41d9eb2c | 748 | int r; |
d564a06e | 749 | |
f7d015b9 CK |
750 | if (amdgpu_vm_had_gpu_reset(adev, id)) { |
751 | gds_switch_needed = true; | |
752 | vm_flush_needed = true; | |
753 | } | |
971fe9a9 | 754 | |
f7d015b9 CK |
755 | if (!vm_flush_needed && !gds_switch_needed) |
756 | return 0; | |
41d9eb2c | 757 | |
c0e51931 CK |
758 | if (ring->funcs->init_cond_exec) |
759 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 760 | |
f7d015b9 | 761 | if (ring->funcs->emit_vm_flush && vm_flush_needed) { |
c0e51931 CK |
762 | u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr); |
763 | struct dma_fence *fence; | |
41d9eb2c | 764 | |
5f1bcf51 | 765 | trace_amdgpu_vm_flush(ring, job->vm_id, pd_addr); |
c0e51931 | 766 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr); |
e9d672b2 | 767 | |
c0e51931 CK |
768 | r = amdgpu_fence_emit(ring, &fence); |
769 | if (r) | |
770 | return r; | |
e9d672b2 | 771 | |
7645670d | 772 | mutex_lock(&id_mgr->lock); |
c0e51931 CK |
773 | dma_fence_put(id->last_flush); |
774 | id->last_flush = fence; | |
bea39672 | 775 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
7645670d | 776 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 777 | } |
e9d672b2 | 778 | |
ca7962d8 | 779 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
780 | id->gds_base = job->gds_base; |
781 | id->gds_size = job->gds_size; | |
782 | id->gws_base = job->gws_base; | |
783 | id->gws_size = job->gws_size; | |
784 | id->oa_base = job->oa_base; | |
785 | id->oa_size = job->oa_size; | |
786 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base, | |
787 | job->gds_size, job->gws_base, | |
788 | job->gws_size, job->oa_base, | |
789 | job->oa_size); | |
790 | } | |
791 | ||
792 | if (ring->funcs->patch_cond_exec) | |
793 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
794 | ||
795 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
796 | if (ring->funcs->emit_switch_buffer) { | |
797 | amdgpu_ring_emit_switch_buffer(ring); | |
798 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 799 | } |
41d9eb2c | 800 | return 0; |
971fe9a9 CK |
801 | } |
802 | ||
803 | /** | |
804 | * amdgpu_vm_reset_id - reset VMID to zero | |
805 | * | |
806 | * @adev: amdgpu device structure | |
807 | * @vm_id: vmid number to use | |
808 | * | |
809 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
810 | */ | |
7645670d CK |
811 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
812 | unsigned vmid) | |
971fe9a9 | 813 | { |
7645670d CK |
814 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
815 | struct amdgpu_vm_id *id = &id_mgr->ids[vmid]; | |
bcb1ba35 | 816 | |
32601d48 | 817 | atomic64_set(&id->owner, 0); |
bcb1ba35 CK |
818 | id->gds_base = 0; |
819 | id->gds_size = 0; | |
820 | id->gws_base = 0; | |
821 | id->gws_size = 0; | |
822 | id->oa_base = 0; | |
823 | id->oa_size = 0; | |
d38ceaf9 AD |
824 | } |
825 | ||
32601d48 CK |
826 | /** |
827 | * amdgpu_vm_reset_all_id - reset VMID to zero | |
828 | * | |
829 | * @adev: amdgpu device structure | |
830 | * | |
831 | * Reset VMID to force flush on next use | |
832 | */ | |
833 | void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev) | |
834 | { | |
835 | unsigned i, j; | |
836 | ||
837 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
838 | struct amdgpu_vm_id_manager *id_mgr = | |
839 | &adev->vm_manager.id_mgr[i]; | |
840 | ||
841 | for (j = 1; j < id_mgr->num_ids; ++j) | |
842 | amdgpu_vm_reset_id(adev, i, j); | |
843 | } | |
844 | } | |
845 | ||
d38ceaf9 AD |
846 | /** |
847 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
848 | * | |
849 | * @vm: requested vm | |
850 | * @bo: requested buffer object | |
851 | * | |
8843dbbb | 852 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
853 | * Search inside the @bos vm list for the requested vm |
854 | * Returns the found bo_va or NULL if none is found | |
855 | * | |
856 | * Object has to be reserved! | |
857 | */ | |
858 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
859 | struct amdgpu_bo *bo) | |
860 | { | |
861 | struct amdgpu_bo_va *bo_va; | |
862 | ||
863 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
864 | if (bo_va->vm == vm) { | |
865 | return bo_va; | |
866 | } | |
867 | } | |
868 | return NULL; | |
869 | } | |
870 | ||
871 | /** | |
afef8b8f | 872 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 873 | * |
29efc4f5 | 874 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
875 | * @pe: addr of the page entry |
876 | * @addr: dst addr to write into pe | |
877 | * @count: number of page entries to update | |
878 | * @incr: increase next addr by incr bytes | |
879 | * @flags: hw access flags | |
d38ceaf9 AD |
880 | * |
881 | * Traces the parameters and calls the right asic functions | |
882 | * to setup the page table using the DMA. | |
883 | */ | |
afef8b8f CK |
884 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
885 | uint64_t pe, uint64_t addr, | |
886 | unsigned count, uint32_t incr, | |
6b777607 | 887 | uint64_t flags) |
d38ceaf9 | 888 | { |
ec2f05f0 | 889 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 890 | |
afef8b8f | 891 | if (count < 3) { |
de9ea7bd CK |
892 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
893 | addr | flags, count, incr); | |
d38ceaf9 AD |
894 | |
895 | } else { | |
27c5f36f | 896 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
897 | count, incr, flags); |
898 | } | |
899 | } | |
900 | ||
afef8b8f CK |
901 | /** |
902 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
903 | * | |
904 | * @params: see amdgpu_pte_update_params definition | |
905 | * @pe: addr of the page entry | |
906 | * @addr: dst addr to write into pe | |
907 | * @count: number of page entries to update | |
908 | * @incr: increase next addr by incr bytes | |
909 | * @flags: hw access flags | |
910 | * | |
911 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
912 | */ | |
913 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
914 | uint64_t pe, uint64_t addr, | |
915 | unsigned count, uint32_t incr, | |
6b777607 | 916 | uint64_t flags) |
afef8b8f | 917 | { |
ec2f05f0 | 918 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 919 | |
ec2f05f0 CK |
920 | |
921 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
922 | ||
923 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
924 | } |
925 | ||
d38ceaf9 | 926 | /** |
b07c9d2a | 927 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 928 | * |
b07c9d2a | 929 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
930 | * @addr: the unmapped addr |
931 | * | |
932 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 933 | * to and return the pointer for the page table entry. |
d38ceaf9 | 934 | */ |
de9ea7bd | 935 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
936 | { |
937 | uint64_t result; | |
938 | ||
de9ea7bd CK |
939 | /* page table offset */ |
940 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 941 | |
de9ea7bd CK |
942 | /* in case cpu page size != gpu page size*/ |
943 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 944 | |
b07c9d2a | 945 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
946 | |
947 | return result; | |
948 | } | |
949 | ||
f8991bab | 950 | /* |
194d2161 | 951 | * amdgpu_vm_update_level - update a single level in the hierarchy |
f8991bab CK |
952 | * |
953 | * @adev: amdgpu_device pointer | |
954 | * @vm: requested vm | |
194d2161 | 955 | * @parent: parent directory |
f8991bab | 956 | * |
194d2161 | 957 | * Makes sure all entries in @parent are up to date. |
f8991bab CK |
958 | * Returns 0 for success, error for failure. |
959 | */ | |
194d2161 CK |
960 | static int amdgpu_vm_update_level(struct amdgpu_device *adev, |
961 | struct amdgpu_vm *vm, | |
962 | struct amdgpu_vm_pt *parent, | |
963 | unsigned level) | |
d38ceaf9 | 964 | { |
f8991bab | 965 | struct amdgpu_bo *shadow; |
2d55e45a | 966 | struct amdgpu_ring *ring; |
f8991bab | 967 | uint64_t pd_addr, shadow_addr; |
194d2161 | 968 | uint32_t incr = amdgpu_vm_bo_size(adev, level + 1); |
f8991bab | 969 | uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; |
d38ceaf9 | 970 | unsigned count = 0, pt_idx, ndw; |
d71518b5 | 971 | struct amdgpu_job *job; |
29efc4f5 | 972 | struct amdgpu_pte_update_params params; |
f54d1867 | 973 | struct dma_fence *fence = NULL; |
d5fc5e82 | 974 | |
d38ceaf9 AD |
975 | int r; |
976 | ||
194d2161 CK |
977 | if (!parent->entries) |
978 | return 0; | |
2d55e45a CK |
979 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
980 | ||
d38ceaf9 AD |
981 | /* padding, etc. */ |
982 | ndw = 64; | |
983 | ||
984 | /* assume the worst case */ | |
194d2161 | 985 | ndw += parent->last_entry_used * 6; |
d38ceaf9 | 986 | |
194d2161 CK |
987 | pd_addr = amdgpu_bo_gpu_offset(parent->bo); |
988 | ||
989 | shadow = parent->bo->shadow; | |
f8991bab CK |
990 | if (shadow) { |
991 | r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); | |
992 | if (r) | |
993 | return r; | |
994 | shadow_addr = amdgpu_bo_gpu_offset(shadow); | |
995 | ndw *= 2; | |
996 | } else { | |
997 | shadow_addr = 0; | |
998 | } | |
999 | ||
d71518b5 CK |
1000 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1001 | if (r) | |
d38ceaf9 | 1002 | return r; |
d71518b5 | 1003 | |
27c5f36f CK |
1004 | memset(¶ms, 0, sizeof(params)); |
1005 | params.adev = adev; | |
29efc4f5 | 1006 | params.ib = &job->ibs[0]; |
d38ceaf9 | 1007 | |
194d2161 CK |
1008 | /* walk over the address space and update the directory */ |
1009 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
1010 | struct amdgpu_bo *bo = parent->entries[pt_idx].bo; | |
d38ceaf9 AD |
1011 | uint64_t pde, pt; |
1012 | ||
1013 | if (bo == NULL) | |
1014 | continue; | |
1015 | ||
0fc8683e | 1016 | if (bo->shadow) { |
f8991bab | 1017 | struct amdgpu_bo *pt_shadow = bo->shadow; |
0fc8683e | 1018 | |
f8991bab CK |
1019 | r = amdgpu_ttm_bind(&pt_shadow->tbo, |
1020 | &pt_shadow->tbo.mem); | |
0fc8683e CK |
1021 | if (r) |
1022 | return r; | |
1023 | } | |
1024 | ||
d38ceaf9 | 1025 | pt = amdgpu_bo_gpu_offset(bo); |
194d2161 | 1026 | if (parent->entries[pt_idx].addr == pt) |
f8991bab CK |
1027 | continue; |
1028 | ||
194d2161 | 1029 | parent->entries[pt_idx].addr = pt; |
d38ceaf9 AD |
1030 | |
1031 | pde = pd_addr + pt_idx * 8; | |
1032 | if (((last_pde + 8 * count) != pde) || | |
96105e53 CK |
1033 | ((last_pt + incr * count) != pt) || |
1034 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
d38ceaf9 AD |
1035 | |
1036 | if (count) { | |
e60f8db5 AX |
1037 | uint64_t pt_addr = |
1038 | amdgpu_vm_adjust_mc_addr(adev, last_pt); | |
1039 | ||
f8991bab CK |
1040 | if (shadow) |
1041 | amdgpu_vm_do_set_ptes(¶ms, | |
1042 | last_shadow, | |
e60f8db5 | 1043 | pt_addr, count, |
f8991bab CK |
1044 | incr, |
1045 | AMDGPU_PTE_VALID); | |
1046 | ||
afef8b8f | 1047 | amdgpu_vm_do_set_ptes(¶ms, last_pde, |
e60f8db5 | 1048 | pt_addr, count, incr, |
afef8b8f | 1049 | AMDGPU_PTE_VALID); |
d38ceaf9 AD |
1050 | } |
1051 | ||
1052 | count = 1; | |
1053 | last_pde = pde; | |
f8991bab | 1054 | last_shadow = shadow_addr + pt_idx * 8; |
d38ceaf9 AD |
1055 | last_pt = pt; |
1056 | } else { | |
1057 | ++count; | |
1058 | } | |
1059 | } | |
1060 | ||
f8991bab | 1061 | if (count) { |
e60f8db5 AX |
1062 | uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt); |
1063 | ||
67003a15 | 1064 | if (vm->root.bo->shadow) |
e60f8db5 | 1065 | amdgpu_vm_do_set_ptes(¶ms, last_shadow, pt_addr, |
f8991bab CK |
1066 | count, incr, AMDGPU_PTE_VALID); |
1067 | ||
e60f8db5 | 1068 | amdgpu_vm_do_set_ptes(¶ms, last_pde, pt_addr, |
afef8b8f | 1069 | count, incr, AMDGPU_PTE_VALID); |
f8991bab | 1070 | } |
d38ceaf9 | 1071 | |
f8991bab CK |
1072 | if (params.ib->length_dw == 0) { |
1073 | amdgpu_job_free(job); | |
194d2161 CK |
1074 | } else { |
1075 | amdgpu_ring_pad_ib(ring, params.ib); | |
1076 | amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv, | |
e86f9cee | 1077 | AMDGPU_FENCE_OWNER_VM); |
194d2161 CK |
1078 | if (shadow) |
1079 | amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv, | |
1080 | AMDGPU_FENCE_OWNER_VM); | |
05906dec | 1081 | |
194d2161 CK |
1082 | WARN_ON(params.ib->length_dw > ndw); |
1083 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
1084 | AMDGPU_FENCE_OWNER_VM, &fence); | |
1085 | if (r) | |
1086 | goto error_free; | |
1087 | ||
1088 | amdgpu_bo_fence(parent->bo, fence, true); | |
1089 | dma_fence_put(vm->last_dir_update); | |
1090 | vm->last_dir_update = dma_fence_get(fence); | |
1091 | dma_fence_put(fence); | |
1092 | } | |
1093 | /* | |
1094 | * Recurse into the subdirectories. This recursion is harmless because | |
1095 | * we only have a maximum of 5 layers. | |
1096 | */ | |
1097 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
1098 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
1099 | ||
1100 | if (!entry->bo) | |
1101 | continue; | |
d5fc5e82 | 1102 | |
194d2161 CK |
1103 | r = amdgpu_vm_update_level(adev, vm, entry, level + 1); |
1104 | if (r) | |
1105 | return r; | |
1106 | } | |
d38ceaf9 AD |
1107 | |
1108 | return 0; | |
d5fc5e82 CZ |
1109 | |
1110 | error_free: | |
d71518b5 | 1111 | amdgpu_job_free(job); |
4af9f07c | 1112 | return r; |
d38ceaf9 AD |
1113 | } |
1114 | ||
194d2161 CK |
1115 | /* |
1116 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1117 | * | |
1118 | * @adev: amdgpu_device pointer | |
1119 | * @vm: requested vm | |
1120 | * | |
1121 | * Makes sure all directories are up to date. | |
1122 | * Returns 0 for success, error for failure. | |
1123 | */ | |
1124 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1125 | struct amdgpu_vm *vm) | |
1126 | { | |
1127 | return amdgpu_vm_update_level(adev, vm, &vm->root, 0); | |
1128 | } | |
1129 | ||
4e2cb640 CK |
1130 | /** |
1131 | * amdgpu_vm_find_pt - find the page table for an address | |
1132 | * | |
1133 | * @p: see amdgpu_pte_update_params definition | |
1134 | * @addr: virtual address in question | |
1135 | * | |
1136 | * Find the page table BO for a virtual address, return NULL when none found. | |
1137 | */ | |
1138 | static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p, | |
1139 | uint64_t addr) | |
1140 | { | |
1141 | struct amdgpu_vm_pt *entry = &p->vm->root; | |
1142 | unsigned idx, level = p->adev->vm_manager.num_level; | |
1143 | ||
1144 | while (entry->entries) { | |
36b32a68 | 1145 | idx = addr >> (p->adev->vm_manager.block_size * level--); |
4e2cb640 CK |
1146 | idx %= amdgpu_bo_size(entry->bo) / 8; |
1147 | entry = &entry->entries[idx]; | |
1148 | } | |
1149 | ||
1150 | if (level) | |
1151 | return NULL; | |
1152 | ||
1153 | return entry->bo; | |
1154 | } | |
1155 | ||
d38ceaf9 AD |
1156 | /** |
1157 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1158 | * | |
29efc4f5 | 1159 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1160 | * @vm: requested vm |
1161 | * @start: start of GPU address range | |
1162 | * @end: end of GPU address range | |
677131a1 | 1163 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1164 | * @flags: mapping flags |
1165 | * | |
8843dbbb | 1166 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 1167 | */ |
27c5f36f | 1168 | static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1169 | uint64_t start, uint64_t end, |
6b777607 | 1170 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1171 | { |
36b32a68 ZJ |
1172 | struct amdgpu_device *adev = params->adev; |
1173 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1174 | |
92696dd5 | 1175 | uint64_t cur_pe_start, cur_nptes, cur_dst; |
677131a1 | 1176 | uint64_t addr; /* next GPU address to be updated */ |
21718497 AX |
1177 | struct amdgpu_bo *pt; |
1178 | unsigned nptes; /* next number of ptes to be updated */ | |
1179 | uint64_t next_pe_start; | |
1180 | ||
1181 | /* initialize the variables */ | |
1182 | addr = start; | |
4e2cb640 | 1183 | pt = amdgpu_vm_get_pt(params, addr); |
1866bac8 FK |
1184 | if (!pt) { |
1185 | pr_err("PT not found, aborting update_ptes\n"); | |
4e2cb640 | 1186 | return; |
1866bac8 | 1187 | } |
4e2cb640 | 1188 | |
4c7e8855 CZ |
1189 | if (params->shadow) { |
1190 | if (!pt->shadow) | |
1191 | return; | |
914b4dce | 1192 | pt = pt->shadow; |
4c7e8855 | 1193 | } |
21718497 AX |
1194 | if ((addr & ~mask) == (end & ~mask)) |
1195 | nptes = end - addr; | |
1196 | else | |
36b32a68 | 1197 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
21718497 AX |
1198 | |
1199 | cur_pe_start = amdgpu_bo_gpu_offset(pt); | |
1200 | cur_pe_start += (addr & mask) * 8; | |
92696dd5 | 1201 | cur_nptes = nptes; |
21718497 AX |
1202 | cur_dst = dst; |
1203 | ||
1204 | /* for next ptb*/ | |
1205 | addr += nptes; | |
1206 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
d38ceaf9 AD |
1207 | |
1208 | /* walk over the address space and update the page tables */ | |
21718497 | 1209 | while (addr < end) { |
4e2cb640 | 1210 | pt = amdgpu_vm_get_pt(params, addr); |
1866bac8 FK |
1211 | if (!pt) { |
1212 | pr_err("PT not found, aborting update_ptes\n"); | |
4e2cb640 | 1213 | return; |
1866bac8 | 1214 | } |
4e2cb640 | 1215 | |
4c7e8855 CZ |
1216 | if (params->shadow) { |
1217 | if (!pt->shadow) | |
1218 | return; | |
914b4dce | 1219 | pt = pt->shadow; |
4c7e8855 | 1220 | } |
d38ceaf9 AD |
1221 | |
1222 | if ((addr & ~mask) == (end & ~mask)) | |
1223 | nptes = end - addr; | |
1224 | else | |
36b32a68 | 1225 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1226 | |
677131a1 AX |
1227 | next_pe_start = amdgpu_bo_gpu_offset(pt); |
1228 | next_pe_start += (addr & mask) * 8; | |
d38ceaf9 | 1229 | |
96105e53 CK |
1230 | if ((cur_pe_start + 8 * cur_nptes) == next_pe_start && |
1231 | ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
3a6f8e0c | 1232 | /* The next ptb is consecutive to current ptb. |
afef8b8f | 1233 | * Don't call the update function now. |
3a6f8e0c AX |
1234 | * Will update two ptbs together in future. |
1235 | */ | |
92696dd5 | 1236 | cur_nptes += nptes; |
3a6f8e0c | 1237 | } else { |
afef8b8f CK |
1238 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
1239 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 | 1240 | |
677131a1 | 1241 | cur_pe_start = next_pe_start; |
92696dd5 | 1242 | cur_nptes = nptes; |
677131a1 | 1243 | cur_dst = dst; |
d38ceaf9 AD |
1244 | } |
1245 | ||
21718497 | 1246 | /* for next ptb*/ |
d38ceaf9 AD |
1247 | addr += nptes; |
1248 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
1249 | } | |
1250 | ||
afef8b8f CK |
1251 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
1252 | AMDGPU_GPU_PAGE_SIZE, flags); | |
92696dd5 CK |
1253 | } |
1254 | ||
1255 | /* | |
1256 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1257 | * | |
1258 | * @params: see amdgpu_pte_update_params definition | |
1259 | * @vm: requested vm | |
1260 | * @start: first PTE to handle | |
1261 | * @end: last PTE to handle | |
1262 | * @dst: addr those PTEs should point to | |
1263 | * @flags: hw mapping flags | |
1264 | */ | |
1265 | static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, | |
92696dd5 | 1266 | uint64_t start, uint64_t end, |
6b777607 | 1267 | uint64_t dst, uint64_t flags) |
92696dd5 CK |
1268 | { |
1269 | /** | |
1270 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1271 | * field in the PTE. When this field is set to a non-zero value, page | |
1272 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1273 | * flags are considered valid for all PTEs within the fragment range | |
1274 | * and corresponding mappings are assumed to be physically contiguous. | |
1275 | * | |
1276 | * The L1 TLB can store a single PTE for the whole fragment, | |
1277 | * significantly increasing the space available for translation | |
1278 | * caching. This leads to large improvements in throughput when the | |
1279 | * TLB is under pressure. | |
1280 | * | |
1281 | * The L2 TLB distributes small and large fragments into two | |
1282 | * asymmetric partitions. The large fragment cache is significantly | |
1283 | * larger. Thus, we try to use large fragments wherever possible. | |
1284 | * Userspace can support this by aligning virtual base address and | |
1285 | * allocation size to the fragment size. | |
1286 | */ | |
1287 | ||
8036617e CK |
1288 | /* SI and newer are optimized for 64KB */ |
1289 | uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG); | |
1290 | uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG; | |
92696dd5 CK |
1291 | |
1292 | uint64_t frag_start = ALIGN(start, frag_align); | |
1293 | uint64_t frag_end = end & ~(frag_align - 1); | |
1294 | ||
1295 | /* system pages are non continuously */ | |
b7fc2cbd | 1296 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
92696dd5 CK |
1297 | (frag_start >= frag_end)) { |
1298 | ||
49ac8a24 | 1299 | amdgpu_vm_update_ptes(params, start, end, dst, flags); |
92696dd5 CK |
1300 | return; |
1301 | } | |
1302 | ||
1303 | /* handle the 4K area at the beginning */ | |
1304 | if (start != frag_start) { | |
49ac8a24 | 1305 | amdgpu_vm_update_ptes(params, start, frag_start, |
92696dd5 CK |
1306 | dst, flags); |
1307 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; | |
1308 | } | |
1309 | ||
1310 | /* handle the area in the middle */ | |
49ac8a24 | 1311 | amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, |
8036617e | 1312 | flags | frag_flags); |
92696dd5 CK |
1313 | |
1314 | /* handle the 4K area at the end */ | |
1315 | if (frag_end != end) { | |
1316 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
49ac8a24 | 1317 | amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); |
92696dd5 | 1318 | } |
d38ceaf9 AD |
1319 | } |
1320 | ||
d38ceaf9 AD |
1321 | /** |
1322 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1323 | * | |
1324 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1325 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
1326 | * @src: address where to copy page table entries from |
1327 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 1328 | * @vm: requested vm |
a14faa65 CK |
1329 | * @start: start of mapped range |
1330 | * @last: last mapped entry | |
1331 | * @flags: flags for the entries | |
d38ceaf9 | 1332 | * @addr: addr to set the area to |
d38ceaf9 AD |
1333 | * @fence: optional resulting fence |
1334 | * | |
a14faa65 | 1335 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 1336 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
1337 | */ |
1338 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1339 | struct dma_fence *exclusive, |
fa3ab3c7 CK |
1340 | uint64_t src, |
1341 | dma_addr_t *pages_addr, | |
d38ceaf9 | 1342 | struct amdgpu_vm *vm, |
a14faa65 | 1343 | uint64_t start, uint64_t last, |
6b777607 | 1344 | uint64_t flags, uint64_t addr, |
f54d1867 | 1345 | struct dma_fence **fence) |
d38ceaf9 | 1346 | { |
2d55e45a | 1347 | struct amdgpu_ring *ring; |
a1e08d3b | 1348 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1349 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1350 | struct amdgpu_job *job; |
29efc4f5 | 1351 | struct amdgpu_pte_update_params params; |
f54d1867 | 1352 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1353 | int r; |
1354 | ||
afef8b8f CK |
1355 | memset(¶ms, 0, sizeof(params)); |
1356 | params.adev = adev; | |
49ac8a24 | 1357 | params.vm = vm; |
afef8b8f CK |
1358 | params.src = src; |
1359 | ||
2d55e45a | 1360 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 1361 | |
a1e08d3b CK |
1362 | /* sync to everything on unmapping */ |
1363 | if (!(flags & AMDGPU_PTE_VALID)) | |
1364 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1365 | ||
a14faa65 | 1366 | nptes = last - start + 1; |
d38ceaf9 AD |
1367 | |
1368 | /* | |
1369 | * reserve space for one command every (1 << BLOCK_SIZE) | |
1370 | * entries or 2k dwords (whatever is smaller) | |
1371 | */ | |
36b32a68 | 1372 | ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1; |
d38ceaf9 AD |
1373 | |
1374 | /* padding, etc. */ | |
1375 | ndw = 64; | |
1376 | ||
b0456f93 | 1377 | if (src) { |
d38ceaf9 AD |
1378 | /* only copy commands needed */ |
1379 | ndw += ncmds * 7; | |
1380 | ||
afef8b8f CK |
1381 | params.func = amdgpu_vm_do_copy_ptes; |
1382 | ||
b0456f93 CK |
1383 | } else if (pages_addr) { |
1384 | /* copy commands needed */ | |
1385 | ndw += ncmds * 7; | |
d38ceaf9 | 1386 | |
b0456f93 | 1387 | /* and also PTEs */ |
d38ceaf9 AD |
1388 | ndw += nptes * 2; |
1389 | ||
afef8b8f CK |
1390 | params.func = amdgpu_vm_do_copy_ptes; |
1391 | ||
d38ceaf9 AD |
1392 | } else { |
1393 | /* set page commands needed */ | |
1394 | ndw += ncmds * 10; | |
1395 | ||
1396 | /* two extra commands for begin/end of fragment */ | |
1397 | ndw += 2 * 10; | |
afef8b8f CK |
1398 | |
1399 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1400 | } |
1401 | ||
d71518b5 CK |
1402 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1403 | if (r) | |
d38ceaf9 | 1404 | return r; |
d71518b5 | 1405 | |
29efc4f5 | 1406 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1407 | |
b0456f93 CK |
1408 | if (!src && pages_addr) { |
1409 | uint64_t *pte; | |
1410 | unsigned i; | |
1411 | ||
1412 | /* Put the PTEs at the end of the IB. */ | |
1413 | i = ndw - nptes * 2; | |
1414 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1415 | params.src = job->ibs->gpu_addr + i * 4; | |
1416 | ||
1417 | for (i = 0; i < nptes; ++i) { | |
1418 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1419 | AMDGPU_GPU_PAGE_SIZE); | |
1420 | pte[i] |= flags; | |
1421 | } | |
d7a4ac66 | 1422 | addr = 0; |
b0456f93 CK |
1423 | } |
1424 | ||
3cabaa54 CK |
1425 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
1426 | if (r) | |
1427 | goto error_free; | |
1428 | ||
67003a15 | 1429 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv, |
a1e08d3b CK |
1430 | owner); |
1431 | if (r) | |
1432 | goto error_free; | |
d38ceaf9 | 1433 | |
67003a15 | 1434 | r = reservation_object_reserve_shared(vm->root.bo->tbo.resv); |
a1e08d3b CK |
1435 | if (r) |
1436 | goto error_free; | |
1437 | ||
4c7e8855 | 1438 | params.shadow = true; |
49ac8a24 | 1439 | amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
4c7e8855 | 1440 | params.shadow = false; |
49ac8a24 | 1441 | amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
d38ceaf9 | 1442 | |
29efc4f5 CK |
1443 | amdgpu_ring_pad_ib(ring, params.ib); |
1444 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1445 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1446 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1447 | if (r) |
1448 | goto error_free; | |
d38ceaf9 | 1449 | |
67003a15 | 1450 | amdgpu_bo_fence(vm->root.bo, f, true); |
284710fa CK |
1451 | dma_fence_put(*fence); |
1452 | *fence = f; | |
d38ceaf9 | 1453 | return 0; |
d5fc5e82 CZ |
1454 | |
1455 | error_free: | |
d71518b5 | 1456 | amdgpu_job_free(job); |
4af9f07c | 1457 | return r; |
d38ceaf9 AD |
1458 | } |
1459 | ||
a14faa65 CK |
1460 | /** |
1461 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1462 | * | |
1463 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1464 | * @exclusive: fence we need to sync to |
8358dcee CK |
1465 | * @gtt_flags: flags as they are used for GTT |
1466 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
1467 | * @vm: requested vm |
1468 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1469 | * @flags: HW flags for the mapping |
63e0ba40 | 1470 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1471 | * @fence: optional resulting fence |
1472 | * | |
1473 | * Split the mapping into smaller chunks so that each update fits | |
1474 | * into a SDMA IB. | |
1475 | * Returns 0 for success, -EINVAL for failure. | |
1476 | */ | |
1477 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1478 | struct dma_fence *exclusive, |
6b777607 | 1479 | uint64_t gtt_flags, |
8358dcee | 1480 | dma_addr_t *pages_addr, |
a14faa65 CK |
1481 | struct amdgpu_vm *vm, |
1482 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1483 | uint64_t flags, |
63e0ba40 | 1484 | struct drm_mm_node *nodes, |
f54d1867 | 1485 | struct dma_fence **fence) |
a14faa65 | 1486 | { |
a9f87f64 | 1487 | uint64_t pfn, src = 0, start = mapping->start; |
a14faa65 CK |
1488 | int r; |
1489 | ||
1490 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1491 | * but in case of something, we filter the flags in first place | |
1492 | */ | |
1493 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1494 | flags &= ~AMDGPU_PTE_READABLE; | |
1495 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1496 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1497 | ||
15b31c59 AX |
1498 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1499 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1500 | ||
b0fd18b0 AX |
1501 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1502 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1503 | ||
d0766e98 ZJ |
1504 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1505 | (adev->asic_type >= CHIP_VEGA10)) { | |
1506 | flags |= AMDGPU_PTE_PRT; | |
1507 | flags &= ~AMDGPU_PTE_VALID; | |
1508 | } | |
1509 | ||
a14faa65 CK |
1510 | trace_amdgpu_vm_bo_update(mapping); |
1511 | ||
63e0ba40 CK |
1512 | pfn = mapping->offset >> PAGE_SHIFT; |
1513 | if (nodes) { | |
1514 | while (pfn >= nodes->size) { | |
1515 | pfn -= nodes->size; | |
1516 | ++nodes; | |
1517 | } | |
fa3ab3c7 | 1518 | } |
a14faa65 | 1519 | |
63e0ba40 CK |
1520 | do { |
1521 | uint64_t max_entries; | |
1522 | uint64_t addr, last; | |
a14faa65 | 1523 | |
63e0ba40 CK |
1524 | if (nodes) { |
1525 | addr = nodes->start << PAGE_SHIFT; | |
1526 | max_entries = (nodes->size - pfn) * | |
1527 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1528 | } else { | |
1529 | addr = 0; | |
1530 | max_entries = S64_MAX; | |
1531 | } | |
a14faa65 | 1532 | |
63e0ba40 CK |
1533 | if (pages_addr) { |
1534 | if (flags == gtt_flags) | |
1535 | src = adev->gart.table_addr + | |
1536 | (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8; | |
1537 | else | |
1538 | max_entries = min(max_entries, 16ull * 1024ull); | |
1539 | addr = 0; | |
1540 | } else if (flags & AMDGPU_PTE_VALID) { | |
1541 | addr += adev->vm_manager.vram_base_offset; | |
1542 | } | |
1543 | addr += pfn << PAGE_SHIFT; | |
1544 | ||
a9f87f64 | 1545 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
3cabaa54 CK |
1546 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1547 | src, pages_addr, vm, | |
a14faa65 CK |
1548 | start, last, flags, addr, |
1549 | fence); | |
1550 | if (r) | |
1551 | return r; | |
1552 | ||
63e0ba40 CK |
1553 | pfn += last - start + 1; |
1554 | if (nodes && nodes->size == pfn) { | |
1555 | pfn = 0; | |
1556 | ++nodes; | |
1557 | } | |
a14faa65 | 1558 | start = last + 1; |
63e0ba40 | 1559 | |
a9f87f64 | 1560 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1561 | |
1562 | return 0; | |
1563 | } | |
1564 | ||
d38ceaf9 AD |
1565 | /** |
1566 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1567 | * | |
1568 | * @adev: amdgpu_device pointer | |
1569 | * @bo_va: requested BO and VM object | |
99e124f4 | 1570 | * @clear: if true clear the entries |
d38ceaf9 AD |
1571 | * |
1572 | * Fill in the page table entries for @bo_va. | |
1573 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1574 | */ |
1575 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1576 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1577 | bool clear) |
d38ceaf9 AD |
1578 | { |
1579 | struct amdgpu_vm *vm = bo_va->vm; | |
1580 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1581 | dma_addr_t *pages_addr = NULL; |
6b777607 | 1582 | uint64_t gtt_flags, flags; |
99e124f4 | 1583 | struct ttm_mem_reg *mem; |
63e0ba40 | 1584 | struct drm_mm_node *nodes; |
f54d1867 | 1585 | struct dma_fence *exclusive; |
d38ceaf9 AD |
1586 | int r; |
1587 | ||
a5f6b5b1 | 1588 | if (clear || !bo_va->bo) { |
99e124f4 | 1589 | mem = NULL; |
63e0ba40 | 1590 | nodes = NULL; |
99e124f4 CK |
1591 | exclusive = NULL; |
1592 | } else { | |
8358dcee CK |
1593 | struct ttm_dma_tt *ttm; |
1594 | ||
99e124f4 | 1595 | mem = &bo_va->bo->tbo.mem; |
63e0ba40 CK |
1596 | nodes = mem->mm_node; |
1597 | if (mem->mem_type == TTM_PL_TT) { | |
8358dcee CK |
1598 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1599 | ttm_dma_tt, ttm); | |
1600 | pages_addr = ttm->dma_address; | |
9ab21462 | 1601 | } |
3cabaa54 | 1602 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); |
d38ceaf9 AD |
1603 | } |
1604 | ||
a5f6b5b1 CK |
1605 | if (bo_va->bo) { |
1606 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); | |
1607 | gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && | |
1608 | adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? | |
1609 | flags : 0; | |
1610 | } else { | |
1611 | flags = 0x0; | |
1612 | gtt_flags = ~0x0; | |
1613 | } | |
d38ceaf9 | 1614 | |
7fc11959 CK |
1615 | spin_lock(&vm->status_lock); |
1616 | if (!list_empty(&bo_va->vm_status)) | |
1617 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1618 | spin_unlock(&vm->status_lock); | |
1619 | ||
1620 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1621 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1622 | gtt_flags, pages_addr, vm, | |
63e0ba40 | 1623 | mapping, flags, nodes, |
8358dcee | 1624 | &bo_va->last_pt_update); |
d38ceaf9 AD |
1625 | if (r) |
1626 | return r; | |
1627 | } | |
1628 | ||
d6c10f6b CK |
1629 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1630 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1631 | trace_amdgpu_vm_bo_mapping(mapping); | |
1632 | ||
1633 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1634 | trace_amdgpu_vm_bo_mapping(mapping); | |
1635 | } | |
1636 | ||
d38ceaf9 | 1637 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1638 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1639 | list_del_init(&bo_va->vm_status); |
99e124f4 | 1640 | if (clear) |
7fc11959 | 1641 | list_add(&bo_va->vm_status, &vm->cleared); |
d38ceaf9 AD |
1642 | spin_unlock(&vm->status_lock); |
1643 | ||
1644 | return 0; | |
1645 | } | |
1646 | ||
284710fa CK |
1647 | /** |
1648 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1649 | */ | |
1650 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1651 | { | |
1652 | unsigned long flags; | |
1653 | bool enable; | |
1654 | ||
1655 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1656 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
284710fa CK |
1657 | adev->gart.gart_funcs->set_prt(adev, enable); |
1658 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
1659 | } | |
1660 | ||
451bc8eb | 1661 | /** |
4388fc2a | 1662 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1663 | */ |
1664 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1665 | { | |
4388fc2a CK |
1666 | if (!adev->gart.gart_funcs->set_prt) |
1667 | return; | |
1668 | ||
451bc8eb CK |
1669 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1670 | amdgpu_vm_update_prt_state(adev); | |
1671 | } | |
1672 | ||
0b15f2fc CK |
1673 | /** |
1674 | * amdgpu_vm_prt_put - drop a PRT user | |
1675 | */ | |
1676 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1677 | { | |
451bc8eb | 1678 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1679 | amdgpu_vm_update_prt_state(adev); |
1680 | } | |
1681 | ||
284710fa | 1682 | /** |
451bc8eb | 1683 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1684 | */ |
1685 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1686 | { | |
1687 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1688 | ||
0b15f2fc | 1689 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1690 | kfree(cb); |
1691 | } | |
1692 | ||
451bc8eb CK |
1693 | /** |
1694 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1695 | */ | |
1696 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1697 | struct dma_fence *fence) | |
1698 | { | |
4388fc2a | 1699 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1700 | |
4388fc2a CK |
1701 | if (!adev->gart.gart_funcs->set_prt) |
1702 | return; | |
1703 | ||
1704 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1705 | if (!cb) { |
1706 | /* Last resort when we are OOM */ | |
1707 | if (fence) | |
1708 | dma_fence_wait(fence, false); | |
1709 | ||
486a68f5 | 1710 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1711 | } else { |
1712 | cb->adev = adev; | |
1713 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1714 | amdgpu_vm_prt_cb)) | |
1715 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1716 | } | |
1717 | } | |
1718 | ||
284710fa CK |
1719 | /** |
1720 | * amdgpu_vm_free_mapping - free a mapping | |
1721 | * | |
1722 | * @adev: amdgpu_device pointer | |
1723 | * @vm: requested vm | |
1724 | * @mapping: mapping to be freed | |
1725 | * @fence: fence of the unmap operation | |
1726 | * | |
1727 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1728 | */ | |
1729 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1730 | struct amdgpu_vm *vm, | |
1731 | struct amdgpu_bo_va_mapping *mapping, | |
1732 | struct dma_fence *fence) | |
1733 | { | |
451bc8eb CK |
1734 | if (mapping->flags & AMDGPU_PTE_PRT) |
1735 | amdgpu_vm_add_prt_cb(adev, fence); | |
1736 | kfree(mapping); | |
1737 | } | |
284710fa | 1738 | |
451bc8eb CK |
1739 | /** |
1740 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1741 | * | |
1742 | * @adev: amdgpu_device pointer | |
1743 | * @vm: requested vm | |
1744 | * | |
1745 | * Register a cleanup callback to disable PRT support after VM dies. | |
1746 | */ | |
1747 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1748 | { | |
67003a15 | 1749 | struct reservation_object *resv = vm->root.bo->tbo.resv; |
451bc8eb CK |
1750 | struct dma_fence *excl, **shared; |
1751 | unsigned i, shared_count; | |
1752 | int r; | |
0b15f2fc | 1753 | |
451bc8eb CK |
1754 | r = reservation_object_get_fences_rcu(resv, &excl, |
1755 | &shared_count, &shared); | |
1756 | if (r) { | |
1757 | /* Not enough memory to grab the fence list, as last resort | |
1758 | * block for all the fences to complete. | |
1759 | */ | |
1760 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1761 | MAX_SCHEDULE_TIMEOUT); | |
1762 | return; | |
284710fa | 1763 | } |
451bc8eb CK |
1764 | |
1765 | /* Add a callback for each fence in the reservation object */ | |
1766 | amdgpu_vm_prt_get(adev); | |
1767 | amdgpu_vm_add_prt_cb(adev, excl); | |
1768 | ||
1769 | for (i = 0; i < shared_count; ++i) { | |
1770 | amdgpu_vm_prt_get(adev); | |
1771 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1772 | } | |
1773 | ||
1774 | kfree(shared); | |
284710fa CK |
1775 | } |
1776 | ||
d38ceaf9 AD |
1777 | /** |
1778 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1779 | * | |
1780 | * @adev: amdgpu_device pointer | |
1781 | * @vm: requested vm | |
f3467818 NH |
1782 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1783 | * or if an error occurred) | |
d38ceaf9 AD |
1784 | * |
1785 | * Make sure all freed BOs are cleared in the PT. | |
1786 | * Returns 0 for success. | |
1787 | * | |
1788 | * PTs have to be reserved and mutex must be locked! | |
1789 | */ | |
1790 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1791 | struct amdgpu_vm *vm, |
1792 | struct dma_fence **fence) | |
d38ceaf9 AD |
1793 | { |
1794 | struct amdgpu_bo_va_mapping *mapping; | |
f3467818 | 1795 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1796 | int r; |
1797 | ||
1798 | while (!list_empty(&vm->freed)) { | |
1799 | mapping = list_first_entry(&vm->freed, | |
1800 | struct amdgpu_bo_va_mapping, list); | |
1801 | list_del(&mapping->list); | |
e17841b9 | 1802 | |
fc6aa33d CK |
1803 | r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm, |
1804 | mapping->start, mapping->last, | |
1805 | 0, 0, &f); | |
f3467818 | 1806 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1807 | if (r) { |
f3467818 | 1808 | dma_fence_put(f); |
d38ceaf9 | 1809 | return r; |
284710fa | 1810 | } |
f3467818 | 1811 | } |
d38ceaf9 | 1812 | |
f3467818 NH |
1813 | if (fence && f) { |
1814 | dma_fence_put(*fence); | |
1815 | *fence = f; | |
1816 | } else { | |
1817 | dma_fence_put(f); | |
d38ceaf9 | 1818 | } |
f3467818 | 1819 | |
d38ceaf9 AD |
1820 | return 0; |
1821 | ||
1822 | } | |
1823 | ||
1824 | /** | |
1825 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1826 | * | |
1827 | * @adev: amdgpu_device pointer | |
1828 | * @vm: requested vm | |
1829 | * | |
1830 | * Make sure all invalidated BOs are cleared in the PT. | |
1831 | * Returns 0 for success. | |
1832 | * | |
1833 | * PTs have to be reserved and mutex must be locked! | |
1834 | */ | |
1835 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1836 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1837 | { |
cfe2c978 | 1838 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1839 | int r = 0; |
d38ceaf9 AD |
1840 | |
1841 | spin_lock(&vm->status_lock); | |
1842 | while (!list_empty(&vm->invalidated)) { | |
1843 | bo_va = list_first_entry(&vm->invalidated, | |
1844 | struct amdgpu_bo_va, vm_status); | |
1845 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1846 | |
99e124f4 | 1847 | r = amdgpu_vm_bo_update(adev, bo_va, true); |
d38ceaf9 AD |
1848 | if (r) |
1849 | return r; | |
1850 | ||
1851 | spin_lock(&vm->status_lock); | |
1852 | } | |
1853 | spin_unlock(&vm->status_lock); | |
1854 | ||
cfe2c978 | 1855 | if (bo_va) |
bb1e38a4 | 1856 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1857 | |
1858 | return r; | |
d38ceaf9 AD |
1859 | } |
1860 | ||
1861 | /** | |
1862 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1863 | * | |
1864 | * @adev: amdgpu_device pointer | |
1865 | * @vm: requested vm | |
1866 | * @bo: amdgpu buffer object | |
1867 | * | |
8843dbbb | 1868 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1869 | * Add @bo to the list of bos associated with the vm |
1870 | * Returns newly added bo_va or NULL for failure | |
1871 | * | |
1872 | * Object has to be reserved! | |
1873 | */ | |
1874 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1875 | struct amdgpu_vm *vm, | |
1876 | struct amdgpu_bo *bo) | |
1877 | { | |
1878 | struct amdgpu_bo_va *bo_va; | |
1879 | ||
1880 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1881 | if (bo_va == NULL) { | |
1882 | return NULL; | |
1883 | } | |
1884 | bo_va->vm = vm; | |
1885 | bo_va->bo = bo; | |
d38ceaf9 AD |
1886 | bo_va->ref_count = 1; |
1887 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1888 | INIT_LIST_HEAD(&bo_va->valids); |
1889 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1890 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1891 | |
a5f6b5b1 CK |
1892 | if (bo) |
1893 | list_add_tail(&bo_va->bo_list, &bo->va); | |
d38ceaf9 AD |
1894 | |
1895 | return bo_va; | |
1896 | } | |
1897 | ||
1898 | /** | |
1899 | * amdgpu_vm_bo_map - map bo inside a vm | |
1900 | * | |
1901 | * @adev: amdgpu_device pointer | |
1902 | * @bo_va: bo_va to store the address | |
1903 | * @saddr: where to map the BO | |
1904 | * @offset: requested offset in the BO | |
1905 | * @flags: attributes of pages (read/write/valid/etc.) | |
1906 | * | |
1907 | * Add a mapping of the BO at the specefied addr into the VM. | |
1908 | * Returns 0 for success, error for failure. | |
1909 | * | |
49b02b18 | 1910 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1911 | */ |
1912 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1913 | struct amdgpu_bo_va *bo_va, | |
1914 | uint64_t saddr, uint64_t offset, | |
268c3001 | 1915 | uint64_t size, uint64_t flags) |
d38ceaf9 | 1916 | { |
a9f87f64 | 1917 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
d38ceaf9 | 1918 | struct amdgpu_vm *vm = bo_va->vm; |
d38ceaf9 | 1919 | uint64_t eaddr; |
d38ceaf9 | 1920 | |
0be52de9 CK |
1921 | /* validate the parameters */ |
1922 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1923 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1924 | return -EINVAL; |
0be52de9 | 1925 | |
d38ceaf9 | 1926 | /* make sure object fit at this offset */ |
005ae95e | 1927 | eaddr = saddr + size - 1; |
a5f6b5b1 CK |
1928 | if (saddr >= eaddr || |
1929 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
d38ceaf9 | 1930 | return -EINVAL; |
d38ceaf9 | 1931 | |
d38ceaf9 AD |
1932 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1933 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1934 | ||
a9f87f64 CK |
1935 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
1936 | if (tmp) { | |
d38ceaf9 AD |
1937 | /* bo and tmp overlap, invalid addr */ |
1938 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
a9f87f64 CK |
1939 | "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr, |
1940 | tmp->start, tmp->last + 1); | |
663e4577 | 1941 | return -EINVAL; |
d38ceaf9 AD |
1942 | } |
1943 | ||
1944 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
1945 | if (!mapping) |
1946 | return -ENOMEM; | |
d38ceaf9 AD |
1947 | |
1948 | INIT_LIST_HEAD(&mapping->list); | |
a9f87f64 CK |
1949 | mapping->start = saddr; |
1950 | mapping->last = eaddr; | |
d38ceaf9 AD |
1951 | mapping->offset = offset; |
1952 | mapping->flags = flags; | |
1953 | ||
7fc11959 | 1954 | list_add(&mapping->list, &bo_va->invalids); |
a9f87f64 | 1955 | amdgpu_vm_it_insert(mapping, &vm->va); |
80f95c57 CK |
1956 | |
1957 | if (flags & AMDGPU_PTE_PRT) | |
1958 | amdgpu_vm_prt_get(adev); | |
1959 | ||
1960 | return 0; | |
1961 | } | |
1962 | ||
1963 | /** | |
1964 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
1965 | * | |
1966 | * @adev: amdgpu_device pointer | |
1967 | * @bo_va: bo_va to store the address | |
1968 | * @saddr: where to map the BO | |
1969 | * @offset: requested offset in the BO | |
1970 | * @flags: attributes of pages (read/write/valid/etc.) | |
1971 | * | |
1972 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
1973 | * mappings as we do so. | |
1974 | * Returns 0 for success, error for failure. | |
1975 | * | |
1976 | * Object has to be reserved and unreserved outside! | |
1977 | */ | |
1978 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
1979 | struct amdgpu_bo_va *bo_va, | |
1980 | uint64_t saddr, uint64_t offset, | |
1981 | uint64_t size, uint64_t flags) | |
1982 | { | |
1983 | struct amdgpu_bo_va_mapping *mapping; | |
1984 | struct amdgpu_vm *vm = bo_va->vm; | |
1985 | uint64_t eaddr; | |
1986 | int r; | |
1987 | ||
1988 | /* validate the parameters */ | |
1989 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
1990 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
1991 | return -EINVAL; | |
1992 | ||
1993 | /* make sure object fit at this offset */ | |
1994 | eaddr = saddr + size - 1; | |
1995 | if (saddr >= eaddr || | |
1996 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
1997 | return -EINVAL; | |
1998 | ||
1999 | /* Allocate all the needed memory */ | |
2000 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2001 | if (!mapping) | |
2002 | return -ENOMEM; | |
2003 | ||
2004 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size); | |
2005 | if (r) { | |
2006 | kfree(mapping); | |
2007 | return r; | |
2008 | } | |
2009 | ||
2010 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2011 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2012 | ||
a9f87f64 CK |
2013 | mapping->start = saddr; |
2014 | mapping->last = eaddr; | |
80f95c57 CK |
2015 | mapping->offset = offset; |
2016 | mapping->flags = flags; | |
2017 | ||
2018 | list_add(&mapping->list, &bo_va->invalids); | |
a9f87f64 | 2019 | amdgpu_vm_it_insert(mapping, &vm->va); |
d38ceaf9 | 2020 | |
4388fc2a CK |
2021 | if (flags & AMDGPU_PTE_PRT) |
2022 | amdgpu_vm_prt_get(adev); | |
2023 | ||
d38ceaf9 | 2024 | return 0; |
d38ceaf9 AD |
2025 | } |
2026 | ||
2027 | /** | |
2028 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2029 | * | |
2030 | * @adev: amdgpu_device pointer | |
2031 | * @bo_va: bo_va to remove the address from | |
2032 | * @saddr: where to the BO is mapped | |
2033 | * | |
2034 | * Remove a mapping of the BO at the specefied addr from the VM. | |
2035 | * Returns 0 for success, error for failure. | |
2036 | * | |
49b02b18 | 2037 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2038 | */ |
2039 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2040 | struct amdgpu_bo_va *bo_va, | |
2041 | uint64_t saddr) | |
2042 | { | |
2043 | struct amdgpu_bo_va_mapping *mapping; | |
2044 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 2045 | bool valid = true; |
d38ceaf9 | 2046 | |
6c7fc503 | 2047 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2048 | |
7fc11959 | 2049 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2050 | if (mapping->start == saddr) |
d38ceaf9 AD |
2051 | break; |
2052 | } | |
2053 | ||
7fc11959 CK |
2054 | if (&mapping->list == &bo_va->valids) { |
2055 | valid = false; | |
2056 | ||
2057 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2058 | if (mapping->start == saddr) |
7fc11959 CK |
2059 | break; |
2060 | } | |
2061 | ||
32b41ac2 | 2062 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2063 | return -ENOENT; |
d38ceaf9 | 2064 | } |
32b41ac2 | 2065 | |
d38ceaf9 | 2066 | list_del(&mapping->list); |
a9f87f64 | 2067 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2068 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2069 | |
e17841b9 | 2070 | if (valid) |
d38ceaf9 | 2071 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2072 | else |
284710fa CK |
2073 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2074 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2075 | |
2076 | return 0; | |
2077 | } | |
2078 | ||
dc54d3d1 CK |
2079 | /** |
2080 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2081 | * | |
2082 | * @adev: amdgpu_device pointer | |
2083 | * @vm: VM structure to use | |
2084 | * @saddr: start of the range | |
2085 | * @size: size of the range | |
2086 | * | |
2087 | * Remove all mappings in a range, split them as appropriate. | |
2088 | * Returns 0 for success, error for failure. | |
2089 | */ | |
2090 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2091 | struct amdgpu_vm *vm, | |
2092 | uint64_t saddr, uint64_t size) | |
2093 | { | |
2094 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2095 | LIST_HEAD(removed); |
2096 | uint64_t eaddr; | |
2097 | ||
2098 | eaddr = saddr + size - 1; | |
2099 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2100 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2101 | ||
2102 | /* Allocate all the needed memory */ | |
2103 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2104 | if (!before) | |
2105 | return -ENOMEM; | |
27f6d610 | 2106 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2107 | |
2108 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2109 | if (!after) { | |
2110 | kfree(before); | |
2111 | return -ENOMEM; | |
2112 | } | |
27f6d610 | 2113 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2114 | |
2115 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2116 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2117 | while (tmp) { | |
dc54d3d1 | 2118 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2119 | if (tmp->start < saddr) { |
2120 | before->start = tmp->start; | |
2121 | before->last = saddr - 1; | |
dc54d3d1 CK |
2122 | before->offset = tmp->offset; |
2123 | before->flags = tmp->flags; | |
2124 | list_add(&before->list, &tmp->list); | |
2125 | } | |
2126 | ||
2127 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2128 | if (tmp->last > eaddr) { |
2129 | after->start = eaddr + 1; | |
2130 | after->last = tmp->last; | |
dc54d3d1 | 2131 | after->offset = tmp->offset; |
a9f87f64 | 2132 | after->offset += after->start - tmp->start; |
dc54d3d1 CK |
2133 | after->flags = tmp->flags; |
2134 | list_add(&after->list, &tmp->list); | |
2135 | } | |
2136 | ||
2137 | list_del(&tmp->list); | |
2138 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2139 | |
2140 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2141 | } |
2142 | ||
2143 | /* And free them up */ | |
2144 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2145 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2146 | list_del(&tmp->list); |
2147 | ||
a9f87f64 CK |
2148 | if (tmp->start < saddr) |
2149 | tmp->start = saddr; | |
2150 | if (tmp->last > eaddr) | |
2151 | tmp->last = eaddr; | |
dc54d3d1 CK |
2152 | |
2153 | list_add(&tmp->list, &vm->freed); | |
2154 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2155 | } | |
2156 | ||
27f6d610 JZ |
2157 | /* Insert partial mapping before the range */ |
2158 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2159 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2160 | if (before->flags & AMDGPU_PTE_PRT) |
2161 | amdgpu_vm_prt_get(adev); | |
2162 | } else { | |
2163 | kfree(before); | |
2164 | } | |
2165 | ||
2166 | /* Insert partial mapping after the range */ | |
27f6d610 | 2167 | if (!list_empty(&after->list)) { |
a9f87f64 | 2168 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2169 | if (after->flags & AMDGPU_PTE_PRT) |
2170 | amdgpu_vm_prt_get(adev); | |
2171 | } else { | |
2172 | kfree(after); | |
2173 | } | |
2174 | ||
2175 | return 0; | |
2176 | } | |
2177 | ||
d38ceaf9 AD |
2178 | /** |
2179 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2180 | * | |
2181 | * @adev: amdgpu_device pointer | |
2182 | * @bo_va: requested bo_va | |
2183 | * | |
8843dbbb | 2184 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2185 | * |
2186 | * Object have to be reserved! | |
2187 | */ | |
2188 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2189 | struct amdgpu_bo_va *bo_va) | |
2190 | { | |
2191 | struct amdgpu_bo_va_mapping *mapping, *next; | |
2192 | struct amdgpu_vm *vm = bo_va->vm; | |
2193 | ||
2194 | list_del(&bo_va->bo_list); | |
2195 | ||
d38ceaf9 AD |
2196 | spin_lock(&vm->status_lock); |
2197 | list_del(&bo_va->vm_status); | |
2198 | spin_unlock(&vm->status_lock); | |
2199 | ||
7fc11959 | 2200 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2201 | list_del(&mapping->list); |
a9f87f64 | 2202 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2203 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2204 | list_add(&mapping->list, &vm->freed); |
2205 | } | |
2206 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2207 | list_del(&mapping->list); | |
a9f87f64 | 2208 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2209 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2210 | bo_va->last_pt_update); | |
d38ceaf9 | 2211 | } |
32b41ac2 | 2212 | |
f54d1867 | 2213 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2214 | kfree(bo_va); |
d38ceaf9 AD |
2215 | } |
2216 | ||
2217 | /** | |
2218 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2219 | * | |
2220 | * @adev: amdgpu_device pointer | |
2221 | * @vm: requested vm | |
2222 | * @bo: amdgpu buffer object | |
2223 | * | |
8843dbbb | 2224 | * Mark @bo as invalid. |
d38ceaf9 AD |
2225 | */ |
2226 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
2227 | struct amdgpu_bo *bo) | |
2228 | { | |
2229 | struct amdgpu_bo_va *bo_va; | |
2230 | ||
2231 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
2232 | spin_lock(&bo_va->vm->status_lock); |
2233 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 2234 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 2235 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
2236 | } |
2237 | } | |
2238 | ||
bab4fee7 JZ |
2239 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2240 | { | |
2241 | /* Total bits covered by PD + PTs */ | |
2242 | unsigned bits = ilog2(vm_size) + 18; | |
2243 | ||
2244 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2245 | Above that split equal between PD and PTs */ | |
2246 | if (vm_size <= 8) | |
2247 | return (bits - 9); | |
2248 | else | |
2249 | return ((bits + 3) / 2); | |
2250 | } | |
2251 | ||
2252 | /** | |
2253 | * amdgpu_vm_adjust_size - adjust vm size and block size | |
2254 | * | |
2255 | * @adev: amdgpu_device pointer | |
2256 | * @vm_size: the default vm size if it's set auto | |
2257 | */ | |
2258 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) | |
2259 | { | |
2260 | /* adjust vm size firstly */ | |
2261 | if (amdgpu_vm_size == -1) | |
2262 | adev->vm_manager.vm_size = vm_size; | |
2263 | else | |
2264 | adev->vm_manager.vm_size = amdgpu_vm_size; | |
2265 | ||
2266 | /* block size depends on vm size */ | |
2267 | if (amdgpu_vm_block_size == -1) | |
2268 | adev->vm_manager.block_size = | |
2269 | amdgpu_vm_get_block_size(adev->vm_manager.vm_size); | |
2270 | else | |
2271 | adev->vm_manager.block_size = amdgpu_vm_block_size; | |
2272 | ||
2273 | DRM_INFO("vm size is %llu GB, block size is %u-bit\n", | |
2274 | adev->vm_manager.vm_size, adev->vm_manager.block_size); | |
2275 | } | |
2276 | ||
d38ceaf9 AD |
2277 | /** |
2278 | * amdgpu_vm_init - initialize a vm instance | |
2279 | * | |
2280 | * @adev: amdgpu_device pointer | |
2281 | * @vm: requested vm | |
2282 | * | |
8843dbbb | 2283 | * Init @vm fields. |
d38ceaf9 AD |
2284 | */ |
2285 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2286 | { | |
2287 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
36b32a68 | 2288 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2289 | unsigned ring_instance; |
2290 | struct amdgpu_ring *ring; | |
2bd9ccfa | 2291 | struct amd_sched_rq *rq; |
36bbf3bf | 2292 | int r, i; |
d38ceaf9 | 2293 | |
d38ceaf9 | 2294 | vm->va = RB_ROOT; |
031e2983 | 2295 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
36bbf3bf CZ |
2296 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2297 | vm->reserved_vmid[i] = NULL; | |
d38ceaf9 AD |
2298 | spin_lock_init(&vm->status_lock); |
2299 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 2300 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 2301 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2302 | |
2bd9ccfa | 2303 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2304 | |
2305 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2306 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2307 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
2308 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
2309 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
2310 | rq, amdgpu_sched_jobs); | |
2311 | if (r) | |
f566ceb1 | 2312 | return r; |
2bd9ccfa | 2313 | |
a24960f3 | 2314 | vm->last_dir_update = NULL; |
05906dec | 2315 | |
f566ceb1 | 2316 | r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, |
857d913d | 2317 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f | 2318 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
03f48dd5 | 2319 | AMDGPU_GEM_CREATE_SHADOW | |
617859e0 CK |
2320 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
2321 | AMDGPU_GEM_CREATE_VRAM_CLEARED, | |
67003a15 | 2322 | NULL, NULL, &vm->root.bo); |
d38ceaf9 | 2323 | if (r) |
2bd9ccfa CK |
2324 | goto error_free_sched_entity; |
2325 | ||
67003a15 | 2326 | r = amdgpu_bo_reserve(vm->root.bo, false); |
2bd9ccfa | 2327 | if (r) |
67003a15 | 2328 | goto error_free_root; |
2bd9ccfa | 2329 | |
5a712a87 | 2330 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
67003a15 | 2331 | amdgpu_bo_unreserve(vm->root.bo); |
d38ceaf9 AD |
2332 | |
2333 | return 0; | |
2bd9ccfa | 2334 | |
67003a15 CK |
2335 | error_free_root: |
2336 | amdgpu_bo_unref(&vm->root.bo->shadow); | |
2337 | amdgpu_bo_unref(&vm->root.bo); | |
2338 | vm->root.bo = NULL; | |
2bd9ccfa CK |
2339 | |
2340 | error_free_sched_entity: | |
2341 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
2342 | ||
2343 | return r; | |
d38ceaf9 AD |
2344 | } |
2345 | ||
f566ceb1 CK |
2346 | /** |
2347 | * amdgpu_vm_free_levels - free PD/PT levels | |
2348 | * | |
2349 | * @level: PD/PT starting level to free | |
2350 | * | |
2351 | * Free the page directory or page table level and all sub levels. | |
2352 | */ | |
2353 | static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) | |
2354 | { | |
2355 | unsigned i; | |
2356 | ||
2357 | if (level->bo) { | |
2358 | amdgpu_bo_unref(&level->bo->shadow); | |
2359 | amdgpu_bo_unref(&level->bo); | |
2360 | } | |
2361 | ||
2362 | if (level->entries) | |
2363 | for (i = 0; i <= level->last_entry_used; i++) | |
2364 | amdgpu_vm_free_levels(&level->entries[i]); | |
2365 | ||
2366 | drm_free_large(level->entries); | |
2367 | } | |
2368 | ||
d38ceaf9 AD |
2369 | /** |
2370 | * amdgpu_vm_fini - tear down a vm instance | |
2371 | * | |
2372 | * @adev: amdgpu_device pointer | |
2373 | * @vm: requested vm | |
2374 | * | |
8843dbbb | 2375 | * Tear down @vm. |
d38ceaf9 AD |
2376 | * Unbind the VM and remove all bos from the vm bo list |
2377 | */ | |
2378 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2379 | { | |
2380 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
4388fc2a | 2381 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
36bbf3bf | 2382 | int i; |
d38ceaf9 | 2383 | |
2d55e45a | 2384 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 2385 | |
d38ceaf9 AD |
2386 | if (!RB_EMPTY_ROOT(&vm->va)) { |
2387 | dev_err(adev->dev, "still active bo inside vm\n"); | |
2388 | } | |
a9f87f64 | 2389 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) { |
d38ceaf9 | 2390 | list_del(&mapping->list); |
a9f87f64 | 2391 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2392 | kfree(mapping); |
2393 | } | |
2394 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2395 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2396 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2397 | prt_fini_needed = false; |
451bc8eb | 2398 | } |
284710fa | 2399 | |
d38ceaf9 | 2400 | list_del(&mapping->list); |
451bc8eb | 2401 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2402 | } |
2403 | ||
f566ceb1 | 2404 | amdgpu_vm_free_levels(&vm->root); |
a24960f3 | 2405 | dma_fence_put(vm->last_dir_update); |
1e9ef26f CZ |
2406 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2407 | amdgpu_vm_free_reserved_vmid(adev, vm, i); | |
d38ceaf9 | 2408 | } |
ea89f8c9 | 2409 | |
a9a78b32 CK |
2410 | /** |
2411 | * amdgpu_vm_manager_init - init the VM manager | |
2412 | * | |
2413 | * @adev: amdgpu_device pointer | |
2414 | * | |
2415 | * Initialize the VM manager structures | |
2416 | */ | |
2417 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2418 | { | |
7645670d CK |
2419 | unsigned i, j; |
2420 | ||
2421 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
2422 | struct amdgpu_vm_id_manager *id_mgr = | |
2423 | &adev->vm_manager.id_mgr[i]; | |
a9a78b32 | 2424 | |
7645670d CK |
2425 | mutex_init(&id_mgr->lock); |
2426 | INIT_LIST_HEAD(&id_mgr->ids_lru); | |
c3505770 | 2427 | atomic_set(&id_mgr->reserved_vmid_num, 0); |
a9a78b32 | 2428 | |
7645670d CK |
2429 | /* skip over VMID 0, since it is the system VM */ |
2430 | for (j = 1; j < id_mgr->num_ids; ++j) { | |
2431 | amdgpu_vm_reset_id(adev, i, j); | |
2432 | amdgpu_sync_create(&id_mgr->ids[i].active); | |
2433 | list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); | |
2434 | } | |
971fe9a9 | 2435 | } |
2d55e45a | 2436 | |
f54d1867 CW |
2437 | adev->vm_manager.fence_context = |
2438 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2439 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2440 | adev->vm_manager.seqno[i] = 0; | |
2441 | ||
2d55e45a | 2442 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 2443 | atomic64_set(&adev->vm_manager.client_counter, 0); |
284710fa | 2444 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2445 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
a9a78b32 CK |
2446 | } |
2447 | ||
ea89f8c9 CK |
2448 | /** |
2449 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2450 | * | |
2451 | * @adev: amdgpu_device pointer | |
2452 | * | |
2453 | * Cleanup the VM manager and free resources. | |
2454 | */ | |
2455 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2456 | { | |
7645670d | 2457 | unsigned i, j; |
ea89f8c9 | 2458 | |
7645670d CK |
2459 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
2460 | struct amdgpu_vm_id_manager *id_mgr = | |
2461 | &adev->vm_manager.id_mgr[i]; | |
bcb1ba35 | 2462 | |
7645670d CK |
2463 | mutex_destroy(&id_mgr->lock); |
2464 | for (j = 0; j < AMDGPU_NUM_VM; ++j) { | |
2465 | struct amdgpu_vm_id *id = &id_mgr->ids[j]; | |
2466 | ||
2467 | amdgpu_sync_free(&id->active); | |
2468 | dma_fence_put(id->flushed_updates); | |
2469 | dma_fence_put(id->last_flush); | |
2470 | } | |
bcb1ba35 | 2471 | } |
ea89f8c9 | 2472 | } |
cfbcacf4 CZ |
2473 | |
2474 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
2475 | { | |
2476 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
2477 | struct amdgpu_device *adev = dev->dev_private; |
2478 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
2479 | int r; | |
cfbcacf4 CZ |
2480 | |
2481 | switch (args->in.op) { | |
2482 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f CZ |
2483 | /* current, we only have requirement to reserve vmid from gfxhub */ |
2484 | r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm, | |
2485 | AMDGPU_GFXHUB); | |
2486 | if (r) | |
2487 | return r; | |
2488 | break; | |
cfbcacf4 | 2489 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
1e9ef26f | 2490 | amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
2491 | break; |
2492 | default: | |
2493 | return -EINVAL; | |
2494 | } | |
2495 | ||
2496 | return 0; | |
2497 | } |