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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
d38ceaf9 AD |
29 | #include <drm/drmP.h> |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu.h" | |
32 | #include "amdgpu_trace.h" | |
33 | ||
34 | /* | |
35 | * GPUVM | |
36 | * GPUVM is similar to the legacy gart on older asics, however | |
37 | * rather than there being a single global gart table | |
38 | * for the entire GPU, there are multiple VM page tables active | |
39 | * at any given time. The VM page tables can contain a mix | |
40 | * vram pages and system memory pages and system memory pages | |
41 | * can be mapped as snooped (cached system pages) or unsnooped | |
42 | * (uncached system pages). | |
43 | * Each VM has an ID associated with it and there is a page table | |
44 | * associated with each VMID. When execting a command buffer, | |
45 | * the kernel tells the the ring what VMID to use for that command | |
46 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
47 | * The userspace drivers maintain their own address space and the kernel | |
48 | * sets up their pages tables accordingly when they submit their | |
49 | * command buffers and a VMID is assigned. | |
50 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
51 | * SI supports 16. | |
52 | */ | |
53 | ||
f4833c4f HK |
54 | /* Local structure. Encapsulate some VM table update parameters to reduce |
55 | * the number of function parameters | |
56 | */ | |
29efc4f5 | 57 | struct amdgpu_pte_update_params { |
27c5f36f CK |
58 | /* amdgpu device we do this update for */ |
59 | struct amdgpu_device *adev; | |
49ac8a24 CK |
60 | /* optional amdgpu_vm we do this update for */ |
61 | struct amdgpu_vm *vm; | |
f4833c4f HK |
62 | /* address where to copy page table entries from */ |
63 | uint64_t src; | |
f4833c4f HK |
64 | /* indirect buffer to fill with commands */ |
65 | struct amdgpu_ib *ib; | |
afef8b8f CK |
66 | /* Function which actually does the update */ |
67 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
68 | uint64_t addr, unsigned count, uint32_t incr, | |
6b777607 | 69 | uint64_t flags); |
4c7e8855 CZ |
70 | /* indicate update pt or its shadow */ |
71 | bool shadow; | |
f4833c4f HK |
72 | }; |
73 | ||
284710fa CK |
74 | /* Helper to disable partial resident texture feature from a fence callback */ |
75 | struct amdgpu_prt_cb { | |
76 | struct amdgpu_device *adev; | |
77 | struct dma_fence_cb cb; | |
78 | }; | |
79 | ||
d38ceaf9 AD |
80 | /** |
81 | * amdgpu_vm_num_pde - return the number of page directory entries | |
82 | * | |
83 | * @adev: amdgpu_device pointer | |
84 | * | |
8843dbbb | 85 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
86 | */ |
87 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
88 | { | |
89 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
90 | } | |
91 | ||
92 | /** | |
93 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
94 | * | |
95 | * @adev: amdgpu_device pointer | |
96 | * | |
8843dbbb | 97 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
98 | */ |
99 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
100 | { | |
101 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
102 | } | |
103 | ||
104 | /** | |
56467ebf | 105 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
106 | * |
107 | * @vm: vm providing the BOs | |
3c0eea6c | 108 | * @validated: head of validation list |
56467ebf | 109 | * @entry: entry to add |
d38ceaf9 AD |
110 | * |
111 | * Add the page directory to the list of BOs to | |
56467ebf | 112 | * validate for command submission. |
d38ceaf9 | 113 | */ |
56467ebf CK |
114 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
115 | struct list_head *validated, | |
116 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 117 | { |
67003a15 | 118 | entry->robj = vm->root.bo; |
56467ebf | 119 | entry->priority = 0; |
67003a15 | 120 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 121 | entry->tv.shared = true; |
2f568dbd | 122 | entry->user_pages = NULL; |
56467ebf CK |
123 | list_add(&entry->tv.head, validated); |
124 | } | |
d38ceaf9 | 125 | |
56467ebf | 126 | /** |
f7da30d9 | 127 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
56467ebf | 128 | * |
5a712a87 | 129 | * @adev: amdgpu device pointer |
56467ebf | 130 | * @vm: vm providing the BOs |
f7da30d9 CK |
131 | * @validate: callback to do the validation |
132 | * @param: parameter for the validation callback | |
d38ceaf9 | 133 | * |
f7da30d9 | 134 | * Validate the page table BOs on command submission if neccessary. |
d38ceaf9 | 135 | */ |
f7da30d9 CK |
136 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
137 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
138 | void *param) | |
d38ceaf9 | 139 | { |
5a712a87 | 140 | uint64_t num_evictions; |
ee1782c3 | 141 | unsigned i; |
f7da30d9 | 142 | int r; |
d38ceaf9 | 143 | |
5a712a87 CK |
144 | /* We only need to validate the page tables |
145 | * if they aren't already valid. | |
146 | */ | |
147 | num_evictions = atomic64_read(&adev->num_evictions); | |
148 | if (num_evictions == vm->last_eviction_counter) | |
f7da30d9 | 149 | return 0; |
5a712a87 | 150 | |
d38ceaf9 | 151 | /* add the vm page table to the list */ |
67003a15 CK |
152 | for (i = 0; i <= vm->root.last_entry_used; ++i) { |
153 | struct amdgpu_bo *bo = vm->root.entries[i].bo; | |
ee1782c3 | 154 | |
914b4dce | 155 | if (!bo) |
d38ceaf9 AD |
156 | continue; |
157 | ||
914b4dce | 158 | r = validate(param, bo); |
f7da30d9 CK |
159 | if (r) |
160 | return r; | |
d38ceaf9 | 161 | } |
eceb8a15 | 162 | |
f7da30d9 | 163 | return 0; |
eceb8a15 CK |
164 | } |
165 | ||
166 | /** | |
167 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
168 | * | |
169 | * @adev: amdgpu device instance | |
170 | * @vm: vm providing the BOs | |
171 | * | |
172 | * Move the PT BOs to the tail of the LRU. | |
173 | */ | |
174 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
175 | struct amdgpu_vm *vm) | |
176 | { | |
177 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
178 | unsigned i; | |
179 | ||
180 | spin_lock(&glob->lru_lock); | |
67003a15 CK |
181 | for (i = 0; i <= vm->root.last_entry_used; ++i) { |
182 | struct amdgpu_bo *bo = vm->root.entries[i].bo; | |
eceb8a15 | 183 | |
914b4dce | 184 | if (!bo) |
eceb8a15 CK |
185 | continue; |
186 | ||
914b4dce | 187 | ttm_bo_move_to_lru_tail(&bo->tbo); |
eceb8a15 CK |
188 | } |
189 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
190 | } |
191 | ||
663e4577 CK |
192 | /** |
193 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
194 | * | |
195 | * @adev: amdgpu_device pointer | |
196 | * @vm: VM to allocate page tables for | |
197 | * @saddr: Start address which needs to be allocated | |
198 | * @size: Size from start address we need. | |
199 | * | |
200 | * Make sure the page tables are allocated. | |
201 | */ | |
202 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
203 | struct amdgpu_vm *vm, | |
204 | uint64_t saddr, uint64_t size) | |
205 | { | |
206 | unsigned last_pfn, pt_idx; | |
207 | uint64_t eaddr; | |
208 | int r; | |
209 | ||
210 | /* validate the parameters */ | |
211 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
212 | return -EINVAL; | |
213 | ||
214 | eaddr = saddr + size - 1; | |
215 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
216 | if (last_pfn >= adev->vm_manager.max_pfn) { | |
217 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
218 | last_pfn, adev->vm_manager.max_pfn); | |
219 | return -EINVAL; | |
220 | } | |
221 | ||
222 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
223 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
224 | ||
225 | saddr >>= amdgpu_vm_block_size; | |
226 | eaddr >>= amdgpu_vm_block_size; | |
227 | ||
228 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
229 | ||
67003a15 CK |
230 | if (eaddr > vm->root.last_entry_used) |
231 | vm->root.last_entry_used = eaddr; | |
663e4577 CK |
232 | |
233 | /* walk over the address space and allocate the page tables */ | |
234 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
67003a15 | 235 | struct reservation_object *resv = vm->root.bo->tbo.resv; |
663e4577 CK |
236 | struct amdgpu_bo *pt; |
237 | ||
67003a15 | 238 | if (vm->root.entries[pt_idx].bo) |
663e4577 CK |
239 | continue; |
240 | ||
241 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, | |
242 | AMDGPU_GPU_PAGE_SIZE, true, | |
243 | AMDGPU_GEM_DOMAIN_VRAM, | |
244 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
245 | AMDGPU_GEM_CREATE_SHADOW | | |
246 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
247 | AMDGPU_GEM_CREATE_VRAM_CLEARED, | |
248 | NULL, resv, &pt); | |
249 | if (r) | |
250 | return r; | |
251 | ||
252 | /* Keep a reference to the page table to avoid freeing | |
253 | * them up in the wrong order. | |
254 | */ | |
67003a15 | 255 | pt->parent = amdgpu_bo_ref(vm->root.bo); |
663e4577 | 256 | |
67003a15 CK |
257 | vm->root.entries[pt_idx].bo = pt; |
258 | vm->root.entries[pt_idx].addr = 0; | |
663e4577 CK |
259 | } |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
192b7dcb CZ |
264 | static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev, |
265 | struct amdgpu_vm_id *id) | |
266 | { | |
267 | return id->current_gpu_reset_count != | |
268 | atomic_read(&adev->gpu_reset_counter) ? true : false; | |
269 | } | |
270 | ||
d38ceaf9 AD |
271 | /** |
272 | * amdgpu_vm_grab_id - allocate the next free VMID | |
273 | * | |
d38ceaf9 | 274 | * @vm: vm to allocate id for |
7f8a5290 CK |
275 | * @ring: ring we want to submit job to |
276 | * @sync: sync object where we add dependencies | |
94dd0a4a | 277 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 278 | * |
7f8a5290 | 279 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 280 | */ |
7f8a5290 | 281 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
f54d1867 | 282 | struct amdgpu_sync *sync, struct dma_fence *fence, |
fd53be30 | 283 | struct amdgpu_job *job) |
d38ceaf9 | 284 | { |
d38ceaf9 | 285 | struct amdgpu_device *adev = ring->adev; |
090b767e | 286 | uint64_t fence_context = adev->fence_context + ring->idx; |
f54d1867 | 287 | struct dma_fence *updates = sync->last_vm_update; |
8d76001e | 288 | struct amdgpu_vm_id *id, *idle; |
f54d1867 | 289 | struct dma_fence **fences; |
1fbb2e92 CK |
290 | unsigned i; |
291 | int r = 0; | |
292 | ||
293 | fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids, | |
294 | GFP_KERNEL); | |
295 | if (!fences) | |
296 | return -ENOMEM; | |
d38ceaf9 | 297 | |
94dd0a4a CK |
298 | mutex_lock(&adev->vm_manager.lock); |
299 | ||
36fd7c5c | 300 | /* Check if we have an idle VMID */ |
1fbb2e92 | 301 | i = 0; |
8d76001e | 302 | list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) { |
1fbb2e92 CK |
303 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
304 | if (!fences[i]) | |
36fd7c5c | 305 | break; |
1fbb2e92 | 306 | ++i; |
36fd7c5c CK |
307 | } |
308 | ||
1fbb2e92 | 309 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
8d76001e | 310 | if (&idle->list == &adev->vm_manager.ids_lru) { |
1fbb2e92 CK |
311 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
312 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
f54d1867 | 313 | struct dma_fence_array *array; |
1fbb2e92 CK |
314 | unsigned j; |
315 | ||
316 | for (j = 0; j < i; ++j) | |
f54d1867 | 317 | dma_fence_get(fences[j]); |
1fbb2e92 | 318 | |
f54d1867 | 319 | array = dma_fence_array_create(i, fences, fence_context, |
1fbb2e92 CK |
320 | seqno, true); |
321 | if (!array) { | |
322 | for (j = 0; j < i; ++j) | |
f54d1867 | 323 | dma_fence_put(fences[j]); |
1fbb2e92 CK |
324 | kfree(fences); |
325 | r = -ENOMEM; | |
326 | goto error; | |
327 | } | |
328 | ||
329 | ||
330 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
f54d1867 | 331 | dma_fence_put(&array->base); |
1fbb2e92 CK |
332 | if (r) |
333 | goto error; | |
334 | ||
335 | mutex_unlock(&adev->vm_manager.lock); | |
336 | return 0; | |
337 | ||
338 | } | |
339 | kfree(fences); | |
340 | ||
fd53be30 | 341 | job->vm_needs_flush = true; |
1fbb2e92 CK |
342 | /* Check if we can use a VMID already assigned to this VM */ |
343 | i = ring->idx; | |
344 | do { | |
f54d1867 | 345 | struct dma_fence *flushed; |
1fbb2e92 CK |
346 | |
347 | id = vm->ids[i++]; | |
348 | if (i == AMDGPU_MAX_RINGS) | |
349 | i = 0; | |
8d76001e | 350 | |
1fbb2e92 CK |
351 | /* Check all the prerequisites to using this VMID */ |
352 | if (!id) | |
353 | continue; | |
192b7dcb | 354 | if (amdgpu_vm_is_gpu_reset(adev, id)) |
6adb0513 | 355 | continue; |
1fbb2e92 CK |
356 | |
357 | if (atomic64_read(&id->owner) != vm->client_id) | |
358 | continue; | |
359 | ||
fd53be30 | 360 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
361 | continue; |
362 | ||
090b767e CK |
363 | if (!id->last_flush) |
364 | continue; | |
365 | ||
366 | if (id->last_flush->context != fence_context && | |
f54d1867 | 367 | !dma_fence_is_signaled(id->last_flush)) |
1fbb2e92 CK |
368 | continue; |
369 | ||
370 | flushed = id->flushed_updates; | |
371 | if (updates && | |
f54d1867 | 372 | (!flushed || dma_fence_is_later(updates, flushed))) |
1fbb2e92 CK |
373 | continue; |
374 | ||
3dab83be CK |
375 | /* Good we can use this VMID. Remember this submission as |
376 | * user of the VMID. | |
377 | */ | |
1fbb2e92 CK |
378 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
379 | if (r) | |
380 | goto error; | |
8d76001e | 381 | |
6adb0513 | 382 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
1fbb2e92 CK |
383 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
384 | vm->ids[ring->idx] = id; | |
8d76001e | 385 | |
fd53be30 CZ |
386 | job->vm_id = id - adev->vm_manager.ids; |
387 | job->vm_needs_flush = false; | |
0c0fdf14 | 388 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
8d76001e | 389 | |
1fbb2e92 CK |
390 | mutex_unlock(&adev->vm_manager.lock); |
391 | return 0; | |
8d76001e | 392 | |
1fbb2e92 | 393 | } while (i != ring->idx); |
8d76001e | 394 | |
1fbb2e92 CK |
395 | /* Still no ID to use? Then use the idle one found earlier */ |
396 | id = idle; | |
8e9fbeb5 | 397 | |
1fbb2e92 CK |
398 | /* Remember this submission as user of the VMID */ |
399 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
400 | if (r) |
401 | goto error; | |
94dd0a4a | 402 | |
f54d1867 CW |
403 | dma_fence_put(id->first); |
404 | id->first = dma_fence_get(fence); | |
94dd0a4a | 405 | |
f54d1867 | 406 | dma_fence_put(id->last_flush); |
41d9eb2c CK |
407 | id->last_flush = NULL; |
408 | ||
f54d1867 CW |
409 | dma_fence_put(id->flushed_updates); |
410 | id->flushed_updates = dma_fence_get(updates); | |
94dd0a4a | 411 | |
fd53be30 | 412 | id->pd_gpu_addr = job->vm_pd_addr; |
b46b8a87 | 413 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
832a902f | 414 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
0ea54b9b | 415 | atomic64_set(&id->owner, vm->client_id); |
832a902f | 416 | vm->ids[ring->idx] = id; |
d38ceaf9 | 417 | |
fd53be30 | 418 | job->vm_id = id - adev->vm_manager.ids; |
0c0fdf14 | 419 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
832a902f CK |
420 | |
421 | error: | |
94dd0a4a | 422 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 423 | return r; |
d38ceaf9 AD |
424 | } |
425 | ||
93dcc37d AD |
426 | static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) |
427 | { | |
428 | struct amdgpu_device *adev = ring->adev; | |
a1255107 | 429 | const struct amdgpu_ip_block *ip_block; |
93dcc37d | 430 | |
21cd942e | 431 | if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) |
93dcc37d AD |
432 | /* only compute rings */ |
433 | return false; | |
434 | ||
435 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
436 | if (!ip_block) | |
437 | return false; | |
438 | ||
a1255107 | 439 | if (ip_block->version->major <= 7) { |
93dcc37d AD |
440 | /* gfx7 has no workaround */ |
441 | return true; | |
a1255107 | 442 | } else if (ip_block->version->major == 8) { |
93dcc37d AD |
443 | if (adev->gfx.mec_fw_version >= 673) |
444 | /* gfx8 is fixed in MEC firmware 673 */ | |
445 | return false; | |
446 | else | |
447 | return true; | |
448 | } | |
449 | return false; | |
450 | } | |
451 | ||
e60f8db5 AX |
452 | static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) |
453 | { | |
454 | u64 addr = mc_addr; | |
455 | ||
456 | if (adev->mc.mc_funcs && adev->mc.mc_funcs->adjust_mc_addr) | |
457 | addr = adev->mc.mc_funcs->adjust_mc_addr(adev, addr); | |
458 | ||
459 | return addr; | |
460 | } | |
461 | ||
d38ceaf9 AD |
462 | /** |
463 | * amdgpu_vm_flush - hardware flush the vm | |
464 | * | |
465 | * @ring: ring to use for flush | |
cffadc83 | 466 | * @vm_id: vmid number to use |
4ff37a83 | 467 | * @pd_addr: address of the page directory |
d38ceaf9 | 468 | * |
4ff37a83 | 469 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 470 | */ |
fd53be30 | 471 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) |
d38ceaf9 | 472 | { |
971fe9a9 | 473 | struct amdgpu_device *adev = ring->adev; |
fd53be30 | 474 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id]; |
d564a06e | 475 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
476 | id->gds_base != job->gds_base || |
477 | id->gds_size != job->gds_size || | |
478 | id->gws_base != job->gws_base || | |
479 | id->gws_size != job->gws_size || | |
480 | id->oa_base != job->oa_base || | |
481 | id->oa_size != job->oa_size); | |
41d9eb2c | 482 | int r; |
d564a06e CK |
483 | |
484 | if (ring->funcs->emit_pipeline_sync && ( | |
fd53be30 | 485 | job->vm_needs_flush || gds_switch_needed || |
93dcc37d | 486 | amdgpu_vm_ring_has_compute_vm_bug(ring))) |
d564a06e | 487 | amdgpu_ring_emit_pipeline_sync(ring); |
971fe9a9 | 488 | |
aa1c8900 CZ |
489 | if (ring->funcs->emit_vm_flush && (job->vm_needs_flush || |
490 | amdgpu_vm_is_gpu_reset(adev, id))) { | |
f54d1867 | 491 | struct dma_fence *fence; |
e60f8db5 | 492 | u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr); |
41d9eb2c | 493 | |
e60f8db5 AX |
494 | trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id); |
495 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr); | |
41d9eb2c | 496 | |
3dab83be CK |
497 | r = amdgpu_fence_emit(ring, &fence); |
498 | if (r) | |
499 | return r; | |
500 | ||
41d9eb2c | 501 | mutex_lock(&adev->vm_manager.lock); |
f54d1867 | 502 | dma_fence_put(id->last_flush); |
3dab83be | 503 | id->last_flush = fence; |
41d9eb2c | 504 | mutex_unlock(&adev->vm_manager.lock); |
d38ceaf9 | 505 | } |
cffadc83 | 506 | |
d564a06e | 507 | if (gds_switch_needed) { |
fd53be30 CZ |
508 | id->gds_base = job->gds_base; |
509 | id->gds_size = job->gds_size; | |
510 | id->gws_base = job->gws_base; | |
511 | id->gws_size = job->gws_size; | |
512 | id->oa_base = job->oa_base; | |
513 | id->oa_size = job->oa_size; | |
514 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, | |
515 | job->gds_base, job->gds_size, | |
516 | job->gws_base, job->gws_size, | |
517 | job->oa_base, job->oa_size); | |
971fe9a9 | 518 | } |
41d9eb2c CK |
519 | |
520 | return 0; | |
971fe9a9 CK |
521 | } |
522 | ||
523 | /** | |
524 | * amdgpu_vm_reset_id - reset VMID to zero | |
525 | * | |
526 | * @adev: amdgpu device structure | |
527 | * @vm_id: vmid number to use | |
528 | * | |
529 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
530 | */ | |
531 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
532 | { | |
bcb1ba35 CK |
533 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
534 | ||
535 | id->gds_base = 0; | |
536 | id->gds_size = 0; | |
537 | id->gws_base = 0; | |
538 | id->gws_size = 0; | |
539 | id->oa_base = 0; | |
540 | id->oa_size = 0; | |
d38ceaf9 AD |
541 | } |
542 | ||
d38ceaf9 AD |
543 | /** |
544 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
545 | * | |
546 | * @vm: requested vm | |
547 | * @bo: requested buffer object | |
548 | * | |
8843dbbb | 549 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
550 | * Search inside the @bos vm list for the requested vm |
551 | * Returns the found bo_va or NULL if none is found | |
552 | * | |
553 | * Object has to be reserved! | |
554 | */ | |
555 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
556 | struct amdgpu_bo *bo) | |
557 | { | |
558 | struct amdgpu_bo_va *bo_va; | |
559 | ||
560 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
561 | if (bo_va->vm == vm) { | |
562 | return bo_va; | |
563 | } | |
564 | } | |
565 | return NULL; | |
566 | } | |
567 | ||
568 | /** | |
afef8b8f | 569 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 570 | * |
29efc4f5 | 571 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
572 | * @pe: addr of the page entry |
573 | * @addr: dst addr to write into pe | |
574 | * @count: number of page entries to update | |
575 | * @incr: increase next addr by incr bytes | |
576 | * @flags: hw access flags | |
d38ceaf9 AD |
577 | * |
578 | * Traces the parameters and calls the right asic functions | |
579 | * to setup the page table using the DMA. | |
580 | */ | |
afef8b8f CK |
581 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
582 | uint64_t pe, uint64_t addr, | |
583 | unsigned count, uint32_t incr, | |
6b777607 | 584 | uint64_t flags) |
d38ceaf9 | 585 | { |
ec2f05f0 | 586 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 587 | |
afef8b8f | 588 | if (count < 3) { |
de9ea7bd CK |
589 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
590 | addr | flags, count, incr); | |
d38ceaf9 AD |
591 | |
592 | } else { | |
27c5f36f | 593 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
594 | count, incr, flags); |
595 | } | |
596 | } | |
597 | ||
afef8b8f CK |
598 | /** |
599 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
600 | * | |
601 | * @params: see amdgpu_pte_update_params definition | |
602 | * @pe: addr of the page entry | |
603 | * @addr: dst addr to write into pe | |
604 | * @count: number of page entries to update | |
605 | * @incr: increase next addr by incr bytes | |
606 | * @flags: hw access flags | |
607 | * | |
608 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
609 | */ | |
610 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
611 | uint64_t pe, uint64_t addr, | |
612 | unsigned count, uint32_t incr, | |
6b777607 | 613 | uint64_t flags) |
afef8b8f | 614 | { |
ec2f05f0 | 615 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 616 | |
ec2f05f0 CK |
617 | |
618 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
619 | ||
620 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
621 | } |
622 | ||
d38ceaf9 | 623 | /** |
b07c9d2a | 624 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 625 | * |
b07c9d2a | 626 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
627 | * @addr: the unmapped addr |
628 | * | |
629 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 630 | * to and return the pointer for the page table entry. |
d38ceaf9 | 631 | */ |
de9ea7bd | 632 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
633 | { |
634 | uint64_t result; | |
635 | ||
de9ea7bd CK |
636 | /* page table offset */ |
637 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 638 | |
de9ea7bd CK |
639 | /* in case cpu page size != gpu page size*/ |
640 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 641 | |
b07c9d2a | 642 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
643 | |
644 | return result; | |
645 | } | |
646 | ||
f8991bab CK |
647 | /* |
648 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
649 | * | |
650 | * @adev: amdgpu_device pointer | |
651 | * @vm: requested vm | |
652 | * @start: start of GPU address range | |
653 | * @end: end of GPU address range | |
654 | * | |
655 | * Allocates new page tables if necessary | |
656 | * and updates the page directory. | |
657 | * Returns 0 for success, error for failure. | |
658 | */ | |
659 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
660 | struct amdgpu_vm *vm) | |
d38ceaf9 | 661 | { |
f8991bab | 662 | struct amdgpu_bo *shadow; |
2d55e45a | 663 | struct amdgpu_ring *ring; |
f8991bab | 664 | uint64_t pd_addr, shadow_addr; |
d38ceaf9 | 665 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; |
f8991bab | 666 | uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; |
d38ceaf9 | 667 | unsigned count = 0, pt_idx, ndw; |
d71518b5 | 668 | struct amdgpu_job *job; |
29efc4f5 | 669 | struct amdgpu_pte_update_params params; |
f54d1867 | 670 | struct dma_fence *fence = NULL; |
d5fc5e82 | 671 | |
d38ceaf9 AD |
672 | int r; |
673 | ||
2d55e45a | 674 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
67003a15 | 675 | shadow = vm->root.bo->shadow; |
2d55e45a | 676 | |
d38ceaf9 AD |
677 | /* padding, etc. */ |
678 | ndw = 64; | |
679 | ||
680 | /* assume the worst case */ | |
67003a15 | 681 | ndw += vm->root.last_entry_used * 6; |
d38ceaf9 | 682 | |
67003a15 | 683 | pd_addr = amdgpu_bo_gpu_offset(vm->root.bo); |
f8991bab CK |
684 | if (shadow) { |
685 | r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); | |
686 | if (r) | |
687 | return r; | |
688 | shadow_addr = amdgpu_bo_gpu_offset(shadow); | |
689 | ndw *= 2; | |
690 | } else { | |
691 | shadow_addr = 0; | |
692 | } | |
693 | ||
d71518b5 CK |
694 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
695 | if (r) | |
d38ceaf9 | 696 | return r; |
d71518b5 | 697 | |
27c5f36f CK |
698 | memset(¶ms, 0, sizeof(params)); |
699 | params.adev = adev; | |
29efc4f5 | 700 | params.ib = &job->ibs[0]; |
d38ceaf9 AD |
701 | |
702 | /* walk over the address space and update the page directory */ | |
67003a15 CK |
703 | for (pt_idx = 0; pt_idx <= vm->root.last_entry_used; ++pt_idx) { |
704 | struct amdgpu_bo *bo = vm->root.entries[pt_idx].bo; | |
d38ceaf9 AD |
705 | uint64_t pde, pt; |
706 | ||
707 | if (bo == NULL) | |
708 | continue; | |
709 | ||
0fc8683e | 710 | if (bo->shadow) { |
f8991bab | 711 | struct amdgpu_bo *pt_shadow = bo->shadow; |
0fc8683e | 712 | |
f8991bab CK |
713 | r = amdgpu_ttm_bind(&pt_shadow->tbo, |
714 | &pt_shadow->tbo.mem); | |
0fc8683e CK |
715 | if (r) |
716 | return r; | |
717 | } | |
718 | ||
d38ceaf9 | 719 | pt = amdgpu_bo_gpu_offset(bo); |
67003a15 | 720 | if (vm->root.entries[pt_idx].addr == pt) |
f8991bab CK |
721 | continue; |
722 | ||
67003a15 | 723 | vm->root.entries[pt_idx].addr = pt; |
d38ceaf9 AD |
724 | |
725 | pde = pd_addr + pt_idx * 8; | |
726 | if (((last_pde + 8 * count) != pde) || | |
96105e53 CK |
727 | ((last_pt + incr * count) != pt) || |
728 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
d38ceaf9 AD |
729 | |
730 | if (count) { | |
e60f8db5 AX |
731 | uint64_t pt_addr = |
732 | amdgpu_vm_adjust_mc_addr(adev, last_pt); | |
733 | ||
f8991bab CK |
734 | if (shadow) |
735 | amdgpu_vm_do_set_ptes(¶ms, | |
736 | last_shadow, | |
e60f8db5 | 737 | pt_addr, count, |
f8991bab CK |
738 | incr, |
739 | AMDGPU_PTE_VALID); | |
740 | ||
afef8b8f | 741 | amdgpu_vm_do_set_ptes(¶ms, last_pde, |
e60f8db5 | 742 | pt_addr, count, incr, |
afef8b8f | 743 | AMDGPU_PTE_VALID); |
d38ceaf9 AD |
744 | } |
745 | ||
746 | count = 1; | |
747 | last_pde = pde; | |
f8991bab | 748 | last_shadow = shadow_addr + pt_idx * 8; |
d38ceaf9 AD |
749 | last_pt = pt; |
750 | } else { | |
751 | ++count; | |
752 | } | |
753 | } | |
754 | ||
f8991bab | 755 | if (count) { |
e60f8db5 AX |
756 | uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt); |
757 | ||
67003a15 | 758 | if (vm->root.bo->shadow) |
e60f8db5 | 759 | amdgpu_vm_do_set_ptes(¶ms, last_shadow, pt_addr, |
f8991bab CK |
760 | count, incr, AMDGPU_PTE_VALID); |
761 | ||
e60f8db5 | 762 | amdgpu_vm_do_set_ptes(¶ms, last_pde, pt_addr, |
afef8b8f | 763 | count, incr, AMDGPU_PTE_VALID); |
f8991bab | 764 | } |
d38ceaf9 | 765 | |
f8991bab CK |
766 | if (params.ib->length_dw == 0) { |
767 | amdgpu_job_free(job); | |
768 | return 0; | |
769 | } | |
770 | ||
771 | amdgpu_ring_pad_ib(ring, params.ib); | |
67003a15 | 772 | amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv, |
f8991bab CK |
773 | AMDGPU_FENCE_OWNER_VM); |
774 | if (shadow) | |
775 | amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv, | |
e86f9cee | 776 | AMDGPU_FENCE_OWNER_VM); |
05906dec | 777 | |
f8991bab CK |
778 | WARN_ON(params.ib->length_dw > ndw); |
779 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
780 | AMDGPU_FENCE_OWNER_VM, &fence); | |
781 | if (r) | |
782 | goto error_free; | |
d5fc5e82 | 783 | |
67003a15 | 784 | amdgpu_bo_fence(vm->root.bo, fence, true); |
a24960f3 CK |
785 | dma_fence_put(vm->last_dir_update); |
786 | vm->last_dir_update = dma_fence_get(fence); | |
220196b3 | 787 | dma_fence_put(fence); |
d38ceaf9 AD |
788 | |
789 | return 0; | |
d5fc5e82 CZ |
790 | |
791 | error_free: | |
d71518b5 | 792 | amdgpu_job_free(job); |
4af9f07c | 793 | return r; |
d38ceaf9 AD |
794 | } |
795 | ||
d38ceaf9 AD |
796 | /** |
797 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
798 | * | |
29efc4f5 | 799 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
800 | * @vm: requested vm |
801 | * @start: start of GPU address range | |
802 | * @end: end of GPU address range | |
677131a1 | 803 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
804 | * @flags: mapping flags |
805 | * | |
8843dbbb | 806 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 807 | */ |
27c5f36f | 808 | static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 809 | uint64_t start, uint64_t end, |
6b777607 | 810 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 811 | { |
31f6c1fe CK |
812 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
813 | ||
92696dd5 | 814 | uint64_t cur_pe_start, cur_nptes, cur_dst; |
677131a1 | 815 | uint64_t addr; /* next GPU address to be updated */ |
21718497 AX |
816 | uint64_t pt_idx; |
817 | struct amdgpu_bo *pt; | |
818 | unsigned nptes; /* next number of ptes to be updated */ | |
819 | uint64_t next_pe_start; | |
820 | ||
821 | /* initialize the variables */ | |
822 | addr = start; | |
823 | pt_idx = addr >> amdgpu_vm_block_size; | |
67003a15 | 824 | pt = params->vm->root.entries[pt_idx].bo; |
4c7e8855 CZ |
825 | if (params->shadow) { |
826 | if (!pt->shadow) | |
827 | return; | |
914b4dce | 828 | pt = pt->shadow; |
4c7e8855 | 829 | } |
21718497 AX |
830 | if ((addr & ~mask) == (end & ~mask)) |
831 | nptes = end - addr; | |
832 | else | |
833 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
834 | ||
835 | cur_pe_start = amdgpu_bo_gpu_offset(pt); | |
836 | cur_pe_start += (addr & mask) * 8; | |
92696dd5 | 837 | cur_nptes = nptes; |
21718497 AX |
838 | cur_dst = dst; |
839 | ||
840 | /* for next ptb*/ | |
841 | addr += nptes; | |
842 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
d38ceaf9 AD |
843 | |
844 | /* walk over the address space and update the page tables */ | |
21718497 AX |
845 | while (addr < end) { |
846 | pt_idx = addr >> amdgpu_vm_block_size; | |
67003a15 | 847 | pt = params->vm->root.entries[pt_idx].bo; |
4c7e8855 CZ |
848 | if (params->shadow) { |
849 | if (!pt->shadow) | |
850 | return; | |
914b4dce | 851 | pt = pt->shadow; |
4c7e8855 | 852 | } |
d38ceaf9 AD |
853 | |
854 | if ((addr & ~mask) == (end & ~mask)) | |
855 | nptes = end - addr; | |
856 | else | |
857 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
858 | ||
677131a1 AX |
859 | next_pe_start = amdgpu_bo_gpu_offset(pt); |
860 | next_pe_start += (addr & mask) * 8; | |
d38ceaf9 | 861 | |
96105e53 CK |
862 | if ((cur_pe_start + 8 * cur_nptes) == next_pe_start && |
863 | ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
3a6f8e0c | 864 | /* The next ptb is consecutive to current ptb. |
afef8b8f | 865 | * Don't call the update function now. |
3a6f8e0c AX |
866 | * Will update two ptbs together in future. |
867 | */ | |
92696dd5 | 868 | cur_nptes += nptes; |
3a6f8e0c | 869 | } else { |
afef8b8f CK |
870 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
871 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 | 872 | |
677131a1 | 873 | cur_pe_start = next_pe_start; |
92696dd5 | 874 | cur_nptes = nptes; |
677131a1 | 875 | cur_dst = dst; |
d38ceaf9 AD |
876 | } |
877 | ||
21718497 | 878 | /* for next ptb*/ |
d38ceaf9 AD |
879 | addr += nptes; |
880 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
881 | } | |
882 | ||
afef8b8f CK |
883 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
884 | AMDGPU_GPU_PAGE_SIZE, flags); | |
92696dd5 CK |
885 | } |
886 | ||
887 | /* | |
888 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
889 | * | |
890 | * @params: see amdgpu_pte_update_params definition | |
891 | * @vm: requested vm | |
892 | * @start: first PTE to handle | |
893 | * @end: last PTE to handle | |
894 | * @dst: addr those PTEs should point to | |
895 | * @flags: hw mapping flags | |
896 | */ | |
897 | static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, | |
92696dd5 | 898 | uint64_t start, uint64_t end, |
6b777607 | 899 | uint64_t dst, uint64_t flags) |
92696dd5 CK |
900 | { |
901 | /** | |
902 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
903 | * field in the PTE. When this field is set to a non-zero value, page | |
904 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
905 | * flags are considered valid for all PTEs within the fragment range | |
906 | * and corresponding mappings are assumed to be physically contiguous. | |
907 | * | |
908 | * The L1 TLB can store a single PTE for the whole fragment, | |
909 | * significantly increasing the space available for translation | |
910 | * caching. This leads to large improvements in throughput when the | |
911 | * TLB is under pressure. | |
912 | * | |
913 | * The L2 TLB distributes small and large fragments into two | |
914 | * asymmetric partitions. The large fragment cache is significantly | |
915 | * larger. Thus, we try to use large fragments wherever possible. | |
916 | * Userspace can support this by aligning virtual base address and | |
917 | * allocation size to the fragment size. | |
918 | */ | |
919 | ||
8036617e CK |
920 | /* SI and newer are optimized for 64KB */ |
921 | uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG); | |
922 | uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG; | |
92696dd5 CK |
923 | |
924 | uint64_t frag_start = ALIGN(start, frag_align); | |
925 | uint64_t frag_end = end & ~(frag_align - 1); | |
926 | ||
927 | /* system pages are non continuously */ | |
b7fc2cbd | 928 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
92696dd5 CK |
929 | (frag_start >= frag_end)) { |
930 | ||
49ac8a24 | 931 | amdgpu_vm_update_ptes(params, start, end, dst, flags); |
92696dd5 CK |
932 | return; |
933 | } | |
934 | ||
935 | /* handle the 4K area at the beginning */ | |
936 | if (start != frag_start) { | |
49ac8a24 | 937 | amdgpu_vm_update_ptes(params, start, frag_start, |
92696dd5 CK |
938 | dst, flags); |
939 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; | |
940 | } | |
941 | ||
942 | /* handle the area in the middle */ | |
49ac8a24 | 943 | amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, |
8036617e | 944 | flags | frag_flags); |
92696dd5 CK |
945 | |
946 | /* handle the 4K area at the end */ | |
947 | if (frag_end != end) { | |
948 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
49ac8a24 | 949 | amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); |
92696dd5 | 950 | } |
d38ceaf9 AD |
951 | } |
952 | ||
d38ceaf9 AD |
953 | /** |
954 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
955 | * | |
956 | * @adev: amdgpu_device pointer | |
3cabaa54 | 957 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
958 | * @src: address where to copy page table entries from |
959 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 960 | * @vm: requested vm |
a14faa65 CK |
961 | * @start: start of mapped range |
962 | * @last: last mapped entry | |
963 | * @flags: flags for the entries | |
d38ceaf9 | 964 | * @addr: addr to set the area to |
d38ceaf9 AD |
965 | * @fence: optional resulting fence |
966 | * | |
a14faa65 | 967 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 968 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
969 | */ |
970 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 971 | struct dma_fence *exclusive, |
fa3ab3c7 CK |
972 | uint64_t src, |
973 | dma_addr_t *pages_addr, | |
d38ceaf9 | 974 | struct amdgpu_vm *vm, |
a14faa65 | 975 | uint64_t start, uint64_t last, |
6b777607 | 976 | uint64_t flags, uint64_t addr, |
f54d1867 | 977 | struct dma_fence **fence) |
d38ceaf9 | 978 | { |
2d55e45a | 979 | struct amdgpu_ring *ring; |
a1e08d3b | 980 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 981 | unsigned nptes, ncmds, ndw; |
d71518b5 | 982 | struct amdgpu_job *job; |
29efc4f5 | 983 | struct amdgpu_pte_update_params params; |
f54d1867 | 984 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
985 | int r; |
986 | ||
afef8b8f CK |
987 | memset(¶ms, 0, sizeof(params)); |
988 | params.adev = adev; | |
49ac8a24 | 989 | params.vm = vm; |
afef8b8f CK |
990 | params.src = src; |
991 | ||
2d55e45a | 992 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 993 | |
a1e08d3b CK |
994 | /* sync to everything on unmapping */ |
995 | if (!(flags & AMDGPU_PTE_VALID)) | |
996 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
997 | ||
a14faa65 | 998 | nptes = last - start + 1; |
d38ceaf9 AD |
999 | |
1000 | /* | |
1001 | * reserve space for one command every (1 << BLOCK_SIZE) | |
1002 | * entries or 2k dwords (whatever is smaller) | |
1003 | */ | |
1004 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
1005 | ||
1006 | /* padding, etc. */ | |
1007 | ndw = 64; | |
1008 | ||
b0456f93 | 1009 | if (src) { |
d38ceaf9 AD |
1010 | /* only copy commands needed */ |
1011 | ndw += ncmds * 7; | |
1012 | ||
afef8b8f CK |
1013 | params.func = amdgpu_vm_do_copy_ptes; |
1014 | ||
b0456f93 CK |
1015 | } else if (pages_addr) { |
1016 | /* copy commands needed */ | |
1017 | ndw += ncmds * 7; | |
d38ceaf9 | 1018 | |
b0456f93 | 1019 | /* and also PTEs */ |
d38ceaf9 AD |
1020 | ndw += nptes * 2; |
1021 | ||
afef8b8f CK |
1022 | params.func = amdgpu_vm_do_copy_ptes; |
1023 | ||
d38ceaf9 AD |
1024 | } else { |
1025 | /* set page commands needed */ | |
1026 | ndw += ncmds * 10; | |
1027 | ||
1028 | /* two extra commands for begin/end of fragment */ | |
1029 | ndw += 2 * 10; | |
afef8b8f CK |
1030 | |
1031 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1032 | } |
1033 | ||
d71518b5 CK |
1034 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1035 | if (r) | |
d38ceaf9 | 1036 | return r; |
d71518b5 | 1037 | |
29efc4f5 | 1038 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1039 | |
b0456f93 CK |
1040 | if (!src && pages_addr) { |
1041 | uint64_t *pte; | |
1042 | unsigned i; | |
1043 | ||
1044 | /* Put the PTEs at the end of the IB. */ | |
1045 | i = ndw - nptes * 2; | |
1046 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1047 | params.src = job->ibs->gpu_addr + i * 4; | |
1048 | ||
1049 | for (i = 0; i < nptes; ++i) { | |
1050 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1051 | AMDGPU_GPU_PAGE_SIZE); | |
1052 | pte[i] |= flags; | |
1053 | } | |
d7a4ac66 | 1054 | addr = 0; |
b0456f93 CK |
1055 | } |
1056 | ||
3cabaa54 CK |
1057 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
1058 | if (r) | |
1059 | goto error_free; | |
1060 | ||
67003a15 | 1061 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv, |
a1e08d3b CK |
1062 | owner); |
1063 | if (r) | |
1064 | goto error_free; | |
d38ceaf9 | 1065 | |
67003a15 | 1066 | r = reservation_object_reserve_shared(vm->root.bo->tbo.resv); |
a1e08d3b CK |
1067 | if (r) |
1068 | goto error_free; | |
1069 | ||
4c7e8855 | 1070 | params.shadow = true; |
49ac8a24 | 1071 | amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
4c7e8855 | 1072 | params.shadow = false; |
49ac8a24 | 1073 | amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
d38ceaf9 | 1074 | |
29efc4f5 CK |
1075 | amdgpu_ring_pad_ib(ring, params.ib); |
1076 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1077 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1078 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1079 | if (r) |
1080 | goto error_free; | |
d38ceaf9 | 1081 | |
67003a15 | 1082 | amdgpu_bo_fence(vm->root.bo, f, true); |
284710fa CK |
1083 | dma_fence_put(*fence); |
1084 | *fence = f; | |
d38ceaf9 | 1085 | return 0; |
d5fc5e82 CZ |
1086 | |
1087 | error_free: | |
d71518b5 | 1088 | amdgpu_job_free(job); |
4af9f07c | 1089 | return r; |
d38ceaf9 AD |
1090 | } |
1091 | ||
a14faa65 CK |
1092 | /** |
1093 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1094 | * | |
1095 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1096 | * @exclusive: fence we need to sync to |
8358dcee CK |
1097 | * @gtt_flags: flags as they are used for GTT |
1098 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
1099 | * @vm: requested vm |
1100 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1101 | * @flags: HW flags for the mapping |
63e0ba40 | 1102 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1103 | * @fence: optional resulting fence |
1104 | * | |
1105 | * Split the mapping into smaller chunks so that each update fits | |
1106 | * into a SDMA IB. | |
1107 | * Returns 0 for success, -EINVAL for failure. | |
1108 | */ | |
1109 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1110 | struct dma_fence *exclusive, |
6b777607 | 1111 | uint64_t gtt_flags, |
8358dcee | 1112 | dma_addr_t *pages_addr, |
a14faa65 CK |
1113 | struct amdgpu_vm *vm, |
1114 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1115 | uint64_t flags, |
63e0ba40 | 1116 | struct drm_mm_node *nodes, |
f54d1867 | 1117 | struct dma_fence **fence) |
a14faa65 | 1118 | { |
63e0ba40 | 1119 | uint64_t pfn, src = 0, start = mapping->it.start; |
a14faa65 CK |
1120 | int r; |
1121 | ||
1122 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1123 | * but in case of something, we filter the flags in first place | |
1124 | */ | |
1125 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1126 | flags &= ~AMDGPU_PTE_READABLE; | |
1127 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1128 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1129 | ||
15b31c59 AX |
1130 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1131 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1132 | ||
b0fd18b0 AX |
1133 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1134 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1135 | ||
a14faa65 CK |
1136 | trace_amdgpu_vm_bo_update(mapping); |
1137 | ||
63e0ba40 CK |
1138 | pfn = mapping->offset >> PAGE_SHIFT; |
1139 | if (nodes) { | |
1140 | while (pfn >= nodes->size) { | |
1141 | pfn -= nodes->size; | |
1142 | ++nodes; | |
1143 | } | |
fa3ab3c7 | 1144 | } |
a14faa65 | 1145 | |
63e0ba40 CK |
1146 | do { |
1147 | uint64_t max_entries; | |
1148 | uint64_t addr, last; | |
a14faa65 | 1149 | |
63e0ba40 CK |
1150 | if (nodes) { |
1151 | addr = nodes->start << PAGE_SHIFT; | |
1152 | max_entries = (nodes->size - pfn) * | |
1153 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1154 | } else { | |
1155 | addr = 0; | |
1156 | max_entries = S64_MAX; | |
1157 | } | |
a14faa65 | 1158 | |
63e0ba40 CK |
1159 | if (pages_addr) { |
1160 | if (flags == gtt_flags) | |
1161 | src = adev->gart.table_addr + | |
1162 | (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8; | |
1163 | else | |
1164 | max_entries = min(max_entries, 16ull * 1024ull); | |
1165 | addr = 0; | |
1166 | } else if (flags & AMDGPU_PTE_VALID) { | |
1167 | addr += adev->vm_manager.vram_base_offset; | |
1168 | } | |
1169 | addr += pfn << PAGE_SHIFT; | |
1170 | ||
1171 | last = min((uint64_t)mapping->it.last, start + max_entries - 1); | |
3cabaa54 CK |
1172 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1173 | src, pages_addr, vm, | |
a14faa65 CK |
1174 | start, last, flags, addr, |
1175 | fence); | |
1176 | if (r) | |
1177 | return r; | |
1178 | ||
63e0ba40 CK |
1179 | pfn += last - start + 1; |
1180 | if (nodes && nodes->size == pfn) { | |
1181 | pfn = 0; | |
1182 | ++nodes; | |
1183 | } | |
a14faa65 | 1184 | start = last + 1; |
63e0ba40 CK |
1185 | |
1186 | } while (unlikely(start != mapping->it.last + 1)); | |
a14faa65 CK |
1187 | |
1188 | return 0; | |
1189 | } | |
1190 | ||
d38ceaf9 AD |
1191 | /** |
1192 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1193 | * | |
1194 | * @adev: amdgpu_device pointer | |
1195 | * @bo_va: requested BO and VM object | |
99e124f4 | 1196 | * @clear: if true clear the entries |
d38ceaf9 AD |
1197 | * |
1198 | * Fill in the page table entries for @bo_va. | |
1199 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1200 | */ |
1201 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1202 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1203 | bool clear) |
d38ceaf9 AD |
1204 | { |
1205 | struct amdgpu_vm *vm = bo_va->vm; | |
1206 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1207 | dma_addr_t *pages_addr = NULL; |
6b777607 | 1208 | uint64_t gtt_flags, flags; |
99e124f4 | 1209 | struct ttm_mem_reg *mem; |
63e0ba40 | 1210 | struct drm_mm_node *nodes; |
f54d1867 | 1211 | struct dma_fence *exclusive; |
d38ceaf9 AD |
1212 | int r; |
1213 | ||
a5f6b5b1 | 1214 | if (clear || !bo_va->bo) { |
99e124f4 | 1215 | mem = NULL; |
63e0ba40 | 1216 | nodes = NULL; |
99e124f4 CK |
1217 | exclusive = NULL; |
1218 | } else { | |
8358dcee CK |
1219 | struct ttm_dma_tt *ttm; |
1220 | ||
99e124f4 | 1221 | mem = &bo_va->bo->tbo.mem; |
63e0ba40 CK |
1222 | nodes = mem->mm_node; |
1223 | if (mem->mem_type == TTM_PL_TT) { | |
8358dcee CK |
1224 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1225 | ttm_dma_tt, ttm); | |
1226 | pages_addr = ttm->dma_address; | |
9ab21462 | 1227 | } |
3cabaa54 | 1228 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); |
d38ceaf9 AD |
1229 | } |
1230 | ||
a5f6b5b1 CK |
1231 | if (bo_va->bo) { |
1232 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); | |
1233 | gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && | |
1234 | adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? | |
1235 | flags : 0; | |
1236 | } else { | |
1237 | flags = 0x0; | |
1238 | gtt_flags = ~0x0; | |
1239 | } | |
d38ceaf9 | 1240 | |
7fc11959 CK |
1241 | spin_lock(&vm->status_lock); |
1242 | if (!list_empty(&bo_va->vm_status)) | |
1243 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1244 | spin_unlock(&vm->status_lock); | |
1245 | ||
1246 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1247 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1248 | gtt_flags, pages_addr, vm, | |
63e0ba40 | 1249 | mapping, flags, nodes, |
8358dcee | 1250 | &bo_va->last_pt_update); |
d38ceaf9 AD |
1251 | if (r) |
1252 | return r; | |
1253 | } | |
1254 | ||
d6c10f6b CK |
1255 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1256 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1257 | trace_amdgpu_vm_bo_mapping(mapping); | |
1258 | ||
1259 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1260 | trace_amdgpu_vm_bo_mapping(mapping); | |
1261 | } | |
1262 | ||
d38ceaf9 | 1263 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1264 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1265 | list_del_init(&bo_va->vm_status); |
99e124f4 | 1266 | if (clear) |
7fc11959 | 1267 | list_add(&bo_va->vm_status, &vm->cleared); |
d38ceaf9 AD |
1268 | spin_unlock(&vm->status_lock); |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
284710fa CK |
1273 | /** |
1274 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1275 | */ | |
1276 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1277 | { | |
1278 | unsigned long flags; | |
1279 | bool enable; | |
1280 | ||
1281 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1282 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
284710fa CK |
1283 | adev->gart.gart_funcs->set_prt(adev, enable); |
1284 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
1285 | } | |
1286 | ||
451bc8eb | 1287 | /** |
4388fc2a | 1288 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1289 | */ |
1290 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1291 | { | |
4388fc2a CK |
1292 | if (!adev->gart.gart_funcs->set_prt) |
1293 | return; | |
1294 | ||
451bc8eb CK |
1295 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1296 | amdgpu_vm_update_prt_state(adev); | |
1297 | } | |
1298 | ||
0b15f2fc CK |
1299 | /** |
1300 | * amdgpu_vm_prt_put - drop a PRT user | |
1301 | */ | |
1302 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1303 | { | |
451bc8eb | 1304 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1305 | amdgpu_vm_update_prt_state(adev); |
1306 | } | |
1307 | ||
284710fa | 1308 | /** |
451bc8eb | 1309 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1310 | */ |
1311 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1312 | { | |
1313 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1314 | ||
0b15f2fc | 1315 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1316 | kfree(cb); |
1317 | } | |
1318 | ||
451bc8eb CK |
1319 | /** |
1320 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1321 | */ | |
1322 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1323 | struct dma_fence *fence) | |
1324 | { | |
4388fc2a | 1325 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1326 | |
4388fc2a CK |
1327 | if (!adev->gart.gart_funcs->set_prt) |
1328 | return; | |
1329 | ||
1330 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1331 | if (!cb) { |
1332 | /* Last resort when we are OOM */ | |
1333 | if (fence) | |
1334 | dma_fence_wait(fence, false); | |
1335 | ||
1336 | amdgpu_vm_prt_put(cb->adev); | |
1337 | } else { | |
1338 | cb->adev = adev; | |
1339 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1340 | amdgpu_vm_prt_cb)) | |
1341 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1342 | } | |
1343 | } | |
1344 | ||
284710fa CK |
1345 | /** |
1346 | * amdgpu_vm_free_mapping - free a mapping | |
1347 | * | |
1348 | * @adev: amdgpu_device pointer | |
1349 | * @vm: requested vm | |
1350 | * @mapping: mapping to be freed | |
1351 | * @fence: fence of the unmap operation | |
1352 | * | |
1353 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1354 | */ | |
1355 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1356 | struct amdgpu_vm *vm, | |
1357 | struct amdgpu_bo_va_mapping *mapping, | |
1358 | struct dma_fence *fence) | |
1359 | { | |
451bc8eb CK |
1360 | if (mapping->flags & AMDGPU_PTE_PRT) |
1361 | amdgpu_vm_add_prt_cb(adev, fence); | |
1362 | kfree(mapping); | |
1363 | } | |
284710fa | 1364 | |
451bc8eb CK |
1365 | /** |
1366 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1367 | * | |
1368 | * @adev: amdgpu_device pointer | |
1369 | * @vm: requested vm | |
1370 | * | |
1371 | * Register a cleanup callback to disable PRT support after VM dies. | |
1372 | */ | |
1373 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1374 | { | |
67003a15 | 1375 | struct reservation_object *resv = vm->root.bo->tbo.resv; |
451bc8eb CK |
1376 | struct dma_fence *excl, **shared; |
1377 | unsigned i, shared_count; | |
1378 | int r; | |
0b15f2fc | 1379 | |
451bc8eb CK |
1380 | r = reservation_object_get_fences_rcu(resv, &excl, |
1381 | &shared_count, &shared); | |
1382 | if (r) { | |
1383 | /* Not enough memory to grab the fence list, as last resort | |
1384 | * block for all the fences to complete. | |
1385 | */ | |
1386 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1387 | MAX_SCHEDULE_TIMEOUT); | |
1388 | return; | |
284710fa | 1389 | } |
451bc8eb CK |
1390 | |
1391 | /* Add a callback for each fence in the reservation object */ | |
1392 | amdgpu_vm_prt_get(adev); | |
1393 | amdgpu_vm_add_prt_cb(adev, excl); | |
1394 | ||
1395 | for (i = 0; i < shared_count; ++i) { | |
1396 | amdgpu_vm_prt_get(adev); | |
1397 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1398 | } | |
1399 | ||
1400 | kfree(shared); | |
284710fa CK |
1401 | } |
1402 | ||
d38ceaf9 AD |
1403 | /** |
1404 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1405 | * | |
1406 | * @adev: amdgpu_device pointer | |
1407 | * @vm: requested vm | |
f3467818 NH |
1408 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1409 | * or if an error occurred) | |
d38ceaf9 AD |
1410 | * |
1411 | * Make sure all freed BOs are cleared in the PT. | |
1412 | * Returns 0 for success. | |
1413 | * | |
1414 | * PTs have to be reserved and mutex must be locked! | |
1415 | */ | |
1416 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1417 | struct amdgpu_vm *vm, |
1418 | struct dma_fence **fence) | |
d38ceaf9 AD |
1419 | { |
1420 | struct amdgpu_bo_va_mapping *mapping; | |
f3467818 | 1421 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1422 | int r; |
1423 | ||
1424 | while (!list_empty(&vm->freed)) { | |
1425 | mapping = list_first_entry(&vm->freed, | |
1426 | struct amdgpu_bo_va_mapping, list); | |
1427 | list_del(&mapping->list); | |
e17841b9 | 1428 | |
3cabaa54 | 1429 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping, |
f3467818 NH |
1430 | 0, 0, &f); |
1431 | amdgpu_vm_free_mapping(adev, vm, mapping, f); | |
284710fa | 1432 | if (r) { |
f3467818 | 1433 | dma_fence_put(f); |
d38ceaf9 | 1434 | return r; |
284710fa | 1435 | } |
f3467818 | 1436 | } |
d38ceaf9 | 1437 | |
f3467818 NH |
1438 | if (fence && f) { |
1439 | dma_fence_put(*fence); | |
1440 | *fence = f; | |
1441 | } else { | |
1442 | dma_fence_put(f); | |
d38ceaf9 | 1443 | } |
f3467818 | 1444 | |
d38ceaf9 AD |
1445 | return 0; |
1446 | ||
1447 | } | |
1448 | ||
1449 | /** | |
1450 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1451 | * | |
1452 | * @adev: amdgpu_device pointer | |
1453 | * @vm: requested vm | |
1454 | * | |
1455 | * Make sure all invalidated BOs are cleared in the PT. | |
1456 | * Returns 0 for success. | |
1457 | * | |
1458 | * PTs have to be reserved and mutex must be locked! | |
1459 | */ | |
1460 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1461 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1462 | { |
cfe2c978 | 1463 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1464 | int r = 0; |
d38ceaf9 AD |
1465 | |
1466 | spin_lock(&vm->status_lock); | |
1467 | while (!list_empty(&vm->invalidated)) { | |
1468 | bo_va = list_first_entry(&vm->invalidated, | |
1469 | struct amdgpu_bo_va, vm_status); | |
1470 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1471 | |
99e124f4 | 1472 | r = amdgpu_vm_bo_update(adev, bo_va, true); |
d38ceaf9 AD |
1473 | if (r) |
1474 | return r; | |
1475 | ||
1476 | spin_lock(&vm->status_lock); | |
1477 | } | |
1478 | spin_unlock(&vm->status_lock); | |
1479 | ||
cfe2c978 | 1480 | if (bo_va) |
bb1e38a4 | 1481 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1482 | |
1483 | return r; | |
d38ceaf9 AD |
1484 | } |
1485 | ||
1486 | /** | |
1487 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1488 | * | |
1489 | * @adev: amdgpu_device pointer | |
1490 | * @vm: requested vm | |
1491 | * @bo: amdgpu buffer object | |
1492 | * | |
8843dbbb | 1493 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1494 | * Add @bo to the list of bos associated with the vm |
1495 | * Returns newly added bo_va or NULL for failure | |
1496 | * | |
1497 | * Object has to be reserved! | |
1498 | */ | |
1499 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1500 | struct amdgpu_vm *vm, | |
1501 | struct amdgpu_bo *bo) | |
1502 | { | |
1503 | struct amdgpu_bo_va *bo_va; | |
1504 | ||
1505 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1506 | if (bo_va == NULL) { | |
1507 | return NULL; | |
1508 | } | |
1509 | bo_va->vm = vm; | |
1510 | bo_va->bo = bo; | |
d38ceaf9 AD |
1511 | bo_va->ref_count = 1; |
1512 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1513 | INIT_LIST_HEAD(&bo_va->valids); |
1514 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1515 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1516 | |
a5f6b5b1 CK |
1517 | if (bo) |
1518 | list_add_tail(&bo_va->bo_list, &bo->va); | |
d38ceaf9 AD |
1519 | |
1520 | return bo_va; | |
1521 | } | |
1522 | ||
1523 | /** | |
1524 | * amdgpu_vm_bo_map - map bo inside a vm | |
1525 | * | |
1526 | * @adev: amdgpu_device pointer | |
1527 | * @bo_va: bo_va to store the address | |
1528 | * @saddr: where to map the BO | |
1529 | * @offset: requested offset in the BO | |
1530 | * @flags: attributes of pages (read/write/valid/etc.) | |
1531 | * | |
1532 | * Add a mapping of the BO at the specefied addr into the VM. | |
1533 | * Returns 0 for success, error for failure. | |
1534 | * | |
49b02b18 | 1535 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1536 | */ |
1537 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1538 | struct amdgpu_bo_va *bo_va, | |
1539 | uint64_t saddr, uint64_t offset, | |
268c3001 | 1540 | uint64_t size, uint64_t flags) |
d38ceaf9 AD |
1541 | { |
1542 | struct amdgpu_bo_va_mapping *mapping; | |
1543 | struct amdgpu_vm *vm = bo_va->vm; | |
1544 | struct interval_tree_node *it; | |
d38ceaf9 | 1545 | uint64_t eaddr; |
d38ceaf9 | 1546 | |
0be52de9 CK |
1547 | /* validate the parameters */ |
1548 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1549 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1550 | return -EINVAL; |
0be52de9 | 1551 | |
d38ceaf9 | 1552 | /* make sure object fit at this offset */ |
005ae95e | 1553 | eaddr = saddr + size - 1; |
a5f6b5b1 CK |
1554 | if (saddr >= eaddr || |
1555 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
d38ceaf9 | 1556 | return -EINVAL; |
d38ceaf9 | 1557 | |
d38ceaf9 AD |
1558 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1559 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1560 | ||
005ae95e | 1561 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
d38ceaf9 AD |
1562 | if (it) { |
1563 | struct amdgpu_bo_va_mapping *tmp; | |
1564 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1565 | /* bo and tmp overlap, invalid addr */ | |
1566 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1567 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1568 | tmp->it.start, tmp->it.last + 1); | |
663e4577 | 1569 | return -EINVAL; |
d38ceaf9 AD |
1570 | } |
1571 | ||
1572 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
1573 | if (!mapping) |
1574 | return -ENOMEM; | |
d38ceaf9 AD |
1575 | |
1576 | INIT_LIST_HEAD(&mapping->list); | |
1577 | mapping->it.start = saddr; | |
005ae95e | 1578 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1579 | mapping->offset = offset; |
1580 | mapping->flags = flags; | |
1581 | ||
7fc11959 | 1582 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 | 1583 | interval_tree_insert(&mapping->it, &vm->va); |
80f95c57 CK |
1584 | |
1585 | if (flags & AMDGPU_PTE_PRT) | |
1586 | amdgpu_vm_prt_get(adev); | |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
1591 | /** | |
1592 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
1593 | * | |
1594 | * @adev: amdgpu_device pointer | |
1595 | * @bo_va: bo_va to store the address | |
1596 | * @saddr: where to map the BO | |
1597 | * @offset: requested offset in the BO | |
1598 | * @flags: attributes of pages (read/write/valid/etc.) | |
1599 | * | |
1600 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
1601 | * mappings as we do so. | |
1602 | * Returns 0 for success, error for failure. | |
1603 | * | |
1604 | * Object has to be reserved and unreserved outside! | |
1605 | */ | |
1606 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
1607 | struct amdgpu_bo_va *bo_va, | |
1608 | uint64_t saddr, uint64_t offset, | |
1609 | uint64_t size, uint64_t flags) | |
1610 | { | |
1611 | struct amdgpu_bo_va_mapping *mapping; | |
1612 | struct amdgpu_vm *vm = bo_va->vm; | |
1613 | uint64_t eaddr; | |
1614 | int r; | |
1615 | ||
1616 | /* validate the parameters */ | |
1617 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
1618 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
1619 | return -EINVAL; | |
1620 | ||
1621 | /* make sure object fit at this offset */ | |
1622 | eaddr = saddr + size - 1; | |
1623 | if (saddr >= eaddr || | |
1624 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
1625 | return -EINVAL; | |
1626 | ||
1627 | /* Allocate all the needed memory */ | |
1628 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1629 | if (!mapping) | |
1630 | return -ENOMEM; | |
1631 | ||
1632 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size); | |
1633 | if (r) { | |
1634 | kfree(mapping); | |
1635 | return r; | |
1636 | } | |
1637 | ||
1638 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
1639 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1640 | ||
1641 | mapping->it.start = saddr; | |
1642 | mapping->it.last = eaddr; | |
1643 | mapping->offset = offset; | |
1644 | mapping->flags = flags; | |
1645 | ||
1646 | list_add(&mapping->list, &bo_va->invalids); | |
1647 | interval_tree_insert(&mapping->it, &vm->va); | |
d38ceaf9 | 1648 | |
4388fc2a CK |
1649 | if (flags & AMDGPU_PTE_PRT) |
1650 | amdgpu_vm_prt_get(adev); | |
1651 | ||
d38ceaf9 | 1652 | return 0; |
d38ceaf9 AD |
1653 | } |
1654 | ||
1655 | /** | |
1656 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1657 | * | |
1658 | * @adev: amdgpu_device pointer | |
1659 | * @bo_va: bo_va to remove the address from | |
1660 | * @saddr: where to the BO is mapped | |
1661 | * | |
1662 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1663 | * Returns 0 for success, error for failure. | |
1664 | * | |
49b02b18 | 1665 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1666 | */ |
1667 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1668 | struct amdgpu_bo_va *bo_va, | |
1669 | uint64_t saddr) | |
1670 | { | |
1671 | struct amdgpu_bo_va_mapping *mapping; | |
1672 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1673 | bool valid = true; |
d38ceaf9 | 1674 | |
6c7fc503 | 1675 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1676 | |
7fc11959 | 1677 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1678 | if (mapping->it.start == saddr) |
1679 | break; | |
1680 | } | |
1681 | ||
7fc11959 CK |
1682 | if (&mapping->list == &bo_va->valids) { |
1683 | valid = false; | |
1684 | ||
1685 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1686 | if (mapping->it.start == saddr) | |
1687 | break; | |
1688 | } | |
1689 | ||
32b41ac2 | 1690 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1691 | return -ENOENT; |
d38ceaf9 | 1692 | } |
32b41ac2 | 1693 | |
d38ceaf9 AD |
1694 | list_del(&mapping->list); |
1695 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1696 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1697 | |
e17841b9 | 1698 | if (valid) |
d38ceaf9 | 1699 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1700 | else |
284710fa CK |
1701 | amdgpu_vm_free_mapping(adev, vm, mapping, |
1702 | bo_va->last_pt_update); | |
d38ceaf9 AD |
1703 | |
1704 | return 0; | |
1705 | } | |
1706 | ||
dc54d3d1 CK |
1707 | /** |
1708 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
1709 | * | |
1710 | * @adev: amdgpu_device pointer | |
1711 | * @vm: VM structure to use | |
1712 | * @saddr: start of the range | |
1713 | * @size: size of the range | |
1714 | * | |
1715 | * Remove all mappings in a range, split them as appropriate. | |
1716 | * Returns 0 for success, error for failure. | |
1717 | */ | |
1718 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
1719 | struct amdgpu_vm *vm, | |
1720 | uint64_t saddr, uint64_t size) | |
1721 | { | |
1722 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
1723 | struct interval_tree_node *it; | |
1724 | LIST_HEAD(removed); | |
1725 | uint64_t eaddr; | |
1726 | ||
1727 | eaddr = saddr + size - 1; | |
1728 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
1729 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1730 | ||
1731 | /* Allocate all the needed memory */ | |
1732 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
1733 | if (!before) | |
1734 | return -ENOMEM; | |
27f6d610 | 1735 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
1736 | |
1737 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
1738 | if (!after) { | |
1739 | kfree(before); | |
1740 | return -ENOMEM; | |
1741 | } | |
27f6d610 | 1742 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
1743 | |
1744 | /* Now gather all removed mappings */ | |
1745 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); | |
1746 | while (it) { | |
1747 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1748 | it = interval_tree_iter_next(it, saddr, eaddr); | |
1749 | ||
1750 | /* Remember mapping split at the start */ | |
1751 | if (tmp->it.start < saddr) { | |
27f6d610 | 1752 | before->it.start = tmp->it.start; |
dc54d3d1 CK |
1753 | before->it.last = saddr - 1; |
1754 | before->offset = tmp->offset; | |
1755 | before->flags = tmp->flags; | |
1756 | list_add(&before->list, &tmp->list); | |
1757 | } | |
1758 | ||
1759 | /* Remember mapping split at the end */ | |
1760 | if (tmp->it.last > eaddr) { | |
1761 | after->it.start = eaddr + 1; | |
1762 | after->it.last = tmp->it.last; | |
1763 | after->offset = tmp->offset; | |
1764 | after->offset += after->it.start - tmp->it.start; | |
1765 | after->flags = tmp->flags; | |
1766 | list_add(&after->list, &tmp->list); | |
1767 | } | |
1768 | ||
1769 | list_del(&tmp->list); | |
1770 | list_add(&tmp->list, &removed); | |
1771 | } | |
1772 | ||
1773 | /* And free them up */ | |
1774 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
1775 | interval_tree_remove(&tmp->it, &vm->va); | |
1776 | list_del(&tmp->list); | |
1777 | ||
1778 | if (tmp->it.start < saddr) | |
1779 | tmp->it.start = saddr; | |
1780 | if (tmp->it.last > eaddr) | |
1781 | tmp->it.last = eaddr; | |
1782 | ||
1783 | list_add(&tmp->list, &vm->freed); | |
1784 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
1785 | } | |
1786 | ||
27f6d610 JZ |
1787 | /* Insert partial mapping before the range */ |
1788 | if (!list_empty(&before->list)) { | |
dc54d3d1 CK |
1789 | interval_tree_insert(&before->it, &vm->va); |
1790 | if (before->flags & AMDGPU_PTE_PRT) | |
1791 | amdgpu_vm_prt_get(adev); | |
1792 | } else { | |
1793 | kfree(before); | |
1794 | } | |
1795 | ||
1796 | /* Insert partial mapping after the range */ | |
27f6d610 | 1797 | if (!list_empty(&after->list)) { |
dc54d3d1 CK |
1798 | interval_tree_insert(&after->it, &vm->va); |
1799 | if (after->flags & AMDGPU_PTE_PRT) | |
1800 | amdgpu_vm_prt_get(adev); | |
1801 | } else { | |
1802 | kfree(after); | |
1803 | } | |
1804 | ||
1805 | return 0; | |
1806 | } | |
1807 | ||
d38ceaf9 AD |
1808 | /** |
1809 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1810 | * | |
1811 | * @adev: amdgpu_device pointer | |
1812 | * @bo_va: requested bo_va | |
1813 | * | |
8843dbbb | 1814 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1815 | * |
1816 | * Object have to be reserved! | |
1817 | */ | |
1818 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1819 | struct amdgpu_bo_va *bo_va) | |
1820 | { | |
1821 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1822 | struct amdgpu_vm *vm = bo_va->vm; | |
1823 | ||
1824 | list_del(&bo_va->bo_list); | |
1825 | ||
d38ceaf9 AD |
1826 | spin_lock(&vm->status_lock); |
1827 | list_del(&bo_va->vm_status); | |
1828 | spin_unlock(&vm->status_lock); | |
1829 | ||
7fc11959 | 1830 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1831 | list_del(&mapping->list); |
1832 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1833 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1834 | list_add(&mapping->list, &vm->freed); |
1835 | } | |
1836 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1837 | list_del(&mapping->list); | |
1838 | interval_tree_remove(&mapping->it, &vm->va); | |
284710fa CK |
1839 | amdgpu_vm_free_mapping(adev, vm, mapping, |
1840 | bo_va->last_pt_update); | |
d38ceaf9 | 1841 | } |
32b41ac2 | 1842 | |
f54d1867 | 1843 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 1844 | kfree(bo_va); |
d38ceaf9 AD |
1845 | } |
1846 | ||
1847 | /** | |
1848 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1849 | * | |
1850 | * @adev: amdgpu_device pointer | |
1851 | * @vm: requested vm | |
1852 | * @bo: amdgpu buffer object | |
1853 | * | |
8843dbbb | 1854 | * Mark @bo as invalid. |
d38ceaf9 AD |
1855 | */ |
1856 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1857 | struct amdgpu_bo *bo) | |
1858 | { | |
1859 | struct amdgpu_bo_va *bo_va; | |
1860 | ||
1861 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1862 | spin_lock(&bo_va->vm->status_lock); |
1863 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1864 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1865 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1866 | } |
1867 | } | |
1868 | ||
1869 | /** | |
1870 | * amdgpu_vm_init - initialize a vm instance | |
1871 | * | |
1872 | * @adev: amdgpu_device pointer | |
1873 | * @vm: requested vm | |
1874 | * | |
8843dbbb | 1875 | * Init @vm fields. |
d38ceaf9 AD |
1876 | */ |
1877 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1878 | { | |
1879 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1880 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1881 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1882 | unsigned ring_instance; |
1883 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1884 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1885 | int i, r; |
1886 | ||
bcb1ba35 CK |
1887 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1888 | vm->ids[i] = NULL; | |
d38ceaf9 | 1889 | vm->va = RB_ROOT; |
031e2983 | 1890 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
d38ceaf9 AD |
1891 | spin_lock_init(&vm->status_lock); |
1892 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1893 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1894 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 1895 | |
d38ceaf9 AD |
1896 | pd_size = amdgpu_vm_directory_size(adev); |
1897 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1898 | ||
1899 | /* allocate page table array */ | |
67003a15 CK |
1900 | vm->root.entries = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
1901 | if (vm->root.entries == NULL) { | |
d38ceaf9 AD |
1902 | DRM_ERROR("Cannot allocate memory for page table array\n"); |
1903 | return -ENOMEM; | |
1904 | } | |
1905 | ||
2bd9ccfa | 1906 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1907 | |
1908 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1909 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1910 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1911 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1912 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1913 | rq, amdgpu_sched_jobs); | |
1914 | if (r) | |
64827adc | 1915 | goto err; |
2bd9ccfa | 1916 | |
a24960f3 | 1917 | vm->last_dir_update = NULL; |
05906dec | 1918 | |
d38ceaf9 | 1919 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d | 1920 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f | 1921 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
03f48dd5 | 1922 | AMDGPU_GEM_CREATE_SHADOW | |
617859e0 CK |
1923 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
1924 | AMDGPU_GEM_CREATE_VRAM_CLEARED, | |
67003a15 | 1925 | NULL, NULL, &vm->root.bo); |
d38ceaf9 | 1926 | if (r) |
2bd9ccfa CK |
1927 | goto error_free_sched_entity; |
1928 | ||
67003a15 | 1929 | r = amdgpu_bo_reserve(vm->root.bo, false); |
2bd9ccfa | 1930 | if (r) |
67003a15 | 1931 | goto error_free_root; |
2bd9ccfa | 1932 | |
5a712a87 | 1933 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
67003a15 | 1934 | amdgpu_bo_unreserve(vm->root.bo); |
d38ceaf9 AD |
1935 | |
1936 | return 0; | |
2bd9ccfa | 1937 | |
67003a15 CK |
1938 | error_free_root: |
1939 | amdgpu_bo_unref(&vm->root.bo->shadow); | |
1940 | amdgpu_bo_unref(&vm->root.bo); | |
1941 | vm->root.bo = NULL; | |
2bd9ccfa CK |
1942 | |
1943 | error_free_sched_entity: | |
1944 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1945 | ||
64827adc | 1946 | err: |
67003a15 | 1947 | drm_free_large(vm->root.entries); |
64827adc | 1948 | |
2bd9ccfa | 1949 | return r; |
d38ceaf9 AD |
1950 | } |
1951 | ||
1952 | /** | |
1953 | * amdgpu_vm_fini - tear down a vm instance | |
1954 | * | |
1955 | * @adev: amdgpu_device pointer | |
1956 | * @vm: requested vm | |
1957 | * | |
8843dbbb | 1958 | * Tear down @vm. |
d38ceaf9 AD |
1959 | * Unbind the VM and remove all bos from the vm bo list |
1960 | */ | |
1961 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1962 | { | |
1963 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
4388fc2a | 1964 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
d38ceaf9 AD |
1965 | int i; |
1966 | ||
2d55e45a | 1967 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1968 | |
d38ceaf9 AD |
1969 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1970 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1971 | } | |
1972 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1973 | list_del(&mapping->list); | |
1974 | interval_tree_remove(&mapping->it, &vm->va); | |
1975 | kfree(mapping); | |
1976 | } | |
1977 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 1978 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 1979 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 1980 | prt_fini_needed = false; |
451bc8eb | 1981 | } |
284710fa | 1982 | |
d38ceaf9 | 1983 | list_del(&mapping->list); |
451bc8eb | 1984 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
1985 | } |
1986 | ||
1baa439f | 1987 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) { |
67003a15 | 1988 | struct amdgpu_bo *pt = vm->root.entries[i].bo; |
2698f620 CK |
1989 | |
1990 | if (!pt) | |
1991 | continue; | |
1992 | ||
1993 | amdgpu_bo_unref(&pt->shadow); | |
1994 | amdgpu_bo_unref(&pt); | |
1baa439f | 1995 | } |
67003a15 | 1996 | drm_free_large(vm->root.entries); |
d38ceaf9 | 1997 | |
67003a15 CK |
1998 | amdgpu_bo_unref(&vm->root.bo->shadow); |
1999 | amdgpu_bo_unref(&vm->root.bo); | |
a24960f3 | 2000 | dma_fence_put(vm->last_dir_update); |
d38ceaf9 | 2001 | } |
ea89f8c9 | 2002 | |
a9a78b32 CK |
2003 | /** |
2004 | * amdgpu_vm_manager_init - init the VM manager | |
2005 | * | |
2006 | * @adev: amdgpu_device pointer | |
2007 | * | |
2008 | * Initialize the VM manager structures | |
2009 | */ | |
2010 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2011 | { | |
2012 | unsigned i; | |
2013 | ||
2014 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
2015 | ||
2016 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
2017 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
2018 | amdgpu_vm_reset_id(adev, i); | |
832a902f | 2019 | amdgpu_sync_create(&adev->vm_manager.ids[i].active); |
a9a78b32 CK |
2020 | list_add_tail(&adev->vm_manager.ids[i].list, |
2021 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 2022 | } |
2d55e45a | 2023 | |
f54d1867 CW |
2024 | adev->vm_manager.fence_context = |
2025 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2026 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2027 | adev->vm_manager.seqno[i] = 0; | |
2028 | ||
2d55e45a | 2029 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 2030 | atomic64_set(&adev->vm_manager.client_counter, 0); |
284710fa | 2031 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2032 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
a9a78b32 CK |
2033 | } |
2034 | ||
ea89f8c9 CK |
2035 | /** |
2036 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2037 | * | |
2038 | * @adev: amdgpu_device pointer | |
2039 | * | |
2040 | * Cleanup the VM manager and free resources. | |
2041 | */ | |
2042 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2043 | { | |
2044 | unsigned i; | |
2045 | ||
bcb1ba35 CK |
2046 | for (i = 0; i < AMDGPU_NUM_VM; ++i) { |
2047 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; | |
2048 | ||
f54d1867 | 2049 | dma_fence_put(adev->vm_manager.ids[i].first); |
832a902f | 2050 | amdgpu_sync_free(&adev->vm_manager.ids[i].active); |
f54d1867 | 2051 | dma_fence_put(id->flushed_updates); |
7b624ad8 | 2052 | dma_fence_put(id->last_flush); |
bcb1ba35 | 2053 | } |
ea89f8c9 | 2054 | } |