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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
d38ceaf9 AD |
30 | #include <drm/drmP.h> |
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
33 | #include "amdgpu_trace.h" | |
34 | ||
35 | /* | |
36 | * GPUVM | |
37 | * GPUVM is similar to the legacy gart on older asics, however | |
38 | * rather than there being a single global gart table | |
39 | * for the entire GPU, there are multiple VM page tables active | |
40 | * at any given time. The VM page tables can contain a mix | |
41 | * vram pages and system memory pages and system memory pages | |
42 | * can be mapped as snooped (cached system pages) or unsnooped | |
43 | * (uncached system pages). | |
44 | * Each VM has an ID associated with it and there is a page table | |
45 | * associated with each VMID. When execting a command buffer, | |
46 | * the kernel tells the the ring what VMID to use for that command | |
47 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
48 | * The userspace drivers maintain their own address space and the kernel | |
49 | * sets up their pages tables accordingly when they submit their | |
50 | * command buffers and a VMID is assigned. | |
51 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
52 | * SI supports 16. | |
53 | */ | |
54 | ||
a9f87f64 CK |
55 | #define START(node) ((node)->start) |
56 | #define LAST(node) ((node)->last) | |
57 | ||
58 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
59 | START, LAST, static, amdgpu_vm_it) | |
60 | ||
61 | #undef START | |
62 | #undef LAST | |
63 | ||
f4833c4f HK |
64 | /* Local structure. Encapsulate some VM table update parameters to reduce |
65 | * the number of function parameters | |
66 | */ | |
29efc4f5 | 67 | struct amdgpu_pte_update_params { |
27c5f36f CK |
68 | /* amdgpu device we do this update for */ |
69 | struct amdgpu_device *adev; | |
49ac8a24 CK |
70 | /* optional amdgpu_vm we do this update for */ |
71 | struct amdgpu_vm *vm; | |
f4833c4f HK |
72 | /* address where to copy page table entries from */ |
73 | uint64_t src; | |
f4833c4f HK |
74 | /* indirect buffer to fill with commands */ |
75 | struct amdgpu_ib *ib; | |
afef8b8f CK |
76 | /* Function which actually does the update */ |
77 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
78 | uint64_t addr, unsigned count, uint32_t incr, | |
6b777607 | 79 | uint64_t flags); |
b4d42511 HK |
80 | /* The next two are used during VM update by CPU |
81 | * DMA addresses to use for mapping | |
82 | * Kernel pointer of PD/PT BO that needs to be updated | |
83 | */ | |
84 | dma_addr_t *pages_addr; | |
85 | void *kptr; | |
f4833c4f HK |
86 | }; |
87 | ||
284710fa CK |
88 | /* Helper to disable partial resident texture feature from a fence callback */ |
89 | struct amdgpu_prt_cb { | |
90 | struct amdgpu_device *adev; | |
91 | struct dma_fence_cb cb; | |
92 | }; | |
93 | ||
d38ceaf9 | 94 | /** |
72a7ec5c | 95 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
96 | * |
97 | * @adev: amdgpu_device pointer | |
98 | * | |
72a7ec5c | 99 | * Calculate the number of entries in a page directory or page table. |
d38ceaf9 | 100 | */ |
72a7ec5c CK |
101 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
102 | unsigned level) | |
d38ceaf9 | 103 | { |
72a7ec5c CK |
104 | if (level == 0) |
105 | /* For the root directory */ | |
106 | return adev->vm_manager.max_pfn >> | |
36b32a68 ZJ |
107 | (adev->vm_manager.block_size * |
108 | adev->vm_manager.num_level); | |
72a7ec5c CK |
109 | else if (level == adev->vm_manager.num_level) |
110 | /* For the page tables on the leaves */ | |
36b32a68 | 111 | return AMDGPU_VM_PTE_COUNT(adev); |
72a7ec5c CK |
112 | else |
113 | /* Everything in between */ | |
36b32a68 | 114 | return 1 << adev->vm_manager.block_size; |
d38ceaf9 AD |
115 | } |
116 | ||
117 | /** | |
72a7ec5c | 118 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
119 | * |
120 | * @adev: amdgpu_device pointer | |
121 | * | |
72a7ec5c | 122 | * Calculate the size of the BO for a page directory or page table in bytes. |
d38ceaf9 | 123 | */ |
72a7ec5c | 124 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 125 | { |
72a7ec5c | 126 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
127 | } |
128 | ||
129 | /** | |
56467ebf | 130 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
131 | * |
132 | * @vm: vm providing the BOs | |
3c0eea6c | 133 | * @validated: head of validation list |
56467ebf | 134 | * @entry: entry to add |
d38ceaf9 AD |
135 | * |
136 | * Add the page directory to the list of BOs to | |
56467ebf | 137 | * validate for command submission. |
d38ceaf9 | 138 | */ |
56467ebf CK |
139 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
140 | struct list_head *validated, | |
141 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 142 | { |
3f3333f8 | 143 | entry->robj = vm->root.base.bo; |
56467ebf | 144 | entry->priority = 0; |
67003a15 | 145 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 146 | entry->tv.shared = true; |
2f568dbd | 147 | entry->user_pages = NULL; |
56467ebf CK |
148 | list_add(&entry->tv.head, validated); |
149 | } | |
d38ceaf9 | 150 | |
56467ebf | 151 | /** |
f7da30d9 | 152 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
56467ebf | 153 | * |
5a712a87 | 154 | * @adev: amdgpu device pointer |
56467ebf | 155 | * @vm: vm providing the BOs |
f7da30d9 CK |
156 | * @validate: callback to do the validation |
157 | * @param: parameter for the validation callback | |
d38ceaf9 | 158 | * |
f7da30d9 | 159 | * Validate the page table BOs on command submission if neccessary. |
d38ceaf9 | 160 | */ |
f7da30d9 CK |
161 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
162 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
163 | void *param) | |
d38ceaf9 | 164 | { |
3f3333f8 CK |
165 | struct ttm_bo_global *glob = adev->mman.bdev.glob; |
166 | int r; | |
d38ceaf9 | 167 | |
3f3333f8 CK |
168 | spin_lock(&vm->status_lock); |
169 | while (!list_empty(&vm->evicted)) { | |
170 | struct amdgpu_vm_bo_base *bo_base; | |
171 | struct amdgpu_bo *bo; | |
5a712a87 | 172 | |
3f3333f8 CK |
173 | bo_base = list_first_entry(&vm->evicted, |
174 | struct amdgpu_vm_bo_base, | |
175 | vm_status); | |
176 | spin_unlock(&vm->status_lock); | |
d711e139 | 177 | |
3f3333f8 CK |
178 | bo = bo_base->bo; |
179 | BUG_ON(!bo); | |
180 | if (bo->parent) { | |
181 | r = validate(param, bo); | |
182 | if (r) | |
183 | return r; | |
34d7be5d | 184 | |
3f3333f8 CK |
185 | spin_lock(&glob->lru_lock); |
186 | ttm_bo_move_to_lru_tail(&bo->tbo); | |
187 | if (bo->shadow) | |
188 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo); | |
189 | spin_unlock(&glob->lru_lock); | |
190 | } | |
191 | ||
192 | if (vm->use_cpu_for_update) { | |
193 | r = amdgpu_bo_kmap(bo, NULL); | |
194 | if (r) | |
195 | return r; | |
196 | } | |
197 | ||
198 | spin_lock(&vm->status_lock); | |
ea09729c | 199 | list_move(&bo_base->vm_status, &vm->relocated); |
3f3333f8 CK |
200 | } |
201 | spin_unlock(&vm->status_lock); | |
34d7be5d CK |
202 | |
203 | return 0; | |
204 | } | |
205 | ||
206 | /** | |
207 | * amdgpu_vm_ready - check VM is ready for updates | |
208 | * | |
34d7be5d CK |
209 | * @vm: VM to check |
210 | * | |
211 | * Check if all VM PDs/PTs are ready for updates | |
212 | */ | |
3f3333f8 | 213 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
34d7be5d | 214 | { |
3f3333f8 CK |
215 | bool ready; |
216 | ||
217 | spin_lock(&vm->status_lock); | |
218 | ready = list_empty(&vm->evicted); | |
219 | spin_unlock(&vm->status_lock); | |
34d7be5d | 220 | |
3f3333f8 | 221 | return ready; |
34d7be5d CK |
222 | } |
223 | ||
d711e139 | 224 | /** |
f566ceb1 CK |
225 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels |
226 | * | |
227 | * @adev: amdgpu_device pointer | |
228 | * @vm: requested vm | |
229 | * @saddr: start of the address range | |
230 | * @eaddr: end of the address range | |
231 | * | |
232 | * Make sure the page directories and page tables are allocated | |
233 | */ | |
234 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
235 | struct amdgpu_vm *vm, | |
236 | struct amdgpu_vm_pt *parent, | |
237 | uint64_t saddr, uint64_t eaddr, | |
238 | unsigned level) | |
239 | { | |
240 | unsigned shift = (adev->vm_manager.num_level - level) * | |
36b32a68 | 241 | adev->vm_manager.block_size; |
f566ceb1 CK |
242 | unsigned pt_idx, from, to; |
243 | int r; | |
3c824172 | 244 | u64 flags; |
51ac7eec | 245 | uint64_t init_value = 0; |
f566ceb1 CK |
246 | |
247 | if (!parent->entries) { | |
248 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
249 | ||
2098105e MH |
250 | parent->entries = kvmalloc_array(num_entries, |
251 | sizeof(struct amdgpu_vm_pt), | |
252 | GFP_KERNEL | __GFP_ZERO); | |
f566ceb1 CK |
253 | if (!parent->entries) |
254 | return -ENOMEM; | |
255 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
256 | } | |
257 | ||
1866bac8 FK |
258 | from = saddr >> shift; |
259 | to = eaddr >> shift; | |
260 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
261 | to >= amdgpu_vm_num_entries(adev, level)) | |
262 | return -EINVAL; | |
f566ceb1 CK |
263 | |
264 | if (to > parent->last_entry_used) | |
265 | parent->last_entry_used = to; | |
266 | ||
267 | ++level; | |
1866bac8 FK |
268 | saddr = saddr & ((1 << shift) - 1); |
269 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 | 270 | |
3c824172 HK |
271 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
272 | AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
273 | if (vm->use_cpu_for_update) | |
274 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
275 | else | |
276 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
277 | AMDGPU_GEM_CREATE_SHADOW); | |
278 | ||
51ac7eec YZ |
279 | if (vm->pte_support_ats) { |
280 | init_value = AMDGPU_PTE_SYSTEM; | |
281 | if (level != adev->vm_manager.num_level - 1) | |
282 | init_value |= AMDGPU_PDE_PTE; | |
283 | } | |
284 | ||
f566ceb1 CK |
285 | /* walk over the address space and allocate the page tables */ |
286 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
3f3333f8 | 287 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
f566ceb1 CK |
288 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
289 | struct amdgpu_bo *pt; | |
290 | ||
3f3333f8 | 291 | if (!entry->base.bo) { |
f566ceb1 CK |
292 | r = amdgpu_bo_create(adev, |
293 | amdgpu_vm_bo_size(adev, level), | |
294 | AMDGPU_GPU_PAGE_SIZE, true, | |
295 | AMDGPU_GEM_DOMAIN_VRAM, | |
3c824172 | 296 | flags, |
51ac7eec | 297 | NULL, resv, init_value, &pt); |
f566ceb1 CK |
298 | if (r) |
299 | return r; | |
300 | ||
0a096fb6 CK |
301 | if (vm->use_cpu_for_update) { |
302 | r = amdgpu_bo_kmap(pt, NULL); | |
303 | if (r) { | |
304 | amdgpu_bo_unref(&pt); | |
305 | return r; | |
306 | } | |
307 | } | |
308 | ||
f566ceb1 CK |
309 | /* Keep a reference to the root directory to avoid |
310 | * freeing them up in the wrong order. | |
311 | */ | |
3f3333f8 | 312 | pt->parent = amdgpu_bo_ref(vm->root.base.bo); |
f566ceb1 | 313 | |
3f3333f8 CK |
314 | entry->base.vm = vm; |
315 | entry->base.bo = pt; | |
316 | list_add_tail(&entry->base.bo_list, &pt->va); | |
ea09729c CK |
317 | spin_lock(&vm->status_lock); |
318 | list_add(&entry->base.vm_status, &vm->relocated); | |
319 | spin_unlock(&vm->status_lock); | |
320 | entry->addr = ~0ULL; | |
f566ceb1 CK |
321 | } |
322 | ||
323 | if (level < adev->vm_manager.num_level) { | |
1866bac8 FK |
324 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
325 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
326 | ((1 << shift) - 1); | |
327 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
328 | sub_eaddr, level); | |
f566ceb1 CK |
329 | if (r) |
330 | return r; | |
331 | } | |
332 | } | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
663e4577 CK |
337 | /** |
338 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
339 | * | |
340 | * @adev: amdgpu_device pointer | |
341 | * @vm: VM to allocate page tables for | |
342 | * @saddr: Start address which needs to be allocated | |
343 | * @size: Size from start address we need. | |
344 | * | |
345 | * Make sure the page tables are allocated. | |
346 | */ | |
347 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
348 | struct amdgpu_vm *vm, | |
349 | uint64_t saddr, uint64_t size) | |
350 | { | |
22770e5a | 351 | uint64_t last_pfn; |
663e4577 | 352 | uint64_t eaddr; |
663e4577 CK |
353 | |
354 | /* validate the parameters */ | |
355 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
356 | return -EINVAL; | |
357 | ||
358 | eaddr = saddr + size - 1; | |
359 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
360 | if (last_pfn >= adev->vm_manager.max_pfn) { | |
22770e5a | 361 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", |
663e4577 CK |
362 | last_pfn, adev->vm_manager.max_pfn); |
363 | return -EINVAL; | |
364 | } | |
365 | ||
366 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
367 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
368 | ||
f566ceb1 | 369 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); |
663e4577 CK |
370 | } |
371 | ||
641e9400 CK |
372 | /** |
373 | * amdgpu_vm_had_gpu_reset - check if reset occured since last use | |
374 | * | |
375 | * @adev: amdgpu_device pointer | |
376 | * @id: VMID structure | |
377 | * | |
378 | * Check if GPU reset occured since last use of the VMID. | |
379 | */ | |
380 | static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev, | |
381 | struct amdgpu_vm_id *id) | |
192b7dcb CZ |
382 | { |
383 | return id->current_gpu_reset_count != | |
641e9400 | 384 | atomic_read(&adev->gpu_reset_counter); |
192b7dcb CZ |
385 | } |
386 | ||
7a63eb23 CZ |
387 | static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub) |
388 | { | |
389 | return !!vm->reserved_vmid[vmhub]; | |
390 | } | |
391 | ||
392 | /* idr_mgr->lock must be held */ | |
393 | static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, | |
394 | struct amdgpu_ring *ring, | |
395 | struct amdgpu_sync *sync, | |
396 | struct dma_fence *fence, | |
397 | struct amdgpu_job *job) | |
398 | { | |
399 | struct amdgpu_device *adev = ring->adev; | |
400 | unsigned vmhub = ring->funcs->vmhub; | |
401 | uint64_t fence_context = adev->fence_context + ring->idx; | |
402 | struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub]; | |
403 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
404 | struct dma_fence *updates = sync->last_vm_update; | |
405 | int r = 0; | |
406 | struct dma_fence *flushed, *tmp; | |
6f1ceabb | 407 | bool needs_flush = vm->use_cpu_for_update; |
7a63eb23 CZ |
408 | |
409 | flushed = id->flushed_updates; | |
410 | if ((amdgpu_vm_had_gpu_reset(adev, id)) || | |
411 | (atomic64_read(&id->owner) != vm->client_id) || | |
412 | (job->vm_pd_addr != id->pd_gpu_addr) || | |
413 | (updates && (!flushed || updates->context != flushed->context || | |
414 | dma_fence_is_later(updates, flushed))) || | |
415 | (!id->last_flush || (id->last_flush->context != fence_context && | |
416 | !dma_fence_is_signaled(id->last_flush)))) { | |
417 | needs_flush = true; | |
418 | /* to prevent one context starved by another context */ | |
419 | id->pd_gpu_addr = 0; | |
420 | tmp = amdgpu_sync_peek_fence(&id->active, ring); | |
421 | if (tmp) { | |
422 | r = amdgpu_sync_fence(adev, sync, tmp); | |
423 | return r; | |
424 | } | |
425 | } | |
426 | ||
427 | /* Good we can use this VMID. Remember this submission as | |
428 | * user of the VMID. | |
429 | */ | |
430 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
431 | if (r) | |
432 | goto out; | |
433 | ||
434 | if (updates && (!flushed || updates->context != flushed->context || | |
435 | dma_fence_is_later(updates, flushed))) { | |
436 | dma_fence_put(id->flushed_updates); | |
437 | id->flushed_updates = dma_fence_get(updates); | |
438 | } | |
439 | id->pd_gpu_addr = job->vm_pd_addr; | |
7a63eb23 CZ |
440 | atomic64_set(&id->owner, vm->client_id); |
441 | job->vm_needs_flush = needs_flush; | |
442 | if (needs_flush) { | |
443 | dma_fence_put(id->last_flush); | |
444 | id->last_flush = NULL; | |
445 | } | |
446 | job->vm_id = id - id_mgr->ids; | |
447 | trace_amdgpu_vm_grab_id(vm, ring, job); | |
448 | out: | |
449 | return r; | |
450 | } | |
451 | ||
d38ceaf9 AD |
452 | /** |
453 | * amdgpu_vm_grab_id - allocate the next free VMID | |
454 | * | |
d38ceaf9 | 455 | * @vm: vm to allocate id for |
7f8a5290 CK |
456 | * @ring: ring we want to submit job to |
457 | * @sync: sync object where we add dependencies | |
94dd0a4a | 458 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 459 | * |
7f8a5290 | 460 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 461 | */ |
7f8a5290 | 462 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
f54d1867 | 463 | struct amdgpu_sync *sync, struct dma_fence *fence, |
fd53be30 | 464 | struct amdgpu_job *job) |
d38ceaf9 | 465 | { |
d38ceaf9 | 466 | struct amdgpu_device *adev = ring->adev; |
2e819849 | 467 | unsigned vmhub = ring->funcs->vmhub; |
7645670d | 468 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
090b767e | 469 | uint64_t fence_context = adev->fence_context + ring->idx; |
f54d1867 | 470 | struct dma_fence *updates = sync->last_vm_update; |
8d76001e | 471 | struct amdgpu_vm_id *id, *idle; |
f54d1867 | 472 | struct dma_fence **fences; |
1fbb2e92 CK |
473 | unsigned i; |
474 | int r = 0; | |
475 | ||
7a63eb23 CZ |
476 | mutex_lock(&id_mgr->lock); |
477 | if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) { | |
478 | r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job); | |
479 | mutex_unlock(&id_mgr->lock); | |
480 | return r; | |
481 | } | |
7645670d | 482 | fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); |
7a63eb23 CZ |
483 | if (!fences) { |
484 | mutex_unlock(&id_mgr->lock); | |
1fbb2e92 | 485 | return -ENOMEM; |
7a63eb23 | 486 | } |
36fd7c5c | 487 | /* Check if we have an idle VMID */ |
1fbb2e92 | 488 | i = 0; |
7645670d | 489 | list_for_each_entry(idle, &id_mgr->ids_lru, list) { |
1fbb2e92 CK |
490 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
491 | if (!fences[i]) | |
36fd7c5c | 492 | break; |
1fbb2e92 | 493 | ++i; |
36fd7c5c CK |
494 | } |
495 | ||
1fbb2e92 | 496 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
7645670d | 497 | if (&idle->list == &id_mgr->ids_lru) { |
1fbb2e92 CK |
498 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
499 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
f54d1867 | 500 | struct dma_fence_array *array; |
1fbb2e92 CK |
501 | unsigned j; |
502 | ||
503 | for (j = 0; j < i; ++j) | |
f54d1867 | 504 | dma_fence_get(fences[j]); |
1fbb2e92 | 505 | |
f54d1867 | 506 | array = dma_fence_array_create(i, fences, fence_context, |
1fbb2e92 CK |
507 | seqno, true); |
508 | if (!array) { | |
509 | for (j = 0; j < i; ++j) | |
f54d1867 | 510 | dma_fence_put(fences[j]); |
1fbb2e92 CK |
511 | kfree(fences); |
512 | r = -ENOMEM; | |
513 | goto error; | |
514 | } | |
515 | ||
516 | ||
517 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
f54d1867 | 518 | dma_fence_put(&array->base); |
1fbb2e92 CK |
519 | if (r) |
520 | goto error; | |
521 | ||
7645670d | 522 | mutex_unlock(&id_mgr->lock); |
1fbb2e92 CK |
523 | return 0; |
524 | ||
525 | } | |
526 | kfree(fences); | |
527 | ||
6f1ceabb | 528 | job->vm_needs_flush = vm->use_cpu_for_update; |
1fbb2e92 | 529 | /* Check if we can use a VMID already assigned to this VM */ |
7645670d | 530 | list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) { |
f54d1867 | 531 | struct dma_fence *flushed; |
6f1ceabb | 532 | bool needs_flush = vm->use_cpu_for_update; |
1fbb2e92 | 533 | |
1fbb2e92 | 534 | /* Check all the prerequisites to using this VMID */ |
641e9400 | 535 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
6adb0513 | 536 | continue; |
1fbb2e92 CK |
537 | |
538 | if (atomic64_read(&id->owner) != vm->client_id) | |
539 | continue; | |
540 | ||
fd53be30 | 541 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
542 | continue; |
543 | ||
87c910d8 CK |
544 | if (!id->last_flush || |
545 | (id->last_flush->context != fence_context && | |
546 | !dma_fence_is_signaled(id->last_flush))) | |
547 | needs_flush = true; | |
1fbb2e92 CK |
548 | |
549 | flushed = id->flushed_updates; | |
87c910d8 CK |
550 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) |
551 | needs_flush = true; | |
552 | ||
553 | /* Concurrent flushes are only possible starting with Vega10 */ | |
554 | if (adev->asic_type < CHIP_VEGA10 && needs_flush) | |
1fbb2e92 CK |
555 | continue; |
556 | ||
3dab83be CK |
557 | /* Good we can use this VMID. Remember this submission as |
558 | * user of the VMID. | |
559 | */ | |
1fbb2e92 CK |
560 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
561 | if (r) | |
562 | goto error; | |
8d76001e | 563 | |
87c910d8 CK |
564 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) { |
565 | dma_fence_put(id->flushed_updates); | |
566 | id->flushed_updates = dma_fence_get(updates); | |
567 | } | |
8d76001e | 568 | |
87c910d8 CK |
569 | if (needs_flush) |
570 | goto needs_flush; | |
571 | else | |
572 | goto no_flush_needed; | |
8d76001e | 573 | |
4f618e73 | 574 | }; |
8d76001e | 575 | |
1fbb2e92 CK |
576 | /* Still no ID to use? Then use the idle one found earlier */ |
577 | id = idle; | |
8e9fbeb5 | 578 | |
1fbb2e92 CK |
579 | /* Remember this submission as user of the VMID */ |
580 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
581 | if (r) |
582 | goto error; | |
94dd0a4a | 583 | |
87c910d8 | 584 | id->pd_gpu_addr = job->vm_pd_addr; |
f54d1867 CW |
585 | dma_fence_put(id->flushed_updates); |
586 | id->flushed_updates = dma_fence_get(updates); | |
0ea54b9b | 587 | atomic64_set(&id->owner, vm->client_id); |
d38ceaf9 | 588 | |
87c910d8 CK |
589 | needs_flush: |
590 | job->vm_needs_flush = true; | |
591 | dma_fence_put(id->last_flush); | |
592 | id->last_flush = NULL; | |
593 | ||
594 | no_flush_needed: | |
595 | list_move_tail(&id->list, &id_mgr->ids_lru); | |
596 | ||
7645670d | 597 | job->vm_id = id - id_mgr->ids; |
c5296d14 | 598 | trace_amdgpu_vm_grab_id(vm, ring, job); |
832a902f CK |
599 | |
600 | error: | |
7645670d | 601 | mutex_unlock(&id_mgr->lock); |
a9a78b32 | 602 | return r; |
d38ceaf9 AD |
603 | } |
604 | ||
1e9ef26f CZ |
605 | static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev, |
606 | struct amdgpu_vm *vm, | |
607 | unsigned vmhub) | |
608 | { | |
609 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
610 | ||
611 | mutex_lock(&id_mgr->lock); | |
612 | if (vm->reserved_vmid[vmhub]) { | |
613 | list_add(&vm->reserved_vmid[vmhub]->list, | |
614 | &id_mgr->ids_lru); | |
615 | vm->reserved_vmid[vmhub] = NULL; | |
c3505770 | 616 | atomic_dec(&id_mgr->reserved_vmid_num); |
1e9ef26f CZ |
617 | } |
618 | mutex_unlock(&id_mgr->lock); | |
619 | } | |
620 | ||
621 | static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev, | |
622 | struct amdgpu_vm *vm, | |
623 | unsigned vmhub) | |
624 | { | |
625 | struct amdgpu_vm_id_manager *id_mgr; | |
626 | struct amdgpu_vm_id *idle; | |
627 | int r = 0; | |
628 | ||
629 | id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
630 | mutex_lock(&id_mgr->lock); | |
631 | if (vm->reserved_vmid[vmhub]) | |
632 | goto unlock; | |
c3505770 CZ |
633 | if (atomic_inc_return(&id_mgr->reserved_vmid_num) > |
634 | AMDGPU_VM_MAX_RESERVED_VMID) { | |
635 | DRM_ERROR("Over limitation of reserved vmid\n"); | |
636 | atomic_dec(&id_mgr->reserved_vmid_num); | |
637 | r = -EINVAL; | |
638 | goto unlock; | |
639 | } | |
1e9ef26f CZ |
640 | /* Select the first entry VMID */ |
641 | idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list); | |
642 | list_del_init(&idle->list); | |
643 | vm->reserved_vmid[vmhub] = idle; | |
644 | mutex_unlock(&id_mgr->lock); | |
645 | ||
646 | return 0; | |
647 | unlock: | |
648 | mutex_unlock(&id_mgr->lock); | |
649 | return r; | |
650 | } | |
651 | ||
e59c0205 AX |
652 | /** |
653 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
654 | * | |
655 | * @adev: amdgpu_device pointer | |
656 | */ | |
657 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 658 | { |
a1255107 | 659 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
660 | bool has_compute_vm_bug; |
661 | struct amdgpu_ring *ring; | |
662 | int i; | |
93dcc37d | 663 | |
e59c0205 | 664 | has_compute_vm_bug = false; |
93dcc37d AD |
665 | |
666 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
e59c0205 AX |
667 | if (ip_block) { |
668 | /* Compute has a VM bug for GFX version < 7. | |
669 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
670 | if (ip_block->version->major <= 7) | |
671 | has_compute_vm_bug = true; | |
672 | else if (ip_block->version->major == 8) | |
673 | if (adev->gfx.mec_fw_version < 673) | |
674 | has_compute_vm_bug = true; | |
675 | } | |
93dcc37d | 676 | |
e59c0205 AX |
677 | for (i = 0; i < adev->num_rings; i++) { |
678 | ring = adev->rings[i]; | |
679 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
680 | /* only compute rings */ | |
681 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 682 | else |
e59c0205 | 683 | ring->has_compute_vm_bug = false; |
93dcc37d | 684 | } |
93dcc37d AD |
685 | } |
686 | ||
b9bf33d5 CZ |
687 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
688 | struct amdgpu_job *job) | |
e60f8db5 | 689 | { |
b9bf33d5 CZ |
690 | struct amdgpu_device *adev = ring->adev; |
691 | unsigned vmhub = ring->funcs->vmhub; | |
692 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
693 | struct amdgpu_vm_id *id; | |
694 | bool gds_switch_needed; | |
e59c0205 | 695 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 CZ |
696 | |
697 | if (job->vm_id == 0) | |
698 | return false; | |
699 | id = &id_mgr->ids[job->vm_id]; | |
700 | gds_switch_needed = ring->funcs->emit_gds_switch && ( | |
701 | id->gds_base != job->gds_base || | |
702 | id->gds_size != job->gds_size || | |
703 | id->gws_base != job->gws_base || | |
704 | id->gws_size != job->gws_size || | |
705 | id->oa_base != job->oa_base || | |
706 | id->oa_size != job->oa_size); | |
e60f8db5 | 707 | |
b9bf33d5 CZ |
708 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
709 | return true; | |
e60f8db5 | 710 | |
bb37b67d | 711 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
712 | } |
713 | ||
9a4b7d4c HK |
714 | static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) |
715 | { | |
716 | return (adev->mc.real_vram_size == adev->mc.visible_vram_size); | |
e60f8db5 AX |
717 | } |
718 | ||
d38ceaf9 AD |
719 | /** |
720 | * amdgpu_vm_flush - hardware flush the vm | |
721 | * | |
722 | * @ring: ring to use for flush | |
cffadc83 | 723 | * @vm_id: vmid number to use |
4ff37a83 | 724 | * @pd_addr: address of the page directory |
d38ceaf9 | 725 | * |
4ff37a83 | 726 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 727 | */ |
8fdf074f | 728 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 729 | { |
971fe9a9 | 730 | struct amdgpu_device *adev = ring->adev; |
7645670d CK |
731 | unsigned vmhub = ring->funcs->vmhub; |
732 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
733 | struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id]; | |
d564a06e | 734 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
735 | id->gds_base != job->gds_base || |
736 | id->gds_size != job->gds_size || | |
737 | id->gws_base != job->gws_base || | |
738 | id->gws_size != job->gws_size || | |
739 | id->oa_base != job->oa_base || | |
740 | id->oa_size != job->oa_size); | |
de37e68a | 741 | bool vm_flush_needed = job->vm_needs_flush; |
c0e51931 | 742 | unsigned patch_offset = 0; |
41d9eb2c | 743 | int r; |
d564a06e | 744 | |
f7d015b9 CK |
745 | if (amdgpu_vm_had_gpu_reset(adev, id)) { |
746 | gds_switch_needed = true; | |
747 | vm_flush_needed = true; | |
748 | } | |
971fe9a9 | 749 | |
8fdf074f | 750 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 751 | return 0; |
41d9eb2c | 752 | |
c0e51931 CK |
753 | if (ring->funcs->init_cond_exec) |
754 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 755 | |
8fdf074f ML |
756 | if (need_pipe_sync) |
757 | amdgpu_ring_emit_pipeline_sync(ring); | |
758 | ||
f7d015b9 | 759 | if (ring->funcs->emit_vm_flush && vm_flush_needed) { |
c0e51931 | 760 | struct dma_fence *fence; |
41d9eb2c | 761 | |
9a94f5a5 CK |
762 | trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr); |
763 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
e9d672b2 | 764 | |
c0e51931 CK |
765 | r = amdgpu_fence_emit(ring, &fence); |
766 | if (r) | |
767 | return r; | |
e9d672b2 | 768 | |
7645670d | 769 | mutex_lock(&id_mgr->lock); |
c0e51931 CK |
770 | dma_fence_put(id->last_flush); |
771 | id->last_flush = fence; | |
bea39672 | 772 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
7645670d | 773 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 774 | } |
e9d672b2 | 775 | |
7c4378f4 | 776 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
777 | id->gds_base = job->gds_base; |
778 | id->gds_size = job->gds_size; | |
779 | id->gws_base = job->gws_base; | |
780 | id->gws_size = job->gws_size; | |
781 | id->oa_base = job->oa_base; | |
782 | id->oa_size = job->oa_size; | |
783 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base, | |
784 | job->gds_size, job->gws_base, | |
785 | job->gws_size, job->oa_base, | |
786 | job->oa_size); | |
787 | } | |
788 | ||
789 | if (ring->funcs->patch_cond_exec) | |
790 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
791 | ||
792 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
793 | if (ring->funcs->emit_switch_buffer) { | |
794 | amdgpu_ring_emit_switch_buffer(ring); | |
795 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 796 | } |
41d9eb2c | 797 | return 0; |
971fe9a9 CK |
798 | } |
799 | ||
800 | /** | |
801 | * amdgpu_vm_reset_id - reset VMID to zero | |
802 | * | |
803 | * @adev: amdgpu device structure | |
804 | * @vm_id: vmid number to use | |
805 | * | |
806 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
807 | */ | |
7645670d CK |
808 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
809 | unsigned vmid) | |
971fe9a9 | 810 | { |
7645670d CK |
811 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
812 | struct amdgpu_vm_id *id = &id_mgr->ids[vmid]; | |
bcb1ba35 | 813 | |
b3c85a0f | 814 | atomic64_set(&id->owner, 0); |
bcb1ba35 CK |
815 | id->gds_base = 0; |
816 | id->gds_size = 0; | |
817 | id->gws_base = 0; | |
818 | id->gws_size = 0; | |
819 | id->oa_base = 0; | |
820 | id->oa_size = 0; | |
d38ceaf9 AD |
821 | } |
822 | ||
b3c85a0f CK |
823 | /** |
824 | * amdgpu_vm_reset_all_id - reset VMID to zero | |
825 | * | |
826 | * @adev: amdgpu device structure | |
827 | * | |
828 | * Reset VMID to force flush on next use | |
829 | */ | |
830 | void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev) | |
831 | { | |
832 | unsigned i, j; | |
833 | ||
834 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
835 | struct amdgpu_vm_id_manager *id_mgr = | |
836 | &adev->vm_manager.id_mgr[i]; | |
837 | ||
838 | for (j = 1; j < id_mgr->num_ids; ++j) | |
839 | amdgpu_vm_reset_id(adev, i, j); | |
840 | } | |
841 | } | |
842 | ||
d38ceaf9 AD |
843 | /** |
844 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
845 | * | |
846 | * @vm: requested vm | |
847 | * @bo: requested buffer object | |
848 | * | |
8843dbbb | 849 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
850 | * Search inside the @bos vm list for the requested vm |
851 | * Returns the found bo_va or NULL if none is found | |
852 | * | |
853 | * Object has to be reserved! | |
854 | */ | |
855 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
856 | struct amdgpu_bo *bo) | |
857 | { | |
858 | struct amdgpu_bo_va *bo_va; | |
859 | ||
ec681545 CK |
860 | list_for_each_entry(bo_va, &bo->va, base.bo_list) { |
861 | if (bo_va->base.vm == vm) { | |
d38ceaf9 AD |
862 | return bo_va; |
863 | } | |
864 | } | |
865 | return NULL; | |
866 | } | |
867 | ||
868 | /** | |
afef8b8f | 869 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 870 | * |
29efc4f5 | 871 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
872 | * @pe: addr of the page entry |
873 | * @addr: dst addr to write into pe | |
874 | * @count: number of page entries to update | |
875 | * @incr: increase next addr by incr bytes | |
876 | * @flags: hw access flags | |
d38ceaf9 AD |
877 | * |
878 | * Traces the parameters and calls the right asic functions | |
879 | * to setup the page table using the DMA. | |
880 | */ | |
afef8b8f CK |
881 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
882 | uint64_t pe, uint64_t addr, | |
883 | unsigned count, uint32_t incr, | |
6b777607 | 884 | uint64_t flags) |
d38ceaf9 | 885 | { |
ec2f05f0 | 886 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 887 | |
afef8b8f | 888 | if (count < 3) { |
de9ea7bd CK |
889 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
890 | addr | flags, count, incr); | |
d38ceaf9 AD |
891 | |
892 | } else { | |
27c5f36f | 893 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
894 | count, incr, flags); |
895 | } | |
896 | } | |
897 | ||
afef8b8f CK |
898 | /** |
899 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
900 | * | |
901 | * @params: see amdgpu_pte_update_params definition | |
902 | * @pe: addr of the page entry | |
903 | * @addr: dst addr to write into pe | |
904 | * @count: number of page entries to update | |
905 | * @incr: increase next addr by incr bytes | |
906 | * @flags: hw access flags | |
907 | * | |
908 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
909 | */ | |
910 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
911 | uint64_t pe, uint64_t addr, | |
912 | unsigned count, uint32_t incr, | |
6b777607 | 913 | uint64_t flags) |
afef8b8f | 914 | { |
ec2f05f0 | 915 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 916 | |
ec2f05f0 CK |
917 | |
918 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
919 | ||
920 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
921 | } |
922 | ||
d38ceaf9 | 923 | /** |
b07c9d2a | 924 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 925 | * |
b07c9d2a | 926 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
927 | * @addr: the unmapped addr |
928 | * | |
929 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 930 | * to and return the pointer for the page table entry. |
d38ceaf9 | 931 | */ |
de9ea7bd | 932 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
933 | { |
934 | uint64_t result; | |
935 | ||
de9ea7bd CK |
936 | /* page table offset */ |
937 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 938 | |
de9ea7bd CK |
939 | /* in case cpu page size != gpu page size*/ |
940 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 941 | |
b07c9d2a | 942 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
943 | |
944 | return result; | |
945 | } | |
946 | ||
3c824172 HK |
947 | /** |
948 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU | |
949 | * | |
950 | * @params: see amdgpu_pte_update_params definition | |
951 | * @pe: kmap addr of the page entry | |
952 | * @addr: dst addr to write into pe | |
953 | * @count: number of page entries to update | |
954 | * @incr: increase next addr by incr bytes | |
955 | * @flags: hw access flags | |
956 | * | |
957 | * Write count number of PT/PD entries directly. | |
958 | */ | |
959 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, | |
960 | uint64_t pe, uint64_t addr, | |
961 | unsigned count, uint32_t incr, | |
962 | uint64_t flags) | |
963 | { | |
964 | unsigned int i; | |
b4d42511 | 965 | uint64_t value; |
3c824172 | 966 | |
03918b36 CK |
967 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
968 | ||
3c824172 | 969 | for (i = 0; i < count; i++) { |
b4d42511 HK |
970 | value = params->pages_addr ? |
971 | amdgpu_vm_map_gart(params->pages_addr, addr) : | |
972 | addr; | |
a1924005 | 973 | amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe, |
b4d42511 | 974 | i, value, flags); |
3c824172 HK |
975 | addr += incr; |
976 | } | |
3c824172 HK |
977 | } |
978 | ||
a33cab7a CK |
979 | static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
980 | void *owner) | |
3c824172 HK |
981 | { |
982 | struct amdgpu_sync sync; | |
983 | int r; | |
984 | ||
985 | amdgpu_sync_create(&sync); | |
3f3333f8 | 986 | amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner); |
3c824172 HK |
987 | r = amdgpu_sync_wait(&sync, true); |
988 | amdgpu_sync_free(&sync); | |
989 | ||
990 | return r; | |
991 | } | |
992 | ||
f8991bab | 993 | /* |
194d2161 | 994 | * amdgpu_vm_update_level - update a single level in the hierarchy |
f8991bab CK |
995 | * |
996 | * @adev: amdgpu_device pointer | |
997 | * @vm: requested vm | |
194d2161 | 998 | * @parent: parent directory |
f8991bab | 999 | * |
194d2161 | 1000 | * Makes sure all entries in @parent are up to date. |
f8991bab CK |
1001 | * Returns 0 for success, error for failure. |
1002 | */ | |
194d2161 CK |
1003 | static int amdgpu_vm_update_level(struct amdgpu_device *adev, |
1004 | struct amdgpu_vm *vm, | |
ea09729c | 1005 | struct amdgpu_vm_pt *parent) |
d38ceaf9 | 1006 | { |
f8991bab | 1007 | struct amdgpu_bo *shadow; |
a1924005 HK |
1008 | struct amdgpu_ring *ring = NULL; |
1009 | uint64_t pd_addr, shadow_addr = 0; | |
f8991bab | 1010 | uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; |
a1924005 | 1011 | unsigned count = 0, pt_idx, ndw = 0; |
d71518b5 | 1012 | struct amdgpu_job *job; |
29efc4f5 | 1013 | struct amdgpu_pte_update_params params; |
f54d1867 | 1014 | struct dma_fence *fence = NULL; |
ea09729c | 1015 | uint32_t incr; |
d5fc5e82 | 1016 | |
d38ceaf9 AD |
1017 | int r; |
1018 | ||
194d2161 CK |
1019 | if (!parent->entries) |
1020 | return 0; | |
2d55e45a | 1021 | |
3c824172 HK |
1022 | memset(¶ms, 0, sizeof(params)); |
1023 | params.adev = adev; | |
3f3333f8 | 1024 | shadow = parent->base.bo->shadow; |
d38ceaf9 | 1025 | |
69277985 | 1026 | if (vm->use_cpu_for_update) { |
3f3333f8 | 1027 | pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); |
a33cab7a | 1028 | r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); |
0a096fb6 | 1029 | if (unlikely(r)) |
3c824172 | 1030 | return r; |
0a096fb6 | 1031 | |
3c824172 HK |
1032 | params.func = amdgpu_vm_cpu_set_ptes; |
1033 | } else { | |
3c824172 HK |
1034 | ring = container_of(vm->entity.sched, struct amdgpu_ring, |
1035 | sched); | |
d38ceaf9 | 1036 | |
3c824172 HK |
1037 | /* padding, etc. */ |
1038 | ndw = 64; | |
194d2161 | 1039 | |
3c824172 HK |
1040 | /* assume the worst case */ |
1041 | ndw += parent->last_entry_used * 6; | |
1042 | ||
3f3333f8 | 1043 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); |
3c824172 HK |
1044 | |
1045 | if (shadow) { | |
1046 | shadow_addr = amdgpu_bo_gpu_offset(shadow); | |
1047 | ndw *= 2; | |
1048 | } else { | |
1049 | shadow_addr = 0; | |
1050 | } | |
1051 | ||
1052 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
f8991bab CK |
1053 | if (r) |
1054 | return r; | |
f8991bab | 1055 | |
3c824172 HK |
1056 | params.ib = &job->ibs[0]; |
1057 | params.func = amdgpu_vm_do_set_ptes; | |
1058 | } | |
d71518b5 | 1059 | |
d38ceaf9 | 1060 | |
194d2161 CK |
1061 | /* walk over the address space and update the directory */ |
1062 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
ea09729c CK |
1063 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
1064 | struct amdgpu_bo *bo = entry->base.bo; | |
d38ceaf9 AD |
1065 | uint64_t pde, pt; |
1066 | ||
1067 | if (bo == NULL) | |
1068 | continue; | |
1069 | ||
ea09729c CK |
1070 | spin_lock(&vm->status_lock); |
1071 | list_del_init(&entry->base.vm_status); | |
1072 | spin_unlock(&vm->status_lock); | |
1073 | ||
d38ceaf9 | 1074 | pt = amdgpu_bo_gpu_offset(bo); |
53e2e91d | 1075 | pt = amdgpu_gart_get_vm_pde(adev, pt); |
4ab4016a CK |
1076 | /* Don't update huge pages here */ |
1077 | if ((parent->entries[pt_idx].addr & AMDGPU_PDE_PTE) || | |
1078 | parent->entries[pt_idx].addr == (pt | AMDGPU_PTE_VALID)) | |
f8991bab CK |
1079 | continue; |
1080 | ||
4ab4016a | 1081 | parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID; |
d38ceaf9 AD |
1082 | |
1083 | pde = pd_addr + pt_idx * 8; | |
ea09729c | 1084 | incr = amdgpu_bo_size(bo); |
d38ceaf9 | 1085 | if (((last_pde + 8 * count) != pde) || |
96105e53 CK |
1086 | ((last_pt + incr * count) != pt) || |
1087 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
d38ceaf9 AD |
1088 | |
1089 | if (count) { | |
f8991bab | 1090 | if (shadow) |
3c824172 HK |
1091 | params.func(¶ms, |
1092 | last_shadow, | |
1093 | last_pt, count, | |
1094 | incr, | |
1095 | AMDGPU_PTE_VALID); | |
1096 | ||
1097 | params.func(¶ms, last_pde, | |
1098 | last_pt, count, incr, | |
1099 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
1100 | } |
1101 | ||
1102 | count = 1; | |
1103 | last_pde = pde; | |
f8991bab | 1104 | last_shadow = shadow_addr + pt_idx * 8; |
d38ceaf9 AD |
1105 | last_pt = pt; |
1106 | } else { | |
1107 | ++count; | |
1108 | } | |
1109 | } | |
1110 | ||
f8991bab | 1111 | if (count) { |
3f3333f8 | 1112 | if (vm->root.base.bo->shadow) |
3c824172 HK |
1113 | params.func(¶ms, last_shadow, last_pt, |
1114 | count, incr, AMDGPU_PTE_VALID); | |
f8991bab | 1115 | |
3c824172 HK |
1116 | params.func(¶ms, last_pde, last_pt, |
1117 | count, incr, AMDGPU_PTE_VALID); | |
f8991bab | 1118 | } |
d38ceaf9 | 1119 | |
0a096fb6 CK |
1120 | if (!vm->use_cpu_for_update) { |
1121 | if (params.ib->length_dw == 0) { | |
1122 | amdgpu_job_free(job); | |
1123 | } else { | |
1124 | amdgpu_ring_pad_ib(ring, params.ib); | |
3f3333f8 CK |
1125 | amdgpu_sync_resv(adev, &job->sync, |
1126 | parent->base.bo->tbo.resv, | |
194d2161 | 1127 | AMDGPU_FENCE_OWNER_VM); |
0a096fb6 CK |
1128 | if (shadow) |
1129 | amdgpu_sync_resv(adev, &job->sync, | |
1130 | shadow->tbo.resv, | |
1131 | AMDGPU_FENCE_OWNER_VM); | |
1132 | ||
1133 | WARN_ON(params.ib->length_dw > ndw); | |
1134 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
1135 | AMDGPU_FENCE_OWNER_VM, &fence); | |
1136 | if (r) | |
1137 | goto error_free; | |
05906dec | 1138 | |
3f3333f8 | 1139 | amdgpu_bo_fence(parent->base.bo, fence, true); |
0a096fb6 CK |
1140 | dma_fence_put(vm->last_dir_update); |
1141 | vm->last_dir_update = dma_fence_get(fence); | |
1142 | dma_fence_put(fence); | |
1143 | } | |
194d2161 | 1144 | } |
d38ceaf9 AD |
1145 | |
1146 | return 0; | |
d5fc5e82 CZ |
1147 | |
1148 | error_free: | |
d71518b5 | 1149 | amdgpu_job_free(job); |
4af9f07c | 1150 | return r; |
d38ceaf9 AD |
1151 | } |
1152 | ||
92456b93 CK |
1153 | /* |
1154 | * amdgpu_vm_invalidate_level - mark all PD levels as invalid | |
1155 | * | |
1156 | * @parent: parent PD | |
1157 | * | |
1158 | * Mark all PD level as invalid after an error. | |
1159 | */ | |
ea09729c CK |
1160 | static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm, |
1161 | struct amdgpu_vm_pt *parent) | |
92456b93 CK |
1162 | { |
1163 | unsigned pt_idx; | |
1164 | ||
1165 | /* | |
1166 | * Recurse into the subdirectories. This recursion is harmless because | |
1167 | * we only have a maximum of 5 layers. | |
1168 | */ | |
1169 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
1170 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
1171 | ||
3f3333f8 | 1172 | if (!entry->base.bo) |
92456b93 CK |
1173 | continue; |
1174 | ||
1175 | entry->addr = ~0ULL; | |
ea09729c CK |
1176 | spin_lock(&vm->status_lock); |
1177 | list_move(&entry->base.vm_status, &vm->relocated); | |
1178 | spin_unlock(&vm->status_lock); | |
1179 | amdgpu_vm_invalidate_level(vm, entry); | |
92456b93 CK |
1180 | } |
1181 | } | |
1182 | ||
194d2161 CK |
1183 | /* |
1184 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1185 | * | |
1186 | * @adev: amdgpu_device pointer | |
1187 | * @vm: requested vm | |
1188 | * | |
1189 | * Makes sure all directories are up to date. | |
1190 | * Returns 0 for success, error for failure. | |
1191 | */ | |
1192 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1193 | struct amdgpu_vm *vm) | |
1194 | { | |
92456b93 CK |
1195 | int r; |
1196 | ||
ea09729c CK |
1197 | spin_lock(&vm->status_lock); |
1198 | while (!list_empty(&vm->relocated)) { | |
1199 | struct amdgpu_vm_bo_base *bo_base; | |
1200 | struct amdgpu_bo *bo; | |
1201 | ||
1202 | bo_base = list_first_entry(&vm->relocated, | |
1203 | struct amdgpu_vm_bo_base, | |
1204 | vm_status); | |
1205 | spin_unlock(&vm->status_lock); | |
1206 | ||
1207 | bo = bo_base->bo->parent; | |
1208 | if (bo) { | |
1209 | struct amdgpu_vm_bo_base *parent; | |
1210 | struct amdgpu_vm_pt *pt; | |
1211 | ||
1212 | parent = list_first_entry(&bo->va, | |
1213 | struct amdgpu_vm_bo_base, | |
1214 | bo_list); | |
1215 | pt = container_of(parent, struct amdgpu_vm_pt, base); | |
1216 | ||
1217 | r = amdgpu_vm_update_level(adev, vm, pt); | |
1218 | if (r) { | |
1219 | amdgpu_vm_invalidate_level(vm, &vm->root); | |
1220 | return r; | |
1221 | } | |
1222 | spin_lock(&vm->status_lock); | |
1223 | } else { | |
1224 | spin_lock(&vm->status_lock); | |
1225 | list_del_init(&bo_base->vm_status); | |
1226 | } | |
1227 | } | |
1228 | spin_unlock(&vm->status_lock); | |
92456b93 | 1229 | |
68c62306 CK |
1230 | if (vm->use_cpu_for_update) { |
1231 | /* Flush HDP */ | |
1232 | mb(); | |
1233 | amdgpu_gart_flush_gpu_tlb(adev, 0); | |
1234 | } | |
1235 | ||
92456b93 | 1236 | return r; |
194d2161 CK |
1237 | } |
1238 | ||
4e2cb640 | 1239 | /** |
cf2f0a37 | 1240 | * amdgpu_vm_find_entry - find the entry for an address |
4e2cb640 CK |
1241 | * |
1242 | * @p: see amdgpu_pte_update_params definition | |
1243 | * @addr: virtual address in question | |
cf2f0a37 AD |
1244 | * @entry: resulting entry or NULL |
1245 | * @parent: parent entry | |
4e2cb640 | 1246 | * |
cf2f0a37 | 1247 | * Find the vm_pt entry and it's parent for the given address. |
4e2cb640 | 1248 | */ |
cf2f0a37 AD |
1249 | void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, |
1250 | struct amdgpu_vm_pt **entry, | |
1251 | struct amdgpu_vm_pt **parent) | |
4e2cb640 | 1252 | { |
4e2cb640 CK |
1253 | unsigned idx, level = p->adev->vm_manager.num_level; |
1254 | ||
cf2f0a37 AD |
1255 | *parent = NULL; |
1256 | *entry = &p->vm->root; | |
1257 | while ((*entry)->entries) { | |
36b32a68 | 1258 | idx = addr >> (p->adev->vm_manager.block_size * level--); |
3f3333f8 | 1259 | idx %= amdgpu_bo_size((*entry)->base.bo) / 8; |
cf2f0a37 AD |
1260 | *parent = *entry; |
1261 | *entry = &(*entry)->entries[idx]; | |
4e2cb640 CK |
1262 | } |
1263 | ||
1264 | if (level) | |
cf2f0a37 AD |
1265 | *entry = NULL; |
1266 | } | |
1267 | ||
1268 | /** | |
1269 | * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages | |
1270 | * | |
1271 | * @p: see amdgpu_pte_update_params definition | |
1272 | * @entry: vm_pt entry to check | |
1273 | * @parent: parent entry | |
1274 | * @nptes: number of PTEs updated with this operation | |
1275 | * @dst: destination address where the PTEs should point to | |
1276 | * @flags: access flags fro the PTEs | |
1277 | * | |
1278 | * Check if we can update the PD with a huge page. | |
1279 | */ | |
ec5207c9 CK |
1280 | static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, |
1281 | struct amdgpu_vm_pt *entry, | |
1282 | struct amdgpu_vm_pt *parent, | |
1283 | unsigned nptes, uint64_t dst, | |
1284 | uint64_t flags) | |
cf2f0a37 AD |
1285 | { |
1286 | bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes); | |
1287 | uint64_t pd_addr, pde; | |
cf2f0a37 AD |
1288 | |
1289 | /* In the case of a mixed PT the PDE must point to it*/ | |
1290 | if (p->adev->asic_type < CHIP_VEGA10 || | |
1291 | nptes != AMDGPU_VM_PTE_COUNT(p->adev) || | |
38a8791a | 1292 | p->src || |
cf2f0a37 AD |
1293 | !(flags & AMDGPU_PTE_VALID)) { |
1294 | ||
3f3333f8 | 1295 | dst = amdgpu_bo_gpu_offset(entry->base.bo); |
cf2f0a37 AD |
1296 | dst = amdgpu_gart_get_vm_pde(p->adev, dst); |
1297 | flags = AMDGPU_PTE_VALID; | |
1298 | } else { | |
4ab4016a | 1299 | /* Set the huge page flag to stop scanning at this PDE */ |
cf2f0a37 AD |
1300 | flags |= AMDGPU_PDE_PTE; |
1301 | } | |
1302 | ||
4ab4016a | 1303 | if (entry->addr == (dst | flags)) |
ec5207c9 | 1304 | return; |
cf2f0a37 | 1305 | |
4ab4016a | 1306 | entry->addr = (dst | flags); |
cf2f0a37 AD |
1307 | |
1308 | if (use_cpu_update) { | |
38a8791a FK |
1309 | /* In case a huge page is replaced with a system |
1310 | * memory mapping, p->pages_addr != NULL and | |
1311 | * amdgpu_vm_cpu_set_ptes would try to translate dst | |
1312 | * through amdgpu_vm_map_gart. But dst is already a | |
1313 | * GPU address (of the page table). Disable | |
1314 | * amdgpu_vm_map_gart temporarily. | |
1315 | */ | |
1316 | dma_addr_t *tmp; | |
1317 | ||
1318 | tmp = p->pages_addr; | |
1319 | p->pages_addr = NULL; | |
1320 | ||
3f3333f8 | 1321 | pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); |
cf2f0a37 AD |
1322 | pde = pd_addr + (entry - parent->entries) * 8; |
1323 | amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags); | |
38a8791a FK |
1324 | |
1325 | p->pages_addr = tmp; | |
cf2f0a37 | 1326 | } else { |
3f3333f8 CK |
1327 | if (parent->base.bo->shadow) { |
1328 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow); | |
cf2f0a37 AD |
1329 | pde = pd_addr + (entry - parent->entries) * 8; |
1330 | amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); | |
1331 | } | |
3f3333f8 | 1332 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); |
cf2f0a37 AD |
1333 | pde = pd_addr + (entry - parent->entries) * 8; |
1334 | amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); | |
1335 | } | |
4e2cb640 CK |
1336 | } |
1337 | ||
d38ceaf9 AD |
1338 | /** |
1339 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1340 | * | |
29efc4f5 | 1341 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1342 | * @vm: requested vm |
1343 | * @start: start of GPU address range | |
1344 | * @end: end of GPU address range | |
677131a1 | 1345 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1346 | * @flags: mapping flags |
1347 | * | |
8843dbbb | 1348 | * Update the page tables in the range @start - @end. |
cc28c4ed | 1349 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 | 1350 | */ |
cc28c4ed | 1351 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1352 | uint64_t start, uint64_t end, |
6b777607 | 1353 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1354 | { |
36b32a68 ZJ |
1355 | struct amdgpu_device *adev = params->adev; |
1356 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1357 | |
301654a4 | 1358 | uint64_t addr, pe_start; |
21718497 | 1359 | struct amdgpu_bo *pt; |
301654a4 | 1360 | unsigned nptes; |
370f092f | 1361 | bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes); |
d38ceaf9 AD |
1362 | |
1363 | /* walk over the address space and update the page tables */ | |
cf2f0a37 AD |
1364 | for (addr = start; addr < end; addr += nptes, |
1365 | dst += nptes * AMDGPU_GPU_PAGE_SIZE) { | |
1366 | struct amdgpu_vm_pt *entry, *parent; | |
1367 | ||
1368 | amdgpu_vm_get_entry(params, addr, &entry, &parent); | |
1369 | if (!entry) | |
1370 | return -ENOENT; | |
4e2cb640 | 1371 | |
d38ceaf9 AD |
1372 | if ((addr & ~mask) == (end & ~mask)) |
1373 | nptes = end - addr; | |
1374 | else | |
36b32a68 | 1375 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1376 | |
ec5207c9 CK |
1377 | amdgpu_vm_handle_huge_pages(params, entry, parent, |
1378 | nptes, dst, flags); | |
4ab4016a CK |
1379 | /* We don't need to update PTEs for huge pages */ |
1380 | if (entry->addr & AMDGPU_PDE_PTE) | |
cf2f0a37 AD |
1381 | continue; |
1382 | ||
3f3333f8 | 1383 | pt = entry->base.bo; |
370f092f | 1384 | if (use_cpu_update) { |
f5e1c740 | 1385 | pe_start = (unsigned long)amdgpu_bo_kptr(pt); |
dd0792c1 CK |
1386 | } else { |
1387 | if (pt->shadow) { | |
1388 | pe_start = amdgpu_bo_gpu_offset(pt->shadow); | |
1389 | pe_start += (addr & mask) * 8; | |
1390 | params->func(params, pe_start, dst, nptes, | |
1391 | AMDGPU_GPU_PAGE_SIZE, flags); | |
1392 | } | |
370f092f | 1393 | pe_start = amdgpu_bo_gpu_offset(pt); |
dd0792c1 | 1394 | } |
d38ceaf9 | 1395 | |
301654a4 | 1396 | pe_start += (addr & mask) * 8; |
301654a4 CK |
1397 | params->func(params, pe_start, dst, nptes, |
1398 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
1399 | } |
1400 | ||
cc28c4ed | 1401 | return 0; |
92696dd5 CK |
1402 | } |
1403 | ||
1404 | /* | |
1405 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1406 | * | |
1407 | * @params: see amdgpu_pte_update_params definition | |
1408 | * @vm: requested vm | |
1409 | * @start: first PTE to handle | |
1410 | * @end: last PTE to handle | |
1411 | * @dst: addr those PTEs should point to | |
1412 | * @flags: hw mapping flags | |
cc28c4ed | 1413 | * Returns 0 for success, -EINVAL for failure. |
92696dd5 | 1414 | */ |
cc28c4ed | 1415 | static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, |
92696dd5 | 1416 | uint64_t start, uint64_t end, |
6b777607 | 1417 | uint64_t dst, uint64_t flags) |
92696dd5 | 1418 | { |
cc28c4ed HK |
1419 | int r; |
1420 | ||
92696dd5 CK |
1421 | /** |
1422 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1423 | * field in the PTE. When this field is set to a non-zero value, page | |
1424 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1425 | * flags are considered valid for all PTEs within the fragment range | |
1426 | * and corresponding mappings are assumed to be physically contiguous. | |
1427 | * | |
1428 | * The L1 TLB can store a single PTE for the whole fragment, | |
1429 | * significantly increasing the space available for translation | |
1430 | * caching. This leads to large improvements in throughput when the | |
1431 | * TLB is under pressure. | |
1432 | * | |
1433 | * The L2 TLB distributes small and large fragments into two | |
1434 | * asymmetric partitions. The large fragment cache is significantly | |
1435 | * larger. Thus, we try to use large fragments wherever possible. | |
1436 | * Userspace can support this by aligning virtual base address and | |
1437 | * allocation size to the fragment size. | |
1438 | */ | |
e618d306 | 1439 | unsigned pages_per_frag = params->adev->vm_manager.fragment_size; |
6be7adb3 CK |
1440 | uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag); |
1441 | uint64_t frag_align = 1 << pages_per_frag; | |
92696dd5 CK |
1442 | |
1443 | uint64_t frag_start = ALIGN(start, frag_align); | |
1444 | uint64_t frag_end = end & ~(frag_align - 1); | |
1445 | ||
1446 | /* system pages are non continuously */ | |
b7fc2cbd | 1447 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
cc28c4ed HK |
1448 | (frag_start >= frag_end)) |
1449 | return amdgpu_vm_update_ptes(params, start, end, dst, flags); | |
92696dd5 CK |
1450 | |
1451 | /* handle the 4K area at the beginning */ | |
1452 | if (start != frag_start) { | |
cc28c4ed HK |
1453 | r = amdgpu_vm_update_ptes(params, start, frag_start, |
1454 | dst, flags); | |
1455 | if (r) | |
1456 | return r; | |
92696dd5 CK |
1457 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; |
1458 | } | |
1459 | ||
1460 | /* handle the area in the middle */ | |
cc28c4ed HK |
1461 | r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, |
1462 | flags | frag_flags); | |
1463 | if (r) | |
1464 | return r; | |
92696dd5 CK |
1465 | |
1466 | /* handle the 4K area at the end */ | |
1467 | if (frag_end != end) { | |
1468 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
cc28c4ed | 1469 | r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); |
92696dd5 | 1470 | } |
cc28c4ed | 1471 | return r; |
d38ceaf9 AD |
1472 | } |
1473 | ||
d38ceaf9 AD |
1474 | /** |
1475 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1476 | * | |
1477 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1478 | * @exclusive: fence we need to sync to |
fa3ab3c7 | 1479 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 | 1480 | * @vm: requested vm |
a14faa65 CK |
1481 | * @start: start of mapped range |
1482 | * @last: last mapped entry | |
1483 | * @flags: flags for the entries | |
d38ceaf9 | 1484 | * @addr: addr to set the area to |
d38ceaf9 AD |
1485 | * @fence: optional resulting fence |
1486 | * | |
a14faa65 | 1487 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 1488 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
1489 | */ |
1490 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1491 | struct dma_fence *exclusive, |
fa3ab3c7 | 1492 | dma_addr_t *pages_addr, |
d38ceaf9 | 1493 | struct amdgpu_vm *vm, |
a14faa65 | 1494 | uint64_t start, uint64_t last, |
6b777607 | 1495 | uint64_t flags, uint64_t addr, |
f54d1867 | 1496 | struct dma_fence **fence) |
d38ceaf9 | 1497 | { |
2d55e45a | 1498 | struct amdgpu_ring *ring; |
a1e08d3b | 1499 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1500 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1501 | struct amdgpu_job *job; |
29efc4f5 | 1502 | struct amdgpu_pte_update_params params; |
f54d1867 | 1503 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1504 | int r; |
1505 | ||
afef8b8f CK |
1506 | memset(¶ms, 0, sizeof(params)); |
1507 | params.adev = adev; | |
49ac8a24 | 1508 | params.vm = vm; |
afef8b8f | 1509 | |
a33cab7a CK |
1510 | /* sync to everything on unmapping */ |
1511 | if (!(flags & AMDGPU_PTE_VALID)) | |
1512 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1513 | ||
b4d42511 HK |
1514 | if (vm->use_cpu_for_update) { |
1515 | /* params.src is used as flag to indicate system Memory */ | |
1516 | if (pages_addr) | |
1517 | params.src = ~0; | |
1518 | ||
1519 | /* Wait for PT BOs to be free. PTs share the same resv. object | |
1520 | * as the root PD BO | |
1521 | */ | |
a33cab7a | 1522 | r = amdgpu_vm_wait_pd(adev, vm, owner); |
b4d42511 HK |
1523 | if (unlikely(r)) |
1524 | return r; | |
1525 | ||
1526 | params.func = amdgpu_vm_cpu_set_ptes; | |
1527 | params.pages_addr = pages_addr; | |
b4d42511 HK |
1528 | return amdgpu_vm_frag_ptes(¶ms, start, last + 1, |
1529 | addr, flags); | |
1530 | } | |
1531 | ||
2d55e45a | 1532 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 1533 | |
a14faa65 | 1534 | nptes = last - start + 1; |
d38ceaf9 AD |
1535 | |
1536 | /* | |
1537 | * reserve space for one command every (1 << BLOCK_SIZE) | |
1538 | * entries or 2k dwords (whatever is smaller) | |
1539 | */ | |
36b32a68 | 1540 | ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1; |
d38ceaf9 AD |
1541 | |
1542 | /* padding, etc. */ | |
1543 | ndw = 64; | |
1544 | ||
cf2f0a37 AD |
1545 | /* one PDE write for each huge page */ |
1546 | ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6; | |
1547 | ||
570144c6 | 1548 | if (pages_addr) { |
b0456f93 CK |
1549 | /* copy commands needed */ |
1550 | ndw += ncmds * 7; | |
d38ceaf9 | 1551 | |
b0456f93 | 1552 | /* and also PTEs */ |
d38ceaf9 AD |
1553 | ndw += nptes * 2; |
1554 | ||
afef8b8f CK |
1555 | params.func = amdgpu_vm_do_copy_ptes; |
1556 | ||
d38ceaf9 AD |
1557 | } else { |
1558 | /* set page commands needed */ | |
1559 | ndw += ncmds * 10; | |
1560 | ||
1561 | /* two extra commands for begin/end of fragment */ | |
1562 | ndw += 2 * 10; | |
afef8b8f CK |
1563 | |
1564 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1565 | } |
1566 | ||
d71518b5 CK |
1567 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1568 | if (r) | |
d38ceaf9 | 1569 | return r; |
d71518b5 | 1570 | |
29efc4f5 | 1571 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1572 | |
570144c6 | 1573 | if (pages_addr) { |
b0456f93 CK |
1574 | uint64_t *pte; |
1575 | unsigned i; | |
1576 | ||
1577 | /* Put the PTEs at the end of the IB. */ | |
1578 | i = ndw - nptes * 2; | |
1579 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1580 | params.src = job->ibs->gpu_addr + i * 4; | |
1581 | ||
1582 | for (i = 0; i < nptes; ++i) { | |
1583 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1584 | AMDGPU_GPU_PAGE_SIZE); | |
1585 | pte[i] |= flags; | |
1586 | } | |
d7a4ac66 | 1587 | addr = 0; |
b0456f93 CK |
1588 | } |
1589 | ||
3cabaa54 CK |
1590 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
1591 | if (r) | |
1592 | goto error_free; | |
1593 | ||
3f3333f8 | 1594 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, |
a1e08d3b CK |
1595 | owner); |
1596 | if (r) | |
1597 | goto error_free; | |
d38ceaf9 | 1598 | |
3f3333f8 | 1599 | r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv); |
a1e08d3b CK |
1600 | if (r) |
1601 | goto error_free; | |
1602 | ||
cc28c4ed HK |
1603 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
1604 | if (r) | |
1605 | goto error_free; | |
d38ceaf9 | 1606 | |
29efc4f5 CK |
1607 | amdgpu_ring_pad_ib(ring, params.ib); |
1608 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1609 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1610 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1611 | if (r) |
1612 | goto error_free; | |
d38ceaf9 | 1613 | |
3f3333f8 | 1614 | amdgpu_bo_fence(vm->root.base.bo, f, true); |
284710fa CK |
1615 | dma_fence_put(*fence); |
1616 | *fence = f; | |
d38ceaf9 | 1617 | return 0; |
d5fc5e82 CZ |
1618 | |
1619 | error_free: | |
d71518b5 | 1620 | amdgpu_job_free(job); |
ea09729c | 1621 | amdgpu_vm_invalidate_level(vm, &vm->root); |
4af9f07c | 1622 | return r; |
d38ceaf9 AD |
1623 | } |
1624 | ||
a14faa65 CK |
1625 | /** |
1626 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1627 | * | |
1628 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1629 | * @exclusive: fence we need to sync to |
8358dcee | 1630 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1631 | * @vm: requested vm |
1632 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1633 | * @flags: HW flags for the mapping |
63e0ba40 | 1634 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1635 | * @fence: optional resulting fence |
1636 | * | |
1637 | * Split the mapping into smaller chunks so that each update fits | |
1638 | * into a SDMA IB. | |
1639 | * Returns 0 for success, -EINVAL for failure. | |
1640 | */ | |
1641 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1642 | struct dma_fence *exclusive, |
8358dcee | 1643 | dma_addr_t *pages_addr, |
a14faa65 CK |
1644 | struct amdgpu_vm *vm, |
1645 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1646 | uint64_t flags, |
63e0ba40 | 1647 | struct drm_mm_node *nodes, |
f54d1867 | 1648 | struct dma_fence **fence) |
a14faa65 | 1649 | { |
570144c6 | 1650 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1651 | int r; |
1652 | ||
1653 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1654 | * but in case of something, we filter the flags in first place | |
1655 | */ | |
1656 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1657 | flags &= ~AMDGPU_PTE_READABLE; | |
1658 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1659 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1660 | ||
15b31c59 AX |
1661 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1662 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1663 | ||
b0fd18b0 AX |
1664 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1665 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1666 | ||
d0766e98 ZJ |
1667 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1668 | (adev->asic_type >= CHIP_VEGA10)) { | |
1669 | flags |= AMDGPU_PTE_PRT; | |
1670 | flags &= ~AMDGPU_PTE_VALID; | |
1671 | } | |
1672 | ||
a14faa65 CK |
1673 | trace_amdgpu_vm_bo_update(mapping); |
1674 | ||
63e0ba40 CK |
1675 | pfn = mapping->offset >> PAGE_SHIFT; |
1676 | if (nodes) { | |
1677 | while (pfn >= nodes->size) { | |
1678 | pfn -= nodes->size; | |
1679 | ++nodes; | |
1680 | } | |
fa3ab3c7 | 1681 | } |
a14faa65 | 1682 | |
63e0ba40 CK |
1683 | do { |
1684 | uint64_t max_entries; | |
1685 | uint64_t addr, last; | |
a14faa65 | 1686 | |
63e0ba40 CK |
1687 | if (nodes) { |
1688 | addr = nodes->start << PAGE_SHIFT; | |
1689 | max_entries = (nodes->size - pfn) * | |
1690 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1691 | } else { | |
1692 | addr = 0; | |
1693 | max_entries = S64_MAX; | |
1694 | } | |
a14faa65 | 1695 | |
63e0ba40 | 1696 | if (pages_addr) { |
febb84a6 | 1697 | max_entries = min(max_entries, 16ull * 1024ull); |
63e0ba40 CK |
1698 | addr = 0; |
1699 | } else if (flags & AMDGPU_PTE_VALID) { | |
1700 | addr += adev->vm_manager.vram_base_offset; | |
1701 | } | |
1702 | addr += pfn << PAGE_SHIFT; | |
1703 | ||
a9f87f64 | 1704 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
570144c6 | 1705 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, pages_addr, vm, |
a14faa65 CK |
1706 | start, last, flags, addr, |
1707 | fence); | |
1708 | if (r) | |
1709 | return r; | |
1710 | ||
63e0ba40 CK |
1711 | pfn += last - start + 1; |
1712 | if (nodes && nodes->size == pfn) { | |
1713 | pfn = 0; | |
1714 | ++nodes; | |
1715 | } | |
a14faa65 | 1716 | start = last + 1; |
63e0ba40 | 1717 | |
a9f87f64 | 1718 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1719 | |
1720 | return 0; | |
1721 | } | |
1722 | ||
d38ceaf9 AD |
1723 | /** |
1724 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1725 | * | |
1726 | * @adev: amdgpu_device pointer | |
1727 | * @bo_va: requested BO and VM object | |
99e124f4 | 1728 | * @clear: if true clear the entries |
d38ceaf9 AD |
1729 | * |
1730 | * Fill in the page table entries for @bo_va. | |
1731 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1732 | */ |
1733 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1734 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1735 | bool clear) |
d38ceaf9 | 1736 | { |
ec681545 CK |
1737 | struct amdgpu_bo *bo = bo_va->base.bo; |
1738 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1739 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1740 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 1741 | struct ttm_mem_reg *mem; |
63e0ba40 | 1742 | struct drm_mm_node *nodes; |
f54d1867 | 1743 | struct dma_fence *exclusive; |
febb84a6 | 1744 | uint64_t flags; |
d38ceaf9 AD |
1745 | int r; |
1746 | ||
ec681545 | 1747 | if (clear || !bo_va->base.bo) { |
99e124f4 | 1748 | mem = NULL; |
63e0ba40 | 1749 | nodes = NULL; |
99e124f4 CK |
1750 | exclusive = NULL; |
1751 | } else { | |
8358dcee CK |
1752 | struct ttm_dma_tt *ttm; |
1753 | ||
ec681545 | 1754 | mem = &bo_va->base.bo->tbo.mem; |
63e0ba40 CK |
1755 | nodes = mem->mm_node; |
1756 | if (mem->mem_type == TTM_PL_TT) { | |
ec681545 CK |
1757 | ttm = container_of(bo_va->base.bo->tbo.ttm, |
1758 | struct ttm_dma_tt, ttm); | |
8358dcee | 1759 | pages_addr = ttm->dma_address; |
9ab21462 | 1760 | } |
ec681545 | 1761 | exclusive = reservation_object_get_excl(bo->tbo.resv); |
d38ceaf9 AD |
1762 | } |
1763 | ||
febb84a6 | 1764 | if (bo) |
ec681545 | 1765 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
febb84a6 | 1766 | else |
a5f6b5b1 | 1767 | flags = 0x0; |
d38ceaf9 | 1768 | |
3d7d4d3a CK |
1769 | if (!clear && bo_va->base.moved) { |
1770 | bo_va->base.moved = false; | |
7fc11959 | 1771 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1772 | |
cb7b6ec2 CK |
1773 | } else if (bo_va->cleared != clear) { |
1774 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1775 | } |
7fc11959 CK |
1776 | |
1777 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
febb84a6 | 1778 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
63e0ba40 | 1779 | mapping, flags, nodes, |
8358dcee | 1780 | &bo_va->last_pt_update); |
d38ceaf9 AD |
1781 | if (r) |
1782 | return r; | |
1783 | } | |
1784 | ||
cb7b6ec2 CK |
1785 | if (vm->use_cpu_for_update) { |
1786 | /* Flush HDP */ | |
1787 | mb(); | |
1788 | amdgpu_gart_flush_gpu_tlb(adev, 0); | |
d6c10f6b CK |
1789 | } |
1790 | ||
d38ceaf9 | 1791 | spin_lock(&vm->status_lock); |
ec681545 | 1792 | list_del_init(&bo_va->base.vm_status); |
d38ceaf9 AD |
1793 | spin_unlock(&vm->status_lock); |
1794 | ||
cb7b6ec2 CK |
1795 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1796 | bo_va->cleared = clear; | |
1797 | ||
1798 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1799 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1800 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1801 | } |
1802 | ||
d38ceaf9 AD |
1803 | return 0; |
1804 | } | |
1805 | ||
284710fa CK |
1806 | /** |
1807 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1808 | */ | |
1809 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1810 | { | |
1811 | unsigned long flags; | |
1812 | bool enable; | |
1813 | ||
1814 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1815 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
284710fa CK |
1816 | adev->gart.gart_funcs->set_prt(adev, enable); |
1817 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
1818 | } | |
1819 | ||
451bc8eb | 1820 | /** |
4388fc2a | 1821 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1822 | */ |
1823 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1824 | { | |
4388fc2a CK |
1825 | if (!adev->gart.gart_funcs->set_prt) |
1826 | return; | |
1827 | ||
451bc8eb CK |
1828 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1829 | amdgpu_vm_update_prt_state(adev); | |
1830 | } | |
1831 | ||
0b15f2fc CK |
1832 | /** |
1833 | * amdgpu_vm_prt_put - drop a PRT user | |
1834 | */ | |
1835 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1836 | { | |
451bc8eb | 1837 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1838 | amdgpu_vm_update_prt_state(adev); |
1839 | } | |
1840 | ||
284710fa | 1841 | /** |
451bc8eb | 1842 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1843 | */ |
1844 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1845 | { | |
1846 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1847 | ||
0b15f2fc | 1848 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1849 | kfree(cb); |
1850 | } | |
1851 | ||
451bc8eb CK |
1852 | /** |
1853 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1854 | */ | |
1855 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1856 | struct dma_fence *fence) | |
1857 | { | |
4388fc2a | 1858 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1859 | |
4388fc2a CK |
1860 | if (!adev->gart.gart_funcs->set_prt) |
1861 | return; | |
1862 | ||
1863 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1864 | if (!cb) { |
1865 | /* Last resort when we are OOM */ | |
1866 | if (fence) | |
1867 | dma_fence_wait(fence, false); | |
1868 | ||
486a68f5 | 1869 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1870 | } else { |
1871 | cb->adev = adev; | |
1872 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1873 | amdgpu_vm_prt_cb)) | |
1874 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1875 | } | |
1876 | } | |
1877 | ||
284710fa CK |
1878 | /** |
1879 | * amdgpu_vm_free_mapping - free a mapping | |
1880 | * | |
1881 | * @adev: amdgpu_device pointer | |
1882 | * @vm: requested vm | |
1883 | * @mapping: mapping to be freed | |
1884 | * @fence: fence of the unmap operation | |
1885 | * | |
1886 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1887 | */ | |
1888 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1889 | struct amdgpu_vm *vm, | |
1890 | struct amdgpu_bo_va_mapping *mapping, | |
1891 | struct dma_fence *fence) | |
1892 | { | |
451bc8eb CK |
1893 | if (mapping->flags & AMDGPU_PTE_PRT) |
1894 | amdgpu_vm_add_prt_cb(adev, fence); | |
1895 | kfree(mapping); | |
1896 | } | |
284710fa | 1897 | |
451bc8eb CK |
1898 | /** |
1899 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1900 | * | |
1901 | * @adev: amdgpu_device pointer | |
1902 | * @vm: requested vm | |
1903 | * | |
1904 | * Register a cleanup callback to disable PRT support after VM dies. | |
1905 | */ | |
1906 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1907 | { | |
3f3333f8 | 1908 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
451bc8eb CK |
1909 | struct dma_fence *excl, **shared; |
1910 | unsigned i, shared_count; | |
1911 | int r; | |
0b15f2fc | 1912 | |
451bc8eb CK |
1913 | r = reservation_object_get_fences_rcu(resv, &excl, |
1914 | &shared_count, &shared); | |
1915 | if (r) { | |
1916 | /* Not enough memory to grab the fence list, as last resort | |
1917 | * block for all the fences to complete. | |
1918 | */ | |
1919 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1920 | MAX_SCHEDULE_TIMEOUT); | |
1921 | return; | |
284710fa | 1922 | } |
451bc8eb CK |
1923 | |
1924 | /* Add a callback for each fence in the reservation object */ | |
1925 | amdgpu_vm_prt_get(adev); | |
1926 | amdgpu_vm_add_prt_cb(adev, excl); | |
1927 | ||
1928 | for (i = 0; i < shared_count; ++i) { | |
1929 | amdgpu_vm_prt_get(adev); | |
1930 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1931 | } | |
1932 | ||
1933 | kfree(shared); | |
284710fa CK |
1934 | } |
1935 | ||
d38ceaf9 AD |
1936 | /** |
1937 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1938 | * | |
1939 | * @adev: amdgpu_device pointer | |
1940 | * @vm: requested vm | |
f3467818 NH |
1941 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1942 | * or if an error occurred) | |
d38ceaf9 AD |
1943 | * |
1944 | * Make sure all freed BOs are cleared in the PT. | |
1945 | * Returns 0 for success. | |
1946 | * | |
1947 | * PTs have to be reserved and mutex must be locked! | |
1948 | */ | |
1949 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1950 | struct amdgpu_vm *vm, |
1951 | struct dma_fence **fence) | |
d38ceaf9 AD |
1952 | { |
1953 | struct amdgpu_bo_va_mapping *mapping; | |
f3467818 | 1954 | struct dma_fence *f = NULL; |
d38ceaf9 | 1955 | int r; |
51ac7eec | 1956 | uint64_t init_pte_value = 0; |
d38ceaf9 AD |
1957 | |
1958 | while (!list_empty(&vm->freed)) { | |
1959 | mapping = list_first_entry(&vm->freed, | |
1960 | struct amdgpu_bo_va_mapping, list); | |
1961 | list_del(&mapping->list); | |
e17841b9 | 1962 | |
51ac7eec YZ |
1963 | if (vm->pte_support_ats) |
1964 | init_pte_value = AMDGPU_PTE_SYSTEM; | |
1965 | ||
570144c6 | 1966 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, |
fc6aa33d | 1967 | mapping->start, mapping->last, |
51ac7eec | 1968 | init_pte_value, 0, &f); |
f3467818 | 1969 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1970 | if (r) { |
f3467818 | 1971 | dma_fence_put(f); |
d38ceaf9 | 1972 | return r; |
284710fa | 1973 | } |
f3467818 | 1974 | } |
d38ceaf9 | 1975 | |
f3467818 NH |
1976 | if (fence && f) { |
1977 | dma_fence_put(*fence); | |
1978 | *fence = f; | |
1979 | } else { | |
1980 | dma_fence_put(f); | |
d38ceaf9 | 1981 | } |
f3467818 | 1982 | |
d38ceaf9 AD |
1983 | return 0; |
1984 | ||
1985 | } | |
1986 | ||
1987 | /** | |
27c7b9ae | 1988 | * amdgpu_vm_clear_moved - clear moved BOs in the PT |
d38ceaf9 AD |
1989 | * |
1990 | * @adev: amdgpu_device pointer | |
1991 | * @vm: requested vm | |
1992 | * | |
27c7b9ae | 1993 | * Make sure all moved BOs are cleared in the PT. |
d38ceaf9 AD |
1994 | * Returns 0 for success. |
1995 | * | |
1996 | * PTs have to be reserved and mutex must be locked! | |
1997 | */ | |
27c7b9ae CK |
1998 | int amdgpu_vm_clear_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
1999 | struct amdgpu_sync *sync) | |
d38ceaf9 | 2000 | { |
cfe2c978 | 2001 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 2002 | int r = 0; |
d38ceaf9 AD |
2003 | |
2004 | spin_lock(&vm->status_lock); | |
27c7b9ae CK |
2005 | while (!list_empty(&vm->moved)) { |
2006 | bo_va = list_first_entry(&vm->moved, | |
ec681545 | 2007 | struct amdgpu_bo_va, base.vm_status); |
d38ceaf9 | 2008 | spin_unlock(&vm->status_lock); |
32b41ac2 | 2009 | |
99e124f4 | 2010 | r = amdgpu_vm_bo_update(adev, bo_va, true); |
d38ceaf9 AD |
2011 | if (r) |
2012 | return r; | |
2013 | ||
2014 | spin_lock(&vm->status_lock); | |
2015 | } | |
2016 | spin_unlock(&vm->status_lock); | |
2017 | ||
cfe2c978 | 2018 | if (bo_va) |
bb1e38a4 | 2019 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
2020 | |
2021 | return r; | |
d38ceaf9 AD |
2022 | } |
2023 | ||
2024 | /** | |
2025 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
2026 | * | |
2027 | * @adev: amdgpu_device pointer | |
2028 | * @vm: requested vm | |
2029 | * @bo: amdgpu buffer object | |
2030 | * | |
8843dbbb | 2031 | * Add @bo into the requested vm. |
d38ceaf9 AD |
2032 | * Add @bo to the list of bos associated with the vm |
2033 | * Returns newly added bo_va or NULL for failure | |
2034 | * | |
2035 | * Object has to be reserved! | |
2036 | */ | |
2037 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
2038 | struct amdgpu_vm *vm, | |
2039 | struct amdgpu_bo *bo) | |
2040 | { | |
2041 | struct amdgpu_bo_va *bo_va; | |
2042 | ||
2043 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2044 | if (bo_va == NULL) { | |
2045 | return NULL; | |
2046 | } | |
ec681545 CK |
2047 | bo_va->base.vm = vm; |
2048 | bo_va->base.bo = bo; | |
2049 | INIT_LIST_HEAD(&bo_va->base.bo_list); | |
2050 | INIT_LIST_HEAD(&bo_va->base.vm_status); | |
2051 | ||
d38ceaf9 | 2052 | bo_va->ref_count = 1; |
7fc11959 CK |
2053 | INIT_LIST_HEAD(&bo_va->valids); |
2054 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2055 | |
a5f6b5b1 | 2056 | if (bo) |
ec681545 | 2057 | list_add_tail(&bo_va->base.bo_list, &bo->va); |
d38ceaf9 AD |
2058 | |
2059 | return bo_va; | |
2060 | } | |
2061 | ||
2062 | /** | |
2063 | * amdgpu_vm_bo_map - map bo inside a vm | |
2064 | * | |
2065 | * @adev: amdgpu_device pointer | |
2066 | * @bo_va: bo_va to store the address | |
2067 | * @saddr: where to map the BO | |
2068 | * @offset: requested offset in the BO | |
2069 | * @flags: attributes of pages (read/write/valid/etc.) | |
2070 | * | |
2071 | * Add a mapping of the BO at the specefied addr into the VM. | |
2072 | * Returns 0 for success, error for failure. | |
2073 | * | |
49b02b18 | 2074 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2075 | */ |
2076 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2077 | struct amdgpu_bo_va *bo_va, | |
2078 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2079 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2080 | { |
a9f87f64 | 2081 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2082 | struct amdgpu_bo *bo = bo_va->base.bo; |
2083 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2084 | uint64_t eaddr; |
d38ceaf9 | 2085 | |
0be52de9 CK |
2086 | /* validate the parameters */ |
2087 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2088 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2089 | return -EINVAL; |
0be52de9 | 2090 | |
d38ceaf9 | 2091 | /* make sure object fit at this offset */ |
005ae95e | 2092 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2093 | if (saddr >= eaddr || |
ec681545 | 2094 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 2095 | return -EINVAL; |
d38ceaf9 | 2096 | |
d38ceaf9 AD |
2097 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2098 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2099 | ||
a9f87f64 CK |
2100 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2101 | if (tmp) { | |
d38ceaf9 AD |
2102 | /* bo and tmp overlap, invalid addr */ |
2103 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2104 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2105 | tmp->start, tmp->last + 1); |
663e4577 | 2106 | return -EINVAL; |
d38ceaf9 AD |
2107 | } |
2108 | ||
2109 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2110 | if (!mapping) |
2111 | return -ENOMEM; | |
d38ceaf9 AD |
2112 | |
2113 | INIT_LIST_HEAD(&mapping->list); | |
a9f87f64 CK |
2114 | mapping->start = saddr; |
2115 | mapping->last = eaddr; | |
d38ceaf9 AD |
2116 | mapping->offset = offset; |
2117 | mapping->flags = flags; | |
2118 | ||
7fc11959 | 2119 | list_add(&mapping->list, &bo_va->invalids); |
a9f87f64 | 2120 | amdgpu_vm_it_insert(mapping, &vm->va); |
80f95c57 CK |
2121 | |
2122 | if (flags & AMDGPU_PTE_PRT) | |
2123 | amdgpu_vm_prt_get(adev); | |
87f64a76 | 2124 | trace_amdgpu_vm_bo_map(bo_va, mapping); |
80f95c57 CK |
2125 | |
2126 | return 0; | |
2127 | } | |
2128 | ||
2129 | /** | |
2130 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2131 | * | |
2132 | * @adev: amdgpu_device pointer | |
2133 | * @bo_va: bo_va to store the address | |
2134 | * @saddr: where to map the BO | |
2135 | * @offset: requested offset in the BO | |
2136 | * @flags: attributes of pages (read/write/valid/etc.) | |
2137 | * | |
2138 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2139 | * mappings as we do so. | |
2140 | * Returns 0 for success, error for failure. | |
2141 | * | |
2142 | * Object has to be reserved and unreserved outside! | |
2143 | */ | |
2144 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2145 | struct amdgpu_bo_va *bo_va, | |
2146 | uint64_t saddr, uint64_t offset, | |
2147 | uint64_t size, uint64_t flags) | |
2148 | { | |
2149 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 CK |
2150 | struct amdgpu_bo *bo = bo_va->base.bo; |
2151 | struct amdgpu_vm *vm = bo_va->base.vm; | |
80f95c57 CK |
2152 | uint64_t eaddr; |
2153 | int r; | |
2154 | ||
2155 | /* validate the parameters */ | |
2156 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2157 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2158 | return -EINVAL; | |
2159 | ||
2160 | /* make sure object fit at this offset */ | |
2161 | eaddr = saddr + size - 1; | |
2162 | if (saddr >= eaddr || | |
ec681545 | 2163 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
2164 | return -EINVAL; |
2165 | ||
2166 | /* Allocate all the needed memory */ | |
2167 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2168 | if (!mapping) | |
2169 | return -ENOMEM; | |
2170 | ||
ec681545 | 2171 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2172 | if (r) { |
2173 | kfree(mapping); | |
2174 | return r; | |
2175 | } | |
2176 | ||
2177 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2178 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2179 | ||
a9f87f64 CK |
2180 | mapping->start = saddr; |
2181 | mapping->last = eaddr; | |
80f95c57 CK |
2182 | mapping->offset = offset; |
2183 | mapping->flags = flags; | |
2184 | ||
2185 | list_add(&mapping->list, &bo_va->invalids); | |
a9f87f64 | 2186 | amdgpu_vm_it_insert(mapping, &vm->va); |
d38ceaf9 | 2187 | |
4388fc2a CK |
2188 | if (flags & AMDGPU_PTE_PRT) |
2189 | amdgpu_vm_prt_get(adev); | |
87f64a76 | 2190 | trace_amdgpu_vm_bo_map(bo_va, mapping); |
4388fc2a | 2191 | |
d38ceaf9 | 2192 | return 0; |
d38ceaf9 AD |
2193 | } |
2194 | ||
2195 | /** | |
2196 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2197 | * | |
2198 | * @adev: amdgpu_device pointer | |
2199 | * @bo_va: bo_va to remove the address from | |
2200 | * @saddr: where to the BO is mapped | |
2201 | * | |
2202 | * Remove a mapping of the BO at the specefied addr from the VM. | |
2203 | * Returns 0 for success, error for failure. | |
2204 | * | |
49b02b18 | 2205 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2206 | */ |
2207 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2208 | struct amdgpu_bo_va *bo_va, | |
2209 | uint64_t saddr) | |
2210 | { | |
2211 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2212 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2213 | bool valid = true; |
d38ceaf9 | 2214 | |
6c7fc503 | 2215 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2216 | |
7fc11959 | 2217 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2218 | if (mapping->start == saddr) |
d38ceaf9 AD |
2219 | break; |
2220 | } | |
2221 | ||
7fc11959 CK |
2222 | if (&mapping->list == &bo_va->valids) { |
2223 | valid = false; | |
2224 | ||
2225 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2226 | if (mapping->start == saddr) |
7fc11959 CK |
2227 | break; |
2228 | } | |
2229 | ||
32b41ac2 | 2230 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2231 | return -ENOENT; |
d38ceaf9 | 2232 | } |
32b41ac2 | 2233 | |
d38ceaf9 | 2234 | list_del(&mapping->list); |
a9f87f64 | 2235 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2236 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2237 | |
e17841b9 | 2238 | if (valid) |
d38ceaf9 | 2239 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2240 | else |
284710fa CK |
2241 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2242 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2243 | |
2244 | return 0; | |
2245 | } | |
2246 | ||
dc54d3d1 CK |
2247 | /** |
2248 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2249 | * | |
2250 | * @adev: amdgpu_device pointer | |
2251 | * @vm: VM structure to use | |
2252 | * @saddr: start of the range | |
2253 | * @size: size of the range | |
2254 | * | |
2255 | * Remove all mappings in a range, split them as appropriate. | |
2256 | * Returns 0 for success, error for failure. | |
2257 | */ | |
2258 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2259 | struct amdgpu_vm *vm, | |
2260 | uint64_t saddr, uint64_t size) | |
2261 | { | |
2262 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2263 | LIST_HEAD(removed); |
2264 | uint64_t eaddr; | |
2265 | ||
2266 | eaddr = saddr + size - 1; | |
2267 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2268 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2269 | ||
2270 | /* Allocate all the needed memory */ | |
2271 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2272 | if (!before) | |
2273 | return -ENOMEM; | |
27f6d610 | 2274 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2275 | |
2276 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2277 | if (!after) { | |
2278 | kfree(before); | |
2279 | return -ENOMEM; | |
2280 | } | |
27f6d610 | 2281 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2282 | |
2283 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2284 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2285 | while (tmp) { | |
dc54d3d1 | 2286 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2287 | if (tmp->start < saddr) { |
2288 | before->start = tmp->start; | |
2289 | before->last = saddr - 1; | |
dc54d3d1 CK |
2290 | before->offset = tmp->offset; |
2291 | before->flags = tmp->flags; | |
2292 | list_add(&before->list, &tmp->list); | |
2293 | } | |
2294 | ||
2295 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2296 | if (tmp->last > eaddr) { |
2297 | after->start = eaddr + 1; | |
2298 | after->last = tmp->last; | |
dc54d3d1 | 2299 | after->offset = tmp->offset; |
a9f87f64 | 2300 | after->offset += after->start - tmp->start; |
dc54d3d1 CK |
2301 | after->flags = tmp->flags; |
2302 | list_add(&after->list, &tmp->list); | |
2303 | } | |
2304 | ||
2305 | list_del(&tmp->list); | |
2306 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2307 | |
2308 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2309 | } |
2310 | ||
2311 | /* And free them up */ | |
2312 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2313 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2314 | list_del(&tmp->list); |
2315 | ||
a9f87f64 CK |
2316 | if (tmp->start < saddr) |
2317 | tmp->start = saddr; | |
2318 | if (tmp->last > eaddr) | |
2319 | tmp->last = eaddr; | |
dc54d3d1 CK |
2320 | |
2321 | list_add(&tmp->list, &vm->freed); | |
2322 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2323 | } | |
2324 | ||
27f6d610 JZ |
2325 | /* Insert partial mapping before the range */ |
2326 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2327 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2328 | if (before->flags & AMDGPU_PTE_PRT) |
2329 | amdgpu_vm_prt_get(adev); | |
2330 | } else { | |
2331 | kfree(before); | |
2332 | } | |
2333 | ||
2334 | /* Insert partial mapping after the range */ | |
27f6d610 | 2335 | if (!list_empty(&after->list)) { |
a9f87f64 | 2336 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2337 | if (after->flags & AMDGPU_PTE_PRT) |
2338 | amdgpu_vm_prt_get(adev); | |
2339 | } else { | |
2340 | kfree(after); | |
2341 | } | |
2342 | ||
2343 | return 0; | |
2344 | } | |
2345 | ||
d38ceaf9 AD |
2346 | /** |
2347 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2348 | * | |
2349 | * @adev: amdgpu_device pointer | |
2350 | * @bo_va: requested bo_va | |
2351 | * | |
8843dbbb | 2352 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2353 | * |
2354 | * Object have to be reserved! | |
2355 | */ | |
2356 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2357 | struct amdgpu_bo_va *bo_va) | |
2358 | { | |
2359 | struct amdgpu_bo_va_mapping *mapping, *next; | |
ec681545 | 2360 | struct amdgpu_vm *vm = bo_va->base.vm; |
d38ceaf9 | 2361 | |
ec681545 | 2362 | list_del(&bo_va->base.bo_list); |
d38ceaf9 | 2363 | |
d38ceaf9 | 2364 | spin_lock(&vm->status_lock); |
ec681545 | 2365 | list_del(&bo_va->base.vm_status); |
d38ceaf9 AD |
2366 | spin_unlock(&vm->status_lock); |
2367 | ||
7fc11959 | 2368 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2369 | list_del(&mapping->list); |
a9f87f64 | 2370 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2371 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2372 | list_add(&mapping->list, &vm->freed); |
2373 | } | |
2374 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2375 | list_del(&mapping->list); | |
a9f87f64 | 2376 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2377 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2378 | bo_va->last_pt_update); | |
d38ceaf9 | 2379 | } |
32b41ac2 | 2380 | |
f54d1867 | 2381 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2382 | kfree(bo_va); |
d38ceaf9 AD |
2383 | } |
2384 | ||
2385 | /** | |
2386 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2387 | * | |
2388 | * @adev: amdgpu_device pointer | |
2389 | * @vm: requested vm | |
2390 | * @bo: amdgpu buffer object | |
2391 | * | |
8843dbbb | 2392 | * Mark @bo as invalid. |
d38ceaf9 AD |
2393 | */ |
2394 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2395 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2396 | { |
ec681545 CK |
2397 | struct amdgpu_vm_bo_base *bo_base; |
2398 | ||
2399 | list_for_each_entry(bo_base, &bo->va, bo_list) { | |
3f3333f8 CK |
2400 | struct amdgpu_vm *vm = bo_base->vm; |
2401 | ||
3d7d4d3a | 2402 | bo_base->moved = true; |
3f3333f8 CK |
2403 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
2404 | spin_lock(&bo_base->vm->status_lock); | |
2405 | list_move(&bo_base->vm_status, &vm->evicted); | |
2406 | spin_unlock(&bo_base->vm->status_lock); | |
2407 | continue; | |
2408 | } | |
2409 | ||
ea09729c CK |
2410 | if (bo->tbo.type == ttm_bo_type_kernel) { |
2411 | spin_lock(&bo_base->vm->status_lock); | |
2412 | if (list_empty(&bo_base->vm_status)) | |
2413 | list_add(&bo_base->vm_status, &vm->relocated); | |
2414 | spin_unlock(&bo_base->vm->status_lock); | |
3f3333f8 | 2415 | continue; |
ea09729c | 2416 | } |
3f3333f8 | 2417 | |
ec681545 | 2418 | spin_lock(&bo_base->vm->status_lock); |
cb7b6ec2 | 2419 | list_move(&bo_base->vm_status, &bo_base->vm->moved); |
ec681545 | 2420 | spin_unlock(&bo_base->vm->status_lock); |
d38ceaf9 AD |
2421 | } |
2422 | } | |
2423 | ||
bab4fee7 JZ |
2424 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2425 | { | |
2426 | /* Total bits covered by PD + PTs */ | |
2427 | unsigned bits = ilog2(vm_size) + 18; | |
2428 | ||
2429 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2430 | Above that split equal between PD and PTs */ | |
2431 | if (vm_size <= 8) | |
2432 | return (bits - 9); | |
2433 | else | |
2434 | return ((bits + 3) / 2); | |
2435 | } | |
2436 | ||
2437 | /** | |
d07f14be RH |
2438 | * amdgpu_vm_set_fragment_size - adjust fragment size in PTE |
2439 | * | |
2440 | * @adev: amdgpu_device pointer | |
2441 | * @fragment_size_default: the default fragment size if it's set auto | |
2442 | */ | |
2443 | void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, uint32_t fragment_size_default) | |
2444 | { | |
2445 | if (amdgpu_vm_fragment_size == -1) | |
2446 | adev->vm_manager.fragment_size = fragment_size_default; | |
2447 | else | |
2448 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
2449 | } | |
2450 | ||
2451 | /** | |
2452 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2453 | * |
2454 | * @adev: amdgpu_device pointer | |
2455 | * @vm_size: the default vm size if it's set auto | |
2456 | */ | |
d07f14be | 2457 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, uint32_t fragment_size_default) |
bab4fee7 JZ |
2458 | { |
2459 | /* adjust vm size firstly */ | |
2460 | if (amdgpu_vm_size == -1) | |
2461 | adev->vm_manager.vm_size = vm_size; | |
2462 | else | |
2463 | adev->vm_manager.vm_size = amdgpu_vm_size; | |
2464 | ||
2465 | /* block size depends on vm size */ | |
2466 | if (amdgpu_vm_block_size == -1) | |
2467 | adev->vm_manager.block_size = | |
2468 | amdgpu_vm_get_block_size(adev->vm_manager.vm_size); | |
2469 | else | |
2470 | adev->vm_manager.block_size = amdgpu_vm_block_size; | |
2471 | ||
d07f14be RH |
2472 | amdgpu_vm_set_fragment_size(adev, fragment_size_default); |
2473 | ||
2474 | DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n", | |
2475 | adev->vm_manager.vm_size, adev->vm_manager.block_size, | |
2476 | adev->vm_manager.fragment_size); | |
bab4fee7 JZ |
2477 | } |
2478 | ||
d38ceaf9 AD |
2479 | /** |
2480 | * amdgpu_vm_init - initialize a vm instance | |
2481 | * | |
2482 | * @adev: amdgpu_device pointer | |
2483 | * @vm: requested vm | |
9a4b7d4c | 2484 | * @vm_context: Indicates if it GFX or Compute context |
d38ceaf9 | 2485 | * |
8843dbbb | 2486 | * Init @vm fields. |
d38ceaf9 | 2487 | */ |
9a4b7d4c HK |
2488 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
2489 | int vm_context) | |
d38ceaf9 AD |
2490 | { |
2491 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
36b32a68 | 2492 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2493 | unsigned ring_instance; |
2494 | struct amdgpu_ring *ring; | |
2bd9ccfa | 2495 | struct amd_sched_rq *rq; |
36bbf3bf | 2496 | int r, i; |
3c824172 | 2497 | u64 flags; |
51ac7eec | 2498 | uint64_t init_pde_value = 0; |
d38ceaf9 | 2499 | |
d38ceaf9 | 2500 | vm->va = RB_ROOT; |
031e2983 | 2501 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
36bbf3bf CZ |
2502 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2503 | vm->reserved_vmid[i] = NULL; | |
d38ceaf9 | 2504 | spin_lock_init(&vm->status_lock); |
3f3333f8 | 2505 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2506 | INIT_LIST_HEAD(&vm->relocated); |
27c7b9ae | 2507 | INIT_LIST_HEAD(&vm->moved); |
d38ceaf9 | 2508 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2509 | |
2bd9ccfa | 2510 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2511 | |
2512 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2513 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2514 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
2515 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
2516 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
2517 | rq, amdgpu_sched_jobs); | |
2518 | if (r) | |
f566ceb1 | 2519 | return r; |
2bd9ccfa | 2520 | |
51ac7eec YZ |
2521 | vm->pte_support_ats = false; |
2522 | ||
2523 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2524 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2525 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec YZ |
2526 | |
2527 | if (adev->asic_type == CHIP_RAVEN) { | |
2528 | vm->pte_support_ats = true; | |
2529 | init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE; | |
2530 | } | |
2531 | } else | |
9a4b7d4c HK |
2532 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2533 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
2534 | DRM_DEBUG_DRIVER("VM update mode is %s\n", | |
2535 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
2536 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), | |
2537 | "CPU update of VM recommended only for large BAR system\n"); | |
a24960f3 | 2538 | vm->last_dir_update = NULL; |
05906dec | 2539 | |
3c824172 HK |
2540 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
2541 | AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
2542 | if (vm->use_cpu_for_update) | |
2543 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
2544 | else | |
2545 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
2546 | AMDGPU_GEM_CREATE_SHADOW); | |
2547 | ||
f566ceb1 | 2548 | r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, |
857d913d | 2549 | AMDGPU_GEM_DOMAIN_VRAM, |
3c824172 | 2550 | flags, |
3f3333f8 | 2551 | NULL, NULL, init_pde_value, &vm->root.base.bo); |
d38ceaf9 | 2552 | if (r) |
2bd9ccfa CK |
2553 | goto error_free_sched_entity; |
2554 | ||
3f3333f8 CK |
2555 | vm->root.base.vm = vm; |
2556 | list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va); | |
2557 | INIT_LIST_HEAD(&vm->root.base.vm_status); | |
0a096fb6 CK |
2558 | |
2559 | if (vm->use_cpu_for_update) { | |
3f3333f8 | 2560 | r = amdgpu_bo_reserve(vm->root.base.bo, false); |
0a096fb6 CK |
2561 | if (r) |
2562 | goto error_free_root; | |
0a096fb6 | 2563 | |
3f3333f8 CK |
2564 | r = amdgpu_bo_kmap(vm->root.base.bo, NULL); |
2565 | if (r) | |
2566 | goto error_free_root; | |
2567 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2568 | } | |
d38ceaf9 AD |
2569 | |
2570 | return 0; | |
2bd9ccfa | 2571 | |
67003a15 | 2572 | error_free_root: |
3f3333f8 CK |
2573 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2574 | amdgpu_bo_unref(&vm->root.base.bo); | |
2575 | vm->root.base.bo = NULL; | |
2bd9ccfa CK |
2576 | |
2577 | error_free_sched_entity: | |
2578 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
2579 | ||
2580 | return r; | |
d38ceaf9 AD |
2581 | } |
2582 | ||
f566ceb1 CK |
2583 | /** |
2584 | * amdgpu_vm_free_levels - free PD/PT levels | |
2585 | * | |
2586 | * @level: PD/PT starting level to free | |
2587 | * | |
2588 | * Free the page directory or page table level and all sub levels. | |
2589 | */ | |
2590 | static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) | |
2591 | { | |
2592 | unsigned i; | |
2593 | ||
3f3333f8 CK |
2594 | if (level->base.bo) { |
2595 | list_del(&level->base.bo_list); | |
2596 | list_del(&level->base.vm_status); | |
2597 | amdgpu_bo_unref(&level->base.bo->shadow); | |
2598 | amdgpu_bo_unref(&level->base.bo); | |
f566ceb1 CK |
2599 | } |
2600 | ||
2601 | if (level->entries) | |
2602 | for (i = 0; i <= level->last_entry_used; i++) | |
2603 | amdgpu_vm_free_levels(&level->entries[i]); | |
2604 | ||
2098105e | 2605 | kvfree(level->entries); |
f566ceb1 CK |
2606 | } |
2607 | ||
d38ceaf9 AD |
2608 | /** |
2609 | * amdgpu_vm_fini - tear down a vm instance | |
2610 | * | |
2611 | * @adev: amdgpu_device pointer | |
2612 | * @vm: requested vm | |
2613 | * | |
8843dbbb | 2614 | * Tear down @vm. |
d38ceaf9 AD |
2615 | * Unbind the VM and remove all bos from the vm bo list |
2616 | */ | |
2617 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2618 | { | |
2619 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
4388fc2a | 2620 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
36bbf3bf | 2621 | int i; |
d38ceaf9 | 2622 | |
2d55e45a | 2623 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 2624 | |
d38ceaf9 AD |
2625 | if (!RB_EMPTY_ROOT(&vm->va)) { |
2626 | dev_err(adev->dev, "still active bo inside vm\n"); | |
2627 | } | |
a9f87f64 | 2628 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) { |
d38ceaf9 | 2629 | list_del(&mapping->list); |
a9f87f64 | 2630 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2631 | kfree(mapping); |
2632 | } | |
2633 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2634 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2635 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2636 | prt_fini_needed = false; |
451bc8eb | 2637 | } |
284710fa | 2638 | |
d38ceaf9 | 2639 | list_del(&mapping->list); |
451bc8eb | 2640 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2641 | } |
2642 | ||
f566ceb1 | 2643 | amdgpu_vm_free_levels(&vm->root); |
a24960f3 | 2644 | dma_fence_put(vm->last_dir_update); |
1e9ef26f CZ |
2645 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2646 | amdgpu_vm_free_reserved_vmid(adev, vm, i); | |
d38ceaf9 | 2647 | } |
ea89f8c9 | 2648 | |
a9a78b32 CK |
2649 | /** |
2650 | * amdgpu_vm_manager_init - init the VM manager | |
2651 | * | |
2652 | * @adev: amdgpu_device pointer | |
2653 | * | |
2654 | * Initialize the VM manager structures | |
2655 | */ | |
2656 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2657 | { | |
7645670d CK |
2658 | unsigned i, j; |
2659 | ||
2660 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
2661 | struct amdgpu_vm_id_manager *id_mgr = | |
2662 | &adev->vm_manager.id_mgr[i]; | |
a9a78b32 | 2663 | |
7645670d CK |
2664 | mutex_init(&id_mgr->lock); |
2665 | INIT_LIST_HEAD(&id_mgr->ids_lru); | |
c3505770 | 2666 | atomic_set(&id_mgr->reserved_vmid_num, 0); |
a9a78b32 | 2667 | |
7645670d CK |
2668 | /* skip over VMID 0, since it is the system VM */ |
2669 | for (j = 1; j < id_mgr->num_ids; ++j) { | |
2670 | amdgpu_vm_reset_id(adev, i, j); | |
2671 | amdgpu_sync_create(&id_mgr->ids[i].active); | |
2672 | list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); | |
2673 | } | |
971fe9a9 | 2674 | } |
2d55e45a | 2675 | |
f54d1867 CW |
2676 | adev->vm_manager.fence_context = |
2677 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2678 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2679 | adev->vm_manager.seqno[i] = 0; | |
2680 | ||
2d55e45a | 2681 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 2682 | atomic64_set(&adev->vm_manager.client_counter, 0); |
284710fa | 2683 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2684 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
2685 | |
2686 | /* If not overridden by the user, by default, only in large BAR systems | |
2687 | * Compute VM tables will be updated by CPU | |
2688 | */ | |
2689 | #ifdef CONFIG_X86_64 | |
2690 | if (amdgpu_vm_update_mode == -1) { | |
2691 | if (amdgpu_vm_is_large_bar(adev)) | |
2692 | adev->vm_manager.vm_update_mode = | |
2693 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
2694 | else | |
2695 | adev->vm_manager.vm_update_mode = 0; | |
2696 | } else | |
2697 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
2698 | #else | |
2699 | adev->vm_manager.vm_update_mode = 0; | |
2700 | #endif | |
2701 | ||
a9a78b32 CK |
2702 | } |
2703 | ||
ea89f8c9 CK |
2704 | /** |
2705 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2706 | * | |
2707 | * @adev: amdgpu_device pointer | |
2708 | * | |
2709 | * Cleanup the VM manager and free resources. | |
2710 | */ | |
2711 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2712 | { | |
7645670d | 2713 | unsigned i, j; |
ea89f8c9 | 2714 | |
7645670d CK |
2715 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
2716 | struct amdgpu_vm_id_manager *id_mgr = | |
2717 | &adev->vm_manager.id_mgr[i]; | |
bcb1ba35 | 2718 | |
7645670d CK |
2719 | mutex_destroy(&id_mgr->lock); |
2720 | for (j = 0; j < AMDGPU_NUM_VM; ++j) { | |
2721 | struct amdgpu_vm_id *id = &id_mgr->ids[j]; | |
2722 | ||
2723 | amdgpu_sync_free(&id->active); | |
2724 | dma_fence_put(id->flushed_updates); | |
2725 | dma_fence_put(id->last_flush); | |
2726 | } | |
bcb1ba35 | 2727 | } |
ea89f8c9 | 2728 | } |
cfbcacf4 CZ |
2729 | |
2730 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
2731 | { | |
2732 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
2733 | struct amdgpu_device *adev = dev->dev_private; |
2734 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
2735 | int r; | |
cfbcacf4 CZ |
2736 | |
2737 | switch (args->in.op) { | |
2738 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f CZ |
2739 | /* current, we only have requirement to reserve vmid from gfxhub */ |
2740 | r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm, | |
2741 | AMDGPU_GFXHUB); | |
2742 | if (r) | |
2743 | return r; | |
2744 | break; | |
cfbcacf4 | 2745 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
1e9ef26f | 2746 | amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
2747 | break; |
2748 | default: | |
2749 | return -EINVAL; | |
2750 | } | |
2751 | ||
2752 | return 0; | |
2753 | } |