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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
02208441 | 30 | #include <linux/idr.h> |
0cf0ee98 | 31 | #include <linux/dma-buf.h> |
fdf2f6c5 | 32 | |
d38ceaf9 AD |
33 | #include <drm/amdgpu_drm.h> |
34 | #include "amdgpu.h" | |
35 | #include "amdgpu_trace.h" | |
ede0dd86 | 36 | #include "amdgpu_amdkfd.h" |
c8c5e569 | 37 | #include "amdgpu_gmc.h" |
df399b06 | 38 | #include "amdgpu_xgmi.h" |
0cf0ee98 | 39 | #include "amdgpu_dma_buf.h" |
d38ceaf9 | 40 | |
7fc48e59 AG |
41 | /** |
42 | * DOC: GPUVM | |
43 | * | |
d38ceaf9 AD |
44 | * GPUVM is similar to the legacy gart on older asics, however |
45 | * rather than there being a single global gart table | |
46 | * for the entire GPU, there are multiple VM page tables active | |
47 | * at any given time. The VM page tables can contain a mix | |
48 | * vram pages and system memory pages and system memory pages | |
49 | * can be mapped as snooped (cached system pages) or unsnooped | |
50 | * (uncached system pages). | |
51 | * Each VM has an ID associated with it and there is a page table | |
52 | * associated with each VMID. When execting a command buffer, | |
53 | * the kernel tells the the ring what VMID to use for that command | |
54 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
55 | * The userspace drivers maintain their own address space and the kernel | |
56 | * sets up their pages tables accordingly when they submit their | |
57 | * command buffers and a VMID is assigned. | |
58 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
59 | * SI supports 16. | |
60 | */ | |
61 | ||
a9f87f64 CK |
62 | #define START(node) ((node)->start) |
63 | #define LAST(node) ((node)->last) | |
64 | ||
65 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
66 | START, LAST, static, amdgpu_vm_it) | |
67 | ||
68 | #undef START | |
69 | #undef LAST | |
70 | ||
7fc48e59 AG |
71 | /** |
72 | * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback | |
73 | */ | |
284710fa | 74 | struct amdgpu_prt_cb { |
7fc48e59 AG |
75 | |
76 | /** | |
77 | * @adev: amdgpu device | |
78 | */ | |
284710fa | 79 | struct amdgpu_device *adev; |
7fc48e59 AG |
80 | |
81 | /** | |
82 | * @cb: callback | |
83 | */ | |
284710fa CK |
84 | struct dma_fence_cb cb; |
85 | }; | |
86 | ||
408d9121 | 87 | /* |
a269e449 AS |
88 | * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS |
89 | * happens while holding this lock anywhere to prevent deadlocks when | |
90 | * an MMU notifier runs in reclaim-FS context. | |
91 | */ | |
92 | static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) | |
93 | { | |
94 | mutex_lock(&vm->eviction_lock); | |
95 | vm->saved_flags = memalloc_nofs_save(); | |
96 | } | |
97 | ||
98 | static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) | |
99 | { | |
100 | if (mutex_trylock(&vm->eviction_lock)) { | |
101 | vm->saved_flags = memalloc_nofs_save(); | |
102 | return 1; | |
103 | } | |
104 | return 0; | |
105 | } | |
106 | ||
107 | static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) | |
108 | { | |
109 | memalloc_nofs_restore(vm->saved_flags); | |
110 | mutex_unlock(&vm->eviction_lock); | |
111 | } | |
112 | ||
50783147 CK |
113 | /** |
114 | * amdgpu_vm_level_shift - return the addr shift for each level | |
115 | * | |
116 | * @adev: amdgpu_device pointer | |
7fc48e59 | 117 | * @level: VMPT level |
50783147 | 118 | * |
7fc48e59 AG |
119 | * Returns: |
120 | * The number of bits the pfn needs to be right shifted for a level. | |
50783147 CK |
121 | */ |
122 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
123 | unsigned level) | |
124 | { | |
196f7489 CZ |
125 | switch (level) { |
126 | case AMDGPU_VM_PDB2: | |
127 | case AMDGPU_VM_PDB1: | |
128 | case AMDGPU_VM_PDB0: | |
55cdd4e9 | 129 | return 9 * (AMDGPU_VM_PDB0 - level) + |
50783147 | 130 | adev->vm_manager.block_size; |
196f7489 | 131 | case AMDGPU_VM_PTB: |
55cdd4e9 | 132 | return 0; |
196f7489 | 133 | default: |
55cdd4e9 | 134 | return ~0; |
196f7489 | 135 | } |
50783147 CK |
136 | } |
137 | ||
d38ceaf9 | 138 | /** |
72a7ec5c | 139 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
140 | * |
141 | * @adev: amdgpu_device pointer | |
7fc48e59 | 142 | * @level: VMPT level |
d38ceaf9 | 143 | * |
7fc48e59 AG |
144 | * Returns: |
145 | * The number of entries in a page directory or page table. | |
d38ceaf9 | 146 | */ |
72a7ec5c CK |
147 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
148 | unsigned level) | |
d38ceaf9 | 149 | { |
196f7489 CZ |
150 | unsigned shift = amdgpu_vm_level_shift(adev, |
151 | adev->vm_manager.root_level); | |
0410c5e5 | 152 | |
196f7489 | 153 | if (level == adev->vm_manager.root_level) |
72a7ec5c | 154 | /* For the root directory */ |
fc39d903 CK |
155 | return round_up(adev->vm_manager.max_pfn, 1ULL << shift) |
156 | >> shift; | |
196f7489 | 157 | else if (level != AMDGPU_VM_PTB) |
0410c5e5 CK |
158 | /* Everything in between */ |
159 | return 512; | |
160 | else | |
72a7ec5c | 161 | /* For the page tables on the leaves */ |
36b32a68 | 162 | return AMDGPU_VM_PTE_COUNT(adev); |
d38ceaf9 AD |
163 | } |
164 | ||
780637cb CK |
165 | /** |
166 | * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD | |
167 | * | |
168 | * @adev: amdgpu_device pointer | |
169 | * | |
170 | * Returns: | |
171 | * The number of entries in the root page directory which needs the ATS setting. | |
172 | */ | |
173 | static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev) | |
174 | { | |
175 | unsigned shift; | |
176 | ||
177 | shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level); | |
178 | return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT); | |
179 | } | |
180 | ||
cb90b97b CK |
181 | /** |
182 | * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT | |
183 | * | |
184 | * @adev: amdgpu_device pointer | |
185 | * @level: VMPT level | |
186 | * | |
187 | * Returns: | |
188 | * The mask to extract the entry number of a PD/PT from an address. | |
189 | */ | |
190 | static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev, | |
191 | unsigned int level) | |
192 | { | |
193 | if (level <= adev->vm_manager.root_level) | |
194 | return 0xffffffff; | |
195 | else if (level != AMDGPU_VM_PTB) | |
196 | return 0x1ff; | |
197 | else | |
198 | return AMDGPU_VM_PTE_COUNT(adev) - 1; | |
199 | } | |
200 | ||
d38ceaf9 | 201 | /** |
72a7ec5c | 202 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
203 | * |
204 | * @adev: amdgpu_device pointer | |
7fc48e59 | 205 | * @level: VMPT level |
d38ceaf9 | 206 | * |
7fc48e59 AG |
207 | * Returns: |
208 | * The size of the BO for a page directory or page table in bytes. | |
d38ceaf9 | 209 | */ |
72a7ec5c | 210 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 211 | { |
72a7ec5c | 212 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
213 | } |
214 | ||
bcdc9fd6 CK |
215 | /** |
216 | * amdgpu_vm_bo_evicted - vm_bo is evicted | |
217 | * | |
218 | * @vm_bo: vm_bo which is evicted | |
219 | * | |
220 | * State for PDs/PTs and per VM BOs which are not at the location they should | |
221 | * be. | |
222 | */ | |
223 | static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) | |
224 | { | |
225 | struct amdgpu_vm *vm = vm_bo->vm; | |
226 | struct amdgpu_bo *bo = vm_bo->bo; | |
227 | ||
228 | vm_bo->moved = true; | |
229 | if (bo->tbo.type == ttm_bo_type_kernel) | |
230 | list_move(&vm_bo->vm_status, &vm->evicted); | |
231 | else | |
232 | list_move_tail(&vm_bo->vm_status, &vm->evicted); | |
233 | } | |
bcdc9fd6 CK |
234 | /** |
235 | * amdgpu_vm_bo_moved - vm_bo is moved | |
236 | * | |
237 | * @vm_bo: vm_bo which is moved | |
238 | * | |
239 | * State for per VM BOs which are moved, but that change is not yet reflected | |
240 | * in the page tables. | |
241 | */ | |
242 | static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) | |
243 | { | |
244 | list_move(&vm_bo->vm_status, &vm_bo->vm->moved); | |
245 | } | |
246 | ||
247 | /** | |
248 | * amdgpu_vm_bo_idle - vm_bo is idle | |
249 | * | |
250 | * @vm_bo: vm_bo which is now idle | |
251 | * | |
252 | * State for PDs/PTs and per VM BOs which have gone through the state machine | |
253 | * and are now idle. | |
254 | */ | |
255 | static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) | |
256 | { | |
257 | list_move(&vm_bo->vm_status, &vm_bo->vm->idle); | |
258 | vm_bo->moved = false; | |
259 | } | |
260 | ||
261 | /** | |
262 | * amdgpu_vm_bo_invalidated - vm_bo is invalidated | |
263 | * | |
264 | * @vm_bo: vm_bo which is now invalidated | |
265 | * | |
266 | * State for normal BOs which are invalidated and that change not yet reflected | |
267 | * in the PTs. | |
268 | */ | |
269 | static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) | |
270 | { | |
271 | spin_lock(&vm_bo->vm->invalidated_lock); | |
272 | list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated); | |
273 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
274 | } | |
275 | ||
a6605c43 | 276 | /** |
277 | * amdgpu_vm_bo_relocated - vm_bo is reloacted | |
278 | * | |
279 | * @vm_bo: vm_bo which is relocated | |
280 | * | |
281 | * State for PDs/PTs which needs to update their parent PD. | |
282 | * For the root PD, just move to idle state. | |
283 | */ | |
284 | static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) | |
285 | { | |
286 | if (vm_bo->bo->parent) | |
287 | list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); | |
288 | else | |
289 | amdgpu_vm_bo_idle(vm_bo); | |
290 | } | |
291 | ||
bcdc9fd6 CK |
292 | /** |
293 | * amdgpu_vm_bo_done - vm_bo is done | |
294 | * | |
295 | * @vm_bo: vm_bo which is now done | |
296 | * | |
297 | * State for normal BOs which are invalidated and that change has been updated | |
298 | * in the PTs. | |
299 | */ | |
300 | static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) | |
301 | { | |
302 | spin_lock(&vm_bo->vm->invalidated_lock); | |
0e601a04 | 303 | list_move(&vm_bo->vm_status, &vm_bo->vm->done); |
bcdc9fd6 CK |
304 | spin_unlock(&vm_bo->vm->invalidated_lock); |
305 | } | |
306 | ||
c460f8a6 CK |
307 | /** |
308 | * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm | |
309 | * | |
310 | * @base: base structure for tracking BO usage in a VM | |
311 | * @vm: vm to which bo is to be added | |
312 | * @bo: amdgpu buffer object | |
313 | * | |
314 | * Initialize a bo_va_base structure and add it to the appropriate lists | |
315 | * | |
316 | */ | |
317 | static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, | |
318 | struct amdgpu_vm *vm, | |
319 | struct amdgpu_bo *bo) | |
320 | { | |
321 | base->vm = vm; | |
322 | base->bo = bo; | |
646b9025 | 323 | base->next = NULL; |
c460f8a6 CK |
324 | INIT_LIST_HEAD(&base->vm_status); |
325 | ||
326 | if (!bo) | |
327 | return; | |
646b9025 CK |
328 | base->next = bo->vm_bo; |
329 | bo->vm_bo = base; | |
c460f8a6 | 330 | |
5a5011a7 | 331 | if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) |
c460f8a6 CK |
332 | return; |
333 | ||
334 | vm->bulk_moveable = false; | |
fda43ab6 | 335 | if (bo->tbo.type == ttm_bo_type_kernel && bo->parent) |
bcdc9fd6 | 336 | amdgpu_vm_bo_relocated(base); |
c460f8a6 | 337 | else |
bcdc9fd6 | 338 | amdgpu_vm_bo_idle(base); |
c460f8a6 CK |
339 | |
340 | if (bo->preferred_domains & | |
341 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)) | |
342 | return; | |
343 | ||
344 | /* | |
345 | * we checked all the prerequisites, but it looks like this per vm bo | |
346 | * is currently evicted. add the bo to the evicted list to make sure it | |
347 | * is validated on next vm use to avoid fault. | |
348 | * */ | |
bcdc9fd6 | 349 | amdgpu_vm_bo_evicted(base); |
c460f8a6 CK |
350 | } |
351 | ||
ba79fde4 CK |
352 | /** |
353 | * amdgpu_vm_pt_parent - get the parent page directory | |
354 | * | |
355 | * @pt: child page table | |
356 | * | |
357 | * Helper to get the parent entry for the child page table. NULL if we are at | |
358 | * the root page directory. | |
359 | */ | |
360 | static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt) | |
361 | { | |
362 | struct amdgpu_bo *parent = pt->base.bo->parent; | |
363 | ||
364 | if (!parent) | |
365 | return NULL; | |
366 | ||
646b9025 | 367 | return container_of(parent->vm_bo, struct amdgpu_vm_pt, base); |
ba79fde4 CK |
368 | } |
369 | ||
1d614ded | 370 | /* |
73633e32 CK |
371 | * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt |
372 | */ | |
373 | struct amdgpu_vm_pt_cursor { | |
374 | uint64_t pfn; | |
375 | struct amdgpu_vm_pt *parent; | |
376 | struct amdgpu_vm_pt *entry; | |
377 | unsigned level; | |
378 | }; | |
379 | ||
380 | /** | |
381 | * amdgpu_vm_pt_start - start PD/PT walk | |
382 | * | |
383 | * @adev: amdgpu_device pointer | |
384 | * @vm: amdgpu_vm structure | |
385 | * @start: start address of the walk | |
386 | * @cursor: state to initialize | |
387 | * | |
388 | * Initialize a amdgpu_vm_pt_cursor to start a walk. | |
389 | */ | |
390 | static void amdgpu_vm_pt_start(struct amdgpu_device *adev, | |
391 | struct amdgpu_vm *vm, uint64_t start, | |
392 | struct amdgpu_vm_pt_cursor *cursor) | |
393 | { | |
394 | cursor->pfn = start; | |
395 | cursor->parent = NULL; | |
396 | cursor->entry = &vm->root; | |
397 | cursor->level = adev->vm_manager.root_level; | |
398 | } | |
399 | ||
400 | /** | |
401 | * amdgpu_vm_pt_descendant - go to child node | |
402 | * | |
403 | * @adev: amdgpu_device pointer | |
404 | * @cursor: current state | |
405 | * | |
406 | * Walk to the child node of the current node. | |
407 | * Returns: | |
408 | * True if the walk was possible, false otherwise. | |
409 | */ | |
410 | static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev, | |
411 | struct amdgpu_vm_pt_cursor *cursor) | |
412 | { | |
cb90b97b | 413 | unsigned mask, shift, idx; |
73633e32 CK |
414 | |
415 | if (!cursor->entry->entries) | |
416 | return false; | |
417 | ||
418 | BUG_ON(!cursor->entry->base.bo); | |
cb90b97b | 419 | mask = amdgpu_vm_entries_mask(adev, cursor->level); |
73633e32 CK |
420 | shift = amdgpu_vm_level_shift(adev, cursor->level); |
421 | ||
422 | ++cursor->level; | |
cb90b97b | 423 | idx = (cursor->pfn >> shift) & mask; |
73633e32 CK |
424 | cursor->parent = cursor->entry; |
425 | cursor->entry = &cursor->entry->entries[idx]; | |
426 | return true; | |
427 | } | |
428 | ||
429 | /** | |
430 | * amdgpu_vm_pt_sibling - go to sibling node | |
431 | * | |
432 | * @adev: amdgpu_device pointer | |
433 | * @cursor: current state | |
434 | * | |
435 | * Walk to the sibling node of the current node. | |
436 | * Returns: | |
437 | * True if the walk was possible, false otherwise. | |
438 | */ | |
439 | static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev, | |
440 | struct amdgpu_vm_pt_cursor *cursor) | |
441 | { | |
442 | unsigned shift, num_entries; | |
443 | ||
444 | /* Root doesn't have a sibling */ | |
445 | if (!cursor->parent) | |
446 | return false; | |
447 | ||
448 | /* Go to our parents and see if we got a sibling */ | |
449 | shift = amdgpu_vm_level_shift(adev, cursor->level - 1); | |
450 | num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1); | |
451 | ||
452 | if (cursor->entry == &cursor->parent->entries[num_entries - 1]) | |
453 | return false; | |
454 | ||
455 | cursor->pfn += 1ULL << shift; | |
456 | cursor->pfn &= ~((1ULL << shift) - 1); | |
457 | ++cursor->entry; | |
458 | return true; | |
459 | } | |
460 | ||
461 | /** | |
462 | * amdgpu_vm_pt_ancestor - go to parent node | |
463 | * | |
464 | * @cursor: current state | |
465 | * | |
466 | * Walk to the parent node of the current node. | |
467 | * Returns: | |
468 | * True if the walk was possible, false otherwise. | |
469 | */ | |
470 | static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor) | |
471 | { | |
472 | if (!cursor->parent) | |
473 | return false; | |
474 | ||
475 | --cursor->level; | |
476 | cursor->entry = cursor->parent; | |
477 | cursor->parent = amdgpu_vm_pt_parent(cursor->parent); | |
478 | return true; | |
479 | } | |
480 | ||
481 | /** | |
482 | * amdgpu_vm_pt_next - get next PD/PT in hieratchy | |
483 | * | |
484 | * @adev: amdgpu_device pointer | |
485 | * @cursor: current state | |
486 | * | |
487 | * Walk the PD/PT tree to the next node. | |
488 | */ | |
489 | static void amdgpu_vm_pt_next(struct amdgpu_device *adev, | |
490 | struct amdgpu_vm_pt_cursor *cursor) | |
491 | { | |
492 | /* First try a newborn child */ | |
493 | if (amdgpu_vm_pt_descendant(adev, cursor)) | |
494 | return; | |
495 | ||
496 | /* If that didn't worked try to find a sibling */ | |
497 | while (!amdgpu_vm_pt_sibling(adev, cursor)) { | |
498 | /* No sibling, go to our parents and grandparents */ | |
499 | if (!amdgpu_vm_pt_ancestor(cursor)) { | |
500 | cursor->pfn = ~0ll; | |
501 | return; | |
502 | } | |
503 | } | |
504 | } | |
505 | ||
506 | /** | |
73633e32 | 507 | * amdgpu_vm_pt_first_dfs - start a deep first search |
73633e32 | 508 | * |
73633e32 | 509 | * @adev: amdgpu_device structure |
73633e32 | 510 | * @vm: amdgpu_vm structure |
1d614ded | 511 | * @start: optional cursor to start with |
73633e32 CK |
512 | * @cursor: state to initialize |
513 | * | |
73633e32 | 514 | * Starts a deep first traversal of the PD/PT tree. |
73633e32 | 515 | */ |
73633e32 CK |
516 | static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev, |
517 | struct amdgpu_vm *vm, | |
e35fb064 | 518 | struct amdgpu_vm_pt_cursor *start, |
73633e32 CK |
519 | struct amdgpu_vm_pt_cursor *cursor) |
520 | { | |
e35fb064 CK |
521 | if (start) |
522 | *cursor = *start; | |
523 | else | |
524 | amdgpu_vm_pt_start(adev, vm, 0, cursor); | |
73633e32 | 525 | while (amdgpu_vm_pt_descendant(adev, cursor)); |
73633e32 CK |
526 | } |
527 | ||
528 | /** | |
e35fb064 | 529 | * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue |
73633e32 | 530 | * |
e35fb064 CK |
531 | * @start: starting point for the search |
532 | * @entry: current entry | |
73633e32 | 533 | * |
e35fb064 CK |
534 | * Returns: |
535 | * True when the search should continue, false otherwise. | |
73633e32 | 536 | */ |
e35fb064 CK |
537 | static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start, |
538 | struct amdgpu_vm_pt *entry) | |
73633e32 | 539 | { |
e35fb064 | 540 | return entry && (!start || entry != start->entry); |
73633e32 CK |
541 | } |
542 | ||
543 | /** | |
544 | * amdgpu_vm_pt_next_dfs - get the next node for a deep first search | |
545 | * | |
546 | * @adev: amdgpu_device structure | |
547 | * @cursor: current state | |
548 | * | |
549 | * Move the cursor to the next node in a deep first search. | |
550 | */ | |
551 | static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev, | |
552 | struct amdgpu_vm_pt_cursor *cursor) | |
553 | { | |
554 | if (!cursor->entry) | |
555 | return; | |
556 | ||
557 | if (!cursor->parent) | |
558 | cursor->entry = NULL; | |
559 | else if (amdgpu_vm_pt_sibling(adev, cursor)) | |
560 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
561 | else | |
562 | amdgpu_vm_pt_ancestor(cursor); | |
563 | } | |
564 | ||
1d614ded | 565 | /* |
73633e32 CK |
566 | * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs |
567 | */ | |
e35fb064 CK |
568 | #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \ |
569 | for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \ | |
73633e32 | 570 | (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\ |
e35fb064 CK |
571 | amdgpu_vm_pt_continue_dfs((start), (entry)); \ |
572 | (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor))) | |
73633e32 | 573 | |
d38ceaf9 | 574 | /** |
56467ebf | 575 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
576 | * |
577 | * @vm: vm providing the BOs | |
3c0eea6c | 578 | * @validated: head of validation list |
56467ebf | 579 | * @entry: entry to add |
d38ceaf9 AD |
580 | * |
581 | * Add the page directory to the list of BOs to | |
56467ebf | 582 | * validate for command submission. |
d38ceaf9 | 583 | */ |
56467ebf CK |
584 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
585 | struct list_head *validated, | |
586 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 587 | { |
56467ebf | 588 | entry->priority = 0; |
e83dfe4d | 589 | entry->tv.bo = &vm->root.base.bo->tbo; |
42e5fee6 CK |
590 | /* Two for VM updates, one for TTM and one for the CS job */ |
591 | entry->tv.num_shared = 4; | |
2f568dbd | 592 | entry->user_pages = NULL; |
56467ebf CK |
593 | list_add(&entry->tv.head, validated); |
594 | } | |
d38ceaf9 | 595 | |
fc39d903 CK |
596 | /** |
597 | * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag | |
598 | * | |
599 | * @bo: BO which was removed from the LRU | |
600 | * | |
601 | * Make sure the bulk_moveable flag is updated when a BO is removed from the | |
602 | * LRU. | |
603 | */ | |
b61857b5 CZ |
604 | void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo) |
605 | { | |
606 | struct amdgpu_bo *abo; | |
607 | struct amdgpu_vm_bo_base *bo_base; | |
608 | ||
609 | if (!amdgpu_bo_is_amdgpu_bo(bo)) | |
610 | return; | |
611 | ||
4671078e | 612 | if (bo->pin_count) |
b61857b5 CZ |
613 | return; |
614 | ||
615 | abo = ttm_to_amdgpu_bo(bo); | |
616 | if (!abo->parent) | |
617 | return; | |
618 | for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) { | |
619 | struct amdgpu_vm *vm = bo_base->vm; | |
620 | ||
5a5011a7 | 621 | if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) |
b61857b5 CZ |
622 | vm->bulk_moveable = false; |
623 | } | |
624 | ||
625 | } | |
f921661b HR |
626 | /** |
627 | * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU | |
628 | * | |
629 | * @adev: amdgpu device pointer | |
630 | * @vm: vm providing the BOs | |
631 | * | |
632 | * Move all BOs to the end of LRU and remember their positions to put them | |
633 | * together. | |
634 | */ | |
635 | void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, | |
636 | struct amdgpu_vm *vm) | |
637 | { | |
f921661b HR |
638 | struct amdgpu_vm_bo_base *bo_base; |
639 | ||
640 | if (vm->bulk_moveable) { | |
97588b5b | 641 | spin_lock(&ttm_bo_glob.lru_lock); |
f921661b | 642 | ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move); |
97588b5b | 643 | spin_unlock(&ttm_bo_glob.lru_lock); |
f921661b HR |
644 | return; |
645 | } | |
646 | ||
647 | memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move)); | |
648 | ||
97588b5b | 649 | spin_lock(&ttm_bo_glob.lru_lock); |
f921661b HR |
650 | list_for_each_entry(bo_base, &vm->idle, vm_status) { |
651 | struct amdgpu_bo *bo = bo_base->bo; | |
652 | ||
653 | if (!bo->parent) | |
654 | continue; | |
655 | ||
656 | ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move); | |
657 | if (bo->shadow) | |
658 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo, | |
659 | &vm->lru_bulk_move); | |
660 | } | |
97588b5b | 661 | spin_unlock(&ttm_bo_glob.lru_lock); |
f921661b HR |
662 | |
663 | vm->bulk_moveable = true; | |
664 | } | |
665 | ||
670fecc8 | 666 | /** |
f7da30d9 | 667 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
670fecc8 | 668 | * |
5a712a87 | 669 | * @adev: amdgpu device pointer |
56467ebf | 670 | * @vm: vm providing the BOs |
670fecc8 CK |
671 | * @validate: callback to do the validation |
672 | * @param: parameter for the validation callback | |
673 | * | |
674 | * Validate the page table BOs on command submission if neccessary. | |
7fc48e59 AG |
675 | * |
676 | * Returns: | |
677 | * Validation result. | |
670fecc8 | 678 | */ |
f7da30d9 CK |
679 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
680 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
681 | void *param) | |
670fecc8 | 682 | { |
91ccdd24 | 683 | struct amdgpu_vm_bo_base *bo_base, *tmp; |
b4ff0f8a | 684 | int r; |
670fecc8 | 685 | |
39bbd331 CK |
686 | vm->bulk_moveable &= list_empty(&vm->evicted); |
687 | ||
91ccdd24 CK |
688 | list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { |
689 | struct amdgpu_bo *bo = bo_base->bo; | |
670fecc8 | 690 | |
262b9c39 CK |
691 | r = validate(param, bo); |
692 | if (r) | |
b4ff0f8a | 693 | return r; |
670fecc8 | 694 | |
af4c0f65 | 695 | if (bo->tbo.type != ttm_bo_type_kernel) { |
bcdc9fd6 | 696 | amdgpu_vm_bo_moved(bo_base); |
af4c0f65 | 697 | } else { |
ecf96b52 | 698 | vm->update_funcs->map_table(bo); |
a6605c43 | 699 | amdgpu_vm_bo_relocated(bo_base); |
af4c0f65 | 700 | } |
670fecc8 CK |
701 | } |
702 | ||
a269e449 | 703 | amdgpu_vm_eviction_lock(vm); |
b4ff0f8a | 704 | vm->evicting = false; |
a269e449 | 705 | amdgpu_vm_eviction_unlock(vm); |
b4ff0f8a CK |
706 | |
707 | return 0; | |
670fecc8 CK |
708 | } |
709 | ||
56467ebf | 710 | /** |
34d7be5d | 711 | * amdgpu_vm_ready - check VM is ready for updates |
56467ebf | 712 | * |
34d7be5d | 713 | * @vm: VM to check |
d38ceaf9 | 714 | * |
34d7be5d | 715 | * Check if all VM PDs/PTs are ready for updates |
7fc48e59 AG |
716 | * |
717 | * Returns: | |
718 | * True if eviction list is empty. | |
d38ceaf9 | 719 | */ |
3f3333f8 | 720 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
d38ceaf9 | 721 | { |
af4c0f65 | 722 | return list_empty(&vm->evicted); |
d711e139 CK |
723 | } |
724 | ||
13307f7e CK |
725 | /** |
726 | * amdgpu_vm_clear_bo - initially clear the PDs/PTs | |
727 | * | |
728 | * @adev: amdgpu_device pointer | |
7fc48e59 | 729 | * @vm: VM to clear BO from |
13307f7e | 730 | * @bo: BO to clear |
eaad0c3a | 731 | * @immediate: use an immediate update |
13307f7e CK |
732 | * |
733 | * Root PD needs to be reserved when calling this. | |
7fc48e59 AG |
734 | * |
735 | * Returns: | |
736 | * 0 on success, errno otherwise. | |
13307f7e CK |
737 | */ |
738 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
780637cb | 739 | struct amdgpu_vm *vm, |
0f6064d6 | 740 | struct amdgpu_bo *bo, |
eaad0c3a | 741 | bool immediate) |
13307f7e CK |
742 | { |
743 | struct ttm_operation_ctx ctx = { true, false }; | |
780637cb | 744 | unsigned level = adev->vm_manager.root_level; |
adc7e863 | 745 | struct amdgpu_vm_update_params params; |
780637cb | 746 | struct amdgpu_bo *ancestor = bo; |
4584312d | 747 | unsigned entries, ats_entries; |
4584312d | 748 | uint64_t addr; |
13307f7e CK |
749 | int r; |
750 | ||
780637cb CK |
751 | /* Figure out our place in the hierarchy */ |
752 | if (ancestor->parent) { | |
753 | ++level; | |
754 | while (ancestor->parent->parent) { | |
755 | ++level; | |
756 | ancestor = ancestor->parent; | |
757 | } | |
758 | } | |
759 | ||
4584312d | 760 | entries = amdgpu_bo_size(bo) / 8; |
780637cb CK |
761 | if (!vm->pte_support_ats) { |
762 | ats_entries = 0; | |
4584312d | 763 | |
780637cb CK |
764 | } else if (!bo->parent) { |
765 | ats_entries = amdgpu_vm_num_ats_entries(adev); | |
766 | ats_entries = min(ats_entries, entries); | |
767 | entries -= ats_entries; | |
4584312d | 768 | |
780637cb CK |
769 | } else { |
770 | struct amdgpu_vm_pt *pt; | |
771 | ||
772 | pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base); | |
773 | ats_entries = amdgpu_vm_num_ats_entries(adev); | |
774 | if ((pt - vm->root.entries) >= ats_entries) { | |
775 | ats_entries = 0; | |
4584312d CK |
776 | } else { |
777 | ats_entries = entries; | |
778 | entries = 0; | |
779 | } | |
13307f7e CK |
780 | } |
781 | ||
13307f7e CK |
782 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); |
783 | if (r) | |
83cd8397 | 784 | return r; |
13307f7e | 785 | |
83cd8397 CK |
786 | if (bo->shadow) { |
787 | r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement, | |
788 | &ctx); | |
789 | if (r) | |
790 | return r; | |
83cd8397 CK |
791 | } |
792 | ||
ecf96b52 | 793 | r = vm->update_funcs->map_table(bo); |
284dec43 CK |
794 | if (r) |
795 | return r; | |
796 | ||
adc7e863 CK |
797 | memset(¶ms, 0, sizeof(params)); |
798 | params.adev = adev; | |
799 | params.vm = vm; | |
eaad0c3a | 800 | params.immediate = immediate; |
adc7e863 | 801 | |
9f3cc18d | 802 | r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT); |
13307f7e | 803 | if (r) |
83cd8397 | 804 | return r; |
13307f7e | 805 | |
adc7e863 | 806 | addr = 0; |
4584312d | 807 | if (ats_entries) { |
5fa76a9d | 808 | uint64_t value = 0, flags; |
4584312d | 809 | |
5fa76a9d CK |
810 | flags = AMDGPU_PTE_DEFAULT_ATC; |
811 | if (level != AMDGPU_VM_PTB) { | |
812 | /* Handle leaf PDEs as PTEs */ | |
813 | flags |= AMDGPU_PDE_PTE; | |
814 | amdgpu_gmc_get_vm_pde(adev, level, &value, &flags); | |
815 | } | |
4584312d | 816 | |
adc7e863 | 817 | r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries, |
5fa76a9d | 818 | value, flags); |
adc7e863 CK |
819 | if (r) |
820 | return r; | |
13307f7e | 821 | |
4584312d CK |
822 | addr += ats_entries * 8; |
823 | } | |
824 | ||
e95b93ce | 825 | if (entries) { |
b6f3a51e CK |
826 | uint64_t value = 0, flags = 0; |
827 | ||
828 | if (adev->asic_type >= CHIP_VEGA10) { | |
829 | if (level != AMDGPU_VM_PTB) { | |
830 | /* Handle leaf PDEs as PTEs */ | |
831 | flags |= AMDGPU_PDE_PTE; | |
832 | amdgpu_gmc_get_vm_pde(adev, level, | |
833 | &value, &flags); | |
834 | } else { | |
835 | /* Workaround for fault priority problem on GMC9 */ | |
836 | flags = AMDGPU_PTE_EXECUTABLE; | |
837 | } | |
838 | } | |
e95b93ce | 839 | |
adc7e863 | 840 | r = vm->update_funcs->update(¶ms, bo, addr, 0, entries, |
b6f3a51e | 841 | value, flags); |
adc7e863 CK |
842 | if (r) |
843 | return r; | |
e95b93ce | 844 | } |
4584312d | 845 | |
adc7e863 | 846 | return vm->update_funcs->commit(¶ms, NULL); |
13307f7e CK |
847 | } |
848 | ||
e21eb261 CK |
849 | /** |
850 | * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation | |
851 | * | |
852 | * @adev: amdgpu_device pointer | |
853 | * @vm: requesting vm | |
63b2b5e9 | 854 | * @level: the page table level |
eaad0c3a | 855 | * @immediate: use a immediate update |
e21eb261 CK |
856 | * @bp: resulting BO allocation parameters |
857 | */ | |
858 | static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
eaad0c3a | 859 | int level, bool immediate, |
061468c4 | 860 | struct amdgpu_bo_param *bp) |
e21eb261 CK |
861 | { |
862 | memset(bp, 0, sizeof(*bp)); | |
863 | ||
864 | bp->size = amdgpu_vm_bo_size(adev, level); | |
865 | bp->byte_align = AMDGPU_GPU_PAGE_SIZE; | |
866 | bp->domain = AMDGPU_GEM_DOMAIN_VRAM; | |
284dec43 CK |
867 | bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain); |
868 | bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
869 | AMDGPU_GEM_CREATE_CPU_GTT_USWC; | |
e21eb261 CK |
870 | if (vm->use_cpu_for_update) |
871 | bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
03e9dee1 FK |
872 | else if (!vm->root.base.bo || vm->root.base.bo->shadow) |
873 | bp->flags |= AMDGPU_GEM_CREATE_SHADOW; | |
e21eb261 | 874 | bp->type = ttm_bo_type_kernel; |
eaad0c3a | 875 | bp->no_wait_gpu = immediate; |
e21eb261 | 876 | if (vm->root.base.bo) |
5a5011a7 | 877 | bp->resv = vm->root.base.bo->tbo.base.resv; |
e21eb261 CK |
878 | } |
879 | ||
663e4577 | 880 | /** |
98ae7f98 | 881 | * amdgpu_vm_alloc_pts - Allocate a specific page table |
663e4577 CK |
882 | * |
883 | * @adev: amdgpu_device pointer | |
884 | * @vm: VM to allocate page tables for | |
98ae7f98 | 885 | * @cursor: Which page table to allocate |
eaad0c3a | 886 | * @immediate: use an immediate update |
663e4577 | 887 | * |
98ae7f98 | 888 | * Make sure a specific page table or directory is allocated. |
7fc48e59 AG |
889 | * |
890 | * Returns: | |
98ae7f98 FK |
891 | * 1 if page table needed to be allocated, 0 if page table was already |
892 | * allocated, negative errno if an error occurred. | |
663e4577 | 893 | */ |
0ce15d6f CK |
894 | static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, |
895 | struct amdgpu_vm *vm, | |
0f6064d6 | 896 | struct amdgpu_vm_pt_cursor *cursor, |
eaad0c3a | 897 | bool immediate) |
663e4577 | 898 | { |
0ce15d6f CK |
899 | struct amdgpu_vm_pt *entry = cursor->entry; |
900 | struct amdgpu_bo_param bp; | |
d72a6887 | 901 | struct amdgpu_bo *pt; |
d72a6887 | 902 | int r; |
663e4577 | 903 | |
0ce15d6f CK |
904 | if (cursor->level < AMDGPU_VM_PTB && !entry->entries) { |
905 | unsigned num_entries; | |
663e4577 | 906 | |
0ce15d6f CK |
907 | num_entries = amdgpu_vm_num_entries(adev, cursor->level); |
908 | entry->entries = kvmalloc_array(num_entries, | |
909 | sizeof(*entry->entries), | |
910 | GFP_KERNEL | __GFP_ZERO); | |
911 | if (!entry->entries) | |
912 | return -ENOMEM; | |
4584312d CK |
913 | } |
914 | ||
0ce15d6f CK |
915 | if (entry->base.bo) |
916 | return 0; | |
d72a6887 | 917 | |
eaad0c3a | 918 | amdgpu_vm_bo_param(adev, vm, cursor->level, immediate, &bp); |
d72a6887 | 919 | |
0ce15d6f CK |
920 | r = amdgpu_bo_create(adev, &bp, &pt); |
921 | if (r) | |
922 | return r; | |
d72a6887 | 923 | |
0ce15d6f CK |
924 | /* Keep a reference to the root directory to avoid |
925 | * freeing them up in the wrong order. | |
926 | */ | |
927 | pt->parent = amdgpu_bo_ref(cursor->parent->base.bo); | |
928 | amdgpu_vm_bo_base_init(&entry->base, vm, pt); | |
1e293037 | 929 | |
eaad0c3a | 930 | r = amdgpu_vm_clear_bo(adev, vm, pt, immediate); |
0ce15d6f CK |
931 | if (r) |
932 | goto error_free_pt; | |
d72a6887 CK |
933 | |
934 | return 0; | |
935 | ||
936 | error_free_pt: | |
937 | amdgpu_bo_unref(&pt->shadow); | |
938 | amdgpu_bo_unref(&pt); | |
939 | return r; | |
663e4577 CK |
940 | } |
941 | ||
e35fb064 CK |
942 | /** |
943 | * amdgpu_vm_free_table - fre one PD/PT | |
944 | * | |
945 | * @entry: PDE to free | |
946 | */ | |
947 | static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry) | |
948 | { | |
949 | if (entry->base.bo) { | |
950 | entry->base.bo->vm_bo = NULL; | |
951 | list_del(&entry->base.vm_status); | |
952 | amdgpu_bo_unref(&entry->base.bo->shadow); | |
953 | amdgpu_bo_unref(&entry->base.bo); | |
954 | } | |
955 | kvfree(entry->entries); | |
956 | entry->entries = NULL; | |
957 | } | |
958 | ||
229a37f8 CK |
959 | /** |
960 | * amdgpu_vm_free_pts - free PD/PT levels | |
961 | * | |
962 | * @adev: amdgpu device structure | |
769f846e | 963 | * @vm: amdgpu vm structure |
e35fb064 | 964 | * @start: optional cursor where to start freeing PDs/PTs |
229a37f8 CK |
965 | * |
966 | * Free the page directory or page table level and all sub levels. | |
967 | */ | |
968 | static void amdgpu_vm_free_pts(struct amdgpu_device *adev, | |
e35fb064 CK |
969 | struct amdgpu_vm *vm, |
970 | struct amdgpu_vm_pt_cursor *start) | |
229a37f8 CK |
971 | { |
972 | struct amdgpu_vm_pt_cursor cursor; | |
973 | struct amdgpu_vm_pt *entry; | |
974 | ||
e35fb064 | 975 | vm->bulk_moveable = false; |
229a37f8 | 976 | |
e35fb064 CK |
977 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) |
978 | amdgpu_vm_free_table(entry); | |
229a37f8 | 979 | |
e35fb064 CK |
980 | if (start) |
981 | amdgpu_vm_free_table(start->entry); | |
229a37f8 CK |
982 | } |
983 | ||
e59c0205 AX |
984 | /** |
985 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
986 | * | |
987 | * @adev: amdgpu_device pointer | |
988 | */ | |
989 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 990 | { |
a1255107 | 991 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
992 | bool has_compute_vm_bug; |
993 | struct amdgpu_ring *ring; | |
994 | int i; | |
93dcc37d | 995 | |
e59c0205 | 996 | has_compute_vm_bug = false; |
93dcc37d | 997 | |
2990a1fc | 998 | ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); |
e59c0205 AX |
999 | if (ip_block) { |
1000 | /* Compute has a VM bug for GFX version < 7. | |
1001 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
1002 | if (ip_block->version->major <= 7) | |
1003 | has_compute_vm_bug = true; | |
1004 | else if (ip_block->version->major == 8) | |
1005 | if (adev->gfx.mec_fw_version < 673) | |
1006 | has_compute_vm_bug = true; | |
1007 | } | |
93dcc37d | 1008 | |
e59c0205 AX |
1009 | for (i = 0; i < adev->num_rings; i++) { |
1010 | ring = adev->rings[i]; | |
1011 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
1012 | /* only compute rings */ | |
1013 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 1014 | else |
e59c0205 | 1015 | ring->has_compute_vm_bug = false; |
93dcc37d | 1016 | } |
93dcc37d AD |
1017 | } |
1018 | ||
7fc48e59 AG |
1019 | /** |
1020 | * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job. | |
1021 | * | |
1022 | * @ring: ring on which the job will be submitted | |
1023 | * @job: job to submit | |
1024 | * | |
1025 | * Returns: | |
1026 | * True if sync is needed. | |
1027 | */ | |
b9bf33d5 CZ |
1028 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
1029 | struct amdgpu_job *job) | |
e60f8db5 | 1030 | { |
b9bf33d5 CZ |
1031 | struct amdgpu_device *adev = ring->adev; |
1032 | unsigned vmhub = ring->funcs->vmhub; | |
620f774f CK |
1033 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
1034 | struct amdgpu_vmid *id; | |
b9bf33d5 | 1035 | bool gds_switch_needed; |
e59c0205 | 1036 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 | 1037 | |
c4f46f22 | 1038 | if (job->vmid == 0) |
b9bf33d5 | 1039 | return false; |
c4f46f22 | 1040 | id = &id_mgr->ids[job->vmid]; |
b9bf33d5 CZ |
1041 | gds_switch_needed = ring->funcs->emit_gds_switch && ( |
1042 | id->gds_base != job->gds_base || | |
1043 | id->gds_size != job->gds_size || | |
1044 | id->gws_base != job->gws_base || | |
1045 | id->gws_size != job->gws_size || | |
1046 | id->oa_base != job->oa_base || | |
1047 | id->oa_size != job->oa_size); | |
e60f8db5 | 1048 | |
620f774f | 1049 | if (amdgpu_vmid_had_gpu_reset(adev, id)) |
b9bf33d5 | 1050 | return true; |
e60f8db5 | 1051 | |
bb37b67d | 1052 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
1053 | } |
1054 | ||
d38ceaf9 AD |
1055 | /** |
1056 | * amdgpu_vm_flush - hardware flush the vm | |
1057 | * | |
1058 | * @ring: ring to use for flush | |
00553cf8 | 1059 | * @job: related job |
7fc48e59 | 1060 | * @need_pipe_sync: is pipe sync needed |
d38ceaf9 | 1061 | * |
4ff37a83 | 1062 | * Emit a VM flush when it is necessary. |
7fc48e59 AG |
1063 | * |
1064 | * Returns: | |
1065 | * 0 on success, errno otherwise. | |
d38ceaf9 | 1066 | */ |
fc39d903 CK |
1067 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, |
1068 | bool need_pipe_sync) | |
d38ceaf9 | 1069 | { |
971fe9a9 | 1070 | struct amdgpu_device *adev = ring->adev; |
7645670d | 1071 | unsigned vmhub = ring->funcs->vmhub; |
620f774f | 1072 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
c4f46f22 | 1073 | struct amdgpu_vmid *id = &id_mgr->ids[job->vmid]; |
d564a06e | 1074 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
1075 | id->gds_base != job->gds_base || |
1076 | id->gds_size != job->gds_size || | |
1077 | id->gws_base != job->gws_base || | |
1078 | id->gws_size != job->gws_size || | |
1079 | id->oa_base != job->oa_base || | |
1080 | id->oa_size != job->oa_size); | |
de37e68a | 1081 | bool vm_flush_needed = job->vm_needs_flush; |
b3cd285f | 1082 | struct dma_fence *fence = NULL; |
17cf678a | 1083 | bool pasid_mapping_needed = false; |
c0e51931 | 1084 | unsigned patch_offset = 0; |
5e208eb6 | 1085 | bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL)); |
41d9eb2c | 1086 | int r; |
d564a06e | 1087 | |
5e208eb6 JH |
1088 | if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid) |
1089 | adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid); | |
1090 | ||
620f774f | 1091 | if (amdgpu_vmid_had_gpu_reset(adev, id)) { |
f7d015b9 CK |
1092 | gds_switch_needed = true; |
1093 | vm_flush_needed = true; | |
b3cd285f | 1094 | pasid_mapping_needed = true; |
f7d015b9 | 1095 | } |
971fe9a9 | 1096 | |
6817bf28 CK |
1097 | mutex_lock(&id_mgr->lock); |
1098 | if (id->pasid != job->pasid || !id->pasid_mapping || | |
1099 | !dma_fence_is_signaled(id->pasid_mapping)) | |
1100 | pasid_mapping_needed = true; | |
1101 | mutex_unlock(&id_mgr->lock); | |
1102 | ||
b3cd285f | 1103 | gds_switch_needed &= !!ring->funcs->emit_gds_switch; |
d8de8260 AG |
1104 | vm_flush_needed &= !!ring->funcs->emit_vm_flush && |
1105 | job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET; | |
b3cd285f CK |
1106 | pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping && |
1107 | ring->funcs->emit_wreg; | |
1108 | ||
8fdf074f | 1109 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 1110 | return 0; |
41d9eb2c | 1111 | |
c0e51931 CK |
1112 | if (ring->funcs->init_cond_exec) |
1113 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 1114 | |
8fdf074f ML |
1115 | if (need_pipe_sync) |
1116 | amdgpu_ring_emit_pipeline_sync(ring); | |
1117 | ||
b3cd285f | 1118 | if (vm_flush_needed) { |
c4f46f22 | 1119 | trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr); |
c633c00b | 1120 | amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr); |
b3cd285f CK |
1121 | } |
1122 | ||
1123 | if (pasid_mapping_needed) | |
1124 | amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); | |
e9d672b2 | 1125 | |
b3cd285f | 1126 | if (vm_flush_needed || pasid_mapping_needed) { |
d240cd9e | 1127 | r = amdgpu_fence_emit(ring, &fence, 0); |
c0e51931 CK |
1128 | if (r) |
1129 | return r; | |
b3cd285f | 1130 | } |
e9d672b2 | 1131 | |
b3cd285f | 1132 | if (vm_flush_needed) { |
7645670d | 1133 | mutex_lock(&id_mgr->lock); |
c0e51931 | 1134 | dma_fence_put(id->last_flush); |
b3cd285f CK |
1135 | id->last_flush = dma_fence_get(fence); |
1136 | id->current_gpu_reset_count = | |
1137 | atomic_read(&adev->gpu_reset_counter); | |
7645670d | 1138 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 1139 | } |
e9d672b2 | 1140 | |
b3cd285f | 1141 | if (pasid_mapping_needed) { |
6817bf28 | 1142 | mutex_lock(&id_mgr->lock); |
b3cd285f CK |
1143 | id->pasid = job->pasid; |
1144 | dma_fence_put(id->pasid_mapping); | |
1145 | id->pasid_mapping = dma_fence_get(fence); | |
6817bf28 | 1146 | mutex_unlock(&id_mgr->lock); |
b3cd285f CK |
1147 | } |
1148 | dma_fence_put(fence); | |
1149 | ||
7c4378f4 | 1150 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
1151 | id->gds_base = job->gds_base; |
1152 | id->gds_size = job->gds_size; | |
1153 | id->gws_base = job->gws_base; | |
1154 | id->gws_size = job->gws_size; | |
1155 | id->oa_base = job->oa_base; | |
1156 | id->oa_size = job->oa_size; | |
c4f46f22 | 1157 | amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base, |
c0e51931 CK |
1158 | job->gds_size, job->gws_base, |
1159 | job->gws_size, job->oa_base, | |
1160 | job->oa_size); | |
1161 | } | |
1162 | ||
1163 | if (ring->funcs->patch_cond_exec) | |
1164 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
1165 | ||
1166 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
1167 | if (ring->funcs->emit_switch_buffer) { | |
1168 | amdgpu_ring_emit_switch_buffer(ring); | |
1169 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 1170 | } |
41d9eb2c | 1171 | return 0; |
971fe9a9 CK |
1172 | } |
1173 | ||
d38ceaf9 AD |
1174 | /** |
1175 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
1176 | * | |
1177 | * @vm: requested vm | |
1178 | * @bo: requested buffer object | |
1179 | * | |
8843dbbb | 1180 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
1181 | * Search inside the @bos vm list for the requested vm |
1182 | * Returns the found bo_va or NULL if none is found | |
1183 | * | |
1184 | * Object has to be reserved! | |
7fc48e59 AG |
1185 | * |
1186 | * Returns: | |
1187 | * Found bo_va or NULL. | |
d38ceaf9 AD |
1188 | */ |
1189 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
1190 | struct amdgpu_bo *bo) | |
1191 | { | |
646b9025 | 1192 | struct amdgpu_vm_bo_base *base; |
d38ceaf9 | 1193 | |
646b9025 CK |
1194 | for (base = bo->vm_bo; base; base = base->next) { |
1195 | if (base->vm != vm) | |
1196 | continue; | |
1197 | ||
1198 | return container_of(base, struct amdgpu_bo_va, base); | |
d38ceaf9 AD |
1199 | } |
1200 | return NULL; | |
1201 | } | |
1202 | ||
d38ceaf9 | 1203 | /** |
b07c9d2a | 1204 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 1205 | * |
b07c9d2a | 1206 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
1207 | * @addr: the unmapped addr |
1208 | * | |
1209 | * Look up the physical address of the page that the pte resolves | |
7fc48e59 AG |
1210 | * to. |
1211 | * | |
1212 | * Returns: | |
1213 | * The pointer for the page table entry. | |
d38ceaf9 | 1214 | */ |
6dd09027 | 1215 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
1216 | { |
1217 | uint64_t result; | |
1218 | ||
de9ea7bd CK |
1219 | /* page table offset */ |
1220 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 1221 | |
de9ea7bd CK |
1222 | /* in case cpu page size != gpu page size*/ |
1223 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 1224 | |
b07c9d2a | 1225 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
1226 | |
1227 | return result; | |
1228 | } | |
1229 | ||
1d614ded | 1230 | /** |
6989f246 | 1231 | * amdgpu_vm_update_pde - update a single level in the hierarchy |
f8991bab | 1232 | * |
1d614ded | 1233 | * @params: parameters for the update |
f8991bab | 1234 | * @vm: requested vm |
6989f246 | 1235 | * @entry: entry to update |
f8991bab | 1236 | * |
6989f246 | 1237 | * Makes sure the requested entry in parent is up to date. |
f8991bab | 1238 | */ |
e6899d55 CK |
1239 | static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params, |
1240 | struct amdgpu_vm *vm, | |
e6899d55 | 1241 | struct amdgpu_vm_pt *entry) |
d38ceaf9 | 1242 | { |
fda43ab6 | 1243 | struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry); |
373ac645 | 1244 | struct amdgpu_bo *bo = parent->base.bo, *pbo; |
3de676d8 CK |
1245 | uint64_t pde, pt, flags; |
1246 | unsigned level; | |
d5fc5e82 | 1247 | |
373ac645 | 1248 | for (level = 0, pbo = bo->parent; pbo; ++level) |
3de676d8 CK |
1249 | pbo = pbo->parent; |
1250 | ||
196f7489 | 1251 | level += params->adev->vm_manager.root_level; |
24a8d289 | 1252 | amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags); |
373ac645 | 1253 | pde = (entry - parent->entries) * 8; |
e6899d55 | 1254 | return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags); |
d38ceaf9 AD |
1255 | } |
1256 | ||
1d614ded | 1257 | /** |
d4085ea9 | 1258 | * amdgpu_vm_invalidate_pds - mark all PDs as invalid |
92456b93 | 1259 | * |
7fc48e59 AG |
1260 | * @adev: amdgpu_device pointer |
1261 | * @vm: related vm | |
92456b93 CK |
1262 | * |
1263 | * Mark all PD level as invalid after an error. | |
1264 | */ | |
d4085ea9 CK |
1265 | static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev, |
1266 | struct amdgpu_vm *vm) | |
92456b93 | 1267 | { |
d4085ea9 CK |
1268 | struct amdgpu_vm_pt_cursor cursor; |
1269 | struct amdgpu_vm_pt *entry; | |
92456b93 | 1270 | |
e35fb064 | 1271 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry) |
d4085ea9 | 1272 | if (entry->base.bo && !entry->base.moved) |
bcdc9fd6 | 1273 | amdgpu_vm_bo_relocated(&entry->base); |
92456b93 CK |
1274 | } |
1275 | ||
1d614ded | 1276 | /** |
807e2994 | 1277 | * amdgpu_vm_update_pdes - make sure that all directories are valid |
194d2161 CK |
1278 | * |
1279 | * @adev: amdgpu_device pointer | |
1280 | * @vm: requested vm | |
eaad0c3a | 1281 | * @immediate: submit immediately to the paging queue |
194d2161 CK |
1282 | * |
1283 | * Makes sure all directories are up to date. | |
7fc48e59 AG |
1284 | * |
1285 | * Returns: | |
1286 | * 0 for success, error for failure. | |
194d2161 | 1287 | */ |
807e2994 | 1288 | int amdgpu_vm_update_pdes(struct amdgpu_device *adev, |
eaad0c3a | 1289 | struct amdgpu_vm *vm, bool immediate) |
194d2161 | 1290 | { |
d1e29462 | 1291 | struct amdgpu_vm_update_params params; |
e6899d55 | 1292 | int r; |
92456b93 | 1293 | |
6989f246 CK |
1294 | if (list_empty(&vm->relocated)) |
1295 | return 0; | |
1296 | ||
6989f246 CK |
1297 | memset(¶ms, 0, sizeof(params)); |
1298 | params.adev = adev; | |
e6899d55 | 1299 | params.vm = vm; |
eaad0c3a | 1300 | params.immediate = immediate; |
6989f246 | 1301 | |
9f3cc18d | 1302 | r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT); |
e6899d55 CK |
1303 | if (r) |
1304 | return r; | |
6989f246 | 1305 | |
ea09729c | 1306 | while (!list_empty(&vm->relocated)) { |
fda43ab6 | 1307 | struct amdgpu_vm_pt *entry; |
ea09729c | 1308 | |
ba79fde4 CK |
1309 | entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt, |
1310 | base.vm_status); | |
1311 | amdgpu_vm_bo_idle(&entry->base); | |
ea09729c | 1312 | |
fda43ab6 | 1313 | r = amdgpu_vm_update_pde(¶ms, vm, entry); |
6989f246 CK |
1314 | if (r) |
1315 | goto error; | |
68c62306 CK |
1316 | } |
1317 | ||
e6899d55 CK |
1318 | r = vm->update_funcs->commit(¶ms, &vm->last_update); |
1319 | if (r) | |
1320 | goto error; | |
6989f246 CK |
1321 | return 0; |
1322 | ||
1323 | error: | |
d4085ea9 | 1324 | amdgpu_vm_invalidate_pds(adev, vm); |
92456b93 | 1325 | return r; |
194d2161 CK |
1326 | } |
1327 | ||
1d614ded | 1328 | /* |
e95b93ce | 1329 | * amdgpu_vm_update_flags - figure out flags for PTE updates |
cf2f0a37 | 1330 | * |
dfcd99f6 | 1331 | * Make sure to set the right flags for the PTEs at the desired level. |
cf2f0a37 | 1332 | */ |
d1e29462 | 1333 | static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params, |
e95b93ce CK |
1334 | struct amdgpu_bo *bo, unsigned level, |
1335 | uint64_t pe, uint64_t addr, | |
1336 | unsigned count, uint32_t incr, | |
1337 | uint64_t flags) | |
cf2f0a37 | 1338 | |
dfcd99f6 CK |
1339 | { |
1340 | if (level != AMDGPU_VM_PTB) { | |
cf2f0a37 | 1341 | flags |= AMDGPU_PDE_PTE; |
dfcd99f6 | 1342 | amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags); |
e95b93ce CK |
1343 | |
1344 | } else if (params->adev->asic_type >= CHIP_VEGA10 && | |
1345 | !(flags & AMDGPU_PTE_VALID) && | |
1346 | !(flags & AMDGPU_PTE_PRT)) { | |
1347 | ||
1348 | /* Workaround for fault priority problem on GMC9 */ | |
1349 | flags |= AMDGPU_PTE_EXECUTABLE; | |
cf2f0a37 AD |
1350 | } |
1351 | ||
c3546695 CK |
1352 | params->vm->update_funcs->update(params, bo, pe, addr, count, incr, |
1353 | flags); | |
dfcd99f6 CK |
1354 | } |
1355 | ||
1356 | /** | |
1357 | * amdgpu_vm_fragment - get fragment for PTEs | |
1358 | * | |
d1e29462 | 1359 | * @params: see amdgpu_vm_update_params definition |
dfcd99f6 CK |
1360 | * @start: first PTE to handle |
1361 | * @end: last PTE to handle | |
1362 | * @flags: hw mapping flags | |
1363 | * @frag: resulting fragment size | |
1364 | * @frag_end: end of this fragment | |
1365 | * | |
1366 | * Returns the first possible fragment for the start and end address. | |
1367 | */ | |
d1e29462 | 1368 | static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params, |
dfcd99f6 CK |
1369 | uint64_t start, uint64_t end, uint64_t flags, |
1370 | unsigned int *frag, uint64_t *frag_end) | |
1371 | { | |
1372 | /** | |
1373 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1374 | * field in the PTE. When this field is set to a non-zero value, page | |
1375 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1376 | * flags are considered valid for all PTEs within the fragment range | |
1377 | * and corresponding mappings are assumed to be physically contiguous. | |
1378 | * | |
1379 | * The L1 TLB can store a single PTE for the whole fragment, | |
1380 | * significantly increasing the space available for translation | |
1381 | * caching. This leads to large improvements in throughput when the | |
1382 | * TLB is under pressure. | |
1383 | * | |
1384 | * The L2 TLB distributes small and large fragments into two | |
1385 | * asymmetric partitions. The large fragment cache is significantly | |
1386 | * larger. Thus, we try to use large fragments wherever possible. | |
1387 | * Userspace can support this by aligning virtual base address and | |
1388 | * allocation size to the fragment size. | |
1b1d5c43 CK |
1389 | * |
1390 | * Starting with Vega10 the fragment size only controls the L1. The L2 | |
1391 | * is now directly feed with small/huge/giant pages from the walker. | |
dfcd99f6 | 1392 | */ |
1b1d5c43 CK |
1393 | unsigned max_frag; |
1394 | ||
1395 | if (params->adev->asic_type < CHIP_VEGA10) | |
1396 | max_frag = params->adev->vm_manager.fragment_size; | |
1397 | else | |
1398 | max_frag = 31; | |
dfcd99f6 CK |
1399 | |
1400 | /* system pages are non continuously */ | |
072b7a0b | 1401 | if (params->pages_addr) { |
dfcd99f6 CK |
1402 | *frag = 0; |
1403 | *frag_end = end; | |
ec5207c9 | 1404 | return; |
3cc1d3ea | 1405 | } |
cf2f0a37 | 1406 | |
dfcd99f6 CK |
1407 | /* This intentionally wraps around if no bit is set */ |
1408 | *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1); | |
1409 | if (*frag >= max_frag) { | |
1410 | *frag = max_frag; | |
1411 | *frag_end = end & ~((1ULL << max_frag) - 1); | |
1412 | } else { | |
1413 | *frag_end = start + (1 << *frag); | |
1414 | } | |
4e2cb640 CK |
1415 | } |
1416 | ||
d38ceaf9 AD |
1417 | /** |
1418 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1419 | * | |
d1e29462 | 1420 | * @params: see amdgpu_vm_update_params definition |
d38ceaf9 AD |
1421 | * @start: start of GPU address range |
1422 | * @end: end of GPU address range | |
677131a1 | 1423 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1424 | * @flags: mapping flags |
1425 | * | |
8843dbbb | 1426 | * Update the page tables in the range @start - @end. |
7fc48e59 AG |
1427 | * |
1428 | * Returns: | |
1429 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 | 1430 | */ |
d1e29462 | 1431 | static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, |
dfcd99f6 CK |
1432 | uint64_t start, uint64_t end, |
1433 | uint64_t dst, uint64_t flags) | |
d38ceaf9 | 1434 | { |
36b32a68 | 1435 | struct amdgpu_device *adev = params->adev; |
dfa70550 | 1436 | struct amdgpu_vm_pt_cursor cursor; |
dfcd99f6 CK |
1437 | uint64_t frag_start = start, frag_end; |
1438 | unsigned int frag; | |
0ce15d6f | 1439 | int r; |
dfcd99f6 CK |
1440 | |
1441 | /* figure out the initial fragment */ | |
1442 | amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end); | |
d38ceaf9 | 1443 | |
dfcd99f6 CK |
1444 | /* walk over the address space and update the PTs */ |
1445 | amdgpu_vm_pt_start(adev, params->vm, start, &cursor); | |
1446 | while (cursor.pfn < end) { | |
cb90b97b | 1447 | unsigned shift, parent_shift, mask; |
dfcd99f6 | 1448 | uint64_t incr, entry_end, pe_start; |
0ce15d6f | 1449 | struct amdgpu_bo *pt; |
cf2f0a37 | 1450 | |
9c466bcb | 1451 | if (!params->unlocked) { |
46cf5f76 CK |
1452 | /* make sure that the page tables covering the |
1453 | * address range are actually allocated | |
1454 | */ | |
1455 | r = amdgpu_vm_alloc_pts(params->adev, params->vm, | |
eaad0c3a | 1456 | &cursor, params->immediate); |
46cf5f76 CK |
1457 | if (r) |
1458 | return r; | |
1459 | } | |
4e2cb640 | 1460 | |
dfcd99f6 CK |
1461 | shift = amdgpu_vm_level_shift(adev, cursor.level); |
1462 | parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1); | |
9c466bcb CK |
1463 | if (params->unlocked) { |
1464 | /* Unlocked updates are only allowed on the leaves */ | |
1465 | if (amdgpu_vm_pt_descendant(adev, &cursor)) | |
1466 | continue; | |
1467 | } else if (adev->asic_type < CHIP_VEGA10 && | |
1468 | (flags & AMDGPU_PTE_VALID)) { | |
dfcd99f6 CK |
1469 | /* No huge page support before GMC v9 */ |
1470 | if (cursor.level != AMDGPU_VM_PTB) { | |
1471 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1472 | return -ENOENT; | |
1473 | continue; | |
1474 | } | |
1475 | } else if (frag < shift) { | |
1476 | /* We can't use this level when the fragment size is | |
1477 | * smaller than the address shift. Go to the next | |
1478 | * child entry and try again. | |
1479 | */ | |
fe6796ac CK |
1480 | if (amdgpu_vm_pt_descendant(adev, &cursor)) |
1481 | continue; | |
55cdd4e9 | 1482 | } else if (frag >= parent_shift) { |
dfcd99f6 | 1483 | /* If the fragment size is even larger than the parent |
55cdd4e9 | 1484 | * shift we should go up one level and check it again. |
dfcd99f6 CK |
1485 | */ |
1486 | if (!amdgpu_vm_pt_ancestor(&cursor)) | |
7d28efe0 | 1487 | return -EINVAL; |
dfcd99f6 | 1488 | continue; |
6849d47c RH |
1489 | } |
1490 | ||
46cf5f76 | 1491 | pt = cursor.entry->base.bo; |
fe6796ac CK |
1492 | if (!pt) { |
1493 | /* We need all PDs and PTs for mapping something, */ | |
1494 | if (flags & AMDGPU_PTE_VALID) | |
1495 | return -ENOENT; | |
1496 | ||
1497 | /* but unmapping something can happen at a higher | |
1498 | * level. | |
1499 | */ | |
1500 | if (!amdgpu_vm_pt_ancestor(&cursor)) | |
1501 | return -EINVAL; | |
1502 | ||
1503 | pt = cursor.entry->base.bo; | |
1504 | shift = parent_shift; | |
79b1eca0 AS |
1505 | frag_end = max(frag_end, ALIGN(frag_start + 1, |
1506 | 1ULL << shift)); | |
fe6796ac | 1507 | } |
46cf5f76 | 1508 | |
dfcd99f6 | 1509 | /* Looks good so far, calculate parameters for the update */ |
9ce2b991 | 1510 | incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift; |
cb90b97b CK |
1511 | mask = amdgpu_vm_entries_mask(adev, cursor.level); |
1512 | pe_start = ((cursor.pfn >> shift) & mask) * 8; | |
bfcd6c69 | 1513 | entry_end = ((uint64_t)mask + 1) << shift; |
dfcd99f6 CK |
1514 | entry_end += cursor.pfn & ~(entry_end - 1); |
1515 | entry_end = min(entry_end, end); | |
1516 | ||
1517 | do { | |
72e71a82 | 1518 | struct amdgpu_vm *vm = params->vm; |
dfcd99f6 CK |
1519 | uint64_t upd_end = min(entry_end, frag_end); |
1520 | unsigned nptes = (upd_end - frag_start) >> shift; | |
72e71a82 | 1521 | uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag); |
dfcd99f6 | 1522 | |
fe6796ac CK |
1523 | /* This can happen when we set higher level PDs to |
1524 | * silent to stop fault floods. | |
1525 | */ | |
1526 | nptes = max(nptes, 1u); | |
72e71a82 SS |
1527 | |
1528 | trace_amdgpu_vm_update_ptes(params, frag_start, upd_end, | |
1529 | nptes, dst, incr, upd_flags, | |
1530 | vm->task_info.pid, | |
1531 | vm->immediate.fence_context); | |
e95b93ce CK |
1532 | amdgpu_vm_update_flags(params, pt, cursor.level, |
1533 | pe_start, dst, nptes, incr, | |
72e71a82 | 1534 | upd_flags); |
dfcd99f6 CK |
1535 | |
1536 | pe_start += nptes * 8; | |
72e71a82 | 1537 | dst += nptes * incr; |
dfcd99f6 CK |
1538 | |
1539 | frag_start = upd_end; | |
1540 | if (frag_start >= frag_end) { | |
1541 | /* figure out the next fragment */ | |
1542 | amdgpu_vm_fragment(params, frag_start, end, | |
1543 | flags, &frag, &frag_end); | |
1544 | if (frag < shift) | |
1545 | break; | |
1546 | } | |
1547 | } while (frag_start < entry_end); | |
92696dd5 | 1548 | |
c1a17777 | 1549 | if (amdgpu_vm_pt_descendant(adev, &cursor)) { |
8863baef AD |
1550 | /* Free all child entries. |
1551 | * Update the tables with the flags and addresses and free up subsequent | |
1552 | * tables in the case of huge pages or freed up areas. | |
1553 | * This is the maximum you can free, because all other page tables are not | |
1554 | * completely covered by the range and so potentially still in use. | |
1555 | */ | |
c1a17777 | 1556 | while (cursor.pfn < frag_start) { |
e35fb064 | 1557 | amdgpu_vm_free_pts(adev, params->vm, &cursor); |
c1a17777 CK |
1558 | amdgpu_vm_pt_next(adev, &cursor); |
1559 | } | |
1560 | ||
1561 | } else if (frag >= shift) { | |
1562 | /* or just move on to the next on the same level. */ | |
dfcd99f6 | 1563 | amdgpu_vm_pt_next(adev, &cursor); |
c1a17777 | 1564 | } |
92696dd5 | 1565 | } |
6849d47c RH |
1566 | |
1567 | return 0; | |
d38ceaf9 AD |
1568 | } |
1569 | ||
d38ceaf9 AD |
1570 | /** |
1571 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1572 | * | |
a39f2a8d CK |
1573 | * @adev: amdgpu_device pointer of the VM |
1574 | * @bo_adev: amdgpu_device pointer of the mapped BO | |
d38ceaf9 | 1575 | * @vm: requested vm |
eaad0c3a | 1576 | * @immediate: immediate submission in a page fault |
9c466bcb | 1577 | * @unlocked: unlocked invalidation during MM callback |
9f3cc18d | 1578 | * @resv: fences we need to sync to |
a14faa65 CK |
1579 | * @start: start of mapped range |
1580 | * @last: last mapped entry | |
1581 | * @flags: flags for the entries | |
a39f2a8d CK |
1582 | * @offset: offset into nodes and pages_addr |
1583 | * @nodes: array of drm_mm_nodes with the MC addresses | |
acb476f5 | 1584 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 AD |
1585 | * @fence: optional resulting fence |
1586 | * | |
a14faa65 | 1587 | * Fill in the page table entries between @start and @last. |
7fc48e59 AG |
1588 | * |
1589 | * Returns: | |
1590 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1591 | */ |
1592 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
a39f2a8d | 1593 | struct amdgpu_device *bo_adev, |
eaad0c3a | 1594 | struct amdgpu_vm *vm, bool immediate, |
9c466bcb | 1595 | bool unlocked, struct dma_resv *resv, |
a14faa65 | 1596 | uint64_t start, uint64_t last, |
a39f2a8d CK |
1597 | uint64_t flags, uint64_t offset, |
1598 | struct drm_mm_node *nodes, | |
acb476f5 | 1599 | dma_addr_t *pages_addr, |
f54d1867 | 1600 | struct dma_fence **fence) |
d38ceaf9 | 1601 | { |
d1e29462 | 1602 | struct amdgpu_vm_update_params params; |
9f3cc18d | 1603 | enum amdgpu_sync_mode sync_mode; |
a39f2a8d | 1604 | uint64_t pfn; |
d38ceaf9 AD |
1605 | int r; |
1606 | ||
afef8b8f CK |
1607 | memset(¶ms, 0, sizeof(params)); |
1608 | params.adev = adev; | |
49ac8a24 | 1609 | params.vm = vm; |
eaad0c3a | 1610 | params.immediate = immediate; |
072b7a0b | 1611 | params.pages_addr = pages_addr; |
5654b897 | 1612 | params.unlocked = unlocked; |
afef8b8f | 1613 | |
9f3cc18d CK |
1614 | /* Implicitly sync to command submissions in the same VM before |
1615 | * unmapping. Sync to moving fences before mapping. | |
1616 | */ | |
a33cab7a | 1617 | if (!(flags & AMDGPU_PTE_VALID)) |
9f3cc18d CK |
1618 | sync_mode = AMDGPU_SYNC_EQ_OWNER; |
1619 | else | |
1620 | sync_mode = AMDGPU_SYNC_EXPLICIT; | |
a33cab7a | 1621 | |
a39f2a8d CK |
1622 | pfn = offset >> PAGE_SHIFT; |
1623 | if (nodes) { | |
1624 | while (pfn >= nodes->size) { | |
1625 | pfn -= nodes->size; | |
1626 | ++nodes; | |
1627 | } | |
1628 | } | |
1629 | ||
a269e449 | 1630 | amdgpu_vm_eviction_lock(vm); |
b4ff0f8a CK |
1631 | if (vm->evicting) { |
1632 | r = -EBUSY; | |
1633 | goto error_unlock; | |
1634 | } | |
1635 | ||
9c466bcb CK |
1636 | if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) { |
1637 | struct dma_fence *tmp = dma_fence_get_stub(); | |
42e5fee6 | 1638 | |
9c466bcb CK |
1639 | amdgpu_bo_fence(vm->root.base.bo, vm->last_unlocked, true); |
1640 | swap(vm->last_unlocked, tmp); | |
1641 | dma_fence_put(tmp); | |
42e5fee6 CK |
1642 | } |
1643 | ||
9f3cc18d | 1644 | r = vm->update_funcs->prepare(¶ms, resv, sync_mode); |
d71518b5 | 1645 | if (r) |
b4ff0f8a | 1646 | goto error_unlock; |
d71518b5 | 1647 | |
63e0ba40 | 1648 | do { |
a39f2a8d | 1649 | uint64_t tmp, num_entries, addr; |
a14faa65 | 1650 | |
a14faa65 | 1651 | |
a39f2a8d | 1652 | num_entries = last - start + 1; |
63e0ba40 CK |
1653 | if (nodes) { |
1654 | addr = nodes->start << PAGE_SHIFT; | |
a39f2a8d CK |
1655 | num_entries = min((nodes->size - pfn) * |
1656 | AMDGPU_GPU_PAGES_IN_CPU_PAGE, num_entries); | |
63e0ba40 CK |
1657 | } else { |
1658 | addr = 0; | |
63e0ba40 | 1659 | } |
a14faa65 | 1660 | |
63e0ba40 | 1661 | if (pages_addr) { |
a39f2a8d | 1662 | bool contiguous = true; |
9fc8fc70 | 1663 | |
a39f2a8d CK |
1664 | if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { |
1665 | uint64_t count; | |
9fc8fc70 | 1666 | |
a39f2a8d CK |
1667 | contiguous = pages_addr[pfn + 1] == |
1668 | pages_addr[pfn] + PAGE_SIZE; | |
1669 | ||
1670 | tmp = num_entries / | |
1671 | AMDGPU_GPU_PAGES_IN_CPU_PAGE; | |
1672 | for (count = 2; count < tmp; ++count) { | |
1673 | uint64_t idx = pfn + count; | |
1674 | ||
1675 | if (contiguous != (pages_addr[idx] == | |
1676 | pages_addr[idx - 1] + PAGE_SIZE)) | |
1677 | break; | |
1678 | } | |
1679 | num_entries = count * | |
1680 | AMDGPU_GPU_PAGES_IN_CPU_PAGE; | |
9fc8fc70 CK |
1681 | } |
1682 | ||
a39f2a8d | 1683 | if (!contiguous) { |
9fc8fc70 | 1684 | addr = pfn << PAGE_SHIFT; |
a39f2a8d | 1685 | params.pages_addr = pages_addr; |
9fc8fc70 CK |
1686 | } else { |
1687 | addr = pages_addr[pfn]; | |
a39f2a8d | 1688 | params.pages_addr = NULL; |
9fc8fc70 CK |
1689 | } |
1690 | ||
31d0271d | 1691 | } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) { |
a690aa0f | 1692 | addr += bo_adev->vm_manager.vram_base_offset; |
9fc8fc70 | 1693 | addr += pfn << PAGE_SHIFT; |
63e0ba40 | 1694 | } |
63e0ba40 | 1695 | |
a39f2a8d CK |
1696 | tmp = start + num_entries; |
1697 | r = amdgpu_vm_update_ptes(¶ms, start, tmp, addr, flags); | |
a14faa65 | 1698 | if (r) |
a39f2a8d | 1699 | goto error_unlock; |
a14faa65 | 1700 | |
a39f2a8d | 1701 | pfn += num_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1702 | if (nodes && nodes->size == pfn) { |
1703 | pfn = 0; | |
1704 | ++nodes; | |
1705 | } | |
a39f2a8d | 1706 | start = tmp; |
63e0ba40 | 1707 | |
a39f2a8d | 1708 | } while (unlikely(start != last + 1)); |
a14faa65 | 1709 | |
a39f2a8d CK |
1710 | r = vm->update_funcs->commit(¶ms, fence); |
1711 | ||
1712 | error_unlock: | |
1713 | amdgpu_vm_eviction_unlock(vm); | |
1714 | return r; | |
a14faa65 CK |
1715 | } |
1716 | ||
d38ceaf9 AD |
1717 | /** |
1718 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1719 | * | |
1720 | * @adev: amdgpu_device pointer | |
1721 | * @bo_va: requested BO and VM object | |
99e124f4 | 1722 | * @clear: if true clear the entries |
d38ceaf9 AD |
1723 | * |
1724 | * Fill in the page table entries for @bo_va. | |
7fc48e59 AG |
1725 | * |
1726 | * Returns: | |
1727 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 | 1728 | */ |
fc39d903 | 1729 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, |
99e124f4 | 1730 | bool clear) |
d38ceaf9 | 1731 | { |
ec681545 CK |
1732 | struct amdgpu_bo *bo = bo_va->base.bo; |
1733 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1734 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1735 | dma_addr_t *pages_addr = NULL; |
2966141a | 1736 | struct ttm_resource *mem; |
63e0ba40 | 1737 | struct drm_mm_node *nodes; |
9f3cc18d CK |
1738 | struct dma_fence **last_update; |
1739 | struct dma_resv *resv; | |
457e0fee | 1740 | uint64_t flags; |
86f7bae5 | 1741 | struct amdgpu_device *bo_adev = adev; |
d38ceaf9 AD |
1742 | int r; |
1743 | ||
7eb80427 | 1744 | if (clear || !bo) { |
99e124f4 | 1745 | mem = NULL; |
63e0ba40 | 1746 | nodes = NULL; |
9f3cc18d | 1747 | resv = vm->root.base.bo->tbo.base.resv; |
99e124f4 | 1748 | } else { |
0cf0ee98 | 1749 | struct drm_gem_object *obj = &bo->tbo.base; |
8358dcee | 1750 | |
0cf0ee98 A |
1751 | resv = bo->tbo.base.resv; |
1752 | if (obj->import_attach && bo_va->is_xgmi) { | |
1753 | struct dma_buf *dma_buf = obj->import_attach->dmabuf; | |
1754 | struct drm_gem_object *gobj = dma_buf->priv; | |
1755 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); | |
1756 | ||
1757 | if (abo->tbo.mem.mem_type == TTM_PL_VRAM) | |
1758 | bo = gem_to_amdgpu_bo(gobj); | |
1759 | } | |
7eb80427 | 1760 | mem = &bo->tbo.mem; |
63e0ba40 | 1761 | nodes = mem->mm_node; |
e34b8fee CK |
1762 | if (mem->mem_type == TTM_PL_TT) |
1763 | pages_addr = bo->tbo.ttm->dma_address; | |
d38ceaf9 AD |
1764 | } |
1765 | ||
a690aa0f | 1766 | if (bo) { |
ec681545 | 1767 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
4cd24494 AD |
1768 | |
1769 | if (amdgpu_bo_encrypted(bo)) | |
1770 | flags |= AMDGPU_PTE_TMZ; | |
1771 | ||
a690aa0f | 1772 | bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); |
1773 | } else { | |
a5f6b5b1 | 1774 | flags = 0x0; |
a690aa0f | 1775 | } |
d38ceaf9 | 1776 | |
9f3cc18d CK |
1777 | if (clear || (bo && bo->tbo.base.resv == |
1778 | vm->root.base.bo->tbo.base.resv)) | |
4e55eb38 CK |
1779 | last_update = &vm->last_update; |
1780 | else | |
1781 | last_update = &bo_va->last_pt_update; | |
1782 | ||
3d7d4d3a CK |
1783 | if (!clear && bo_va->base.moved) { |
1784 | bo_va->base.moved = false; | |
7fc11959 | 1785 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1786 | |
cb7b6ec2 CK |
1787 | } else if (bo_va->cleared != clear) { |
1788 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1789 | } |
7fc11959 CK |
1790 | |
1791 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a39f2a8d CK |
1792 | uint64_t update_flags = flags; |
1793 | ||
1794 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1795 | * but in case of something, we filter the flags in first place | |
1796 | */ | |
1797 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1798 | update_flags &= ~AMDGPU_PTE_READABLE; | |
1799 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1800 | update_flags &= ~AMDGPU_PTE_WRITEABLE; | |
1801 | ||
1802 | /* Apply ASIC specific mapping flags */ | |
1803 | amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags); | |
1804 | ||
1805 | trace_amdgpu_vm_bo_update(mapping); | |
1806 | ||
1807 | r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false, | |
1808 | resv, mapping->start, | |
1809 | mapping->last, update_flags, | |
1810 | mapping->offset, nodes, | |
1811 | pages_addr, last_update); | |
d38ceaf9 AD |
1812 | if (r) |
1813 | return r; | |
1814 | } | |
1815 | ||
bb475839 JZ |
1816 | /* If the BO is not in its preferred location add it back to |
1817 | * the evicted list so that it gets validated again on the | |
1818 | * next command submission. | |
1819 | */ | |
5a5011a7 | 1820 | if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) { |
806f043f CK |
1821 | uint32_t mem_type = bo->tbo.mem.mem_type; |
1822 | ||
fc39d903 CK |
1823 | if (!(bo->preferred_domains & |
1824 | amdgpu_mem_type_to_domain(mem_type))) | |
bcdc9fd6 | 1825 | amdgpu_vm_bo_evicted(&bo_va->base); |
806f043f | 1826 | else |
bcdc9fd6 | 1827 | amdgpu_vm_bo_idle(&bo_va->base); |
c12a2ee5 | 1828 | } else { |
bcdc9fd6 | 1829 | amdgpu_vm_bo_done(&bo_va->base); |
806f043f | 1830 | } |
d38ceaf9 | 1831 | |
cb7b6ec2 CK |
1832 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1833 | bo_va->cleared = clear; | |
1834 | ||
1835 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1836 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1837 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1838 | } |
1839 | ||
d38ceaf9 AD |
1840 | return 0; |
1841 | } | |
1842 | ||
284710fa CK |
1843 | /** |
1844 | * amdgpu_vm_update_prt_state - update the global PRT state | |
7fc48e59 AG |
1845 | * |
1846 | * @adev: amdgpu_device pointer | |
284710fa CK |
1847 | */ |
1848 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1849 | { | |
1850 | unsigned long flags; | |
1851 | bool enable; | |
1852 | ||
1853 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1854 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
132f34e4 | 1855 | adev->gmc.gmc_funcs->set_prt(adev, enable); |
284710fa CK |
1856 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); |
1857 | } | |
1858 | ||
451bc8eb | 1859 | /** |
4388fc2a | 1860 | * amdgpu_vm_prt_get - add a PRT user |
7fc48e59 AG |
1861 | * |
1862 | * @adev: amdgpu_device pointer | |
451bc8eb CK |
1863 | */ |
1864 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1865 | { | |
132f34e4 | 1866 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1867 | return; |
1868 | ||
451bc8eb CK |
1869 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1870 | amdgpu_vm_update_prt_state(adev); | |
1871 | } | |
1872 | ||
0b15f2fc CK |
1873 | /** |
1874 | * amdgpu_vm_prt_put - drop a PRT user | |
7fc48e59 AG |
1875 | * |
1876 | * @adev: amdgpu_device pointer | |
0b15f2fc CK |
1877 | */ |
1878 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1879 | { | |
451bc8eb | 1880 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1881 | amdgpu_vm_update_prt_state(adev); |
1882 | } | |
1883 | ||
284710fa | 1884 | /** |
451bc8eb | 1885 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
7fc48e59 AG |
1886 | * |
1887 | * @fence: fence for the callback | |
00553cf8 | 1888 | * @_cb: the callback function |
284710fa CK |
1889 | */ |
1890 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1891 | { | |
1892 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1893 | ||
0b15f2fc | 1894 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1895 | kfree(cb); |
1896 | } | |
1897 | ||
451bc8eb CK |
1898 | /** |
1899 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
7fc48e59 AG |
1900 | * |
1901 | * @adev: amdgpu_device pointer | |
1902 | * @fence: fence for the callback | |
451bc8eb CK |
1903 | */ |
1904 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1905 | struct dma_fence *fence) | |
1906 | { | |
4388fc2a | 1907 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1908 | |
132f34e4 | 1909 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1910 | return; |
1911 | ||
1912 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1913 | if (!cb) { |
1914 | /* Last resort when we are OOM */ | |
1915 | if (fence) | |
1916 | dma_fence_wait(fence, false); | |
1917 | ||
486a68f5 | 1918 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1919 | } else { |
1920 | cb->adev = adev; | |
1921 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1922 | amdgpu_vm_prt_cb)) | |
1923 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1924 | } | |
1925 | } | |
1926 | ||
284710fa CK |
1927 | /** |
1928 | * amdgpu_vm_free_mapping - free a mapping | |
1929 | * | |
1930 | * @adev: amdgpu_device pointer | |
1931 | * @vm: requested vm | |
1932 | * @mapping: mapping to be freed | |
1933 | * @fence: fence of the unmap operation | |
1934 | * | |
1935 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1936 | */ | |
1937 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1938 | struct amdgpu_vm *vm, | |
1939 | struct amdgpu_bo_va_mapping *mapping, | |
1940 | struct dma_fence *fence) | |
1941 | { | |
451bc8eb CK |
1942 | if (mapping->flags & AMDGPU_PTE_PRT) |
1943 | amdgpu_vm_add_prt_cb(adev, fence); | |
1944 | kfree(mapping); | |
1945 | } | |
284710fa | 1946 | |
451bc8eb CK |
1947 | /** |
1948 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1949 | * | |
1950 | * @adev: amdgpu_device pointer | |
1951 | * @vm: requested vm | |
1952 | * | |
1953 | * Register a cleanup callback to disable PRT support after VM dies. | |
1954 | */ | |
1955 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1956 | { | |
52791eee | 1957 | struct dma_resv *resv = vm->root.base.bo->tbo.base.resv; |
451bc8eb CK |
1958 | struct dma_fence *excl, **shared; |
1959 | unsigned i, shared_count; | |
1960 | int r; | |
0b15f2fc | 1961 | |
52791eee | 1962 | r = dma_resv_get_fences_rcu(resv, &excl, |
451bc8eb CK |
1963 | &shared_count, &shared); |
1964 | if (r) { | |
1965 | /* Not enough memory to grab the fence list, as last resort | |
1966 | * block for all the fences to complete. | |
1967 | */ | |
52791eee | 1968 | dma_resv_wait_timeout_rcu(resv, true, false, |
451bc8eb CK |
1969 | MAX_SCHEDULE_TIMEOUT); |
1970 | return; | |
284710fa | 1971 | } |
451bc8eb CK |
1972 | |
1973 | /* Add a callback for each fence in the reservation object */ | |
1974 | amdgpu_vm_prt_get(adev); | |
1975 | amdgpu_vm_add_prt_cb(adev, excl); | |
1976 | ||
1977 | for (i = 0; i < shared_count; ++i) { | |
1978 | amdgpu_vm_prt_get(adev); | |
1979 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1980 | } | |
1981 | ||
1982 | kfree(shared); | |
284710fa CK |
1983 | } |
1984 | ||
d38ceaf9 AD |
1985 | /** |
1986 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1987 | * | |
1988 | * @adev: amdgpu_device pointer | |
1989 | * @vm: requested vm | |
f3467818 NH |
1990 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1991 | * or if an error occurred) | |
d38ceaf9 AD |
1992 | * |
1993 | * Make sure all freed BOs are cleared in the PT. | |
d38ceaf9 | 1994 | * PTs have to be reserved and mutex must be locked! |
7fc48e59 AG |
1995 | * |
1996 | * Returns: | |
1997 | * 0 for success. | |
1998 | * | |
d38ceaf9 AD |
1999 | */ |
2000 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
2001 | struct amdgpu_vm *vm, |
2002 | struct dma_fence **fence) | |
d38ceaf9 | 2003 | { |
9f3cc18d | 2004 | struct dma_resv *resv = vm->root.base.bo->tbo.base.resv; |
d38ceaf9 | 2005 | struct amdgpu_bo_va_mapping *mapping; |
4584312d | 2006 | uint64_t init_pte_value = 0; |
f3467818 | 2007 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
2008 | int r; |
2009 | ||
2010 | while (!list_empty(&vm->freed)) { | |
2011 | mapping = list_first_entry(&vm->freed, | |
2012 | struct amdgpu_bo_va_mapping, list); | |
2013 | list_del(&mapping->list); | |
e17841b9 | 2014 | |
ad9a5b78 CK |
2015 | if (vm->pte_support_ats && |
2016 | mapping->start < AMDGPU_GMC_HOLE_START) | |
6d16dac8 | 2017 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec | 2018 | |
a39f2a8d CK |
2019 | r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false, |
2020 | resv, mapping->start, | |
2021 | mapping->last, init_pte_value, | |
2022 | 0, NULL, NULL, &f); | |
f3467818 | 2023 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 2024 | if (r) { |
f3467818 | 2025 | dma_fence_put(f); |
d38ceaf9 | 2026 | return r; |
284710fa | 2027 | } |
f3467818 | 2028 | } |
d38ceaf9 | 2029 | |
f3467818 NH |
2030 | if (fence && f) { |
2031 | dma_fence_put(*fence); | |
2032 | *fence = f; | |
2033 | } else { | |
2034 | dma_fence_put(f); | |
d38ceaf9 | 2035 | } |
f3467818 | 2036 | |
d38ceaf9 AD |
2037 | return 0; |
2038 | ||
2039 | } | |
2040 | ||
2041 | /** | |
73fb16e7 | 2042 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
2043 | * |
2044 | * @adev: amdgpu_device pointer | |
2045 | * @vm: requested vm | |
2046 | * | |
73fb16e7 | 2047 | * Make sure all BOs which are moved are updated in the PTs. |
7fc48e59 AG |
2048 | * |
2049 | * Returns: | |
2050 | * 0 for success. | |
d38ceaf9 | 2051 | * |
73fb16e7 | 2052 | * PTs have to be reserved! |
d38ceaf9 | 2053 | */ |
73fb16e7 | 2054 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 2055 | struct amdgpu_vm *vm) |
d38ceaf9 | 2056 | { |
789f3317 | 2057 | struct amdgpu_bo_va *bo_va, *tmp; |
52791eee | 2058 | struct dma_resv *resv; |
73fb16e7 | 2059 | bool clear; |
789f3317 | 2060 | int r; |
d38ceaf9 | 2061 | |
c12a2ee5 CK |
2062 | list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { |
2063 | /* Per VM BOs never need to bo cleared in the page tables */ | |
2064 | r = amdgpu_vm_bo_update(adev, bo_va, false); | |
2065 | if (r) | |
2066 | return r; | |
2067 | } | |
32b41ac2 | 2068 | |
c12a2ee5 CK |
2069 | spin_lock(&vm->invalidated_lock); |
2070 | while (!list_empty(&vm->invalidated)) { | |
2071 | bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, | |
2072 | base.vm_status); | |
5a5011a7 | 2073 | resv = bo_va->base.bo->tbo.base.resv; |
c12a2ee5 | 2074 | spin_unlock(&vm->invalidated_lock); |
ec363e0d | 2075 | |
ec363e0d | 2076 | /* Try to reserve the BO to avoid clearing its ptes */ |
52791eee | 2077 | if (!amdgpu_vm_debug && dma_resv_trylock(resv)) |
ec363e0d CK |
2078 | clear = false; |
2079 | /* Somebody else is using the BO right now */ | |
2080 | else | |
2081 | clear = true; | |
73fb16e7 CK |
2082 | |
2083 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
c12a2ee5 | 2084 | if (r) |
d38ceaf9 AD |
2085 | return r; |
2086 | ||
c12a2ee5 | 2087 | if (!clear) |
52791eee | 2088 | dma_resv_unlock(resv); |
c12a2ee5 | 2089 | spin_lock(&vm->invalidated_lock); |
d38ceaf9 | 2090 | } |
c12a2ee5 | 2091 | spin_unlock(&vm->invalidated_lock); |
d38ceaf9 | 2092 | |
789f3317 | 2093 | return 0; |
d38ceaf9 AD |
2094 | } |
2095 | ||
2096 | /** | |
2097 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
2098 | * | |
2099 | * @adev: amdgpu_device pointer | |
2100 | * @vm: requested vm | |
2101 | * @bo: amdgpu buffer object | |
2102 | * | |
8843dbbb | 2103 | * Add @bo into the requested vm. |
d38ceaf9 | 2104 | * Add @bo to the list of bos associated with the vm |
7fc48e59 AG |
2105 | * |
2106 | * Returns: | |
2107 | * Newly added bo_va or NULL for failure | |
d38ceaf9 AD |
2108 | * |
2109 | * Object has to be reserved! | |
2110 | */ | |
2111 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
2112 | struct amdgpu_vm *vm, | |
2113 | struct amdgpu_bo *bo) | |
2114 | { | |
2115 | struct amdgpu_bo_va *bo_va; | |
2116 | ||
2117 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2118 | if (bo_va == NULL) { | |
2119 | return NULL; | |
2120 | } | |
3f4299be | 2121 | amdgpu_vm_bo_base_init(&bo_va->base, vm, bo); |
ec681545 | 2122 | |
d38ceaf9 | 2123 | bo_va->ref_count = 1; |
7fc11959 CK |
2124 | INIT_LIST_HEAD(&bo_va->valids); |
2125 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2126 | |
0cf0ee98 A |
2127 | if (!bo) |
2128 | return bo_va; | |
2129 | ||
2130 | if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) { | |
df399b06 | 2131 | bo_va->is_xgmi = true; |
df399b06 | 2132 | /* Power up XGMI if it can be potentially used */ |
d84a430d | 2133 | amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20); |
df399b06 | 2134 | } |
2135 | ||
d38ceaf9 AD |
2136 | return bo_va; |
2137 | } | |
2138 | ||
73fb16e7 CK |
2139 | |
2140 | /** | |
c45dd3bd | 2141 | * amdgpu_vm_bo_insert_map - insert a new mapping |
73fb16e7 CK |
2142 | * |
2143 | * @adev: amdgpu_device pointer | |
2144 | * @bo_va: bo_va to store the address | |
2145 | * @mapping: the mapping to insert | |
2146 | * | |
2147 | * Insert a new mapping into all structures. | |
2148 | */ | |
2149 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2150 | struct amdgpu_bo_va *bo_va, | |
2151 | struct amdgpu_bo_va_mapping *mapping) | |
2152 | { | |
2153 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2154 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2155 | ||
aebc5e6f | 2156 | mapping->bo_va = bo_va; |
73fb16e7 CK |
2157 | list_add(&mapping->list, &bo_va->invalids); |
2158 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2159 | ||
2160 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2161 | amdgpu_vm_prt_get(adev); | |
2162 | ||
5a5011a7 | 2163 | if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv && |
862b8c57 | 2164 | !bo_va->base.moved) { |
862b8c57 | 2165 | list_move(&bo_va->base.vm_status, &vm->moved); |
73fb16e7 CK |
2166 | } |
2167 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2168 | } | |
2169 | ||
d38ceaf9 AD |
2170 | /** |
2171 | * amdgpu_vm_bo_map - map bo inside a vm | |
2172 | * | |
2173 | * @adev: amdgpu_device pointer | |
2174 | * @bo_va: bo_va to store the address | |
2175 | * @saddr: where to map the BO | |
2176 | * @offset: requested offset in the BO | |
00553cf8 | 2177 | * @size: BO size in bytes |
d38ceaf9 AD |
2178 | * @flags: attributes of pages (read/write/valid/etc.) |
2179 | * | |
2180 | * Add a mapping of the BO at the specefied addr into the VM. | |
7fc48e59 AG |
2181 | * |
2182 | * Returns: | |
2183 | * 0 for success, error for failure. | |
d38ceaf9 | 2184 | * |
49b02b18 | 2185 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2186 | */ |
2187 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2188 | struct amdgpu_bo_va *bo_va, | |
2189 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2190 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2191 | { |
a9f87f64 | 2192 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2193 | struct amdgpu_bo *bo = bo_va->base.bo; |
2194 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2195 | uint64_t eaddr; |
d38ceaf9 | 2196 | |
0be52de9 CK |
2197 | /* validate the parameters */ |
2198 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2199 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2200 | return -EINVAL; |
0be52de9 | 2201 | |
d38ceaf9 | 2202 | /* make sure object fit at this offset */ |
005ae95e | 2203 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2204 | if (saddr >= eaddr || |
8b80d74b RB |
2205 | (bo && offset + size > amdgpu_bo_size(bo)) || |
2206 | (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT)) | |
d38ceaf9 | 2207 | return -EINVAL; |
d38ceaf9 | 2208 | |
d38ceaf9 AD |
2209 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2210 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2211 | ||
a9f87f64 CK |
2212 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2213 | if (tmp) { | |
d38ceaf9 AD |
2214 | /* bo and tmp overlap, invalid addr */ |
2215 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2216 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2217 | tmp->start, tmp->last + 1); |
663e4577 | 2218 | return -EINVAL; |
d38ceaf9 AD |
2219 | } |
2220 | ||
2221 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2222 | if (!mapping) |
2223 | return -ENOMEM; | |
d38ceaf9 | 2224 | |
a9f87f64 CK |
2225 | mapping->start = saddr; |
2226 | mapping->last = eaddr; | |
d38ceaf9 AD |
2227 | mapping->offset = offset; |
2228 | mapping->flags = flags; | |
2229 | ||
73fb16e7 | 2230 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
2231 | |
2232 | return 0; | |
2233 | } | |
2234 | ||
2235 | /** | |
2236 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2237 | * | |
2238 | * @adev: amdgpu_device pointer | |
2239 | * @bo_va: bo_va to store the address | |
2240 | * @saddr: where to map the BO | |
2241 | * @offset: requested offset in the BO | |
00553cf8 | 2242 | * @size: BO size in bytes |
80f95c57 CK |
2243 | * @flags: attributes of pages (read/write/valid/etc.) |
2244 | * | |
2245 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2246 | * mappings as we do so. | |
7fc48e59 AG |
2247 | * |
2248 | * Returns: | |
2249 | * 0 for success, error for failure. | |
80f95c57 CK |
2250 | * |
2251 | * Object has to be reserved and unreserved outside! | |
2252 | */ | |
2253 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2254 | struct amdgpu_bo_va *bo_va, | |
2255 | uint64_t saddr, uint64_t offset, | |
2256 | uint64_t size, uint64_t flags) | |
2257 | { | |
2258 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2259 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
2260 | uint64_t eaddr; |
2261 | int r; | |
2262 | ||
2263 | /* validate the parameters */ | |
2264 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2265 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2266 | return -EINVAL; | |
2267 | ||
2268 | /* make sure object fit at this offset */ | |
2269 | eaddr = saddr + size - 1; | |
2270 | if (saddr >= eaddr || | |
8b80d74b RB |
2271 | (bo && offset + size > amdgpu_bo_size(bo)) || |
2272 | (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT)) | |
80f95c57 CK |
2273 | return -EINVAL; |
2274 | ||
2275 | /* Allocate all the needed memory */ | |
2276 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2277 | if (!mapping) | |
2278 | return -ENOMEM; | |
2279 | ||
ec681545 | 2280 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2281 | if (r) { |
2282 | kfree(mapping); | |
2283 | return r; | |
2284 | } | |
2285 | ||
2286 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2287 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2288 | ||
a9f87f64 CK |
2289 | mapping->start = saddr; |
2290 | mapping->last = eaddr; | |
80f95c57 CK |
2291 | mapping->offset = offset; |
2292 | mapping->flags = flags; | |
2293 | ||
73fb16e7 | 2294 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 2295 | |
d38ceaf9 | 2296 | return 0; |
d38ceaf9 AD |
2297 | } |
2298 | ||
2299 | /** | |
2300 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2301 | * | |
2302 | * @adev: amdgpu_device pointer | |
2303 | * @bo_va: bo_va to remove the address from | |
2304 | * @saddr: where to the BO is mapped | |
2305 | * | |
2306 | * Remove a mapping of the BO at the specefied addr from the VM. | |
7fc48e59 AG |
2307 | * |
2308 | * Returns: | |
2309 | * 0 for success, error for failure. | |
d38ceaf9 | 2310 | * |
49b02b18 | 2311 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2312 | */ |
2313 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2314 | struct amdgpu_bo_va *bo_va, | |
2315 | uint64_t saddr) | |
2316 | { | |
2317 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2318 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2319 | bool valid = true; |
d38ceaf9 | 2320 | |
6c7fc503 | 2321 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2322 | |
7fc11959 | 2323 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2324 | if (mapping->start == saddr) |
d38ceaf9 AD |
2325 | break; |
2326 | } | |
2327 | ||
7fc11959 CK |
2328 | if (&mapping->list == &bo_va->valids) { |
2329 | valid = false; | |
2330 | ||
2331 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2332 | if (mapping->start == saddr) |
7fc11959 CK |
2333 | break; |
2334 | } | |
2335 | ||
32b41ac2 | 2336 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2337 | return -ENOENT; |
d38ceaf9 | 2338 | } |
32b41ac2 | 2339 | |
d38ceaf9 | 2340 | list_del(&mapping->list); |
a9f87f64 | 2341 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2342 | mapping->bo_va = NULL; |
93e3e438 | 2343 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2344 | |
e17841b9 | 2345 | if (valid) |
d38ceaf9 | 2346 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2347 | else |
284710fa CK |
2348 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2349 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2350 | |
2351 | return 0; | |
2352 | } | |
2353 | ||
dc54d3d1 CK |
2354 | /** |
2355 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2356 | * | |
2357 | * @adev: amdgpu_device pointer | |
2358 | * @vm: VM structure to use | |
2359 | * @saddr: start of the range | |
2360 | * @size: size of the range | |
2361 | * | |
2362 | * Remove all mappings in a range, split them as appropriate. | |
7fc48e59 AG |
2363 | * |
2364 | * Returns: | |
2365 | * 0 for success, error for failure. | |
dc54d3d1 CK |
2366 | */ |
2367 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2368 | struct amdgpu_vm *vm, | |
2369 | uint64_t saddr, uint64_t size) | |
2370 | { | |
2371 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2372 | LIST_HEAD(removed); |
2373 | uint64_t eaddr; | |
2374 | ||
2375 | eaddr = saddr + size - 1; | |
2376 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2377 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2378 | ||
2379 | /* Allocate all the needed memory */ | |
2380 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2381 | if (!before) | |
2382 | return -ENOMEM; | |
27f6d610 | 2383 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2384 | |
2385 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2386 | if (!after) { | |
2387 | kfree(before); | |
2388 | return -ENOMEM; | |
2389 | } | |
27f6d610 | 2390 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2391 | |
2392 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2393 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2394 | while (tmp) { | |
dc54d3d1 | 2395 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2396 | if (tmp->start < saddr) { |
2397 | before->start = tmp->start; | |
2398 | before->last = saddr - 1; | |
dc54d3d1 CK |
2399 | before->offset = tmp->offset; |
2400 | before->flags = tmp->flags; | |
387f49e5 JZ |
2401 | before->bo_va = tmp->bo_va; |
2402 | list_add(&before->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2403 | } |
2404 | ||
2405 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2406 | if (tmp->last > eaddr) { |
2407 | after->start = eaddr + 1; | |
2408 | after->last = tmp->last; | |
dc54d3d1 | 2409 | after->offset = tmp->offset; |
787fece7 | 2410 | after->offset += (after->start - tmp->start) << PAGE_SHIFT; |
dc54d3d1 | 2411 | after->flags = tmp->flags; |
387f49e5 JZ |
2412 | after->bo_va = tmp->bo_va; |
2413 | list_add(&after->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2414 | } |
2415 | ||
2416 | list_del(&tmp->list); | |
2417 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2418 | |
2419 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2420 | } |
2421 | ||
2422 | /* And free them up */ | |
2423 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2424 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2425 | list_del(&tmp->list); |
2426 | ||
a9f87f64 CK |
2427 | if (tmp->start < saddr) |
2428 | tmp->start = saddr; | |
2429 | if (tmp->last > eaddr) | |
2430 | tmp->last = eaddr; | |
dc54d3d1 | 2431 | |
aebc5e6f | 2432 | tmp->bo_va = NULL; |
dc54d3d1 CK |
2433 | list_add(&tmp->list, &vm->freed); |
2434 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2435 | } | |
2436 | ||
27f6d610 JZ |
2437 | /* Insert partial mapping before the range */ |
2438 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2439 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2440 | if (before->flags & AMDGPU_PTE_PRT) |
2441 | amdgpu_vm_prt_get(adev); | |
2442 | } else { | |
2443 | kfree(before); | |
2444 | } | |
2445 | ||
2446 | /* Insert partial mapping after the range */ | |
27f6d610 | 2447 | if (!list_empty(&after->list)) { |
a9f87f64 | 2448 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2449 | if (after->flags & AMDGPU_PTE_PRT) |
2450 | amdgpu_vm_prt_get(adev); | |
2451 | } else { | |
2452 | kfree(after); | |
2453 | } | |
2454 | ||
2455 | return 0; | |
2456 | } | |
2457 | ||
aebc5e6f CK |
2458 | /** |
2459 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2460 | * | |
2461 | * @vm: the requested VM | |
00553cf8 | 2462 | * @addr: the address |
aebc5e6f CK |
2463 | * |
2464 | * Find a mapping by it's address. | |
7fc48e59 AG |
2465 | * |
2466 | * Returns: | |
2467 | * The amdgpu_bo_va_mapping matching for addr or NULL | |
2468 | * | |
aebc5e6f CK |
2469 | */ |
2470 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2471 | uint64_t addr) | |
2472 | { | |
2473 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2474 | } | |
2475 | ||
8ab19ea6 CK |
2476 | /** |
2477 | * amdgpu_vm_bo_trace_cs - trace all reserved mappings | |
2478 | * | |
2479 | * @vm: the requested vm | |
2480 | * @ticket: CS ticket | |
2481 | * | |
2482 | * Trace all mappings of BOs reserved during a command submission. | |
2483 | */ | |
2484 | void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) | |
2485 | { | |
2486 | struct amdgpu_bo_va_mapping *mapping; | |
2487 | ||
2488 | if (!trace_amdgpu_vm_bo_cs_enabled()) | |
2489 | return; | |
2490 | ||
2491 | for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping; | |
2492 | mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) { | |
2493 | if (mapping->bo_va && mapping->bo_va->base.bo) { | |
2494 | struct amdgpu_bo *bo; | |
2495 | ||
2496 | bo = mapping->bo_va->base.bo; | |
52791eee | 2497 | if (dma_resv_locking_ctx(bo->tbo.base.resv) != |
0dbd555a | 2498 | ticket) |
8ab19ea6 CK |
2499 | continue; |
2500 | } | |
2501 | ||
2502 | trace_amdgpu_vm_bo_cs(mapping); | |
2503 | } | |
2504 | } | |
2505 | ||
d38ceaf9 AD |
2506 | /** |
2507 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2508 | * | |
2509 | * @adev: amdgpu_device pointer | |
2510 | * @bo_va: requested bo_va | |
2511 | * | |
8843dbbb | 2512 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2513 | * |
2514 | * Object have to be reserved! | |
2515 | */ | |
2516 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2517 | struct amdgpu_bo_va *bo_va) | |
2518 | { | |
2519 | struct amdgpu_bo_va_mapping *mapping, *next; | |
fbbf794c | 2520 | struct amdgpu_bo *bo = bo_va->base.bo; |
ec681545 | 2521 | struct amdgpu_vm *vm = bo_va->base.vm; |
646b9025 | 2522 | struct amdgpu_vm_bo_base **base; |
d38ceaf9 | 2523 | |
646b9025 | 2524 | if (bo) { |
5a5011a7 | 2525 | if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) |
646b9025 | 2526 | vm->bulk_moveable = false; |
fbbf794c | 2527 | |
646b9025 CK |
2528 | for (base = &bo_va->base.bo->vm_bo; *base; |
2529 | base = &(*base)->next) { | |
2530 | if (*base != &bo_va->base) | |
2531 | continue; | |
2532 | ||
2533 | *base = bo_va->base.next; | |
2534 | break; | |
2535 | } | |
2536 | } | |
d38ceaf9 | 2537 | |
c12a2ee5 | 2538 | spin_lock(&vm->invalidated_lock); |
ec681545 | 2539 | list_del(&bo_va->base.vm_status); |
c12a2ee5 | 2540 | spin_unlock(&vm->invalidated_lock); |
d38ceaf9 | 2541 | |
7fc11959 | 2542 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2543 | list_del(&mapping->list); |
a9f87f64 | 2544 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2545 | mapping->bo_va = NULL; |
93e3e438 | 2546 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2547 | list_add(&mapping->list, &vm->freed); |
2548 | } | |
2549 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2550 | list_del(&mapping->list); | |
a9f87f64 | 2551 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2552 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2553 | bo_va->last_pt_update); | |
d38ceaf9 | 2554 | } |
32b41ac2 | 2555 | |
f54d1867 | 2556 | dma_fence_put(bo_va->last_pt_update); |
df399b06 | 2557 | |
d84a430d JK |
2558 | if (bo && bo_va->is_xgmi) |
2559 | amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN); | |
df399b06 | 2560 | |
d38ceaf9 | 2561 | kfree(bo_va); |
d38ceaf9 AD |
2562 | } |
2563 | ||
6ceeb144 CK |
2564 | /** |
2565 | * amdgpu_vm_evictable - check if we can evict a VM | |
2566 | * | |
2567 | * @bo: A page table of the VM. | |
2568 | * | |
2569 | * Check if it is possible to evict a VM. | |
2570 | */ | |
2571 | bool amdgpu_vm_evictable(struct amdgpu_bo *bo) | |
2572 | { | |
2573 | struct amdgpu_vm_bo_base *bo_base = bo->vm_bo; | |
2574 | ||
2575 | /* Page tables of a destroyed VM can go away immediately */ | |
2576 | if (!bo_base || !bo_base->vm) | |
2577 | return true; | |
2578 | ||
2579 | /* Don't evict VM page tables while they are busy */ | |
2580 | if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true)) | |
2581 | return false; | |
2582 | ||
b4ff0f8a | 2583 | /* Try to block ongoing updates */ |
a269e449 | 2584 | if (!amdgpu_vm_eviction_trylock(bo_base->vm)) |
b4ff0f8a CK |
2585 | return false; |
2586 | ||
90b69cdc | 2587 | /* Don't evict VM page tables while they are updated */ |
9c466bcb | 2588 | if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) { |
a269e449 | 2589 | amdgpu_vm_eviction_unlock(bo_base->vm); |
90b69cdc | 2590 | return false; |
b4ff0f8a | 2591 | } |
90b69cdc | 2592 | |
b4ff0f8a | 2593 | bo_base->vm->evicting = true; |
a269e449 | 2594 | amdgpu_vm_eviction_unlock(bo_base->vm); |
6ceeb144 CK |
2595 | return true; |
2596 | } | |
2597 | ||
d38ceaf9 AD |
2598 | /** |
2599 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2600 | * | |
2601 | * @adev: amdgpu_device pointer | |
d38ceaf9 | 2602 | * @bo: amdgpu buffer object |
00553cf8 | 2603 | * @evicted: is the BO evicted |
d38ceaf9 | 2604 | * |
8843dbbb | 2605 | * Mark @bo as invalid. |
d38ceaf9 AD |
2606 | */ |
2607 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2608 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2609 | { |
ec681545 CK |
2610 | struct amdgpu_vm_bo_base *bo_base; |
2611 | ||
4bebccee CZ |
2612 | /* shadow bo doesn't have bo base, its validation needs its parent */ |
2613 | if (bo->parent && bo->parent->shadow == bo) | |
2614 | bo = bo->parent; | |
2615 | ||
646b9025 | 2616 | for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { |
3f3333f8 CK |
2617 | struct amdgpu_vm *vm = bo_base->vm; |
2618 | ||
5a5011a7 | 2619 | if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) { |
bcdc9fd6 | 2620 | amdgpu_vm_bo_evicted(bo_base); |
3f3333f8 CK |
2621 | continue; |
2622 | } | |
2623 | ||
bcdc9fd6 | 2624 | if (bo_base->moved) |
3f3333f8 | 2625 | continue; |
bcdc9fd6 | 2626 | bo_base->moved = true; |
3f3333f8 | 2627 | |
bcdc9fd6 CK |
2628 | if (bo->tbo.type == ttm_bo_type_kernel) |
2629 | amdgpu_vm_bo_relocated(bo_base); | |
5a5011a7 | 2630 | else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) |
bcdc9fd6 CK |
2631 | amdgpu_vm_bo_moved(bo_base); |
2632 | else | |
2633 | amdgpu_vm_bo_invalidated(bo_base); | |
d38ceaf9 AD |
2634 | } |
2635 | } | |
2636 | ||
7fc48e59 AG |
2637 | /** |
2638 | * amdgpu_vm_get_block_size - calculate VM page table size as power of two | |
2639 | * | |
2640 | * @vm_size: VM size | |
2641 | * | |
2642 | * Returns: | |
2643 | * VM page table as power of two | |
2644 | */ | |
bab4fee7 JZ |
2645 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2646 | { | |
2647 | /* Total bits covered by PD + PTs */ | |
2648 | unsigned bits = ilog2(vm_size) + 18; | |
2649 | ||
2650 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2651 | Above that split equal between PD and PTs */ | |
2652 | if (vm_size <= 8) | |
2653 | return (bits - 9); | |
2654 | else | |
2655 | return ((bits + 3) / 2); | |
2656 | } | |
2657 | ||
d07f14be RH |
2658 | /** |
2659 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2660 | * |
2661 | * @adev: amdgpu_device pointer | |
43370c4c | 2662 | * @min_vm_size: the minimum vm size in GB if it's set auto |
00553cf8 AG |
2663 | * @fragment_size_default: Default PTE fragment size |
2664 | * @max_level: max VMPT level | |
2665 | * @max_bits: max address space size in bits | |
2666 | * | |
bab4fee7 | 2667 | */ |
43370c4c | 2668 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, |
f3368128 CK |
2669 | uint32_t fragment_size_default, unsigned max_level, |
2670 | unsigned max_bits) | |
bab4fee7 | 2671 | { |
43370c4c FK |
2672 | unsigned int max_size = 1 << (max_bits - 30); |
2673 | unsigned int vm_size; | |
36539dce CK |
2674 | uint64_t tmp; |
2675 | ||
2676 | /* adjust vm size first */ | |
f3368128 | 2677 | if (amdgpu_vm_size != -1) { |
fdd5faaa | 2678 | vm_size = amdgpu_vm_size; |
f3368128 CK |
2679 | if (vm_size > max_size) { |
2680 | dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", | |
2681 | amdgpu_vm_size, max_size); | |
2682 | vm_size = max_size; | |
2683 | } | |
43370c4c FK |
2684 | } else { |
2685 | struct sysinfo si; | |
2686 | unsigned int phys_ram_gb; | |
2687 | ||
2688 | /* Optimal VM size depends on the amount of physical | |
2689 | * RAM available. Underlying requirements and | |
2690 | * assumptions: | |
2691 | * | |
2692 | * - Need to map system memory and VRAM from all GPUs | |
2693 | * - VRAM from other GPUs not known here | |
2694 | * - Assume VRAM <= system memory | |
2695 | * - On GFX8 and older, VM space can be segmented for | |
2696 | * different MTYPEs | |
2697 | * - Need to allow room for fragmentation, guard pages etc. | |
2698 | * | |
2699 | * This adds up to a rough guess of system memory x3. | |
2700 | * Round up to power of two to maximize the available | |
2701 | * VM size with the given page table size. | |
2702 | */ | |
2703 | si_meminfo(&si); | |
2704 | phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit + | |
2705 | (1 << 30) - 1) >> 30; | |
2706 | vm_size = roundup_pow_of_two( | |
2707 | min(max(phys_ram_gb * 3, min_vm_size), max_size)); | |
f3368128 | 2708 | } |
fdd5faaa CK |
2709 | |
2710 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
36539dce CK |
2711 | |
2712 | tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); | |
97489129 CK |
2713 | if (amdgpu_vm_block_size != -1) |
2714 | tmp >>= amdgpu_vm_block_size - 9; | |
36539dce CK |
2715 | tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; |
2716 | adev->vm_manager.num_level = min(max_level, (unsigned)tmp); | |
196f7489 CZ |
2717 | switch (adev->vm_manager.num_level) { |
2718 | case 3: | |
2719 | adev->vm_manager.root_level = AMDGPU_VM_PDB2; | |
2720 | break; | |
2721 | case 2: | |
2722 | adev->vm_manager.root_level = AMDGPU_VM_PDB1; | |
2723 | break; | |
2724 | case 1: | |
2725 | adev->vm_manager.root_level = AMDGPU_VM_PDB0; | |
2726 | break; | |
2727 | default: | |
2728 | dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n"); | |
2729 | } | |
b38f41eb | 2730 | /* block size depends on vm size and hw setup*/ |
97489129 | 2731 | if (amdgpu_vm_block_size != -1) |
bab4fee7 | 2732 | adev->vm_manager.block_size = |
97489129 CK |
2733 | min((unsigned)amdgpu_vm_block_size, max_bits |
2734 | - AMDGPU_GPU_PAGE_SHIFT | |
2735 | - 9 * adev->vm_manager.num_level); | |
2736 | else if (adev->vm_manager.num_level > 1) | |
2737 | adev->vm_manager.block_size = 9; | |
bab4fee7 | 2738 | else |
97489129 | 2739 | adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); |
bab4fee7 | 2740 | |
b38f41eb CK |
2741 | if (amdgpu_vm_fragment_size == -1) |
2742 | adev->vm_manager.fragment_size = fragment_size_default; | |
2743 | else | |
2744 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
d07f14be | 2745 | |
36539dce CK |
2746 | DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", |
2747 | vm_size, adev->vm_manager.num_level + 1, | |
2748 | adev->vm_manager.block_size, | |
fdd5faaa | 2749 | adev->vm_manager.fragment_size); |
bab4fee7 JZ |
2750 | } |
2751 | ||
56753e73 CK |
2752 | /** |
2753 | * amdgpu_vm_wait_idle - wait for the VM to become idle | |
2754 | * | |
2755 | * @vm: VM object to wait for | |
2756 | * @timeout: timeout to wait for VM to become idle | |
2757 | */ | |
2758 | long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout) | |
240cd9a6 | 2759 | { |
90b69cdc CK |
2760 | timeout = dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv, |
2761 | true, true, timeout); | |
2762 | if (timeout <= 0) | |
2763 | return timeout; | |
2764 | ||
9c466bcb | 2765 | return dma_fence_wait_timeout(vm->last_unlocked, true, timeout); |
240cd9a6 OZ |
2766 | } |
2767 | ||
d38ceaf9 AD |
2768 | /** |
2769 | * amdgpu_vm_init - initialize a vm instance | |
2770 | * | |
2771 | * @adev: amdgpu_device pointer | |
2772 | * @vm: requested vm | |
9a4b7d4c | 2773 | * @vm_context: Indicates if it GFX or Compute context |
00553cf8 | 2774 | * @pasid: Process address space identifier |
d38ceaf9 | 2775 | * |
8843dbbb | 2776 | * Init @vm fields. |
7fc48e59 AG |
2777 | * |
2778 | * Returns: | |
2779 | * 0 for success, error for failure. | |
d38ceaf9 | 2780 | */ |
9a4b7d4c | 2781 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
c7b6bac9 | 2782 | int vm_context, u32 pasid) |
d38ceaf9 | 2783 | { |
3216c6b7 | 2784 | struct amdgpu_bo_param bp; |
3f4299be | 2785 | struct amdgpu_bo *root; |
36bbf3bf | 2786 | int r, i; |
d38ceaf9 | 2787 | |
f808c13f | 2788 | vm->va = RB_ROOT_CACHED; |
36bbf3bf CZ |
2789 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2790 | vm->reserved_vmid[i] = NULL; | |
3f3333f8 | 2791 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2792 | INIT_LIST_HEAD(&vm->relocated); |
27c7b9ae | 2793 | INIT_LIST_HEAD(&vm->moved); |
806f043f | 2794 | INIT_LIST_HEAD(&vm->idle); |
c12a2ee5 CK |
2795 | INIT_LIST_HEAD(&vm->invalidated); |
2796 | spin_lock_init(&vm->invalidated_lock); | |
d38ceaf9 | 2797 | INIT_LIST_HEAD(&vm->freed); |
0e601a04 | 2798 | INIT_LIST_HEAD(&vm->done); |
b3ac1766 | 2799 | |
a2cf3247 | 2800 | /* create scheduler entities for page table updates */ |
eaad0c3a | 2801 | r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL, |
0c88b430 ND |
2802 | adev->vm_manager.vm_pte_scheds, |
2803 | adev->vm_manager.vm_pte_num_scheds, NULL); | |
2bd9ccfa | 2804 | if (r) |
f566ceb1 | 2805 | return r; |
2bd9ccfa | 2806 | |
b3ac1766 | 2807 | r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL, |
0c88b430 ND |
2808 | adev->vm_manager.vm_pte_scheds, |
2809 | adev->vm_manager.vm_pte_num_scheds, NULL); | |
a2cf3247 | 2810 | if (r) |
eaad0c3a | 2811 | goto error_free_immediate; |
a2cf3247 | 2812 | |
51ac7eec | 2813 | vm->pte_support_ats = false; |
f43ef951 | 2814 | vm->is_compute_context = false; |
51ac7eec YZ |
2815 | |
2816 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2817 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2818 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec | 2819 | |
741deade | 2820 | if (adev->asic_type == CHIP_RAVEN) |
51ac7eec | 2821 | vm->pte_support_ats = true; |
13307f7e | 2822 | } else { |
9a4b7d4c HK |
2823 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2824 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
13307f7e | 2825 | } |
9a4b7d4c HK |
2826 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2827 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
fc39d903 CK |
2828 | WARN_ONCE((vm->use_cpu_for_update && |
2829 | !amdgpu_gmc_vram_full_visible(&adev->gmc)), | |
9a4b7d4c | 2830 | "CPU update of VM recommended only for large BAR system\n"); |
6dd09027 CK |
2831 | |
2832 | if (vm->use_cpu_for_update) | |
2833 | vm->update_funcs = &amdgpu_vm_cpu_funcs; | |
2834 | else | |
2835 | vm->update_funcs = &amdgpu_vm_sdma_funcs; | |
d5884513 | 2836 | vm->last_update = NULL; |
9c466bcb | 2837 | vm->last_unlocked = dma_fence_get_stub(); |
05906dec | 2838 | |
b4ff0f8a CK |
2839 | mutex_init(&vm->eviction_lock); |
2840 | vm->evicting = false; | |
2841 | ||
061468c4 | 2842 | amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, &bp); |
03e9dee1 FK |
2843 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) |
2844 | bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW; | |
3f4299be | 2845 | r = amdgpu_bo_create(adev, &bp, &root); |
d38ceaf9 | 2846 | if (r) |
a2cf3247 | 2847 | goto error_free_delayed; |
2bd9ccfa | 2848 | |
3f4299be | 2849 | r = amdgpu_bo_reserve(root, true); |
d3aab672 CK |
2850 | if (r) |
2851 | goto error_free_root; | |
2852 | ||
52791eee | 2853 | r = dma_resv_reserve_shared(root->tbo.base.resv, 1); |
0aa7aa24 CK |
2854 | if (r) |
2855 | goto error_unreserve; | |
2856 | ||
1e293037 CK |
2857 | amdgpu_vm_bo_base_init(&vm->root.base, vm, root); |
2858 | ||
0f6064d6 | 2859 | r = amdgpu_vm_clear_bo(adev, vm, root, false); |
13307f7e CK |
2860 | if (r) |
2861 | goto error_unreserve; | |
2862 | ||
d3aab672 | 2863 | amdgpu_bo_unreserve(vm->root.base.bo); |
d38ceaf9 | 2864 | |
02208441 FK |
2865 | if (pasid) { |
2866 | unsigned long flags; | |
2867 | ||
2868 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2869 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2870 | GFP_ATOMIC); | |
2871 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2872 | if (r < 0) | |
2873 | goto error_free_root; | |
2874 | ||
2875 | vm->pasid = pasid; | |
0a096fb6 CK |
2876 | } |
2877 | ||
a2f14820 | 2878 | INIT_KFIFO(vm->faults); |
d38ceaf9 AD |
2879 | |
2880 | return 0; | |
2bd9ccfa | 2881 | |
13307f7e CK |
2882 | error_unreserve: |
2883 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2884 | ||
67003a15 | 2885 | error_free_root: |
3f3333f8 CK |
2886 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2887 | amdgpu_bo_unref(&vm->root.base.bo); | |
2888 | vm->root.base.bo = NULL; | |
2bd9ccfa | 2889 | |
a2cf3247 | 2890 | error_free_delayed: |
9c466bcb | 2891 | dma_fence_put(vm->last_unlocked); |
a2cf3247 CK |
2892 | drm_sched_entity_destroy(&vm->delayed); |
2893 | ||
eaad0c3a CK |
2894 | error_free_immediate: |
2895 | drm_sched_entity_destroy(&vm->immediate); | |
2bd9ccfa CK |
2896 | |
2897 | return r; | |
d38ceaf9 AD |
2898 | } |
2899 | ||
3680624e TH |
2900 | /** |
2901 | * amdgpu_vm_check_clean_reserved - check if a VM is clean | |
2902 | * | |
2903 | * @adev: amdgpu_device pointer | |
2904 | * @vm: the VM to check | |
2905 | * | |
2906 | * check all entries of the root PD, if any subsequent PDs are allocated, | |
2907 | * it means there are page table creating and filling, and is no a clean | |
2908 | * VM | |
2909 | * | |
2910 | * Returns: | |
2911 | * 0 if this VM is clean | |
2912 | */ | |
2913 | static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev, | |
2914 | struct amdgpu_vm *vm) | |
2915 | { | |
2916 | enum amdgpu_vm_level root = adev->vm_manager.root_level; | |
2917 | unsigned int entries = amdgpu_vm_num_entries(adev, root); | |
2918 | unsigned int i = 0; | |
2919 | ||
2920 | if (!(vm->root.entries)) | |
2921 | return 0; | |
2922 | ||
2923 | for (i = 0; i < entries; i++) { | |
2924 | if (vm->root.entries[i].base.bo) | |
2925 | return -EINVAL; | |
2926 | } | |
2927 | ||
2928 | return 0; | |
2929 | } | |
2930 | ||
b236fa1d FK |
2931 | /** |
2932 | * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM | |
2933 | * | |
7fc48e59 AG |
2934 | * @adev: amdgpu_device pointer |
2935 | * @vm: requested vm | |
1d614ded | 2936 | * @pasid: pasid to use |
7fc48e59 | 2937 | * |
b236fa1d FK |
2938 | * This only works on GFX VMs that don't have any BOs added and no |
2939 | * page tables allocated yet. | |
2940 | * | |
2941 | * Changes the following VM parameters: | |
2942 | * - use_cpu_for_update | |
2943 | * - pte_supports_ats | |
2944 | * - pasid (old PASID is released, because compute manages its own PASIDs) | |
2945 | * | |
2946 | * Reinitializes the page directory to reflect the changed ATS | |
b5d21aac | 2947 | * setting. |
b236fa1d | 2948 | * |
7fc48e59 AG |
2949 | * Returns: |
2950 | * 0 for success, -errno for errors. | |
b236fa1d | 2951 | */ |
fc39d903 | 2952 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
c7b6bac9 | 2953 | u32 pasid) |
b236fa1d | 2954 | { |
741deade | 2955 | bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); |
b236fa1d FK |
2956 | int r; |
2957 | ||
2958 | r = amdgpu_bo_reserve(vm->root.base.bo, true); | |
2959 | if (r) | |
2960 | return r; | |
2961 | ||
2962 | /* Sanity checks */ | |
3680624e TH |
2963 | r = amdgpu_vm_check_clean_reserved(adev, vm); |
2964 | if (r) | |
1685b01a | 2965 | goto unreserve_bo; |
1685b01a OZ |
2966 | |
2967 | if (pasid) { | |
2968 | unsigned long flags; | |
2969 | ||
2970 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2971 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2972 | GFP_ATOMIC); | |
2973 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2974 | ||
2975 | if (r == -ENOSPC) | |
2976 | goto unreserve_bo; | |
2977 | r = 0; | |
b236fa1d FK |
2978 | } |
2979 | ||
2980 | /* Check if PD needs to be reinitialized and do it before | |
2981 | * changing any other state, in case it fails. | |
2982 | */ | |
2983 | if (pte_support_ats != vm->pte_support_ats) { | |
780637cb | 2984 | vm->pte_support_ats = pte_support_ats; |
0f6064d6 | 2985 | r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false); |
b236fa1d | 2986 | if (r) |
1685b01a | 2987 | goto free_idr; |
b236fa1d FK |
2988 | } |
2989 | ||
2990 | /* Update VM state */ | |
2991 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
2992 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
b236fa1d FK |
2993 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2994 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
fc39d903 CK |
2995 | WARN_ONCE((vm->use_cpu_for_update && |
2996 | !amdgpu_gmc_vram_full_visible(&adev->gmc)), | |
b236fa1d FK |
2997 | "CPU update of VM recommended only for large BAR system\n"); |
2998 | ||
90ca78de FK |
2999 | if (vm->use_cpu_for_update) { |
3000 | /* Sync with last SDMA update/clear before switching to CPU */ | |
3001 | r = amdgpu_bo_sync_wait(vm->root.base.bo, | |
3002 | AMDGPU_FENCE_OWNER_UNDEFINED, true); | |
3003 | if (r) | |
3004 | goto free_idr; | |
3005 | ||
108b4d92 | 3006 | vm->update_funcs = &amdgpu_vm_cpu_funcs; |
90ca78de | 3007 | } else { |
108b4d92 | 3008 | vm->update_funcs = &amdgpu_vm_sdma_funcs; |
90ca78de | 3009 | } |
108b4d92 GB |
3010 | dma_fence_put(vm->last_update); |
3011 | vm->last_update = NULL; | |
f43ef951 | 3012 | vm->is_compute_context = true; |
108b4d92 | 3013 | |
b236fa1d FK |
3014 | if (vm->pasid) { |
3015 | unsigned long flags; | |
3016 | ||
3017 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3018 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3019 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3020 | ||
1685b01a OZ |
3021 | /* Free the original amdgpu allocated pasid |
3022 | * Will be replaced with kfd allocated pasid | |
3023 | */ | |
3024 | amdgpu_pasid_free(vm->pasid); | |
b236fa1d FK |
3025 | vm->pasid = 0; |
3026 | } | |
3027 | ||
b5d21aac SL |
3028 | /* Free the shadow bo for compute VM */ |
3029 | amdgpu_bo_unref(&vm->root.base.bo->shadow); | |
3030 | ||
1685b01a OZ |
3031 | if (pasid) |
3032 | vm->pasid = pasid; | |
3033 | ||
3034 | goto unreserve_bo; | |
3035 | ||
3036 | free_idr: | |
3037 | if (pasid) { | |
3038 | unsigned long flags; | |
3039 | ||
3040 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3041 | idr_remove(&adev->vm_manager.pasid_idr, pasid); | |
3042 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3043 | } | |
3044 | unreserve_bo: | |
b236fa1d FK |
3045 | amdgpu_bo_unreserve(vm->root.base.bo); |
3046 | return r; | |
3047 | } | |
3048 | ||
bf47afba OZ |
3049 | /** |
3050 | * amdgpu_vm_release_compute - release a compute vm | |
3051 | * @adev: amdgpu_device pointer | |
3052 | * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute | |
3053 | * | |
3054 | * This is a correspondant of amdgpu_vm_make_compute. It decouples compute | |
3055 | * pasid from vm. Compute should stop use of vm after this call. | |
3056 | */ | |
3057 | void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
3058 | { | |
3059 | if (vm->pasid) { | |
3060 | unsigned long flags; | |
3061 | ||
3062 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3063 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3064 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3065 | } | |
3066 | vm->pasid = 0; | |
f43ef951 | 3067 | vm->is_compute_context = false; |
bf47afba OZ |
3068 | } |
3069 | ||
d38ceaf9 AD |
3070 | /** |
3071 | * amdgpu_vm_fini - tear down a vm instance | |
3072 | * | |
3073 | * @adev: amdgpu_device pointer | |
3074 | * @vm: requested vm | |
3075 | * | |
8843dbbb | 3076 | * Tear down @vm. |
d38ceaf9 AD |
3077 | * Unbind the VM and remove all bos from the vm bo list |
3078 | */ | |
3079 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
3080 | { | |
3081 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
132f34e4 | 3082 | bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt; |
2642cf11 | 3083 | struct amdgpu_bo *root; |
b65709a9 | 3084 | int i; |
d38ceaf9 | 3085 | |
ede0dd86 FK |
3086 | amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm); |
3087 | ||
b65709a9 CK |
3088 | root = amdgpu_bo_ref(vm->root.base.bo); |
3089 | amdgpu_bo_reserve(root, true); | |
02208441 FK |
3090 | if (vm->pasid) { |
3091 | unsigned long flags; | |
3092 | ||
3093 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3094 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3095 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
b65709a9 | 3096 | vm->pasid = 0; |
02208441 FK |
3097 | } |
3098 | ||
9c466bcb CK |
3099 | dma_fence_wait(vm->last_unlocked, false); |
3100 | dma_fence_put(vm->last_unlocked); | |
90b69cdc | 3101 | |
ee8bcc23 PP |
3102 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { |
3103 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { | |
3104 | amdgpu_vm_prt_fini(adev, vm); | |
3105 | prt_fini_needed = false; | |
3106 | } | |
3107 | ||
3108 | list_del(&mapping->list); | |
3109 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); | |
3110 | } | |
3111 | ||
b65709a9 CK |
3112 | amdgpu_vm_free_pts(adev, vm, NULL); |
3113 | amdgpu_bo_unreserve(root); | |
3114 | amdgpu_bo_unref(&root); | |
3115 | WARN_ON(vm->root.base.bo); | |
3116 | ||
eaad0c3a | 3117 | drm_sched_entity_destroy(&vm->immediate); |
a2cf3247 | 3118 | drm_sched_entity_destroy(&vm->delayed); |
2bd9ccfa | 3119 | |
f808c13f | 3120 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
d38ceaf9 AD |
3121 | dev_err(adev->dev, "still active bo inside vm\n"); |
3122 | } | |
f808c13f DB |
3123 | rbtree_postorder_for_each_entry_safe(mapping, tmp, |
3124 | &vm->va.rb_root, rb) { | |
0af5c656 CK |
3125 | /* Don't remove the mapping here, we don't want to trigger a |
3126 | * rebalance and the tree is about to be destroyed anyway. | |
3127 | */ | |
d38ceaf9 | 3128 | list_del(&mapping->list); |
d38ceaf9 AD |
3129 | kfree(mapping); |
3130 | } | |
d38ceaf9 | 3131 | |
d5884513 | 3132 | dma_fence_put(vm->last_update); |
1e9ef26f | 3133 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
620f774f | 3134 | amdgpu_vmid_free_reserved(adev, vm, i); |
d38ceaf9 | 3135 | } |
ea89f8c9 | 3136 | |
a9a78b32 CK |
3137 | /** |
3138 | * amdgpu_vm_manager_init - init the VM manager | |
3139 | * | |
3140 | * @adev: amdgpu_device pointer | |
3141 | * | |
3142 | * Initialize the VM manager structures | |
3143 | */ | |
3144 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
3145 | { | |
620f774f | 3146 | unsigned i; |
a9a78b32 | 3147 | |
620f774f | 3148 | amdgpu_vmid_mgr_init(adev); |
2d55e45a | 3149 | |
f54d1867 CW |
3150 | adev->vm_manager.fence_context = |
3151 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
3152 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
3153 | adev->vm_manager.seqno[i] = 0; | |
3154 | ||
284710fa | 3155 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 3156 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
3157 | |
3158 | /* If not overridden by the user, by default, only in large BAR systems | |
3159 | * Compute VM tables will be updated by CPU | |
3160 | */ | |
3161 | #ifdef CONFIG_X86_64 | |
3162 | if (amdgpu_vm_update_mode == -1) { | |
c8c5e569 | 3163 | if (amdgpu_gmc_vram_full_visible(&adev->gmc)) |
9a4b7d4c HK |
3164 | adev->vm_manager.vm_update_mode = |
3165 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
3166 | else | |
3167 | adev->vm_manager.vm_update_mode = 0; | |
3168 | } else | |
3169 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
3170 | #else | |
3171 | adev->vm_manager.vm_update_mode = 0; | |
3172 | #endif | |
3173 | ||
02208441 FK |
3174 | idr_init(&adev->vm_manager.pasid_idr); |
3175 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
a9a78b32 CK |
3176 | } |
3177 | ||
ea89f8c9 CK |
3178 | /** |
3179 | * amdgpu_vm_manager_fini - cleanup VM manager | |
3180 | * | |
3181 | * @adev: amdgpu_device pointer | |
3182 | * | |
3183 | * Cleanup the VM manager and free resources. | |
3184 | */ | |
3185 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
3186 | { | |
02208441 FK |
3187 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); |
3188 | idr_destroy(&adev->vm_manager.pasid_idr); | |
3189 | ||
620f774f | 3190 | amdgpu_vmid_mgr_fini(adev); |
ea89f8c9 | 3191 | } |
cfbcacf4 | 3192 | |
7fc48e59 AG |
3193 | /** |
3194 | * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs. | |
3195 | * | |
3196 | * @dev: drm device pointer | |
3197 | * @data: drm_amdgpu_vm | |
3198 | * @filp: drm file pointer | |
3199 | * | |
3200 | * Returns: | |
3201 | * 0 for success, -errno for errors. | |
3202 | */ | |
cfbcacf4 CZ |
3203 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
3204 | { | |
3205 | union drm_amdgpu_vm *args = data; | |
1348969a | 3206 | struct amdgpu_device *adev = drm_to_adev(dev); |
1e9ef26f | 3207 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
5e208eb6 | 3208 | long timeout = msecs_to_jiffies(2000); |
1e9ef26f | 3209 | int r; |
cfbcacf4 CZ |
3210 | |
3211 | switch (args->in.op) { | |
3212 | case AMDGPU_VM_OP_RESERVE_VMID: | |
fc39d903 CK |
3213 | /* We only have requirement to reserve vmid from gfxhub */ |
3214 | r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, | |
3215 | AMDGPU_GFXHUB_0); | |
1e9ef26f CZ |
3216 | if (r) |
3217 | return r; | |
3218 | break; | |
cfbcacf4 | 3219 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
5e208eb6 JH |
3220 | if (amdgpu_sriov_runtime(adev)) |
3221 | timeout = 8 * timeout; | |
3222 | ||
3223 | /* Wait vm idle to make sure the vmid set in SPM_VMID is | |
3224 | * not referenced anymore. | |
3225 | */ | |
3226 | r = amdgpu_bo_reserve(fpriv->vm.root.base.bo, true); | |
3227 | if (r) | |
3228 | return r; | |
3229 | ||
3230 | r = amdgpu_vm_wait_idle(&fpriv->vm, timeout); | |
3231 | if (r < 0) | |
3232 | return r; | |
3233 | ||
3234 | amdgpu_bo_unreserve(fpriv->vm.root.base.bo); | |
a2d15ed7 | 3235 | amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0); |
cfbcacf4 CZ |
3236 | break; |
3237 | default: | |
3238 | return -EINVAL; | |
3239 | } | |
3240 | ||
3241 | return 0; | |
3242 | } | |
2aa37bf5 AG |
3243 | |
3244 | /** | |
3245 | * amdgpu_vm_get_task_info - Extracts task info for a PASID. | |
3246 | * | |
989edc69 | 3247 | * @adev: drm device pointer |
2aa37bf5 AG |
3248 | * @pasid: PASID identifier for VM |
3249 | * @task_info: task_info to fill. | |
3250 | */ | |
c7b6bac9 | 3251 | void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid, |
2aa37bf5 AG |
3252 | struct amdgpu_task_info *task_info) |
3253 | { | |
3254 | struct amdgpu_vm *vm; | |
0a5f49cb | 3255 | unsigned long flags; |
2aa37bf5 | 3256 | |
0a5f49cb | 3257 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); |
2aa37bf5 AG |
3258 | |
3259 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3260 | if (vm) | |
3261 | *task_info = vm->task_info; | |
3262 | ||
0a5f49cb | 3263 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); |
2aa37bf5 AG |
3264 | } |
3265 | ||
3266 | /** | |
3267 | * amdgpu_vm_set_task_info - Sets VMs task info. | |
3268 | * | |
3269 | * @vm: vm for which to set the info | |
3270 | */ | |
3271 | void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) | |
3272 | { | |
fc39d903 CK |
3273 | if (vm->task_info.pid) |
3274 | return; | |
2aa37bf5 | 3275 | |
fc39d903 CK |
3276 | vm->task_info.pid = current->pid; |
3277 | get_task_comm(vm->task_info.task_name, current); | |
3278 | ||
3279 | if (current->group_leader->mm != current->mm) | |
3280 | return; | |
3281 | ||
3282 | vm->task_info.tgid = current->group_leader->pid; | |
3283 | get_task_comm(vm->task_info.process_name, current->group_leader); | |
2aa37bf5 | 3284 | } |
ec671737 CK |
3285 | |
3286 | /** | |
3287 | * amdgpu_vm_handle_fault - graceful handling of VM faults. | |
3288 | * @adev: amdgpu device pointer | |
3289 | * @pasid: PASID of the VM | |
3290 | * @addr: Address of the fault | |
3291 | * | |
3292 | * Try to gracefully handle a VM fault. Return true if the fault was handled and | |
3293 | * shouldn't be reported any more. | |
3294 | */ | |
c7b6bac9 | 3295 | bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, |
ec671737 CK |
3296 | uint64_t addr) |
3297 | { | |
3298 | struct amdgpu_bo *root; | |
3299 | uint64_t value, flags; | |
3300 | struct amdgpu_vm *vm; | |
3301 | long r; | |
3302 | ||
3303 | spin_lock(&adev->vm_manager.pasid_lock); | |
3304 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3305 | if (vm) | |
3306 | root = amdgpu_bo_ref(vm->root.base.bo); | |
3307 | else | |
3308 | root = NULL; | |
3309 | spin_unlock(&adev->vm_manager.pasid_lock); | |
3310 | ||
3311 | if (!root) | |
3312 | return false; | |
3313 | ||
3314 | r = amdgpu_bo_reserve(root, true); | |
3315 | if (r) | |
3316 | goto error_unref; | |
3317 | ||
3318 | /* Double check that the VM still exists */ | |
3319 | spin_lock(&adev->vm_manager.pasid_lock); | |
3320 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3321 | if (vm && vm->root.base.bo != root) | |
3322 | vm = NULL; | |
3323 | spin_unlock(&adev->vm_manager.pasid_lock); | |
3324 | if (!vm) | |
3325 | goto error_unlock; | |
3326 | ||
3327 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
3328 | flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED | | |
3329 | AMDGPU_PTE_SYSTEM; | |
3330 | ||
b4672c8a AS |
3331 | if (vm->is_compute_context) { |
3332 | /* Intentionally setting invalid PTE flag | |
3333 | * combination to force a no-retry-fault | |
3334 | */ | |
3335 | flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | | |
3336 | AMDGPU_PTE_TF; | |
3337 | value = 0; | |
3338 | ||
3339 | } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) { | |
ec671737 CK |
3340 | /* Redirect the access to the dummy page */ |
3341 | value = adev->dummy_page_addr; | |
3342 | flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE | | |
3343 | AMDGPU_PTE_WRITEABLE; | |
b4672c8a | 3344 | |
ec671737 CK |
3345 | } else { |
3346 | /* Let the hw retry silently on the PTE */ | |
3347 | value = 0; | |
3348 | } | |
3349 | ||
a39f2a8d | 3350 | r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr, |
19201c07 | 3351 | addr, flags, value, NULL, NULL, |
a39f2a8d | 3352 | NULL); |
ec671737 CK |
3353 | if (r) |
3354 | goto error_unlock; | |
3355 | ||
3356 | r = amdgpu_vm_update_pdes(adev, vm, true); | |
3357 | ||
3358 | error_unlock: | |
3359 | amdgpu_bo_unreserve(root); | |
3360 | if (r < 0) | |
3361 | DRM_ERROR("Can't handle page fault (%ld)\n", r); | |
3362 | ||
3363 | error_unref: | |
3364 | amdgpu_bo_unref(&root); | |
3365 | ||
3366 | return false; | |
3367 | } | |
ff72bc40 MBP |
3368 | |
3369 | #if defined(CONFIG_DEBUG_FS) | |
3370 | /** | |
3371 | * amdgpu_debugfs_vm_bo_info - print BO info for the VM | |
3372 | * | |
3373 | * @vm: Requested VM for printing BO info | |
3374 | * @m: debugfs file | |
3375 | * | |
3376 | * Print BO information in debugfs file for the VM | |
3377 | */ | |
3378 | void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) | |
3379 | { | |
3380 | struct amdgpu_bo_va *bo_va, *tmp; | |
3381 | u64 total_idle = 0; | |
3382 | u64 total_evicted = 0; | |
3383 | u64 total_relocated = 0; | |
3384 | u64 total_moved = 0; | |
3385 | u64 total_invalidated = 0; | |
0e601a04 | 3386 | u64 total_done = 0; |
ff72bc40 MBP |
3387 | unsigned int total_idle_objs = 0; |
3388 | unsigned int total_evicted_objs = 0; | |
3389 | unsigned int total_relocated_objs = 0; | |
3390 | unsigned int total_moved_objs = 0; | |
3391 | unsigned int total_invalidated_objs = 0; | |
0e601a04 | 3392 | unsigned int total_done_objs = 0; |
ff72bc40 MBP |
3393 | unsigned int id = 0; |
3394 | ||
3395 | seq_puts(m, "\tIdle BOs:\n"); | |
3396 | list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) { | |
3397 | if (!bo_va->base.bo) | |
3398 | continue; | |
3399 | total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m); | |
3400 | } | |
3401 | total_idle_objs = id; | |
3402 | id = 0; | |
3403 | ||
3404 | seq_puts(m, "\tEvicted BOs:\n"); | |
3405 | list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) { | |
3406 | if (!bo_va->base.bo) | |
3407 | continue; | |
3408 | total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m); | |
3409 | } | |
3410 | total_evicted_objs = id; | |
3411 | id = 0; | |
3412 | ||
3413 | seq_puts(m, "\tRelocated BOs:\n"); | |
3414 | list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) { | |
3415 | if (!bo_va->base.bo) | |
3416 | continue; | |
3417 | total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m); | |
3418 | } | |
3419 | total_relocated_objs = id; | |
3420 | id = 0; | |
3421 | ||
3422 | seq_puts(m, "\tMoved BOs:\n"); | |
3423 | list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { | |
3424 | if (!bo_va->base.bo) | |
3425 | continue; | |
3426 | total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m); | |
3427 | } | |
3428 | total_moved_objs = id; | |
3429 | id = 0; | |
3430 | ||
3431 | seq_puts(m, "\tInvalidated BOs:\n"); | |
3432 | spin_lock(&vm->invalidated_lock); | |
3433 | list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) { | |
3434 | if (!bo_va->base.bo) | |
3435 | continue; | |
3436 | total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m); | |
3437 | } | |
ff72bc40 | 3438 | total_invalidated_objs = id; |
0e601a04 MBP |
3439 | id = 0; |
3440 | ||
3441 | seq_puts(m, "\tDone BOs:\n"); | |
3442 | list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) { | |
3443 | if (!bo_va->base.bo) | |
3444 | continue; | |
3445 | total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m); | |
3446 | } | |
3447 | spin_unlock(&vm->invalidated_lock); | |
3448 | total_done_objs = id; | |
ff72bc40 MBP |
3449 | |
3450 | seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle, | |
3451 | total_idle_objs); | |
3452 | seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted, | |
3453 | total_evicted_objs); | |
3454 | seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated, | |
3455 | total_relocated_objs); | |
3456 | seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved, | |
3457 | total_moved_objs); | |
3458 | seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated, | |
3459 | total_invalidated_objs); | |
0e601a04 MBP |
3460 | seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done, |
3461 | total_done_objs); | |
ff72bc40 MBP |
3462 | } |
3463 | #endif |