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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
02208441 | 30 | #include <linux/idr.h> |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "amdgpu_trace.h" | |
35 | ||
02208441 FK |
36 | /* |
37 | * PASID manager | |
38 | * | |
39 | * PASIDs are global address space identifiers that can be shared | |
40 | * between the GPU, an IOMMU and the driver. VMs on different devices | |
41 | * may use the same PASID if they share the same address | |
42 | * space. Therefore PASIDs are allocated using a global IDA. VMs are | |
43 | * looked up from the PASID per amdgpu_device. | |
44 | */ | |
45 | static DEFINE_IDA(amdgpu_vm_pasid_ida); | |
46 | ||
47 | /** | |
48 | * amdgpu_vm_alloc_pasid - Allocate a PASID | |
49 | * @bits: Maximum width of the PASID in bits, must be at least 1 | |
50 | * | |
51 | * Allocates a PASID of the given width while keeping smaller PASIDs | |
52 | * available if possible. | |
53 | * | |
54 | * Returns a positive integer on success. Returns %-EINVAL if bits==0. | |
55 | * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on | |
56 | * memory allocation failure. | |
57 | */ | |
58 | int amdgpu_vm_alloc_pasid(unsigned int bits) | |
59 | { | |
60 | int pasid = -EINVAL; | |
61 | ||
62 | for (bits = min(bits, 31U); bits > 0; bits--) { | |
63 | pasid = ida_simple_get(&amdgpu_vm_pasid_ida, | |
64 | 1U << (bits - 1), 1U << bits, | |
65 | GFP_KERNEL); | |
66 | if (pasid != -ENOSPC) | |
67 | break; | |
68 | } | |
69 | ||
70 | return pasid; | |
71 | } | |
72 | ||
73 | /** | |
74 | * amdgpu_vm_free_pasid - Free a PASID | |
75 | * @pasid: PASID to free | |
76 | */ | |
77 | void amdgpu_vm_free_pasid(unsigned int pasid) | |
78 | { | |
79 | ida_simple_remove(&amdgpu_vm_pasid_ida, pasid); | |
80 | } | |
81 | ||
d38ceaf9 AD |
82 | /* |
83 | * GPUVM | |
84 | * GPUVM is similar to the legacy gart on older asics, however | |
85 | * rather than there being a single global gart table | |
86 | * for the entire GPU, there are multiple VM page tables active | |
87 | * at any given time. The VM page tables can contain a mix | |
88 | * vram pages and system memory pages and system memory pages | |
89 | * can be mapped as snooped (cached system pages) or unsnooped | |
90 | * (uncached system pages). | |
91 | * Each VM has an ID associated with it and there is a page table | |
92 | * associated with each VMID. When execting a command buffer, | |
93 | * the kernel tells the the ring what VMID to use for that command | |
94 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
95 | * The userspace drivers maintain their own address space and the kernel | |
96 | * sets up their pages tables accordingly when they submit their | |
97 | * command buffers and a VMID is assigned. | |
98 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
99 | * SI supports 16. | |
100 | */ | |
101 | ||
a9f87f64 CK |
102 | #define START(node) ((node)->start) |
103 | #define LAST(node) ((node)->last) | |
104 | ||
105 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
106 | START, LAST, static, amdgpu_vm_it) | |
107 | ||
108 | #undef START | |
109 | #undef LAST | |
110 | ||
f4833c4f HK |
111 | /* Local structure. Encapsulate some VM table update parameters to reduce |
112 | * the number of function parameters | |
113 | */ | |
29efc4f5 | 114 | struct amdgpu_pte_update_params { |
27c5f36f CK |
115 | /* amdgpu device we do this update for */ |
116 | struct amdgpu_device *adev; | |
49ac8a24 CK |
117 | /* optional amdgpu_vm we do this update for */ |
118 | struct amdgpu_vm *vm; | |
f4833c4f HK |
119 | /* address where to copy page table entries from */ |
120 | uint64_t src; | |
f4833c4f HK |
121 | /* indirect buffer to fill with commands */ |
122 | struct amdgpu_ib *ib; | |
afef8b8f CK |
123 | /* Function which actually does the update */ |
124 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
125 | uint64_t addr, unsigned count, uint32_t incr, | |
6b777607 | 126 | uint64_t flags); |
b4d42511 HK |
127 | /* The next two are used during VM update by CPU |
128 | * DMA addresses to use for mapping | |
129 | * Kernel pointer of PD/PT BO that needs to be updated | |
130 | */ | |
131 | dma_addr_t *pages_addr; | |
132 | void *kptr; | |
f4833c4f HK |
133 | }; |
134 | ||
284710fa CK |
135 | /* Helper to disable partial resident texture feature from a fence callback */ |
136 | struct amdgpu_prt_cb { | |
137 | struct amdgpu_device *adev; | |
138 | struct dma_fence_cb cb; | |
139 | }; | |
140 | ||
50783147 CK |
141 | /** |
142 | * amdgpu_vm_level_shift - return the addr shift for each level | |
143 | * | |
144 | * @adev: amdgpu_device pointer | |
145 | * | |
146 | * Returns the number of bits the pfn needs to be right shifted for a level. | |
147 | */ | |
148 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
149 | unsigned level) | |
150 | { | |
151 | if (level != adev->vm_manager.num_level) | |
152 | return 9 * (adev->vm_manager.num_level - level - 1) + | |
153 | adev->vm_manager.block_size; | |
154 | else | |
155 | /* For the page tables on the leaves */ | |
156 | return 0; | |
157 | } | |
158 | ||
d38ceaf9 | 159 | /** |
72a7ec5c | 160 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
161 | * |
162 | * @adev: amdgpu_device pointer | |
163 | * | |
72a7ec5c | 164 | * Calculate the number of entries in a page directory or page table. |
d38ceaf9 | 165 | */ |
72a7ec5c CK |
166 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
167 | unsigned level) | |
d38ceaf9 | 168 | { |
0410c5e5 CK |
169 | unsigned shift = amdgpu_vm_level_shift(adev, 0); |
170 | ||
72a7ec5c CK |
171 | if (level == 0) |
172 | /* For the root directory */ | |
0410c5e5 CK |
173 | return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; |
174 | else if (level != adev->vm_manager.num_level) | |
175 | /* Everything in between */ | |
176 | return 512; | |
177 | else | |
72a7ec5c | 178 | /* For the page tables on the leaves */ |
36b32a68 | 179 | return AMDGPU_VM_PTE_COUNT(adev); |
d38ceaf9 AD |
180 | } |
181 | ||
182 | /** | |
72a7ec5c | 183 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
184 | * |
185 | * @adev: amdgpu_device pointer | |
186 | * | |
72a7ec5c | 187 | * Calculate the size of the BO for a page directory or page table in bytes. |
d38ceaf9 | 188 | */ |
72a7ec5c | 189 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 190 | { |
72a7ec5c | 191 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
192 | } |
193 | ||
194 | /** | |
56467ebf | 195 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
196 | * |
197 | * @vm: vm providing the BOs | |
3c0eea6c | 198 | * @validated: head of validation list |
56467ebf | 199 | * @entry: entry to add |
d38ceaf9 AD |
200 | * |
201 | * Add the page directory to the list of BOs to | |
56467ebf | 202 | * validate for command submission. |
d38ceaf9 | 203 | */ |
56467ebf CK |
204 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
205 | struct list_head *validated, | |
206 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 207 | { |
3f3333f8 | 208 | entry->robj = vm->root.base.bo; |
56467ebf | 209 | entry->priority = 0; |
67003a15 | 210 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 211 | entry->tv.shared = true; |
2f568dbd | 212 | entry->user_pages = NULL; |
56467ebf CK |
213 | list_add(&entry->tv.head, validated); |
214 | } | |
d38ceaf9 | 215 | |
670fecc8 | 216 | /** |
f7da30d9 | 217 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
670fecc8 | 218 | * |
5a712a87 | 219 | * @adev: amdgpu device pointer |
56467ebf | 220 | * @vm: vm providing the BOs |
670fecc8 CK |
221 | * @validate: callback to do the validation |
222 | * @param: parameter for the validation callback | |
223 | * | |
224 | * Validate the page table BOs on command submission if neccessary. | |
225 | */ | |
f7da30d9 CK |
226 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
227 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
228 | void *param) | |
670fecc8 | 229 | { |
3f3333f8 | 230 | struct ttm_bo_global *glob = adev->mman.bdev.glob; |
670fecc8 CK |
231 | int r; |
232 | ||
3f3333f8 CK |
233 | spin_lock(&vm->status_lock); |
234 | while (!list_empty(&vm->evicted)) { | |
235 | struct amdgpu_vm_bo_base *bo_base; | |
236 | struct amdgpu_bo *bo; | |
670fecc8 | 237 | |
3f3333f8 CK |
238 | bo_base = list_first_entry(&vm->evicted, |
239 | struct amdgpu_vm_bo_base, | |
240 | vm_status); | |
241 | spin_unlock(&vm->status_lock); | |
670fecc8 | 242 | |
3f3333f8 CK |
243 | bo = bo_base->bo; |
244 | BUG_ON(!bo); | |
245 | if (bo->parent) { | |
246 | r = validate(param, bo); | |
247 | if (r) | |
248 | return r; | |
670fecc8 | 249 | |
3f3333f8 CK |
250 | spin_lock(&glob->lru_lock); |
251 | ttm_bo_move_to_lru_tail(&bo->tbo); | |
252 | if (bo->shadow) | |
253 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo); | |
254 | spin_unlock(&glob->lru_lock); | |
255 | } | |
670fecc8 | 256 | |
73fb16e7 CK |
257 | if (bo->tbo.type == ttm_bo_type_kernel && |
258 | vm->use_cpu_for_update) { | |
3f3333f8 CK |
259 | r = amdgpu_bo_kmap(bo, NULL); |
260 | if (r) | |
261 | return r; | |
262 | } | |
b6369225 | 263 | |
3f3333f8 | 264 | spin_lock(&vm->status_lock); |
73fb16e7 CK |
265 | if (bo->tbo.type != ttm_bo_type_kernel) |
266 | list_move(&bo_base->vm_status, &vm->moved); | |
267 | else | |
268 | list_move(&bo_base->vm_status, &vm->relocated); | |
670fecc8 | 269 | } |
3f3333f8 | 270 | spin_unlock(&vm->status_lock); |
670fecc8 | 271 | |
34d7be5d | 272 | return 0; |
670fecc8 CK |
273 | } |
274 | ||
56467ebf | 275 | /** |
34d7be5d | 276 | * amdgpu_vm_ready - check VM is ready for updates |
56467ebf | 277 | * |
34d7be5d | 278 | * @vm: VM to check |
d38ceaf9 | 279 | * |
34d7be5d | 280 | * Check if all VM PDs/PTs are ready for updates |
d38ceaf9 | 281 | */ |
3f3333f8 | 282 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
d38ceaf9 | 283 | { |
3f3333f8 | 284 | bool ready; |
d38ceaf9 | 285 | |
3f3333f8 CK |
286 | spin_lock(&vm->status_lock); |
287 | ready = list_empty(&vm->evicted); | |
288 | spin_unlock(&vm->status_lock); | |
5a712a87 | 289 | |
3f3333f8 | 290 | return ready; |
d711e139 CK |
291 | } |
292 | ||
293 | /** | |
f566ceb1 CK |
294 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels |
295 | * | |
296 | * @adev: amdgpu_device pointer | |
297 | * @vm: requested vm | |
298 | * @saddr: start of the address range | |
299 | * @eaddr: end of the address range | |
300 | * | |
301 | * Make sure the page directories and page tables are allocated | |
302 | */ | |
303 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
304 | struct amdgpu_vm *vm, | |
305 | struct amdgpu_vm_pt *parent, | |
306 | uint64_t saddr, uint64_t eaddr, | |
307 | unsigned level) | |
308 | { | |
50783147 | 309 | unsigned shift = amdgpu_vm_level_shift(adev, level); |
f566ceb1 CK |
310 | unsigned pt_idx, from, to; |
311 | int r; | |
3c824172 | 312 | u64 flags; |
51ac7eec | 313 | uint64_t init_value = 0; |
f566ceb1 CK |
314 | |
315 | if (!parent->entries) { | |
316 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
317 | ||
2098105e MH |
318 | parent->entries = kvmalloc_array(num_entries, |
319 | sizeof(struct amdgpu_vm_pt), | |
320 | GFP_KERNEL | __GFP_ZERO); | |
f566ceb1 CK |
321 | if (!parent->entries) |
322 | return -ENOMEM; | |
323 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
324 | } | |
325 | ||
1866bac8 FK |
326 | from = saddr >> shift; |
327 | to = eaddr >> shift; | |
328 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
329 | to >= amdgpu_vm_num_entries(adev, level)) | |
330 | return -EINVAL; | |
f566ceb1 | 331 | |
f566ceb1 | 332 | ++level; |
1866bac8 FK |
333 | saddr = saddr & ((1 << shift) - 1); |
334 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 | 335 | |
3c824172 HK |
336 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
337 | AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
338 | if (vm->use_cpu_for_update) | |
339 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
340 | else | |
341 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
342 | AMDGPU_GEM_CREATE_SHADOW); | |
343 | ||
51ac7eec | 344 | if (vm->pte_support_ats) { |
6d16dac8 | 345 | init_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec YZ |
346 | if (level != adev->vm_manager.num_level - 1) |
347 | init_value |= AMDGPU_PDE_PTE; | |
6d16dac8 | 348 | |
51ac7eec YZ |
349 | } |
350 | ||
f566ceb1 CK |
351 | /* walk over the address space and allocate the page tables */ |
352 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
3f3333f8 | 353 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
f566ceb1 CK |
354 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
355 | struct amdgpu_bo *pt; | |
356 | ||
3f3333f8 | 357 | if (!entry->base.bo) { |
f566ceb1 CK |
358 | r = amdgpu_bo_create(adev, |
359 | amdgpu_vm_bo_size(adev, level), | |
360 | AMDGPU_GPU_PAGE_SIZE, true, | |
361 | AMDGPU_GEM_DOMAIN_VRAM, | |
3c824172 | 362 | flags, |
51ac7eec | 363 | NULL, resv, init_value, &pt); |
f566ceb1 CK |
364 | if (r) |
365 | return r; | |
366 | ||
0a096fb6 CK |
367 | if (vm->use_cpu_for_update) { |
368 | r = amdgpu_bo_kmap(pt, NULL); | |
369 | if (r) { | |
370 | amdgpu_bo_unref(&pt); | |
371 | return r; | |
372 | } | |
373 | } | |
374 | ||
f566ceb1 CK |
375 | /* Keep a reference to the root directory to avoid |
376 | * freeing them up in the wrong order. | |
377 | */ | |
0f2fc435 | 378 | pt->parent = amdgpu_bo_ref(parent->base.bo); |
f566ceb1 | 379 | |
3f3333f8 CK |
380 | entry->base.vm = vm; |
381 | entry->base.bo = pt; | |
382 | list_add_tail(&entry->base.bo_list, &pt->va); | |
ea09729c CK |
383 | spin_lock(&vm->status_lock); |
384 | list_add(&entry->base.vm_status, &vm->relocated); | |
385 | spin_unlock(&vm->status_lock); | |
f566ceb1 CK |
386 | } |
387 | ||
388 | if (level < adev->vm_manager.num_level) { | |
1866bac8 FK |
389 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
390 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
391 | ((1 << shift) - 1); | |
392 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
393 | sub_eaddr, level); | |
f566ceb1 CK |
394 | if (r) |
395 | return r; | |
396 | } | |
397 | } | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
663e4577 CK |
402 | /** |
403 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
404 | * | |
405 | * @adev: amdgpu_device pointer | |
406 | * @vm: VM to allocate page tables for | |
407 | * @saddr: Start address which needs to be allocated | |
408 | * @size: Size from start address we need. | |
409 | * | |
410 | * Make sure the page tables are allocated. | |
411 | */ | |
412 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
413 | struct amdgpu_vm *vm, | |
414 | uint64_t saddr, uint64_t size) | |
415 | { | |
22770e5a | 416 | uint64_t last_pfn; |
663e4577 | 417 | uint64_t eaddr; |
663e4577 CK |
418 | |
419 | /* validate the parameters */ | |
420 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
421 | return -EINVAL; | |
422 | ||
423 | eaddr = saddr + size - 1; | |
424 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
425 | if (last_pfn >= adev->vm_manager.max_pfn) { | |
22770e5a | 426 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", |
663e4577 CK |
427 | last_pfn, adev->vm_manager.max_pfn); |
428 | return -EINVAL; | |
429 | } | |
430 | ||
431 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
432 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
433 | ||
f566ceb1 | 434 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); |
663e4577 CK |
435 | } |
436 | ||
641e9400 CK |
437 | /** |
438 | * amdgpu_vm_had_gpu_reset - check if reset occured since last use | |
439 | * | |
440 | * @adev: amdgpu_device pointer | |
441 | * @id: VMID structure | |
442 | * | |
443 | * Check if GPU reset occured since last use of the VMID. | |
444 | */ | |
445 | static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev, | |
446 | struct amdgpu_vm_id *id) | |
192b7dcb CZ |
447 | { |
448 | return id->current_gpu_reset_count != | |
641e9400 | 449 | atomic_read(&adev->gpu_reset_counter); |
192b7dcb CZ |
450 | } |
451 | ||
7a63eb23 CZ |
452 | static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub) |
453 | { | |
454 | return !!vm->reserved_vmid[vmhub]; | |
455 | } | |
456 | ||
457 | /* idr_mgr->lock must be held */ | |
458 | static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, | |
459 | struct amdgpu_ring *ring, | |
460 | struct amdgpu_sync *sync, | |
461 | struct dma_fence *fence, | |
462 | struct amdgpu_job *job) | |
463 | { | |
464 | struct amdgpu_device *adev = ring->adev; | |
465 | unsigned vmhub = ring->funcs->vmhub; | |
466 | uint64_t fence_context = adev->fence_context + ring->idx; | |
467 | struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub]; | |
468 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
469 | struct dma_fence *updates = sync->last_vm_update; | |
470 | int r = 0; | |
471 | struct dma_fence *flushed, *tmp; | |
6f1ceabb | 472 | bool needs_flush = vm->use_cpu_for_update; |
7a63eb23 CZ |
473 | |
474 | flushed = id->flushed_updates; | |
475 | if ((amdgpu_vm_had_gpu_reset(adev, id)) || | |
476 | (atomic64_read(&id->owner) != vm->client_id) || | |
477 | (job->vm_pd_addr != id->pd_gpu_addr) || | |
478 | (updates && (!flushed || updates->context != flushed->context || | |
479 | dma_fence_is_later(updates, flushed))) || | |
480 | (!id->last_flush || (id->last_flush->context != fence_context && | |
481 | !dma_fence_is_signaled(id->last_flush)))) { | |
482 | needs_flush = true; | |
483 | /* to prevent one context starved by another context */ | |
484 | id->pd_gpu_addr = 0; | |
485 | tmp = amdgpu_sync_peek_fence(&id->active, ring); | |
486 | if (tmp) { | |
cebb52b7 | 487 | r = amdgpu_sync_fence(adev, sync, tmp, false); |
7a63eb23 CZ |
488 | return r; |
489 | } | |
490 | } | |
491 | ||
492 | /* Good we can use this VMID. Remember this submission as | |
493 | * user of the VMID. | |
494 | */ | |
cebb52b7 | 495 | r = amdgpu_sync_fence(ring->adev, &id->active, fence, false); |
7a63eb23 CZ |
496 | if (r) |
497 | goto out; | |
498 | ||
499 | if (updates && (!flushed || updates->context != flushed->context || | |
500 | dma_fence_is_later(updates, flushed))) { | |
501 | dma_fence_put(id->flushed_updates); | |
502 | id->flushed_updates = dma_fence_get(updates); | |
503 | } | |
504 | id->pd_gpu_addr = job->vm_pd_addr; | |
7a63eb23 CZ |
505 | atomic64_set(&id->owner, vm->client_id); |
506 | job->vm_needs_flush = needs_flush; | |
507 | if (needs_flush) { | |
508 | dma_fence_put(id->last_flush); | |
509 | id->last_flush = NULL; | |
510 | } | |
511 | job->vm_id = id - id_mgr->ids; | |
512 | trace_amdgpu_vm_grab_id(vm, ring, job); | |
513 | out: | |
514 | return r; | |
515 | } | |
516 | ||
d38ceaf9 AD |
517 | /** |
518 | * amdgpu_vm_grab_id - allocate the next free VMID | |
519 | * | |
d38ceaf9 | 520 | * @vm: vm to allocate id for |
7f8a5290 CK |
521 | * @ring: ring we want to submit job to |
522 | * @sync: sync object where we add dependencies | |
94dd0a4a | 523 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 524 | * |
7f8a5290 | 525 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 526 | */ |
7f8a5290 | 527 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
f54d1867 | 528 | struct amdgpu_sync *sync, struct dma_fence *fence, |
fd53be30 | 529 | struct amdgpu_job *job) |
d38ceaf9 | 530 | { |
d38ceaf9 | 531 | struct amdgpu_device *adev = ring->adev; |
2e819849 | 532 | unsigned vmhub = ring->funcs->vmhub; |
7645670d | 533 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
090b767e | 534 | uint64_t fence_context = adev->fence_context + ring->idx; |
f54d1867 | 535 | struct dma_fence *updates = sync->last_vm_update; |
8d76001e | 536 | struct amdgpu_vm_id *id, *idle; |
f54d1867 | 537 | struct dma_fence **fences; |
1fbb2e92 CK |
538 | unsigned i; |
539 | int r = 0; | |
540 | ||
7a63eb23 CZ |
541 | mutex_lock(&id_mgr->lock); |
542 | if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) { | |
543 | r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job); | |
544 | mutex_unlock(&id_mgr->lock); | |
545 | return r; | |
546 | } | |
7645670d | 547 | fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); |
7a63eb23 CZ |
548 | if (!fences) { |
549 | mutex_unlock(&id_mgr->lock); | |
1fbb2e92 | 550 | return -ENOMEM; |
7a63eb23 | 551 | } |
36fd7c5c | 552 | /* Check if we have an idle VMID */ |
1fbb2e92 | 553 | i = 0; |
7645670d | 554 | list_for_each_entry(idle, &id_mgr->ids_lru, list) { |
1fbb2e92 CK |
555 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
556 | if (!fences[i]) | |
36fd7c5c | 557 | break; |
1fbb2e92 | 558 | ++i; |
36fd7c5c CK |
559 | } |
560 | ||
1fbb2e92 | 561 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
7645670d | 562 | if (&idle->list == &id_mgr->ids_lru) { |
1fbb2e92 CK |
563 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
564 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
f54d1867 | 565 | struct dma_fence_array *array; |
1fbb2e92 CK |
566 | unsigned j; |
567 | ||
568 | for (j = 0; j < i; ++j) | |
f54d1867 | 569 | dma_fence_get(fences[j]); |
1fbb2e92 | 570 | |
f54d1867 | 571 | array = dma_fence_array_create(i, fences, fence_context, |
1fbb2e92 CK |
572 | seqno, true); |
573 | if (!array) { | |
574 | for (j = 0; j < i; ++j) | |
f54d1867 | 575 | dma_fence_put(fences[j]); |
1fbb2e92 CK |
576 | kfree(fences); |
577 | r = -ENOMEM; | |
578 | goto error; | |
579 | } | |
580 | ||
581 | ||
cebb52b7 | 582 | r = amdgpu_sync_fence(ring->adev, sync, &array->base, false); |
f54d1867 | 583 | dma_fence_put(&array->base); |
1fbb2e92 CK |
584 | if (r) |
585 | goto error; | |
586 | ||
7645670d | 587 | mutex_unlock(&id_mgr->lock); |
1fbb2e92 CK |
588 | return 0; |
589 | ||
590 | } | |
591 | kfree(fences); | |
592 | ||
6f1ceabb | 593 | job->vm_needs_flush = vm->use_cpu_for_update; |
1fbb2e92 | 594 | /* Check if we can use a VMID already assigned to this VM */ |
7645670d | 595 | list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) { |
f54d1867 | 596 | struct dma_fence *flushed; |
6f1ceabb | 597 | bool needs_flush = vm->use_cpu_for_update; |
1fbb2e92 | 598 | |
1fbb2e92 | 599 | /* Check all the prerequisites to using this VMID */ |
641e9400 | 600 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
6adb0513 | 601 | continue; |
1fbb2e92 CK |
602 | |
603 | if (atomic64_read(&id->owner) != vm->client_id) | |
604 | continue; | |
605 | ||
fd53be30 | 606 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
607 | continue; |
608 | ||
87c910d8 CK |
609 | if (!id->last_flush || |
610 | (id->last_flush->context != fence_context && | |
611 | !dma_fence_is_signaled(id->last_flush))) | |
612 | needs_flush = true; | |
1fbb2e92 CK |
613 | |
614 | flushed = id->flushed_updates; | |
87c910d8 CK |
615 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) |
616 | needs_flush = true; | |
617 | ||
618 | /* Concurrent flushes are only possible starting with Vega10 */ | |
619 | if (adev->asic_type < CHIP_VEGA10 && needs_flush) | |
1fbb2e92 CK |
620 | continue; |
621 | ||
3dab83be CK |
622 | /* Good we can use this VMID. Remember this submission as |
623 | * user of the VMID. | |
624 | */ | |
cebb52b7 | 625 | r = amdgpu_sync_fence(ring->adev, &id->active, fence, false); |
1fbb2e92 CK |
626 | if (r) |
627 | goto error; | |
8d76001e | 628 | |
87c910d8 CK |
629 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) { |
630 | dma_fence_put(id->flushed_updates); | |
631 | id->flushed_updates = dma_fence_get(updates); | |
632 | } | |
8d76001e | 633 | |
87c910d8 CK |
634 | if (needs_flush) |
635 | goto needs_flush; | |
636 | else | |
637 | goto no_flush_needed; | |
8d76001e | 638 | |
4f618e73 | 639 | }; |
8d76001e | 640 | |
1fbb2e92 CK |
641 | /* Still no ID to use? Then use the idle one found earlier */ |
642 | id = idle; | |
8e9fbeb5 | 643 | |
1fbb2e92 | 644 | /* Remember this submission as user of the VMID */ |
cebb52b7 | 645 | r = amdgpu_sync_fence(ring->adev, &id->active, fence, false); |
832a902f CK |
646 | if (r) |
647 | goto error; | |
94dd0a4a | 648 | |
87c910d8 | 649 | id->pd_gpu_addr = job->vm_pd_addr; |
f54d1867 CW |
650 | dma_fence_put(id->flushed_updates); |
651 | id->flushed_updates = dma_fence_get(updates); | |
0ea54b9b | 652 | atomic64_set(&id->owner, vm->client_id); |
d38ceaf9 | 653 | |
87c910d8 CK |
654 | needs_flush: |
655 | job->vm_needs_flush = true; | |
656 | dma_fence_put(id->last_flush); | |
657 | id->last_flush = NULL; | |
658 | ||
659 | no_flush_needed: | |
660 | list_move_tail(&id->list, &id_mgr->ids_lru); | |
661 | ||
7645670d | 662 | job->vm_id = id - id_mgr->ids; |
c5296d14 | 663 | trace_amdgpu_vm_grab_id(vm, ring, job); |
832a902f CK |
664 | |
665 | error: | |
7645670d | 666 | mutex_unlock(&id_mgr->lock); |
a9a78b32 | 667 | return r; |
d38ceaf9 AD |
668 | } |
669 | ||
1e9ef26f CZ |
670 | static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev, |
671 | struct amdgpu_vm *vm, | |
672 | unsigned vmhub) | |
673 | { | |
674 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
675 | ||
676 | mutex_lock(&id_mgr->lock); | |
677 | if (vm->reserved_vmid[vmhub]) { | |
678 | list_add(&vm->reserved_vmid[vmhub]->list, | |
679 | &id_mgr->ids_lru); | |
680 | vm->reserved_vmid[vmhub] = NULL; | |
c3505770 | 681 | atomic_dec(&id_mgr->reserved_vmid_num); |
1e9ef26f CZ |
682 | } |
683 | mutex_unlock(&id_mgr->lock); | |
684 | } | |
685 | ||
686 | static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev, | |
687 | struct amdgpu_vm *vm, | |
688 | unsigned vmhub) | |
689 | { | |
690 | struct amdgpu_vm_id_manager *id_mgr; | |
691 | struct amdgpu_vm_id *idle; | |
692 | int r = 0; | |
693 | ||
694 | id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
695 | mutex_lock(&id_mgr->lock); | |
696 | if (vm->reserved_vmid[vmhub]) | |
697 | goto unlock; | |
c3505770 CZ |
698 | if (atomic_inc_return(&id_mgr->reserved_vmid_num) > |
699 | AMDGPU_VM_MAX_RESERVED_VMID) { | |
700 | DRM_ERROR("Over limitation of reserved vmid\n"); | |
701 | atomic_dec(&id_mgr->reserved_vmid_num); | |
702 | r = -EINVAL; | |
703 | goto unlock; | |
704 | } | |
1e9ef26f CZ |
705 | /* Select the first entry VMID */ |
706 | idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list); | |
707 | list_del_init(&idle->list); | |
708 | vm->reserved_vmid[vmhub] = idle; | |
709 | mutex_unlock(&id_mgr->lock); | |
710 | ||
711 | return 0; | |
712 | unlock: | |
713 | mutex_unlock(&id_mgr->lock); | |
714 | return r; | |
715 | } | |
716 | ||
e59c0205 AX |
717 | /** |
718 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
719 | * | |
720 | * @adev: amdgpu_device pointer | |
721 | */ | |
722 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 723 | { |
a1255107 | 724 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
725 | bool has_compute_vm_bug; |
726 | struct amdgpu_ring *ring; | |
727 | int i; | |
93dcc37d | 728 | |
e59c0205 | 729 | has_compute_vm_bug = false; |
93dcc37d AD |
730 | |
731 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
e59c0205 AX |
732 | if (ip_block) { |
733 | /* Compute has a VM bug for GFX version < 7. | |
734 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
735 | if (ip_block->version->major <= 7) | |
736 | has_compute_vm_bug = true; | |
737 | else if (ip_block->version->major == 8) | |
738 | if (adev->gfx.mec_fw_version < 673) | |
739 | has_compute_vm_bug = true; | |
740 | } | |
93dcc37d | 741 | |
e59c0205 AX |
742 | for (i = 0; i < adev->num_rings; i++) { |
743 | ring = adev->rings[i]; | |
744 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
745 | /* only compute rings */ | |
746 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 747 | else |
e59c0205 | 748 | ring->has_compute_vm_bug = false; |
93dcc37d | 749 | } |
93dcc37d AD |
750 | } |
751 | ||
b9bf33d5 CZ |
752 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
753 | struct amdgpu_job *job) | |
e60f8db5 | 754 | { |
b9bf33d5 CZ |
755 | struct amdgpu_device *adev = ring->adev; |
756 | unsigned vmhub = ring->funcs->vmhub; | |
757 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
758 | struct amdgpu_vm_id *id; | |
759 | bool gds_switch_needed; | |
e59c0205 | 760 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 CZ |
761 | |
762 | if (job->vm_id == 0) | |
763 | return false; | |
764 | id = &id_mgr->ids[job->vm_id]; | |
765 | gds_switch_needed = ring->funcs->emit_gds_switch && ( | |
766 | id->gds_base != job->gds_base || | |
767 | id->gds_size != job->gds_size || | |
768 | id->gws_base != job->gws_base || | |
769 | id->gws_size != job->gws_size || | |
770 | id->oa_base != job->oa_base || | |
771 | id->oa_size != job->oa_size); | |
e60f8db5 | 772 | |
b9bf33d5 CZ |
773 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
774 | return true; | |
e60f8db5 | 775 | |
bb37b67d | 776 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
777 | } |
778 | ||
9a4b7d4c HK |
779 | static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) |
780 | { | |
781 | return (adev->mc.real_vram_size == adev->mc.visible_vram_size); | |
e60f8db5 AX |
782 | } |
783 | ||
d38ceaf9 AD |
784 | /** |
785 | * amdgpu_vm_flush - hardware flush the vm | |
786 | * | |
787 | * @ring: ring to use for flush | |
cffadc83 | 788 | * @vm_id: vmid number to use |
4ff37a83 | 789 | * @pd_addr: address of the page directory |
d38ceaf9 | 790 | * |
4ff37a83 | 791 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 792 | */ |
8fdf074f | 793 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 794 | { |
971fe9a9 | 795 | struct amdgpu_device *adev = ring->adev; |
7645670d CK |
796 | unsigned vmhub = ring->funcs->vmhub; |
797 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
798 | struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id]; | |
d564a06e | 799 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
800 | id->gds_base != job->gds_base || |
801 | id->gds_size != job->gds_size || | |
802 | id->gws_base != job->gws_base || | |
803 | id->gws_size != job->gws_size || | |
804 | id->oa_base != job->oa_base || | |
805 | id->oa_size != job->oa_size); | |
de37e68a | 806 | bool vm_flush_needed = job->vm_needs_flush; |
c0e51931 | 807 | unsigned patch_offset = 0; |
41d9eb2c | 808 | int r; |
d564a06e | 809 | |
f7d015b9 CK |
810 | if (amdgpu_vm_had_gpu_reset(adev, id)) { |
811 | gds_switch_needed = true; | |
812 | vm_flush_needed = true; | |
813 | } | |
971fe9a9 | 814 | |
8fdf074f | 815 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 816 | return 0; |
41d9eb2c | 817 | |
c0e51931 CK |
818 | if (ring->funcs->init_cond_exec) |
819 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 820 | |
8fdf074f ML |
821 | if (need_pipe_sync) |
822 | amdgpu_ring_emit_pipeline_sync(ring); | |
823 | ||
f7d015b9 | 824 | if (ring->funcs->emit_vm_flush && vm_flush_needed) { |
c0e51931 | 825 | struct dma_fence *fence; |
41d9eb2c | 826 | |
9a94f5a5 CK |
827 | trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr); |
828 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
e9d672b2 | 829 | |
c0e51931 CK |
830 | r = amdgpu_fence_emit(ring, &fence); |
831 | if (r) | |
832 | return r; | |
e9d672b2 | 833 | |
7645670d | 834 | mutex_lock(&id_mgr->lock); |
c0e51931 CK |
835 | dma_fence_put(id->last_flush); |
836 | id->last_flush = fence; | |
bea39672 | 837 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
7645670d | 838 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 839 | } |
e9d672b2 | 840 | |
7c4378f4 | 841 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
842 | id->gds_base = job->gds_base; |
843 | id->gds_size = job->gds_size; | |
844 | id->gws_base = job->gws_base; | |
845 | id->gws_size = job->gws_size; | |
846 | id->oa_base = job->oa_base; | |
847 | id->oa_size = job->oa_size; | |
848 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base, | |
849 | job->gds_size, job->gws_base, | |
850 | job->gws_size, job->oa_base, | |
851 | job->oa_size); | |
852 | } | |
853 | ||
854 | if (ring->funcs->patch_cond_exec) | |
855 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
856 | ||
857 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
858 | if (ring->funcs->emit_switch_buffer) { | |
859 | amdgpu_ring_emit_switch_buffer(ring); | |
860 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 861 | } |
41d9eb2c | 862 | return 0; |
971fe9a9 CK |
863 | } |
864 | ||
865 | /** | |
866 | * amdgpu_vm_reset_id - reset VMID to zero | |
867 | * | |
868 | * @adev: amdgpu device structure | |
869 | * @vm_id: vmid number to use | |
870 | * | |
871 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
872 | */ | |
7645670d CK |
873 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
874 | unsigned vmid) | |
971fe9a9 | 875 | { |
7645670d CK |
876 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
877 | struct amdgpu_vm_id *id = &id_mgr->ids[vmid]; | |
bcb1ba35 | 878 | |
b3c85a0f | 879 | atomic64_set(&id->owner, 0); |
bcb1ba35 CK |
880 | id->gds_base = 0; |
881 | id->gds_size = 0; | |
882 | id->gws_base = 0; | |
883 | id->gws_size = 0; | |
884 | id->oa_base = 0; | |
885 | id->oa_size = 0; | |
d38ceaf9 AD |
886 | } |
887 | ||
b3c85a0f CK |
888 | /** |
889 | * amdgpu_vm_reset_all_id - reset VMID to zero | |
890 | * | |
891 | * @adev: amdgpu device structure | |
892 | * | |
893 | * Reset VMID to force flush on next use | |
894 | */ | |
895 | void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev) | |
896 | { | |
897 | unsigned i, j; | |
898 | ||
899 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
900 | struct amdgpu_vm_id_manager *id_mgr = | |
901 | &adev->vm_manager.id_mgr[i]; | |
902 | ||
903 | for (j = 1; j < id_mgr->num_ids; ++j) | |
904 | amdgpu_vm_reset_id(adev, i, j); | |
905 | } | |
906 | } | |
907 | ||
d38ceaf9 AD |
908 | /** |
909 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
910 | * | |
911 | * @vm: requested vm | |
912 | * @bo: requested buffer object | |
913 | * | |
8843dbbb | 914 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
915 | * Search inside the @bos vm list for the requested vm |
916 | * Returns the found bo_va or NULL if none is found | |
917 | * | |
918 | * Object has to be reserved! | |
919 | */ | |
920 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
921 | struct amdgpu_bo *bo) | |
922 | { | |
923 | struct amdgpu_bo_va *bo_va; | |
924 | ||
ec681545 CK |
925 | list_for_each_entry(bo_va, &bo->va, base.bo_list) { |
926 | if (bo_va->base.vm == vm) { | |
d38ceaf9 AD |
927 | return bo_va; |
928 | } | |
929 | } | |
930 | return NULL; | |
931 | } | |
932 | ||
933 | /** | |
afef8b8f | 934 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 935 | * |
29efc4f5 | 936 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
937 | * @pe: addr of the page entry |
938 | * @addr: dst addr to write into pe | |
939 | * @count: number of page entries to update | |
940 | * @incr: increase next addr by incr bytes | |
941 | * @flags: hw access flags | |
d38ceaf9 AD |
942 | * |
943 | * Traces the parameters and calls the right asic functions | |
944 | * to setup the page table using the DMA. | |
945 | */ | |
afef8b8f CK |
946 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
947 | uint64_t pe, uint64_t addr, | |
948 | unsigned count, uint32_t incr, | |
6b777607 | 949 | uint64_t flags) |
d38ceaf9 | 950 | { |
ec2f05f0 | 951 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 952 | |
afef8b8f | 953 | if (count < 3) { |
de9ea7bd CK |
954 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
955 | addr | flags, count, incr); | |
d38ceaf9 AD |
956 | |
957 | } else { | |
27c5f36f | 958 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
959 | count, incr, flags); |
960 | } | |
961 | } | |
962 | ||
afef8b8f CK |
963 | /** |
964 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
965 | * | |
966 | * @params: see amdgpu_pte_update_params definition | |
967 | * @pe: addr of the page entry | |
968 | * @addr: dst addr to write into pe | |
969 | * @count: number of page entries to update | |
970 | * @incr: increase next addr by incr bytes | |
971 | * @flags: hw access flags | |
972 | * | |
973 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
974 | */ | |
975 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
976 | uint64_t pe, uint64_t addr, | |
977 | unsigned count, uint32_t incr, | |
6b777607 | 978 | uint64_t flags) |
afef8b8f | 979 | { |
ec2f05f0 | 980 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 981 | |
ec2f05f0 CK |
982 | |
983 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
984 | ||
985 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
986 | } |
987 | ||
d38ceaf9 | 988 | /** |
b07c9d2a | 989 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 990 | * |
b07c9d2a | 991 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
992 | * @addr: the unmapped addr |
993 | * | |
994 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 995 | * to and return the pointer for the page table entry. |
d38ceaf9 | 996 | */ |
de9ea7bd | 997 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
998 | { |
999 | uint64_t result; | |
1000 | ||
de9ea7bd CK |
1001 | /* page table offset */ |
1002 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 1003 | |
de9ea7bd CK |
1004 | /* in case cpu page size != gpu page size*/ |
1005 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 1006 | |
b07c9d2a | 1007 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
1008 | |
1009 | return result; | |
1010 | } | |
1011 | ||
3c824172 HK |
1012 | /** |
1013 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU | |
1014 | * | |
1015 | * @params: see amdgpu_pte_update_params definition | |
1016 | * @pe: kmap addr of the page entry | |
1017 | * @addr: dst addr to write into pe | |
1018 | * @count: number of page entries to update | |
1019 | * @incr: increase next addr by incr bytes | |
1020 | * @flags: hw access flags | |
1021 | * | |
1022 | * Write count number of PT/PD entries directly. | |
1023 | */ | |
1024 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, | |
1025 | uint64_t pe, uint64_t addr, | |
1026 | unsigned count, uint32_t incr, | |
1027 | uint64_t flags) | |
1028 | { | |
1029 | unsigned int i; | |
b4d42511 | 1030 | uint64_t value; |
3c824172 | 1031 | |
03918b36 CK |
1032 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
1033 | ||
3c824172 | 1034 | for (i = 0; i < count; i++) { |
b4d42511 HK |
1035 | value = params->pages_addr ? |
1036 | amdgpu_vm_map_gart(params->pages_addr, addr) : | |
1037 | addr; | |
a1924005 | 1038 | amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe, |
b4d42511 | 1039 | i, value, flags); |
3c824172 HK |
1040 | addr += incr; |
1041 | } | |
3c824172 HK |
1042 | } |
1043 | ||
a33cab7a CK |
1044 | static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
1045 | void *owner) | |
3c824172 HK |
1046 | { |
1047 | struct amdgpu_sync sync; | |
1048 | int r; | |
1049 | ||
1050 | amdgpu_sync_create(&sync); | |
177ae09b | 1051 | amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false); |
3c824172 HK |
1052 | r = amdgpu_sync_wait(&sync, true); |
1053 | amdgpu_sync_free(&sync); | |
1054 | ||
1055 | return r; | |
1056 | } | |
1057 | ||
f8991bab | 1058 | /* |
194d2161 | 1059 | * amdgpu_vm_update_level - update a single level in the hierarchy |
f8991bab CK |
1060 | * |
1061 | * @adev: amdgpu_device pointer | |
1062 | * @vm: requested vm | |
194d2161 | 1063 | * @parent: parent directory |
f8991bab | 1064 | * |
194d2161 | 1065 | * Makes sure all entries in @parent are up to date. |
f8991bab CK |
1066 | * Returns 0 for success, error for failure. |
1067 | */ | |
b852f3d3 CK |
1068 | static int amdgpu_vm_update_pde(struct amdgpu_device *adev, |
1069 | struct amdgpu_vm *vm, | |
1070 | struct amdgpu_vm_pt *parent, | |
1071 | struct amdgpu_vm_pt *entry) | |
d38ceaf9 | 1072 | { |
b852f3d3 CK |
1073 | struct amdgpu_pte_update_params params; |
1074 | struct amdgpu_bo *bo = entry->base.bo; | |
f8991bab | 1075 | struct amdgpu_bo *shadow; |
a1924005 HK |
1076 | struct amdgpu_ring *ring = NULL; |
1077 | uint64_t pd_addr, shadow_addr = 0; | |
d71518b5 | 1078 | struct amdgpu_job *job; |
f54d1867 | 1079 | struct dma_fence *fence = NULL; |
b852f3d3 CK |
1080 | unsigned ndw = 0; |
1081 | uint64_t pde, pt; | |
d5fc5e82 | 1082 | |
d38ceaf9 AD |
1083 | int r; |
1084 | ||
194d2161 CK |
1085 | if (!parent->entries) |
1086 | return 0; | |
2d55e45a | 1087 | |
3c824172 HK |
1088 | memset(¶ms, 0, sizeof(params)); |
1089 | params.adev = adev; | |
3f3333f8 | 1090 | shadow = parent->base.bo->shadow; |
d38ceaf9 | 1091 | |
69277985 | 1092 | if (vm->use_cpu_for_update) { |
3f3333f8 | 1093 | pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); |
a33cab7a | 1094 | r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); |
0a096fb6 | 1095 | if (unlikely(r)) |
3c824172 | 1096 | return r; |
0a096fb6 | 1097 | |
3c824172 HK |
1098 | params.func = amdgpu_vm_cpu_set_ptes; |
1099 | } else { | |
3c824172 HK |
1100 | ring = container_of(vm->entity.sched, struct amdgpu_ring, |
1101 | sched); | |
d38ceaf9 | 1102 | |
b852f3d3 | 1103 | /* should be sufficient for two commands plus padding, etc. */ |
3c824172 | 1104 | ndw = 64; |
194d2161 | 1105 | |
3f3333f8 | 1106 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); |
b852f3d3 | 1107 | if (shadow) |
3c824172 | 1108 | shadow_addr = amdgpu_bo_gpu_offset(shadow); |
b852f3d3 | 1109 | else |
3c824172 | 1110 | shadow_addr = 0; |
3c824172 HK |
1111 | |
1112 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
f8991bab CK |
1113 | if (r) |
1114 | return r; | |
f8991bab | 1115 | |
3c824172 HK |
1116 | params.ib = &job->ibs[0]; |
1117 | params.func = amdgpu_vm_do_set_ptes; | |
1118 | } | |
d71518b5 | 1119 | |
b852f3d3 CK |
1120 | spin_lock(&vm->status_lock); |
1121 | list_del_init(&entry->base.vm_status); | |
1122 | spin_unlock(&vm->status_lock); | |
d38ceaf9 | 1123 | |
b852f3d3 CK |
1124 | pt = amdgpu_bo_gpu_offset(bo); |
1125 | pt = amdgpu_gart_get_vm_pde(adev, pt); | |
1126 | /* Don't update huge pages here */ | |
78eb2f0c | 1127 | if (entry->huge) { |
b852f3d3 CK |
1128 | if (!vm->use_cpu_for_update) |
1129 | amdgpu_job_free(job); | |
1130 | return 0; | |
1131 | } | |
d38ceaf9 | 1132 | |
b852f3d3 CK |
1133 | if (shadow) { |
1134 | pde = shadow_addr + (entry - parent->entries) * 8; | |
1135 | params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID); | |
f8991bab | 1136 | } |
d38ceaf9 | 1137 | |
b852f3d3 CK |
1138 | pde = pd_addr + (entry - parent->entries) * 8; |
1139 | params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID); | |
1140 | ||
0a096fb6 CK |
1141 | if (!vm->use_cpu_for_update) { |
1142 | if (params.ib->length_dw == 0) { | |
1143 | amdgpu_job_free(job); | |
1144 | } else { | |
1145 | amdgpu_ring_pad_ib(ring, params.ib); | |
3f3333f8 CK |
1146 | amdgpu_sync_resv(adev, &job->sync, |
1147 | parent->base.bo->tbo.resv, | |
177ae09b | 1148 | AMDGPU_FENCE_OWNER_VM, false); |
0a096fb6 CK |
1149 | if (shadow) |
1150 | amdgpu_sync_resv(adev, &job->sync, | |
1151 | shadow->tbo.resv, | |
177ae09b | 1152 | AMDGPU_FENCE_OWNER_VM, false); |
0a096fb6 CK |
1153 | |
1154 | WARN_ON(params.ib->length_dw > ndw); | |
1155 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
1156 | AMDGPU_FENCE_OWNER_VM, &fence); | |
1157 | if (r) | |
1158 | goto error_free; | |
05906dec | 1159 | |
3f3333f8 | 1160 | amdgpu_bo_fence(parent->base.bo, fence, true); |
d5884513 CK |
1161 | dma_fence_put(vm->last_update); |
1162 | vm->last_update = fence; | |
0a096fb6 | 1163 | } |
194d2161 | 1164 | } |
d38ceaf9 AD |
1165 | |
1166 | return 0; | |
d5fc5e82 CZ |
1167 | |
1168 | error_free: | |
d71518b5 | 1169 | amdgpu_job_free(job); |
4af9f07c | 1170 | return r; |
d38ceaf9 AD |
1171 | } |
1172 | ||
92456b93 CK |
1173 | /* |
1174 | * amdgpu_vm_invalidate_level - mark all PD levels as invalid | |
1175 | * | |
1176 | * @parent: parent PD | |
1177 | * | |
1178 | * Mark all PD level as invalid after an error. | |
1179 | */ | |
8f19cd78 CK |
1180 | static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev, |
1181 | struct amdgpu_vm *vm, | |
1182 | struct amdgpu_vm_pt *parent, | |
1183 | unsigned level) | |
92456b93 | 1184 | { |
8f19cd78 | 1185 | unsigned pt_idx, num_entries; |
92456b93 CK |
1186 | |
1187 | /* | |
1188 | * Recurse into the subdirectories. This recursion is harmless because | |
1189 | * we only have a maximum of 5 layers. | |
1190 | */ | |
8f19cd78 CK |
1191 | num_entries = amdgpu_vm_num_entries(adev, level); |
1192 | for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) { | |
92456b93 CK |
1193 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
1194 | ||
3f3333f8 | 1195 | if (!entry->base.bo) |
92456b93 CK |
1196 | continue; |
1197 | ||
ea09729c | 1198 | spin_lock(&vm->status_lock); |
481c2e94 CK |
1199 | if (list_empty(&entry->base.vm_status)) |
1200 | list_add(&entry->base.vm_status, &vm->relocated); | |
ea09729c | 1201 | spin_unlock(&vm->status_lock); |
8f19cd78 | 1202 | amdgpu_vm_invalidate_level(adev, vm, entry, level + 1); |
92456b93 CK |
1203 | } |
1204 | } | |
1205 | ||
194d2161 CK |
1206 | /* |
1207 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1208 | * | |
1209 | * @adev: amdgpu_device pointer | |
1210 | * @vm: requested vm | |
1211 | * | |
1212 | * Makes sure all directories are up to date. | |
1213 | * Returns 0 for success, error for failure. | |
1214 | */ | |
1215 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1216 | struct amdgpu_vm *vm) | |
1217 | { | |
78aa02c7 | 1218 | int r = 0; |
92456b93 | 1219 | |
ea09729c CK |
1220 | spin_lock(&vm->status_lock); |
1221 | while (!list_empty(&vm->relocated)) { | |
1222 | struct amdgpu_vm_bo_base *bo_base; | |
1223 | struct amdgpu_bo *bo; | |
1224 | ||
1225 | bo_base = list_first_entry(&vm->relocated, | |
1226 | struct amdgpu_vm_bo_base, | |
1227 | vm_status); | |
1228 | spin_unlock(&vm->status_lock); | |
1229 | ||
1230 | bo = bo_base->bo->parent; | |
1231 | if (bo) { | |
1232 | struct amdgpu_vm_bo_base *parent; | |
b852f3d3 | 1233 | struct amdgpu_vm_pt *pt, *entry; |
ea09729c CK |
1234 | |
1235 | parent = list_first_entry(&bo->va, | |
1236 | struct amdgpu_vm_bo_base, | |
1237 | bo_list); | |
1238 | pt = container_of(parent, struct amdgpu_vm_pt, base); | |
b852f3d3 CK |
1239 | entry = container_of(bo_base, struct amdgpu_vm_pt, |
1240 | base); | |
ea09729c | 1241 | |
b852f3d3 | 1242 | r = amdgpu_vm_update_pde(adev, vm, pt, entry); |
ea09729c | 1243 | if (r) { |
8f19cd78 CK |
1244 | amdgpu_vm_invalidate_level(adev, vm, |
1245 | &vm->root, 0); | |
ea09729c CK |
1246 | return r; |
1247 | } | |
1248 | spin_lock(&vm->status_lock); | |
1249 | } else { | |
1250 | spin_lock(&vm->status_lock); | |
1251 | list_del_init(&bo_base->vm_status); | |
1252 | } | |
1253 | } | |
1254 | spin_unlock(&vm->status_lock); | |
92456b93 | 1255 | |
68c62306 CK |
1256 | if (vm->use_cpu_for_update) { |
1257 | /* Flush HDP */ | |
1258 | mb(); | |
1259 | amdgpu_gart_flush_gpu_tlb(adev, 0); | |
1260 | } | |
1261 | ||
92456b93 | 1262 | return r; |
194d2161 CK |
1263 | } |
1264 | ||
4e2cb640 | 1265 | /** |
cf2f0a37 | 1266 | * amdgpu_vm_find_entry - find the entry for an address |
4e2cb640 CK |
1267 | * |
1268 | * @p: see amdgpu_pte_update_params definition | |
1269 | * @addr: virtual address in question | |
cf2f0a37 AD |
1270 | * @entry: resulting entry or NULL |
1271 | * @parent: parent entry | |
4e2cb640 | 1272 | * |
cf2f0a37 | 1273 | * Find the vm_pt entry and it's parent for the given address. |
4e2cb640 | 1274 | */ |
cf2f0a37 AD |
1275 | void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, |
1276 | struct amdgpu_vm_pt **entry, | |
1277 | struct amdgpu_vm_pt **parent) | |
4e2cb640 | 1278 | { |
50783147 | 1279 | unsigned level = 0; |
4e2cb640 | 1280 | |
cf2f0a37 AD |
1281 | *parent = NULL; |
1282 | *entry = &p->vm->root; | |
1283 | while ((*entry)->entries) { | |
e3a1b32a | 1284 | unsigned shift = amdgpu_vm_level_shift(p->adev, level++); |
50783147 | 1285 | |
cf2f0a37 | 1286 | *parent = *entry; |
e3a1b32a CK |
1287 | *entry = &(*entry)->entries[addr >> shift]; |
1288 | addr &= (1ULL << shift) - 1; | |
4e2cb640 CK |
1289 | } |
1290 | ||
50783147 | 1291 | if (level != p->adev->vm_manager.num_level) |
cf2f0a37 AD |
1292 | *entry = NULL; |
1293 | } | |
1294 | ||
1295 | /** | |
1296 | * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages | |
1297 | * | |
1298 | * @p: see amdgpu_pte_update_params definition | |
1299 | * @entry: vm_pt entry to check | |
1300 | * @parent: parent entry | |
1301 | * @nptes: number of PTEs updated with this operation | |
1302 | * @dst: destination address where the PTEs should point to | |
1303 | * @flags: access flags fro the PTEs | |
1304 | * | |
1305 | * Check if we can update the PD with a huge page. | |
1306 | */ | |
ec5207c9 CK |
1307 | static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, |
1308 | struct amdgpu_vm_pt *entry, | |
1309 | struct amdgpu_vm_pt *parent, | |
1310 | unsigned nptes, uint64_t dst, | |
1311 | uint64_t flags) | |
cf2f0a37 AD |
1312 | { |
1313 | bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes); | |
1314 | uint64_t pd_addr, pde; | |
cf2f0a37 AD |
1315 | |
1316 | /* In the case of a mixed PT the PDE must point to it*/ | |
1317 | if (p->adev->asic_type < CHIP_VEGA10 || | |
1318 | nptes != AMDGPU_VM_PTE_COUNT(p->adev) || | |
b252903a | 1319 | p->src || |
cf2f0a37 AD |
1320 | !(flags & AMDGPU_PTE_VALID)) { |
1321 | ||
3f3333f8 | 1322 | dst = amdgpu_bo_gpu_offset(entry->base.bo); |
cf2f0a37 AD |
1323 | dst = amdgpu_gart_get_vm_pde(p->adev, dst); |
1324 | flags = AMDGPU_PTE_VALID; | |
1325 | } else { | |
4ab4016a | 1326 | /* Set the huge page flag to stop scanning at this PDE */ |
cf2f0a37 AD |
1327 | flags |= AMDGPU_PDE_PTE; |
1328 | } | |
1329 | ||
78eb2f0c | 1330 | if (!entry->huge && !(flags & AMDGPU_PDE_PTE)) |
ec5207c9 | 1331 | return; |
cf2f0a37 | 1332 | |
78eb2f0c | 1333 | entry->huge = !!(flags & AMDGPU_PDE_PTE); |
cf2f0a37 AD |
1334 | |
1335 | if (use_cpu_update) { | |
b252903a FK |
1336 | /* In case a huge page is replaced with a system |
1337 | * memory mapping, p->pages_addr != NULL and | |
1338 | * amdgpu_vm_cpu_set_ptes would try to translate dst | |
1339 | * through amdgpu_vm_map_gart. But dst is already a | |
1340 | * GPU address (of the page table). Disable | |
1341 | * amdgpu_vm_map_gart temporarily. | |
1342 | */ | |
1343 | dma_addr_t *tmp; | |
1344 | ||
1345 | tmp = p->pages_addr; | |
1346 | p->pages_addr = NULL; | |
1347 | ||
3f3333f8 | 1348 | pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); |
cf2f0a37 AD |
1349 | pde = pd_addr + (entry - parent->entries) * 8; |
1350 | amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags); | |
b252903a FK |
1351 | |
1352 | p->pages_addr = tmp; | |
cf2f0a37 | 1353 | } else { |
3f3333f8 CK |
1354 | if (parent->base.bo->shadow) { |
1355 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow); | |
cf2f0a37 AD |
1356 | pde = pd_addr + (entry - parent->entries) * 8; |
1357 | amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); | |
1358 | } | |
3f3333f8 | 1359 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); |
cf2f0a37 AD |
1360 | pde = pd_addr + (entry - parent->entries) * 8; |
1361 | amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); | |
1362 | } | |
4e2cb640 CK |
1363 | } |
1364 | ||
d38ceaf9 AD |
1365 | /** |
1366 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1367 | * | |
29efc4f5 | 1368 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1369 | * @vm: requested vm |
1370 | * @start: start of GPU address range | |
1371 | * @end: end of GPU address range | |
677131a1 | 1372 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1373 | * @flags: mapping flags |
1374 | * | |
8843dbbb | 1375 | * Update the page tables in the range @start - @end. |
cc28c4ed | 1376 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 | 1377 | */ |
cc28c4ed | 1378 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1379 | uint64_t start, uint64_t end, |
6b777607 | 1380 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1381 | { |
36b32a68 ZJ |
1382 | struct amdgpu_device *adev = params->adev; |
1383 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1384 | |
301654a4 | 1385 | uint64_t addr, pe_start; |
21718497 | 1386 | struct amdgpu_bo *pt; |
301654a4 | 1387 | unsigned nptes; |
370f092f | 1388 | bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes); |
d38ceaf9 AD |
1389 | |
1390 | /* walk over the address space and update the page tables */ | |
cf2f0a37 AD |
1391 | for (addr = start; addr < end; addr += nptes, |
1392 | dst += nptes * AMDGPU_GPU_PAGE_SIZE) { | |
1393 | struct amdgpu_vm_pt *entry, *parent; | |
1394 | ||
1395 | amdgpu_vm_get_entry(params, addr, &entry, &parent); | |
1396 | if (!entry) | |
1397 | return -ENOENT; | |
4e2cb640 | 1398 | |
d38ceaf9 AD |
1399 | if ((addr & ~mask) == (end & ~mask)) |
1400 | nptes = end - addr; | |
1401 | else | |
36b32a68 | 1402 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1403 | |
ec5207c9 CK |
1404 | amdgpu_vm_handle_huge_pages(params, entry, parent, |
1405 | nptes, dst, flags); | |
4ab4016a | 1406 | /* We don't need to update PTEs for huge pages */ |
78eb2f0c | 1407 | if (entry->huge) |
cf2f0a37 AD |
1408 | continue; |
1409 | ||
3f3333f8 | 1410 | pt = entry->base.bo; |
370f092f | 1411 | if (use_cpu_update) { |
f5e1c740 | 1412 | pe_start = (unsigned long)amdgpu_bo_kptr(pt); |
dd0792c1 CK |
1413 | } else { |
1414 | if (pt->shadow) { | |
1415 | pe_start = amdgpu_bo_gpu_offset(pt->shadow); | |
1416 | pe_start += (addr & mask) * 8; | |
1417 | params->func(params, pe_start, dst, nptes, | |
1418 | AMDGPU_GPU_PAGE_SIZE, flags); | |
1419 | } | |
370f092f | 1420 | pe_start = amdgpu_bo_gpu_offset(pt); |
dd0792c1 | 1421 | } |
d38ceaf9 | 1422 | |
301654a4 | 1423 | pe_start += (addr & mask) * 8; |
301654a4 CK |
1424 | params->func(params, pe_start, dst, nptes, |
1425 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
1426 | } |
1427 | ||
cc28c4ed | 1428 | return 0; |
92696dd5 CK |
1429 | } |
1430 | ||
1431 | /* | |
1432 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1433 | * | |
1434 | * @params: see amdgpu_pte_update_params definition | |
1435 | * @vm: requested vm | |
1436 | * @start: first PTE to handle | |
1437 | * @end: last PTE to handle | |
1438 | * @dst: addr those PTEs should point to | |
1439 | * @flags: hw mapping flags | |
cc28c4ed | 1440 | * Returns 0 for success, -EINVAL for failure. |
92696dd5 | 1441 | */ |
cc28c4ed | 1442 | static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, |
92696dd5 | 1443 | uint64_t start, uint64_t end, |
6b777607 | 1444 | uint64_t dst, uint64_t flags) |
92696dd5 CK |
1445 | { |
1446 | /** | |
1447 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1448 | * field in the PTE. When this field is set to a non-zero value, page | |
1449 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1450 | * flags are considered valid for all PTEs within the fragment range | |
1451 | * and corresponding mappings are assumed to be physically contiguous. | |
1452 | * | |
1453 | * The L1 TLB can store a single PTE for the whole fragment, | |
1454 | * significantly increasing the space available for translation | |
1455 | * caching. This leads to large improvements in throughput when the | |
1456 | * TLB is under pressure. | |
1457 | * | |
1458 | * The L2 TLB distributes small and large fragments into two | |
1459 | * asymmetric partitions. The large fragment cache is significantly | |
1460 | * larger. Thus, we try to use large fragments wherever possible. | |
1461 | * Userspace can support this by aligning virtual base address and | |
1462 | * allocation size to the fragment size. | |
1463 | */ | |
6849d47c RH |
1464 | unsigned max_frag = params->adev->vm_manager.fragment_size; |
1465 | int r; | |
92696dd5 CK |
1466 | |
1467 | /* system pages are non continuously */ | |
6849d47c | 1468 | if (params->src || !(flags & AMDGPU_PTE_VALID)) |
cc28c4ed | 1469 | return amdgpu_vm_update_ptes(params, start, end, dst, flags); |
92696dd5 | 1470 | |
6849d47c RH |
1471 | while (start != end) { |
1472 | uint64_t frag_flags, frag_end; | |
1473 | unsigned frag; | |
1474 | ||
1475 | /* This intentionally wraps around if no bit is set */ | |
1476 | frag = min((unsigned)ffs(start) - 1, | |
1477 | (unsigned)fls64(end - start) - 1); | |
1478 | if (frag >= max_frag) { | |
1479 | frag_flags = AMDGPU_PTE_FRAG(max_frag); | |
1480 | frag_end = end & ~((1ULL << max_frag) - 1); | |
1481 | } else { | |
1482 | frag_flags = AMDGPU_PTE_FRAG(frag); | |
1483 | frag_end = start + (1 << frag); | |
1484 | } | |
1485 | ||
1486 | r = amdgpu_vm_update_ptes(params, start, frag_end, dst, | |
1487 | flags | frag_flags); | |
cc28c4ed HK |
1488 | if (r) |
1489 | return r; | |
92696dd5 | 1490 | |
6849d47c RH |
1491 | dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE; |
1492 | start = frag_end; | |
92696dd5 | 1493 | } |
6849d47c RH |
1494 | |
1495 | return 0; | |
d38ceaf9 AD |
1496 | } |
1497 | ||
d38ceaf9 AD |
1498 | /** |
1499 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1500 | * | |
1501 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1502 | * @exclusive: fence we need to sync to |
fa3ab3c7 | 1503 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 | 1504 | * @vm: requested vm |
a14faa65 CK |
1505 | * @start: start of mapped range |
1506 | * @last: last mapped entry | |
1507 | * @flags: flags for the entries | |
d38ceaf9 | 1508 | * @addr: addr to set the area to |
d38ceaf9 AD |
1509 | * @fence: optional resulting fence |
1510 | * | |
a14faa65 | 1511 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 1512 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
1513 | */ |
1514 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1515 | struct dma_fence *exclusive, |
fa3ab3c7 | 1516 | dma_addr_t *pages_addr, |
d38ceaf9 | 1517 | struct amdgpu_vm *vm, |
a14faa65 | 1518 | uint64_t start, uint64_t last, |
6b777607 | 1519 | uint64_t flags, uint64_t addr, |
f54d1867 | 1520 | struct dma_fence **fence) |
d38ceaf9 | 1521 | { |
2d55e45a | 1522 | struct amdgpu_ring *ring; |
a1e08d3b | 1523 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1524 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1525 | struct amdgpu_job *job; |
29efc4f5 | 1526 | struct amdgpu_pte_update_params params; |
f54d1867 | 1527 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1528 | int r; |
1529 | ||
afef8b8f CK |
1530 | memset(¶ms, 0, sizeof(params)); |
1531 | params.adev = adev; | |
49ac8a24 | 1532 | params.vm = vm; |
afef8b8f | 1533 | |
a33cab7a CK |
1534 | /* sync to everything on unmapping */ |
1535 | if (!(flags & AMDGPU_PTE_VALID)) | |
1536 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1537 | ||
b4d42511 HK |
1538 | if (vm->use_cpu_for_update) { |
1539 | /* params.src is used as flag to indicate system Memory */ | |
1540 | if (pages_addr) | |
1541 | params.src = ~0; | |
1542 | ||
1543 | /* Wait for PT BOs to be free. PTs share the same resv. object | |
1544 | * as the root PD BO | |
1545 | */ | |
a33cab7a | 1546 | r = amdgpu_vm_wait_pd(adev, vm, owner); |
b4d42511 HK |
1547 | if (unlikely(r)) |
1548 | return r; | |
1549 | ||
1550 | params.func = amdgpu_vm_cpu_set_ptes; | |
1551 | params.pages_addr = pages_addr; | |
b4d42511 HK |
1552 | return amdgpu_vm_frag_ptes(¶ms, start, last + 1, |
1553 | addr, flags); | |
1554 | } | |
1555 | ||
2d55e45a | 1556 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 1557 | |
a14faa65 | 1558 | nptes = last - start + 1; |
d38ceaf9 AD |
1559 | |
1560 | /* | |
86209523 | 1561 | * reserve space for two commands every (1 << BLOCK_SIZE) |
d38ceaf9 | 1562 | * entries or 2k dwords (whatever is smaller) |
86209523 BN |
1563 | * |
1564 | * The second command is for the shadow pagetables. | |
d38ceaf9 | 1565 | */ |
86209523 | 1566 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2; |
d38ceaf9 AD |
1567 | |
1568 | /* padding, etc. */ | |
1569 | ndw = 64; | |
1570 | ||
cf2f0a37 AD |
1571 | /* one PDE write for each huge page */ |
1572 | ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6; | |
1573 | ||
570144c6 | 1574 | if (pages_addr) { |
b0456f93 | 1575 | /* copy commands needed */ |
e6d92197 | 1576 | ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; |
d38ceaf9 | 1577 | |
b0456f93 | 1578 | /* and also PTEs */ |
d38ceaf9 AD |
1579 | ndw += nptes * 2; |
1580 | ||
afef8b8f CK |
1581 | params.func = amdgpu_vm_do_copy_ptes; |
1582 | ||
d38ceaf9 AD |
1583 | } else { |
1584 | /* set page commands needed */ | |
7bdc53f9 | 1585 | ndw += ncmds * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw; |
d38ceaf9 | 1586 | |
6849d47c | 1587 | /* extra commands for begin/end fragments */ |
7bdc53f9 YZ |
1588 | ndw += 2 * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw |
1589 | * adev->vm_manager.fragment_size; | |
afef8b8f CK |
1590 | |
1591 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1592 | } |
1593 | ||
d71518b5 CK |
1594 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1595 | if (r) | |
d38ceaf9 | 1596 | return r; |
d71518b5 | 1597 | |
29efc4f5 | 1598 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1599 | |
570144c6 | 1600 | if (pages_addr) { |
b0456f93 CK |
1601 | uint64_t *pte; |
1602 | unsigned i; | |
1603 | ||
1604 | /* Put the PTEs at the end of the IB. */ | |
1605 | i = ndw - nptes * 2; | |
1606 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1607 | params.src = job->ibs->gpu_addr + i * 4; | |
1608 | ||
1609 | for (i = 0; i < nptes; ++i) { | |
1610 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1611 | AMDGPU_GPU_PAGE_SIZE); | |
1612 | pte[i] |= flags; | |
1613 | } | |
d7a4ac66 | 1614 | addr = 0; |
b0456f93 CK |
1615 | } |
1616 | ||
cebb52b7 | 1617 | r = amdgpu_sync_fence(adev, &job->sync, exclusive, false); |
3cabaa54 CK |
1618 | if (r) |
1619 | goto error_free; | |
1620 | ||
3f3333f8 | 1621 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, |
177ae09b | 1622 | owner, false); |
a1e08d3b CK |
1623 | if (r) |
1624 | goto error_free; | |
d38ceaf9 | 1625 | |
3f3333f8 | 1626 | r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv); |
a1e08d3b CK |
1627 | if (r) |
1628 | goto error_free; | |
1629 | ||
cc28c4ed HK |
1630 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
1631 | if (r) | |
1632 | goto error_free; | |
d38ceaf9 | 1633 | |
29efc4f5 CK |
1634 | amdgpu_ring_pad_ib(ring, params.ib); |
1635 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1636 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1637 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1638 | if (r) |
1639 | goto error_free; | |
d38ceaf9 | 1640 | |
3f3333f8 | 1641 | amdgpu_bo_fence(vm->root.base.bo, f, true); |
284710fa CK |
1642 | dma_fence_put(*fence); |
1643 | *fence = f; | |
d38ceaf9 | 1644 | return 0; |
d5fc5e82 CZ |
1645 | |
1646 | error_free: | |
d71518b5 | 1647 | amdgpu_job_free(job); |
8f19cd78 | 1648 | amdgpu_vm_invalidate_level(adev, vm, &vm->root, 0); |
4af9f07c | 1649 | return r; |
d38ceaf9 AD |
1650 | } |
1651 | ||
a14faa65 CK |
1652 | /** |
1653 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1654 | * | |
1655 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1656 | * @exclusive: fence we need to sync to |
8358dcee | 1657 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1658 | * @vm: requested vm |
1659 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1660 | * @flags: HW flags for the mapping |
63e0ba40 | 1661 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1662 | * @fence: optional resulting fence |
1663 | * | |
1664 | * Split the mapping into smaller chunks so that each update fits | |
1665 | * into a SDMA IB. | |
1666 | * Returns 0 for success, -EINVAL for failure. | |
1667 | */ | |
1668 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1669 | struct dma_fence *exclusive, |
8358dcee | 1670 | dma_addr_t *pages_addr, |
a14faa65 CK |
1671 | struct amdgpu_vm *vm, |
1672 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1673 | uint64_t flags, |
63e0ba40 | 1674 | struct drm_mm_node *nodes, |
f54d1867 | 1675 | struct dma_fence **fence) |
a14faa65 | 1676 | { |
9fc8fc70 | 1677 | unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; |
570144c6 | 1678 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1679 | int r; |
1680 | ||
1681 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1682 | * but in case of something, we filter the flags in first place | |
1683 | */ | |
1684 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1685 | flags &= ~AMDGPU_PTE_READABLE; | |
1686 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1687 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1688 | ||
15b31c59 AX |
1689 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1690 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1691 | ||
b0fd18b0 AX |
1692 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1693 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1694 | ||
d0766e98 ZJ |
1695 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1696 | (adev->asic_type >= CHIP_VEGA10)) { | |
1697 | flags |= AMDGPU_PTE_PRT; | |
1698 | flags &= ~AMDGPU_PTE_VALID; | |
1699 | } | |
1700 | ||
a14faa65 CK |
1701 | trace_amdgpu_vm_bo_update(mapping); |
1702 | ||
63e0ba40 CK |
1703 | pfn = mapping->offset >> PAGE_SHIFT; |
1704 | if (nodes) { | |
1705 | while (pfn >= nodes->size) { | |
1706 | pfn -= nodes->size; | |
1707 | ++nodes; | |
1708 | } | |
fa3ab3c7 | 1709 | } |
a14faa65 | 1710 | |
63e0ba40 | 1711 | do { |
9fc8fc70 | 1712 | dma_addr_t *dma_addr = NULL; |
63e0ba40 CK |
1713 | uint64_t max_entries; |
1714 | uint64_t addr, last; | |
a14faa65 | 1715 | |
63e0ba40 CK |
1716 | if (nodes) { |
1717 | addr = nodes->start << PAGE_SHIFT; | |
1718 | max_entries = (nodes->size - pfn) * | |
1719 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1720 | } else { | |
1721 | addr = 0; | |
1722 | max_entries = S64_MAX; | |
1723 | } | |
a14faa65 | 1724 | |
63e0ba40 | 1725 | if (pages_addr) { |
9fc8fc70 CK |
1726 | uint64_t count; |
1727 | ||
457e0fee | 1728 | max_entries = min(max_entries, 16ull * 1024ull); |
9fc8fc70 CK |
1729 | for (count = 1; count < max_entries; ++count) { |
1730 | uint64_t idx = pfn + count; | |
1731 | ||
1732 | if (pages_addr[idx] != | |
1733 | (pages_addr[idx - 1] + PAGE_SIZE)) | |
1734 | break; | |
1735 | } | |
1736 | ||
1737 | if (count < min_linear_pages) { | |
1738 | addr = pfn << PAGE_SHIFT; | |
1739 | dma_addr = pages_addr; | |
1740 | } else { | |
1741 | addr = pages_addr[pfn]; | |
1742 | max_entries = count; | |
1743 | } | |
1744 | ||
63e0ba40 CK |
1745 | } else if (flags & AMDGPU_PTE_VALID) { |
1746 | addr += adev->vm_manager.vram_base_offset; | |
9fc8fc70 | 1747 | addr += pfn << PAGE_SHIFT; |
63e0ba40 | 1748 | } |
63e0ba40 | 1749 | |
a9f87f64 | 1750 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
9fc8fc70 | 1751 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, |
a14faa65 CK |
1752 | start, last, flags, addr, |
1753 | fence); | |
1754 | if (r) | |
1755 | return r; | |
1756 | ||
63e0ba40 CK |
1757 | pfn += last - start + 1; |
1758 | if (nodes && nodes->size == pfn) { | |
1759 | pfn = 0; | |
1760 | ++nodes; | |
1761 | } | |
a14faa65 | 1762 | start = last + 1; |
63e0ba40 | 1763 | |
a9f87f64 | 1764 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1765 | |
1766 | return 0; | |
1767 | } | |
1768 | ||
d38ceaf9 AD |
1769 | /** |
1770 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1771 | * | |
1772 | * @adev: amdgpu_device pointer | |
1773 | * @bo_va: requested BO and VM object | |
99e124f4 | 1774 | * @clear: if true clear the entries |
d38ceaf9 AD |
1775 | * |
1776 | * Fill in the page table entries for @bo_va. | |
1777 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1778 | */ |
1779 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1780 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1781 | bool clear) |
d38ceaf9 | 1782 | { |
ec681545 CK |
1783 | struct amdgpu_bo *bo = bo_va->base.bo; |
1784 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1785 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1786 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 1787 | struct ttm_mem_reg *mem; |
63e0ba40 | 1788 | struct drm_mm_node *nodes; |
4e55eb38 | 1789 | struct dma_fence *exclusive, **last_update; |
457e0fee | 1790 | uint64_t flags; |
d38ceaf9 AD |
1791 | int r; |
1792 | ||
ec681545 | 1793 | if (clear || !bo_va->base.bo) { |
99e124f4 | 1794 | mem = NULL; |
63e0ba40 | 1795 | nodes = NULL; |
99e124f4 CK |
1796 | exclusive = NULL; |
1797 | } else { | |
8358dcee CK |
1798 | struct ttm_dma_tt *ttm; |
1799 | ||
ec681545 | 1800 | mem = &bo_va->base.bo->tbo.mem; |
63e0ba40 CK |
1801 | nodes = mem->mm_node; |
1802 | if (mem->mem_type == TTM_PL_TT) { | |
ec681545 CK |
1803 | ttm = container_of(bo_va->base.bo->tbo.ttm, |
1804 | struct ttm_dma_tt, ttm); | |
8358dcee | 1805 | pages_addr = ttm->dma_address; |
9ab21462 | 1806 | } |
ec681545 | 1807 | exclusive = reservation_object_get_excl(bo->tbo.resv); |
d38ceaf9 AD |
1808 | } |
1809 | ||
457e0fee | 1810 | if (bo) |
ec681545 | 1811 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
457e0fee | 1812 | else |
a5f6b5b1 | 1813 | flags = 0x0; |
d38ceaf9 | 1814 | |
4e55eb38 CK |
1815 | if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) |
1816 | last_update = &vm->last_update; | |
1817 | else | |
1818 | last_update = &bo_va->last_pt_update; | |
1819 | ||
3d7d4d3a CK |
1820 | if (!clear && bo_va->base.moved) { |
1821 | bo_va->base.moved = false; | |
7fc11959 | 1822 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1823 | |
cb7b6ec2 CK |
1824 | } else if (bo_va->cleared != clear) { |
1825 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1826 | } |
7fc11959 CK |
1827 | |
1828 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
457e0fee | 1829 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
63e0ba40 | 1830 | mapping, flags, nodes, |
4e55eb38 | 1831 | last_update); |
d38ceaf9 AD |
1832 | if (r) |
1833 | return r; | |
1834 | } | |
1835 | ||
cb7b6ec2 CK |
1836 | if (vm->use_cpu_for_update) { |
1837 | /* Flush HDP */ | |
1838 | mb(); | |
1839 | amdgpu_gart_flush_gpu_tlb(adev, 0); | |
d6c10f6b CK |
1840 | } |
1841 | ||
d38ceaf9 | 1842 | spin_lock(&vm->status_lock); |
ec681545 | 1843 | list_del_init(&bo_va->base.vm_status); |
d38ceaf9 AD |
1844 | spin_unlock(&vm->status_lock); |
1845 | ||
cb7b6ec2 CK |
1846 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1847 | bo_va->cleared = clear; | |
1848 | ||
1849 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1850 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1851 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1852 | } |
1853 | ||
d38ceaf9 AD |
1854 | return 0; |
1855 | } | |
1856 | ||
284710fa CK |
1857 | /** |
1858 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1859 | */ | |
1860 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1861 | { | |
1862 | unsigned long flags; | |
1863 | bool enable; | |
1864 | ||
1865 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1866 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
284710fa CK |
1867 | adev->gart.gart_funcs->set_prt(adev, enable); |
1868 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
1869 | } | |
1870 | ||
451bc8eb | 1871 | /** |
4388fc2a | 1872 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1873 | */ |
1874 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1875 | { | |
4388fc2a CK |
1876 | if (!adev->gart.gart_funcs->set_prt) |
1877 | return; | |
1878 | ||
451bc8eb CK |
1879 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1880 | amdgpu_vm_update_prt_state(adev); | |
1881 | } | |
1882 | ||
0b15f2fc CK |
1883 | /** |
1884 | * amdgpu_vm_prt_put - drop a PRT user | |
1885 | */ | |
1886 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1887 | { | |
451bc8eb | 1888 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1889 | amdgpu_vm_update_prt_state(adev); |
1890 | } | |
1891 | ||
284710fa | 1892 | /** |
451bc8eb | 1893 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1894 | */ |
1895 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1896 | { | |
1897 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1898 | ||
0b15f2fc | 1899 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1900 | kfree(cb); |
1901 | } | |
1902 | ||
451bc8eb CK |
1903 | /** |
1904 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1905 | */ | |
1906 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1907 | struct dma_fence *fence) | |
1908 | { | |
4388fc2a | 1909 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1910 | |
4388fc2a CK |
1911 | if (!adev->gart.gart_funcs->set_prt) |
1912 | return; | |
1913 | ||
1914 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1915 | if (!cb) { |
1916 | /* Last resort when we are OOM */ | |
1917 | if (fence) | |
1918 | dma_fence_wait(fence, false); | |
1919 | ||
486a68f5 | 1920 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1921 | } else { |
1922 | cb->adev = adev; | |
1923 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1924 | amdgpu_vm_prt_cb)) | |
1925 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1926 | } | |
1927 | } | |
1928 | ||
284710fa CK |
1929 | /** |
1930 | * amdgpu_vm_free_mapping - free a mapping | |
1931 | * | |
1932 | * @adev: amdgpu_device pointer | |
1933 | * @vm: requested vm | |
1934 | * @mapping: mapping to be freed | |
1935 | * @fence: fence of the unmap operation | |
1936 | * | |
1937 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1938 | */ | |
1939 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1940 | struct amdgpu_vm *vm, | |
1941 | struct amdgpu_bo_va_mapping *mapping, | |
1942 | struct dma_fence *fence) | |
1943 | { | |
451bc8eb CK |
1944 | if (mapping->flags & AMDGPU_PTE_PRT) |
1945 | amdgpu_vm_add_prt_cb(adev, fence); | |
1946 | kfree(mapping); | |
1947 | } | |
284710fa | 1948 | |
451bc8eb CK |
1949 | /** |
1950 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1951 | * | |
1952 | * @adev: amdgpu_device pointer | |
1953 | * @vm: requested vm | |
1954 | * | |
1955 | * Register a cleanup callback to disable PRT support after VM dies. | |
1956 | */ | |
1957 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1958 | { | |
3f3333f8 | 1959 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
451bc8eb CK |
1960 | struct dma_fence *excl, **shared; |
1961 | unsigned i, shared_count; | |
1962 | int r; | |
0b15f2fc | 1963 | |
451bc8eb CK |
1964 | r = reservation_object_get_fences_rcu(resv, &excl, |
1965 | &shared_count, &shared); | |
1966 | if (r) { | |
1967 | /* Not enough memory to grab the fence list, as last resort | |
1968 | * block for all the fences to complete. | |
1969 | */ | |
1970 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1971 | MAX_SCHEDULE_TIMEOUT); | |
1972 | return; | |
284710fa | 1973 | } |
451bc8eb CK |
1974 | |
1975 | /* Add a callback for each fence in the reservation object */ | |
1976 | amdgpu_vm_prt_get(adev); | |
1977 | amdgpu_vm_add_prt_cb(adev, excl); | |
1978 | ||
1979 | for (i = 0; i < shared_count; ++i) { | |
1980 | amdgpu_vm_prt_get(adev); | |
1981 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1982 | } | |
1983 | ||
1984 | kfree(shared); | |
284710fa CK |
1985 | } |
1986 | ||
d38ceaf9 AD |
1987 | /** |
1988 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1989 | * | |
1990 | * @adev: amdgpu_device pointer | |
1991 | * @vm: requested vm | |
f3467818 NH |
1992 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1993 | * or if an error occurred) | |
d38ceaf9 AD |
1994 | * |
1995 | * Make sure all freed BOs are cleared in the PT. | |
1996 | * Returns 0 for success. | |
1997 | * | |
1998 | * PTs have to be reserved and mutex must be locked! | |
1999 | */ | |
2000 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
2001 | struct amdgpu_vm *vm, |
2002 | struct dma_fence **fence) | |
d38ceaf9 AD |
2003 | { |
2004 | struct amdgpu_bo_va_mapping *mapping; | |
f3467818 | 2005 | struct dma_fence *f = NULL; |
d38ceaf9 | 2006 | int r; |
51ac7eec | 2007 | uint64_t init_pte_value = 0; |
d38ceaf9 AD |
2008 | |
2009 | while (!list_empty(&vm->freed)) { | |
2010 | mapping = list_first_entry(&vm->freed, | |
2011 | struct amdgpu_bo_va_mapping, list); | |
2012 | list_del(&mapping->list); | |
e17841b9 | 2013 | |
51ac7eec | 2014 | if (vm->pte_support_ats) |
6d16dac8 | 2015 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec | 2016 | |
570144c6 | 2017 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, |
fc6aa33d | 2018 | mapping->start, mapping->last, |
51ac7eec | 2019 | init_pte_value, 0, &f); |
f3467818 | 2020 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 2021 | if (r) { |
f3467818 | 2022 | dma_fence_put(f); |
d38ceaf9 | 2023 | return r; |
284710fa | 2024 | } |
f3467818 | 2025 | } |
d38ceaf9 | 2026 | |
f3467818 NH |
2027 | if (fence && f) { |
2028 | dma_fence_put(*fence); | |
2029 | *fence = f; | |
2030 | } else { | |
2031 | dma_fence_put(f); | |
d38ceaf9 | 2032 | } |
f3467818 | 2033 | |
d38ceaf9 AD |
2034 | return 0; |
2035 | ||
2036 | } | |
2037 | ||
2038 | /** | |
73fb16e7 | 2039 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
2040 | * |
2041 | * @adev: amdgpu_device pointer | |
2042 | * @vm: requested vm | |
73fb16e7 | 2043 | * @sync: sync object to add fences to |
d38ceaf9 | 2044 | * |
73fb16e7 | 2045 | * Make sure all BOs which are moved are updated in the PTs. |
d38ceaf9 AD |
2046 | * Returns 0 for success. |
2047 | * | |
73fb16e7 | 2048 | * PTs have to be reserved! |
d38ceaf9 | 2049 | */ |
73fb16e7 | 2050 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 2051 | struct amdgpu_vm *vm) |
d38ceaf9 | 2052 | { |
73fb16e7 | 2053 | bool clear; |
91e1a520 | 2054 | int r = 0; |
d38ceaf9 AD |
2055 | |
2056 | spin_lock(&vm->status_lock); | |
27c7b9ae | 2057 | while (!list_empty(&vm->moved)) { |
4e55eb38 CK |
2058 | struct amdgpu_bo_va *bo_va; |
2059 | ||
27c7b9ae | 2060 | bo_va = list_first_entry(&vm->moved, |
ec681545 | 2061 | struct amdgpu_bo_va, base.vm_status); |
d38ceaf9 | 2062 | spin_unlock(&vm->status_lock); |
32b41ac2 | 2063 | |
73fb16e7 CK |
2064 | /* Per VM BOs never need to bo cleared in the page tables */ |
2065 | clear = bo_va->base.bo->tbo.resv != vm->root.base.bo->tbo.resv; | |
2066 | ||
2067 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
d38ceaf9 AD |
2068 | if (r) |
2069 | return r; | |
2070 | ||
2071 | spin_lock(&vm->status_lock); | |
2072 | } | |
2073 | spin_unlock(&vm->status_lock); | |
2074 | ||
91e1a520 | 2075 | return r; |
d38ceaf9 AD |
2076 | } |
2077 | ||
2078 | /** | |
2079 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
2080 | * | |
2081 | * @adev: amdgpu_device pointer | |
2082 | * @vm: requested vm | |
2083 | * @bo: amdgpu buffer object | |
2084 | * | |
8843dbbb | 2085 | * Add @bo into the requested vm. |
d38ceaf9 AD |
2086 | * Add @bo to the list of bos associated with the vm |
2087 | * Returns newly added bo_va or NULL for failure | |
2088 | * | |
2089 | * Object has to be reserved! | |
2090 | */ | |
2091 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
2092 | struct amdgpu_vm *vm, | |
2093 | struct amdgpu_bo *bo) | |
2094 | { | |
2095 | struct amdgpu_bo_va *bo_va; | |
2096 | ||
2097 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2098 | if (bo_va == NULL) { | |
2099 | return NULL; | |
2100 | } | |
ec681545 CK |
2101 | bo_va->base.vm = vm; |
2102 | bo_va->base.bo = bo; | |
2103 | INIT_LIST_HEAD(&bo_va->base.bo_list); | |
2104 | INIT_LIST_HEAD(&bo_va->base.vm_status); | |
2105 | ||
d38ceaf9 | 2106 | bo_va->ref_count = 1; |
7fc11959 CK |
2107 | INIT_LIST_HEAD(&bo_va->valids); |
2108 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2109 | |
a5f6b5b1 | 2110 | if (bo) |
ec681545 | 2111 | list_add_tail(&bo_va->base.bo_list, &bo->va); |
d38ceaf9 AD |
2112 | |
2113 | return bo_va; | |
2114 | } | |
2115 | ||
73fb16e7 CK |
2116 | |
2117 | /** | |
2118 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
2119 | * | |
2120 | * @adev: amdgpu_device pointer | |
2121 | * @bo_va: bo_va to store the address | |
2122 | * @mapping: the mapping to insert | |
2123 | * | |
2124 | * Insert a new mapping into all structures. | |
2125 | */ | |
2126 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2127 | struct amdgpu_bo_va *bo_va, | |
2128 | struct amdgpu_bo_va_mapping *mapping) | |
2129 | { | |
2130 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2131 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2132 | ||
aebc5e6f | 2133 | mapping->bo_va = bo_va; |
73fb16e7 CK |
2134 | list_add(&mapping->list, &bo_va->invalids); |
2135 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2136 | ||
2137 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2138 | amdgpu_vm_prt_get(adev); | |
2139 | ||
2140 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { | |
2141 | spin_lock(&vm->status_lock); | |
481c2e94 CK |
2142 | if (list_empty(&bo_va->base.vm_status)) |
2143 | list_add(&bo_va->base.vm_status, &vm->moved); | |
73fb16e7 CK |
2144 | spin_unlock(&vm->status_lock); |
2145 | } | |
2146 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2147 | } | |
2148 | ||
d38ceaf9 AD |
2149 | /** |
2150 | * amdgpu_vm_bo_map - map bo inside a vm | |
2151 | * | |
2152 | * @adev: amdgpu_device pointer | |
2153 | * @bo_va: bo_va to store the address | |
2154 | * @saddr: where to map the BO | |
2155 | * @offset: requested offset in the BO | |
2156 | * @flags: attributes of pages (read/write/valid/etc.) | |
2157 | * | |
2158 | * Add a mapping of the BO at the specefied addr into the VM. | |
2159 | * Returns 0 for success, error for failure. | |
2160 | * | |
49b02b18 | 2161 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2162 | */ |
2163 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2164 | struct amdgpu_bo_va *bo_va, | |
2165 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2166 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2167 | { |
a9f87f64 | 2168 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2169 | struct amdgpu_bo *bo = bo_va->base.bo; |
2170 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2171 | uint64_t eaddr; |
d38ceaf9 | 2172 | |
0be52de9 CK |
2173 | /* validate the parameters */ |
2174 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2175 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2176 | return -EINVAL; |
0be52de9 | 2177 | |
d38ceaf9 | 2178 | /* make sure object fit at this offset */ |
005ae95e | 2179 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2180 | if (saddr >= eaddr || |
ec681545 | 2181 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 2182 | return -EINVAL; |
d38ceaf9 | 2183 | |
d38ceaf9 AD |
2184 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2185 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2186 | ||
a9f87f64 CK |
2187 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2188 | if (tmp) { | |
d38ceaf9 AD |
2189 | /* bo and tmp overlap, invalid addr */ |
2190 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2191 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2192 | tmp->start, tmp->last + 1); |
663e4577 | 2193 | return -EINVAL; |
d38ceaf9 AD |
2194 | } |
2195 | ||
2196 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2197 | if (!mapping) |
2198 | return -ENOMEM; | |
d38ceaf9 | 2199 | |
a9f87f64 CK |
2200 | mapping->start = saddr; |
2201 | mapping->last = eaddr; | |
d38ceaf9 AD |
2202 | mapping->offset = offset; |
2203 | mapping->flags = flags; | |
2204 | ||
73fb16e7 | 2205 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
2206 | |
2207 | return 0; | |
2208 | } | |
2209 | ||
2210 | /** | |
2211 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2212 | * | |
2213 | * @adev: amdgpu_device pointer | |
2214 | * @bo_va: bo_va to store the address | |
2215 | * @saddr: where to map the BO | |
2216 | * @offset: requested offset in the BO | |
2217 | * @flags: attributes of pages (read/write/valid/etc.) | |
2218 | * | |
2219 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2220 | * mappings as we do so. | |
2221 | * Returns 0 for success, error for failure. | |
2222 | * | |
2223 | * Object has to be reserved and unreserved outside! | |
2224 | */ | |
2225 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2226 | struct amdgpu_bo_va *bo_va, | |
2227 | uint64_t saddr, uint64_t offset, | |
2228 | uint64_t size, uint64_t flags) | |
2229 | { | |
2230 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2231 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
2232 | uint64_t eaddr; |
2233 | int r; | |
2234 | ||
2235 | /* validate the parameters */ | |
2236 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2237 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2238 | return -EINVAL; | |
2239 | ||
2240 | /* make sure object fit at this offset */ | |
2241 | eaddr = saddr + size - 1; | |
2242 | if (saddr >= eaddr || | |
ec681545 | 2243 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
2244 | return -EINVAL; |
2245 | ||
2246 | /* Allocate all the needed memory */ | |
2247 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2248 | if (!mapping) | |
2249 | return -ENOMEM; | |
2250 | ||
ec681545 | 2251 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2252 | if (r) { |
2253 | kfree(mapping); | |
2254 | return r; | |
2255 | } | |
2256 | ||
2257 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2258 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2259 | ||
a9f87f64 CK |
2260 | mapping->start = saddr; |
2261 | mapping->last = eaddr; | |
80f95c57 CK |
2262 | mapping->offset = offset; |
2263 | mapping->flags = flags; | |
2264 | ||
73fb16e7 | 2265 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 2266 | |
d38ceaf9 | 2267 | return 0; |
d38ceaf9 AD |
2268 | } |
2269 | ||
2270 | /** | |
2271 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2272 | * | |
2273 | * @adev: amdgpu_device pointer | |
2274 | * @bo_va: bo_va to remove the address from | |
2275 | * @saddr: where to the BO is mapped | |
2276 | * | |
2277 | * Remove a mapping of the BO at the specefied addr from the VM. | |
2278 | * Returns 0 for success, error for failure. | |
2279 | * | |
49b02b18 | 2280 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2281 | */ |
2282 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2283 | struct amdgpu_bo_va *bo_va, | |
2284 | uint64_t saddr) | |
2285 | { | |
2286 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2287 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2288 | bool valid = true; |
d38ceaf9 | 2289 | |
6c7fc503 | 2290 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2291 | |
7fc11959 | 2292 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2293 | if (mapping->start == saddr) |
d38ceaf9 AD |
2294 | break; |
2295 | } | |
2296 | ||
7fc11959 CK |
2297 | if (&mapping->list == &bo_va->valids) { |
2298 | valid = false; | |
2299 | ||
2300 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2301 | if (mapping->start == saddr) |
7fc11959 CK |
2302 | break; |
2303 | } | |
2304 | ||
32b41ac2 | 2305 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2306 | return -ENOENT; |
d38ceaf9 | 2307 | } |
32b41ac2 | 2308 | |
d38ceaf9 | 2309 | list_del(&mapping->list); |
a9f87f64 | 2310 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2311 | mapping->bo_va = NULL; |
93e3e438 | 2312 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2313 | |
e17841b9 | 2314 | if (valid) |
d38ceaf9 | 2315 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2316 | else |
284710fa CK |
2317 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2318 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2319 | |
2320 | return 0; | |
2321 | } | |
2322 | ||
dc54d3d1 CK |
2323 | /** |
2324 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2325 | * | |
2326 | * @adev: amdgpu_device pointer | |
2327 | * @vm: VM structure to use | |
2328 | * @saddr: start of the range | |
2329 | * @size: size of the range | |
2330 | * | |
2331 | * Remove all mappings in a range, split them as appropriate. | |
2332 | * Returns 0 for success, error for failure. | |
2333 | */ | |
2334 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2335 | struct amdgpu_vm *vm, | |
2336 | uint64_t saddr, uint64_t size) | |
2337 | { | |
2338 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2339 | LIST_HEAD(removed); |
2340 | uint64_t eaddr; | |
2341 | ||
2342 | eaddr = saddr + size - 1; | |
2343 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2344 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2345 | ||
2346 | /* Allocate all the needed memory */ | |
2347 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2348 | if (!before) | |
2349 | return -ENOMEM; | |
27f6d610 | 2350 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2351 | |
2352 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2353 | if (!after) { | |
2354 | kfree(before); | |
2355 | return -ENOMEM; | |
2356 | } | |
27f6d610 | 2357 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2358 | |
2359 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2360 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2361 | while (tmp) { | |
dc54d3d1 | 2362 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2363 | if (tmp->start < saddr) { |
2364 | before->start = tmp->start; | |
2365 | before->last = saddr - 1; | |
dc54d3d1 CK |
2366 | before->offset = tmp->offset; |
2367 | before->flags = tmp->flags; | |
2368 | list_add(&before->list, &tmp->list); | |
2369 | } | |
2370 | ||
2371 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2372 | if (tmp->last > eaddr) { |
2373 | after->start = eaddr + 1; | |
2374 | after->last = tmp->last; | |
dc54d3d1 | 2375 | after->offset = tmp->offset; |
a9f87f64 | 2376 | after->offset += after->start - tmp->start; |
dc54d3d1 CK |
2377 | after->flags = tmp->flags; |
2378 | list_add(&after->list, &tmp->list); | |
2379 | } | |
2380 | ||
2381 | list_del(&tmp->list); | |
2382 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2383 | |
2384 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2385 | } |
2386 | ||
2387 | /* And free them up */ | |
2388 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2389 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2390 | list_del(&tmp->list); |
2391 | ||
a9f87f64 CK |
2392 | if (tmp->start < saddr) |
2393 | tmp->start = saddr; | |
2394 | if (tmp->last > eaddr) | |
2395 | tmp->last = eaddr; | |
dc54d3d1 | 2396 | |
aebc5e6f | 2397 | tmp->bo_va = NULL; |
dc54d3d1 CK |
2398 | list_add(&tmp->list, &vm->freed); |
2399 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2400 | } | |
2401 | ||
27f6d610 JZ |
2402 | /* Insert partial mapping before the range */ |
2403 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2404 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2405 | if (before->flags & AMDGPU_PTE_PRT) |
2406 | amdgpu_vm_prt_get(adev); | |
2407 | } else { | |
2408 | kfree(before); | |
2409 | } | |
2410 | ||
2411 | /* Insert partial mapping after the range */ | |
27f6d610 | 2412 | if (!list_empty(&after->list)) { |
a9f87f64 | 2413 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2414 | if (after->flags & AMDGPU_PTE_PRT) |
2415 | amdgpu_vm_prt_get(adev); | |
2416 | } else { | |
2417 | kfree(after); | |
2418 | } | |
2419 | ||
2420 | return 0; | |
2421 | } | |
2422 | ||
aebc5e6f CK |
2423 | /** |
2424 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2425 | * | |
2426 | * @vm: the requested VM | |
2427 | * | |
2428 | * Find a mapping by it's address. | |
2429 | */ | |
2430 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2431 | uint64_t addr) | |
2432 | { | |
2433 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2434 | } | |
2435 | ||
d38ceaf9 AD |
2436 | /** |
2437 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2438 | * | |
2439 | * @adev: amdgpu_device pointer | |
2440 | * @bo_va: requested bo_va | |
2441 | * | |
8843dbbb | 2442 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2443 | * |
2444 | * Object have to be reserved! | |
2445 | */ | |
2446 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2447 | struct amdgpu_bo_va *bo_va) | |
2448 | { | |
2449 | struct amdgpu_bo_va_mapping *mapping, *next; | |
ec681545 | 2450 | struct amdgpu_vm *vm = bo_va->base.vm; |
d38ceaf9 | 2451 | |
ec681545 | 2452 | list_del(&bo_va->base.bo_list); |
d38ceaf9 | 2453 | |
d38ceaf9 | 2454 | spin_lock(&vm->status_lock); |
ec681545 | 2455 | list_del(&bo_va->base.vm_status); |
d38ceaf9 AD |
2456 | spin_unlock(&vm->status_lock); |
2457 | ||
7fc11959 | 2458 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2459 | list_del(&mapping->list); |
a9f87f64 | 2460 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2461 | mapping->bo_va = NULL; |
93e3e438 | 2462 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2463 | list_add(&mapping->list, &vm->freed); |
2464 | } | |
2465 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2466 | list_del(&mapping->list); | |
a9f87f64 | 2467 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2468 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2469 | bo_va->last_pt_update); | |
d38ceaf9 | 2470 | } |
32b41ac2 | 2471 | |
f54d1867 | 2472 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2473 | kfree(bo_va); |
d38ceaf9 AD |
2474 | } |
2475 | ||
2476 | /** | |
2477 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2478 | * | |
2479 | * @adev: amdgpu_device pointer | |
2480 | * @vm: requested vm | |
2481 | * @bo: amdgpu buffer object | |
2482 | * | |
8843dbbb | 2483 | * Mark @bo as invalid. |
d38ceaf9 AD |
2484 | */ |
2485 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2486 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2487 | { |
ec681545 CK |
2488 | struct amdgpu_vm_bo_base *bo_base; |
2489 | ||
2490 | list_for_each_entry(bo_base, &bo->va, bo_list) { | |
3f3333f8 CK |
2491 | struct amdgpu_vm *vm = bo_base->vm; |
2492 | ||
3d7d4d3a | 2493 | bo_base->moved = true; |
3f3333f8 CK |
2494 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
2495 | spin_lock(&bo_base->vm->status_lock); | |
73fb16e7 CK |
2496 | if (bo->tbo.type == ttm_bo_type_kernel) |
2497 | list_move(&bo_base->vm_status, &vm->evicted); | |
2498 | else | |
2499 | list_move_tail(&bo_base->vm_status, | |
2500 | &vm->evicted); | |
3f3333f8 CK |
2501 | spin_unlock(&bo_base->vm->status_lock); |
2502 | continue; | |
2503 | } | |
2504 | ||
ea09729c CK |
2505 | if (bo->tbo.type == ttm_bo_type_kernel) { |
2506 | spin_lock(&bo_base->vm->status_lock); | |
2507 | if (list_empty(&bo_base->vm_status)) | |
2508 | list_add(&bo_base->vm_status, &vm->relocated); | |
2509 | spin_unlock(&bo_base->vm->status_lock); | |
3f3333f8 | 2510 | continue; |
ea09729c | 2511 | } |
3f3333f8 | 2512 | |
ec681545 CK |
2513 | spin_lock(&bo_base->vm->status_lock); |
2514 | if (list_empty(&bo_base->vm_status)) | |
481c2e94 | 2515 | list_add(&bo_base->vm_status, &vm->moved); |
ec681545 | 2516 | spin_unlock(&bo_base->vm->status_lock); |
d38ceaf9 AD |
2517 | } |
2518 | } | |
2519 | ||
bab4fee7 JZ |
2520 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2521 | { | |
2522 | /* Total bits covered by PD + PTs */ | |
2523 | unsigned bits = ilog2(vm_size) + 18; | |
2524 | ||
2525 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2526 | Above that split equal between PD and PTs */ | |
2527 | if (vm_size <= 8) | |
2528 | return (bits - 9); | |
2529 | else | |
2530 | return ((bits + 3) / 2); | |
2531 | } | |
2532 | ||
d07f14be RH |
2533 | /** |
2534 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2535 | * |
2536 | * @adev: amdgpu_device pointer | |
2537 | * @vm_size: the default vm size if it's set auto | |
2538 | */ | |
fdd5faaa | 2539 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, |
f3368128 CK |
2540 | uint32_t fragment_size_default, unsigned max_level, |
2541 | unsigned max_bits) | |
bab4fee7 | 2542 | { |
36539dce CK |
2543 | uint64_t tmp; |
2544 | ||
2545 | /* adjust vm size first */ | |
f3368128 CK |
2546 | if (amdgpu_vm_size != -1) { |
2547 | unsigned max_size = 1 << (max_bits - 30); | |
2548 | ||
fdd5faaa | 2549 | vm_size = amdgpu_vm_size; |
f3368128 CK |
2550 | if (vm_size > max_size) { |
2551 | dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", | |
2552 | amdgpu_vm_size, max_size); | |
2553 | vm_size = max_size; | |
2554 | } | |
2555 | } | |
fdd5faaa CK |
2556 | |
2557 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
36539dce CK |
2558 | |
2559 | tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); | |
97489129 CK |
2560 | if (amdgpu_vm_block_size != -1) |
2561 | tmp >>= amdgpu_vm_block_size - 9; | |
36539dce CK |
2562 | tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; |
2563 | adev->vm_manager.num_level = min(max_level, (unsigned)tmp); | |
bab4fee7 | 2564 | |
b38f41eb | 2565 | /* block size depends on vm size and hw setup*/ |
97489129 | 2566 | if (amdgpu_vm_block_size != -1) |
bab4fee7 | 2567 | adev->vm_manager.block_size = |
97489129 CK |
2568 | min((unsigned)amdgpu_vm_block_size, max_bits |
2569 | - AMDGPU_GPU_PAGE_SHIFT | |
2570 | - 9 * adev->vm_manager.num_level); | |
2571 | else if (adev->vm_manager.num_level > 1) | |
2572 | adev->vm_manager.block_size = 9; | |
bab4fee7 | 2573 | else |
97489129 | 2574 | adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); |
bab4fee7 | 2575 | |
b38f41eb CK |
2576 | if (amdgpu_vm_fragment_size == -1) |
2577 | adev->vm_manager.fragment_size = fragment_size_default; | |
2578 | else | |
2579 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
d07f14be | 2580 | |
36539dce CK |
2581 | DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", |
2582 | vm_size, adev->vm_manager.num_level + 1, | |
2583 | adev->vm_manager.block_size, | |
fdd5faaa | 2584 | adev->vm_manager.fragment_size); |
bab4fee7 JZ |
2585 | } |
2586 | ||
d38ceaf9 AD |
2587 | /** |
2588 | * amdgpu_vm_init - initialize a vm instance | |
2589 | * | |
2590 | * @adev: amdgpu_device pointer | |
2591 | * @vm: requested vm | |
9a4b7d4c | 2592 | * @vm_context: Indicates if it GFX or Compute context |
d38ceaf9 | 2593 | * |
8843dbbb | 2594 | * Init @vm fields. |
d38ceaf9 | 2595 | */ |
9a4b7d4c | 2596 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 2597 | int vm_context, unsigned int pasid) |
d38ceaf9 AD |
2598 | { |
2599 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
36b32a68 | 2600 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2601 | unsigned ring_instance; |
2602 | struct amdgpu_ring *ring; | |
1b1f42d8 | 2603 | struct drm_sched_rq *rq; |
36bbf3bf | 2604 | int r, i; |
3c824172 | 2605 | u64 flags; |
51ac7eec | 2606 | uint64_t init_pde_value = 0; |
d38ceaf9 | 2607 | |
f808c13f | 2608 | vm->va = RB_ROOT_CACHED; |
031e2983 | 2609 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
36bbf3bf CZ |
2610 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2611 | vm->reserved_vmid[i] = NULL; | |
d38ceaf9 | 2612 | spin_lock_init(&vm->status_lock); |
3f3333f8 | 2613 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2614 | INIT_LIST_HEAD(&vm->relocated); |
27c7b9ae | 2615 | INIT_LIST_HEAD(&vm->moved); |
d38ceaf9 | 2616 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2617 | |
2bd9ccfa | 2618 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2619 | |
2620 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2621 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2622 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
1b1f42d8 LS |
2623 | rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL]; |
2624 | r = drm_sched_entity_init(&ring->sched, &vm->entity, | |
b3eebe3d | 2625 | rq, amdgpu_sched_jobs, NULL); |
2bd9ccfa | 2626 | if (r) |
f566ceb1 | 2627 | return r; |
2bd9ccfa | 2628 | |
51ac7eec YZ |
2629 | vm->pte_support_ats = false; |
2630 | ||
2631 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2632 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2633 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec YZ |
2634 | |
2635 | if (adev->asic_type == CHIP_RAVEN) { | |
2636 | vm->pte_support_ats = true; | |
6d16dac8 YZ |
2637 | init_pde_value = AMDGPU_PTE_DEFAULT_ATC |
2638 | | AMDGPU_PDE_PTE; | |
2639 | ||
51ac7eec YZ |
2640 | } |
2641 | } else | |
9a4b7d4c HK |
2642 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2643 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
2644 | DRM_DEBUG_DRIVER("VM update mode is %s\n", | |
2645 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
2646 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), | |
2647 | "CPU update of VM recommended only for large BAR system\n"); | |
d5884513 | 2648 | vm->last_update = NULL; |
05906dec | 2649 | |
3c824172 HK |
2650 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
2651 | AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
2652 | if (vm->use_cpu_for_update) | |
2653 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
2654 | else | |
2655 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
2656 | AMDGPU_GEM_CREATE_SHADOW); | |
2657 | ||
f566ceb1 | 2658 | r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, |
857d913d | 2659 | AMDGPU_GEM_DOMAIN_VRAM, |
3c824172 | 2660 | flags, |
3f3333f8 | 2661 | NULL, NULL, init_pde_value, &vm->root.base.bo); |
d38ceaf9 | 2662 | if (r) |
2bd9ccfa CK |
2663 | goto error_free_sched_entity; |
2664 | ||
3f3333f8 CK |
2665 | vm->root.base.vm = vm; |
2666 | list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va); | |
2667 | INIT_LIST_HEAD(&vm->root.base.vm_status); | |
0a096fb6 CK |
2668 | |
2669 | if (vm->use_cpu_for_update) { | |
3f3333f8 | 2670 | r = amdgpu_bo_reserve(vm->root.base.bo, false); |
0a096fb6 CK |
2671 | if (r) |
2672 | goto error_free_root; | |
0a096fb6 | 2673 | |
3f3333f8 | 2674 | r = amdgpu_bo_kmap(vm->root.base.bo, NULL); |
ca290da8 | 2675 | amdgpu_bo_unreserve(vm->root.base.bo); |
3f3333f8 CK |
2676 | if (r) |
2677 | goto error_free_root; | |
3f3333f8 | 2678 | } |
d38ceaf9 | 2679 | |
02208441 FK |
2680 | if (pasid) { |
2681 | unsigned long flags; | |
2682 | ||
2683 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2684 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2685 | GFP_ATOMIC); | |
2686 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2687 | if (r < 0) | |
2688 | goto error_free_root; | |
2689 | ||
2690 | vm->pasid = pasid; | |
0a096fb6 CK |
2691 | } |
2692 | ||
a2f14820 | 2693 | INIT_KFIFO(vm->faults); |
c98171cc | 2694 | vm->fault_credit = 16; |
d38ceaf9 AD |
2695 | |
2696 | return 0; | |
2bd9ccfa | 2697 | |
67003a15 | 2698 | error_free_root: |
3f3333f8 CK |
2699 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2700 | amdgpu_bo_unref(&vm->root.base.bo); | |
2701 | vm->root.base.bo = NULL; | |
2bd9ccfa CK |
2702 | |
2703 | error_free_sched_entity: | |
1b1f42d8 | 2704 | drm_sched_entity_fini(&ring->sched, &vm->entity); |
2bd9ccfa CK |
2705 | |
2706 | return r; | |
d38ceaf9 AD |
2707 | } |
2708 | ||
f566ceb1 CK |
2709 | /** |
2710 | * amdgpu_vm_free_levels - free PD/PT levels | |
2711 | * | |
8f19cd78 CK |
2712 | * @adev: amdgpu device structure |
2713 | * @parent: PD/PT starting level to free | |
2714 | * @level: level of parent structure | |
f566ceb1 CK |
2715 | * |
2716 | * Free the page directory or page table level and all sub levels. | |
2717 | */ | |
8f19cd78 CK |
2718 | static void amdgpu_vm_free_levels(struct amdgpu_device *adev, |
2719 | struct amdgpu_vm_pt *parent, | |
2720 | unsigned level) | |
f566ceb1 | 2721 | { |
8f19cd78 | 2722 | unsigned i, num_entries = amdgpu_vm_num_entries(adev, level); |
f566ceb1 | 2723 | |
8f19cd78 CK |
2724 | if (parent->base.bo) { |
2725 | list_del(&parent->base.bo_list); | |
2726 | list_del(&parent->base.vm_status); | |
2727 | amdgpu_bo_unref(&parent->base.bo->shadow); | |
2728 | amdgpu_bo_unref(&parent->base.bo); | |
f566ceb1 CK |
2729 | } |
2730 | ||
8f19cd78 CK |
2731 | if (parent->entries) |
2732 | for (i = 0; i < num_entries; i++) | |
2733 | amdgpu_vm_free_levels(adev, &parent->entries[i], | |
2734 | level + 1); | |
f566ceb1 | 2735 | |
8f19cd78 | 2736 | kvfree(parent->entries); |
f566ceb1 CK |
2737 | } |
2738 | ||
d38ceaf9 AD |
2739 | /** |
2740 | * amdgpu_vm_fini - tear down a vm instance | |
2741 | * | |
2742 | * @adev: amdgpu_device pointer | |
2743 | * @vm: requested vm | |
2744 | * | |
8843dbbb | 2745 | * Tear down @vm. |
d38ceaf9 AD |
2746 | * Unbind the VM and remove all bos from the vm bo list |
2747 | */ | |
2748 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2749 | { | |
2750 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
4388fc2a | 2751 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
2642cf11 | 2752 | struct amdgpu_bo *root; |
a2f14820 | 2753 | u64 fault; |
2642cf11 | 2754 | int i, r; |
d38ceaf9 | 2755 | |
a2f14820 FK |
2756 | /* Clear pending page faults from IH when the VM is destroyed */ |
2757 | while (kfifo_get(&vm->faults, &fault)) | |
2758 | amdgpu_ih_clear_fault(adev, fault); | |
2759 | ||
02208441 FK |
2760 | if (vm->pasid) { |
2761 | unsigned long flags; | |
2762 | ||
2763 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2764 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2765 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2766 | } | |
2767 | ||
1b1f42d8 | 2768 | drm_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 2769 | |
f808c13f | 2770 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
d38ceaf9 AD |
2771 | dev_err(adev->dev, "still active bo inside vm\n"); |
2772 | } | |
f808c13f DB |
2773 | rbtree_postorder_for_each_entry_safe(mapping, tmp, |
2774 | &vm->va.rb_root, rb) { | |
d38ceaf9 | 2775 | list_del(&mapping->list); |
a9f87f64 | 2776 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2777 | kfree(mapping); |
2778 | } | |
2779 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2780 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2781 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2782 | prt_fini_needed = false; |
451bc8eb | 2783 | } |
284710fa | 2784 | |
d38ceaf9 | 2785 | list_del(&mapping->list); |
451bc8eb | 2786 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2787 | } |
2788 | ||
2642cf11 CK |
2789 | root = amdgpu_bo_ref(vm->root.base.bo); |
2790 | r = amdgpu_bo_reserve(root, true); | |
2791 | if (r) { | |
2792 | dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); | |
2793 | } else { | |
8f19cd78 | 2794 | amdgpu_vm_free_levels(adev, &vm->root, 0); |
2642cf11 CK |
2795 | amdgpu_bo_unreserve(root); |
2796 | } | |
2797 | amdgpu_bo_unref(&root); | |
d5884513 | 2798 | dma_fence_put(vm->last_update); |
1e9ef26f CZ |
2799 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2800 | amdgpu_vm_free_reserved_vmid(adev, vm, i); | |
d38ceaf9 | 2801 | } |
ea89f8c9 | 2802 | |
c98171cc FK |
2803 | /** |
2804 | * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID | |
2805 | * | |
2806 | * @adev: amdgpu_device pointer | |
2807 | * @pasid: PASID do identify the VM | |
2808 | * | |
2809 | * This function is expected to be called in interrupt context. Returns | |
2810 | * true if there was fault credit, false otherwise | |
2811 | */ | |
2812 | bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, | |
2813 | unsigned int pasid) | |
2814 | { | |
2815 | struct amdgpu_vm *vm; | |
2816 | ||
2817 | spin_lock(&adev->vm_manager.pasid_lock); | |
2818 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
2819 | spin_unlock(&adev->vm_manager.pasid_lock); | |
2820 | if (!vm) | |
2821 | /* VM not found, can't track fault credit */ | |
2822 | return true; | |
2823 | ||
2824 | /* No lock needed. only accessed by IRQ handler */ | |
2825 | if (!vm->fault_credit) | |
2826 | /* Too many faults in this VM */ | |
2827 | return false; | |
2828 | ||
2829 | vm->fault_credit--; | |
2830 | return true; | |
2831 | } | |
2832 | ||
a9a78b32 CK |
2833 | /** |
2834 | * amdgpu_vm_manager_init - init the VM manager | |
2835 | * | |
2836 | * @adev: amdgpu_device pointer | |
2837 | * | |
2838 | * Initialize the VM manager structures | |
2839 | */ | |
2840 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2841 | { | |
7645670d CK |
2842 | unsigned i, j; |
2843 | ||
2844 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
2845 | struct amdgpu_vm_id_manager *id_mgr = | |
2846 | &adev->vm_manager.id_mgr[i]; | |
a9a78b32 | 2847 | |
7645670d CK |
2848 | mutex_init(&id_mgr->lock); |
2849 | INIT_LIST_HEAD(&id_mgr->ids_lru); | |
c3505770 | 2850 | atomic_set(&id_mgr->reserved_vmid_num, 0); |
a9a78b32 | 2851 | |
7645670d CK |
2852 | /* skip over VMID 0, since it is the system VM */ |
2853 | for (j = 1; j < id_mgr->num_ids; ++j) { | |
2854 | amdgpu_vm_reset_id(adev, i, j); | |
2855 | amdgpu_sync_create(&id_mgr->ids[i].active); | |
2856 | list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); | |
2857 | } | |
971fe9a9 | 2858 | } |
2d55e45a | 2859 | |
f54d1867 CW |
2860 | adev->vm_manager.fence_context = |
2861 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2862 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2863 | adev->vm_manager.seqno[i] = 0; | |
2864 | ||
2d55e45a | 2865 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 2866 | atomic64_set(&adev->vm_manager.client_counter, 0); |
284710fa | 2867 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2868 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
2869 | |
2870 | /* If not overridden by the user, by default, only in large BAR systems | |
2871 | * Compute VM tables will be updated by CPU | |
2872 | */ | |
2873 | #ifdef CONFIG_X86_64 | |
2874 | if (amdgpu_vm_update_mode == -1) { | |
2875 | if (amdgpu_vm_is_large_bar(adev)) | |
2876 | adev->vm_manager.vm_update_mode = | |
2877 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
2878 | else | |
2879 | adev->vm_manager.vm_update_mode = 0; | |
2880 | } else | |
2881 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
2882 | #else | |
2883 | adev->vm_manager.vm_update_mode = 0; | |
2884 | #endif | |
2885 | ||
02208441 FK |
2886 | idr_init(&adev->vm_manager.pasid_idr); |
2887 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
a9a78b32 CK |
2888 | } |
2889 | ||
ea89f8c9 CK |
2890 | /** |
2891 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2892 | * | |
2893 | * @adev: amdgpu_device pointer | |
2894 | * | |
2895 | * Cleanup the VM manager and free resources. | |
2896 | */ | |
2897 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2898 | { | |
7645670d | 2899 | unsigned i, j; |
ea89f8c9 | 2900 | |
02208441 FK |
2901 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); |
2902 | idr_destroy(&adev->vm_manager.pasid_idr); | |
2903 | ||
7645670d CK |
2904 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
2905 | struct amdgpu_vm_id_manager *id_mgr = | |
2906 | &adev->vm_manager.id_mgr[i]; | |
bcb1ba35 | 2907 | |
7645670d CK |
2908 | mutex_destroy(&id_mgr->lock); |
2909 | for (j = 0; j < AMDGPU_NUM_VM; ++j) { | |
2910 | struct amdgpu_vm_id *id = &id_mgr->ids[j]; | |
2911 | ||
2912 | amdgpu_sync_free(&id->active); | |
2913 | dma_fence_put(id->flushed_updates); | |
2914 | dma_fence_put(id->last_flush); | |
2915 | } | |
bcb1ba35 | 2916 | } |
ea89f8c9 | 2917 | } |
cfbcacf4 CZ |
2918 | |
2919 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
2920 | { | |
2921 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
2922 | struct amdgpu_device *adev = dev->dev_private; |
2923 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
2924 | int r; | |
cfbcacf4 CZ |
2925 | |
2926 | switch (args->in.op) { | |
2927 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f CZ |
2928 | /* current, we only have requirement to reserve vmid from gfxhub */ |
2929 | r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm, | |
2930 | AMDGPU_GFXHUB); | |
2931 | if (r) | |
2932 | return r; | |
2933 | break; | |
cfbcacf4 | 2934 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
1e9ef26f | 2935 | amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
2936 | break; |
2937 | default: | |
2938 | return -EINVAL; | |
2939 | } | |
2940 | ||
2941 | return 0; | |
2942 | } |