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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
d38ceaf9 AD |
29 | #include <drm/drmP.h> |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu.h" | |
32 | #include "amdgpu_trace.h" | |
33 | ||
34 | /* | |
35 | * GPUVM | |
36 | * GPUVM is similar to the legacy gart on older asics, however | |
37 | * rather than there being a single global gart table | |
38 | * for the entire GPU, there are multiple VM page tables active | |
39 | * at any given time. The VM page tables can contain a mix | |
40 | * vram pages and system memory pages and system memory pages | |
41 | * can be mapped as snooped (cached system pages) or unsnooped | |
42 | * (uncached system pages). | |
43 | * Each VM has an ID associated with it and there is a page table | |
44 | * associated with each VMID. When execting a command buffer, | |
45 | * the kernel tells the the ring what VMID to use for that command | |
46 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
47 | * The userspace drivers maintain their own address space and the kernel | |
48 | * sets up their pages tables accordingly when they submit their | |
49 | * command buffers and a VMID is assigned. | |
50 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
51 | * SI supports 16. | |
52 | */ | |
53 | ||
f4833c4f HK |
54 | /* Local structure. Encapsulate some VM table update parameters to reduce |
55 | * the number of function parameters | |
56 | */ | |
29efc4f5 | 57 | struct amdgpu_pte_update_params { |
27c5f36f CK |
58 | /* amdgpu device we do this update for */ |
59 | struct amdgpu_device *adev; | |
f4833c4f HK |
60 | /* address where to copy page table entries from */ |
61 | uint64_t src; | |
f4833c4f HK |
62 | /* indirect buffer to fill with commands */ |
63 | struct amdgpu_ib *ib; | |
afef8b8f CK |
64 | /* Function which actually does the update */ |
65 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
66 | uint64_t addr, unsigned count, uint32_t incr, | |
6b777607 | 67 | uint64_t flags); |
4c7e8855 CZ |
68 | /* indicate update pt or its shadow */ |
69 | bool shadow; | |
f4833c4f HK |
70 | }; |
71 | ||
284710fa CK |
72 | /* Helper to disable partial resident texture feature from a fence callback */ |
73 | struct amdgpu_prt_cb { | |
74 | struct amdgpu_device *adev; | |
75 | struct dma_fence_cb cb; | |
76 | }; | |
77 | ||
d38ceaf9 AD |
78 | /** |
79 | * amdgpu_vm_num_pde - return the number of page directory entries | |
80 | * | |
81 | * @adev: amdgpu_device pointer | |
82 | * | |
8843dbbb | 83 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
84 | */ |
85 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
86 | { | |
87 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
88 | } | |
89 | ||
90 | /** | |
91 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
92 | * | |
93 | * @adev: amdgpu_device pointer | |
94 | * | |
8843dbbb | 95 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
96 | */ |
97 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
98 | { | |
99 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
100 | } | |
101 | ||
102 | /** | |
56467ebf | 103 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
104 | * |
105 | * @vm: vm providing the BOs | |
3c0eea6c | 106 | * @validated: head of validation list |
56467ebf | 107 | * @entry: entry to add |
d38ceaf9 AD |
108 | * |
109 | * Add the page directory to the list of BOs to | |
56467ebf | 110 | * validate for command submission. |
d38ceaf9 | 111 | */ |
56467ebf CK |
112 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
113 | struct list_head *validated, | |
114 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 115 | { |
56467ebf | 116 | entry->robj = vm->page_directory; |
56467ebf CK |
117 | entry->priority = 0; |
118 | entry->tv.bo = &vm->page_directory->tbo; | |
119 | entry->tv.shared = true; | |
2f568dbd | 120 | entry->user_pages = NULL; |
56467ebf CK |
121 | list_add(&entry->tv.head, validated); |
122 | } | |
d38ceaf9 | 123 | |
56467ebf | 124 | /** |
f7da30d9 | 125 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
56467ebf | 126 | * |
5a712a87 | 127 | * @adev: amdgpu device pointer |
56467ebf | 128 | * @vm: vm providing the BOs |
f7da30d9 CK |
129 | * @validate: callback to do the validation |
130 | * @param: parameter for the validation callback | |
d38ceaf9 | 131 | * |
f7da30d9 | 132 | * Validate the page table BOs on command submission if neccessary. |
d38ceaf9 | 133 | */ |
f7da30d9 CK |
134 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
135 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
136 | void *param) | |
d38ceaf9 | 137 | { |
5a712a87 | 138 | uint64_t num_evictions; |
ee1782c3 | 139 | unsigned i; |
f7da30d9 | 140 | int r; |
d38ceaf9 | 141 | |
5a712a87 CK |
142 | /* We only need to validate the page tables |
143 | * if they aren't already valid. | |
144 | */ | |
145 | num_evictions = atomic64_read(&adev->num_evictions); | |
146 | if (num_evictions == vm->last_eviction_counter) | |
f7da30d9 | 147 | return 0; |
5a712a87 | 148 | |
d38ceaf9 | 149 | /* add the vm page table to the list */ |
ee1782c3 | 150 | for (i = 0; i <= vm->max_pde_used; ++i) { |
914b4dce | 151 | struct amdgpu_bo *bo = vm->page_tables[i].bo; |
ee1782c3 | 152 | |
914b4dce | 153 | if (!bo) |
d38ceaf9 AD |
154 | continue; |
155 | ||
914b4dce | 156 | r = validate(param, bo); |
f7da30d9 CK |
157 | if (r) |
158 | return r; | |
d38ceaf9 | 159 | } |
eceb8a15 | 160 | |
f7da30d9 | 161 | return 0; |
eceb8a15 CK |
162 | } |
163 | ||
164 | /** | |
165 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
166 | * | |
167 | * @adev: amdgpu device instance | |
168 | * @vm: vm providing the BOs | |
169 | * | |
170 | * Move the PT BOs to the tail of the LRU. | |
171 | */ | |
172 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
173 | struct amdgpu_vm *vm) | |
174 | { | |
175 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
176 | unsigned i; | |
177 | ||
178 | spin_lock(&glob->lru_lock); | |
179 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
914b4dce | 180 | struct amdgpu_bo *bo = vm->page_tables[i].bo; |
eceb8a15 | 181 | |
914b4dce | 182 | if (!bo) |
eceb8a15 CK |
183 | continue; |
184 | ||
914b4dce | 185 | ttm_bo_move_to_lru_tail(&bo->tbo); |
eceb8a15 CK |
186 | } |
187 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
188 | } |
189 | ||
663e4577 CK |
190 | /** |
191 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
192 | * | |
193 | * @adev: amdgpu_device pointer | |
194 | * @vm: VM to allocate page tables for | |
195 | * @saddr: Start address which needs to be allocated | |
196 | * @size: Size from start address we need. | |
197 | * | |
198 | * Make sure the page tables are allocated. | |
199 | */ | |
200 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
201 | struct amdgpu_vm *vm, | |
202 | uint64_t saddr, uint64_t size) | |
203 | { | |
204 | unsigned last_pfn, pt_idx; | |
205 | uint64_t eaddr; | |
206 | int r; | |
207 | ||
208 | /* validate the parameters */ | |
209 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
210 | return -EINVAL; | |
211 | ||
212 | eaddr = saddr + size - 1; | |
213 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
214 | if (last_pfn >= adev->vm_manager.max_pfn) { | |
215 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
216 | last_pfn, adev->vm_manager.max_pfn); | |
217 | return -EINVAL; | |
218 | } | |
219 | ||
220 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
221 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
222 | ||
223 | saddr >>= amdgpu_vm_block_size; | |
224 | eaddr >>= amdgpu_vm_block_size; | |
225 | ||
226 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
227 | ||
228 | if (eaddr > vm->max_pde_used) | |
229 | vm->max_pde_used = eaddr; | |
230 | ||
231 | /* walk over the address space and allocate the page tables */ | |
232 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
233 | struct reservation_object *resv = vm->page_directory->tbo.resv; | |
234 | struct amdgpu_bo *pt; | |
235 | ||
236 | if (vm->page_tables[pt_idx].bo) | |
237 | continue; | |
238 | ||
239 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, | |
240 | AMDGPU_GPU_PAGE_SIZE, true, | |
241 | AMDGPU_GEM_DOMAIN_VRAM, | |
242 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
243 | AMDGPU_GEM_CREATE_SHADOW | | |
244 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
245 | AMDGPU_GEM_CREATE_VRAM_CLEARED, | |
246 | NULL, resv, &pt); | |
247 | if (r) | |
248 | return r; | |
249 | ||
250 | /* Keep a reference to the page table to avoid freeing | |
251 | * them up in the wrong order. | |
252 | */ | |
253 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
254 | ||
255 | vm->page_tables[pt_idx].bo = pt; | |
256 | vm->page_tables[pt_idx].addr = 0; | |
257 | } | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
192b7dcb CZ |
262 | static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev, |
263 | struct amdgpu_vm_id *id) | |
264 | { | |
265 | return id->current_gpu_reset_count != | |
266 | atomic_read(&adev->gpu_reset_counter) ? true : false; | |
267 | } | |
268 | ||
d38ceaf9 AD |
269 | /** |
270 | * amdgpu_vm_grab_id - allocate the next free VMID | |
271 | * | |
d38ceaf9 | 272 | * @vm: vm to allocate id for |
7f8a5290 CK |
273 | * @ring: ring we want to submit job to |
274 | * @sync: sync object where we add dependencies | |
94dd0a4a | 275 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 276 | * |
7f8a5290 | 277 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 278 | */ |
7f8a5290 | 279 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
f54d1867 | 280 | struct amdgpu_sync *sync, struct dma_fence *fence, |
fd53be30 | 281 | struct amdgpu_job *job) |
d38ceaf9 | 282 | { |
d38ceaf9 | 283 | struct amdgpu_device *adev = ring->adev; |
090b767e | 284 | uint64_t fence_context = adev->fence_context + ring->idx; |
f54d1867 | 285 | struct dma_fence *updates = sync->last_vm_update; |
8d76001e | 286 | struct amdgpu_vm_id *id, *idle; |
f54d1867 | 287 | struct dma_fence **fences; |
1fbb2e92 CK |
288 | unsigned i; |
289 | int r = 0; | |
290 | ||
291 | fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids, | |
292 | GFP_KERNEL); | |
293 | if (!fences) | |
294 | return -ENOMEM; | |
d38ceaf9 | 295 | |
94dd0a4a CK |
296 | mutex_lock(&adev->vm_manager.lock); |
297 | ||
36fd7c5c | 298 | /* Check if we have an idle VMID */ |
1fbb2e92 | 299 | i = 0; |
8d76001e | 300 | list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) { |
1fbb2e92 CK |
301 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
302 | if (!fences[i]) | |
36fd7c5c | 303 | break; |
1fbb2e92 | 304 | ++i; |
36fd7c5c CK |
305 | } |
306 | ||
1fbb2e92 | 307 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
8d76001e | 308 | if (&idle->list == &adev->vm_manager.ids_lru) { |
1fbb2e92 CK |
309 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
310 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
f54d1867 | 311 | struct dma_fence_array *array; |
1fbb2e92 CK |
312 | unsigned j; |
313 | ||
314 | for (j = 0; j < i; ++j) | |
f54d1867 | 315 | dma_fence_get(fences[j]); |
1fbb2e92 | 316 | |
f54d1867 | 317 | array = dma_fence_array_create(i, fences, fence_context, |
1fbb2e92 CK |
318 | seqno, true); |
319 | if (!array) { | |
320 | for (j = 0; j < i; ++j) | |
f54d1867 | 321 | dma_fence_put(fences[j]); |
1fbb2e92 CK |
322 | kfree(fences); |
323 | r = -ENOMEM; | |
324 | goto error; | |
325 | } | |
326 | ||
327 | ||
328 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
f54d1867 | 329 | dma_fence_put(&array->base); |
1fbb2e92 CK |
330 | if (r) |
331 | goto error; | |
332 | ||
333 | mutex_unlock(&adev->vm_manager.lock); | |
334 | return 0; | |
335 | ||
336 | } | |
337 | kfree(fences); | |
338 | ||
fd53be30 | 339 | job->vm_needs_flush = true; |
1fbb2e92 CK |
340 | /* Check if we can use a VMID already assigned to this VM */ |
341 | i = ring->idx; | |
342 | do { | |
f54d1867 | 343 | struct dma_fence *flushed; |
1fbb2e92 CK |
344 | |
345 | id = vm->ids[i++]; | |
346 | if (i == AMDGPU_MAX_RINGS) | |
347 | i = 0; | |
8d76001e | 348 | |
1fbb2e92 CK |
349 | /* Check all the prerequisites to using this VMID */ |
350 | if (!id) | |
351 | continue; | |
192b7dcb | 352 | if (amdgpu_vm_is_gpu_reset(adev, id)) |
6adb0513 | 353 | continue; |
1fbb2e92 CK |
354 | |
355 | if (atomic64_read(&id->owner) != vm->client_id) | |
356 | continue; | |
357 | ||
fd53be30 | 358 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
359 | continue; |
360 | ||
090b767e CK |
361 | if (!id->last_flush) |
362 | continue; | |
363 | ||
364 | if (id->last_flush->context != fence_context && | |
f54d1867 | 365 | !dma_fence_is_signaled(id->last_flush)) |
1fbb2e92 CK |
366 | continue; |
367 | ||
368 | flushed = id->flushed_updates; | |
369 | if (updates && | |
f54d1867 | 370 | (!flushed || dma_fence_is_later(updates, flushed))) |
1fbb2e92 CK |
371 | continue; |
372 | ||
3dab83be CK |
373 | /* Good we can use this VMID. Remember this submission as |
374 | * user of the VMID. | |
375 | */ | |
1fbb2e92 CK |
376 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
377 | if (r) | |
378 | goto error; | |
8d76001e | 379 | |
6adb0513 | 380 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
1fbb2e92 CK |
381 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
382 | vm->ids[ring->idx] = id; | |
8d76001e | 383 | |
fd53be30 CZ |
384 | job->vm_id = id - adev->vm_manager.ids; |
385 | job->vm_needs_flush = false; | |
0c0fdf14 | 386 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
8d76001e | 387 | |
1fbb2e92 CK |
388 | mutex_unlock(&adev->vm_manager.lock); |
389 | return 0; | |
8d76001e | 390 | |
1fbb2e92 | 391 | } while (i != ring->idx); |
8d76001e | 392 | |
1fbb2e92 CK |
393 | /* Still no ID to use? Then use the idle one found earlier */ |
394 | id = idle; | |
8e9fbeb5 | 395 | |
1fbb2e92 CK |
396 | /* Remember this submission as user of the VMID */ |
397 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
398 | if (r) |
399 | goto error; | |
94dd0a4a | 400 | |
f54d1867 CW |
401 | dma_fence_put(id->first); |
402 | id->first = dma_fence_get(fence); | |
94dd0a4a | 403 | |
f54d1867 | 404 | dma_fence_put(id->last_flush); |
41d9eb2c CK |
405 | id->last_flush = NULL; |
406 | ||
f54d1867 CW |
407 | dma_fence_put(id->flushed_updates); |
408 | id->flushed_updates = dma_fence_get(updates); | |
94dd0a4a | 409 | |
fd53be30 | 410 | id->pd_gpu_addr = job->vm_pd_addr; |
b46b8a87 | 411 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
832a902f | 412 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
0ea54b9b | 413 | atomic64_set(&id->owner, vm->client_id); |
832a902f | 414 | vm->ids[ring->idx] = id; |
d38ceaf9 | 415 | |
fd53be30 | 416 | job->vm_id = id - adev->vm_manager.ids; |
0c0fdf14 | 417 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
832a902f CK |
418 | |
419 | error: | |
94dd0a4a | 420 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 421 | return r; |
d38ceaf9 AD |
422 | } |
423 | ||
93dcc37d AD |
424 | static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) |
425 | { | |
426 | struct amdgpu_device *adev = ring->adev; | |
a1255107 | 427 | const struct amdgpu_ip_block *ip_block; |
93dcc37d | 428 | |
21cd942e | 429 | if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) |
93dcc37d AD |
430 | /* only compute rings */ |
431 | return false; | |
432 | ||
433 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
434 | if (!ip_block) | |
435 | return false; | |
436 | ||
a1255107 | 437 | if (ip_block->version->major <= 7) { |
93dcc37d AD |
438 | /* gfx7 has no workaround */ |
439 | return true; | |
a1255107 | 440 | } else if (ip_block->version->major == 8) { |
93dcc37d AD |
441 | if (adev->gfx.mec_fw_version >= 673) |
442 | /* gfx8 is fixed in MEC firmware 673 */ | |
443 | return false; | |
444 | else | |
445 | return true; | |
446 | } | |
447 | return false; | |
448 | } | |
449 | ||
d38ceaf9 AD |
450 | /** |
451 | * amdgpu_vm_flush - hardware flush the vm | |
452 | * | |
453 | * @ring: ring to use for flush | |
cffadc83 | 454 | * @vm_id: vmid number to use |
4ff37a83 | 455 | * @pd_addr: address of the page directory |
d38ceaf9 | 456 | * |
4ff37a83 | 457 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 458 | */ |
fd53be30 | 459 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) |
d38ceaf9 | 460 | { |
971fe9a9 | 461 | struct amdgpu_device *adev = ring->adev; |
fd53be30 | 462 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id]; |
d564a06e | 463 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
464 | id->gds_base != job->gds_base || |
465 | id->gds_size != job->gds_size || | |
466 | id->gws_base != job->gws_base || | |
467 | id->gws_size != job->gws_size || | |
468 | id->oa_base != job->oa_base || | |
469 | id->oa_size != job->oa_size); | |
41d9eb2c | 470 | int r; |
d564a06e CK |
471 | |
472 | if (ring->funcs->emit_pipeline_sync && ( | |
fd53be30 | 473 | job->vm_needs_flush || gds_switch_needed || |
93dcc37d | 474 | amdgpu_vm_ring_has_compute_vm_bug(ring))) |
d564a06e | 475 | amdgpu_ring_emit_pipeline_sync(ring); |
971fe9a9 | 476 | |
aa1c8900 CZ |
477 | if (ring->funcs->emit_vm_flush && (job->vm_needs_flush || |
478 | amdgpu_vm_is_gpu_reset(adev, id))) { | |
f54d1867 | 479 | struct dma_fence *fence; |
41d9eb2c | 480 | |
fd53be30 CZ |
481 | trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id); |
482 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
41d9eb2c | 483 | |
3dab83be CK |
484 | r = amdgpu_fence_emit(ring, &fence); |
485 | if (r) | |
486 | return r; | |
487 | ||
41d9eb2c | 488 | mutex_lock(&adev->vm_manager.lock); |
f54d1867 | 489 | dma_fence_put(id->last_flush); |
3dab83be | 490 | id->last_flush = fence; |
41d9eb2c | 491 | mutex_unlock(&adev->vm_manager.lock); |
d38ceaf9 | 492 | } |
cffadc83 | 493 | |
d564a06e | 494 | if (gds_switch_needed) { |
fd53be30 CZ |
495 | id->gds_base = job->gds_base; |
496 | id->gds_size = job->gds_size; | |
497 | id->gws_base = job->gws_base; | |
498 | id->gws_size = job->gws_size; | |
499 | id->oa_base = job->oa_base; | |
500 | id->oa_size = job->oa_size; | |
501 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, | |
502 | job->gds_base, job->gds_size, | |
503 | job->gws_base, job->gws_size, | |
504 | job->oa_base, job->oa_size); | |
971fe9a9 | 505 | } |
41d9eb2c CK |
506 | |
507 | return 0; | |
971fe9a9 CK |
508 | } |
509 | ||
510 | /** | |
511 | * amdgpu_vm_reset_id - reset VMID to zero | |
512 | * | |
513 | * @adev: amdgpu device structure | |
514 | * @vm_id: vmid number to use | |
515 | * | |
516 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
517 | */ | |
518 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
519 | { | |
bcb1ba35 CK |
520 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
521 | ||
522 | id->gds_base = 0; | |
523 | id->gds_size = 0; | |
524 | id->gws_base = 0; | |
525 | id->gws_size = 0; | |
526 | id->oa_base = 0; | |
527 | id->oa_size = 0; | |
d38ceaf9 AD |
528 | } |
529 | ||
d38ceaf9 AD |
530 | /** |
531 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
532 | * | |
533 | * @vm: requested vm | |
534 | * @bo: requested buffer object | |
535 | * | |
8843dbbb | 536 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
537 | * Search inside the @bos vm list for the requested vm |
538 | * Returns the found bo_va or NULL if none is found | |
539 | * | |
540 | * Object has to be reserved! | |
541 | */ | |
542 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
543 | struct amdgpu_bo *bo) | |
544 | { | |
545 | struct amdgpu_bo_va *bo_va; | |
546 | ||
547 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
548 | if (bo_va->vm == vm) { | |
549 | return bo_va; | |
550 | } | |
551 | } | |
552 | return NULL; | |
553 | } | |
554 | ||
555 | /** | |
afef8b8f | 556 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 557 | * |
29efc4f5 | 558 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
559 | * @pe: addr of the page entry |
560 | * @addr: dst addr to write into pe | |
561 | * @count: number of page entries to update | |
562 | * @incr: increase next addr by incr bytes | |
563 | * @flags: hw access flags | |
d38ceaf9 AD |
564 | * |
565 | * Traces the parameters and calls the right asic functions | |
566 | * to setup the page table using the DMA. | |
567 | */ | |
afef8b8f CK |
568 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
569 | uint64_t pe, uint64_t addr, | |
570 | unsigned count, uint32_t incr, | |
6b777607 | 571 | uint64_t flags) |
d38ceaf9 | 572 | { |
ec2f05f0 | 573 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 574 | |
afef8b8f | 575 | if (count < 3) { |
de9ea7bd CK |
576 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
577 | addr | flags, count, incr); | |
d38ceaf9 AD |
578 | |
579 | } else { | |
27c5f36f | 580 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
581 | count, incr, flags); |
582 | } | |
583 | } | |
584 | ||
afef8b8f CK |
585 | /** |
586 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
587 | * | |
588 | * @params: see amdgpu_pte_update_params definition | |
589 | * @pe: addr of the page entry | |
590 | * @addr: dst addr to write into pe | |
591 | * @count: number of page entries to update | |
592 | * @incr: increase next addr by incr bytes | |
593 | * @flags: hw access flags | |
594 | * | |
595 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
596 | */ | |
597 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
598 | uint64_t pe, uint64_t addr, | |
599 | unsigned count, uint32_t incr, | |
6b777607 | 600 | uint64_t flags) |
afef8b8f | 601 | { |
ec2f05f0 | 602 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 603 | |
ec2f05f0 CK |
604 | |
605 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
606 | ||
607 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
608 | } |
609 | ||
d38ceaf9 | 610 | /** |
b07c9d2a | 611 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 612 | * |
b07c9d2a | 613 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
614 | * @addr: the unmapped addr |
615 | * | |
616 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 617 | * to and return the pointer for the page table entry. |
d38ceaf9 | 618 | */ |
de9ea7bd | 619 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
620 | { |
621 | uint64_t result; | |
622 | ||
de9ea7bd CK |
623 | /* page table offset */ |
624 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 625 | |
de9ea7bd CK |
626 | /* in case cpu page size != gpu page size*/ |
627 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 628 | |
b07c9d2a | 629 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
630 | |
631 | return result; | |
632 | } | |
633 | ||
f8991bab CK |
634 | /* |
635 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
636 | * | |
637 | * @adev: amdgpu_device pointer | |
638 | * @vm: requested vm | |
639 | * @start: start of GPU address range | |
640 | * @end: end of GPU address range | |
641 | * | |
642 | * Allocates new page tables if necessary | |
643 | * and updates the page directory. | |
644 | * Returns 0 for success, error for failure. | |
645 | */ | |
646 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
647 | struct amdgpu_vm *vm) | |
d38ceaf9 | 648 | { |
f8991bab | 649 | struct amdgpu_bo *shadow; |
2d55e45a | 650 | struct amdgpu_ring *ring; |
f8991bab | 651 | uint64_t pd_addr, shadow_addr; |
d38ceaf9 | 652 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; |
f8991bab | 653 | uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; |
d38ceaf9 | 654 | unsigned count = 0, pt_idx, ndw; |
d71518b5 | 655 | struct amdgpu_job *job; |
29efc4f5 | 656 | struct amdgpu_pte_update_params params; |
f54d1867 | 657 | struct dma_fence *fence = NULL; |
d5fc5e82 | 658 | |
d38ceaf9 AD |
659 | int r; |
660 | ||
2d55e45a | 661 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
f8991bab | 662 | shadow = vm->page_directory->shadow; |
2d55e45a | 663 | |
d38ceaf9 AD |
664 | /* padding, etc. */ |
665 | ndw = 64; | |
666 | ||
667 | /* assume the worst case */ | |
668 | ndw += vm->max_pde_used * 6; | |
669 | ||
f8991bab CK |
670 | pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); |
671 | if (shadow) { | |
672 | r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); | |
673 | if (r) | |
674 | return r; | |
675 | shadow_addr = amdgpu_bo_gpu_offset(shadow); | |
676 | ndw *= 2; | |
677 | } else { | |
678 | shadow_addr = 0; | |
679 | } | |
680 | ||
d71518b5 CK |
681 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
682 | if (r) | |
d38ceaf9 | 683 | return r; |
d71518b5 | 684 | |
27c5f36f CK |
685 | memset(¶ms, 0, sizeof(params)); |
686 | params.adev = adev; | |
29efc4f5 | 687 | params.ib = &job->ibs[0]; |
d38ceaf9 AD |
688 | |
689 | /* walk over the address space and update the page directory */ | |
690 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
914b4dce | 691 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo; |
d38ceaf9 AD |
692 | uint64_t pde, pt; |
693 | ||
694 | if (bo == NULL) | |
695 | continue; | |
696 | ||
0fc8683e | 697 | if (bo->shadow) { |
f8991bab | 698 | struct amdgpu_bo *pt_shadow = bo->shadow; |
0fc8683e | 699 | |
f8991bab CK |
700 | r = amdgpu_ttm_bind(&pt_shadow->tbo, |
701 | &pt_shadow->tbo.mem); | |
0fc8683e CK |
702 | if (r) |
703 | return r; | |
704 | } | |
705 | ||
d38ceaf9 | 706 | pt = amdgpu_bo_gpu_offset(bo); |
f8991bab CK |
707 | if (vm->page_tables[pt_idx].addr == pt) |
708 | continue; | |
709 | ||
710 | vm->page_tables[pt_idx].addr = pt; | |
d38ceaf9 AD |
711 | |
712 | pde = pd_addr + pt_idx * 8; | |
713 | if (((last_pde + 8 * count) != pde) || | |
96105e53 CK |
714 | ((last_pt + incr * count) != pt) || |
715 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
d38ceaf9 AD |
716 | |
717 | if (count) { | |
f8991bab CK |
718 | if (shadow) |
719 | amdgpu_vm_do_set_ptes(¶ms, | |
720 | last_shadow, | |
721 | last_pt, count, | |
722 | incr, | |
723 | AMDGPU_PTE_VALID); | |
724 | ||
afef8b8f CK |
725 | amdgpu_vm_do_set_ptes(¶ms, last_pde, |
726 | last_pt, count, incr, | |
727 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
728 | } |
729 | ||
730 | count = 1; | |
731 | last_pde = pde; | |
f8991bab | 732 | last_shadow = shadow_addr + pt_idx * 8; |
d38ceaf9 AD |
733 | last_pt = pt; |
734 | } else { | |
735 | ++count; | |
736 | } | |
737 | } | |
738 | ||
f8991bab CK |
739 | if (count) { |
740 | if (vm->page_directory->shadow) | |
741 | amdgpu_vm_do_set_ptes(¶ms, last_shadow, last_pt, | |
742 | count, incr, AMDGPU_PTE_VALID); | |
743 | ||
afef8b8f CK |
744 | amdgpu_vm_do_set_ptes(¶ms, last_pde, last_pt, |
745 | count, incr, AMDGPU_PTE_VALID); | |
f8991bab | 746 | } |
d38ceaf9 | 747 | |
f8991bab CK |
748 | if (params.ib->length_dw == 0) { |
749 | amdgpu_job_free(job); | |
750 | return 0; | |
751 | } | |
752 | ||
753 | amdgpu_ring_pad_ib(ring, params.ib); | |
754 | amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, | |
755 | AMDGPU_FENCE_OWNER_VM); | |
756 | if (shadow) | |
757 | amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv, | |
e86f9cee | 758 | AMDGPU_FENCE_OWNER_VM); |
05906dec | 759 | |
f8991bab CK |
760 | WARN_ON(params.ib->length_dw > ndw); |
761 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
762 | AMDGPU_FENCE_OWNER_VM, &fence); | |
763 | if (r) | |
764 | goto error_free; | |
d5fc5e82 | 765 | |
f8991bab | 766 | amdgpu_bo_fence(vm->page_directory, fence, true); |
220196b3 DA |
767 | dma_fence_put(vm->page_directory_fence); |
768 | vm->page_directory_fence = dma_fence_get(fence); | |
769 | dma_fence_put(fence); | |
d38ceaf9 AD |
770 | |
771 | return 0; | |
d5fc5e82 CZ |
772 | |
773 | error_free: | |
d71518b5 | 774 | amdgpu_job_free(job); |
4af9f07c | 775 | return r; |
d38ceaf9 AD |
776 | } |
777 | ||
d38ceaf9 AD |
778 | /** |
779 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
780 | * | |
29efc4f5 | 781 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
782 | * @vm: requested vm |
783 | * @start: start of GPU address range | |
784 | * @end: end of GPU address range | |
677131a1 | 785 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
786 | * @flags: mapping flags |
787 | * | |
8843dbbb | 788 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 789 | */ |
27c5f36f | 790 | static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 791 | struct amdgpu_vm *vm, |
a1e08d3b | 792 | uint64_t start, uint64_t end, |
6b777607 | 793 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 794 | { |
31f6c1fe CK |
795 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
796 | ||
92696dd5 | 797 | uint64_t cur_pe_start, cur_nptes, cur_dst; |
677131a1 | 798 | uint64_t addr; /* next GPU address to be updated */ |
21718497 AX |
799 | uint64_t pt_idx; |
800 | struct amdgpu_bo *pt; | |
801 | unsigned nptes; /* next number of ptes to be updated */ | |
802 | uint64_t next_pe_start; | |
803 | ||
804 | /* initialize the variables */ | |
805 | addr = start; | |
806 | pt_idx = addr >> amdgpu_vm_block_size; | |
914b4dce | 807 | pt = vm->page_tables[pt_idx].bo; |
4c7e8855 CZ |
808 | if (params->shadow) { |
809 | if (!pt->shadow) | |
810 | return; | |
914b4dce | 811 | pt = pt->shadow; |
4c7e8855 | 812 | } |
21718497 AX |
813 | if ((addr & ~mask) == (end & ~mask)) |
814 | nptes = end - addr; | |
815 | else | |
816 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
817 | ||
818 | cur_pe_start = amdgpu_bo_gpu_offset(pt); | |
819 | cur_pe_start += (addr & mask) * 8; | |
92696dd5 | 820 | cur_nptes = nptes; |
21718497 AX |
821 | cur_dst = dst; |
822 | ||
823 | /* for next ptb*/ | |
824 | addr += nptes; | |
825 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
d38ceaf9 AD |
826 | |
827 | /* walk over the address space and update the page tables */ | |
21718497 AX |
828 | while (addr < end) { |
829 | pt_idx = addr >> amdgpu_vm_block_size; | |
914b4dce | 830 | pt = vm->page_tables[pt_idx].bo; |
4c7e8855 CZ |
831 | if (params->shadow) { |
832 | if (!pt->shadow) | |
833 | return; | |
914b4dce | 834 | pt = pt->shadow; |
4c7e8855 | 835 | } |
d38ceaf9 AD |
836 | |
837 | if ((addr & ~mask) == (end & ~mask)) | |
838 | nptes = end - addr; | |
839 | else | |
840 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
841 | ||
677131a1 AX |
842 | next_pe_start = amdgpu_bo_gpu_offset(pt); |
843 | next_pe_start += (addr & mask) * 8; | |
d38ceaf9 | 844 | |
96105e53 CK |
845 | if ((cur_pe_start + 8 * cur_nptes) == next_pe_start && |
846 | ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
3a6f8e0c | 847 | /* The next ptb is consecutive to current ptb. |
afef8b8f | 848 | * Don't call the update function now. |
3a6f8e0c AX |
849 | * Will update two ptbs together in future. |
850 | */ | |
92696dd5 | 851 | cur_nptes += nptes; |
3a6f8e0c | 852 | } else { |
afef8b8f CK |
853 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
854 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 | 855 | |
677131a1 | 856 | cur_pe_start = next_pe_start; |
92696dd5 | 857 | cur_nptes = nptes; |
677131a1 | 858 | cur_dst = dst; |
d38ceaf9 AD |
859 | } |
860 | ||
21718497 | 861 | /* for next ptb*/ |
d38ceaf9 AD |
862 | addr += nptes; |
863 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
864 | } | |
865 | ||
afef8b8f CK |
866 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
867 | AMDGPU_GPU_PAGE_SIZE, flags); | |
92696dd5 CK |
868 | } |
869 | ||
870 | /* | |
871 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
872 | * | |
873 | * @params: see amdgpu_pte_update_params definition | |
874 | * @vm: requested vm | |
875 | * @start: first PTE to handle | |
876 | * @end: last PTE to handle | |
877 | * @dst: addr those PTEs should point to | |
878 | * @flags: hw mapping flags | |
879 | */ | |
880 | static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, | |
881 | struct amdgpu_vm *vm, | |
882 | uint64_t start, uint64_t end, | |
6b777607 | 883 | uint64_t dst, uint64_t flags) |
92696dd5 CK |
884 | { |
885 | /** | |
886 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
887 | * field in the PTE. When this field is set to a non-zero value, page | |
888 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
889 | * flags are considered valid for all PTEs within the fragment range | |
890 | * and corresponding mappings are assumed to be physically contiguous. | |
891 | * | |
892 | * The L1 TLB can store a single PTE for the whole fragment, | |
893 | * significantly increasing the space available for translation | |
894 | * caching. This leads to large improvements in throughput when the | |
895 | * TLB is under pressure. | |
896 | * | |
897 | * The L2 TLB distributes small and large fragments into two | |
898 | * asymmetric partitions. The large fragment cache is significantly | |
899 | * larger. Thus, we try to use large fragments wherever possible. | |
900 | * Userspace can support this by aligning virtual base address and | |
901 | * allocation size to the fragment size. | |
902 | */ | |
903 | ||
8036617e CK |
904 | /* SI and newer are optimized for 64KB */ |
905 | uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG); | |
906 | uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG; | |
92696dd5 CK |
907 | |
908 | uint64_t frag_start = ALIGN(start, frag_align); | |
909 | uint64_t frag_end = end & ~(frag_align - 1); | |
910 | ||
911 | /* system pages are non continuously */ | |
b7fc2cbd | 912 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
92696dd5 CK |
913 | (frag_start >= frag_end)) { |
914 | ||
915 | amdgpu_vm_update_ptes(params, vm, start, end, dst, flags); | |
916 | return; | |
917 | } | |
918 | ||
919 | /* handle the 4K area at the beginning */ | |
920 | if (start != frag_start) { | |
921 | amdgpu_vm_update_ptes(params, vm, start, frag_start, | |
922 | dst, flags); | |
923 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; | |
924 | } | |
925 | ||
926 | /* handle the area in the middle */ | |
927 | amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst, | |
8036617e | 928 | flags | frag_flags); |
92696dd5 CK |
929 | |
930 | /* handle the 4K area at the end */ | |
931 | if (frag_end != end) { | |
932 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
933 | amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags); | |
934 | } | |
d38ceaf9 AD |
935 | } |
936 | ||
d38ceaf9 AD |
937 | /** |
938 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
939 | * | |
940 | * @adev: amdgpu_device pointer | |
3cabaa54 | 941 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
942 | * @src: address where to copy page table entries from |
943 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 944 | * @vm: requested vm |
a14faa65 CK |
945 | * @start: start of mapped range |
946 | * @last: last mapped entry | |
947 | * @flags: flags for the entries | |
d38ceaf9 | 948 | * @addr: addr to set the area to |
d38ceaf9 AD |
949 | * @fence: optional resulting fence |
950 | * | |
a14faa65 | 951 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 952 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
953 | */ |
954 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 955 | struct dma_fence *exclusive, |
fa3ab3c7 CK |
956 | uint64_t src, |
957 | dma_addr_t *pages_addr, | |
d38ceaf9 | 958 | struct amdgpu_vm *vm, |
a14faa65 | 959 | uint64_t start, uint64_t last, |
6b777607 | 960 | uint64_t flags, uint64_t addr, |
f54d1867 | 961 | struct dma_fence **fence) |
d38ceaf9 | 962 | { |
2d55e45a | 963 | struct amdgpu_ring *ring; |
a1e08d3b | 964 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 965 | unsigned nptes, ncmds, ndw; |
d71518b5 | 966 | struct amdgpu_job *job; |
29efc4f5 | 967 | struct amdgpu_pte_update_params params; |
f54d1867 | 968 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
969 | int r; |
970 | ||
afef8b8f CK |
971 | memset(¶ms, 0, sizeof(params)); |
972 | params.adev = adev; | |
973 | params.src = src; | |
974 | ||
2d55e45a | 975 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 976 | |
29efc4f5 | 977 | memset(¶ms, 0, sizeof(params)); |
27c5f36f | 978 | params.adev = adev; |
29efc4f5 | 979 | params.src = src; |
2d55e45a | 980 | |
a1e08d3b CK |
981 | /* sync to everything on unmapping */ |
982 | if (!(flags & AMDGPU_PTE_VALID)) | |
983 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
984 | ||
a14faa65 | 985 | nptes = last - start + 1; |
d38ceaf9 AD |
986 | |
987 | /* | |
988 | * reserve space for one command every (1 << BLOCK_SIZE) | |
989 | * entries or 2k dwords (whatever is smaller) | |
990 | */ | |
991 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
992 | ||
993 | /* padding, etc. */ | |
994 | ndw = 64; | |
995 | ||
b0456f93 | 996 | if (src) { |
d38ceaf9 AD |
997 | /* only copy commands needed */ |
998 | ndw += ncmds * 7; | |
999 | ||
afef8b8f CK |
1000 | params.func = amdgpu_vm_do_copy_ptes; |
1001 | ||
b0456f93 CK |
1002 | } else if (pages_addr) { |
1003 | /* copy commands needed */ | |
1004 | ndw += ncmds * 7; | |
d38ceaf9 | 1005 | |
b0456f93 | 1006 | /* and also PTEs */ |
d38ceaf9 AD |
1007 | ndw += nptes * 2; |
1008 | ||
afef8b8f CK |
1009 | params.func = amdgpu_vm_do_copy_ptes; |
1010 | ||
d38ceaf9 AD |
1011 | } else { |
1012 | /* set page commands needed */ | |
1013 | ndw += ncmds * 10; | |
1014 | ||
1015 | /* two extra commands for begin/end of fragment */ | |
1016 | ndw += 2 * 10; | |
afef8b8f CK |
1017 | |
1018 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1019 | } |
1020 | ||
d71518b5 CK |
1021 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1022 | if (r) | |
d38ceaf9 | 1023 | return r; |
d71518b5 | 1024 | |
29efc4f5 | 1025 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1026 | |
b0456f93 CK |
1027 | if (!src && pages_addr) { |
1028 | uint64_t *pte; | |
1029 | unsigned i; | |
1030 | ||
1031 | /* Put the PTEs at the end of the IB. */ | |
1032 | i = ndw - nptes * 2; | |
1033 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1034 | params.src = job->ibs->gpu_addr + i * 4; | |
1035 | ||
1036 | for (i = 0; i < nptes; ++i) { | |
1037 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1038 | AMDGPU_GPU_PAGE_SIZE); | |
1039 | pte[i] |= flags; | |
1040 | } | |
d7a4ac66 | 1041 | addr = 0; |
b0456f93 CK |
1042 | } |
1043 | ||
3cabaa54 CK |
1044 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
1045 | if (r) | |
1046 | goto error_free; | |
1047 | ||
e86f9cee | 1048 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
1049 | owner); |
1050 | if (r) | |
1051 | goto error_free; | |
d38ceaf9 | 1052 | |
a1e08d3b CK |
1053 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
1054 | if (r) | |
1055 | goto error_free; | |
1056 | ||
4c7e8855 CZ |
1057 | params.shadow = true; |
1058 | amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags); | |
1059 | params.shadow = false; | |
92696dd5 | 1060 | amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags); |
d38ceaf9 | 1061 | |
29efc4f5 CK |
1062 | amdgpu_ring_pad_ib(ring, params.ib); |
1063 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1064 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1065 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1066 | if (r) |
1067 | goto error_free; | |
d38ceaf9 | 1068 | |
bf60efd3 | 1069 | amdgpu_bo_fence(vm->page_directory, f, true); |
284710fa CK |
1070 | dma_fence_put(*fence); |
1071 | *fence = f; | |
d38ceaf9 | 1072 | return 0; |
d5fc5e82 CZ |
1073 | |
1074 | error_free: | |
d71518b5 | 1075 | amdgpu_job_free(job); |
4af9f07c | 1076 | return r; |
d38ceaf9 AD |
1077 | } |
1078 | ||
a14faa65 CK |
1079 | /** |
1080 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1081 | * | |
1082 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1083 | * @exclusive: fence we need to sync to |
8358dcee CK |
1084 | * @gtt_flags: flags as they are used for GTT |
1085 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
1086 | * @vm: requested vm |
1087 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1088 | * @flags: HW flags for the mapping |
63e0ba40 | 1089 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1090 | * @fence: optional resulting fence |
1091 | * | |
1092 | * Split the mapping into smaller chunks so that each update fits | |
1093 | * into a SDMA IB. | |
1094 | * Returns 0 for success, -EINVAL for failure. | |
1095 | */ | |
1096 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1097 | struct dma_fence *exclusive, |
6b777607 | 1098 | uint64_t gtt_flags, |
8358dcee | 1099 | dma_addr_t *pages_addr, |
a14faa65 CK |
1100 | struct amdgpu_vm *vm, |
1101 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1102 | uint64_t flags, |
63e0ba40 | 1103 | struct drm_mm_node *nodes, |
f54d1867 | 1104 | struct dma_fence **fence) |
a14faa65 | 1105 | { |
63e0ba40 | 1106 | uint64_t pfn, src = 0, start = mapping->it.start; |
a14faa65 CK |
1107 | int r; |
1108 | ||
1109 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1110 | * but in case of something, we filter the flags in first place | |
1111 | */ | |
1112 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1113 | flags &= ~AMDGPU_PTE_READABLE; | |
1114 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1115 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1116 | ||
1117 | trace_amdgpu_vm_bo_update(mapping); | |
1118 | ||
63e0ba40 CK |
1119 | pfn = mapping->offset >> PAGE_SHIFT; |
1120 | if (nodes) { | |
1121 | while (pfn >= nodes->size) { | |
1122 | pfn -= nodes->size; | |
1123 | ++nodes; | |
1124 | } | |
fa3ab3c7 | 1125 | } |
a14faa65 | 1126 | |
63e0ba40 CK |
1127 | do { |
1128 | uint64_t max_entries; | |
1129 | uint64_t addr, last; | |
a14faa65 | 1130 | |
63e0ba40 CK |
1131 | if (nodes) { |
1132 | addr = nodes->start << PAGE_SHIFT; | |
1133 | max_entries = (nodes->size - pfn) * | |
1134 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1135 | } else { | |
1136 | addr = 0; | |
1137 | max_entries = S64_MAX; | |
1138 | } | |
a14faa65 | 1139 | |
63e0ba40 CK |
1140 | if (pages_addr) { |
1141 | if (flags == gtt_flags) | |
1142 | src = adev->gart.table_addr + | |
1143 | (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8; | |
1144 | else | |
1145 | max_entries = min(max_entries, 16ull * 1024ull); | |
1146 | addr = 0; | |
1147 | } else if (flags & AMDGPU_PTE_VALID) { | |
1148 | addr += adev->vm_manager.vram_base_offset; | |
1149 | } | |
1150 | addr += pfn << PAGE_SHIFT; | |
1151 | ||
1152 | last = min((uint64_t)mapping->it.last, start + max_entries - 1); | |
3cabaa54 CK |
1153 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1154 | src, pages_addr, vm, | |
a14faa65 CK |
1155 | start, last, flags, addr, |
1156 | fence); | |
1157 | if (r) | |
1158 | return r; | |
1159 | ||
63e0ba40 CK |
1160 | pfn += last - start + 1; |
1161 | if (nodes && nodes->size == pfn) { | |
1162 | pfn = 0; | |
1163 | ++nodes; | |
1164 | } | |
a14faa65 | 1165 | start = last + 1; |
63e0ba40 CK |
1166 | |
1167 | } while (unlikely(start != mapping->it.last + 1)); | |
a14faa65 CK |
1168 | |
1169 | return 0; | |
1170 | } | |
1171 | ||
d38ceaf9 AD |
1172 | /** |
1173 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1174 | * | |
1175 | * @adev: amdgpu_device pointer | |
1176 | * @bo_va: requested BO and VM object | |
99e124f4 | 1177 | * @clear: if true clear the entries |
d38ceaf9 AD |
1178 | * |
1179 | * Fill in the page table entries for @bo_va. | |
1180 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1181 | */ |
1182 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1183 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1184 | bool clear) |
d38ceaf9 AD |
1185 | { |
1186 | struct amdgpu_vm *vm = bo_va->vm; | |
1187 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1188 | dma_addr_t *pages_addr = NULL; |
6b777607 | 1189 | uint64_t gtt_flags, flags; |
99e124f4 | 1190 | struct ttm_mem_reg *mem; |
63e0ba40 | 1191 | struct drm_mm_node *nodes; |
f54d1867 | 1192 | struct dma_fence *exclusive; |
d38ceaf9 AD |
1193 | int r; |
1194 | ||
a5f6b5b1 | 1195 | if (clear || !bo_va->bo) { |
99e124f4 | 1196 | mem = NULL; |
63e0ba40 | 1197 | nodes = NULL; |
99e124f4 CK |
1198 | exclusive = NULL; |
1199 | } else { | |
8358dcee CK |
1200 | struct ttm_dma_tt *ttm; |
1201 | ||
99e124f4 | 1202 | mem = &bo_va->bo->tbo.mem; |
63e0ba40 CK |
1203 | nodes = mem->mm_node; |
1204 | if (mem->mem_type == TTM_PL_TT) { | |
8358dcee CK |
1205 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1206 | ttm_dma_tt, ttm); | |
1207 | pages_addr = ttm->dma_address; | |
9ab21462 | 1208 | } |
3cabaa54 | 1209 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); |
d38ceaf9 AD |
1210 | } |
1211 | ||
a5f6b5b1 CK |
1212 | if (bo_va->bo) { |
1213 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); | |
1214 | gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && | |
1215 | adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? | |
1216 | flags : 0; | |
1217 | } else { | |
1218 | flags = 0x0; | |
1219 | gtt_flags = ~0x0; | |
1220 | } | |
d38ceaf9 | 1221 | |
7fc11959 CK |
1222 | spin_lock(&vm->status_lock); |
1223 | if (!list_empty(&bo_va->vm_status)) | |
1224 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1225 | spin_unlock(&vm->status_lock); | |
1226 | ||
1227 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1228 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1229 | gtt_flags, pages_addr, vm, | |
63e0ba40 | 1230 | mapping, flags, nodes, |
8358dcee | 1231 | &bo_va->last_pt_update); |
d38ceaf9 AD |
1232 | if (r) |
1233 | return r; | |
1234 | } | |
1235 | ||
d6c10f6b CK |
1236 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1237 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1238 | trace_amdgpu_vm_bo_mapping(mapping); | |
1239 | ||
1240 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1241 | trace_amdgpu_vm_bo_mapping(mapping); | |
1242 | } | |
1243 | ||
d38ceaf9 | 1244 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1245 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1246 | list_del_init(&bo_va->vm_status); |
99e124f4 | 1247 | if (clear) |
7fc11959 | 1248 | list_add(&bo_va->vm_status, &vm->cleared); |
d38ceaf9 AD |
1249 | spin_unlock(&vm->status_lock); |
1250 | ||
1251 | return 0; | |
1252 | } | |
1253 | ||
284710fa CK |
1254 | /** |
1255 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1256 | */ | |
1257 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1258 | { | |
1259 | unsigned long flags; | |
1260 | bool enable; | |
1261 | ||
1262 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1263 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
284710fa CK |
1264 | adev->gart.gart_funcs->set_prt(adev, enable); |
1265 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
1266 | } | |
1267 | ||
451bc8eb | 1268 | /** |
4388fc2a | 1269 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1270 | */ |
1271 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1272 | { | |
4388fc2a CK |
1273 | if (!adev->gart.gart_funcs->set_prt) |
1274 | return; | |
1275 | ||
451bc8eb CK |
1276 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1277 | amdgpu_vm_update_prt_state(adev); | |
1278 | } | |
1279 | ||
0b15f2fc CK |
1280 | /** |
1281 | * amdgpu_vm_prt_put - drop a PRT user | |
1282 | */ | |
1283 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1284 | { | |
451bc8eb | 1285 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1286 | amdgpu_vm_update_prt_state(adev); |
1287 | } | |
1288 | ||
284710fa | 1289 | /** |
451bc8eb | 1290 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1291 | */ |
1292 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1293 | { | |
1294 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1295 | ||
0b15f2fc | 1296 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1297 | kfree(cb); |
1298 | } | |
1299 | ||
451bc8eb CK |
1300 | /** |
1301 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1302 | */ | |
1303 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1304 | struct dma_fence *fence) | |
1305 | { | |
4388fc2a | 1306 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1307 | |
4388fc2a CK |
1308 | if (!adev->gart.gart_funcs->set_prt) |
1309 | return; | |
1310 | ||
1311 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1312 | if (!cb) { |
1313 | /* Last resort when we are OOM */ | |
1314 | if (fence) | |
1315 | dma_fence_wait(fence, false); | |
1316 | ||
1317 | amdgpu_vm_prt_put(cb->adev); | |
1318 | } else { | |
1319 | cb->adev = adev; | |
1320 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1321 | amdgpu_vm_prt_cb)) | |
1322 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1323 | } | |
1324 | } | |
1325 | ||
284710fa CK |
1326 | /** |
1327 | * amdgpu_vm_free_mapping - free a mapping | |
1328 | * | |
1329 | * @adev: amdgpu_device pointer | |
1330 | * @vm: requested vm | |
1331 | * @mapping: mapping to be freed | |
1332 | * @fence: fence of the unmap operation | |
1333 | * | |
1334 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1335 | */ | |
1336 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1337 | struct amdgpu_vm *vm, | |
1338 | struct amdgpu_bo_va_mapping *mapping, | |
1339 | struct dma_fence *fence) | |
1340 | { | |
451bc8eb CK |
1341 | if (mapping->flags & AMDGPU_PTE_PRT) |
1342 | amdgpu_vm_add_prt_cb(adev, fence); | |
1343 | kfree(mapping); | |
1344 | } | |
284710fa | 1345 | |
451bc8eb CK |
1346 | /** |
1347 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1348 | * | |
1349 | * @adev: amdgpu_device pointer | |
1350 | * @vm: requested vm | |
1351 | * | |
1352 | * Register a cleanup callback to disable PRT support after VM dies. | |
1353 | */ | |
1354 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1355 | { | |
1356 | struct reservation_object *resv = vm->page_directory->tbo.resv; | |
1357 | struct dma_fence *excl, **shared; | |
1358 | unsigned i, shared_count; | |
1359 | int r; | |
0b15f2fc | 1360 | |
451bc8eb CK |
1361 | r = reservation_object_get_fences_rcu(resv, &excl, |
1362 | &shared_count, &shared); | |
1363 | if (r) { | |
1364 | /* Not enough memory to grab the fence list, as last resort | |
1365 | * block for all the fences to complete. | |
1366 | */ | |
1367 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1368 | MAX_SCHEDULE_TIMEOUT); | |
1369 | return; | |
284710fa | 1370 | } |
451bc8eb CK |
1371 | |
1372 | /* Add a callback for each fence in the reservation object */ | |
1373 | amdgpu_vm_prt_get(adev); | |
1374 | amdgpu_vm_add_prt_cb(adev, excl); | |
1375 | ||
1376 | for (i = 0; i < shared_count; ++i) { | |
1377 | amdgpu_vm_prt_get(adev); | |
1378 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1379 | } | |
1380 | ||
1381 | kfree(shared); | |
284710fa CK |
1382 | } |
1383 | ||
d38ceaf9 AD |
1384 | /** |
1385 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1386 | * | |
1387 | * @adev: amdgpu_device pointer | |
1388 | * @vm: requested vm | |
1389 | * | |
1390 | * Make sure all freed BOs are cleared in the PT. | |
1391 | * Returns 0 for success. | |
1392 | * | |
1393 | * PTs have to be reserved and mutex must be locked! | |
1394 | */ | |
1395 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
1396 | struct amdgpu_vm *vm) | |
1397 | { | |
1398 | struct amdgpu_bo_va_mapping *mapping; | |
284710fa | 1399 | struct dma_fence *fence = NULL; |
d38ceaf9 AD |
1400 | int r; |
1401 | ||
1402 | while (!list_empty(&vm->freed)) { | |
1403 | mapping = list_first_entry(&vm->freed, | |
1404 | struct amdgpu_bo_va_mapping, list); | |
1405 | list_del(&mapping->list); | |
e17841b9 | 1406 | |
3cabaa54 | 1407 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping, |
284710fa CK |
1408 | 0, 0, &fence); |
1409 | amdgpu_vm_free_mapping(adev, vm, mapping, fence); | |
1410 | if (r) { | |
1411 | dma_fence_put(fence); | |
d38ceaf9 | 1412 | return r; |
284710fa | 1413 | } |
d38ceaf9 AD |
1414 | |
1415 | } | |
284710fa | 1416 | dma_fence_put(fence); |
d38ceaf9 AD |
1417 | return 0; |
1418 | ||
1419 | } | |
1420 | ||
1421 | /** | |
1422 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1423 | * | |
1424 | * @adev: amdgpu_device pointer | |
1425 | * @vm: requested vm | |
1426 | * | |
1427 | * Make sure all invalidated BOs are cleared in the PT. | |
1428 | * Returns 0 for success. | |
1429 | * | |
1430 | * PTs have to be reserved and mutex must be locked! | |
1431 | */ | |
1432 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1433 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1434 | { |
cfe2c978 | 1435 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1436 | int r = 0; |
d38ceaf9 AD |
1437 | |
1438 | spin_lock(&vm->status_lock); | |
1439 | while (!list_empty(&vm->invalidated)) { | |
1440 | bo_va = list_first_entry(&vm->invalidated, | |
1441 | struct amdgpu_bo_va, vm_status); | |
1442 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1443 | |
99e124f4 | 1444 | r = amdgpu_vm_bo_update(adev, bo_va, true); |
d38ceaf9 AD |
1445 | if (r) |
1446 | return r; | |
1447 | ||
1448 | spin_lock(&vm->status_lock); | |
1449 | } | |
1450 | spin_unlock(&vm->status_lock); | |
1451 | ||
cfe2c978 | 1452 | if (bo_va) |
bb1e38a4 | 1453 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1454 | |
1455 | return r; | |
d38ceaf9 AD |
1456 | } |
1457 | ||
1458 | /** | |
1459 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1460 | * | |
1461 | * @adev: amdgpu_device pointer | |
1462 | * @vm: requested vm | |
1463 | * @bo: amdgpu buffer object | |
1464 | * | |
8843dbbb | 1465 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1466 | * Add @bo to the list of bos associated with the vm |
1467 | * Returns newly added bo_va or NULL for failure | |
1468 | * | |
1469 | * Object has to be reserved! | |
1470 | */ | |
1471 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1472 | struct amdgpu_vm *vm, | |
1473 | struct amdgpu_bo *bo) | |
1474 | { | |
1475 | struct amdgpu_bo_va *bo_va; | |
1476 | ||
1477 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1478 | if (bo_va == NULL) { | |
1479 | return NULL; | |
1480 | } | |
1481 | bo_va->vm = vm; | |
1482 | bo_va->bo = bo; | |
d38ceaf9 AD |
1483 | bo_va->ref_count = 1; |
1484 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1485 | INIT_LIST_HEAD(&bo_va->valids); |
1486 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1487 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1488 | |
a5f6b5b1 CK |
1489 | if (bo) |
1490 | list_add_tail(&bo_va->bo_list, &bo->va); | |
d38ceaf9 AD |
1491 | |
1492 | return bo_va; | |
1493 | } | |
1494 | ||
1495 | /** | |
1496 | * amdgpu_vm_bo_map - map bo inside a vm | |
1497 | * | |
1498 | * @adev: amdgpu_device pointer | |
1499 | * @bo_va: bo_va to store the address | |
1500 | * @saddr: where to map the BO | |
1501 | * @offset: requested offset in the BO | |
1502 | * @flags: attributes of pages (read/write/valid/etc.) | |
1503 | * | |
1504 | * Add a mapping of the BO at the specefied addr into the VM. | |
1505 | * Returns 0 for success, error for failure. | |
1506 | * | |
49b02b18 | 1507 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1508 | */ |
1509 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1510 | struct amdgpu_bo_va *bo_va, | |
1511 | uint64_t saddr, uint64_t offset, | |
268c3001 | 1512 | uint64_t size, uint64_t flags) |
d38ceaf9 AD |
1513 | { |
1514 | struct amdgpu_bo_va_mapping *mapping; | |
1515 | struct amdgpu_vm *vm = bo_va->vm; | |
1516 | struct interval_tree_node *it; | |
d38ceaf9 | 1517 | uint64_t eaddr; |
d38ceaf9 | 1518 | |
0be52de9 CK |
1519 | /* validate the parameters */ |
1520 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1521 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1522 | return -EINVAL; |
0be52de9 | 1523 | |
d38ceaf9 | 1524 | /* make sure object fit at this offset */ |
005ae95e | 1525 | eaddr = saddr + size - 1; |
a5f6b5b1 CK |
1526 | if (saddr >= eaddr || |
1527 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
d38ceaf9 | 1528 | return -EINVAL; |
d38ceaf9 | 1529 | |
d38ceaf9 AD |
1530 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1531 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1532 | ||
005ae95e | 1533 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
d38ceaf9 AD |
1534 | if (it) { |
1535 | struct amdgpu_bo_va_mapping *tmp; | |
1536 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1537 | /* bo and tmp overlap, invalid addr */ | |
1538 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1539 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1540 | tmp->it.start, tmp->it.last + 1); | |
663e4577 | 1541 | return -EINVAL; |
d38ceaf9 AD |
1542 | } |
1543 | ||
1544 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
1545 | if (!mapping) |
1546 | return -ENOMEM; | |
d38ceaf9 AD |
1547 | |
1548 | INIT_LIST_HEAD(&mapping->list); | |
1549 | mapping->it.start = saddr; | |
005ae95e | 1550 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1551 | mapping->offset = offset; |
1552 | mapping->flags = flags; | |
1553 | ||
7fc11959 | 1554 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 | 1555 | interval_tree_insert(&mapping->it, &vm->va); |
80f95c57 CK |
1556 | |
1557 | if (flags & AMDGPU_PTE_PRT) | |
1558 | amdgpu_vm_prt_get(adev); | |
1559 | ||
1560 | return 0; | |
1561 | } | |
1562 | ||
1563 | /** | |
1564 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
1565 | * | |
1566 | * @adev: amdgpu_device pointer | |
1567 | * @bo_va: bo_va to store the address | |
1568 | * @saddr: where to map the BO | |
1569 | * @offset: requested offset in the BO | |
1570 | * @flags: attributes of pages (read/write/valid/etc.) | |
1571 | * | |
1572 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
1573 | * mappings as we do so. | |
1574 | * Returns 0 for success, error for failure. | |
1575 | * | |
1576 | * Object has to be reserved and unreserved outside! | |
1577 | */ | |
1578 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
1579 | struct amdgpu_bo_va *bo_va, | |
1580 | uint64_t saddr, uint64_t offset, | |
1581 | uint64_t size, uint64_t flags) | |
1582 | { | |
1583 | struct amdgpu_bo_va_mapping *mapping; | |
1584 | struct amdgpu_vm *vm = bo_va->vm; | |
1585 | uint64_t eaddr; | |
1586 | int r; | |
1587 | ||
1588 | /* validate the parameters */ | |
1589 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
1590 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
1591 | return -EINVAL; | |
1592 | ||
1593 | /* make sure object fit at this offset */ | |
1594 | eaddr = saddr + size - 1; | |
1595 | if (saddr >= eaddr || | |
1596 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
1597 | return -EINVAL; | |
1598 | ||
1599 | /* Allocate all the needed memory */ | |
1600 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1601 | if (!mapping) | |
1602 | return -ENOMEM; | |
1603 | ||
1604 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size); | |
1605 | if (r) { | |
1606 | kfree(mapping); | |
1607 | return r; | |
1608 | } | |
1609 | ||
1610 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
1611 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1612 | ||
1613 | mapping->it.start = saddr; | |
1614 | mapping->it.last = eaddr; | |
1615 | mapping->offset = offset; | |
1616 | mapping->flags = flags; | |
1617 | ||
1618 | list_add(&mapping->list, &bo_va->invalids); | |
1619 | interval_tree_insert(&mapping->it, &vm->va); | |
d38ceaf9 | 1620 | |
4388fc2a CK |
1621 | if (flags & AMDGPU_PTE_PRT) |
1622 | amdgpu_vm_prt_get(adev); | |
1623 | ||
d38ceaf9 | 1624 | return 0; |
d38ceaf9 AD |
1625 | } |
1626 | ||
1627 | /** | |
1628 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1629 | * | |
1630 | * @adev: amdgpu_device pointer | |
1631 | * @bo_va: bo_va to remove the address from | |
1632 | * @saddr: where to the BO is mapped | |
1633 | * | |
1634 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1635 | * Returns 0 for success, error for failure. | |
1636 | * | |
49b02b18 | 1637 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1638 | */ |
1639 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1640 | struct amdgpu_bo_va *bo_va, | |
1641 | uint64_t saddr) | |
1642 | { | |
1643 | struct amdgpu_bo_va_mapping *mapping; | |
1644 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1645 | bool valid = true; |
d38ceaf9 | 1646 | |
6c7fc503 | 1647 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1648 | |
7fc11959 | 1649 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1650 | if (mapping->it.start == saddr) |
1651 | break; | |
1652 | } | |
1653 | ||
7fc11959 CK |
1654 | if (&mapping->list == &bo_va->valids) { |
1655 | valid = false; | |
1656 | ||
1657 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1658 | if (mapping->it.start == saddr) | |
1659 | break; | |
1660 | } | |
1661 | ||
32b41ac2 | 1662 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1663 | return -ENOENT; |
d38ceaf9 | 1664 | } |
32b41ac2 | 1665 | |
d38ceaf9 AD |
1666 | list_del(&mapping->list); |
1667 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1668 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1669 | |
e17841b9 | 1670 | if (valid) |
d38ceaf9 | 1671 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1672 | else |
284710fa CK |
1673 | amdgpu_vm_free_mapping(adev, vm, mapping, |
1674 | bo_va->last_pt_update); | |
d38ceaf9 AD |
1675 | |
1676 | return 0; | |
1677 | } | |
1678 | ||
dc54d3d1 CK |
1679 | /** |
1680 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
1681 | * | |
1682 | * @adev: amdgpu_device pointer | |
1683 | * @vm: VM structure to use | |
1684 | * @saddr: start of the range | |
1685 | * @size: size of the range | |
1686 | * | |
1687 | * Remove all mappings in a range, split them as appropriate. | |
1688 | * Returns 0 for success, error for failure. | |
1689 | */ | |
1690 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
1691 | struct amdgpu_vm *vm, | |
1692 | uint64_t saddr, uint64_t size) | |
1693 | { | |
1694 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
1695 | struct interval_tree_node *it; | |
1696 | LIST_HEAD(removed); | |
1697 | uint64_t eaddr; | |
1698 | ||
1699 | eaddr = saddr + size - 1; | |
1700 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
1701 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1702 | ||
1703 | /* Allocate all the needed memory */ | |
1704 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
1705 | if (!before) | |
1706 | return -ENOMEM; | |
1707 | ||
1708 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
1709 | if (!after) { | |
1710 | kfree(before); | |
1711 | return -ENOMEM; | |
1712 | } | |
1713 | ||
1714 | /* Now gather all removed mappings */ | |
1715 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); | |
1716 | while (it) { | |
1717 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1718 | it = interval_tree_iter_next(it, saddr, eaddr); | |
1719 | ||
1720 | /* Remember mapping split at the start */ | |
1721 | if (tmp->it.start < saddr) { | |
1722 | before->it.start = tmp->it.start;; | |
1723 | before->it.last = saddr - 1; | |
1724 | before->offset = tmp->offset; | |
1725 | before->flags = tmp->flags; | |
1726 | list_add(&before->list, &tmp->list); | |
1727 | } | |
1728 | ||
1729 | /* Remember mapping split at the end */ | |
1730 | if (tmp->it.last > eaddr) { | |
1731 | after->it.start = eaddr + 1; | |
1732 | after->it.last = tmp->it.last; | |
1733 | after->offset = tmp->offset; | |
1734 | after->offset += after->it.start - tmp->it.start; | |
1735 | after->flags = tmp->flags; | |
1736 | list_add(&after->list, &tmp->list); | |
1737 | } | |
1738 | ||
1739 | list_del(&tmp->list); | |
1740 | list_add(&tmp->list, &removed); | |
1741 | } | |
1742 | ||
1743 | /* And free them up */ | |
1744 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
1745 | interval_tree_remove(&tmp->it, &vm->va); | |
1746 | list_del(&tmp->list); | |
1747 | ||
1748 | if (tmp->it.start < saddr) | |
1749 | tmp->it.start = saddr; | |
1750 | if (tmp->it.last > eaddr) | |
1751 | tmp->it.last = eaddr; | |
1752 | ||
1753 | list_add(&tmp->list, &vm->freed); | |
1754 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
1755 | } | |
1756 | ||
1757 | /* Insert partial mapping before the range*/ | |
1758 | if (before->it.start != before->it.last) { | |
1759 | interval_tree_insert(&before->it, &vm->va); | |
1760 | if (before->flags & AMDGPU_PTE_PRT) | |
1761 | amdgpu_vm_prt_get(adev); | |
1762 | } else { | |
1763 | kfree(before); | |
1764 | } | |
1765 | ||
1766 | /* Insert partial mapping after the range */ | |
1767 | if (after->it.start != after->it.last) { | |
1768 | interval_tree_insert(&after->it, &vm->va); | |
1769 | if (after->flags & AMDGPU_PTE_PRT) | |
1770 | amdgpu_vm_prt_get(adev); | |
1771 | } else { | |
1772 | kfree(after); | |
1773 | } | |
1774 | ||
1775 | return 0; | |
1776 | } | |
1777 | ||
d38ceaf9 AD |
1778 | /** |
1779 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1780 | * | |
1781 | * @adev: amdgpu_device pointer | |
1782 | * @bo_va: requested bo_va | |
1783 | * | |
8843dbbb | 1784 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1785 | * |
1786 | * Object have to be reserved! | |
1787 | */ | |
1788 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1789 | struct amdgpu_bo_va *bo_va) | |
1790 | { | |
1791 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1792 | struct amdgpu_vm *vm = bo_va->vm; | |
1793 | ||
1794 | list_del(&bo_va->bo_list); | |
1795 | ||
d38ceaf9 AD |
1796 | spin_lock(&vm->status_lock); |
1797 | list_del(&bo_va->vm_status); | |
1798 | spin_unlock(&vm->status_lock); | |
1799 | ||
7fc11959 | 1800 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1801 | list_del(&mapping->list); |
1802 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1803 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1804 | list_add(&mapping->list, &vm->freed); |
1805 | } | |
1806 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1807 | list_del(&mapping->list); | |
1808 | interval_tree_remove(&mapping->it, &vm->va); | |
284710fa CK |
1809 | amdgpu_vm_free_mapping(adev, vm, mapping, |
1810 | bo_va->last_pt_update); | |
d38ceaf9 | 1811 | } |
32b41ac2 | 1812 | |
f54d1867 | 1813 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 1814 | kfree(bo_va); |
d38ceaf9 AD |
1815 | } |
1816 | ||
1817 | /** | |
1818 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1819 | * | |
1820 | * @adev: amdgpu_device pointer | |
1821 | * @vm: requested vm | |
1822 | * @bo: amdgpu buffer object | |
1823 | * | |
8843dbbb | 1824 | * Mark @bo as invalid. |
d38ceaf9 AD |
1825 | */ |
1826 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1827 | struct amdgpu_bo *bo) | |
1828 | { | |
1829 | struct amdgpu_bo_va *bo_va; | |
1830 | ||
1831 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1832 | spin_lock(&bo_va->vm->status_lock); |
1833 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1834 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1835 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1836 | } |
1837 | } | |
1838 | ||
1839 | /** | |
1840 | * amdgpu_vm_init - initialize a vm instance | |
1841 | * | |
1842 | * @adev: amdgpu_device pointer | |
1843 | * @vm: requested vm | |
1844 | * | |
8843dbbb | 1845 | * Init @vm fields. |
d38ceaf9 AD |
1846 | */ |
1847 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1848 | { | |
1849 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1850 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1851 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1852 | unsigned ring_instance; |
1853 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1854 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1855 | int i, r; |
1856 | ||
bcb1ba35 CK |
1857 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1858 | vm->ids[i] = NULL; | |
d38ceaf9 | 1859 | vm->va = RB_ROOT; |
031e2983 | 1860 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
d38ceaf9 AD |
1861 | spin_lock_init(&vm->status_lock); |
1862 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1863 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1864 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 1865 | |
d38ceaf9 AD |
1866 | pd_size = amdgpu_vm_directory_size(adev); |
1867 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1868 | ||
1869 | /* allocate page table array */ | |
9571e1d8 | 1870 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1871 | if (vm->page_tables == NULL) { |
1872 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1873 | return -ENOMEM; | |
1874 | } | |
1875 | ||
2bd9ccfa | 1876 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1877 | |
1878 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1879 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1880 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1881 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1882 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1883 | rq, amdgpu_sched_jobs); | |
1884 | if (r) | |
64827adc | 1885 | goto err; |
2bd9ccfa | 1886 | |
05906dec BN |
1887 | vm->page_directory_fence = NULL; |
1888 | ||
d38ceaf9 | 1889 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d | 1890 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f | 1891 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
03f48dd5 | 1892 | AMDGPU_GEM_CREATE_SHADOW | |
617859e0 CK |
1893 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
1894 | AMDGPU_GEM_CREATE_VRAM_CLEARED, | |
72d7668b | 1895 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1896 | if (r) |
2bd9ccfa CK |
1897 | goto error_free_sched_entity; |
1898 | ||
ef9f0a83 | 1899 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1900 | if (r) |
1901 | goto error_free_page_directory; | |
1902 | ||
5a712a87 | 1903 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
2a82ec21 | 1904 | amdgpu_bo_unreserve(vm->page_directory); |
d38ceaf9 AD |
1905 | |
1906 | return 0; | |
2bd9ccfa CK |
1907 | |
1908 | error_free_page_directory: | |
2698f620 | 1909 | amdgpu_bo_unref(&vm->page_directory->shadow); |
2bd9ccfa CK |
1910 | amdgpu_bo_unref(&vm->page_directory); |
1911 | vm->page_directory = NULL; | |
1912 | ||
1913 | error_free_sched_entity: | |
1914 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1915 | ||
64827adc CZ |
1916 | err: |
1917 | drm_free_large(vm->page_tables); | |
1918 | ||
2bd9ccfa | 1919 | return r; |
d38ceaf9 AD |
1920 | } |
1921 | ||
1922 | /** | |
1923 | * amdgpu_vm_fini - tear down a vm instance | |
1924 | * | |
1925 | * @adev: amdgpu_device pointer | |
1926 | * @vm: requested vm | |
1927 | * | |
8843dbbb | 1928 | * Tear down @vm. |
d38ceaf9 AD |
1929 | * Unbind the VM and remove all bos from the vm bo list |
1930 | */ | |
1931 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1932 | { | |
1933 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
4388fc2a | 1934 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
d38ceaf9 AD |
1935 | int i; |
1936 | ||
2d55e45a | 1937 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1938 | |
d38ceaf9 AD |
1939 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1940 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1941 | } | |
1942 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1943 | list_del(&mapping->list); | |
1944 | interval_tree_remove(&mapping->it, &vm->va); | |
1945 | kfree(mapping); | |
1946 | } | |
1947 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 1948 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 1949 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 1950 | prt_fini_needed = false; |
451bc8eb | 1951 | } |
284710fa | 1952 | |
d38ceaf9 | 1953 | list_del(&mapping->list); |
451bc8eb | 1954 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
1955 | } |
1956 | ||
1baa439f | 1957 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) { |
914b4dce | 1958 | struct amdgpu_bo *pt = vm->page_tables[i].bo; |
2698f620 CK |
1959 | |
1960 | if (!pt) | |
1961 | continue; | |
1962 | ||
1963 | amdgpu_bo_unref(&pt->shadow); | |
1964 | amdgpu_bo_unref(&pt); | |
1baa439f | 1965 | } |
9571e1d8 | 1966 | drm_free_large(vm->page_tables); |
d38ceaf9 | 1967 | |
2698f620 | 1968 | amdgpu_bo_unref(&vm->page_directory->shadow); |
d38ceaf9 | 1969 | amdgpu_bo_unref(&vm->page_directory); |
f54d1867 | 1970 | dma_fence_put(vm->page_directory_fence); |
d38ceaf9 | 1971 | } |
ea89f8c9 | 1972 | |
a9a78b32 CK |
1973 | /** |
1974 | * amdgpu_vm_manager_init - init the VM manager | |
1975 | * | |
1976 | * @adev: amdgpu_device pointer | |
1977 | * | |
1978 | * Initialize the VM manager structures | |
1979 | */ | |
1980 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1981 | { | |
1982 | unsigned i; | |
1983 | ||
1984 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1985 | ||
1986 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1987 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1988 | amdgpu_vm_reset_id(adev, i); | |
832a902f | 1989 | amdgpu_sync_create(&adev->vm_manager.ids[i].active); |
a9a78b32 CK |
1990 | list_add_tail(&adev->vm_manager.ids[i].list, |
1991 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1992 | } |
2d55e45a | 1993 | |
f54d1867 CW |
1994 | adev->vm_manager.fence_context = |
1995 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
1996 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1997 | adev->vm_manager.seqno[i] = 0; | |
1998 | ||
2d55e45a | 1999 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 2000 | atomic64_set(&adev->vm_manager.client_counter, 0); |
284710fa | 2001 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2002 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
a9a78b32 CK |
2003 | } |
2004 | ||
ea89f8c9 CK |
2005 | /** |
2006 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2007 | * | |
2008 | * @adev: amdgpu_device pointer | |
2009 | * | |
2010 | * Cleanup the VM manager and free resources. | |
2011 | */ | |
2012 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2013 | { | |
2014 | unsigned i; | |
2015 | ||
bcb1ba35 CK |
2016 | for (i = 0; i < AMDGPU_NUM_VM; ++i) { |
2017 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; | |
2018 | ||
f54d1867 | 2019 | dma_fence_put(adev->vm_manager.ids[i].first); |
832a902f | 2020 | amdgpu_sync_free(&adev->vm_manager.ids[i].active); |
f54d1867 | 2021 | dma_fence_put(id->flushed_updates); |
7b624ad8 | 2022 | dma_fence_put(id->last_flush); |
bcb1ba35 | 2023 | } |
ea89f8c9 | 2024 | } |