]>
Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
53 | /** | |
54 | * amdgpu_vm_num_pde - return the number of page directory entries | |
55 | * | |
56 | * @adev: amdgpu_device pointer | |
57 | * | |
58 | * Calculate the number of page directory entries (cayman+). | |
59 | */ | |
60 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
61 | { | |
62 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
63 | } | |
64 | ||
65 | /** | |
66 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
67 | * | |
68 | * @adev: amdgpu_device pointer | |
69 | * | |
70 | * Calculate the size of the page directory in bytes (cayman+). | |
71 | */ | |
72 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
73 | { | |
74 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
75 | } | |
76 | ||
77 | /** | |
56467ebf | 78 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
79 | * |
80 | * @vm: vm providing the BOs | |
3c0eea6c | 81 | * @validated: head of validation list |
56467ebf | 82 | * @entry: entry to add |
d38ceaf9 AD |
83 | * |
84 | * Add the page directory to the list of BOs to | |
56467ebf | 85 | * validate for command submission. |
d38ceaf9 | 86 | */ |
56467ebf CK |
87 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
88 | struct list_head *validated, | |
89 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 90 | { |
56467ebf | 91 | entry->robj = vm->page_directory; |
56467ebf CK |
92 | entry->priority = 0; |
93 | entry->tv.bo = &vm->page_directory->tbo; | |
94 | entry->tv.shared = true; | |
95 | list_add(&entry->tv.head, validated); | |
96 | } | |
d38ceaf9 | 97 | |
56467ebf | 98 | /** |
ee1782c3 | 99 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf CK |
100 | * |
101 | * @vm: vm providing the BOs | |
3c0eea6c | 102 | * @duplicates: head of duplicates list |
d38ceaf9 | 103 | * |
ee1782c3 CK |
104 | * Add the page directory to the BO duplicates list |
105 | * for command submission. | |
d38ceaf9 | 106 | */ |
ee1782c3 | 107 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates) |
d38ceaf9 | 108 | { |
ee1782c3 | 109 | unsigned i; |
d38ceaf9 AD |
110 | |
111 | /* add the vm page table to the list */ | |
ee1782c3 CK |
112 | for (i = 0; i <= vm->max_pde_used; ++i) { |
113 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
114 | ||
115 | if (!entry->robj) | |
d38ceaf9 AD |
116 | continue; |
117 | ||
ee1782c3 | 118 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 119 | } |
eceb8a15 CK |
120 | |
121 | } | |
122 | ||
123 | /** | |
124 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
125 | * | |
126 | * @adev: amdgpu device instance | |
127 | * @vm: vm providing the BOs | |
128 | * | |
129 | * Move the PT BOs to the tail of the LRU. | |
130 | */ | |
131 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
132 | struct amdgpu_vm *vm) | |
133 | { | |
134 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
135 | unsigned i; | |
136 | ||
137 | spin_lock(&glob->lru_lock); | |
138 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
139 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
140 | ||
141 | if (!entry->robj) | |
142 | continue; | |
143 | ||
144 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
145 | } | |
146 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
147 | } |
148 | ||
149 | /** | |
150 | * amdgpu_vm_grab_id - allocate the next free VMID | |
151 | * | |
d38ceaf9 | 152 | * @vm: vm to allocate id for |
7f8a5290 CK |
153 | * @ring: ring we want to submit job to |
154 | * @sync: sync object where we add dependencies | |
d38ceaf9 | 155 | * |
7f8a5290 | 156 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 157 | * |
7f8a5290 | 158 | * Global mutex must be locked! |
d38ceaf9 | 159 | */ |
7f8a5290 CK |
160 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
161 | struct amdgpu_sync *sync) | |
d38ceaf9 | 162 | { |
d5283298 | 163 | struct fence *best[AMDGPU_MAX_RINGS] = {}; |
d38ceaf9 AD |
164 | struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; |
165 | struct amdgpu_device *adev = ring->adev; | |
166 | ||
167 | unsigned choices[2] = {}; | |
168 | unsigned i; | |
169 | ||
170 | /* check if the id is still valid */ | |
1c16c0a7 CK |
171 | if (vm_id->id) { |
172 | unsigned id = vm_id->id; | |
173 | long owner; | |
174 | ||
175 | owner = atomic_long_read(&adev->vm_manager.ids[id].owner); | |
176 | if (owner == (long)vm) { | |
165e4e07 | 177 | trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx); |
1c16c0a7 CK |
178 | return 0; |
179 | } | |
39ff8449 | 180 | } |
d38ceaf9 AD |
181 | |
182 | /* we definately need to flush */ | |
183 | vm_id->pd_gpu_addr = ~0ll; | |
184 | ||
185 | /* skip over VMID 0, since it is the system VM */ | |
186 | for (i = 1; i < adev->vm_manager.nvm; ++i) { | |
1c16c0a7 | 187 | struct fence *fence = adev->vm_manager.ids[i].active; |
d5283298 | 188 | struct amdgpu_ring *fring; |
d38ceaf9 AD |
189 | |
190 | if (fence == NULL) { | |
191 | /* found a free one */ | |
192 | vm_id->id = i; | |
165e4e07 | 193 | trace_amdgpu_vm_grab_id(vm, i, ring->idx); |
7f8a5290 | 194 | return 0; |
d38ceaf9 AD |
195 | } |
196 | ||
d5283298 CK |
197 | fring = amdgpu_ring_from_fence(fence); |
198 | if (best[fring->idx] == NULL || | |
199 | fence_is_later(best[fring->idx], fence)) { | |
200 | best[fring->idx] = fence; | |
201 | choices[fring == ring ? 0 : 1] = i; | |
d38ceaf9 AD |
202 | } |
203 | } | |
204 | ||
205 | for (i = 0; i < 2; ++i) { | |
206 | if (choices[i]) { | |
d5283298 | 207 | struct fence *fence; |
7f8a5290 | 208 | |
1c16c0a7 | 209 | fence = adev->vm_manager.ids[choices[i]].active; |
d38ceaf9 | 210 | vm_id->id = choices[i]; |
7f8a5290 | 211 | |
165e4e07 | 212 | trace_amdgpu_vm_grab_id(vm, choices[i], ring->idx); |
d5283298 | 213 | return amdgpu_sync_fence(ring->adev, sync, fence); |
d38ceaf9 AD |
214 | } |
215 | } | |
216 | ||
217 | /* should never happen */ | |
218 | BUG(); | |
7f8a5290 | 219 | return -EINVAL; |
d38ceaf9 AD |
220 | } |
221 | ||
222 | /** | |
223 | * amdgpu_vm_flush - hardware flush the vm | |
224 | * | |
225 | * @ring: ring to use for flush | |
226 | * @vm: vm we want to flush | |
227 | * @updates: last vm update that we waited for | |
228 | * | |
229 | * Flush the vm (cayman+). | |
230 | * | |
231 | * Global and local mutex must be locked! | |
232 | */ | |
233 | void amdgpu_vm_flush(struct amdgpu_ring *ring, | |
234 | struct amdgpu_vm *vm, | |
3c62338c | 235 | struct fence *updates) |
d38ceaf9 AD |
236 | { |
237 | uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); | |
238 | struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; | |
3c62338c | 239 | struct fence *flushed_updates = vm_id->flushed_updates; |
b56c2285 | 240 | bool is_later; |
3c62338c | 241 | |
b56c2285 CK |
242 | if (!flushed_updates) |
243 | is_later = true; | |
244 | else if (!updates) | |
245 | is_later = false; | |
246 | else | |
247 | is_later = fence_is_later(updates, flushed_updates); | |
d38ceaf9 | 248 | |
b56c2285 | 249 | if (pd_addr != vm_id->pd_gpu_addr || is_later) { |
d38ceaf9 | 250 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id); |
b56c2285 | 251 | if (is_later) { |
3c62338c CZ |
252 | vm_id->flushed_updates = fence_get(updates); |
253 | fence_put(flushed_updates); | |
254 | } | |
d38ceaf9 AD |
255 | vm_id->pd_gpu_addr = pd_addr; |
256 | amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr); | |
257 | } | |
258 | } | |
259 | ||
260 | /** | |
261 | * amdgpu_vm_fence - remember fence for vm | |
262 | * | |
263 | * @adev: amdgpu_device pointer | |
264 | * @vm: vm we want to fence | |
265 | * @fence: fence to remember | |
266 | * | |
267 | * Fence the vm (cayman+). | |
268 | * Set the fence used to protect page table and id. | |
269 | * | |
270 | * Global and local mutex must be locked! | |
271 | */ | |
272 | void amdgpu_vm_fence(struct amdgpu_device *adev, | |
273 | struct amdgpu_vm *vm, | |
16ae42fe | 274 | struct fence *fence) |
d38ceaf9 | 275 | { |
16ae42fe CK |
276 | struct amdgpu_ring *ring = amdgpu_ring_from_fence(fence); |
277 | unsigned vm_id = vm->ids[ring->idx].id; | |
d38ceaf9 | 278 | |
1c16c0a7 CK |
279 | fence_put(adev->vm_manager.ids[vm_id].active); |
280 | adev->vm_manager.ids[vm_id].active = fence_get(fence); | |
281 | atomic_long_set(&adev->vm_manager.ids[vm_id].owner, (long)vm); | |
d38ceaf9 AD |
282 | } |
283 | ||
284 | /** | |
285 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
286 | * | |
287 | * @vm: requested vm | |
288 | * @bo: requested buffer object | |
289 | * | |
290 | * Find @bo inside the requested vm (cayman+). | |
291 | * Search inside the @bos vm list for the requested vm | |
292 | * Returns the found bo_va or NULL if none is found | |
293 | * | |
294 | * Object has to be reserved! | |
295 | */ | |
296 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
297 | struct amdgpu_bo *bo) | |
298 | { | |
299 | struct amdgpu_bo_va *bo_va; | |
300 | ||
301 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
302 | if (bo_va->vm == vm) { | |
303 | return bo_va; | |
304 | } | |
305 | } | |
306 | return NULL; | |
307 | } | |
308 | ||
309 | /** | |
310 | * amdgpu_vm_update_pages - helper to call the right asic function | |
311 | * | |
312 | * @adev: amdgpu_device pointer | |
313 | * @ib: indirect buffer to fill with commands | |
314 | * @pe: addr of the page entry | |
315 | * @addr: dst addr to write into pe | |
316 | * @count: number of page entries to update | |
317 | * @incr: increase next addr by incr bytes | |
318 | * @flags: hw access flags | |
319 | * @gtt_flags: GTT hw access flags | |
320 | * | |
321 | * Traces the parameters and calls the right asic functions | |
322 | * to setup the page table using the DMA. | |
323 | */ | |
324 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
325 | struct amdgpu_ib *ib, | |
326 | uint64_t pe, uint64_t addr, | |
327 | unsigned count, uint32_t incr, | |
328 | uint32_t flags, uint32_t gtt_flags) | |
329 | { | |
330 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
331 | ||
332 | if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) { | |
333 | uint64_t src = adev->gart.table_addr + (addr >> 12) * 8; | |
334 | amdgpu_vm_copy_pte(adev, ib, pe, src, count); | |
335 | ||
336 | } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) { | |
337 | amdgpu_vm_write_pte(adev, ib, pe, addr, | |
338 | count, incr, flags); | |
339 | ||
340 | } else { | |
341 | amdgpu_vm_set_pte_pde(adev, ib, pe, addr, | |
342 | count, incr, flags); | |
343 | } | |
344 | } | |
345 | ||
4c7eb91c | 346 | int amdgpu_vm_free_job(struct amdgpu_job *job) |
d5fc5e82 CZ |
347 | { |
348 | int i; | |
4c7eb91c JZ |
349 | for (i = 0; i < job->num_ibs; i++) |
350 | amdgpu_ib_free(job->adev, &job->ibs[i]); | |
351 | kfree(job->ibs); | |
d5fc5e82 CZ |
352 | return 0; |
353 | } | |
354 | ||
d38ceaf9 AD |
355 | /** |
356 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
357 | * | |
358 | * @adev: amdgpu_device pointer | |
359 | * @bo: bo to clear | |
ef9f0a83 CZ |
360 | * |
361 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
362 | */ |
363 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
364 | struct amdgpu_bo *bo) | |
365 | { | |
366 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
4af9f07c | 367 | struct fence *fence = NULL; |
d5fc5e82 | 368 | struct amdgpu_ib *ib; |
d38ceaf9 AD |
369 | unsigned entries; |
370 | uint64_t addr; | |
371 | int r; | |
372 | ||
ca952613 | 373 | r = reservation_object_reserve_shared(bo->tbo.resv); |
374 | if (r) | |
375 | return r; | |
376 | ||
d38ceaf9 AD |
377 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
378 | if (r) | |
ef9f0a83 | 379 | goto error; |
d38ceaf9 AD |
380 | |
381 | addr = amdgpu_bo_gpu_offset(bo); | |
382 | entries = amdgpu_bo_size(bo) / 8; | |
383 | ||
d5fc5e82 CZ |
384 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
385 | if (!ib) | |
ef9f0a83 | 386 | goto error; |
d38ceaf9 | 387 | |
d5fc5e82 | 388 | r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib); |
d38ceaf9 AD |
389 | if (r) |
390 | goto error_free; | |
391 | ||
d5fc5e82 CZ |
392 | ib->length_dw = 0; |
393 | ||
394 | amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0); | |
395 | amdgpu_vm_pad_ib(adev, ib); | |
396 | WARN_ON(ib->length_dw > 64); | |
4af9f07c CZ |
397 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
398 | &amdgpu_vm_free_job, | |
399 | AMDGPU_FENCE_OWNER_VM, | |
400 | &fence); | |
401 | if (!r) | |
402 | amdgpu_bo_fence(bo, fence, true); | |
281b4223 | 403 | fence_put(fence); |
cadf97b1 | 404 | return 0; |
ef9f0a83 | 405 | |
d38ceaf9 | 406 | error_free: |
d5fc5e82 CZ |
407 | amdgpu_ib_free(adev, ib); |
408 | kfree(ib); | |
d38ceaf9 | 409 | |
ef9f0a83 | 410 | error: |
d38ceaf9 AD |
411 | return r; |
412 | } | |
413 | ||
414 | /** | |
415 | * amdgpu_vm_map_gart - get the physical address of a gart page | |
416 | * | |
417 | * @adev: amdgpu_device pointer | |
418 | * @addr: the unmapped addr | |
419 | * | |
420 | * Look up the physical address of the page that the pte resolves | |
421 | * to (cayman+). | |
422 | * Returns the physical address of the page. | |
423 | */ | |
424 | uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr) | |
425 | { | |
426 | uint64_t result; | |
427 | ||
428 | /* page table offset */ | |
429 | result = adev->gart.pages_addr[addr >> PAGE_SHIFT]; | |
430 | ||
431 | /* in case cpu page size != gpu page size*/ | |
432 | result |= addr & (~PAGE_MASK); | |
433 | ||
434 | return result; | |
435 | } | |
436 | ||
437 | /** | |
438 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
439 | * | |
440 | * @adev: amdgpu_device pointer | |
441 | * @vm: requested vm | |
442 | * @start: start of GPU address range | |
443 | * @end: end of GPU address range | |
444 | * | |
445 | * Allocates new page tables if necessary | |
446 | * and updates the page directory (cayman+). | |
447 | * Returns 0 for success, error for failure. | |
448 | * | |
449 | * Global and local mutex must be locked! | |
450 | */ | |
451 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
452 | struct amdgpu_vm *vm) | |
453 | { | |
454 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
455 | struct amdgpu_bo *pd = vm->page_directory; | |
456 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
457 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
458 | uint64_t last_pde = ~0, last_pt = ~0; | |
459 | unsigned count = 0, pt_idx, ndw; | |
d5fc5e82 | 460 | struct amdgpu_ib *ib; |
4af9f07c | 461 | struct fence *fence = NULL; |
d5fc5e82 | 462 | |
d38ceaf9 AD |
463 | int r; |
464 | ||
465 | /* padding, etc. */ | |
466 | ndw = 64; | |
467 | ||
468 | /* assume the worst case */ | |
469 | ndw += vm->max_pde_used * 6; | |
470 | ||
471 | /* update too big for an IB */ | |
472 | if (ndw > 0xfffff) | |
473 | return -ENOMEM; | |
474 | ||
d5fc5e82 CZ |
475 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
476 | if (!ib) | |
477 | return -ENOMEM; | |
478 | ||
479 | r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); | |
7a574557 SM |
480 | if (r) { |
481 | kfree(ib); | |
d38ceaf9 | 482 | return r; |
7a574557 | 483 | } |
d5fc5e82 | 484 | ib->length_dw = 0; |
d38ceaf9 AD |
485 | |
486 | /* walk over the address space and update the page directory */ | |
487 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 488 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
489 | uint64_t pde, pt; |
490 | ||
491 | if (bo == NULL) | |
492 | continue; | |
493 | ||
494 | pt = amdgpu_bo_gpu_offset(bo); | |
495 | if (vm->page_tables[pt_idx].addr == pt) | |
496 | continue; | |
497 | vm->page_tables[pt_idx].addr = pt; | |
498 | ||
499 | pde = pd_addr + pt_idx * 8; | |
500 | if (((last_pde + 8 * count) != pde) || | |
501 | ((last_pt + incr * count) != pt)) { | |
502 | ||
503 | if (count) { | |
d5fc5e82 | 504 | amdgpu_vm_update_pages(adev, ib, last_pde, |
d38ceaf9 AD |
505 | last_pt, count, incr, |
506 | AMDGPU_PTE_VALID, 0); | |
507 | } | |
508 | ||
509 | count = 1; | |
510 | last_pde = pde; | |
511 | last_pt = pt; | |
512 | } else { | |
513 | ++count; | |
514 | } | |
515 | } | |
516 | ||
517 | if (count) | |
d5fc5e82 | 518 | amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count, |
d38ceaf9 AD |
519 | incr, AMDGPU_PTE_VALID, 0); |
520 | ||
d5fc5e82 CZ |
521 | if (ib->length_dw != 0) { |
522 | amdgpu_vm_pad_ib(adev, ib); | |
523 | amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM); | |
524 | WARN_ON(ib->length_dw > ndw); | |
4af9f07c CZ |
525 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
526 | &amdgpu_vm_free_job, | |
527 | AMDGPU_FENCE_OWNER_VM, | |
528 | &fence); | |
529 | if (r) | |
530 | goto error_free; | |
05906dec | 531 | |
4af9f07c | 532 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
533 | fence_put(vm->page_directory_fence); |
534 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 535 | fence_put(fence); |
d38ceaf9 | 536 | } |
d5fc5e82 | 537 | |
cadf97b1 | 538 | if (ib->length_dw == 0) { |
d5fc5e82 CZ |
539 | amdgpu_ib_free(adev, ib); |
540 | kfree(ib); | |
541 | } | |
d38ceaf9 AD |
542 | |
543 | return 0; | |
d5fc5e82 CZ |
544 | |
545 | error_free: | |
d5fc5e82 CZ |
546 | amdgpu_ib_free(adev, ib); |
547 | kfree(ib); | |
4af9f07c | 548 | return r; |
d38ceaf9 AD |
549 | } |
550 | ||
551 | /** | |
552 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
553 | * | |
554 | * @adev: amdgpu_device pointer | |
555 | * @ib: IB for the update | |
556 | * @pe_start: first PTE to handle | |
557 | * @pe_end: last PTE to handle | |
558 | * @addr: addr those PTEs should point to | |
559 | * @flags: hw mapping flags | |
560 | * @gtt_flags: GTT hw mapping flags | |
561 | * | |
562 | * Global and local mutex must be locked! | |
563 | */ | |
564 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
565 | struct amdgpu_ib *ib, | |
566 | uint64_t pe_start, uint64_t pe_end, | |
567 | uint64_t addr, uint32_t flags, | |
568 | uint32_t gtt_flags) | |
569 | { | |
570 | /** | |
571 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
572 | * field in the PTE. When this field is set to a non-zero value, page | |
573 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
574 | * flags are considered valid for all PTEs within the fragment range | |
575 | * and corresponding mappings are assumed to be physically contiguous. | |
576 | * | |
577 | * The L1 TLB can store a single PTE for the whole fragment, | |
578 | * significantly increasing the space available for translation | |
579 | * caching. This leads to large improvements in throughput when the | |
580 | * TLB is under pressure. | |
581 | * | |
582 | * The L2 TLB distributes small and large fragments into two | |
583 | * asymmetric partitions. The large fragment cache is significantly | |
584 | * larger. Thus, we try to use large fragments wherever possible. | |
585 | * Userspace can support this by aligning virtual base address and | |
586 | * allocation size to the fragment size. | |
587 | */ | |
588 | ||
589 | /* SI and newer are optimized for 64KB */ | |
590 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
591 | uint64_t frag_align = 0x80; | |
592 | ||
593 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
594 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
595 | ||
596 | unsigned count; | |
597 | ||
598 | /* system pages are non continuously */ | |
599 | if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) || | |
600 | (frag_start >= frag_end)) { | |
601 | ||
602 | count = (pe_end - pe_start) / 8; | |
603 | amdgpu_vm_update_pages(adev, ib, pe_start, addr, count, | |
604 | AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); | |
605 | return; | |
606 | } | |
607 | ||
608 | /* handle the 4K area at the beginning */ | |
609 | if (pe_start != frag_start) { | |
610 | count = (frag_start - pe_start) / 8; | |
611 | amdgpu_vm_update_pages(adev, ib, pe_start, addr, count, | |
612 | AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); | |
613 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
614 | } | |
615 | ||
616 | /* handle the area in the middle */ | |
617 | count = (frag_end - frag_start) / 8; | |
618 | amdgpu_vm_update_pages(adev, ib, frag_start, addr, count, | |
619 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags, | |
620 | gtt_flags); | |
621 | ||
622 | /* handle the 4K area at the end */ | |
623 | if (frag_end != pe_end) { | |
624 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
625 | count = (pe_end - frag_end) / 8; | |
626 | amdgpu_vm_update_pages(adev, ib, frag_end, addr, count, | |
627 | AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); | |
628 | } | |
629 | } | |
630 | ||
631 | /** | |
632 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
633 | * | |
634 | * @adev: amdgpu_device pointer | |
635 | * @vm: requested vm | |
636 | * @start: start of GPU address range | |
637 | * @end: end of GPU address range | |
638 | * @dst: destination address to map to | |
639 | * @flags: mapping flags | |
640 | * | |
641 | * Update the page tables in the range @start - @end (cayman+). | |
642 | * | |
643 | * Global and local mutex must be locked! | |
644 | */ | |
645 | static int amdgpu_vm_update_ptes(struct amdgpu_device *adev, | |
646 | struct amdgpu_vm *vm, | |
647 | struct amdgpu_ib *ib, | |
648 | uint64_t start, uint64_t end, | |
649 | uint64_t dst, uint32_t flags, | |
650 | uint32_t gtt_flags) | |
651 | { | |
652 | uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; | |
653 | uint64_t last_pte = ~0, last_dst = ~0; | |
a60c4232 | 654 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 AD |
655 | unsigned count = 0; |
656 | uint64_t addr; | |
657 | ||
a60c4232 CK |
658 | /* sync to everything on unmapping */ |
659 | if (!(flags & AMDGPU_PTE_VALID)) | |
660 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
661 | ||
d38ceaf9 AD |
662 | /* walk over the address space and update the page tables */ |
663 | for (addr = start; addr < end; ) { | |
664 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | |
ee1782c3 | 665 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
666 | unsigned nptes; |
667 | uint64_t pte; | |
668 | int r; | |
669 | ||
a60c4232 | 670 | amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner); |
d38ceaf9 AD |
671 | r = reservation_object_reserve_shared(pt->tbo.resv); |
672 | if (r) | |
673 | return r; | |
674 | ||
675 | if ((addr & ~mask) == (end & ~mask)) | |
676 | nptes = end - addr; | |
677 | else | |
678 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
679 | ||
680 | pte = amdgpu_bo_gpu_offset(pt); | |
681 | pte += (addr & mask) * 8; | |
682 | ||
683 | if ((last_pte + 8 * count) != pte) { | |
684 | ||
685 | if (count) { | |
686 | amdgpu_vm_frag_ptes(adev, ib, last_pte, | |
687 | last_pte + 8 * count, | |
688 | last_dst, flags, | |
689 | gtt_flags); | |
690 | } | |
691 | ||
692 | count = nptes; | |
693 | last_pte = pte; | |
694 | last_dst = dst; | |
695 | } else { | |
696 | count += nptes; | |
697 | } | |
698 | ||
699 | addr += nptes; | |
700 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
701 | } | |
702 | ||
703 | if (count) { | |
704 | amdgpu_vm_frag_ptes(adev, ib, last_pte, | |
705 | last_pte + 8 * count, | |
706 | last_dst, flags, gtt_flags); | |
707 | } | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
d38ceaf9 AD |
712 | /** |
713 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
714 | * | |
715 | * @adev: amdgpu_device pointer | |
716 | * @vm: requested vm | |
717 | * @mapping: mapped range and flags to use for the update | |
718 | * @addr: addr to set the area to | |
719 | * @gtt_flags: flags as they are used for GTT | |
720 | * @fence: optional resulting fence | |
721 | * | |
722 | * Fill in the page table entries for @mapping. | |
723 | * Returns 0 for success, -EINVAL for failure. | |
724 | * | |
725 | * Object have to be reserved and mutex must be locked! | |
726 | */ | |
727 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
728 | struct amdgpu_vm *vm, | |
729 | struct amdgpu_bo_va_mapping *mapping, | |
730 | uint64_t addr, uint32_t gtt_flags, | |
bb1e38a4 | 731 | struct fence **fence) |
d38ceaf9 AD |
732 | { |
733 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
734 | unsigned nptes, ncmds, ndw; | |
735 | uint32_t flags = gtt_flags; | |
d5fc5e82 | 736 | struct amdgpu_ib *ib; |
4af9f07c | 737 | struct fence *f = NULL; |
d38ceaf9 AD |
738 | int r; |
739 | ||
740 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
741 | * but in case of something, we filter the flags in first place | |
742 | */ | |
743 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
744 | flags &= ~AMDGPU_PTE_READABLE; | |
745 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
746 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
747 | ||
748 | trace_amdgpu_vm_bo_update(mapping); | |
749 | ||
750 | nptes = mapping->it.last - mapping->it.start + 1; | |
751 | ||
752 | /* | |
753 | * reserve space for one command every (1 << BLOCK_SIZE) | |
754 | * entries or 2k dwords (whatever is smaller) | |
755 | */ | |
756 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
757 | ||
758 | /* padding, etc. */ | |
759 | ndw = 64; | |
760 | ||
761 | if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) { | |
762 | /* only copy commands needed */ | |
763 | ndw += ncmds * 7; | |
764 | ||
765 | } else if (flags & AMDGPU_PTE_SYSTEM) { | |
766 | /* header for write data commands */ | |
767 | ndw += ncmds * 4; | |
768 | ||
769 | /* body of write data command */ | |
770 | ndw += nptes * 2; | |
771 | ||
772 | } else { | |
773 | /* set page commands needed */ | |
774 | ndw += ncmds * 10; | |
775 | ||
776 | /* two extra commands for begin/end of fragment */ | |
777 | ndw += 2 * 10; | |
778 | } | |
779 | ||
780 | /* update too big for an IB */ | |
781 | if (ndw > 0xfffff) | |
782 | return -ENOMEM; | |
783 | ||
d5fc5e82 CZ |
784 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
785 | if (!ib) | |
786 | return -ENOMEM; | |
787 | ||
788 | r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); | |
789 | if (r) { | |
790 | kfree(ib); | |
d38ceaf9 | 791 | return r; |
d5fc5e82 CZ |
792 | } |
793 | ||
794 | ib->length_dw = 0; | |
d38ceaf9 | 795 | |
d5fc5e82 | 796 | r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start, |
d38ceaf9 AD |
797 | mapping->it.last + 1, addr + mapping->offset, |
798 | flags, gtt_flags); | |
799 | ||
800 | if (r) { | |
d5fc5e82 CZ |
801 | amdgpu_ib_free(adev, ib); |
802 | kfree(ib); | |
d38ceaf9 AD |
803 | return r; |
804 | } | |
805 | ||
d5fc5e82 CZ |
806 | amdgpu_vm_pad_ib(adev, ib); |
807 | WARN_ON(ib->length_dw > ndw); | |
4af9f07c CZ |
808 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
809 | &amdgpu_vm_free_job, | |
810 | AMDGPU_FENCE_OWNER_VM, | |
811 | &f); | |
812 | if (r) | |
813 | goto error_free; | |
d38ceaf9 | 814 | |
bf60efd3 | 815 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
816 | if (fence) { |
817 | fence_put(*fence); | |
818 | *fence = fence_get(f); | |
819 | } | |
281b4223 | 820 | fence_put(f); |
d38ceaf9 | 821 | return 0; |
d5fc5e82 CZ |
822 | |
823 | error_free: | |
d5fc5e82 CZ |
824 | amdgpu_ib_free(adev, ib); |
825 | kfree(ib); | |
4af9f07c | 826 | return r; |
d38ceaf9 AD |
827 | } |
828 | ||
829 | /** | |
830 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
831 | * | |
832 | * @adev: amdgpu_device pointer | |
833 | * @bo_va: requested BO and VM object | |
834 | * @mem: ttm mem | |
835 | * | |
836 | * Fill in the page table entries for @bo_va. | |
837 | * Returns 0 for success, -EINVAL for failure. | |
838 | * | |
839 | * Object have to be reserved and mutex must be locked! | |
840 | */ | |
841 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
842 | struct amdgpu_bo_va *bo_va, | |
843 | struct ttm_mem_reg *mem) | |
844 | { | |
845 | struct amdgpu_vm *vm = bo_va->vm; | |
846 | struct amdgpu_bo_va_mapping *mapping; | |
847 | uint32_t flags; | |
848 | uint64_t addr; | |
849 | int r; | |
850 | ||
851 | if (mem) { | |
b7d698d7 | 852 | addr = (u64)mem->start << PAGE_SHIFT; |
d38ceaf9 AD |
853 | if (mem->mem_type != TTM_PL_TT) |
854 | addr += adev->vm_manager.vram_base_offset; | |
855 | } else { | |
856 | addr = 0; | |
857 | } | |
858 | ||
d38ceaf9 AD |
859 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
860 | ||
7fc11959 CK |
861 | spin_lock(&vm->status_lock); |
862 | if (!list_empty(&bo_va->vm_status)) | |
863 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
864 | spin_unlock(&vm->status_lock); | |
865 | ||
866 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
d38ceaf9 AD |
867 | r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr, |
868 | flags, &bo_va->last_pt_update); | |
869 | if (r) | |
870 | return r; | |
871 | } | |
872 | ||
d6c10f6b CK |
873 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
874 | list_for_each_entry(mapping, &bo_va->valids, list) | |
875 | trace_amdgpu_vm_bo_mapping(mapping); | |
876 | ||
877 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
878 | trace_amdgpu_vm_bo_mapping(mapping); | |
879 | } | |
880 | ||
d38ceaf9 | 881 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 882 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 883 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
884 | if (!mem) |
885 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
886 | spin_unlock(&vm->status_lock); |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
891 | /** | |
892 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
893 | * | |
894 | * @adev: amdgpu_device pointer | |
895 | * @vm: requested vm | |
896 | * | |
897 | * Make sure all freed BOs are cleared in the PT. | |
898 | * Returns 0 for success. | |
899 | * | |
900 | * PTs have to be reserved and mutex must be locked! | |
901 | */ | |
902 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
903 | struct amdgpu_vm *vm) | |
904 | { | |
905 | struct amdgpu_bo_va_mapping *mapping; | |
906 | int r; | |
907 | ||
81d75a30 | 908 | spin_lock(&vm->freed_lock); |
d38ceaf9 AD |
909 | while (!list_empty(&vm->freed)) { |
910 | mapping = list_first_entry(&vm->freed, | |
911 | struct amdgpu_bo_va_mapping, list); | |
912 | list_del(&mapping->list); | |
81d75a30 | 913 | spin_unlock(&vm->freed_lock); |
d38ceaf9 AD |
914 | r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL); |
915 | kfree(mapping); | |
916 | if (r) | |
917 | return r; | |
918 | ||
81d75a30 | 919 | spin_lock(&vm->freed_lock); |
d38ceaf9 | 920 | } |
81d75a30 | 921 | spin_unlock(&vm->freed_lock); |
922 | ||
d38ceaf9 AD |
923 | return 0; |
924 | ||
925 | } | |
926 | ||
927 | /** | |
928 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
929 | * | |
930 | * @adev: amdgpu_device pointer | |
931 | * @vm: requested vm | |
932 | * | |
933 | * Make sure all invalidated BOs are cleared in the PT. | |
934 | * Returns 0 for success. | |
935 | * | |
936 | * PTs have to be reserved and mutex must be locked! | |
937 | */ | |
938 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 939 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 940 | { |
cfe2c978 | 941 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 942 | int r = 0; |
d38ceaf9 AD |
943 | |
944 | spin_lock(&vm->status_lock); | |
945 | while (!list_empty(&vm->invalidated)) { | |
946 | bo_va = list_first_entry(&vm->invalidated, | |
947 | struct amdgpu_bo_va, vm_status); | |
948 | spin_unlock(&vm->status_lock); | |
69b576a1 | 949 | mutex_lock(&bo_va->mutex); |
d38ceaf9 | 950 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
69b576a1 | 951 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 AD |
952 | if (r) |
953 | return r; | |
954 | ||
955 | spin_lock(&vm->status_lock); | |
956 | } | |
957 | spin_unlock(&vm->status_lock); | |
958 | ||
cfe2c978 | 959 | if (bo_va) |
bb1e38a4 | 960 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
961 | |
962 | return r; | |
d38ceaf9 AD |
963 | } |
964 | ||
965 | /** | |
966 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
967 | * | |
968 | * @adev: amdgpu_device pointer | |
969 | * @vm: requested vm | |
970 | * @bo: amdgpu buffer object | |
971 | * | |
972 | * Add @bo into the requested vm (cayman+). | |
973 | * Add @bo to the list of bos associated with the vm | |
974 | * Returns newly added bo_va or NULL for failure | |
975 | * | |
976 | * Object has to be reserved! | |
977 | */ | |
978 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
979 | struct amdgpu_vm *vm, | |
980 | struct amdgpu_bo *bo) | |
981 | { | |
982 | struct amdgpu_bo_va *bo_va; | |
983 | ||
984 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
985 | if (bo_va == NULL) { | |
986 | return NULL; | |
987 | } | |
988 | bo_va->vm = vm; | |
989 | bo_va->bo = bo; | |
d38ceaf9 AD |
990 | bo_va->ref_count = 1; |
991 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
992 | INIT_LIST_HEAD(&bo_va->valids); |
993 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 994 | INIT_LIST_HEAD(&bo_va->vm_status); |
69b576a1 | 995 | mutex_init(&bo_va->mutex); |
d38ceaf9 | 996 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
997 | |
998 | return bo_va; | |
999 | } | |
1000 | ||
1001 | /** | |
1002 | * amdgpu_vm_bo_map - map bo inside a vm | |
1003 | * | |
1004 | * @adev: amdgpu_device pointer | |
1005 | * @bo_va: bo_va to store the address | |
1006 | * @saddr: where to map the BO | |
1007 | * @offset: requested offset in the BO | |
1008 | * @flags: attributes of pages (read/write/valid/etc.) | |
1009 | * | |
1010 | * Add a mapping of the BO at the specefied addr into the VM. | |
1011 | * Returns 0 for success, error for failure. | |
1012 | * | |
49b02b18 | 1013 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1014 | */ |
1015 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1016 | struct amdgpu_bo_va *bo_va, | |
1017 | uint64_t saddr, uint64_t offset, | |
1018 | uint64_t size, uint32_t flags) | |
1019 | { | |
1020 | struct amdgpu_bo_va_mapping *mapping; | |
1021 | struct amdgpu_vm *vm = bo_va->vm; | |
1022 | struct interval_tree_node *it; | |
1023 | unsigned last_pfn, pt_idx; | |
1024 | uint64_t eaddr; | |
1025 | int r; | |
1026 | ||
0be52de9 CK |
1027 | /* validate the parameters */ |
1028 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1029 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1030 | return -EINVAL; |
0be52de9 | 1031 | |
d38ceaf9 | 1032 | /* make sure object fit at this offset */ |
005ae95e | 1033 | eaddr = saddr + size - 1; |
49b02b18 | 1034 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1035 | return -EINVAL; |
d38ceaf9 AD |
1036 | |
1037 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1038 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1039 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1040 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1041 | return -EINVAL; |
1042 | } | |
1043 | ||
d38ceaf9 AD |
1044 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1045 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1046 | ||
c25867df | 1047 | spin_lock(&vm->it_lock); |
005ae95e | 1048 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
c25867df | 1049 | spin_unlock(&vm->it_lock); |
d38ceaf9 AD |
1050 | if (it) { |
1051 | struct amdgpu_bo_va_mapping *tmp; | |
1052 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1053 | /* bo and tmp overlap, invalid addr */ | |
1054 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1055 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1056 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1057 | r = -EINVAL; |
f48b2659 | 1058 | goto error; |
d38ceaf9 AD |
1059 | } |
1060 | ||
1061 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1062 | if (!mapping) { | |
d38ceaf9 | 1063 | r = -ENOMEM; |
f48b2659 | 1064 | goto error; |
d38ceaf9 AD |
1065 | } |
1066 | ||
1067 | INIT_LIST_HEAD(&mapping->list); | |
1068 | mapping->it.start = saddr; | |
005ae95e | 1069 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1070 | mapping->offset = offset; |
1071 | mapping->flags = flags; | |
1072 | ||
69b576a1 | 1073 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1074 | list_add(&mapping->list, &bo_va->invalids); |
69b576a1 | 1075 | mutex_unlock(&bo_va->mutex); |
c25867df | 1076 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1077 | interval_tree_insert(&mapping->it, &vm->va); |
c25867df | 1078 | spin_unlock(&vm->it_lock); |
93e3e438 | 1079 | trace_amdgpu_vm_bo_map(bo_va, mapping); |
d38ceaf9 AD |
1080 | |
1081 | /* Make sure the page tables are allocated */ | |
1082 | saddr >>= amdgpu_vm_block_size; | |
1083 | eaddr >>= amdgpu_vm_block_size; | |
1084 | ||
1085 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1086 | ||
1087 | if (eaddr > vm->max_pde_used) | |
1088 | vm->max_pde_used = eaddr; | |
1089 | ||
d38ceaf9 AD |
1090 | /* walk over the address space and allocate the page tables */ |
1091 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1092 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1093 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1094 | struct amdgpu_bo *pt; |
1095 | ||
ee1782c3 CK |
1096 | entry = &vm->page_tables[pt_idx].entry; |
1097 | if (entry->robj) | |
d38ceaf9 AD |
1098 | continue; |
1099 | ||
d38ceaf9 AD |
1100 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1101 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1102 | AMDGPU_GEM_DOMAIN_VRAM, |
1103 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 | 1104 | NULL, resv, &pt); |
49b02b18 | 1105 | if (r) |
d38ceaf9 | 1106 | goto error_free; |
49b02b18 | 1107 | |
82b9c55b CK |
1108 | /* Keep a reference to the page table to avoid freeing |
1109 | * them up in the wrong order. | |
1110 | */ | |
1111 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1112 | ||
d38ceaf9 AD |
1113 | r = amdgpu_vm_clear_bo(adev, pt); |
1114 | if (r) { | |
1115 | amdgpu_bo_unref(&pt); | |
1116 | goto error_free; | |
1117 | } | |
1118 | ||
ee1782c3 | 1119 | entry->robj = pt; |
ee1782c3 CK |
1120 | entry->priority = 0; |
1121 | entry->tv.bo = &entry->robj->tbo; | |
1122 | entry->tv.shared = true; | |
d38ceaf9 | 1123 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1124 | } |
1125 | ||
d38ceaf9 AD |
1126 | return 0; |
1127 | ||
1128 | error_free: | |
d38ceaf9 | 1129 | list_del(&mapping->list); |
c25867df | 1130 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1131 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1132 | spin_unlock(&vm->it_lock); |
93e3e438 | 1133 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1134 | kfree(mapping); |
1135 | ||
f48b2659 | 1136 | error: |
d38ceaf9 AD |
1137 | return r; |
1138 | } | |
1139 | ||
1140 | /** | |
1141 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1142 | * | |
1143 | * @adev: amdgpu_device pointer | |
1144 | * @bo_va: bo_va to remove the address from | |
1145 | * @saddr: where to the BO is mapped | |
1146 | * | |
1147 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1148 | * Returns 0 for success, error for failure. | |
1149 | * | |
49b02b18 | 1150 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1151 | */ |
1152 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1153 | struct amdgpu_bo_va *bo_va, | |
1154 | uint64_t saddr) | |
1155 | { | |
1156 | struct amdgpu_bo_va_mapping *mapping; | |
1157 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1158 | bool valid = true; |
d38ceaf9 | 1159 | |
6c7fc503 | 1160 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
69b576a1 | 1161 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1162 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1163 | if (mapping->it.start == saddr) |
1164 | break; | |
1165 | } | |
1166 | ||
7fc11959 CK |
1167 | if (&mapping->list == &bo_va->valids) { |
1168 | valid = false; | |
1169 | ||
1170 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1171 | if (mapping->it.start == saddr) | |
1172 | break; | |
1173 | } | |
1174 | ||
69b576a1 CZ |
1175 | if (&mapping->list == &bo_va->invalids) { |
1176 | mutex_unlock(&bo_va->mutex); | |
7fc11959 | 1177 | return -ENOENT; |
69b576a1 | 1178 | } |
d38ceaf9 | 1179 | } |
69b576a1 | 1180 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 | 1181 | list_del(&mapping->list); |
c25867df | 1182 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1183 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1184 | spin_unlock(&vm->it_lock); |
93e3e438 | 1185 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1186 | |
81d75a30 | 1187 | if (valid) { |
1188 | spin_lock(&vm->freed_lock); | |
d38ceaf9 | 1189 | list_add(&mapping->list, &vm->freed); |
81d75a30 | 1190 | spin_unlock(&vm->freed_lock); |
1191 | } else { | |
d38ceaf9 | 1192 | kfree(mapping); |
81d75a30 | 1193 | } |
d38ceaf9 AD |
1194 | |
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | /** | |
1199 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1200 | * | |
1201 | * @adev: amdgpu_device pointer | |
1202 | * @bo_va: requested bo_va | |
1203 | * | |
1204 | * Remove @bo_va->bo from the requested vm (cayman+). | |
1205 | * | |
1206 | * Object have to be reserved! | |
1207 | */ | |
1208 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1209 | struct amdgpu_bo_va *bo_va) | |
1210 | { | |
1211 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1212 | struct amdgpu_vm *vm = bo_va->vm; | |
1213 | ||
1214 | list_del(&bo_va->bo_list); | |
1215 | ||
d38ceaf9 AD |
1216 | spin_lock(&vm->status_lock); |
1217 | list_del(&bo_va->vm_status); | |
1218 | spin_unlock(&vm->status_lock); | |
1219 | ||
7fc11959 | 1220 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 1221 | list_del(&mapping->list); |
c25867df | 1222 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1223 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1224 | spin_unlock(&vm->it_lock); |
93e3e438 | 1225 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
81d75a30 | 1226 | spin_lock(&vm->freed_lock); |
7fc11959 | 1227 | list_add(&mapping->list, &vm->freed); |
81d75a30 | 1228 | spin_unlock(&vm->freed_lock); |
7fc11959 CK |
1229 | } |
1230 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1231 | list_del(&mapping->list); | |
c25867df | 1232 | spin_lock(&vm->it_lock); |
7fc11959 | 1233 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1234 | spin_unlock(&vm->it_lock); |
7fc11959 | 1235 | kfree(mapping); |
d38ceaf9 | 1236 | } |
bb1e38a4 | 1237 | fence_put(bo_va->last_pt_update); |
69b576a1 | 1238 | mutex_destroy(&bo_va->mutex); |
d38ceaf9 | 1239 | kfree(bo_va); |
d38ceaf9 AD |
1240 | } |
1241 | ||
1242 | /** | |
1243 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1244 | * | |
1245 | * @adev: amdgpu_device pointer | |
1246 | * @vm: requested vm | |
1247 | * @bo: amdgpu buffer object | |
1248 | * | |
1249 | * Mark @bo as invalid (cayman+). | |
1250 | */ | |
1251 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1252 | struct amdgpu_bo *bo) | |
1253 | { | |
1254 | struct amdgpu_bo_va *bo_va; | |
1255 | ||
1256 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1257 | spin_lock(&bo_va->vm->status_lock); |
1258 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1259 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1260 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1261 | } |
1262 | } | |
1263 | ||
1264 | /** | |
1265 | * amdgpu_vm_init - initialize a vm instance | |
1266 | * | |
1267 | * @adev: amdgpu_device pointer | |
1268 | * @vm: requested vm | |
1269 | * | |
1270 | * Init @vm fields (cayman+). | |
1271 | */ | |
1272 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1273 | { | |
1274 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1275 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1276 | unsigned pd_size, pd_entries; |
d38ceaf9 AD |
1277 | int i, r; |
1278 | ||
1279 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1280 | vm->ids[i].id = 0; | |
1281 | vm->ids[i].flushed_updates = NULL; | |
d38ceaf9 | 1282 | } |
d38ceaf9 AD |
1283 | vm->va = RB_ROOT; |
1284 | spin_lock_init(&vm->status_lock); | |
1285 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1286 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1287 | INIT_LIST_HEAD(&vm->freed); |
c25867df | 1288 | spin_lock_init(&vm->it_lock); |
81d75a30 | 1289 | spin_lock_init(&vm->freed_lock); |
d38ceaf9 AD |
1290 | pd_size = amdgpu_vm_directory_size(adev); |
1291 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1292 | ||
1293 | /* allocate page table array */ | |
9571e1d8 | 1294 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1295 | if (vm->page_tables == NULL) { |
1296 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1297 | return -ENOMEM; | |
1298 | } | |
1299 | ||
05906dec BN |
1300 | vm->page_directory_fence = NULL; |
1301 | ||
d38ceaf9 | 1302 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1303 | AMDGPU_GEM_DOMAIN_VRAM, |
1304 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1305 | NULL, NULL, &vm->page_directory); |
d38ceaf9 AD |
1306 | if (r) |
1307 | return r; | |
ef9f0a83 CZ |
1308 | r = amdgpu_bo_reserve(vm->page_directory, false); |
1309 | if (r) { | |
1310 | amdgpu_bo_unref(&vm->page_directory); | |
1311 | vm->page_directory = NULL; | |
1312 | return r; | |
1313 | } | |
d38ceaf9 | 1314 | r = amdgpu_vm_clear_bo(adev, vm->page_directory); |
ef9f0a83 | 1315 | amdgpu_bo_unreserve(vm->page_directory); |
d38ceaf9 AD |
1316 | if (r) { |
1317 | amdgpu_bo_unref(&vm->page_directory); | |
1318 | vm->page_directory = NULL; | |
1319 | return r; | |
1320 | } | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
1325 | /** | |
1326 | * amdgpu_vm_fini - tear down a vm instance | |
1327 | * | |
1328 | * @adev: amdgpu_device pointer | |
1329 | * @vm: requested vm | |
1330 | * | |
1331 | * Tear down @vm (cayman+). | |
1332 | * Unbind the VM and remove all bos from the vm bo list | |
1333 | */ | |
1334 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1335 | { | |
1336 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1337 | int i; | |
1338 | ||
1339 | if (!RB_EMPTY_ROOT(&vm->va)) { | |
1340 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1341 | } | |
1342 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1343 | list_del(&mapping->list); | |
1344 | interval_tree_remove(&mapping->it, &vm->va); | |
1345 | kfree(mapping); | |
1346 | } | |
1347 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1348 | list_del(&mapping->list); | |
1349 | kfree(mapping); | |
1350 | } | |
1351 | ||
1352 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
ee1782c3 | 1353 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
9571e1d8 | 1354 | drm_free_large(vm->page_tables); |
d38ceaf9 AD |
1355 | |
1356 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1357 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1358 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
1c16c0a7 CK |
1359 | unsigned id = vm->ids[i].id; |
1360 | ||
1361 | atomic_long_cmpxchg(&adev->vm_manager.ids[id].owner, | |
1362 | (long)vm, 0); | |
3c62338c | 1363 | fence_put(vm->ids[i].flushed_updates); |
d38ceaf9 AD |
1364 | } |
1365 | ||
d38ceaf9 | 1366 | } |
ea89f8c9 CK |
1367 | |
1368 | /** | |
1369 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1370 | * | |
1371 | * @adev: amdgpu_device pointer | |
1372 | * | |
1373 | * Cleanup the VM manager and free resources. | |
1374 | */ | |
1375 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1376 | { | |
1377 | unsigned i; | |
1378 | ||
1379 | for (i = 0; i < AMDGPU_NUM_VM; ++i) | |
1c16c0a7 | 1380 | fence_put(adev->vm_manager.ids[i].active); |
ea89f8c9 | 1381 | } |