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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
02208441 | 30 | #include <linux/idr.h> |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "amdgpu_trace.h" | |
ede0dd86 | 35 | #include "amdgpu_amdkfd.h" |
d38ceaf9 | 36 | |
7fc48e59 AG |
37 | /** |
38 | * DOC: GPUVM | |
39 | * | |
d38ceaf9 AD |
40 | * GPUVM is similar to the legacy gart on older asics, however |
41 | * rather than there being a single global gart table | |
42 | * for the entire GPU, there are multiple VM page tables active | |
43 | * at any given time. The VM page tables can contain a mix | |
44 | * vram pages and system memory pages and system memory pages | |
45 | * can be mapped as snooped (cached system pages) or unsnooped | |
46 | * (uncached system pages). | |
47 | * Each VM has an ID associated with it and there is a page table | |
48 | * associated with each VMID. When execting a command buffer, | |
49 | * the kernel tells the the ring what VMID to use for that command | |
50 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
51 | * The userspace drivers maintain their own address space and the kernel | |
52 | * sets up their pages tables accordingly when they submit their | |
53 | * command buffers and a VMID is assigned. | |
54 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
55 | * SI supports 16. | |
56 | */ | |
57 | ||
a9f87f64 CK |
58 | #define START(node) ((node)->start) |
59 | #define LAST(node) ((node)->last) | |
60 | ||
61 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
62 | START, LAST, static, amdgpu_vm_it) | |
63 | ||
64 | #undef START | |
65 | #undef LAST | |
66 | ||
7fc48e59 AG |
67 | /** |
68 | * struct amdgpu_pte_update_params - Local structure | |
69 | * | |
70 | * Encapsulate some VM table update parameters to reduce | |
f4833c4f | 71 | * the number of function parameters |
7fc48e59 | 72 | * |
f4833c4f | 73 | */ |
29efc4f5 | 74 | struct amdgpu_pte_update_params { |
7fc48e59 AG |
75 | |
76 | /** | |
77 | * @adev: amdgpu device we do this update for | |
78 | */ | |
27c5f36f | 79 | struct amdgpu_device *adev; |
7fc48e59 AG |
80 | |
81 | /** | |
82 | * @vm: optional amdgpu_vm we do this update for | |
83 | */ | |
49ac8a24 | 84 | struct amdgpu_vm *vm; |
7fc48e59 AG |
85 | |
86 | /** | |
87 | * @src: address where to copy page table entries from | |
88 | */ | |
f4833c4f | 89 | uint64_t src; |
7fc48e59 AG |
90 | |
91 | /** | |
92 | * @ib: indirect buffer to fill with commands | |
93 | */ | |
f4833c4f | 94 | struct amdgpu_ib *ib; |
7fc48e59 AG |
95 | |
96 | /** | |
97 | * @func: Function which actually does the update | |
98 | */ | |
373ac645 CK |
99 | void (*func)(struct amdgpu_pte_update_params *params, |
100 | struct amdgpu_bo *bo, uint64_t pe, | |
afef8b8f | 101 | uint64_t addr, unsigned count, uint32_t incr, |
6b777607 | 102 | uint64_t flags); |
7fc48e59 AG |
103 | /** |
104 | * @pages_addr: | |
105 | * | |
106 | * DMA addresses to use for mapping, used during VM update by CPU | |
b4d42511 HK |
107 | */ |
108 | dma_addr_t *pages_addr; | |
7fc48e59 AG |
109 | |
110 | /** | |
111 | * @kptr: | |
112 | * | |
113 | * Kernel pointer of PD/PT BO that needs to be updated, | |
114 | * used during VM update by CPU | |
115 | */ | |
b4d42511 | 116 | void *kptr; |
f4833c4f HK |
117 | }; |
118 | ||
7fc48e59 AG |
119 | /** |
120 | * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback | |
121 | */ | |
284710fa | 122 | struct amdgpu_prt_cb { |
7fc48e59 AG |
123 | |
124 | /** | |
125 | * @adev: amdgpu device | |
126 | */ | |
284710fa | 127 | struct amdgpu_device *adev; |
7fc48e59 AG |
128 | |
129 | /** | |
130 | * @cb: callback | |
131 | */ | |
284710fa CK |
132 | struct dma_fence_cb cb; |
133 | }; | |
134 | ||
7fc48e59 AG |
135 | /** |
136 | * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm | |
137 | * | |
138 | * @base: base structure for tracking BO usage in a VM | |
139 | * @vm: vm to which bo is to be added | |
140 | * @bo: amdgpu buffer object | |
141 | * | |
142 | * Initialize a bo_va_base structure and add it to the appropriate lists | |
143 | * | |
144 | */ | |
3f4299be CZ |
145 | static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, |
146 | struct amdgpu_vm *vm, | |
147 | struct amdgpu_bo *bo) | |
148 | { | |
149 | base->vm = vm; | |
150 | base->bo = bo; | |
151 | INIT_LIST_HEAD(&base->bo_list); | |
152 | INIT_LIST_HEAD(&base->vm_status); | |
153 | ||
154 | if (!bo) | |
155 | return; | |
156 | list_add_tail(&base->bo_list, &bo->va); | |
157 | ||
158 | if (bo->tbo.resv != vm->root.base.bo->tbo.resv) | |
159 | return; | |
160 | ||
161 | if (bo->preferred_domains & | |
162 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)) | |
163 | return; | |
164 | ||
165 | /* | |
166 | * we checked all the prerequisites, but it looks like this per vm bo | |
167 | * is currently evicted. add the bo to the evicted list to make sure it | |
168 | * is validated on next vm use to avoid fault. | |
169 | * */ | |
3f4299be | 170 | list_move_tail(&base->vm_status, &vm->evicted); |
3f4299be CZ |
171 | } |
172 | ||
50783147 CK |
173 | /** |
174 | * amdgpu_vm_level_shift - return the addr shift for each level | |
175 | * | |
176 | * @adev: amdgpu_device pointer | |
7fc48e59 | 177 | * @level: VMPT level |
50783147 | 178 | * |
7fc48e59 AG |
179 | * Returns: |
180 | * The number of bits the pfn needs to be right shifted for a level. | |
50783147 CK |
181 | */ |
182 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
183 | unsigned level) | |
184 | { | |
196f7489 CZ |
185 | unsigned shift = 0xff; |
186 | ||
187 | switch (level) { | |
188 | case AMDGPU_VM_PDB2: | |
189 | case AMDGPU_VM_PDB1: | |
190 | case AMDGPU_VM_PDB0: | |
191 | shift = 9 * (AMDGPU_VM_PDB0 - level) + | |
50783147 | 192 | adev->vm_manager.block_size; |
196f7489 CZ |
193 | break; |
194 | case AMDGPU_VM_PTB: | |
195 | shift = 0; | |
196 | break; | |
197 | default: | |
198 | dev_err(adev->dev, "the level%d isn't supported.\n", level); | |
199 | } | |
200 | ||
201 | return shift; | |
50783147 CK |
202 | } |
203 | ||
d38ceaf9 | 204 | /** |
72a7ec5c | 205 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
206 | * |
207 | * @adev: amdgpu_device pointer | |
7fc48e59 | 208 | * @level: VMPT level |
d38ceaf9 | 209 | * |
7fc48e59 AG |
210 | * Returns: |
211 | * The number of entries in a page directory or page table. | |
d38ceaf9 | 212 | */ |
72a7ec5c CK |
213 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
214 | unsigned level) | |
d38ceaf9 | 215 | { |
196f7489 CZ |
216 | unsigned shift = amdgpu_vm_level_shift(adev, |
217 | adev->vm_manager.root_level); | |
0410c5e5 | 218 | |
196f7489 | 219 | if (level == adev->vm_manager.root_level) |
72a7ec5c | 220 | /* For the root directory */ |
0410c5e5 | 221 | return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; |
196f7489 | 222 | else if (level != AMDGPU_VM_PTB) |
0410c5e5 CK |
223 | /* Everything in between */ |
224 | return 512; | |
225 | else | |
72a7ec5c | 226 | /* For the page tables on the leaves */ |
36b32a68 | 227 | return AMDGPU_VM_PTE_COUNT(adev); |
d38ceaf9 AD |
228 | } |
229 | ||
230 | /** | |
72a7ec5c | 231 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
232 | * |
233 | * @adev: amdgpu_device pointer | |
7fc48e59 | 234 | * @level: VMPT level |
d38ceaf9 | 235 | * |
7fc48e59 AG |
236 | * Returns: |
237 | * The size of the BO for a page directory or page table in bytes. | |
d38ceaf9 | 238 | */ |
72a7ec5c | 239 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 240 | { |
72a7ec5c | 241 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
242 | } |
243 | ||
244 | /** | |
56467ebf | 245 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
246 | * |
247 | * @vm: vm providing the BOs | |
3c0eea6c | 248 | * @validated: head of validation list |
56467ebf | 249 | * @entry: entry to add |
d38ceaf9 AD |
250 | * |
251 | * Add the page directory to the list of BOs to | |
56467ebf | 252 | * validate for command submission. |
d38ceaf9 | 253 | */ |
56467ebf CK |
254 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
255 | struct list_head *validated, | |
256 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 257 | { |
3f3333f8 | 258 | entry->robj = vm->root.base.bo; |
56467ebf | 259 | entry->priority = 0; |
67003a15 | 260 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 261 | entry->tv.shared = true; |
2f568dbd | 262 | entry->user_pages = NULL; |
56467ebf CK |
263 | list_add(&entry->tv.head, validated); |
264 | } | |
d38ceaf9 | 265 | |
670fecc8 | 266 | /** |
f7da30d9 | 267 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
670fecc8 | 268 | * |
5a712a87 | 269 | * @adev: amdgpu device pointer |
56467ebf | 270 | * @vm: vm providing the BOs |
670fecc8 CK |
271 | * @validate: callback to do the validation |
272 | * @param: parameter for the validation callback | |
273 | * | |
274 | * Validate the page table BOs on command submission if neccessary. | |
7fc48e59 AG |
275 | * |
276 | * Returns: | |
277 | * Validation result. | |
670fecc8 | 278 | */ |
f7da30d9 CK |
279 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
280 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
281 | void *param) | |
670fecc8 | 282 | { |
3f3333f8 | 283 | struct ttm_bo_global *glob = adev->mman.bdev.glob; |
91ccdd24 CK |
284 | struct amdgpu_vm_bo_base *bo_base, *tmp; |
285 | int r = 0; | |
670fecc8 | 286 | |
91ccdd24 CK |
287 | list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { |
288 | struct amdgpu_bo *bo = bo_base->bo; | |
670fecc8 | 289 | |
3f3333f8 CK |
290 | if (bo->parent) { |
291 | r = validate(param, bo); | |
292 | if (r) | |
91ccdd24 | 293 | break; |
670fecc8 | 294 | |
3f3333f8 CK |
295 | spin_lock(&glob->lru_lock); |
296 | ttm_bo_move_to_lru_tail(&bo->tbo); | |
297 | if (bo->shadow) | |
298 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo); | |
299 | spin_unlock(&glob->lru_lock); | |
300 | } | |
670fecc8 | 301 | |
af4c0f65 CK |
302 | if (bo->tbo.type != ttm_bo_type_kernel) { |
303 | spin_lock(&vm->moved_lock); | |
73fb16e7 | 304 | list_move(&bo_base->vm_status, &vm->moved); |
af4c0f65 CK |
305 | spin_unlock(&vm->moved_lock); |
306 | } else { | |
73fb16e7 | 307 | list_move(&bo_base->vm_status, &vm->relocated); |
af4c0f65 | 308 | } |
670fecc8 CK |
309 | } |
310 | ||
806f043f CK |
311 | spin_lock(&glob->lru_lock); |
312 | list_for_each_entry(bo_base, &vm->idle, vm_status) { | |
313 | struct amdgpu_bo *bo = bo_base->bo; | |
314 | ||
315 | if (!bo->parent) | |
316 | continue; | |
317 | ||
318 | ttm_bo_move_to_lru_tail(&bo->tbo); | |
319 | if (bo->shadow) | |
320 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo); | |
321 | } | |
322 | spin_unlock(&glob->lru_lock); | |
323 | ||
91ccdd24 | 324 | return r; |
670fecc8 CK |
325 | } |
326 | ||
56467ebf | 327 | /** |
34d7be5d | 328 | * amdgpu_vm_ready - check VM is ready for updates |
56467ebf | 329 | * |
34d7be5d | 330 | * @vm: VM to check |
d38ceaf9 | 331 | * |
34d7be5d | 332 | * Check if all VM PDs/PTs are ready for updates |
7fc48e59 AG |
333 | * |
334 | * Returns: | |
335 | * True if eviction list is empty. | |
d38ceaf9 | 336 | */ |
3f3333f8 | 337 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
d38ceaf9 | 338 | { |
af4c0f65 | 339 | return list_empty(&vm->evicted); |
d711e139 CK |
340 | } |
341 | ||
13307f7e CK |
342 | /** |
343 | * amdgpu_vm_clear_bo - initially clear the PDs/PTs | |
344 | * | |
345 | * @adev: amdgpu_device pointer | |
7fc48e59 | 346 | * @vm: VM to clear BO from |
13307f7e CK |
347 | * @bo: BO to clear |
348 | * @level: level this BO is at | |
349 | * | |
350 | * Root PD needs to be reserved when calling this. | |
7fc48e59 AG |
351 | * |
352 | * Returns: | |
353 | * 0 on success, errno otherwise. | |
13307f7e CK |
354 | */ |
355 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
4584312d CK |
356 | struct amdgpu_vm *vm, struct amdgpu_bo *bo, |
357 | unsigned level, bool pte_support_ats) | |
13307f7e CK |
358 | { |
359 | struct ttm_operation_ctx ctx = { true, false }; | |
360 | struct dma_fence *fence = NULL; | |
4584312d | 361 | unsigned entries, ats_entries; |
13307f7e CK |
362 | struct amdgpu_ring *ring; |
363 | struct amdgpu_job *job; | |
4584312d | 364 | uint64_t addr; |
13307f7e CK |
365 | int r; |
366 | ||
4584312d CK |
367 | addr = amdgpu_bo_gpu_offset(bo); |
368 | entries = amdgpu_bo_size(bo) / 8; | |
369 | ||
370 | if (pte_support_ats) { | |
371 | if (level == adev->vm_manager.root_level) { | |
372 | ats_entries = amdgpu_vm_level_shift(adev, level); | |
373 | ats_entries += AMDGPU_GPU_PAGE_SHIFT; | |
374 | ats_entries = AMDGPU_VA_HOLE_START >> ats_entries; | |
375 | ats_entries = min(ats_entries, entries); | |
376 | entries -= ats_entries; | |
377 | } else { | |
378 | ats_entries = entries; | |
379 | entries = 0; | |
380 | } | |
13307f7e | 381 | } else { |
4584312d | 382 | ats_entries = 0; |
13307f7e CK |
383 | } |
384 | ||
385 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); | |
386 | ||
387 | r = reservation_object_reserve_shared(bo->tbo.resv); | |
388 | if (r) | |
389 | return r; | |
390 | ||
391 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | |
392 | if (r) | |
393 | goto error; | |
394 | ||
13307f7e CK |
395 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
396 | if (r) | |
397 | goto error; | |
398 | ||
4584312d CK |
399 | if (ats_entries) { |
400 | uint64_t ats_value; | |
401 | ||
402 | ats_value = AMDGPU_PTE_DEFAULT_ATC; | |
403 | if (level != AMDGPU_VM_PTB) | |
404 | ats_value |= AMDGPU_PDE_PTE; | |
405 | ||
406 | amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, | |
407 | ats_entries, 0, ats_value); | |
408 | addr += ats_entries * 8; | |
409 | } | |
410 | ||
411 | if (entries) | |
412 | amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, | |
413 | entries, 0, 0); | |
414 | ||
13307f7e CK |
415 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
416 | ||
417 | WARN_ON(job->ibs[0].length_dw > 64); | |
29e8357b CK |
418 | r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv, |
419 | AMDGPU_FENCE_OWNER_UNDEFINED, false); | |
420 | if (r) | |
421 | goto error_free; | |
422 | ||
13307f7e CK |
423 | r = amdgpu_job_submit(job, ring, &vm->entity, |
424 | AMDGPU_FENCE_OWNER_UNDEFINED, &fence); | |
425 | if (r) | |
426 | goto error_free; | |
427 | ||
428 | amdgpu_bo_fence(bo, fence, true); | |
429 | dma_fence_put(fence); | |
e61736da CK |
430 | |
431 | if (bo->shadow) | |
432 | return amdgpu_vm_clear_bo(adev, vm, bo->shadow, | |
433 | level, pte_support_ats); | |
434 | ||
13307f7e CK |
435 | return 0; |
436 | ||
437 | error_free: | |
438 | amdgpu_job_free(job); | |
439 | ||
440 | error: | |
441 | return r; | |
442 | } | |
443 | ||
d711e139 | 444 | /** |
f566ceb1 CK |
445 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels |
446 | * | |
447 | * @adev: amdgpu_device pointer | |
448 | * @vm: requested vm | |
7fc48e59 | 449 | * @parent: parent PT |
f566ceb1 CK |
450 | * @saddr: start of the address range |
451 | * @eaddr: end of the address range | |
7fc48e59 AG |
452 | * @level: VMPT level |
453 | * @ats: indicate ATS support from PTE | |
f566ceb1 CK |
454 | * |
455 | * Make sure the page directories and page tables are allocated | |
7fc48e59 AG |
456 | * |
457 | * Returns: | |
458 | * 0 on success, errno otherwise. | |
f566ceb1 CK |
459 | */ |
460 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
461 | struct amdgpu_vm *vm, | |
462 | struct amdgpu_vm_pt *parent, | |
463 | uint64_t saddr, uint64_t eaddr, | |
4584312d | 464 | unsigned level, bool ats) |
f566ceb1 | 465 | { |
50783147 | 466 | unsigned shift = amdgpu_vm_level_shift(adev, level); |
f566ceb1 | 467 | unsigned pt_idx, from, to; |
3c824172 | 468 | u64 flags; |
13307f7e | 469 | int r; |
f566ceb1 CK |
470 | |
471 | if (!parent->entries) { | |
472 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
473 | ||
2098105e MH |
474 | parent->entries = kvmalloc_array(num_entries, |
475 | sizeof(struct amdgpu_vm_pt), | |
476 | GFP_KERNEL | __GFP_ZERO); | |
f566ceb1 CK |
477 | if (!parent->entries) |
478 | return -ENOMEM; | |
479 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
480 | } | |
481 | ||
1866bac8 FK |
482 | from = saddr >> shift; |
483 | to = eaddr >> shift; | |
484 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
485 | to >= amdgpu_vm_num_entries(adev, level)) | |
486 | return -EINVAL; | |
f566ceb1 | 487 | |
f566ceb1 | 488 | ++level; |
1866bac8 FK |
489 | saddr = saddr & ((1 << shift) - 1); |
490 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 | 491 | |
13307f7e | 492 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; |
3c824172 HK |
493 | if (vm->use_cpu_for_update) |
494 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
495 | else | |
496 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
497 | AMDGPU_GEM_CREATE_SHADOW); | |
498 | ||
f566ceb1 CK |
499 | /* walk over the address space and allocate the page tables */ |
500 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
3f3333f8 | 501 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
f566ceb1 CK |
502 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
503 | struct amdgpu_bo *pt; | |
504 | ||
3f3333f8 | 505 | if (!entry->base.bo) { |
3216c6b7 CZ |
506 | struct amdgpu_bo_param bp; |
507 | ||
508 | memset(&bp, 0, sizeof(bp)); | |
509 | bp.size = amdgpu_vm_bo_size(adev, level); | |
510 | bp.byte_align = AMDGPU_GPU_PAGE_SIZE; | |
511 | bp.domain = AMDGPU_GEM_DOMAIN_VRAM; | |
512 | bp.flags = flags; | |
513 | bp.type = ttm_bo_type_kernel; | |
514 | bp.resv = resv; | |
515 | r = amdgpu_bo_create(adev, &bp, &pt); | |
f566ceb1 CK |
516 | if (r) |
517 | return r; | |
518 | ||
4584312d | 519 | r = amdgpu_vm_clear_bo(adev, vm, pt, level, ats); |
13307f7e | 520 | if (r) { |
e5197a4c | 521 | amdgpu_bo_unref(&pt->shadow); |
13307f7e CK |
522 | amdgpu_bo_unref(&pt); |
523 | return r; | |
524 | } | |
525 | ||
0a096fb6 CK |
526 | if (vm->use_cpu_for_update) { |
527 | r = amdgpu_bo_kmap(pt, NULL); | |
528 | if (r) { | |
e5197a4c | 529 | amdgpu_bo_unref(&pt->shadow); |
0a096fb6 CK |
530 | amdgpu_bo_unref(&pt); |
531 | return r; | |
532 | } | |
533 | } | |
534 | ||
f566ceb1 CK |
535 | /* Keep a reference to the root directory to avoid |
536 | * freeing them up in the wrong order. | |
537 | */ | |
0f2fc435 | 538 | pt->parent = amdgpu_bo_ref(parent->base.bo); |
f566ceb1 | 539 | |
3f4299be | 540 | amdgpu_vm_bo_base_init(&entry->base, vm, pt); |
3f4299be | 541 | list_move(&entry->base.vm_status, &vm->relocated); |
f566ceb1 CK |
542 | } |
543 | ||
196f7489 | 544 | if (level < AMDGPU_VM_PTB) { |
1866bac8 FK |
545 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
546 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
547 | ((1 << shift) - 1); | |
548 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
4584312d | 549 | sub_eaddr, level, ats); |
f566ceb1 CK |
550 | if (r) |
551 | return r; | |
552 | } | |
553 | } | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
663e4577 CK |
558 | /** |
559 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
560 | * | |
561 | * @adev: amdgpu_device pointer | |
562 | * @vm: VM to allocate page tables for | |
563 | * @saddr: Start address which needs to be allocated | |
564 | * @size: Size from start address we need. | |
565 | * | |
566 | * Make sure the page tables are allocated. | |
7fc48e59 AG |
567 | * |
568 | * Returns: | |
569 | * 0 on success, errno otherwise. | |
663e4577 CK |
570 | */ |
571 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
572 | struct amdgpu_vm *vm, | |
573 | uint64_t saddr, uint64_t size) | |
574 | { | |
663e4577 | 575 | uint64_t eaddr; |
4584312d | 576 | bool ats = false; |
663e4577 CK |
577 | |
578 | /* validate the parameters */ | |
579 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
580 | return -EINVAL; | |
581 | ||
582 | eaddr = saddr + size - 1; | |
4584312d CK |
583 | |
584 | if (vm->pte_support_ats) | |
585 | ats = saddr < AMDGPU_VA_HOLE_START; | |
663e4577 CK |
586 | |
587 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
588 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
589 | ||
4584312d CK |
590 | if (eaddr >= adev->vm_manager.max_pfn) { |
591 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", | |
592 | eaddr, adev->vm_manager.max_pfn); | |
593 | return -EINVAL; | |
594 | } | |
595 | ||
196f7489 | 596 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, |
4584312d | 597 | adev->vm_manager.root_level, ats); |
663e4577 CK |
598 | } |
599 | ||
e59c0205 AX |
600 | /** |
601 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
602 | * | |
603 | * @adev: amdgpu_device pointer | |
604 | */ | |
605 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 606 | { |
a1255107 | 607 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
608 | bool has_compute_vm_bug; |
609 | struct amdgpu_ring *ring; | |
610 | int i; | |
93dcc37d | 611 | |
e59c0205 | 612 | has_compute_vm_bug = false; |
93dcc37d | 613 | |
2990a1fc | 614 | ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); |
e59c0205 AX |
615 | if (ip_block) { |
616 | /* Compute has a VM bug for GFX version < 7. | |
617 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
618 | if (ip_block->version->major <= 7) | |
619 | has_compute_vm_bug = true; | |
620 | else if (ip_block->version->major == 8) | |
621 | if (adev->gfx.mec_fw_version < 673) | |
622 | has_compute_vm_bug = true; | |
623 | } | |
93dcc37d | 624 | |
e59c0205 AX |
625 | for (i = 0; i < adev->num_rings; i++) { |
626 | ring = adev->rings[i]; | |
627 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
628 | /* only compute rings */ | |
629 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 630 | else |
e59c0205 | 631 | ring->has_compute_vm_bug = false; |
93dcc37d | 632 | } |
93dcc37d AD |
633 | } |
634 | ||
7fc48e59 AG |
635 | /** |
636 | * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job. | |
637 | * | |
638 | * @ring: ring on which the job will be submitted | |
639 | * @job: job to submit | |
640 | * | |
641 | * Returns: | |
642 | * True if sync is needed. | |
643 | */ | |
b9bf33d5 CZ |
644 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
645 | struct amdgpu_job *job) | |
e60f8db5 | 646 | { |
b9bf33d5 CZ |
647 | struct amdgpu_device *adev = ring->adev; |
648 | unsigned vmhub = ring->funcs->vmhub; | |
620f774f CK |
649 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
650 | struct amdgpu_vmid *id; | |
b9bf33d5 | 651 | bool gds_switch_needed; |
e59c0205 | 652 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 | 653 | |
c4f46f22 | 654 | if (job->vmid == 0) |
b9bf33d5 | 655 | return false; |
c4f46f22 | 656 | id = &id_mgr->ids[job->vmid]; |
b9bf33d5 CZ |
657 | gds_switch_needed = ring->funcs->emit_gds_switch && ( |
658 | id->gds_base != job->gds_base || | |
659 | id->gds_size != job->gds_size || | |
660 | id->gws_base != job->gws_base || | |
661 | id->gws_size != job->gws_size || | |
662 | id->oa_base != job->oa_base || | |
663 | id->oa_size != job->oa_size); | |
e60f8db5 | 664 | |
620f774f | 665 | if (amdgpu_vmid_had_gpu_reset(adev, id)) |
b9bf33d5 | 666 | return true; |
e60f8db5 | 667 | |
bb37b67d | 668 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
669 | } |
670 | ||
7fc48e59 AG |
671 | /** |
672 | * amdgpu_vm_is_large_bar - Check if BAR is large enough | |
673 | * | |
674 | * @adev: amdgpu_device pointer | |
675 | * | |
676 | * Returns: | |
677 | * True if BAR is large enough. | |
678 | */ | |
9a4b7d4c HK |
679 | static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) |
680 | { | |
770d13b1 | 681 | return (adev->gmc.real_vram_size == adev->gmc.visible_vram_size); |
e60f8db5 AX |
682 | } |
683 | ||
d38ceaf9 AD |
684 | /** |
685 | * amdgpu_vm_flush - hardware flush the vm | |
686 | * | |
687 | * @ring: ring to use for flush | |
7fc48e59 | 688 | * @need_pipe_sync: is pipe sync needed |
d38ceaf9 | 689 | * |
4ff37a83 | 690 | * Emit a VM flush when it is necessary. |
7fc48e59 AG |
691 | * |
692 | * Returns: | |
693 | * 0 on success, errno otherwise. | |
d38ceaf9 | 694 | */ |
8fdf074f | 695 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 696 | { |
971fe9a9 | 697 | struct amdgpu_device *adev = ring->adev; |
7645670d | 698 | unsigned vmhub = ring->funcs->vmhub; |
620f774f | 699 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
c4f46f22 | 700 | struct amdgpu_vmid *id = &id_mgr->ids[job->vmid]; |
d564a06e | 701 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
702 | id->gds_base != job->gds_base || |
703 | id->gds_size != job->gds_size || | |
704 | id->gws_base != job->gws_base || | |
705 | id->gws_size != job->gws_size || | |
706 | id->oa_base != job->oa_base || | |
707 | id->oa_size != job->oa_size); | |
de37e68a | 708 | bool vm_flush_needed = job->vm_needs_flush; |
b3cd285f CK |
709 | bool pasid_mapping_needed = id->pasid != job->pasid || |
710 | !id->pasid_mapping || | |
711 | !dma_fence_is_signaled(id->pasid_mapping); | |
712 | struct dma_fence *fence = NULL; | |
c0e51931 | 713 | unsigned patch_offset = 0; |
41d9eb2c | 714 | int r; |
d564a06e | 715 | |
620f774f | 716 | if (amdgpu_vmid_had_gpu_reset(adev, id)) { |
f7d015b9 CK |
717 | gds_switch_needed = true; |
718 | vm_flush_needed = true; | |
b3cd285f | 719 | pasid_mapping_needed = true; |
f7d015b9 | 720 | } |
971fe9a9 | 721 | |
b3cd285f CK |
722 | gds_switch_needed &= !!ring->funcs->emit_gds_switch; |
723 | vm_flush_needed &= !!ring->funcs->emit_vm_flush; | |
724 | pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping && | |
725 | ring->funcs->emit_wreg; | |
726 | ||
8fdf074f | 727 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 728 | return 0; |
41d9eb2c | 729 | |
c0e51931 CK |
730 | if (ring->funcs->init_cond_exec) |
731 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 732 | |
8fdf074f ML |
733 | if (need_pipe_sync) |
734 | amdgpu_ring_emit_pipeline_sync(ring); | |
735 | ||
b3cd285f | 736 | if (vm_flush_needed) { |
c4f46f22 | 737 | trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr); |
c633c00b | 738 | amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr); |
b3cd285f CK |
739 | } |
740 | ||
741 | if (pasid_mapping_needed) | |
742 | amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); | |
e9d672b2 | 743 | |
b3cd285f | 744 | if (vm_flush_needed || pasid_mapping_needed) { |
d240cd9e | 745 | r = amdgpu_fence_emit(ring, &fence, 0); |
c0e51931 CK |
746 | if (r) |
747 | return r; | |
b3cd285f | 748 | } |
e9d672b2 | 749 | |
b3cd285f | 750 | if (vm_flush_needed) { |
7645670d | 751 | mutex_lock(&id_mgr->lock); |
c0e51931 | 752 | dma_fence_put(id->last_flush); |
b3cd285f CK |
753 | id->last_flush = dma_fence_get(fence); |
754 | id->current_gpu_reset_count = | |
755 | atomic_read(&adev->gpu_reset_counter); | |
7645670d | 756 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 757 | } |
e9d672b2 | 758 | |
b3cd285f CK |
759 | if (pasid_mapping_needed) { |
760 | id->pasid = job->pasid; | |
761 | dma_fence_put(id->pasid_mapping); | |
762 | id->pasid_mapping = dma_fence_get(fence); | |
763 | } | |
764 | dma_fence_put(fence); | |
765 | ||
7c4378f4 | 766 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
767 | id->gds_base = job->gds_base; |
768 | id->gds_size = job->gds_size; | |
769 | id->gws_base = job->gws_base; | |
770 | id->gws_size = job->gws_size; | |
771 | id->oa_base = job->oa_base; | |
772 | id->oa_size = job->oa_size; | |
c4f46f22 | 773 | amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base, |
c0e51931 CK |
774 | job->gds_size, job->gws_base, |
775 | job->gws_size, job->oa_base, | |
776 | job->oa_size); | |
777 | } | |
778 | ||
779 | if (ring->funcs->patch_cond_exec) | |
780 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
781 | ||
782 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
783 | if (ring->funcs->emit_switch_buffer) { | |
784 | amdgpu_ring_emit_switch_buffer(ring); | |
785 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 786 | } |
41d9eb2c | 787 | return 0; |
971fe9a9 CK |
788 | } |
789 | ||
d38ceaf9 AD |
790 | /** |
791 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
792 | * | |
793 | * @vm: requested vm | |
794 | * @bo: requested buffer object | |
795 | * | |
8843dbbb | 796 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
797 | * Search inside the @bos vm list for the requested vm |
798 | * Returns the found bo_va or NULL if none is found | |
799 | * | |
800 | * Object has to be reserved! | |
7fc48e59 AG |
801 | * |
802 | * Returns: | |
803 | * Found bo_va or NULL. | |
d38ceaf9 AD |
804 | */ |
805 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
806 | struct amdgpu_bo *bo) | |
807 | { | |
808 | struct amdgpu_bo_va *bo_va; | |
809 | ||
ec681545 CK |
810 | list_for_each_entry(bo_va, &bo->va, base.bo_list) { |
811 | if (bo_va->base.vm == vm) { | |
d38ceaf9 AD |
812 | return bo_va; |
813 | } | |
814 | } | |
815 | return NULL; | |
816 | } | |
817 | ||
818 | /** | |
afef8b8f | 819 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 820 | * |
29efc4f5 | 821 | * @params: see amdgpu_pte_update_params definition |
373ac645 | 822 | * @bo: PD/PT to update |
d38ceaf9 AD |
823 | * @pe: addr of the page entry |
824 | * @addr: dst addr to write into pe | |
825 | * @count: number of page entries to update | |
826 | * @incr: increase next addr by incr bytes | |
827 | * @flags: hw access flags | |
d38ceaf9 AD |
828 | * |
829 | * Traces the parameters and calls the right asic functions | |
830 | * to setup the page table using the DMA. | |
831 | */ | |
afef8b8f | 832 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
373ac645 | 833 | struct amdgpu_bo *bo, |
afef8b8f CK |
834 | uint64_t pe, uint64_t addr, |
835 | unsigned count, uint32_t incr, | |
6b777607 | 836 | uint64_t flags) |
d38ceaf9 | 837 | { |
373ac645 | 838 | pe += amdgpu_bo_gpu_offset(bo); |
ec2f05f0 | 839 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 840 | |
afef8b8f | 841 | if (count < 3) { |
de9ea7bd CK |
842 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
843 | addr | flags, count, incr); | |
d38ceaf9 AD |
844 | |
845 | } else { | |
27c5f36f | 846 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
847 | count, incr, flags); |
848 | } | |
849 | } | |
850 | ||
afef8b8f CK |
851 | /** |
852 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
853 | * | |
854 | * @params: see amdgpu_pte_update_params definition | |
373ac645 | 855 | * @bo: PD/PT to update |
afef8b8f CK |
856 | * @pe: addr of the page entry |
857 | * @addr: dst addr to write into pe | |
858 | * @count: number of page entries to update | |
859 | * @incr: increase next addr by incr bytes | |
860 | * @flags: hw access flags | |
861 | * | |
862 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
863 | */ | |
864 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
373ac645 | 865 | struct amdgpu_bo *bo, |
afef8b8f CK |
866 | uint64_t pe, uint64_t addr, |
867 | unsigned count, uint32_t incr, | |
6b777607 | 868 | uint64_t flags) |
afef8b8f | 869 | { |
ec2f05f0 | 870 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 871 | |
373ac645 | 872 | pe += amdgpu_bo_gpu_offset(bo); |
ec2f05f0 CK |
873 | trace_amdgpu_vm_copy_ptes(pe, src, count); |
874 | ||
875 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
876 | } |
877 | ||
d38ceaf9 | 878 | /** |
b07c9d2a | 879 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 880 | * |
b07c9d2a | 881 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
882 | * @addr: the unmapped addr |
883 | * | |
884 | * Look up the physical address of the page that the pte resolves | |
7fc48e59 AG |
885 | * to. |
886 | * | |
887 | * Returns: | |
888 | * The pointer for the page table entry. | |
d38ceaf9 | 889 | */ |
de9ea7bd | 890 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
891 | { |
892 | uint64_t result; | |
893 | ||
de9ea7bd CK |
894 | /* page table offset */ |
895 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 896 | |
de9ea7bd CK |
897 | /* in case cpu page size != gpu page size*/ |
898 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 899 | |
b07c9d2a | 900 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
901 | |
902 | return result; | |
903 | } | |
904 | ||
3c824172 HK |
905 | /** |
906 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU | |
907 | * | |
908 | * @params: see amdgpu_pte_update_params definition | |
373ac645 | 909 | * @bo: PD/PT to update |
3c824172 HK |
910 | * @pe: kmap addr of the page entry |
911 | * @addr: dst addr to write into pe | |
912 | * @count: number of page entries to update | |
913 | * @incr: increase next addr by incr bytes | |
914 | * @flags: hw access flags | |
915 | * | |
916 | * Write count number of PT/PD entries directly. | |
917 | */ | |
918 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, | |
373ac645 | 919 | struct amdgpu_bo *bo, |
3c824172 HK |
920 | uint64_t pe, uint64_t addr, |
921 | unsigned count, uint32_t incr, | |
922 | uint64_t flags) | |
923 | { | |
924 | unsigned int i; | |
b4d42511 | 925 | uint64_t value; |
3c824172 | 926 | |
373ac645 CK |
927 | pe += (unsigned long)amdgpu_bo_kptr(bo); |
928 | ||
03918b36 CK |
929 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
930 | ||
3c824172 | 931 | for (i = 0; i < count; i++) { |
b4d42511 HK |
932 | value = params->pages_addr ? |
933 | amdgpu_vm_map_gart(params->pages_addr, addr) : | |
934 | addr; | |
132f34e4 CK |
935 | amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe, |
936 | i, value, flags); | |
3c824172 HK |
937 | addr += incr; |
938 | } | |
3c824172 HK |
939 | } |
940 | ||
7fc48e59 AG |
941 | |
942 | /** | |
943 | * amdgpu_vm_wait_pd - Wait for PT BOs to be free. | |
944 | * | |
945 | * @adev: amdgpu_device pointer | |
946 | * @vm: related vm | |
947 | * @owner: fence owner | |
948 | * | |
949 | * Returns: | |
950 | * 0 on success, errno otherwise. | |
951 | */ | |
a33cab7a CK |
952 | static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
953 | void *owner) | |
3c824172 HK |
954 | { |
955 | struct amdgpu_sync sync; | |
956 | int r; | |
957 | ||
958 | amdgpu_sync_create(&sync); | |
177ae09b | 959 | amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false); |
3c824172 HK |
960 | r = amdgpu_sync_wait(&sync, true); |
961 | amdgpu_sync_free(&sync); | |
962 | ||
963 | return r; | |
964 | } | |
965 | ||
f8991bab | 966 | /* |
6989f246 | 967 | * amdgpu_vm_update_pde - update a single level in the hierarchy |
f8991bab | 968 | * |
6989f246 | 969 | * @param: parameters for the update |
f8991bab | 970 | * @vm: requested vm |
194d2161 | 971 | * @parent: parent directory |
6989f246 | 972 | * @entry: entry to update |
f8991bab | 973 | * |
6989f246 | 974 | * Makes sure the requested entry in parent is up to date. |
f8991bab | 975 | */ |
6989f246 CK |
976 | static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, |
977 | struct amdgpu_vm *vm, | |
978 | struct amdgpu_vm_pt *parent, | |
979 | struct amdgpu_vm_pt *entry) | |
d38ceaf9 | 980 | { |
373ac645 | 981 | struct amdgpu_bo *bo = parent->base.bo, *pbo; |
3de676d8 CK |
982 | uint64_t pde, pt, flags; |
983 | unsigned level; | |
d5fc5e82 | 984 | |
6989f246 CK |
985 | /* Don't update huge pages here */ |
986 | if (entry->huge) | |
987 | return; | |
d38ceaf9 | 988 | |
373ac645 | 989 | for (level = 0, pbo = bo->parent; pbo; ++level) |
3de676d8 CK |
990 | pbo = pbo->parent; |
991 | ||
196f7489 | 992 | level += params->adev->vm_manager.root_level; |
373ac645 | 993 | pt = amdgpu_bo_gpu_offset(entry->base.bo); |
3de676d8 | 994 | flags = AMDGPU_PTE_VALID; |
132f34e4 | 995 | amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags); |
373ac645 CK |
996 | pde = (entry - parent->entries) * 8; |
997 | if (bo->shadow) | |
998 | params->func(params, bo->shadow, pde, pt, 1, 0, flags); | |
999 | params->func(params, bo, pde, pt, 1, 0, flags); | |
d38ceaf9 AD |
1000 | } |
1001 | ||
92456b93 CK |
1002 | /* |
1003 | * amdgpu_vm_invalidate_level - mark all PD levels as invalid | |
1004 | * | |
7fc48e59 AG |
1005 | * @adev: amdgpu_device pointer |
1006 | * @vm: related vm | |
92456b93 | 1007 | * @parent: parent PD |
7fc48e59 | 1008 | * @level: VMPT level |
92456b93 CK |
1009 | * |
1010 | * Mark all PD level as invalid after an error. | |
1011 | */ | |
8f19cd78 CK |
1012 | static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev, |
1013 | struct amdgpu_vm *vm, | |
1014 | struct amdgpu_vm_pt *parent, | |
1015 | unsigned level) | |
92456b93 | 1016 | { |
8f19cd78 | 1017 | unsigned pt_idx, num_entries; |
92456b93 CK |
1018 | |
1019 | /* | |
1020 | * Recurse into the subdirectories. This recursion is harmless because | |
1021 | * we only have a maximum of 5 layers. | |
1022 | */ | |
8f19cd78 CK |
1023 | num_entries = amdgpu_vm_num_entries(adev, level); |
1024 | for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) { | |
92456b93 CK |
1025 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
1026 | ||
3f3333f8 | 1027 | if (!entry->base.bo) |
92456b93 CK |
1028 | continue; |
1029 | ||
862b8c57 CK |
1030 | if (!entry->base.moved) |
1031 | list_move(&entry->base.vm_status, &vm->relocated); | |
8f19cd78 | 1032 | amdgpu_vm_invalidate_level(adev, vm, entry, level + 1); |
92456b93 CK |
1033 | } |
1034 | } | |
1035 | ||
194d2161 CK |
1036 | /* |
1037 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1038 | * | |
1039 | * @adev: amdgpu_device pointer | |
1040 | * @vm: requested vm | |
1041 | * | |
1042 | * Makes sure all directories are up to date. | |
7fc48e59 AG |
1043 | * |
1044 | * Returns: | |
1045 | * 0 for success, error for failure. | |
194d2161 CK |
1046 | */ |
1047 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1048 | struct amdgpu_vm *vm) | |
1049 | { | |
6989f246 CK |
1050 | struct amdgpu_pte_update_params params; |
1051 | struct amdgpu_job *job; | |
1052 | unsigned ndw = 0; | |
78aa02c7 | 1053 | int r = 0; |
92456b93 | 1054 | |
6989f246 CK |
1055 | if (list_empty(&vm->relocated)) |
1056 | return 0; | |
1057 | ||
1058 | restart: | |
1059 | memset(¶ms, 0, sizeof(params)); | |
1060 | params.adev = adev; | |
1061 | ||
1062 | if (vm->use_cpu_for_update) { | |
a7f91061 CK |
1063 | struct amdgpu_vm_bo_base *bo_base; |
1064 | ||
1065 | list_for_each_entry(bo_base, &vm->relocated, vm_status) { | |
1066 | r = amdgpu_bo_kmap(bo_base->bo, NULL); | |
1067 | if (unlikely(r)) | |
1068 | return r; | |
1069 | } | |
1070 | ||
6989f246 CK |
1071 | r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); |
1072 | if (unlikely(r)) | |
1073 | return r; | |
1074 | ||
1075 | params.func = amdgpu_vm_cpu_set_ptes; | |
1076 | } else { | |
1077 | ndw = 512 * 8; | |
1078 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
1079 | if (r) | |
1080 | return r; | |
1081 | ||
1082 | params.ib = &job->ibs[0]; | |
1083 | params.func = amdgpu_vm_do_set_ptes; | |
1084 | } | |
1085 | ||
ea09729c | 1086 | while (!list_empty(&vm->relocated)) { |
6989f246 CK |
1087 | struct amdgpu_vm_bo_base *bo_base, *parent; |
1088 | struct amdgpu_vm_pt *pt, *entry; | |
ea09729c CK |
1089 | struct amdgpu_bo *bo; |
1090 | ||
1091 | bo_base = list_first_entry(&vm->relocated, | |
1092 | struct amdgpu_vm_bo_base, | |
1093 | vm_status); | |
862b8c57 | 1094 | bo_base->moved = false; |
806f043f | 1095 | list_move(&bo_base->vm_status, &vm->idle); |
ea09729c CK |
1096 | |
1097 | bo = bo_base->bo->parent; | |
af4c0f65 | 1098 | if (!bo) |
6989f246 | 1099 | continue; |
6989f246 CK |
1100 | |
1101 | parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base, | |
1102 | bo_list); | |
1103 | pt = container_of(parent, struct amdgpu_vm_pt, base); | |
1104 | entry = container_of(bo_base, struct amdgpu_vm_pt, base); | |
1105 | ||
1106 | amdgpu_vm_update_pde(¶ms, vm, pt, entry); | |
1107 | ||
6989f246 CK |
1108 | if (!vm->use_cpu_for_update && |
1109 | (ndw - params.ib->length_dw) < 32) | |
1110 | break; | |
ea09729c | 1111 | } |
92456b93 | 1112 | |
68c62306 CK |
1113 | if (vm->use_cpu_for_update) { |
1114 | /* Flush HDP */ | |
1115 | mb(); | |
69882565 | 1116 | amdgpu_asic_flush_hdp(adev, NULL); |
6989f246 CK |
1117 | } else if (params.ib->length_dw == 0) { |
1118 | amdgpu_job_free(job); | |
1119 | } else { | |
1120 | struct amdgpu_bo *root = vm->root.base.bo; | |
1121 | struct amdgpu_ring *ring; | |
1122 | struct dma_fence *fence; | |
1123 | ||
1124 | ring = container_of(vm->entity.sched, struct amdgpu_ring, | |
1125 | sched); | |
1126 | ||
1127 | amdgpu_ring_pad_ib(ring, params.ib); | |
1128 | amdgpu_sync_resv(adev, &job->sync, root->tbo.resv, | |
1129 | AMDGPU_FENCE_OWNER_VM, false); | |
6989f246 CK |
1130 | WARN_ON(params.ib->length_dw > ndw); |
1131 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
1132 | AMDGPU_FENCE_OWNER_VM, &fence); | |
1133 | if (r) | |
1134 | goto error; | |
1135 | ||
1136 | amdgpu_bo_fence(root, fence, true); | |
1137 | dma_fence_put(vm->last_update); | |
1138 | vm->last_update = fence; | |
68c62306 CK |
1139 | } |
1140 | ||
6989f246 CK |
1141 | if (!list_empty(&vm->relocated)) |
1142 | goto restart; | |
1143 | ||
1144 | return 0; | |
1145 | ||
1146 | error: | |
196f7489 CZ |
1147 | amdgpu_vm_invalidate_level(adev, vm, &vm->root, |
1148 | adev->vm_manager.root_level); | |
6989f246 | 1149 | amdgpu_job_free(job); |
92456b93 | 1150 | return r; |
194d2161 CK |
1151 | } |
1152 | ||
4e2cb640 | 1153 | /** |
cf2f0a37 | 1154 | * amdgpu_vm_find_entry - find the entry for an address |
4e2cb640 CK |
1155 | * |
1156 | * @p: see amdgpu_pte_update_params definition | |
1157 | * @addr: virtual address in question | |
cf2f0a37 AD |
1158 | * @entry: resulting entry or NULL |
1159 | * @parent: parent entry | |
4e2cb640 | 1160 | * |
cf2f0a37 | 1161 | * Find the vm_pt entry and it's parent for the given address. |
4e2cb640 | 1162 | */ |
cf2f0a37 AD |
1163 | void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, |
1164 | struct amdgpu_vm_pt **entry, | |
1165 | struct amdgpu_vm_pt **parent) | |
4e2cb640 | 1166 | { |
196f7489 | 1167 | unsigned level = p->adev->vm_manager.root_level; |
4e2cb640 | 1168 | |
cf2f0a37 AD |
1169 | *parent = NULL; |
1170 | *entry = &p->vm->root; | |
1171 | while ((*entry)->entries) { | |
e3a1b32a | 1172 | unsigned shift = amdgpu_vm_level_shift(p->adev, level++); |
50783147 | 1173 | |
cf2f0a37 | 1174 | *parent = *entry; |
e3a1b32a CK |
1175 | *entry = &(*entry)->entries[addr >> shift]; |
1176 | addr &= (1ULL << shift) - 1; | |
4e2cb640 CK |
1177 | } |
1178 | ||
196f7489 | 1179 | if (level != AMDGPU_VM_PTB) |
cf2f0a37 AD |
1180 | *entry = NULL; |
1181 | } | |
1182 | ||
1183 | /** | |
1184 | * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages | |
1185 | * | |
1186 | * @p: see amdgpu_pte_update_params definition | |
1187 | * @entry: vm_pt entry to check | |
1188 | * @parent: parent entry | |
1189 | * @nptes: number of PTEs updated with this operation | |
1190 | * @dst: destination address where the PTEs should point to | |
1191 | * @flags: access flags fro the PTEs | |
1192 | * | |
1193 | * Check if we can update the PD with a huge page. | |
1194 | */ | |
ec5207c9 CK |
1195 | static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, |
1196 | struct amdgpu_vm_pt *entry, | |
1197 | struct amdgpu_vm_pt *parent, | |
1198 | unsigned nptes, uint64_t dst, | |
1199 | uint64_t flags) | |
cf2f0a37 | 1200 | { |
373ac645 | 1201 | uint64_t pde; |
cf2f0a37 AD |
1202 | |
1203 | /* In the case of a mixed PT the PDE must point to it*/ | |
3cc1d3ea CK |
1204 | if (p->adev->asic_type >= CHIP_VEGA10 && !p->src && |
1205 | nptes == AMDGPU_VM_PTE_COUNT(p->adev)) { | |
4ab4016a | 1206 | /* Set the huge page flag to stop scanning at this PDE */ |
cf2f0a37 AD |
1207 | flags |= AMDGPU_PDE_PTE; |
1208 | } | |
1209 | ||
3cc1d3ea CK |
1210 | if (!(flags & AMDGPU_PDE_PTE)) { |
1211 | if (entry->huge) { | |
1212 | /* Add the entry to the relocated list to update it. */ | |
1213 | entry->huge = false; | |
3cc1d3ea | 1214 | list_move(&entry->base.vm_status, &p->vm->relocated); |
3cc1d3ea | 1215 | } |
ec5207c9 | 1216 | return; |
3cc1d3ea | 1217 | } |
cf2f0a37 | 1218 | |
3cc1d3ea | 1219 | entry->huge = true; |
132f34e4 | 1220 | amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags); |
3de676d8 | 1221 | |
373ac645 CK |
1222 | pde = (entry - parent->entries) * 8; |
1223 | if (parent->base.bo->shadow) | |
1224 | p->func(p, parent->base.bo->shadow, pde, dst, 1, 0, flags); | |
1225 | p->func(p, parent->base.bo, pde, dst, 1, 0, flags); | |
4e2cb640 CK |
1226 | } |
1227 | ||
d38ceaf9 AD |
1228 | /** |
1229 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1230 | * | |
29efc4f5 | 1231 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1232 | * @start: start of GPU address range |
1233 | * @end: end of GPU address range | |
677131a1 | 1234 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1235 | * @flags: mapping flags |
1236 | * | |
8843dbbb | 1237 | * Update the page tables in the range @start - @end. |
7fc48e59 AG |
1238 | * |
1239 | * Returns: | |
1240 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 | 1241 | */ |
cc28c4ed | 1242 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1243 | uint64_t start, uint64_t end, |
6b777607 | 1244 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1245 | { |
36b32a68 ZJ |
1246 | struct amdgpu_device *adev = params->adev; |
1247 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1248 | |
301654a4 | 1249 | uint64_t addr, pe_start; |
21718497 | 1250 | struct amdgpu_bo *pt; |
301654a4 | 1251 | unsigned nptes; |
d38ceaf9 AD |
1252 | |
1253 | /* walk over the address space and update the page tables */ | |
cf2f0a37 AD |
1254 | for (addr = start; addr < end; addr += nptes, |
1255 | dst += nptes * AMDGPU_GPU_PAGE_SIZE) { | |
1256 | struct amdgpu_vm_pt *entry, *parent; | |
1257 | ||
1258 | amdgpu_vm_get_entry(params, addr, &entry, &parent); | |
1259 | if (!entry) | |
1260 | return -ENOENT; | |
4e2cb640 | 1261 | |
d38ceaf9 AD |
1262 | if ((addr & ~mask) == (end & ~mask)) |
1263 | nptes = end - addr; | |
1264 | else | |
36b32a68 | 1265 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1266 | |
ec5207c9 CK |
1267 | amdgpu_vm_handle_huge_pages(params, entry, parent, |
1268 | nptes, dst, flags); | |
4ab4016a | 1269 | /* We don't need to update PTEs for huge pages */ |
78eb2f0c | 1270 | if (entry->huge) |
cf2f0a37 AD |
1271 | continue; |
1272 | ||
3f3333f8 | 1273 | pt = entry->base.bo; |
373ac645 CK |
1274 | pe_start = (addr & mask) * 8; |
1275 | if (pt->shadow) | |
1276 | params->func(params, pt->shadow, pe_start, dst, nptes, | |
1277 | AMDGPU_GPU_PAGE_SIZE, flags); | |
1278 | params->func(params, pt, pe_start, dst, nptes, | |
301654a4 | 1279 | AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
1280 | } |
1281 | ||
cc28c4ed | 1282 | return 0; |
92696dd5 CK |
1283 | } |
1284 | ||
1285 | /* | |
1286 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1287 | * | |
1288 | * @params: see amdgpu_pte_update_params definition | |
1289 | * @vm: requested vm | |
1290 | * @start: first PTE to handle | |
1291 | * @end: last PTE to handle | |
1292 | * @dst: addr those PTEs should point to | |
1293 | * @flags: hw mapping flags | |
7fc48e59 AG |
1294 | * |
1295 | * Returns: | |
1296 | * 0 for success, -EINVAL for failure. | |
92696dd5 | 1297 | */ |
cc28c4ed | 1298 | static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, |
92696dd5 | 1299 | uint64_t start, uint64_t end, |
6b777607 | 1300 | uint64_t dst, uint64_t flags) |
92696dd5 CK |
1301 | { |
1302 | /** | |
1303 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1304 | * field in the PTE. When this field is set to a non-zero value, page | |
1305 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1306 | * flags are considered valid for all PTEs within the fragment range | |
1307 | * and corresponding mappings are assumed to be physically contiguous. | |
1308 | * | |
1309 | * The L1 TLB can store a single PTE for the whole fragment, | |
1310 | * significantly increasing the space available for translation | |
1311 | * caching. This leads to large improvements in throughput when the | |
1312 | * TLB is under pressure. | |
1313 | * | |
1314 | * The L2 TLB distributes small and large fragments into two | |
1315 | * asymmetric partitions. The large fragment cache is significantly | |
1316 | * larger. Thus, we try to use large fragments wherever possible. | |
1317 | * Userspace can support this by aligning virtual base address and | |
1318 | * allocation size to the fragment size. | |
1319 | */ | |
6849d47c RH |
1320 | unsigned max_frag = params->adev->vm_manager.fragment_size; |
1321 | int r; | |
92696dd5 CK |
1322 | |
1323 | /* system pages are non continuously */ | |
6849d47c | 1324 | if (params->src || !(flags & AMDGPU_PTE_VALID)) |
cc28c4ed | 1325 | return amdgpu_vm_update_ptes(params, start, end, dst, flags); |
92696dd5 | 1326 | |
6849d47c RH |
1327 | while (start != end) { |
1328 | uint64_t frag_flags, frag_end; | |
1329 | unsigned frag; | |
1330 | ||
1331 | /* This intentionally wraps around if no bit is set */ | |
1332 | frag = min((unsigned)ffs(start) - 1, | |
1333 | (unsigned)fls64(end - start) - 1); | |
1334 | if (frag >= max_frag) { | |
1335 | frag_flags = AMDGPU_PTE_FRAG(max_frag); | |
1336 | frag_end = end & ~((1ULL << max_frag) - 1); | |
1337 | } else { | |
1338 | frag_flags = AMDGPU_PTE_FRAG(frag); | |
1339 | frag_end = start + (1 << frag); | |
1340 | } | |
1341 | ||
1342 | r = amdgpu_vm_update_ptes(params, start, frag_end, dst, | |
1343 | flags | frag_flags); | |
cc28c4ed HK |
1344 | if (r) |
1345 | return r; | |
92696dd5 | 1346 | |
6849d47c RH |
1347 | dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE; |
1348 | start = frag_end; | |
92696dd5 | 1349 | } |
6849d47c RH |
1350 | |
1351 | return 0; | |
d38ceaf9 AD |
1352 | } |
1353 | ||
d38ceaf9 AD |
1354 | /** |
1355 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1356 | * | |
1357 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1358 | * @exclusive: fence we need to sync to |
fa3ab3c7 | 1359 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 | 1360 | * @vm: requested vm |
a14faa65 CK |
1361 | * @start: start of mapped range |
1362 | * @last: last mapped entry | |
1363 | * @flags: flags for the entries | |
d38ceaf9 | 1364 | * @addr: addr to set the area to |
d38ceaf9 AD |
1365 | * @fence: optional resulting fence |
1366 | * | |
a14faa65 | 1367 | * Fill in the page table entries between @start and @last. |
7fc48e59 AG |
1368 | * |
1369 | * Returns: | |
1370 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1371 | */ |
1372 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1373 | struct dma_fence *exclusive, |
fa3ab3c7 | 1374 | dma_addr_t *pages_addr, |
d38ceaf9 | 1375 | struct amdgpu_vm *vm, |
a14faa65 | 1376 | uint64_t start, uint64_t last, |
6b777607 | 1377 | uint64_t flags, uint64_t addr, |
f54d1867 | 1378 | struct dma_fence **fence) |
d38ceaf9 | 1379 | { |
2d55e45a | 1380 | struct amdgpu_ring *ring; |
a1e08d3b | 1381 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1382 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1383 | struct amdgpu_job *job; |
29efc4f5 | 1384 | struct amdgpu_pte_update_params params; |
f54d1867 | 1385 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1386 | int r; |
1387 | ||
afef8b8f CK |
1388 | memset(¶ms, 0, sizeof(params)); |
1389 | params.adev = adev; | |
49ac8a24 | 1390 | params.vm = vm; |
afef8b8f | 1391 | |
a33cab7a CK |
1392 | /* sync to everything on unmapping */ |
1393 | if (!(flags & AMDGPU_PTE_VALID)) | |
1394 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1395 | ||
b4d42511 HK |
1396 | if (vm->use_cpu_for_update) { |
1397 | /* params.src is used as flag to indicate system Memory */ | |
1398 | if (pages_addr) | |
1399 | params.src = ~0; | |
1400 | ||
1401 | /* Wait for PT BOs to be free. PTs share the same resv. object | |
1402 | * as the root PD BO | |
1403 | */ | |
a33cab7a | 1404 | r = amdgpu_vm_wait_pd(adev, vm, owner); |
b4d42511 HK |
1405 | if (unlikely(r)) |
1406 | return r; | |
1407 | ||
1408 | params.func = amdgpu_vm_cpu_set_ptes; | |
1409 | params.pages_addr = pages_addr; | |
b4d42511 HK |
1410 | return amdgpu_vm_frag_ptes(¶ms, start, last + 1, |
1411 | addr, flags); | |
1412 | } | |
1413 | ||
2d55e45a | 1414 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 1415 | |
a14faa65 | 1416 | nptes = last - start + 1; |
d38ceaf9 AD |
1417 | |
1418 | /* | |
86209523 | 1419 | * reserve space for two commands every (1 << BLOCK_SIZE) |
d38ceaf9 | 1420 | * entries or 2k dwords (whatever is smaller) |
86209523 BN |
1421 | * |
1422 | * The second command is for the shadow pagetables. | |
d38ceaf9 | 1423 | */ |
104bd2ca ED |
1424 | if (vm->root.base.bo->shadow) |
1425 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2; | |
1426 | else | |
1427 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1); | |
d38ceaf9 AD |
1428 | |
1429 | /* padding, etc. */ | |
1430 | ndw = 64; | |
1431 | ||
570144c6 | 1432 | if (pages_addr) { |
b0456f93 | 1433 | /* copy commands needed */ |
e6d92197 | 1434 | ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; |
d38ceaf9 | 1435 | |
b0456f93 | 1436 | /* and also PTEs */ |
d38ceaf9 AD |
1437 | ndw += nptes * 2; |
1438 | ||
afef8b8f CK |
1439 | params.func = amdgpu_vm_do_copy_ptes; |
1440 | ||
d38ceaf9 AD |
1441 | } else { |
1442 | /* set page commands needed */ | |
44e1baeb | 1443 | ndw += ncmds * 10; |
d38ceaf9 | 1444 | |
6849d47c | 1445 | /* extra commands for begin/end fragments */ |
11528640 ED |
1446 | if (vm->root.base.bo->shadow) |
1447 | ndw += 2 * 10 * adev->vm_manager.fragment_size * 2; | |
1448 | else | |
1449 | ndw += 2 * 10 * adev->vm_manager.fragment_size; | |
afef8b8f CK |
1450 | |
1451 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1452 | } |
1453 | ||
d71518b5 CK |
1454 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1455 | if (r) | |
d38ceaf9 | 1456 | return r; |
d71518b5 | 1457 | |
29efc4f5 | 1458 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1459 | |
570144c6 | 1460 | if (pages_addr) { |
b0456f93 CK |
1461 | uint64_t *pte; |
1462 | unsigned i; | |
1463 | ||
1464 | /* Put the PTEs at the end of the IB. */ | |
1465 | i = ndw - nptes * 2; | |
1466 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1467 | params.src = job->ibs->gpu_addr + i * 4; | |
1468 | ||
1469 | for (i = 0; i < nptes; ++i) { | |
1470 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1471 | AMDGPU_GPU_PAGE_SIZE); | |
1472 | pte[i] |= flags; | |
1473 | } | |
d7a4ac66 | 1474 | addr = 0; |
b0456f93 CK |
1475 | } |
1476 | ||
cebb52b7 | 1477 | r = amdgpu_sync_fence(adev, &job->sync, exclusive, false); |
3cabaa54 CK |
1478 | if (r) |
1479 | goto error_free; | |
1480 | ||
3f3333f8 | 1481 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, |
177ae09b | 1482 | owner, false); |
a1e08d3b CK |
1483 | if (r) |
1484 | goto error_free; | |
d38ceaf9 | 1485 | |
3f3333f8 | 1486 | r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv); |
a1e08d3b CK |
1487 | if (r) |
1488 | goto error_free; | |
1489 | ||
cc28c4ed HK |
1490 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
1491 | if (r) | |
1492 | goto error_free; | |
d38ceaf9 | 1493 | |
29efc4f5 CK |
1494 | amdgpu_ring_pad_ib(ring, params.ib); |
1495 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1496 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1497 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1498 | if (r) |
1499 | goto error_free; | |
d38ceaf9 | 1500 | |
3f3333f8 | 1501 | amdgpu_bo_fence(vm->root.base.bo, f, true); |
284710fa CK |
1502 | dma_fence_put(*fence); |
1503 | *fence = f; | |
d38ceaf9 | 1504 | return 0; |
d5fc5e82 CZ |
1505 | |
1506 | error_free: | |
d71518b5 | 1507 | amdgpu_job_free(job); |
4af9f07c | 1508 | return r; |
d38ceaf9 AD |
1509 | } |
1510 | ||
a14faa65 CK |
1511 | /** |
1512 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1513 | * | |
1514 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1515 | * @exclusive: fence we need to sync to |
8358dcee | 1516 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1517 | * @vm: requested vm |
1518 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1519 | * @flags: HW flags for the mapping |
63e0ba40 | 1520 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1521 | * @fence: optional resulting fence |
1522 | * | |
1523 | * Split the mapping into smaller chunks so that each update fits | |
1524 | * into a SDMA IB. | |
7fc48e59 AG |
1525 | * |
1526 | * Returns: | |
1527 | * 0 for success, -EINVAL for failure. | |
a14faa65 CK |
1528 | */ |
1529 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1530 | struct dma_fence *exclusive, |
8358dcee | 1531 | dma_addr_t *pages_addr, |
a14faa65 CK |
1532 | struct amdgpu_vm *vm, |
1533 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1534 | uint64_t flags, |
63e0ba40 | 1535 | struct drm_mm_node *nodes, |
f54d1867 | 1536 | struct dma_fence **fence) |
a14faa65 | 1537 | { |
9fc8fc70 | 1538 | unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; |
570144c6 | 1539 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1540 | int r; |
1541 | ||
1542 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1543 | * but in case of something, we filter the flags in first place | |
1544 | */ | |
1545 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1546 | flags &= ~AMDGPU_PTE_READABLE; | |
1547 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1548 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1549 | ||
15b31c59 AX |
1550 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1551 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1552 | ||
b0fd18b0 AX |
1553 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1554 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1555 | ||
d0766e98 ZJ |
1556 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1557 | (adev->asic_type >= CHIP_VEGA10)) { | |
1558 | flags |= AMDGPU_PTE_PRT; | |
1559 | flags &= ~AMDGPU_PTE_VALID; | |
1560 | } | |
1561 | ||
a14faa65 CK |
1562 | trace_amdgpu_vm_bo_update(mapping); |
1563 | ||
63e0ba40 CK |
1564 | pfn = mapping->offset >> PAGE_SHIFT; |
1565 | if (nodes) { | |
1566 | while (pfn >= nodes->size) { | |
1567 | pfn -= nodes->size; | |
1568 | ++nodes; | |
1569 | } | |
fa3ab3c7 | 1570 | } |
a14faa65 | 1571 | |
63e0ba40 | 1572 | do { |
9fc8fc70 | 1573 | dma_addr_t *dma_addr = NULL; |
63e0ba40 CK |
1574 | uint64_t max_entries; |
1575 | uint64_t addr, last; | |
a14faa65 | 1576 | |
63e0ba40 CK |
1577 | if (nodes) { |
1578 | addr = nodes->start << PAGE_SHIFT; | |
1579 | max_entries = (nodes->size - pfn) * | |
1580 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1581 | } else { | |
1582 | addr = 0; | |
1583 | max_entries = S64_MAX; | |
1584 | } | |
a14faa65 | 1585 | |
63e0ba40 | 1586 | if (pages_addr) { |
9fc8fc70 CK |
1587 | uint64_t count; |
1588 | ||
457e0fee | 1589 | max_entries = min(max_entries, 16ull * 1024ull); |
9fc8fc70 CK |
1590 | for (count = 1; count < max_entries; ++count) { |
1591 | uint64_t idx = pfn + count; | |
1592 | ||
1593 | if (pages_addr[idx] != | |
1594 | (pages_addr[idx - 1] + PAGE_SIZE)) | |
1595 | break; | |
1596 | } | |
1597 | ||
1598 | if (count < min_linear_pages) { | |
1599 | addr = pfn << PAGE_SHIFT; | |
1600 | dma_addr = pages_addr; | |
1601 | } else { | |
1602 | addr = pages_addr[pfn]; | |
1603 | max_entries = count; | |
1604 | } | |
1605 | ||
63e0ba40 CK |
1606 | } else if (flags & AMDGPU_PTE_VALID) { |
1607 | addr += adev->vm_manager.vram_base_offset; | |
9fc8fc70 | 1608 | addr += pfn << PAGE_SHIFT; |
63e0ba40 | 1609 | } |
63e0ba40 | 1610 | |
a9f87f64 | 1611 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
9fc8fc70 | 1612 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, |
a14faa65 CK |
1613 | start, last, flags, addr, |
1614 | fence); | |
1615 | if (r) | |
1616 | return r; | |
1617 | ||
63e0ba40 CK |
1618 | pfn += last - start + 1; |
1619 | if (nodes && nodes->size == pfn) { | |
1620 | pfn = 0; | |
1621 | ++nodes; | |
1622 | } | |
a14faa65 | 1623 | start = last + 1; |
63e0ba40 | 1624 | |
a9f87f64 | 1625 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1626 | |
1627 | return 0; | |
1628 | } | |
1629 | ||
d38ceaf9 AD |
1630 | /** |
1631 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1632 | * | |
1633 | * @adev: amdgpu_device pointer | |
1634 | * @bo_va: requested BO and VM object | |
99e124f4 | 1635 | * @clear: if true clear the entries |
d38ceaf9 AD |
1636 | * |
1637 | * Fill in the page table entries for @bo_va. | |
7fc48e59 AG |
1638 | * |
1639 | * Returns: | |
1640 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1641 | */ |
1642 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1643 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1644 | bool clear) |
d38ceaf9 | 1645 | { |
ec681545 CK |
1646 | struct amdgpu_bo *bo = bo_va->base.bo; |
1647 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1648 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1649 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 1650 | struct ttm_mem_reg *mem; |
63e0ba40 | 1651 | struct drm_mm_node *nodes; |
4e55eb38 | 1652 | struct dma_fence *exclusive, **last_update; |
457e0fee | 1653 | uint64_t flags; |
d38ceaf9 AD |
1654 | int r; |
1655 | ||
ec681545 | 1656 | if (clear || !bo_va->base.bo) { |
99e124f4 | 1657 | mem = NULL; |
63e0ba40 | 1658 | nodes = NULL; |
99e124f4 CK |
1659 | exclusive = NULL; |
1660 | } else { | |
8358dcee CK |
1661 | struct ttm_dma_tt *ttm; |
1662 | ||
ec681545 | 1663 | mem = &bo_va->base.bo->tbo.mem; |
63e0ba40 CK |
1664 | nodes = mem->mm_node; |
1665 | if (mem->mem_type == TTM_PL_TT) { | |
ec681545 CK |
1666 | ttm = container_of(bo_va->base.bo->tbo.ttm, |
1667 | struct ttm_dma_tt, ttm); | |
8358dcee | 1668 | pages_addr = ttm->dma_address; |
9ab21462 | 1669 | } |
ec681545 | 1670 | exclusive = reservation_object_get_excl(bo->tbo.resv); |
d38ceaf9 AD |
1671 | } |
1672 | ||
457e0fee | 1673 | if (bo) |
ec681545 | 1674 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
457e0fee | 1675 | else |
a5f6b5b1 | 1676 | flags = 0x0; |
d38ceaf9 | 1677 | |
4e55eb38 CK |
1678 | if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) |
1679 | last_update = &vm->last_update; | |
1680 | else | |
1681 | last_update = &bo_va->last_pt_update; | |
1682 | ||
3d7d4d3a CK |
1683 | if (!clear && bo_va->base.moved) { |
1684 | bo_va->base.moved = false; | |
7fc11959 | 1685 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1686 | |
cb7b6ec2 CK |
1687 | } else if (bo_va->cleared != clear) { |
1688 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1689 | } |
7fc11959 CK |
1690 | |
1691 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
457e0fee | 1692 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
63e0ba40 | 1693 | mapping, flags, nodes, |
4e55eb38 | 1694 | last_update); |
d38ceaf9 AD |
1695 | if (r) |
1696 | return r; | |
1697 | } | |
1698 | ||
cb7b6ec2 CK |
1699 | if (vm->use_cpu_for_update) { |
1700 | /* Flush HDP */ | |
1701 | mb(); | |
69882565 | 1702 | amdgpu_asic_flush_hdp(adev, NULL); |
d6c10f6b CK |
1703 | } |
1704 | ||
af4c0f65 | 1705 | spin_lock(&vm->moved_lock); |
bb475839 | 1706 | list_del_init(&bo_va->base.vm_status); |
af4c0f65 | 1707 | spin_unlock(&vm->moved_lock); |
36188364 | 1708 | |
bb475839 JZ |
1709 | /* If the BO is not in its preferred location add it back to |
1710 | * the evicted list so that it gets validated again on the | |
1711 | * next command submission. | |
1712 | */ | |
806f043f CK |
1713 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
1714 | uint32_t mem_type = bo->tbo.mem.mem_type; | |
1715 | ||
1716 | if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type))) | |
1717 | list_add_tail(&bo_va->base.vm_status, &vm->evicted); | |
1718 | else | |
1719 | list_add(&bo_va->base.vm_status, &vm->idle); | |
1720 | } | |
d38ceaf9 | 1721 | |
cb7b6ec2 CK |
1722 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1723 | bo_va->cleared = clear; | |
1724 | ||
1725 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1726 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1727 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1728 | } |
1729 | ||
d38ceaf9 AD |
1730 | return 0; |
1731 | } | |
1732 | ||
284710fa CK |
1733 | /** |
1734 | * amdgpu_vm_update_prt_state - update the global PRT state | |
7fc48e59 AG |
1735 | * |
1736 | * @adev: amdgpu_device pointer | |
284710fa CK |
1737 | */ |
1738 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1739 | { | |
1740 | unsigned long flags; | |
1741 | bool enable; | |
1742 | ||
1743 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1744 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
132f34e4 | 1745 | adev->gmc.gmc_funcs->set_prt(adev, enable); |
284710fa CK |
1746 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); |
1747 | } | |
1748 | ||
451bc8eb | 1749 | /** |
4388fc2a | 1750 | * amdgpu_vm_prt_get - add a PRT user |
7fc48e59 AG |
1751 | * |
1752 | * @adev: amdgpu_device pointer | |
451bc8eb CK |
1753 | */ |
1754 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1755 | { | |
132f34e4 | 1756 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1757 | return; |
1758 | ||
451bc8eb CK |
1759 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1760 | amdgpu_vm_update_prt_state(adev); | |
1761 | } | |
1762 | ||
0b15f2fc CK |
1763 | /** |
1764 | * amdgpu_vm_prt_put - drop a PRT user | |
7fc48e59 AG |
1765 | * |
1766 | * @adev: amdgpu_device pointer | |
0b15f2fc CK |
1767 | */ |
1768 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1769 | { | |
451bc8eb | 1770 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1771 | amdgpu_vm_update_prt_state(adev); |
1772 | } | |
1773 | ||
284710fa | 1774 | /** |
451bc8eb | 1775 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
7fc48e59 AG |
1776 | * |
1777 | * @fence: fence for the callback | |
284710fa CK |
1778 | */ |
1779 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1780 | { | |
1781 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1782 | ||
0b15f2fc | 1783 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1784 | kfree(cb); |
1785 | } | |
1786 | ||
451bc8eb CK |
1787 | /** |
1788 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
7fc48e59 AG |
1789 | * |
1790 | * @adev: amdgpu_device pointer | |
1791 | * @fence: fence for the callback | |
451bc8eb CK |
1792 | */ |
1793 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1794 | struct dma_fence *fence) | |
1795 | { | |
4388fc2a | 1796 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1797 | |
132f34e4 | 1798 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1799 | return; |
1800 | ||
1801 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1802 | if (!cb) { |
1803 | /* Last resort when we are OOM */ | |
1804 | if (fence) | |
1805 | dma_fence_wait(fence, false); | |
1806 | ||
486a68f5 | 1807 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1808 | } else { |
1809 | cb->adev = adev; | |
1810 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1811 | amdgpu_vm_prt_cb)) | |
1812 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1813 | } | |
1814 | } | |
1815 | ||
284710fa CK |
1816 | /** |
1817 | * amdgpu_vm_free_mapping - free a mapping | |
1818 | * | |
1819 | * @adev: amdgpu_device pointer | |
1820 | * @vm: requested vm | |
1821 | * @mapping: mapping to be freed | |
1822 | * @fence: fence of the unmap operation | |
1823 | * | |
1824 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1825 | */ | |
1826 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1827 | struct amdgpu_vm *vm, | |
1828 | struct amdgpu_bo_va_mapping *mapping, | |
1829 | struct dma_fence *fence) | |
1830 | { | |
451bc8eb CK |
1831 | if (mapping->flags & AMDGPU_PTE_PRT) |
1832 | amdgpu_vm_add_prt_cb(adev, fence); | |
1833 | kfree(mapping); | |
1834 | } | |
284710fa | 1835 | |
451bc8eb CK |
1836 | /** |
1837 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1838 | * | |
1839 | * @adev: amdgpu_device pointer | |
1840 | * @vm: requested vm | |
1841 | * | |
1842 | * Register a cleanup callback to disable PRT support after VM dies. | |
1843 | */ | |
1844 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1845 | { | |
3f3333f8 | 1846 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
451bc8eb CK |
1847 | struct dma_fence *excl, **shared; |
1848 | unsigned i, shared_count; | |
1849 | int r; | |
0b15f2fc | 1850 | |
451bc8eb CK |
1851 | r = reservation_object_get_fences_rcu(resv, &excl, |
1852 | &shared_count, &shared); | |
1853 | if (r) { | |
1854 | /* Not enough memory to grab the fence list, as last resort | |
1855 | * block for all the fences to complete. | |
1856 | */ | |
1857 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1858 | MAX_SCHEDULE_TIMEOUT); | |
1859 | return; | |
284710fa | 1860 | } |
451bc8eb CK |
1861 | |
1862 | /* Add a callback for each fence in the reservation object */ | |
1863 | amdgpu_vm_prt_get(adev); | |
1864 | amdgpu_vm_add_prt_cb(adev, excl); | |
1865 | ||
1866 | for (i = 0; i < shared_count; ++i) { | |
1867 | amdgpu_vm_prt_get(adev); | |
1868 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1869 | } | |
1870 | ||
1871 | kfree(shared); | |
284710fa CK |
1872 | } |
1873 | ||
d38ceaf9 AD |
1874 | /** |
1875 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1876 | * | |
1877 | * @adev: amdgpu_device pointer | |
1878 | * @vm: requested vm | |
f3467818 NH |
1879 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1880 | * or if an error occurred) | |
d38ceaf9 AD |
1881 | * |
1882 | * Make sure all freed BOs are cleared in the PT. | |
d38ceaf9 | 1883 | * PTs have to be reserved and mutex must be locked! |
7fc48e59 AG |
1884 | * |
1885 | * Returns: | |
1886 | * 0 for success. | |
1887 | * | |
d38ceaf9 AD |
1888 | */ |
1889 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1890 | struct amdgpu_vm *vm, |
1891 | struct dma_fence **fence) | |
d38ceaf9 AD |
1892 | { |
1893 | struct amdgpu_bo_va_mapping *mapping; | |
4584312d | 1894 | uint64_t init_pte_value = 0; |
f3467818 | 1895 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1896 | int r; |
1897 | ||
1898 | while (!list_empty(&vm->freed)) { | |
1899 | mapping = list_first_entry(&vm->freed, | |
1900 | struct amdgpu_bo_va_mapping, list); | |
1901 | list_del(&mapping->list); | |
e17841b9 | 1902 | |
4584312d | 1903 | if (vm->pte_support_ats && mapping->start < AMDGPU_VA_HOLE_START) |
6d16dac8 | 1904 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec | 1905 | |
570144c6 | 1906 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, |
fc6aa33d | 1907 | mapping->start, mapping->last, |
51ac7eec | 1908 | init_pte_value, 0, &f); |
f3467818 | 1909 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1910 | if (r) { |
f3467818 | 1911 | dma_fence_put(f); |
d38ceaf9 | 1912 | return r; |
284710fa | 1913 | } |
f3467818 | 1914 | } |
d38ceaf9 | 1915 | |
f3467818 NH |
1916 | if (fence && f) { |
1917 | dma_fence_put(*fence); | |
1918 | *fence = f; | |
1919 | } else { | |
1920 | dma_fence_put(f); | |
d38ceaf9 | 1921 | } |
f3467818 | 1922 | |
d38ceaf9 AD |
1923 | return 0; |
1924 | ||
1925 | } | |
1926 | ||
1927 | /** | |
73fb16e7 | 1928 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
1929 | * |
1930 | * @adev: amdgpu_device pointer | |
1931 | * @vm: requested vm | |
1932 | * | |
73fb16e7 | 1933 | * Make sure all BOs which are moved are updated in the PTs. |
7fc48e59 AG |
1934 | * |
1935 | * Returns: | |
1936 | * 0 for success. | |
d38ceaf9 | 1937 | * |
73fb16e7 | 1938 | * PTs have to be reserved! |
d38ceaf9 | 1939 | */ |
73fb16e7 | 1940 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 1941 | struct amdgpu_vm *vm) |
d38ceaf9 | 1942 | { |
789f3317 CK |
1943 | struct amdgpu_bo_va *bo_va, *tmp; |
1944 | struct list_head moved; | |
73fb16e7 | 1945 | bool clear; |
789f3317 | 1946 | int r; |
d38ceaf9 | 1947 | |
789f3317 | 1948 | INIT_LIST_HEAD(&moved); |
af4c0f65 | 1949 | spin_lock(&vm->moved_lock); |
789f3317 CK |
1950 | list_splice_init(&vm->moved, &moved); |
1951 | spin_unlock(&vm->moved_lock); | |
32b41ac2 | 1952 | |
789f3317 CK |
1953 | list_for_each_entry_safe(bo_va, tmp, &moved, base.vm_status) { |
1954 | struct reservation_object *resv = bo_va->base.bo->tbo.resv; | |
ec363e0d | 1955 | |
73fb16e7 | 1956 | /* Per VM BOs never need to bo cleared in the page tables */ |
ec363e0d CK |
1957 | if (resv == vm->root.base.bo->tbo.resv) |
1958 | clear = false; | |
1959 | /* Try to reserve the BO to avoid clearing its ptes */ | |
9b8cad20 | 1960 | else if (!amdgpu_vm_debug && reservation_object_trylock(resv)) |
ec363e0d CK |
1961 | clear = false; |
1962 | /* Somebody else is using the BO right now */ | |
1963 | else | |
1964 | clear = true; | |
73fb16e7 CK |
1965 | |
1966 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
789f3317 CK |
1967 | if (r) { |
1968 | spin_lock(&vm->moved_lock); | |
1969 | list_splice(&moved, &vm->moved); | |
1970 | spin_unlock(&vm->moved_lock); | |
d38ceaf9 | 1971 | return r; |
789f3317 | 1972 | } |
d38ceaf9 | 1973 | |
ec363e0d CK |
1974 | if (!clear && resv != vm->root.base.bo->tbo.resv) |
1975 | reservation_object_unlock(resv); | |
1976 | ||
d38ceaf9 | 1977 | } |
d38ceaf9 | 1978 | |
789f3317 | 1979 | return 0; |
d38ceaf9 AD |
1980 | } |
1981 | ||
1982 | /** | |
1983 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1984 | * | |
1985 | * @adev: amdgpu_device pointer | |
1986 | * @vm: requested vm | |
1987 | * @bo: amdgpu buffer object | |
1988 | * | |
8843dbbb | 1989 | * Add @bo into the requested vm. |
d38ceaf9 | 1990 | * Add @bo to the list of bos associated with the vm |
7fc48e59 AG |
1991 | * |
1992 | * Returns: | |
1993 | * Newly added bo_va or NULL for failure | |
d38ceaf9 AD |
1994 | * |
1995 | * Object has to be reserved! | |
1996 | */ | |
1997 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1998 | struct amdgpu_vm *vm, | |
1999 | struct amdgpu_bo *bo) | |
2000 | { | |
2001 | struct amdgpu_bo_va *bo_va; | |
2002 | ||
2003 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2004 | if (bo_va == NULL) { | |
2005 | return NULL; | |
2006 | } | |
3f4299be | 2007 | amdgpu_vm_bo_base_init(&bo_va->base, vm, bo); |
ec681545 | 2008 | |
d38ceaf9 | 2009 | bo_va->ref_count = 1; |
7fc11959 CK |
2010 | INIT_LIST_HEAD(&bo_va->valids); |
2011 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2012 | |
d38ceaf9 AD |
2013 | return bo_va; |
2014 | } | |
2015 | ||
73fb16e7 CK |
2016 | |
2017 | /** | |
2018 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
2019 | * | |
2020 | * @adev: amdgpu_device pointer | |
2021 | * @bo_va: bo_va to store the address | |
2022 | * @mapping: the mapping to insert | |
2023 | * | |
2024 | * Insert a new mapping into all structures. | |
2025 | */ | |
2026 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2027 | struct amdgpu_bo_va *bo_va, | |
2028 | struct amdgpu_bo_va_mapping *mapping) | |
2029 | { | |
2030 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2031 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2032 | ||
aebc5e6f | 2033 | mapping->bo_va = bo_va; |
73fb16e7 CK |
2034 | list_add(&mapping->list, &bo_va->invalids); |
2035 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2036 | ||
2037 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2038 | amdgpu_vm_prt_get(adev); | |
2039 | ||
862b8c57 CK |
2040 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv && |
2041 | !bo_va->base.moved) { | |
af4c0f65 | 2042 | spin_lock(&vm->moved_lock); |
862b8c57 | 2043 | list_move(&bo_va->base.vm_status, &vm->moved); |
af4c0f65 | 2044 | spin_unlock(&vm->moved_lock); |
73fb16e7 CK |
2045 | } |
2046 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2047 | } | |
2048 | ||
d38ceaf9 AD |
2049 | /** |
2050 | * amdgpu_vm_bo_map - map bo inside a vm | |
2051 | * | |
2052 | * @adev: amdgpu_device pointer | |
2053 | * @bo_va: bo_va to store the address | |
2054 | * @saddr: where to map the BO | |
2055 | * @offset: requested offset in the BO | |
2056 | * @flags: attributes of pages (read/write/valid/etc.) | |
2057 | * | |
2058 | * Add a mapping of the BO at the specefied addr into the VM. | |
7fc48e59 AG |
2059 | * |
2060 | * Returns: | |
2061 | * 0 for success, error for failure. | |
d38ceaf9 | 2062 | * |
49b02b18 | 2063 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2064 | */ |
2065 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2066 | struct amdgpu_bo_va *bo_va, | |
2067 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2068 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2069 | { |
a9f87f64 | 2070 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2071 | struct amdgpu_bo *bo = bo_va->base.bo; |
2072 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2073 | uint64_t eaddr; |
d38ceaf9 | 2074 | |
0be52de9 CK |
2075 | /* validate the parameters */ |
2076 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2077 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2078 | return -EINVAL; |
0be52de9 | 2079 | |
d38ceaf9 | 2080 | /* make sure object fit at this offset */ |
005ae95e | 2081 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2082 | if (saddr >= eaddr || |
ec681545 | 2083 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 2084 | return -EINVAL; |
d38ceaf9 | 2085 | |
d38ceaf9 AD |
2086 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2087 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2088 | ||
a9f87f64 CK |
2089 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2090 | if (tmp) { | |
d38ceaf9 AD |
2091 | /* bo and tmp overlap, invalid addr */ |
2092 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2093 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2094 | tmp->start, tmp->last + 1); |
663e4577 | 2095 | return -EINVAL; |
d38ceaf9 AD |
2096 | } |
2097 | ||
2098 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2099 | if (!mapping) |
2100 | return -ENOMEM; | |
d38ceaf9 | 2101 | |
a9f87f64 CK |
2102 | mapping->start = saddr; |
2103 | mapping->last = eaddr; | |
d38ceaf9 AD |
2104 | mapping->offset = offset; |
2105 | mapping->flags = flags; | |
2106 | ||
73fb16e7 | 2107 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
2108 | |
2109 | return 0; | |
2110 | } | |
2111 | ||
2112 | /** | |
2113 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2114 | * | |
2115 | * @adev: amdgpu_device pointer | |
2116 | * @bo_va: bo_va to store the address | |
2117 | * @saddr: where to map the BO | |
2118 | * @offset: requested offset in the BO | |
2119 | * @flags: attributes of pages (read/write/valid/etc.) | |
2120 | * | |
2121 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2122 | * mappings as we do so. | |
7fc48e59 AG |
2123 | * |
2124 | * Returns: | |
2125 | * 0 for success, error for failure. | |
80f95c57 CK |
2126 | * |
2127 | * Object has to be reserved and unreserved outside! | |
2128 | */ | |
2129 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2130 | struct amdgpu_bo_va *bo_va, | |
2131 | uint64_t saddr, uint64_t offset, | |
2132 | uint64_t size, uint64_t flags) | |
2133 | { | |
2134 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2135 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
2136 | uint64_t eaddr; |
2137 | int r; | |
2138 | ||
2139 | /* validate the parameters */ | |
2140 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2141 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2142 | return -EINVAL; | |
2143 | ||
2144 | /* make sure object fit at this offset */ | |
2145 | eaddr = saddr + size - 1; | |
2146 | if (saddr >= eaddr || | |
ec681545 | 2147 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
2148 | return -EINVAL; |
2149 | ||
2150 | /* Allocate all the needed memory */ | |
2151 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2152 | if (!mapping) | |
2153 | return -ENOMEM; | |
2154 | ||
ec681545 | 2155 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2156 | if (r) { |
2157 | kfree(mapping); | |
2158 | return r; | |
2159 | } | |
2160 | ||
2161 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2162 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2163 | ||
a9f87f64 CK |
2164 | mapping->start = saddr; |
2165 | mapping->last = eaddr; | |
80f95c57 CK |
2166 | mapping->offset = offset; |
2167 | mapping->flags = flags; | |
2168 | ||
73fb16e7 | 2169 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 2170 | |
d38ceaf9 | 2171 | return 0; |
d38ceaf9 AD |
2172 | } |
2173 | ||
2174 | /** | |
2175 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2176 | * | |
2177 | * @adev: amdgpu_device pointer | |
2178 | * @bo_va: bo_va to remove the address from | |
2179 | * @saddr: where to the BO is mapped | |
2180 | * | |
2181 | * Remove a mapping of the BO at the specefied addr from the VM. | |
7fc48e59 AG |
2182 | * |
2183 | * Returns: | |
2184 | * 0 for success, error for failure. | |
d38ceaf9 | 2185 | * |
49b02b18 | 2186 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2187 | */ |
2188 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2189 | struct amdgpu_bo_va *bo_va, | |
2190 | uint64_t saddr) | |
2191 | { | |
2192 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2193 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2194 | bool valid = true; |
d38ceaf9 | 2195 | |
6c7fc503 | 2196 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2197 | |
7fc11959 | 2198 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2199 | if (mapping->start == saddr) |
d38ceaf9 AD |
2200 | break; |
2201 | } | |
2202 | ||
7fc11959 CK |
2203 | if (&mapping->list == &bo_va->valids) { |
2204 | valid = false; | |
2205 | ||
2206 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2207 | if (mapping->start == saddr) |
7fc11959 CK |
2208 | break; |
2209 | } | |
2210 | ||
32b41ac2 | 2211 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2212 | return -ENOENT; |
d38ceaf9 | 2213 | } |
32b41ac2 | 2214 | |
d38ceaf9 | 2215 | list_del(&mapping->list); |
a9f87f64 | 2216 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2217 | mapping->bo_va = NULL; |
93e3e438 | 2218 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2219 | |
e17841b9 | 2220 | if (valid) |
d38ceaf9 | 2221 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2222 | else |
284710fa CK |
2223 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2224 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2225 | |
2226 | return 0; | |
2227 | } | |
2228 | ||
dc54d3d1 CK |
2229 | /** |
2230 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2231 | * | |
2232 | * @adev: amdgpu_device pointer | |
2233 | * @vm: VM structure to use | |
2234 | * @saddr: start of the range | |
2235 | * @size: size of the range | |
2236 | * | |
2237 | * Remove all mappings in a range, split them as appropriate. | |
7fc48e59 AG |
2238 | * |
2239 | * Returns: | |
2240 | * 0 for success, error for failure. | |
dc54d3d1 CK |
2241 | */ |
2242 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2243 | struct amdgpu_vm *vm, | |
2244 | uint64_t saddr, uint64_t size) | |
2245 | { | |
2246 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2247 | LIST_HEAD(removed); |
2248 | uint64_t eaddr; | |
2249 | ||
2250 | eaddr = saddr + size - 1; | |
2251 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2252 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2253 | ||
2254 | /* Allocate all the needed memory */ | |
2255 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2256 | if (!before) | |
2257 | return -ENOMEM; | |
27f6d610 | 2258 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2259 | |
2260 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2261 | if (!after) { | |
2262 | kfree(before); | |
2263 | return -ENOMEM; | |
2264 | } | |
27f6d610 | 2265 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2266 | |
2267 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2268 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2269 | while (tmp) { | |
dc54d3d1 | 2270 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2271 | if (tmp->start < saddr) { |
2272 | before->start = tmp->start; | |
2273 | before->last = saddr - 1; | |
dc54d3d1 CK |
2274 | before->offset = tmp->offset; |
2275 | before->flags = tmp->flags; | |
387f49e5 JZ |
2276 | before->bo_va = tmp->bo_va; |
2277 | list_add(&before->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2278 | } |
2279 | ||
2280 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2281 | if (tmp->last > eaddr) { |
2282 | after->start = eaddr + 1; | |
2283 | after->last = tmp->last; | |
dc54d3d1 | 2284 | after->offset = tmp->offset; |
a9f87f64 | 2285 | after->offset += after->start - tmp->start; |
dc54d3d1 | 2286 | after->flags = tmp->flags; |
387f49e5 JZ |
2287 | after->bo_va = tmp->bo_va; |
2288 | list_add(&after->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2289 | } |
2290 | ||
2291 | list_del(&tmp->list); | |
2292 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2293 | |
2294 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2295 | } |
2296 | ||
2297 | /* And free them up */ | |
2298 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2299 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2300 | list_del(&tmp->list); |
2301 | ||
a9f87f64 CK |
2302 | if (tmp->start < saddr) |
2303 | tmp->start = saddr; | |
2304 | if (tmp->last > eaddr) | |
2305 | tmp->last = eaddr; | |
dc54d3d1 | 2306 | |
aebc5e6f | 2307 | tmp->bo_va = NULL; |
dc54d3d1 CK |
2308 | list_add(&tmp->list, &vm->freed); |
2309 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2310 | } | |
2311 | ||
27f6d610 JZ |
2312 | /* Insert partial mapping before the range */ |
2313 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2314 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2315 | if (before->flags & AMDGPU_PTE_PRT) |
2316 | amdgpu_vm_prt_get(adev); | |
2317 | } else { | |
2318 | kfree(before); | |
2319 | } | |
2320 | ||
2321 | /* Insert partial mapping after the range */ | |
27f6d610 | 2322 | if (!list_empty(&after->list)) { |
a9f87f64 | 2323 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2324 | if (after->flags & AMDGPU_PTE_PRT) |
2325 | amdgpu_vm_prt_get(adev); | |
2326 | } else { | |
2327 | kfree(after); | |
2328 | } | |
2329 | ||
2330 | return 0; | |
2331 | } | |
2332 | ||
aebc5e6f CK |
2333 | /** |
2334 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2335 | * | |
2336 | * @vm: the requested VM | |
2337 | * | |
2338 | * Find a mapping by it's address. | |
7fc48e59 AG |
2339 | * |
2340 | * Returns: | |
2341 | * The amdgpu_bo_va_mapping matching for addr or NULL | |
2342 | * | |
aebc5e6f CK |
2343 | */ |
2344 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2345 | uint64_t addr) | |
2346 | { | |
2347 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2348 | } | |
2349 | ||
d38ceaf9 AD |
2350 | /** |
2351 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2352 | * | |
2353 | * @adev: amdgpu_device pointer | |
2354 | * @bo_va: requested bo_va | |
2355 | * | |
8843dbbb | 2356 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2357 | * |
2358 | * Object have to be reserved! | |
2359 | */ | |
2360 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2361 | struct amdgpu_bo_va *bo_va) | |
2362 | { | |
2363 | struct amdgpu_bo_va_mapping *mapping, *next; | |
ec681545 | 2364 | struct amdgpu_vm *vm = bo_va->base.vm; |
d38ceaf9 | 2365 | |
ec681545 | 2366 | list_del(&bo_va->base.bo_list); |
d38ceaf9 | 2367 | |
af4c0f65 | 2368 | spin_lock(&vm->moved_lock); |
ec681545 | 2369 | list_del(&bo_va->base.vm_status); |
af4c0f65 | 2370 | spin_unlock(&vm->moved_lock); |
d38ceaf9 | 2371 | |
7fc11959 | 2372 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2373 | list_del(&mapping->list); |
a9f87f64 | 2374 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2375 | mapping->bo_va = NULL; |
93e3e438 | 2376 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2377 | list_add(&mapping->list, &vm->freed); |
2378 | } | |
2379 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2380 | list_del(&mapping->list); | |
a9f87f64 | 2381 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2382 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2383 | bo_va->last_pt_update); | |
d38ceaf9 | 2384 | } |
32b41ac2 | 2385 | |
f54d1867 | 2386 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2387 | kfree(bo_va); |
d38ceaf9 AD |
2388 | } |
2389 | ||
2390 | /** | |
2391 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2392 | * | |
2393 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
2394 | * @bo: amdgpu buffer object |
2395 | * | |
8843dbbb | 2396 | * Mark @bo as invalid. |
d38ceaf9 AD |
2397 | */ |
2398 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2399 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2400 | { |
ec681545 CK |
2401 | struct amdgpu_vm_bo_base *bo_base; |
2402 | ||
4bebccee CZ |
2403 | /* shadow bo doesn't have bo base, its validation needs its parent */ |
2404 | if (bo->parent && bo->parent->shadow == bo) | |
2405 | bo = bo->parent; | |
2406 | ||
ec681545 | 2407 | list_for_each_entry(bo_base, &bo->va, bo_list) { |
3f3333f8 | 2408 | struct amdgpu_vm *vm = bo_base->vm; |
862b8c57 | 2409 | bool was_moved = bo_base->moved; |
3f3333f8 | 2410 | |
3d7d4d3a | 2411 | bo_base->moved = true; |
3f3333f8 | 2412 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
73fb16e7 CK |
2413 | if (bo->tbo.type == ttm_bo_type_kernel) |
2414 | list_move(&bo_base->vm_status, &vm->evicted); | |
2415 | else | |
2416 | list_move_tail(&bo_base->vm_status, | |
2417 | &vm->evicted); | |
3f3333f8 CK |
2418 | continue; |
2419 | } | |
2420 | ||
862b8c57 | 2421 | if (was_moved) |
3f3333f8 CK |
2422 | continue; |
2423 | ||
862b8c57 CK |
2424 | if (bo->tbo.type == ttm_bo_type_kernel) { |
2425 | list_move(&bo_base->vm_status, &vm->relocated); | |
2426 | } else { | |
2427 | spin_lock(&bo_base->vm->moved_lock); | |
2428 | list_move(&bo_base->vm_status, &vm->moved); | |
2429 | spin_unlock(&bo_base->vm->moved_lock); | |
2430 | } | |
d38ceaf9 AD |
2431 | } |
2432 | } | |
2433 | ||
7fc48e59 AG |
2434 | /** |
2435 | * amdgpu_vm_get_block_size - calculate VM page table size as power of two | |
2436 | * | |
2437 | * @vm_size: VM size | |
2438 | * | |
2439 | * Returns: | |
2440 | * VM page table as power of two | |
2441 | */ | |
bab4fee7 JZ |
2442 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2443 | { | |
2444 | /* Total bits covered by PD + PTs */ | |
2445 | unsigned bits = ilog2(vm_size) + 18; | |
2446 | ||
2447 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2448 | Above that split equal between PD and PTs */ | |
2449 | if (vm_size <= 8) | |
2450 | return (bits - 9); | |
2451 | else | |
2452 | return ((bits + 3) / 2); | |
2453 | } | |
2454 | ||
d07f14be RH |
2455 | /** |
2456 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2457 | * |
2458 | * @adev: amdgpu_device pointer | |
2459 | * @vm_size: the default vm size if it's set auto | |
2460 | */ | |
fdd5faaa | 2461 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, |
f3368128 CK |
2462 | uint32_t fragment_size_default, unsigned max_level, |
2463 | unsigned max_bits) | |
bab4fee7 | 2464 | { |
36539dce CK |
2465 | uint64_t tmp; |
2466 | ||
2467 | /* adjust vm size first */ | |
f3368128 CK |
2468 | if (amdgpu_vm_size != -1) { |
2469 | unsigned max_size = 1 << (max_bits - 30); | |
2470 | ||
fdd5faaa | 2471 | vm_size = amdgpu_vm_size; |
f3368128 CK |
2472 | if (vm_size > max_size) { |
2473 | dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", | |
2474 | amdgpu_vm_size, max_size); | |
2475 | vm_size = max_size; | |
2476 | } | |
2477 | } | |
fdd5faaa CK |
2478 | |
2479 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
36539dce CK |
2480 | |
2481 | tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); | |
97489129 CK |
2482 | if (amdgpu_vm_block_size != -1) |
2483 | tmp >>= amdgpu_vm_block_size - 9; | |
36539dce CK |
2484 | tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; |
2485 | adev->vm_manager.num_level = min(max_level, (unsigned)tmp); | |
196f7489 CZ |
2486 | switch (adev->vm_manager.num_level) { |
2487 | case 3: | |
2488 | adev->vm_manager.root_level = AMDGPU_VM_PDB2; | |
2489 | break; | |
2490 | case 2: | |
2491 | adev->vm_manager.root_level = AMDGPU_VM_PDB1; | |
2492 | break; | |
2493 | case 1: | |
2494 | adev->vm_manager.root_level = AMDGPU_VM_PDB0; | |
2495 | break; | |
2496 | default: | |
2497 | dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n"); | |
2498 | } | |
b38f41eb | 2499 | /* block size depends on vm size and hw setup*/ |
97489129 | 2500 | if (amdgpu_vm_block_size != -1) |
bab4fee7 | 2501 | adev->vm_manager.block_size = |
97489129 CK |
2502 | min((unsigned)amdgpu_vm_block_size, max_bits |
2503 | - AMDGPU_GPU_PAGE_SHIFT | |
2504 | - 9 * adev->vm_manager.num_level); | |
2505 | else if (adev->vm_manager.num_level > 1) | |
2506 | adev->vm_manager.block_size = 9; | |
bab4fee7 | 2507 | else |
97489129 | 2508 | adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); |
bab4fee7 | 2509 | |
b38f41eb CK |
2510 | if (amdgpu_vm_fragment_size == -1) |
2511 | adev->vm_manager.fragment_size = fragment_size_default; | |
2512 | else | |
2513 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
d07f14be | 2514 | |
36539dce CK |
2515 | DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", |
2516 | vm_size, adev->vm_manager.num_level + 1, | |
2517 | adev->vm_manager.block_size, | |
fdd5faaa | 2518 | adev->vm_manager.fragment_size); |
bab4fee7 JZ |
2519 | } |
2520 | ||
d38ceaf9 AD |
2521 | /** |
2522 | * amdgpu_vm_init - initialize a vm instance | |
2523 | * | |
2524 | * @adev: amdgpu_device pointer | |
2525 | * @vm: requested vm | |
9a4b7d4c | 2526 | * @vm_context: Indicates if it GFX or Compute context |
d38ceaf9 | 2527 | * |
8843dbbb | 2528 | * Init @vm fields. |
7fc48e59 AG |
2529 | * |
2530 | * Returns: | |
2531 | * 0 for success, error for failure. | |
d38ceaf9 | 2532 | */ |
9a4b7d4c | 2533 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 2534 | int vm_context, unsigned int pasid) |
d38ceaf9 | 2535 | { |
3216c6b7 | 2536 | struct amdgpu_bo_param bp; |
3f4299be | 2537 | struct amdgpu_bo *root; |
d38ceaf9 | 2538 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, |
36b32a68 | 2539 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2540 | unsigned ring_instance; |
2541 | struct amdgpu_ring *ring; | |
1b1f42d8 | 2542 | struct drm_sched_rq *rq; |
d3aab672 | 2543 | unsigned long size; |
13307f7e | 2544 | uint64_t flags; |
36bbf3bf | 2545 | int r, i; |
d38ceaf9 | 2546 | |
f808c13f | 2547 | vm->va = RB_ROOT_CACHED; |
36bbf3bf CZ |
2548 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2549 | vm->reserved_vmid[i] = NULL; | |
3f3333f8 | 2550 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2551 | INIT_LIST_HEAD(&vm->relocated); |
af4c0f65 | 2552 | spin_lock_init(&vm->moved_lock); |
27c7b9ae | 2553 | INIT_LIST_HEAD(&vm->moved); |
806f043f | 2554 | INIT_LIST_HEAD(&vm->idle); |
d38ceaf9 | 2555 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2556 | |
2bd9ccfa | 2557 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2558 | |
2559 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2560 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2561 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
1b1f42d8 LS |
2562 | rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL]; |
2563 | r = drm_sched_entity_init(&ring->sched, &vm->entity, | |
8344c53f | 2564 | rq, NULL); |
2bd9ccfa | 2565 | if (r) |
f566ceb1 | 2566 | return r; |
2bd9ccfa | 2567 | |
51ac7eec YZ |
2568 | vm->pte_support_ats = false; |
2569 | ||
2570 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2571 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2572 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec | 2573 | |
13307f7e | 2574 | if (adev->asic_type == CHIP_RAVEN) |
51ac7eec | 2575 | vm->pte_support_ats = true; |
13307f7e | 2576 | } else { |
9a4b7d4c HK |
2577 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2578 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
13307f7e | 2579 | } |
9a4b7d4c HK |
2580 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2581 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
2582 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), | |
2583 | "CPU update of VM recommended only for large BAR system\n"); | |
d5884513 | 2584 | vm->last_update = NULL; |
05906dec | 2585 | |
13307f7e | 2586 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; |
3c824172 HK |
2587 | if (vm->use_cpu_for_update) |
2588 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
2589 | else | |
810955ba | 2590 | flags |= AMDGPU_GEM_CREATE_SHADOW; |
3c824172 | 2591 | |
d3aab672 | 2592 | size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level); |
3216c6b7 CZ |
2593 | memset(&bp, 0, sizeof(bp)); |
2594 | bp.size = size; | |
2595 | bp.byte_align = align; | |
2596 | bp.domain = AMDGPU_GEM_DOMAIN_VRAM; | |
2597 | bp.flags = flags; | |
2598 | bp.type = ttm_bo_type_kernel; | |
2599 | bp.resv = NULL; | |
3f4299be | 2600 | r = amdgpu_bo_create(adev, &bp, &root); |
d38ceaf9 | 2601 | if (r) |
2bd9ccfa CK |
2602 | goto error_free_sched_entity; |
2603 | ||
3f4299be | 2604 | r = amdgpu_bo_reserve(root, true); |
d3aab672 CK |
2605 | if (r) |
2606 | goto error_free_root; | |
2607 | ||
3f4299be | 2608 | r = amdgpu_vm_clear_bo(adev, vm, root, |
4584312d CK |
2609 | adev->vm_manager.root_level, |
2610 | vm->pte_support_ats); | |
13307f7e CK |
2611 | if (r) |
2612 | goto error_unreserve; | |
2613 | ||
3f4299be | 2614 | amdgpu_vm_bo_base_init(&vm->root.base, vm, root); |
d3aab672 | 2615 | amdgpu_bo_unreserve(vm->root.base.bo); |
d38ceaf9 | 2616 | |
02208441 FK |
2617 | if (pasid) { |
2618 | unsigned long flags; | |
2619 | ||
2620 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2621 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2622 | GFP_ATOMIC); | |
2623 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2624 | if (r < 0) | |
2625 | goto error_free_root; | |
2626 | ||
2627 | vm->pasid = pasid; | |
0a096fb6 CK |
2628 | } |
2629 | ||
a2f14820 | 2630 | INIT_KFIFO(vm->faults); |
c98171cc | 2631 | vm->fault_credit = 16; |
d38ceaf9 AD |
2632 | |
2633 | return 0; | |
2bd9ccfa | 2634 | |
13307f7e CK |
2635 | error_unreserve: |
2636 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2637 | ||
67003a15 | 2638 | error_free_root: |
3f3333f8 CK |
2639 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2640 | amdgpu_bo_unref(&vm->root.base.bo); | |
2641 | vm->root.base.bo = NULL; | |
2bd9ccfa CK |
2642 | |
2643 | error_free_sched_entity: | |
1b1f42d8 | 2644 | drm_sched_entity_fini(&ring->sched, &vm->entity); |
2bd9ccfa CK |
2645 | |
2646 | return r; | |
d38ceaf9 AD |
2647 | } |
2648 | ||
b236fa1d FK |
2649 | /** |
2650 | * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM | |
2651 | * | |
7fc48e59 AG |
2652 | * @adev: amdgpu_device pointer |
2653 | * @vm: requested vm | |
2654 | * | |
b236fa1d FK |
2655 | * This only works on GFX VMs that don't have any BOs added and no |
2656 | * page tables allocated yet. | |
2657 | * | |
2658 | * Changes the following VM parameters: | |
2659 | * - use_cpu_for_update | |
2660 | * - pte_supports_ats | |
2661 | * - pasid (old PASID is released, because compute manages its own PASIDs) | |
2662 | * | |
2663 | * Reinitializes the page directory to reflect the changed ATS | |
2664 | * setting. May leave behind an unused shadow BO for the page | |
2665 | * directory when switching from SDMA updates to CPU updates. | |
2666 | * | |
7fc48e59 AG |
2667 | * Returns: |
2668 | * 0 for success, -errno for errors. | |
b236fa1d FK |
2669 | */ |
2670 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2671 | { | |
2672 | bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); | |
2673 | int r; | |
2674 | ||
2675 | r = amdgpu_bo_reserve(vm->root.base.bo, true); | |
2676 | if (r) | |
2677 | return r; | |
2678 | ||
2679 | /* Sanity checks */ | |
2680 | if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) { | |
2681 | r = -EINVAL; | |
2682 | goto error; | |
2683 | } | |
2684 | ||
2685 | /* Check if PD needs to be reinitialized and do it before | |
2686 | * changing any other state, in case it fails. | |
2687 | */ | |
2688 | if (pte_support_ats != vm->pte_support_ats) { | |
2689 | r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, | |
2690 | adev->vm_manager.root_level, | |
2691 | pte_support_ats); | |
2692 | if (r) | |
2693 | goto error; | |
2694 | } | |
2695 | ||
2696 | /* Update VM state */ | |
2697 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
2698 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
2699 | vm->pte_support_ats = pte_support_ats; | |
2700 | DRM_DEBUG_DRIVER("VM update mode is %s\n", | |
2701 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
2702 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), | |
2703 | "CPU update of VM recommended only for large BAR system\n"); | |
2704 | ||
2705 | if (vm->pasid) { | |
2706 | unsigned long flags; | |
2707 | ||
2708 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2709 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2710 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2711 | ||
2712 | vm->pasid = 0; | |
2713 | } | |
2714 | ||
2715 | error: | |
2716 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2717 | return r; | |
2718 | } | |
2719 | ||
f566ceb1 CK |
2720 | /** |
2721 | * amdgpu_vm_free_levels - free PD/PT levels | |
2722 | * | |
8f19cd78 CK |
2723 | * @adev: amdgpu device structure |
2724 | * @parent: PD/PT starting level to free | |
2725 | * @level: level of parent structure | |
f566ceb1 CK |
2726 | * |
2727 | * Free the page directory or page table level and all sub levels. | |
2728 | */ | |
8f19cd78 CK |
2729 | static void amdgpu_vm_free_levels(struct amdgpu_device *adev, |
2730 | struct amdgpu_vm_pt *parent, | |
2731 | unsigned level) | |
f566ceb1 | 2732 | { |
8f19cd78 | 2733 | unsigned i, num_entries = amdgpu_vm_num_entries(adev, level); |
f566ceb1 | 2734 | |
8f19cd78 CK |
2735 | if (parent->base.bo) { |
2736 | list_del(&parent->base.bo_list); | |
2737 | list_del(&parent->base.vm_status); | |
2738 | amdgpu_bo_unref(&parent->base.bo->shadow); | |
2739 | amdgpu_bo_unref(&parent->base.bo); | |
f566ceb1 CK |
2740 | } |
2741 | ||
8f19cd78 CK |
2742 | if (parent->entries) |
2743 | for (i = 0; i < num_entries; i++) | |
2744 | amdgpu_vm_free_levels(adev, &parent->entries[i], | |
2745 | level + 1); | |
f566ceb1 | 2746 | |
8f19cd78 | 2747 | kvfree(parent->entries); |
f566ceb1 CK |
2748 | } |
2749 | ||
d38ceaf9 AD |
2750 | /** |
2751 | * amdgpu_vm_fini - tear down a vm instance | |
2752 | * | |
2753 | * @adev: amdgpu_device pointer | |
2754 | * @vm: requested vm | |
2755 | * | |
8843dbbb | 2756 | * Tear down @vm. |
d38ceaf9 AD |
2757 | * Unbind the VM and remove all bos from the vm bo list |
2758 | */ | |
2759 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2760 | { | |
2761 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
132f34e4 | 2762 | bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt; |
2642cf11 | 2763 | struct amdgpu_bo *root; |
a2f14820 | 2764 | u64 fault; |
2642cf11 | 2765 | int i, r; |
d38ceaf9 | 2766 | |
ede0dd86 FK |
2767 | amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm); |
2768 | ||
a2f14820 FK |
2769 | /* Clear pending page faults from IH when the VM is destroyed */ |
2770 | while (kfifo_get(&vm->faults, &fault)) | |
2771 | amdgpu_ih_clear_fault(adev, fault); | |
2772 | ||
02208441 FK |
2773 | if (vm->pasid) { |
2774 | unsigned long flags; | |
2775 | ||
2776 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2777 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2778 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2779 | } | |
2780 | ||
1b1f42d8 | 2781 | drm_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 2782 | |
f808c13f | 2783 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
d38ceaf9 AD |
2784 | dev_err(adev->dev, "still active bo inside vm\n"); |
2785 | } | |
f808c13f DB |
2786 | rbtree_postorder_for_each_entry_safe(mapping, tmp, |
2787 | &vm->va.rb_root, rb) { | |
d38ceaf9 | 2788 | list_del(&mapping->list); |
a9f87f64 | 2789 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2790 | kfree(mapping); |
2791 | } | |
2792 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2793 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2794 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2795 | prt_fini_needed = false; |
451bc8eb | 2796 | } |
284710fa | 2797 | |
d38ceaf9 | 2798 | list_del(&mapping->list); |
451bc8eb | 2799 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2800 | } |
2801 | ||
2642cf11 CK |
2802 | root = amdgpu_bo_ref(vm->root.base.bo); |
2803 | r = amdgpu_bo_reserve(root, true); | |
2804 | if (r) { | |
2805 | dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); | |
2806 | } else { | |
196f7489 CZ |
2807 | amdgpu_vm_free_levels(adev, &vm->root, |
2808 | adev->vm_manager.root_level); | |
2642cf11 CK |
2809 | amdgpu_bo_unreserve(root); |
2810 | } | |
2811 | amdgpu_bo_unref(&root); | |
d5884513 | 2812 | dma_fence_put(vm->last_update); |
1e9ef26f | 2813 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
620f774f | 2814 | amdgpu_vmid_free_reserved(adev, vm, i); |
d38ceaf9 | 2815 | } |
ea89f8c9 | 2816 | |
c98171cc FK |
2817 | /** |
2818 | * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID | |
2819 | * | |
2820 | * @adev: amdgpu_device pointer | |
2821 | * @pasid: PASID do identify the VM | |
2822 | * | |
7fc48e59 AG |
2823 | * This function is expected to be called in interrupt context. |
2824 | * | |
2825 | * Returns: | |
2826 | * True if there was fault credit, false otherwise | |
c98171cc FK |
2827 | */ |
2828 | bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, | |
2829 | unsigned int pasid) | |
2830 | { | |
2831 | struct amdgpu_vm *vm; | |
2832 | ||
2833 | spin_lock(&adev->vm_manager.pasid_lock); | |
2834 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
d958939a | 2835 | if (!vm) { |
c98171cc | 2836 | /* VM not found, can't track fault credit */ |
d958939a | 2837 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc | 2838 | return true; |
d958939a | 2839 | } |
c98171cc FK |
2840 | |
2841 | /* No lock needed. only accessed by IRQ handler */ | |
d958939a | 2842 | if (!vm->fault_credit) { |
c98171cc | 2843 | /* Too many faults in this VM */ |
d958939a | 2844 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc | 2845 | return false; |
d958939a | 2846 | } |
c98171cc FK |
2847 | |
2848 | vm->fault_credit--; | |
d958939a | 2849 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc FK |
2850 | return true; |
2851 | } | |
2852 | ||
a9a78b32 CK |
2853 | /** |
2854 | * amdgpu_vm_manager_init - init the VM manager | |
2855 | * | |
2856 | * @adev: amdgpu_device pointer | |
2857 | * | |
2858 | * Initialize the VM manager structures | |
2859 | */ | |
2860 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2861 | { | |
620f774f | 2862 | unsigned i; |
a9a78b32 | 2863 | |
620f774f | 2864 | amdgpu_vmid_mgr_init(adev); |
2d55e45a | 2865 | |
f54d1867 CW |
2866 | adev->vm_manager.fence_context = |
2867 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2868 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2869 | adev->vm_manager.seqno[i] = 0; | |
2870 | ||
2d55e45a | 2871 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
284710fa | 2872 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2873 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
2874 | |
2875 | /* If not overridden by the user, by default, only in large BAR systems | |
2876 | * Compute VM tables will be updated by CPU | |
2877 | */ | |
2878 | #ifdef CONFIG_X86_64 | |
2879 | if (amdgpu_vm_update_mode == -1) { | |
2880 | if (amdgpu_vm_is_large_bar(adev)) | |
2881 | adev->vm_manager.vm_update_mode = | |
2882 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
2883 | else | |
2884 | adev->vm_manager.vm_update_mode = 0; | |
2885 | } else | |
2886 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
2887 | #else | |
2888 | adev->vm_manager.vm_update_mode = 0; | |
2889 | #endif | |
2890 | ||
02208441 FK |
2891 | idr_init(&adev->vm_manager.pasid_idr); |
2892 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
a9a78b32 CK |
2893 | } |
2894 | ||
ea89f8c9 CK |
2895 | /** |
2896 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2897 | * | |
2898 | * @adev: amdgpu_device pointer | |
2899 | * | |
2900 | * Cleanup the VM manager and free resources. | |
2901 | */ | |
2902 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2903 | { | |
02208441 FK |
2904 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); |
2905 | idr_destroy(&adev->vm_manager.pasid_idr); | |
2906 | ||
620f774f | 2907 | amdgpu_vmid_mgr_fini(adev); |
ea89f8c9 | 2908 | } |
cfbcacf4 | 2909 | |
7fc48e59 AG |
2910 | /** |
2911 | * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs. | |
2912 | * | |
2913 | * @dev: drm device pointer | |
2914 | * @data: drm_amdgpu_vm | |
2915 | * @filp: drm file pointer | |
2916 | * | |
2917 | * Returns: | |
2918 | * 0 for success, -errno for errors. | |
2919 | */ | |
cfbcacf4 CZ |
2920 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
2921 | { | |
2922 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
2923 | struct amdgpu_device *adev = dev->dev_private; |
2924 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
2925 | int r; | |
cfbcacf4 CZ |
2926 | |
2927 | switch (args->in.op) { | |
2928 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f | 2929 | /* current, we only have requirement to reserve vmid from gfxhub */ |
620f774f | 2930 | r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
1e9ef26f CZ |
2931 | if (r) |
2932 | return r; | |
2933 | break; | |
cfbcacf4 | 2934 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
620f774f | 2935 | amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
2936 | break; |
2937 | default: | |
2938 | return -EINVAL; | |
2939 | } | |
2940 | ||
2941 | return 0; | |
2942 | } |