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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
02208441 | 30 | #include <linux/idr.h> |
fdf2f6c5 | 31 | |
d38ceaf9 AD |
32 | #include <drm/amdgpu_drm.h> |
33 | #include "amdgpu.h" | |
34 | #include "amdgpu_trace.h" | |
ede0dd86 | 35 | #include "amdgpu_amdkfd.h" |
c8c5e569 | 36 | #include "amdgpu_gmc.h" |
df399b06 | 37 | #include "amdgpu_xgmi.h" |
d38ceaf9 | 38 | |
7fc48e59 AG |
39 | /** |
40 | * DOC: GPUVM | |
41 | * | |
d38ceaf9 AD |
42 | * GPUVM is similar to the legacy gart on older asics, however |
43 | * rather than there being a single global gart table | |
44 | * for the entire GPU, there are multiple VM page tables active | |
45 | * at any given time. The VM page tables can contain a mix | |
46 | * vram pages and system memory pages and system memory pages | |
47 | * can be mapped as snooped (cached system pages) or unsnooped | |
48 | * (uncached system pages). | |
49 | * Each VM has an ID associated with it and there is a page table | |
50 | * associated with each VMID. When execting a command buffer, | |
51 | * the kernel tells the the ring what VMID to use for that command | |
52 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
53 | * The userspace drivers maintain their own address space and the kernel | |
54 | * sets up their pages tables accordingly when they submit their | |
55 | * command buffers and a VMID is assigned. | |
56 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
57 | * SI supports 16. | |
58 | */ | |
59 | ||
a9f87f64 CK |
60 | #define START(node) ((node)->start) |
61 | #define LAST(node) ((node)->last) | |
62 | ||
63 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
64 | START, LAST, static, amdgpu_vm_it) | |
65 | ||
66 | #undef START | |
67 | #undef LAST | |
68 | ||
7fc48e59 AG |
69 | /** |
70 | * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback | |
71 | */ | |
284710fa | 72 | struct amdgpu_prt_cb { |
7fc48e59 AG |
73 | |
74 | /** | |
75 | * @adev: amdgpu device | |
76 | */ | |
284710fa | 77 | struct amdgpu_device *adev; |
7fc48e59 AG |
78 | |
79 | /** | |
80 | * @cb: callback | |
81 | */ | |
284710fa CK |
82 | struct dma_fence_cb cb; |
83 | }; | |
84 | ||
50783147 CK |
85 | /** |
86 | * amdgpu_vm_level_shift - return the addr shift for each level | |
87 | * | |
88 | * @adev: amdgpu_device pointer | |
7fc48e59 | 89 | * @level: VMPT level |
50783147 | 90 | * |
7fc48e59 AG |
91 | * Returns: |
92 | * The number of bits the pfn needs to be right shifted for a level. | |
50783147 CK |
93 | */ |
94 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
95 | unsigned level) | |
96 | { | |
196f7489 CZ |
97 | unsigned shift = 0xff; |
98 | ||
99 | switch (level) { | |
100 | case AMDGPU_VM_PDB2: | |
101 | case AMDGPU_VM_PDB1: | |
102 | case AMDGPU_VM_PDB0: | |
103 | shift = 9 * (AMDGPU_VM_PDB0 - level) + | |
50783147 | 104 | adev->vm_manager.block_size; |
196f7489 CZ |
105 | break; |
106 | case AMDGPU_VM_PTB: | |
107 | shift = 0; | |
108 | break; | |
109 | default: | |
110 | dev_err(adev->dev, "the level%d isn't supported.\n", level); | |
111 | } | |
112 | ||
113 | return shift; | |
50783147 CK |
114 | } |
115 | ||
d38ceaf9 | 116 | /** |
72a7ec5c | 117 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
118 | * |
119 | * @adev: amdgpu_device pointer | |
7fc48e59 | 120 | * @level: VMPT level |
d38ceaf9 | 121 | * |
7fc48e59 AG |
122 | * Returns: |
123 | * The number of entries in a page directory or page table. | |
d38ceaf9 | 124 | */ |
72a7ec5c CK |
125 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
126 | unsigned level) | |
d38ceaf9 | 127 | { |
196f7489 CZ |
128 | unsigned shift = amdgpu_vm_level_shift(adev, |
129 | adev->vm_manager.root_level); | |
0410c5e5 | 130 | |
196f7489 | 131 | if (level == adev->vm_manager.root_level) |
72a7ec5c | 132 | /* For the root directory */ |
fc39d903 CK |
133 | return round_up(adev->vm_manager.max_pfn, 1ULL << shift) |
134 | >> shift; | |
196f7489 | 135 | else if (level != AMDGPU_VM_PTB) |
0410c5e5 CK |
136 | /* Everything in between */ |
137 | return 512; | |
138 | else | |
72a7ec5c | 139 | /* For the page tables on the leaves */ |
36b32a68 | 140 | return AMDGPU_VM_PTE_COUNT(adev); |
d38ceaf9 AD |
141 | } |
142 | ||
780637cb CK |
143 | /** |
144 | * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD | |
145 | * | |
146 | * @adev: amdgpu_device pointer | |
147 | * | |
148 | * Returns: | |
149 | * The number of entries in the root page directory which needs the ATS setting. | |
150 | */ | |
151 | static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev) | |
152 | { | |
153 | unsigned shift; | |
154 | ||
155 | shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level); | |
156 | return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT); | |
157 | } | |
158 | ||
cb90b97b CK |
159 | /** |
160 | * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT | |
161 | * | |
162 | * @adev: amdgpu_device pointer | |
163 | * @level: VMPT level | |
164 | * | |
165 | * Returns: | |
166 | * The mask to extract the entry number of a PD/PT from an address. | |
167 | */ | |
168 | static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev, | |
169 | unsigned int level) | |
170 | { | |
171 | if (level <= adev->vm_manager.root_level) | |
172 | return 0xffffffff; | |
173 | else if (level != AMDGPU_VM_PTB) | |
174 | return 0x1ff; | |
175 | else | |
176 | return AMDGPU_VM_PTE_COUNT(adev) - 1; | |
177 | } | |
178 | ||
d38ceaf9 | 179 | /** |
72a7ec5c | 180 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
181 | * |
182 | * @adev: amdgpu_device pointer | |
7fc48e59 | 183 | * @level: VMPT level |
d38ceaf9 | 184 | * |
7fc48e59 AG |
185 | * Returns: |
186 | * The size of the BO for a page directory or page table in bytes. | |
d38ceaf9 | 187 | */ |
72a7ec5c | 188 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 189 | { |
72a7ec5c | 190 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
191 | } |
192 | ||
bcdc9fd6 CK |
193 | /** |
194 | * amdgpu_vm_bo_evicted - vm_bo is evicted | |
195 | * | |
196 | * @vm_bo: vm_bo which is evicted | |
197 | * | |
198 | * State for PDs/PTs and per VM BOs which are not at the location they should | |
199 | * be. | |
200 | */ | |
201 | static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) | |
202 | { | |
203 | struct amdgpu_vm *vm = vm_bo->vm; | |
204 | struct amdgpu_bo *bo = vm_bo->bo; | |
205 | ||
206 | vm_bo->moved = true; | |
207 | if (bo->tbo.type == ttm_bo_type_kernel) | |
208 | list_move(&vm_bo->vm_status, &vm->evicted); | |
209 | else | |
210 | list_move_tail(&vm_bo->vm_status, &vm->evicted); | |
211 | } | |
212 | ||
213 | /** | |
214 | * amdgpu_vm_bo_relocated - vm_bo is reloacted | |
215 | * | |
216 | * @vm_bo: vm_bo which is relocated | |
217 | * | |
218 | * State for PDs/PTs which needs to update their parent PD. | |
219 | */ | |
220 | static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) | |
221 | { | |
222 | list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); | |
223 | } | |
224 | ||
225 | /** | |
226 | * amdgpu_vm_bo_moved - vm_bo is moved | |
227 | * | |
228 | * @vm_bo: vm_bo which is moved | |
229 | * | |
230 | * State for per VM BOs which are moved, but that change is not yet reflected | |
231 | * in the page tables. | |
232 | */ | |
233 | static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) | |
234 | { | |
235 | list_move(&vm_bo->vm_status, &vm_bo->vm->moved); | |
236 | } | |
237 | ||
238 | /** | |
239 | * amdgpu_vm_bo_idle - vm_bo is idle | |
240 | * | |
241 | * @vm_bo: vm_bo which is now idle | |
242 | * | |
243 | * State for PDs/PTs and per VM BOs which have gone through the state machine | |
244 | * and are now idle. | |
245 | */ | |
246 | static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) | |
247 | { | |
248 | list_move(&vm_bo->vm_status, &vm_bo->vm->idle); | |
249 | vm_bo->moved = false; | |
250 | } | |
251 | ||
252 | /** | |
253 | * amdgpu_vm_bo_invalidated - vm_bo is invalidated | |
254 | * | |
255 | * @vm_bo: vm_bo which is now invalidated | |
256 | * | |
257 | * State for normal BOs which are invalidated and that change not yet reflected | |
258 | * in the PTs. | |
259 | */ | |
260 | static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) | |
261 | { | |
262 | spin_lock(&vm_bo->vm->invalidated_lock); | |
263 | list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated); | |
264 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
265 | } | |
266 | ||
267 | /** | |
268 | * amdgpu_vm_bo_done - vm_bo is done | |
269 | * | |
270 | * @vm_bo: vm_bo which is now done | |
271 | * | |
272 | * State for normal BOs which are invalidated and that change has been updated | |
273 | * in the PTs. | |
274 | */ | |
275 | static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) | |
276 | { | |
277 | spin_lock(&vm_bo->vm->invalidated_lock); | |
278 | list_del_init(&vm_bo->vm_status); | |
279 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
280 | } | |
281 | ||
c460f8a6 CK |
282 | /** |
283 | * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm | |
284 | * | |
285 | * @base: base structure for tracking BO usage in a VM | |
286 | * @vm: vm to which bo is to be added | |
287 | * @bo: amdgpu buffer object | |
288 | * | |
289 | * Initialize a bo_va_base structure and add it to the appropriate lists | |
290 | * | |
291 | */ | |
292 | static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, | |
293 | struct amdgpu_vm *vm, | |
294 | struct amdgpu_bo *bo) | |
295 | { | |
296 | base->vm = vm; | |
297 | base->bo = bo; | |
646b9025 | 298 | base->next = NULL; |
c460f8a6 CK |
299 | INIT_LIST_HEAD(&base->vm_status); |
300 | ||
301 | if (!bo) | |
302 | return; | |
646b9025 CK |
303 | base->next = bo->vm_bo; |
304 | bo->vm_bo = base; | |
c460f8a6 | 305 | |
5a5011a7 | 306 | if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) |
c460f8a6 CK |
307 | return; |
308 | ||
309 | vm->bulk_moveable = false; | |
fda43ab6 | 310 | if (bo->tbo.type == ttm_bo_type_kernel && bo->parent) |
bcdc9fd6 | 311 | amdgpu_vm_bo_relocated(base); |
c460f8a6 | 312 | else |
bcdc9fd6 | 313 | amdgpu_vm_bo_idle(base); |
c460f8a6 CK |
314 | |
315 | if (bo->preferred_domains & | |
316 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)) | |
317 | return; | |
318 | ||
319 | /* | |
320 | * we checked all the prerequisites, but it looks like this per vm bo | |
321 | * is currently evicted. add the bo to the evicted list to make sure it | |
322 | * is validated on next vm use to avoid fault. | |
323 | * */ | |
bcdc9fd6 | 324 | amdgpu_vm_bo_evicted(base); |
c460f8a6 CK |
325 | } |
326 | ||
ba79fde4 CK |
327 | /** |
328 | * amdgpu_vm_pt_parent - get the parent page directory | |
329 | * | |
330 | * @pt: child page table | |
331 | * | |
332 | * Helper to get the parent entry for the child page table. NULL if we are at | |
333 | * the root page directory. | |
334 | */ | |
335 | static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt) | |
336 | { | |
337 | struct amdgpu_bo *parent = pt->base.bo->parent; | |
338 | ||
339 | if (!parent) | |
340 | return NULL; | |
341 | ||
646b9025 | 342 | return container_of(parent->vm_bo, struct amdgpu_vm_pt, base); |
ba79fde4 CK |
343 | } |
344 | ||
1d614ded | 345 | /* |
73633e32 CK |
346 | * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt |
347 | */ | |
348 | struct amdgpu_vm_pt_cursor { | |
349 | uint64_t pfn; | |
350 | struct amdgpu_vm_pt *parent; | |
351 | struct amdgpu_vm_pt *entry; | |
352 | unsigned level; | |
353 | }; | |
354 | ||
355 | /** | |
356 | * amdgpu_vm_pt_start - start PD/PT walk | |
357 | * | |
358 | * @adev: amdgpu_device pointer | |
359 | * @vm: amdgpu_vm structure | |
360 | * @start: start address of the walk | |
361 | * @cursor: state to initialize | |
362 | * | |
363 | * Initialize a amdgpu_vm_pt_cursor to start a walk. | |
364 | */ | |
365 | static void amdgpu_vm_pt_start(struct amdgpu_device *adev, | |
366 | struct amdgpu_vm *vm, uint64_t start, | |
367 | struct amdgpu_vm_pt_cursor *cursor) | |
368 | { | |
369 | cursor->pfn = start; | |
370 | cursor->parent = NULL; | |
371 | cursor->entry = &vm->root; | |
372 | cursor->level = adev->vm_manager.root_level; | |
373 | } | |
374 | ||
375 | /** | |
376 | * amdgpu_vm_pt_descendant - go to child node | |
377 | * | |
378 | * @adev: amdgpu_device pointer | |
379 | * @cursor: current state | |
380 | * | |
381 | * Walk to the child node of the current node. | |
382 | * Returns: | |
383 | * True if the walk was possible, false otherwise. | |
384 | */ | |
385 | static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev, | |
386 | struct amdgpu_vm_pt_cursor *cursor) | |
387 | { | |
cb90b97b | 388 | unsigned mask, shift, idx; |
73633e32 CK |
389 | |
390 | if (!cursor->entry->entries) | |
391 | return false; | |
392 | ||
393 | BUG_ON(!cursor->entry->base.bo); | |
cb90b97b | 394 | mask = amdgpu_vm_entries_mask(adev, cursor->level); |
73633e32 CK |
395 | shift = amdgpu_vm_level_shift(adev, cursor->level); |
396 | ||
397 | ++cursor->level; | |
cb90b97b | 398 | idx = (cursor->pfn >> shift) & mask; |
73633e32 CK |
399 | cursor->parent = cursor->entry; |
400 | cursor->entry = &cursor->entry->entries[idx]; | |
401 | return true; | |
402 | } | |
403 | ||
404 | /** | |
405 | * amdgpu_vm_pt_sibling - go to sibling node | |
406 | * | |
407 | * @adev: amdgpu_device pointer | |
408 | * @cursor: current state | |
409 | * | |
410 | * Walk to the sibling node of the current node. | |
411 | * Returns: | |
412 | * True if the walk was possible, false otherwise. | |
413 | */ | |
414 | static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev, | |
415 | struct amdgpu_vm_pt_cursor *cursor) | |
416 | { | |
417 | unsigned shift, num_entries; | |
418 | ||
419 | /* Root doesn't have a sibling */ | |
420 | if (!cursor->parent) | |
421 | return false; | |
422 | ||
423 | /* Go to our parents and see if we got a sibling */ | |
424 | shift = amdgpu_vm_level_shift(adev, cursor->level - 1); | |
425 | num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1); | |
426 | ||
427 | if (cursor->entry == &cursor->parent->entries[num_entries - 1]) | |
428 | return false; | |
429 | ||
430 | cursor->pfn += 1ULL << shift; | |
431 | cursor->pfn &= ~((1ULL << shift) - 1); | |
432 | ++cursor->entry; | |
433 | return true; | |
434 | } | |
435 | ||
436 | /** | |
437 | * amdgpu_vm_pt_ancestor - go to parent node | |
438 | * | |
439 | * @cursor: current state | |
440 | * | |
441 | * Walk to the parent node of the current node. | |
442 | * Returns: | |
443 | * True if the walk was possible, false otherwise. | |
444 | */ | |
445 | static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor) | |
446 | { | |
447 | if (!cursor->parent) | |
448 | return false; | |
449 | ||
450 | --cursor->level; | |
451 | cursor->entry = cursor->parent; | |
452 | cursor->parent = amdgpu_vm_pt_parent(cursor->parent); | |
453 | return true; | |
454 | } | |
455 | ||
456 | /** | |
457 | * amdgpu_vm_pt_next - get next PD/PT in hieratchy | |
458 | * | |
459 | * @adev: amdgpu_device pointer | |
460 | * @cursor: current state | |
461 | * | |
462 | * Walk the PD/PT tree to the next node. | |
463 | */ | |
464 | static void amdgpu_vm_pt_next(struct amdgpu_device *adev, | |
465 | struct amdgpu_vm_pt_cursor *cursor) | |
466 | { | |
467 | /* First try a newborn child */ | |
468 | if (amdgpu_vm_pt_descendant(adev, cursor)) | |
469 | return; | |
470 | ||
471 | /* If that didn't worked try to find a sibling */ | |
472 | while (!amdgpu_vm_pt_sibling(adev, cursor)) { | |
473 | /* No sibling, go to our parents and grandparents */ | |
474 | if (!amdgpu_vm_pt_ancestor(cursor)) { | |
475 | cursor->pfn = ~0ll; | |
476 | return; | |
477 | } | |
478 | } | |
479 | } | |
480 | ||
481 | /** | |
73633e32 | 482 | * amdgpu_vm_pt_first_dfs - start a deep first search |
73633e32 | 483 | * |
73633e32 | 484 | * @adev: amdgpu_device structure |
73633e32 | 485 | * @vm: amdgpu_vm structure |
1d614ded | 486 | * @start: optional cursor to start with |
73633e32 CK |
487 | * @cursor: state to initialize |
488 | * | |
73633e32 | 489 | * Starts a deep first traversal of the PD/PT tree. |
73633e32 | 490 | */ |
73633e32 CK |
491 | static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev, |
492 | struct amdgpu_vm *vm, | |
e35fb064 | 493 | struct amdgpu_vm_pt_cursor *start, |
73633e32 CK |
494 | struct amdgpu_vm_pt_cursor *cursor) |
495 | { | |
e35fb064 CK |
496 | if (start) |
497 | *cursor = *start; | |
498 | else | |
499 | amdgpu_vm_pt_start(adev, vm, 0, cursor); | |
73633e32 | 500 | while (amdgpu_vm_pt_descendant(adev, cursor)); |
73633e32 CK |
501 | } |
502 | ||
503 | /** | |
e35fb064 | 504 | * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue |
73633e32 | 505 | * |
e35fb064 CK |
506 | * @start: starting point for the search |
507 | * @entry: current entry | |
73633e32 | 508 | * |
e35fb064 CK |
509 | * Returns: |
510 | * True when the search should continue, false otherwise. | |
73633e32 | 511 | */ |
e35fb064 CK |
512 | static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start, |
513 | struct amdgpu_vm_pt *entry) | |
73633e32 | 514 | { |
e35fb064 | 515 | return entry && (!start || entry != start->entry); |
73633e32 CK |
516 | } |
517 | ||
518 | /** | |
519 | * amdgpu_vm_pt_next_dfs - get the next node for a deep first search | |
520 | * | |
521 | * @adev: amdgpu_device structure | |
522 | * @cursor: current state | |
523 | * | |
524 | * Move the cursor to the next node in a deep first search. | |
525 | */ | |
526 | static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev, | |
527 | struct amdgpu_vm_pt_cursor *cursor) | |
528 | { | |
529 | if (!cursor->entry) | |
530 | return; | |
531 | ||
532 | if (!cursor->parent) | |
533 | cursor->entry = NULL; | |
534 | else if (amdgpu_vm_pt_sibling(adev, cursor)) | |
535 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
536 | else | |
537 | amdgpu_vm_pt_ancestor(cursor); | |
538 | } | |
539 | ||
1d614ded | 540 | /* |
73633e32 CK |
541 | * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs |
542 | */ | |
e35fb064 CK |
543 | #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \ |
544 | for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \ | |
73633e32 | 545 | (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\ |
e35fb064 CK |
546 | amdgpu_vm_pt_continue_dfs((start), (entry)); \ |
547 | (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor))) | |
73633e32 | 548 | |
d38ceaf9 | 549 | /** |
56467ebf | 550 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
551 | * |
552 | * @vm: vm providing the BOs | |
3c0eea6c | 553 | * @validated: head of validation list |
56467ebf | 554 | * @entry: entry to add |
d38ceaf9 AD |
555 | * |
556 | * Add the page directory to the list of BOs to | |
56467ebf | 557 | * validate for command submission. |
d38ceaf9 | 558 | */ |
56467ebf CK |
559 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
560 | struct list_head *validated, | |
561 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 562 | { |
56467ebf | 563 | entry->priority = 0; |
e83dfe4d | 564 | entry->tv.bo = &vm->root.base.bo->tbo; |
90b69cdc CK |
565 | /* One for TTM and one for the CS job */ |
566 | entry->tv.num_shared = 2; | |
2f568dbd | 567 | entry->user_pages = NULL; |
56467ebf CK |
568 | list_add(&entry->tv.head, validated); |
569 | } | |
d38ceaf9 | 570 | |
fc39d903 CK |
571 | /** |
572 | * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag | |
573 | * | |
574 | * @bo: BO which was removed from the LRU | |
575 | * | |
576 | * Make sure the bulk_moveable flag is updated when a BO is removed from the | |
577 | * LRU. | |
578 | */ | |
b61857b5 CZ |
579 | void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo) |
580 | { | |
581 | struct amdgpu_bo *abo; | |
582 | struct amdgpu_vm_bo_base *bo_base; | |
583 | ||
584 | if (!amdgpu_bo_is_amdgpu_bo(bo)) | |
585 | return; | |
586 | ||
587 | if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT) | |
588 | return; | |
589 | ||
590 | abo = ttm_to_amdgpu_bo(bo); | |
591 | if (!abo->parent) | |
592 | return; | |
593 | for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) { | |
594 | struct amdgpu_vm *vm = bo_base->vm; | |
595 | ||
5a5011a7 | 596 | if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) |
b61857b5 CZ |
597 | vm->bulk_moveable = false; |
598 | } | |
599 | ||
600 | } | |
f921661b HR |
601 | /** |
602 | * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU | |
603 | * | |
604 | * @adev: amdgpu device pointer | |
605 | * @vm: vm providing the BOs | |
606 | * | |
607 | * Move all BOs to the end of LRU and remember their positions to put them | |
608 | * together. | |
609 | */ | |
610 | void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, | |
611 | struct amdgpu_vm *vm) | |
612 | { | |
f921661b HR |
613 | struct amdgpu_vm_bo_base *bo_base; |
614 | ||
615 | if (vm->bulk_moveable) { | |
97588b5b | 616 | spin_lock(&ttm_bo_glob.lru_lock); |
f921661b | 617 | ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move); |
97588b5b | 618 | spin_unlock(&ttm_bo_glob.lru_lock); |
f921661b HR |
619 | return; |
620 | } | |
621 | ||
622 | memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move)); | |
623 | ||
97588b5b | 624 | spin_lock(&ttm_bo_glob.lru_lock); |
f921661b HR |
625 | list_for_each_entry(bo_base, &vm->idle, vm_status) { |
626 | struct amdgpu_bo *bo = bo_base->bo; | |
627 | ||
628 | if (!bo->parent) | |
629 | continue; | |
630 | ||
631 | ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move); | |
632 | if (bo->shadow) | |
633 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo, | |
634 | &vm->lru_bulk_move); | |
635 | } | |
97588b5b | 636 | spin_unlock(&ttm_bo_glob.lru_lock); |
f921661b HR |
637 | |
638 | vm->bulk_moveable = true; | |
639 | } | |
640 | ||
670fecc8 | 641 | /** |
f7da30d9 | 642 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
670fecc8 | 643 | * |
5a712a87 | 644 | * @adev: amdgpu device pointer |
56467ebf | 645 | * @vm: vm providing the BOs |
670fecc8 CK |
646 | * @validate: callback to do the validation |
647 | * @param: parameter for the validation callback | |
648 | * | |
649 | * Validate the page table BOs on command submission if neccessary. | |
7fc48e59 AG |
650 | * |
651 | * Returns: | |
652 | * Validation result. | |
670fecc8 | 653 | */ |
f7da30d9 CK |
654 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
655 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
656 | void *param) | |
670fecc8 | 657 | { |
91ccdd24 | 658 | struct amdgpu_vm_bo_base *bo_base, *tmp; |
b4ff0f8a | 659 | int r; |
670fecc8 | 660 | |
39bbd331 CK |
661 | vm->bulk_moveable &= list_empty(&vm->evicted); |
662 | ||
91ccdd24 CK |
663 | list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { |
664 | struct amdgpu_bo *bo = bo_base->bo; | |
670fecc8 | 665 | |
262b9c39 CK |
666 | r = validate(param, bo); |
667 | if (r) | |
b4ff0f8a | 668 | return r; |
670fecc8 | 669 | |
af4c0f65 | 670 | if (bo->tbo.type != ttm_bo_type_kernel) { |
bcdc9fd6 | 671 | amdgpu_vm_bo_moved(bo_base); |
af4c0f65 | 672 | } else { |
ecf96b52 | 673 | vm->update_funcs->map_table(bo); |
fda43ab6 CK |
674 | if (bo->parent) |
675 | amdgpu_vm_bo_relocated(bo_base); | |
17cc5252 | 676 | else |
fda43ab6 | 677 | amdgpu_vm_bo_idle(bo_base); |
af4c0f65 | 678 | } |
670fecc8 CK |
679 | } |
680 | ||
b4ff0f8a CK |
681 | mutex_lock(&vm->eviction_lock); |
682 | vm->evicting = false; | |
683 | mutex_unlock(&vm->eviction_lock); | |
684 | ||
685 | return 0; | |
670fecc8 CK |
686 | } |
687 | ||
56467ebf | 688 | /** |
34d7be5d | 689 | * amdgpu_vm_ready - check VM is ready for updates |
56467ebf | 690 | * |
34d7be5d | 691 | * @vm: VM to check |
d38ceaf9 | 692 | * |
34d7be5d | 693 | * Check if all VM PDs/PTs are ready for updates |
7fc48e59 AG |
694 | * |
695 | * Returns: | |
696 | * True if eviction list is empty. | |
d38ceaf9 | 697 | */ |
3f3333f8 | 698 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
d38ceaf9 | 699 | { |
af4c0f65 | 700 | return list_empty(&vm->evicted); |
d711e139 CK |
701 | } |
702 | ||
13307f7e CK |
703 | /** |
704 | * amdgpu_vm_clear_bo - initially clear the PDs/PTs | |
705 | * | |
706 | * @adev: amdgpu_device pointer | |
7fc48e59 | 707 | * @vm: VM to clear BO from |
13307f7e | 708 | * @bo: BO to clear |
0f6064d6 | 709 | * @direct: use a direct update |
13307f7e CK |
710 | * |
711 | * Root PD needs to be reserved when calling this. | |
7fc48e59 AG |
712 | * |
713 | * Returns: | |
714 | * 0 on success, errno otherwise. | |
13307f7e CK |
715 | */ |
716 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
780637cb | 717 | struct amdgpu_vm *vm, |
0f6064d6 CK |
718 | struct amdgpu_bo *bo, |
719 | bool direct) | |
13307f7e CK |
720 | { |
721 | struct ttm_operation_ctx ctx = { true, false }; | |
780637cb | 722 | unsigned level = adev->vm_manager.root_level; |
adc7e863 | 723 | struct amdgpu_vm_update_params params; |
780637cb | 724 | struct amdgpu_bo *ancestor = bo; |
4584312d | 725 | unsigned entries, ats_entries; |
4584312d | 726 | uint64_t addr; |
13307f7e CK |
727 | int r; |
728 | ||
780637cb CK |
729 | /* Figure out our place in the hierarchy */ |
730 | if (ancestor->parent) { | |
731 | ++level; | |
732 | while (ancestor->parent->parent) { | |
733 | ++level; | |
734 | ancestor = ancestor->parent; | |
735 | } | |
736 | } | |
737 | ||
4584312d | 738 | entries = amdgpu_bo_size(bo) / 8; |
780637cb CK |
739 | if (!vm->pte_support_ats) { |
740 | ats_entries = 0; | |
4584312d | 741 | |
780637cb CK |
742 | } else if (!bo->parent) { |
743 | ats_entries = amdgpu_vm_num_ats_entries(adev); | |
744 | ats_entries = min(ats_entries, entries); | |
745 | entries -= ats_entries; | |
4584312d | 746 | |
780637cb CK |
747 | } else { |
748 | struct amdgpu_vm_pt *pt; | |
749 | ||
750 | pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base); | |
751 | ats_entries = amdgpu_vm_num_ats_entries(adev); | |
752 | if ((pt - vm->root.entries) >= ats_entries) { | |
753 | ats_entries = 0; | |
4584312d CK |
754 | } else { |
755 | ats_entries = entries; | |
756 | entries = 0; | |
757 | } | |
13307f7e CK |
758 | } |
759 | ||
13307f7e CK |
760 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); |
761 | if (r) | |
83cd8397 | 762 | return r; |
13307f7e | 763 | |
83cd8397 CK |
764 | if (bo->shadow) { |
765 | r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement, | |
766 | &ctx); | |
767 | if (r) | |
768 | return r; | |
83cd8397 CK |
769 | } |
770 | ||
ecf96b52 | 771 | r = vm->update_funcs->map_table(bo); |
284dec43 CK |
772 | if (r) |
773 | return r; | |
774 | ||
adc7e863 CK |
775 | memset(¶ms, 0, sizeof(params)); |
776 | params.adev = adev; | |
777 | params.vm = vm; | |
0f6064d6 | 778 | params.direct = direct; |
adc7e863 CK |
779 | |
780 | r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_KFD, NULL); | |
13307f7e | 781 | if (r) |
83cd8397 | 782 | return r; |
13307f7e | 783 | |
adc7e863 | 784 | addr = 0; |
4584312d | 785 | if (ats_entries) { |
5fa76a9d | 786 | uint64_t value = 0, flags; |
4584312d | 787 | |
5fa76a9d CK |
788 | flags = AMDGPU_PTE_DEFAULT_ATC; |
789 | if (level != AMDGPU_VM_PTB) { | |
790 | /* Handle leaf PDEs as PTEs */ | |
791 | flags |= AMDGPU_PDE_PTE; | |
792 | amdgpu_gmc_get_vm_pde(adev, level, &value, &flags); | |
793 | } | |
4584312d | 794 | |
adc7e863 | 795 | r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries, |
5fa76a9d | 796 | value, flags); |
adc7e863 CK |
797 | if (r) |
798 | return r; | |
13307f7e | 799 | |
4584312d CK |
800 | addr += ats_entries * 8; |
801 | } | |
802 | ||
e95b93ce | 803 | if (entries) { |
b6f3a51e CK |
804 | uint64_t value = 0, flags = 0; |
805 | ||
806 | if (adev->asic_type >= CHIP_VEGA10) { | |
807 | if (level != AMDGPU_VM_PTB) { | |
808 | /* Handle leaf PDEs as PTEs */ | |
809 | flags |= AMDGPU_PDE_PTE; | |
810 | amdgpu_gmc_get_vm_pde(adev, level, | |
811 | &value, &flags); | |
812 | } else { | |
813 | /* Workaround for fault priority problem on GMC9 */ | |
814 | flags = AMDGPU_PTE_EXECUTABLE; | |
815 | } | |
816 | } | |
e95b93ce | 817 | |
adc7e863 | 818 | r = vm->update_funcs->update(¶ms, bo, addr, 0, entries, |
b6f3a51e | 819 | value, flags); |
adc7e863 CK |
820 | if (r) |
821 | return r; | |
e95b93ce | 822 | } |
4584312d | 823 | |
adc7e863 | 824 | return vm->update_funcs->commit(¶ms, NULL); |
13307f7e CK |
825 | } |
826 | ||
e21eb261 CK |
827 | /** |
828 | * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation | |
829 | * | |
830 | * @adev: amdgpu_device pointer | |
831 | * @vm: requesting vm | |
63b2b5e9 AD |
832 | * @level: the page table level |
833 | * @direct: use a direct update | |
e21eb261 CK |
834 | * @bp: resulting BO allocation parameters |
835 | */ | |
836 | static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
061468c4 CK |
837 | int level, bool direct, |
838 | struct amdgpu_bo_param *bp) | |
e21eb261 CK |
839 | { |
840 | memset(bp, 0, sizeof(*bp)); | |
841 | ||
842 | bp->size = amdgpu_vm_bo_size(adev, level); | |
843 | bp->byte_align = AMDGPU_GPU_PAGE_SIZE; | |
844 | bp->domain = AMDGPU_GEM_DOMAIN_VRAM; | |
284dec43 CK |
845 | bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain); |
846 | bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
847 | AMDGPU_GEM_CREATE_CPU_GTT_USWC; | |
e21eb261 CK |
848 | if (vm->use_cpu_for_update) |
849 | bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
03e9dee1 FK |
850 | else if (!vm->root.base.bo || vm->root.base.bo->shadow) |
851 | bp->flags |= AMDGPU_GEM_CREATE_SHADOW; | |
e21eb261 | 852 | bp->type = ttm_bo_type_kernel; |
061468c4 | 853 | bp->no_wait_gpu = direct; |
e21eb261 | 854 | if (vm->root.base.bo) |
5a5011a7 | 855 | bp->resv = vm->root.base.bo->tbo.base.resv; |
e21eb261 CK |
856 | } |
857 | ||
663e4577 | 858 | /** |
98ae7f98 | 859 | * amdgpu_vm_alloc_pts - Allocate a specific page table |
663e4577 CK |
860 | * |
861 | * @adev: amdgpu_device pointer | |
862 | * @vm: VM to allocate page tables for | |
98ae7f98 | 863 | * @cursor: Which page table to allocate |
1d614ded | 864 | * @direct: use a direct update |
663e4577 | 865 | * |
98ae7f98 | 866 | * Make sure a specific page table or directory is allocated. |
7fc48e59 AG |
867 | * |
868 | * Returns: | |
98ae7f98 FK |
869 | * 1 if page table needed to be allocated, 0 if page table was already |
870 | * allocated, negative errno if an error occurred. | |
663e4577 | 871 | */ |
0ce15d6f CK |
872 | static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, |
873 | struct amdgpu_vm *vm, | |
0f6064d6 CK |
874 | struct amdgpu_vm_pt_cursor *cursor, |
875 | bool direct) | |
663e4577 | 876 | { |
0ce15d6f CK |
877 | struct amdgpu_vm_pt *entry = cursor->entry; |
878 | struct amdgpu_bo_param bp; | |
d72a6887 | 879 | struct amdgpu_bo *pt; |
d72a6887 | 880 | int r; |
663e4577 | 881 | |
0ce15d6f CK |
882 | if (cursor->level < AMDGPU_VM_PTB && !entry->entries) { |
883 | unsigned num_entries; | |
663e4577 | 884 | |
0ce15d6f CK |
885 | num_entries = amdgpu_vm_num_entries(adev, cursor->level); |
886 | entry->entries = kvmalloc_array(num_entries, | |
887 | sizeof(*entry->entries), | |
888 | GFP_KERNEL | __GFP_ZERO); | |
889 | if (!entry->entries) | |
890 | return -ENOMEM; | |
4584312d CK |
891 | } |
892 | ||
0ce15d6f CK |
893 | if (entry->base.bo) |
894 | return 0; | |
d72a6887 | 895 | |
061468c4 | 896 | amdgpu_vm_bo_param(adev, vm, cursor->level, direct, &bp); |
d72a6887 | 897 | |
0ce15d6f CK |
898 | r = amdgpu_bo_create(adev, &bp, &pt); |
899 | if (r) | |
900 | return r; | |
d72a6887 | 901 | |
0ce15d6f CK |
902 | /* Keep a reference to the root directory to avoid |
903 | * freeing them up in the wrong order. | |
904 | */ | |
905 | pt->parent = amdgpu_bo_ref(cursor->parent->base.bo); | |
906 | amdgpu_vm_bo_base_init(&entry->base, vm, pt); | |
1e293037 | 907 | |
0f6064d6 | 908 | r = amdgpu_vm_clear_bo(adev, vm, pt, direct); |
0ce15d6f CK |
909 | if (r) |
910 | goto error_free_pt; | |
d72a6887 CK |
911 | |
912 | return 0; | |
913 | ||
914 | error_free_pt: | |
915 | amdgpu_bo_unref(&pt->shadow); | |
916 | amdgpu_bo_unref(&pt); | |
917 | return r; | |
663e4577 CK |
918 | } |
919 | ||
e35fb064 CK |
920 | /** |
921 | * amdgpu_vm_free_table - fre one PD/PT | |
922 | * | |
923 | * @entry: PDE to free | |
924 | */ | |
925 | static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry) | |
926 | { | |
927 | if (entry->base.bo) { | |
928 | entry->base.bo->vm_bo = NULL; | |
929 | list_del(&entry->base.vm_status); | |
930 | amdgpu_bo_unref(&entry->base.bo->shadow); | |
931 | amdgpu_bo_unref(&entry->base.bo); | |
932 | } | |
933 | kvfree(entry->entries); | |
934 | entry->entries = NULL; | |
935 | } | |
936 | ||
229a37f8 CK |
937 | /** |
938 | * amdgpu_vm_free_pts - free PD/PT levels | |
939 | * | |
940 | * @adev: amdgpu device structure | |
769f846e | 941 | * @vm: amdgpu vm structure |
e35fb064 | 942 | * @start: optional cursor where to start freeing PDs/PTs |
229a37f8 CK |
943 | * |
944 | * Free the page directory or page table level and all sub levels. | |
945 | */ | |
946 | static void amdgpu_vm_free_pts(struct amdgpu_device *adev, | |
e35fb064 CK |
947 | struct amdgpu_vm *vm, |
948 | struct amdgpu_vm_pt_cursor *start) | |
229a37f8 CK |
949 | { |
950 | struct amdgpu_vm_pt_cursor cursor; | |
951 | struct amdgpu_vm_pt *entry; | |
952 | ||
e35fb064 | 953 | vm->bulk_moveable = false; |
229a37f8 | 954 | |
e35fb064 CK |
955 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) |
956 | amdgpu_vm_free_table(entry); | |
229a37f8 | 957 | |
e35fb064 CK |
958 | if (start) |
959 | amdgpu_vm_free_table(start->entry); | |
229a37f8 CK |
960 | } |
961 | ||
e59c0205 AX |
962 | /** |
963 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
964 | * | |
965 | * @adev: amdgpu_device pointer | |
966 | */ | |
967 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 968 | { |
a1255107 | 969 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
970 | bool has_compute_vm_bug; |
971 | struct amdgpu_ring *ring; | |
972 | int i; | |
93dcc37d | 973 | |
e59c0205 | 974 | has_compute_vm_bug = false; |
93dcc37d | 975 | |
2990a1fc | 976 | ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); |
e59c0205 AX |
977 | if (ip_block) { |
978 | /* Compute has a VM bug for GFX version < 7. | |
979 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
980 | if (ip_block->version->major <= 7) | |
981 | has_compute_vm_bug = true; | |
982 | else if (ip_block->version->major == 8) | |
983 | if (adev->gfx.mec_fw_version < 673) | |
984 | has_compute_vm_bug = true; | |
985 | } | |
93dcc37d | 986 | |
e59c0205 AX |
987 | for (i = 0; i < adev->num_rings; i++) { |
988 | ring = adev->rings[i]; | |
989 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
990 | /* only compute rings */ | |
991 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 992 | else |
e59c0205 | 993 | ring->has_compute_vm_bug = false; |
93dcc37d | 994 | } |
93dcc37d AD |
995 | } |
996 | ||
7fc48e59 AG |
997 | /** |
998 | * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job. | |
999 | * | |
1000 | * @ring: ring on which the job will be submitted | |
1001 | * @job: job to submit | |
1002 | * | |
1003 | * Returns: | |
1004 | * True if sync is needed. | |
1005 | */ | |
b9bf33d5 CZ |
1006 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
1007 | struct amdgpu_job *job) | |
e60f8db5 | 1008 | { |
b9bf33d5 CZ |
1009 | struct amdgpu_device *adev = ring->adev; |
1010 | unsigned vmhub = ring->funcs->vmhub; | |
620f774f CK |
1011 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
1012 | struct amdgpu_vmid *id; | |
b9bf33d5 | 1013 | bool gds_switch_needed; |
e59c0205 | 1014 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 | 1015 | |
c4f46f22 | 1016 | if (job->vmid == 0) |
b9bf33d5 | 1017 | return false; |
c4f46f22 | 1018 | id = &id_mgr->ids[job->vmid]; |
b9bf33d5 CZ |
1019 | gds_switch_needed = ring->funcs->emit_gds_switch && ( |
1020 | id->gds_base != job->gds_base || | |
1021 | id->gds_size != job->gds_size || | |
1022 | id->gws_base != job->gws_base || | |
1023 | id->gws_size != job->gws_size || | |
1024 | id->oa_base != job->oa_base || | |
1025 | id->oa_size != job->oa_size); | |
e60f8db5 | 1026 | |
620f774f | 1027 | if (amdgpu_vmid_had_gpu_reset(adev, id)) |
b9bf33d5 | 1028 | return true; |
e60f8db5 | 1029 | |
bb37b67d | 1030 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
1031 | } |
1032 | ||
d38ceaf9 AD |
1033 | /** |
1034 | * amdgpu_vm_flush - hardware flush the vm | |
1035 | * | |
1036 | * @ring: ring to use for flush | |
00553cf8 | 1037 | * @job: related job |
7fc48e59 | 1038 | * @need_pipe_sync: is pipe sync needed |
d38ceaf9 | 1039 | * |
4ff37a83 | 1040 | * Emit a VM flush when it is necessary. |
7fc48e59 AG |
1041 | * |
1042 | * Returns: | |
1043 | * 0 on success, errno otherwise. | |
d38ceaf9 | 1044 | */ |
fc39d903 CK |
1045 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, |
1046 | bool need_pipe_sync) | |
d38ceaf9 | 1047 | { |
971fe9a9 | 1048 | struct amdgpu_device *adev = ring->adev; |
7645670d | 1049 | unsigned vmhub = ring->funcs->vmhub; |
620f774f | 1050 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
c4f46f22 | 1051 | struct amdgpu_vmid *id = &id_mgr->ids[job->vmid]; |
d564a06e | 1052 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
1053 | id->gds_base != job->gds_base || |
1054 | id->gds_size != job->gds_size || | |
1055 | id->gws_base != job->gws_base || | |
1056 | id->gws_size != job->gws_size || | |
1057 | id->oa_base != job->oa_base || | |
1058 | id->oa_size != job->oa_size); | |
de37e68a | 1059 | bool vm_flush_needed = job->vm_needs_flush; |
b3cd285f | 1060 | struct dma_fence *fence = NULL; |
17cf678a | 1061 | bool pasid_mapping_needed = false; |
c0e51931 | 1062 | unsigned patch_offset = 0; |
41d9eb2c | 1063 | int r; |
d564a06e | 1064 | |
620f774f | 1065 | if (amdgpu_vmid_had_gpu_reset(adev, id)) { |
f7d015b9 CK |
1066 | gds_switch_needed = true; |
1067 | vm_flush_needed = true; | |
b3cd285f | 1068 | pasid_mapping_needed = true; |
f7d015b9 | 1069 | } |
971fe9a9 | 1070 | |
6817bf28 CK |
1071 | mutex_lock(&id_mgr->lock); |
1072 | if (id->pasid != job->pasid || !id->pasid_mapping || | |
1073 | !dma_fence_is_signaled(id->pasid_mapping)) | |
1074 | pasid_mapping_needed = true; | |
1075 | mutex_unlock(&id_mgr->lock); | |
1076 | ||
b3cd285f | 1077 | gds_switch_needed &= !!ring->funcs->emit_gds_switch; |
d8de8260 AG |
1078 | vm_flush_needed &= !!ring->funcs->emit_vm_flush && |
1079 | job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET; | |
b3cd285f CK |
1080 | pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping && |
1081 | ring->funcs->emit_wreg; | |
1082 | ||
8fdf074f | 1083 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 1084 | return 0; |
41d9eb2c | 1085 | |
c0e51931 CK |
1086 | if (ring->funcs->init_cond_exec) |
1087 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 1088 | |
8fdf074f ML |
1089 | if (need_pipe_sync) |
1090 | amdgpu_ring_emit_pipeline_sync(ring); | |
1091 | ||
b3cd285f | 1092 | if (vm_flush_needed) { |
c4f46f22 | 1093 | trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr); |
c633c00b | 1094 | amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr); |
b3cd285f CK |
1095 | } |
1096 | ||
1097 | if (pasid_mapping_needed) | |
1098 | amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); | |
e9d672b2 | 1099 | |
b3cd285f | 1100 | if (vm_flush_needed || pasid_mapping_needed) { |
d240cd9e | 1101 | r = amdgpu_fence_emit(ring, &fence, 0); |
c0e51931 CK |
1102 | if (r) |
1103 | return r; | |
b3cd285f | 1104 | } |
e9d672b2 | 1105 | |
b3cd285f | 1106 | if (vm_flush_needed) { |
7645670d | 1107 | mutex_lock(&id_mgr->lock); |
c0e51931 | 1108 | dma_fence_put(id->last_flush); |
b3cd285f CK |
1109 | id->last_flush = dma_fence_get(fence); |
1110 | id->current_gpu_reset_count = | |
1111 | atomic_read(&adev->gpu_reset_counter); | |
7645670d | 1112 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 1113 | } |
e9d672b2 | 1114 | |
b3cd285f | 1115 | if (pasid_mapping_needed) { |
6817bf28 | 1116 | mutex_lock(&id_mgr->lock); |
b3cd285f CK |
1117 | id->pasid = job->pasid; |
1118 | dma_fence_put(id->pasid_mapping); | |
1119 | id->pasid_mapping = dma_fence_get(fence); | |
6817bf28 | 1120 | mutex_unlock(&id_mgr->lock); |
b3cd285f CK |
1121 | } |
1122 | dma_fence_put(fence); | |
1123 | ||
7c4378f4 | 1124 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
1125 | id->gds_base = job->gds_base; |
1126 | id->gds_size = job->gds_size; | |
1127 | id->gws_base = job->gws_base; | |
1128 | id->gws_size = job->gws_size; | |
1129 | id->oa_base = job->oa_base; | |
1130 | id->oa_size = job->oa_size; | |
c4f46f22 | 1131 | amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base, |
c0e51931 CK |
1132 | job->gds_size, job->gws_base, |
1133 | job->gws_size, job->oa_base, | |
1134 | job->oa_size); | |
1135 | } | |
1136 | ||
1137 | if (ring->funcs->patch_cond_exec) | |
1138 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
1139 | ||
1140 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
1141 | if (ring->funcs->emit_switch_buffer) { | |
1142 | amdgpu_ring_emit_switch_buffer(ring); | |
1143 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 1144 | } |
41d9eb2c | 1145 | return 0; |
971fe9a9 CK |
1146 | } |
1147 | ||
d38ceaf9 AD |
1148 | /** |
1149 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
1150 | * | |
1151 | * @vm: requested vm | |
1152 | * @bo: requested buffer object | |
1153 | * | |
8843dbbb | 1154 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
1155 | * Search inside the @bos vm list for the requested vm |
1156 | * Returns the found bo_va or NULL if none is found | |
1157 | * | |
1158 | * Object has to be reserved! | |
7fc48e59 AG |
1159 | * |
1160 | * Returns: | |
1161 | * Found bo_va or NULL. | |
d38ceaf9 AD |
1162 | */ |
1163 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
1164 | struct amdgpu_bo *bo) | |
1165 | { | |
646b9025 | 1166 | struct amdgpu_vm_bo_base *base; |
d38ceaf9 | 1167 | |
646b9025 CK |
1168 | for (base = bo->vm_bo; base; base = base->next) { |
1169 | if (base->vm != vm) | |
1170 | continue; | |
1171 | ||
1172 | return container_of(base, struct amdgpu_bo_va, base); | |
d38ceaf9 AD |
1173 | } |
1174 | return NULL; | |
1175 | } | |
1176 | ||
d38ceaf9 | 1177 | /** |
b07c9d2a | 1178 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 1179 | * |
b07c9d2a | 1180 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
1181 | * @addr: the unmapped addr |
1182 | * | |
1183 | * Look up the physical address of the page that the pte resolves | |
7fc48e59 AG |
1184 | * to. |
1185 | * | |
1186 | * Returns: | |
1187 | * The pointer for the page table entry. | |
d38ceaf9 | 1188 | */ |
6dd09027 | 1189 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
1190 | { |
1191 | uint64_t result; | |
1192 | ||
de9ea7bd CK |
1193 | /* page table offset */ |
1194 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 1195 | |
de9ea7bd CK |
1196 | /* in case cpu page size != gpu page size*/ |
1197 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 1198 | |
b07c9d2a | 1199 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
1200 | |
1201 | return result; | |
1202 | } | |
1203 | ||
1d614ded | 1204 | /** |
6989f246 | 1205 | * amdgpu_vm_update_pde - update a single level in the hierarchy |
f8991bab | 1206 | * |
1d614ded | 1207 | * @params: parameters for the update |
f8991bab | 1208 | * @vm: requested vm |
6989f246 | 1209 | * @entry: entry to update |
f8991bab | 1210 | * |
6989f246 | 1211 | * Makes sure the requested entry in parent is up to date. |
f8991bab | 1212 | */ |
e6899d55 CK |
1213 | static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params, |
1214 | struct amdgpu_vm *vm, | |
e6899d55 | 1215 | struct amdgpu_vm_pt *entry) |
d38ceaf9 | 1216 | { |
fda43ab6 | 1217 | struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry); |
373ac645 | 1218 | struct amdgpu_bo *bo = parent->base.bo, *pbo; |
3de676d8 CK |
1219 | uint64_t pde, pt, flags; |
1220 | unsigned level; | |
d5fc5e82 | 1221 | |
373ac645 | 1222 | for (level = 0, pbo = bo->parent; pbo; ++level) |
3de676d8 CK |
1223 | pbo = pbo->parent; |
1224 | ||
196f7489 | 1225 | level += params->adev->vm_manager.root_level; |
24a8d289 | 1226 | amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags); |
373ac645 | 1227 | pde = (entry - parent->entries) * 8; |
e6899d55 | 1228 | return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags); |
d38ceaf9 AD |
1229 | } |
1230 | ||
1d614ded | 1231 | /** |
d4085ea9 | 1232 | * amdgpu_vm_invalidate_pds - mark all PDs as invalid |
92456b93 | 1233 | * |
7fc48e59 AG |
1234 | * @adev: amdgpu_device pointer |
1235 | * @vm: related vm | |
92456b93 CK |
1236 | * |
1237 | * Mark all PD level as invalid after an error. | |
1238 | */ | |
d4085ea9 CK |
1239 | static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev, |
1240 | struct amdgpu_vm *vm) | |
92456b93 | 1241 | { |
d4085ea9 CK |
1242 | struct amdgpu_vm_pt_cursor cursor; |
1243 | struct amdgpu_vm_pt *entry; | |
92456b93 | 1244 | |
e35fb064 | 1245 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry) |
d4085ea9 | 1246 | if (entry->base.bo && !entry->base.moved) |
bcdc9fd6 | 1247 | amdgpu_vm_bo_relocated(&entry->base); |
92456b93 CK |
1248 | } |
1249 | ||
1d614ded | 1250 | /** |
807e2994 | 1251 | * amdgpu_vm_update_pdes - make sure that all directories are valid |
194d2161 CK |
1252 | * |
1253 | * @adev: amdgpu_device pointer | |
1254 | * @vm: requested vm | |
807e2994 | 1255 | * @direct: submit directly to the paging queue |
194d2161 CK |
1256 | * |
1257 | * Makes sure all directories are up to date. | |
7fc48e59 AG |
1258 | * |
1259 | * Returns: | |
1260 | * 0 for success, error for failure. | |
194d2161 | 1261 | */ |
807e2994 CK |
1262 | int amdgpu_vm_update_pdes(struct amdgpu_device *adev, |
1263 | struct amdgpu_vm *vm, bool direct) | |
194d2161 | 1264 | { |
d1e29462 | 1265 | struct amdgpu_vm_update_params params; |
e6899d55 | 1266 | int r; |
92456b93 | 1267 | |
6989f246 CK |
1268 | if (list_empty(&vm->relocated)) |
1269 | return 0; | |
1270 | ||
6989f246 CK |
1271 | memset(¶ms, 0, sizeof(params)); |
1272 | params.adev = adev; | |
e6899d55 | 1273 | params.vm = vm; |
807e2994 | 1274 | params.direct = direct; |
6989f246 | 1275 | |
e6899d55 CK |
1276 | r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_VM, NULL); |
1277 | if (r) | |
1278 | return r; | |
6989f246 | 1279 | |
ea09729c | 1280 | while (!list_empty(&vm->relocated)) { |
fda43ab6 | 1281 | struct amdgpu_vm_pt *entry; |
ea09729c | 1282 | |
ba79fde4 CK |
1283 | entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt, |
1284 | base.vm_status); | |
1285 | amdgpu_vm_bo_idle(&entry->base); | |
ea09729c | 1286 | |
fda43ab6 | 1287 | r = amdgpu_vm_update_pde(¶ms, vm, entry); |
6989f246 CK |
1288 | if (r) |
1289 | goto error; | |
68c62306 CK |
1290 | } |
1291 | ||
e6899d55 CK |
1292 | r = vm->update_funcs->commit(¶ms, &vm->last_update); |
1293 | if (r) | |
1294 | goto error; | |
6989f246 CK |
1295 | return 0; |
1296 | ||
1297 | error: | |
d4085ea9 | 1298 | amdgpu_vm_invalidate_pds(adev, vm); |
92456b93 | 1299 | return r; |
194d2161 CK |
1300 | } |
1301 | ||
1d614ded | 1302 | /* |
e95b93ce | 1303 | * amdgpu_vm_update_flags - figure out flags for PTE updates |
cf2f0a37 | 1304 | * |
dfcd99f6 | 1305 | * Make sure to set the right flags for the PTEs at the desired level. |
cf2f0a37 | 1306 | */ |
d1e29462 | 1307 | static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params, |
e95b93ce CK |
1308 | struct amdgpu_bo *bo, unsigned level, |
1309 | uint64_t pe, uint64_t addr, | |
1310 | unsigned count, uint32_t incr, | |
1311 | uint64_t flags) | |
cf2f0a37 | 1312 | |
dfcd99f6 CK |
1313 | { |
1314 | if (level != AMDGPU_VM_PTB) { | |
cf2f0a37 | 1315 | flags |= AMDGPU_PDE_PTE; |
dfcd99f6 | 1316 | amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags); |
e95b93ce CK |
1317 | |
1318 | } else if (params->adev->asic_type >= CHIP_VEGA10 && | |
1319 | !(flags & AMDGPU_PTE_VALID) && | |
1320 | !(flags & AMDGPU_PTE_PRT)) { | |
1321 | ||
1322 | /* Workaround for fault priority problem on GMC9 */ | |
1323 | flags |= AMDGPU_PTE_EXECUTABLE; | |
cf2f0a37 AD |
1324 | } |
1325 | ||
c3546695 CK |
1326 | params->vm->update_funcs->update(params, bo, pe, addr, count, incr, |
1327 | flags); | |
dfcd99f6 CK |
1328 | } |
1329 | ||
1330 | /** | |
1331 | * amdgpu_vm_fragment - get fragment for PTEs | |
1332 | * | |
d1e29462 | 1333 | * @params: see amdgpu_vm_update_params definition |
dfcd99f6 CK |
1334 | * @start: first PTE to handle |
1335 | * @end: last PTE to handle | |
1336 | * @flags: hw mapping flags | |
1337 | * @frag: resulting fragment size | |
1338 | * @frag_end: end of this fragment | |
1339 | * | |
1340 | * Returns the first possible fragment for the start and end address. | |
1341 | */ | |
d1e29462 | 1342 | static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params, |
dfcd99f6 CK |
1343 | uint64_t start, uint64_t end, uint64_t flags, |
1344 | unsigned int *frag, uint64_t *frag_end) | |
1345 | { | |
1346 | /** | |
1347 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1348 | * field in the PTE. When this field is set to a non-zero value, page | |
1349 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1350 | * flags are considered valid for all PTEs within the fragment range | |
1351 | * and corresponding mappings are assumed to be physically contiguous. | |
1352 | * | |
1353 | * The L1 TLB can store a single PTE for the whole fragment, | |
1354 | * significantly increasing the space available for translation | |
1355 | * caching. This leads to large improvements in throughput when the | |
1356 | * TLB is under pressure. | |
1357 | * | |
1358 | * The L2 TLB distributes small and large fragments into two | |
1359 | * asymmetric partitions. The large fragment cache is significantly | |
1360 | * larger. Thus, we try to use large fragments wherever possible. | |
1361 | * Userspace can support this by aligning virtual base address and | |
1362 | * allocation size to the fragment size. | |
1b1d5c43 CK |
1363 | * |
1364 | * Starting with Vega10 the fragment size only controls the L1. The L2 | |
1365 | * is now directly feed with small/huge/giant pages from the walker. | |
dfcd99f6 | 1366 | */ |
1b1d5c43 CK |
1367 | unsigned max_frag; |
1368 | ||
1369 | if (params->adev->asic_type < CHIP_VEGA10) | |
1370 | max_frag = params->adev->vm_manager.fragment_size; | |
1371 | else | |
1372 | max_frag = 31; | |
dfcd99f6 CK |
1373 | |
1374 | /* system pages are non continuously */ | |
072b7a0b | 1375 | if (params->pages_addr) { |
dfcd99f6 CK |
1376 | *frag = 0; |
1377 | *frag_end = end; | |
ec5207c9 | 1378 | return; |
3cc1d3ea | 1379 | } |
cf2f0a37 | 1380 | |
dfcd99f6 CK |
1381 | /* This intentionally wraps around if no bit is set */ |
1382 | *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1); | |
1383 | if (*frag >= max_frag) { | |
1384 | *frag = max_frag; | |
1385 | *frag_end = end & ~((1ULL << max_frag) - 1); | |
1386 | } else { | |
1387 | *frag_end = start + (1 << *frag); | |
1388 | } | |
4e2cb640 CK |
1389 | } |
1390 | ||
d38ceaf9 AD |
1391 | /** |
1392 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1393 | * | |
d1e29462 | 1394 | * @params: see amdgpu_vm_update_params definition |
d38ceaf9 AD |
1395 | * @start: start of GPU address range |
1396 | * @end: end of GPU address range | |
677131a1 | 1397 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1398 | * @flags: mapping flags |
1399 | * | |
8843dbbb | 1400 | * Update the page tables in the range @start - @end. |
7fc48e59 AG |
1401 | * |
1402 | * Returns: | |
1403 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 | 1404 | */ |
d1e29462 | 1405 | static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, |
dfcd99f6 CK |
1406 | uint64_t start, uint64_t end, |
1407 | uint64_t dst, uint64_t flags) | |
d38ceaf9 | 1408 | { |
36b32a68 | 1409 | struct amdgpu_device *adev = params->adev; |
dfa70550 | 1410 | struct amdgpu_vm_pt_cursor cursor; |
dfcd99f6 CK |
1411 | uint64_t frag_start = start, frag_end; |
1412 | unsigned int frag; | |
0ce15d6f | 1413 | int r; |
dfcd99f6 CK |
1414 | |
1415 | /* figure out the initial fragment */ | |
1416 | amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end); | |
d38ceaf9 | 1417 | |
dfcd99f6 CK |
1418 | /* walk over the address space and update the PTs */ |
1419 | amdgpu_vm_pt_start(adev, params->vm, start, &cursor); | |
1420 | while (cursor.pfn < end) { | |
cb90b97b | 1421 | unsigned shift, parent_shift, mask; |
dfcd99f6 | 1422 | uint64_t incr, entry_end, pe_start; |
0ce15d6f | 1423 | struct amdgpu_bo *pt; |
cf2f0a37 | 1424 | |
8863baef AD |
1425 | /* make sure that the page tables covering the address range are |
1426 | * actually allocated | |
1427 | */ | |
0f6064d6 CK |
1428 | r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor, |
1429 | params->direct); | |
adc7e863 | 1430 | if (r) |
0ce15d6f CK |
1431 | return r; |
1432 | ||
1433 | pt = cursor.entry->base.bo; | |
4e2cb640 | 1434 | |
dfcd99f6 CK |
1435 | /* The root level can't be a huge page */ |
1436 | if (cursor.level == adev->vm_manager.root_level) { | |
1437 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1438 | return -ENOENT; | |
cf2f0a37 | 1439 | continue; |
dfa70550 | 1440 | } |
cf2f0a37 | 1441 | |
dfcd99f6 CK |
1442 | shift = amdgpu_vm_level_shift(adev, cursor.level); |
1443 | parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1); | |
8ce1f7e7 CK |
1444 | if (adev->asic_type < CHIP_VEGA10 && |
1445 | (flags & AMDGPU_PTE_VALID)) { | |
dfcd99f6 CK |
1446 | /* No huge page support before GMC v9 */ |
1447 | if (cursor.level != AMDGPU_VM_PTB) { | |
1448 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1449 | return -ENOENT; | |
1450 | continue; | |
1451 | } | |
1452 | } else if (frag < shift) { | |
1453 | /* We can't use this level when the fragment size is | |
1454 | * smaller than the address shift. Go to the next | |
1455 | * child entry and try again. | |
1456 | */ | |
1457 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1458 | return -ENOENT; | |
1459 | continue; | |
1954db15 FK |
1460 | } else if (frag >= parent_shift && |
1461 | cursor.level - 1 != adev->vm_manager.root_level) { | |
dfcd99f6 | 1462 | /* If the fragment size is even larger than the parent |
1954db15 FK |
1463 | * shift we should go up one level and check it again |
1464 | * unless one level up is the root level. | |
dfcd99f6 CK |
1465 | */ |
1466 | if (!amdgpu_vm_pt_ancestor(&cursor)) | |
1467 | return -ENOENT; | |
1468 | continue; | |
6849d47c RH |
1469 | } |
1470 | ||
dfcd99f6 | 1471 | /* Looks good so far, calculate parameters for the update */ |
9ce2b991 | 1472 | incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift; |
cb90b97b CK |
1473 | mask = amdgpu_vm_entries_mask(adev, cursor.level); |
1474 | pe_start = ((cursor.pfn >> shift) & mask) * 8; | |
9ce2b991 | 1475 | entry_end = (uint64_t)(mask + 1) << shift; |
dfcd99f6 CK |
1476 | entry_end += cursor.pfn & ~(entry_end - 1); |
1477 | entry_end = min(entry_end, end); | |
1478 | ||
1479 | do { | |
1480 | uint64_t upd_end = min(entry_end, frag_end); | |
1481 | unsigned nptes = (upd_end - frag_start) >> shift; | |
1482 | ||
e95b93ce CK |
1483 | amdgpu_vm_update_flags(params, pt, cursor.level, |
1484 | pe_start, dst, nptes, incr, | |
1485 | flags | AMDGPU_PTE_FRAG(frag)); | |
dfcd99f6 CK |
1486 | |
1487 | pe_start += nptes * 8; | |
9ce2b991 | 1488 | dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift; |
dfcd99f6 CK |
1489 | |
1490 | frag_start = upd_end; | |
1491 | if (frag_start >= frag_end) { | |
1492 | /* figure out the next fragment */ | |
1493 | amdgpu_vm_fragment(params, frag_start, end, | |
1494 | flags, &frag, &frag_end); | |
1495 | if (frag < shift) | |
1496 | break; | |
1497 | } | |
1498 | } while (frag_start < entry_end); | |
92696dd5 | 1499 | |
c1a17777 | 1500 | if (amdgpu_vm_pt_descendant(adev, &cursor)) { |
8863baef AD |
1501 | /* Free all child entries. |
1502 | * Update the tables with the flags and addresses and free up subsequent | |
1503 | * tables in the case of huge pages or freed up areas. | |
1504 | * This is the maximum you can free, because all other page tables are not | |
1505 | * completely covered by the range and so potentially still in use. | |
1506 | */ | |
c1a17777 | 1507 | while (cursor.pfn < frag_start) { |
e35fb064 | 1508 | amdgpu_vm_free_pts(adev, params->vm, &cursor); |
c1a17777 CK |
1509 | amdgpu_vm_pt_next(adev, &cursor); |
1510 | } | |
1511 | ||
1512 | } else if (frag >= shift) { | |
1513 | /* or just move on to the next on the same level. */ | |
dfcd99f6 | 1514 | amdgpu_vm_pt_next(adev, &cursor); |
c1a17777 | 1515 | } |
92696dd5 | 1516 | } |
6849d47c RH |
1517 | |
1518 | return 0; | |
d38ceaf9 AD |
1519 | } |
1520 | ||
d38ceaf9 AD |
1521 | /** |
1522 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1523 | * | |
1524 | * @adev: amdgpu_device pointer | |
1525 | * @vm: requested vm | |
acb476f5 CK |
1526 | * @direct: direct submission in a page fault |
1527 | * @exclusive: fence we need to sync to | |
a14faa65 CK |
1528 | * @start: start of mapped range |
1529 | * @last: last mapped entry | |
1530 | * @flags: flags for the entries | |
d38ceaf9 | 1531 | * @addr: addr to set the area to |
acb476f5 | 1532 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 AD |
1533 | * @fence: optional resulting fence |
1534 | * | |
a14faa65 | 1535 | * Fill in the page table entries between @start and @last. |
7fc48e59 AG |
1536 | * |
1537 | * Returns: | |
1538 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1539 | */ |
1540 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
acb476f5 | 1541 | struct amdgpu_vm *vm, bool direct, |
f54d1867 | 1542 | struct dma_fence *exclusive, |
a14faa65 | 1543 | uint64_t start, uint64_t last, |
6b777607 | 1544 | uint64_t flags, uint64_t addr, |
acb476f5 | 1545 | dma_addr_t *pages_addr, |
f54d1867 | 1546 | struct dma_fence **fence) |
d38ceaf9 | 1547 | { |
d1e29462 | 1548 | struct amdgpu_vm_update_params params; |
a1e08d3b | 1549 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 AD |
1550 | int r; |
1551 | ||
afef8b8f CK |
1552 | memset(¶ms, 0, sizeof(params)); |
1553 | params.adev = adev; | |
49ac8a24 | 1554 | params.vm = vm; |
acb476f5 | 1555 | params.direct = direct; |
072b7a0b | 1556 | params.pages_addr = pages_addr; |
afef8b8f | 1557 | |
8db588d5 | 1558 | /* sync to everything except eviction fences on unmapping */ |
a33cab7a | 1559 | if (!(flags & AMDGPU_PTE_VALID)) |
8db588d5 | 1560 | owner = AMDGPU_FENCE_OWNER_KFD; |
a33cab7a | 1561 | |
b4ff0f8a CK |
1562 | mutex_lock(&vm->eviction_lock); |
1563 | if (vm->evicting) { | |
1564 | r = -EBUSY; | |
1565 | goto error_unlock; | |
1566 | } | |
1567 | ||
c3546695 | 1568 | r = vm->update_funcs->prepare(¶ms, owner, exclusive); |
d71518b5 | 1569 | if (r) |
b4ff0f8a | 1570 | goto error_unlock; |
d71518b5 | 1571 | |
dfcd99f6 | 1572 | r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags); |
cc28c4ed | 1573 | if (r) |
b4ff0f8a | 1574 | goto error_unlock; |
d5fc5e82 | 1575 | |
b4ff0f8a CK |
1576 | r = vm->update_funcs->commit(¶ms, fence); |
1577 | ||
1578 | error_unlock: | |
1579 | mutex_unlock(&vm->eviction_lock); | |
1580 | return r; | |
d38ceaf9 AD |
1581 | } |
1582 | ||
a14faa65 CK |
1583 | /** |
1584 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1585 | * | |
1586 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1587 | * @exclusive: fence we need to sync to |
8358dcee | 1588 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1589 | * @vm: requested vm |
1590 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1591 | * @flags: HW flags for the mapping |
a690aa0f | 1592 | * @bo_adev: amdgpu_device pointer that bo actually been allocated |
63e0ba40 | 1593 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1594 | * @fence: optional resulting fence |
1595 | * | |
1596 | * Split the mapping into smaller chunks so that each update fits | |
1597 | * into a SDMA IB. | |
7fc48e59 AG |
1598 | * |
1599 | * Returns: | |
1600 | * 0 for success, -EINVAL for failure. | |
a14faa65 CK |
1601 | */ |
1602 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1603 | struct dma_fence *exclusive, |
8358dcee | 1604 | dma_addr_t *pages_addr, |
a14faa65 CK |
1605 | struct amdgpu_vm *vm, |
1606 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1607 | uint64_t flags, |
a690aa0f | 1608 | struct amdgpu_device *bo_adev, |
63e0ba40 | 1609 | struct drm_mm_node *nodes, |
f54d1867 | 1610 | struct dma_fence **fence) |
a14faa65 | 1611 | { |
9fc8fc70 | 1612 | unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; |
570144c6 | 1613 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1614 | int r; |
1615 | ||
1616 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1617 | * but in case of something, we filter the flags in first place | |
1618 | */ | |
1619 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1620 | flags &= ~AMDGPU_PTE_READABLE; | |
1621 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1622 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1623 | ||
cbfae36c CK |
1624 | /* Apply ASIC specific mapping flags */ |
1625 | amdgpu_gmc_get_vm_pte(adev, mapping, &flags); | |
d0766e98 | 1626 | |
a14faa65 CK |
1627 | trace_amdgpu_vm_bo_update(mapping); |
1628 | ||
63e0ba40 CK |
1629 | pfn = mapping->offset >> PAGE_SHIFT; |
1630 | if (nodes) { | |
1631 | while (pfn >= nodes->size) { | |
1632 | pfn -= nodes->size; | |
1633 | ++nodes; | |
1634 | } | |
fa3ab3c7 | 1635 | } |
a14faa65 | 1636 | |
63e0ba40 | 1637 | do { |
9fc8fc70 | 1638 | dma_addr_t *dma_addr = NULL; |
63e0ba40 CK |
1639 | uint64_t max_entries; |
1640 | uint64_t addr, last; | |
a14faa65 | 1641 | |
63e0ba40 CK |
1642 | if (nodes) { |
1643 | addr = nodes->start << PAGE_SHIFT; | |
1644 | max_entries = (nodes->size - pfn) * | |
463d2fe8 | 1645 | AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1646 | } else { |
1647 | addr = 0; | |
1648 | max_entries = S64_MAX; | |
1649 | } | |
a14faa65 | 1650 | |
63e0ba40 | 1651 | if (pages_addr) { |
9fc8fc70 CK |
1652 | uint64_t count; |
1653 | ||
38e624a1 | 1654 | for (count = 1; |
463d2fe8 | 1655 | count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
38e624a1 | 1656 | ++count) { |
9fc8fc70 CK |
1657 | uint64_t idx = pfn + count; |
1658 | ||
1659 | if (pages_addr[idx] != | |
1660 | (pages_addr[idx - 1] + PAGE_SIZE)) | |
1661 | break; | |
1662 | } | |
1663 | ||
1664 | if (count < min_linear_pages) { | |
1665 | addr = pfn << PAGE_SHIFT; | |
1666 | dma_addr = pages_addr; | |
1667 | } else { | |
1668 | addr = pages_addr[pfn]; | |
fc39d903 CK |
1669 | max_entries = count * |
1670 | AMDGPU_GPU_PAGES_IN_CPU_PAGE; | |
9fc8fc70 CK |
1671 | } |
1672 | ||
63e0ba40 | 1673 | } else if (flags & AMDGPU_PTE_VALID) { |
a690aa0f | 1674 | addr += bo_adev->vm_manager.vram_base_offset; |
9fc8fc70 | 1675 | addr += pfn << PAGE_SHIFT; |
63e0ba40 | 1676 | } |
63e0ba40 | 1677 | |
a9f87f64 | 1678 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
acb476f5 | 1679 | r = amdgpu_vm_bo_update_mapping(adev, vm, false, exclusive, |
a14faa65 | 1680 | start, last, flags, addr, |
acb476f5 | 1681 | dma_addr, fence); |
a14faa65 CK |
1682 | if (r) |
1683 | return r; | |
1684 | ||
463d2fe8 | 1685 | pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1686 | if (nodes && nodes->size == pfn) { |
1687 | pfn = 0; | |
1688 | ++nodes; | |
1689 | } | |
a14faa65 | 1690 | start = last + 1; |
63e0ba40 | 1691 | |
a9f87f64 | 1692 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1693 | |
1694 | return 0; | |
1695 | } | |
1696 | ||
d38ceaf9 AD |
1697 | /** |
1698 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1699 | * | |
1700 | * @adev: amdgpu_device pointer | |
1701 | * @bo_va: requested BO and VM object | |
99e124f4 | 1702 | * @clear: if true clear the entries |
d38ceaf9 AD |
1703 | * |
1704 | * Fill in the page table entries for @bo_va. | |
7fc48e59 AG |
1705 | * |
1706 | * Returns: | |
1707 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 | 1708 | */ |
fc39d903 | 1709 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, |
99e124f4 | 1710 | bool clear) |
d38ceaf9 | 1711 | { |
ec681545 CK |
1712 | struct amdgpu_bo *bo = bo_va->base.bo; |
1713 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1714 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1715 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 1716 | struct ttm_mem_reg *mem; |
63e0ba40 | 1717 | struct drm_mm_node *nodes; |
4e55eb38 | 1718 | struct dma_fence *exclusive, **last_update; |
457e0fee | 1719 | uint64_t flags; |
86f7bae5 | 1720 | struct amdgpu_device *bo_adev = adev; |
d38ceaf9 AD |
1721 | int r; |
1722 | ||
7eb80427 | 1723 | if (clear || !bo) { |
99e124f4 | 1724 | mem = NULL; |
63e0ba40 | 1725 | nodes = NULL; |
99e124f4 CK |
1726 | exclusive = NULL; |
1727 | } else { | |
8358dcee CK |
1728 | struct ttm_dma_tt *ttm; |
1729 | ||
7eb80427 | 1730 | mem = &bo->tbo.mem; |
63e0ba40 CK |
1731 | nodes = mem->mm_node; |
1732 | if (mem->mem_type == TTM_PL_TT) { | |
7eb80427 | 1733 | ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm); |
8358dcee | 1734 | pages_addr = ttm->dma_address; |
9ab21462 | 1735 | } |
629be203 | 1736 | exclusive = bo->tbo.moving; |
d38ceaf9 AD |
1737 | } |
1738 | ||
a690aa0f | 1739 | if (bo) { |
ec681545 | 1740 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
a690aa0f | 1741 | bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); |
1742 | } else { | |
a5f6b5b1 | 1743 | flags = 0x0; |
a690aa0f | 1744 | } |
d38ceaf9 | 1745 | |
5a5011a7 | 1746 | if (clear || (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)) |
4e55eb38 CK |
1747 | last_update = &vm->last_update; |
1748 | else | |
1749 | last_update = &bo_va->last_pt_update; | |
1750 | ||
3d7d4d3a CK |
1751 | if (!clear && bo_va->base.moved) { |
1752 | bo_va->base.moved = false; | |
7fc11959 | 1753 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1754 | |
cb7b6ec2 CK |
1755 | } else if (bo_va->cleared != clear) { |
1756 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1757 | } |
7fc11959 CK |
1758 | |
1759 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
457e0fee | 1760 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
a690aa0f | 1761 | mapping, flags, bo_adev, nodes, |
4e55eb38 | 1762 | last_update); |
d38ceaf9 AD |
1763 | if (r) |
1764 | return r; | |
1765 | } | |
1766 | ||
bb475839 JZ |
1767 | /* If the BO is not in its preferred location add it back to |
1768 | * the evicted list so that it gets validated again on the | |
1769 | * next command submission. | |
1770 | */ | |
5a5011a7 | 1771 | if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) { |
806f043f CK |
1772 | uint32_t mem_type = bo->tbo.mem.mem_type; |
1773 | ||
fc39d903 CK |
1774 | if (!(bo->preferred_domains & |
1775 | amdgpu_mem_type_to_domain(mem_type))) | |
bcdc9fd6 | 1776 | amdgpu_vm_bo_evicted(&bo_va->base); |
806f043f | 1777 | else |
bcdc9fd6 | 1778 | amdgpu_vm_bo_idle(&bo_va->base); |
c12a2ee5 | 1779 | } else { |
bcdc9fd6 | 1780 | amdgpu_vm_bo_done(&bo_va->base); |
806f043f | 1781 | } |
d38ceaf9 | 1782 | |
cb7b6ec2 CK |
1783 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1784 | bo_va->cleared = clear; | |
1785 | ||
1786 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1787 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1788 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1789 | } |
1790 | ||
d38ceaf9 AD |
1791 | return 0; |
1792 | } | |
1793 | ||
284710fa CK |
1794 | /** |
1795 | * amdgpu_vm_update_prt_state - update the global PRT state | |
7fc48e59 AG |
1796 | * |
1797 | * @adev: amdgpu_device pointer | |
284710fa CK |
1798 | */ |
1799 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1800 | { | |
1801 | unsigned long flags; | |
1802 | bool enable; | |
1803 | ||
1804 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1805 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
132f34e4 | 1806 | adev->gmc.gmc_funcs->set_prt(adev, enable); |
284710fa CK |
1807 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); |
1808 | } | |
1809 | ||
451bc8eb | 1810 | /** |
4388fc2a | 1811 | * amdgpu_vm_prt_get - add a PRT user |
7fc48e59 AG |
1812 | * |
1813 | * @adev: amdgpu_device pointer | |
451bc8eb CK |
1814 | */ |
1815 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1816 | { | |
132f34e4 | 1817 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1818 | return; |
1819 | ||
451bc8eb CK |
1820 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1821 | amdgpu_vm_update_prt_state(adev); | |
1822 | } | |
1823 | ||
0b15f2fc CK |
1824 | /** |
1825 | * amdgpu_vm_prt_put - drop a PRT user | |
7fc48e59 AG |
1826 | * |
1827 | * @adev: amdgpu_device pointer | |
0b15f2fc CK |
1828 | */ |
1829 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1830 | { | |
451bc8eb | 1831 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1832 | amdgpu_vm_update_prt_state(adev); |
1833 | } | |
1834 | ||
284710fa | 1835 | /** |
451bc8eb | 1836 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
7fc48e59 AG |
1837 | * |
1838 | * @fence: fence for the callback | |
00553cf8 | 1839 | * @_cb: the callback function |
284710fa CK |
1840 | */ |
1841 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1842 | { | |
1843 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1844 | ||
0b15f2fc | 1845 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1846 | kfree(cb); |
1847 | } | |
1848 | ||
451bc8eb CK |
1849 | /** |
1850 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
7fc48e59 AG |
1851 | * |
1852 | * @adev: amdgpu_device pointer | |
1853 | * @fence: fence for the callback | |
451bc8eb CK |
1854 | */ |
1855 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1856 | struct dma_fence *fence) | |
1857 | { | |
4388fc2a | 1858 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1859 | |
132f34e4 | 1860 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1861 | return; |
1862 | ||
1863 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1864 | if (!cb) { |
1865 | /* Last resort when we are OOM */ | |
1866 | if (fence) | |
1867 | dma_fence_wait(fence, false); | |
1868 | ||
486a68f5 | 1869 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1870 | } else { |
1871 | cb->adev = adev; | |
1872 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1873 | amdgpu_vm_prt_cb)) | |
1874 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1875 | } | |
1876 | } | |
1877 | ||
284710fa CK |
1878 | /** |
1879 | * amdgpu_vm_free_mapping - free a mapping | |
1880 | * | |
1881 | * @adev: amdgpu_device pointer | |
1882 | * @vm: requested vm | |
1883 | * @mapping: mapping to be freed | |
1884 | * @fence: fence of the unmap operation | |
1885 | * | |
1886 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1887 | */ | |
1888 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1889 | struct amdgpu_vm *vm, | |
1890 | struct amdgpu_bo_va_mapping *mapping, | |
1891 | struct dma_fence *fence) | |
1892 | { | |
451bc8eb CK |
1893 | if (mapping->flags & AMDGPU_PTE_PRT) |
1894 | amdgpu_vm_add_prt_cb(adev, fence); | |
1895 | kfree(mapping); | |
1896 | } | |
284710fa | 1897 | |
451bc8eb CK |
1898 | /** |
1899 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1900 | * | |
1901 | * @adev: amdgpu_device pointer | |
1902 | * @vm: requested vm | |
1903 | * | |
1904 | * Register a cleanup callback to disable PRT support after VM dies. | |
1905 | */ | |
1906 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1907 | { | |
52791eee | 1908 | struct dma_resv *resv = vm->root.base.bo->tbo.base.resv; |
451bc8eb CK |
1909 | struct dma_fence *excl, **shared; |
1910 | unsigned i, shared_count; | |
1911 | int r; | |
0b15f2fc | 1912 | |
52791eee | 1913 | r = dma_resv_get_fences_rcu(resv, &excl, |
451bc8eb CK |
1914 | &shared_count, &shared); |
1915 | if (r) { | |
1916 | /* Not enough memory to grab the fence list, as last resort | |
1917 | * block for all the fences to complete. | |
1918 | */ | |
52791eee | 1919 | dma_resv_wait_timeout_rcu(resv, true, false, |
451bc8eb CK |
1920 | MAX_SCHEDULE_TIMEOUT); |
1921 | return; | |
284710fa | 1922 | } |
451bc8eb CK |
1923 | |
1924 | /* Add a callback for each fence in the reservation object */ | |
1925 | amdgpu_vm_prt_get(adev); | |
1926 | amdgpu_vm_add_prt_cb(adev, excl); | |
1927 | ||
1928 | for (i = 0; i < shared_count; ++i) { | |
1929 | amdgpu_vm_prt_get(adev); | |
1930 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1931 | } | |
1932 | ||
1933 | kfree(shared); | |
284710fa CK |
1934 | } |
1935 | ||
d38ceaf9 AD |
1936 | /** |
1937 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1938 | * | |
1939 | * @adev: amdgpu_device pointer | |
1940 | * @vm: requested vm | |
f3467818 NH |
1941 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1942 | * or if an error occurred) | |
d38ceaf9 AD |
1943 | * |
1944 | * Make sure all freed BOs are cleared in the PT. | |
d38ceaf9 | 1945 | * PTs have to be reserved and mutex must be locked! |
7fc48e59 AG |
1946 | * |
1947 | * Returns: | |
1948 | * 0 for success. | |
1949 | * | |
d38ceaf9 AD |
1950 | */ |
1951 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1952 | struct amdgpu_vm *vm, |
1953 | struct dma_fence **fence) | |
d38ceaf9 AD |
1954 | { |
1955 | struct amdgpu_bo_va_mapping *mapping; | |
4584312d | 1956 | uint64_t init_pte_value = 0; |
f3467818 | 1957 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1958 | int r; |
1959 | ||
1960 | while (!list_empty(&vm->freed)) { | |
1961 | mapping = list_first_entry(&vm->freed, | |
1962 | struct amdgpu_bo_va_mapping, list); | |
1963 | list_del(&mapping->list); | |
e17841b9 | 1964 | |
ad9a5b78 CK |
1965 | if (vm->pte_support_ats && |
1966 | mapping->start < AMDGPU_GMC_HOLE_START) | |
6d16dac8 | 1967 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec | 1968 | |
acb476f5 | 1969 | r = amdgpu_vm_bo_update_mapping(adev, vm, false, NULL, |
fc6aa33d | 1970 | mapping->start, mapping->last, |
acb476f5 | 1971 | init_pte_value, 0, NULL, &f); |
f3467818 | 1972 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1973 | if (r) { |
f3467818 | 1974 | dma_fence_put(f); |
d38ceaf9 | 1975 | return r; |
284710fa | 1976 | } |
f3467818 | 1977 | } |
d38ceaf9 | 1978 | |
f3467818 NH |
1979 | if (fence && f) { |
1980 | dma_fence_put(*fence); | |
1981 | *fence = f; | |
1982 | } else { | |
1983 | dma_fence_put(f); | |
d38ceaf9 | 1984 | } |
f3467818 | 1985 | |
d38ceaf9 AD |
1986 | return 0; |
1987 | ||
1988 | } | |
1989 | ||
1990 | /** | |
73fb16e7 | 1991 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
1992 | * |
1993 | * @adev: amdgpu_device pointer | |
1994 | * @vm: requested vm | |
1995 | * | |
73fb16e7 | 1996 | * Make sure all BOs which are moved are updated in the PTs. |
7fc48e59 AG |
1997 | * |
1998 | * Returns: | |
1999 | * 0 for success. | |
d38ceaf9 | 2000 | * |
73fb16e7 | 2001 | * PTs have to be reserved! |
d38ceaf9 | 2002 | */ |
73fb16e7 | 2003 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 2004 | struct amdgpu_vm *vm) |
d38ceaf9 | 2005 | { |
789f3317 | 2006 | struct amdgpu_bo_va *bo_va, *tmp; |
52791eee | 2007 | struct dma_resv *resv; |
73fb16e7 | 2008 | bool clear; |
789f3317 | 2009 | int r; |
d38ceaf9 | 2010 | |
c12a2ee5 CK |
2011 | list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { |
2012 | /* Per VM BOs never need to bo cleared in the page tables */ | |
2013 | r = amdgpu_vm_bo_update(adev, bo_va, false); | |
2014 | if (r) | |
2015 | return r; | |
2016 | } | |
32b41ac2 | 2017 | |
c12a2ee5 CK |
2018 | spin_lock(&vm->invalidated_lock); |
2019 | while (!list_empty(&vm->invalidated)) { | |
2020 | bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, | |
2021 | base.vm_status); | |
5a5011a7 | 2022 | resv = bo_va->base.bo->tbo.base.resv; |
c12a2ee5 | 2023 | spin_unlock(&vm->invalidated_lock); |
ec363e0d | 2024 | |
ec363e0d | 2025 | /* Try to reserve the BO to avoid clearing its ptes */ |
52791eee | 2026 | if (!amdgpu_vm_debug && dma_resv_trylock(resv)) |
ec363e0d CK |
2027 | clear = false; |
2028 | /* Somebody else is using the BO right now */ | |
2029 | else | |
2030 | clear = true; | |
73fb16e7 CK |
2031 | |
2032 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
c12a2ee5 | 2033 | if (r) |
d38ceaf9 AD |
2034 | return r; |
2035 | ||
c12a2ee5 | 2036 | if (!clear) |
52791eee | 2037 | dma_resv_unlock(resv); |
c12a2ee5 | 2038 | spin_lock(&vm->invalidated_lock); |
d38ceaf9 | 2039 | } |
c12a2ee5 | 2040 | spin_unlock(&vm->invalidated_lock); |
d38ceaf9 | 2041 | |
789f3317 | 2042 | return 0; |
d38ceaf9 AD |
2043 | } |
2044 | ||
2045 | /** | |
2046 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
2047 | * | |
2048 | * @adev: amdgpu_device pointer | |
2049 | * @vm: requested vm | |
2050 | * @bo: amdgpu buffer object | |
2051 | * | |
8843dbbb | 2052 | * Add @bo into the requested vm. |
d38ceaf9 | 2053 | * Add @bo to the list of bos associated with the vm |
7fc48e59 AG |
2054 | * |
2055 | * Returns: | |
2056 | * Newly added bo_va or NULL for failure | |
d38ceaf9 AD |
2057 | * |
2058 | * Object has to be reserved! | |
2059 | */ | |
2060 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
2061 | struct amdgpu_vm *vm, | |
2062 | struct amdgpu_bo *bo) | |
2063 | { | |
2064 | struct amdgpu_bo_va *bo_va; | |
2065 | ||
2066 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2067 | if (bo_va == NULL) { | |
2068 | return NULL; | |
2069 | } | |
3f4299be | 2070 | amdgpu_vm_bo_base_init(&bo_va->base, vm, bo); |
ec681545 | 2071 | |
d38ceaf9 | 2072 | bo_va->ref_count = 1; |
7fc11959 CK |
2073 | INIT_LIST_HEAD(&bo_va->valids); |
2074 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2075 | |
b4ae4fe6 | 2076 | if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) && |
2077 | (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)) { | |
df399b06 | 2078 | bo_va->is_xgmi = true; |
2079 | mutex_lock(&adev->vm_manager.lock_pstate); | |
2080 | /* Power up XGMI if it can be potentially used */ | |
2081 | if (++adev->vm_manager.xgmi_map_counter == 1) | |
2082 | amdgpu_xgmi_set_pstate(adev, 1); | |
2083 | mutex_unlock(&adev->vm_manager.lock_pstate); | |
2084 | } | |
2085 | ||
d38ceaf9 AD |
2086 | return bo_va; |
2087 | } | |
2088 | ||
73fb16e7 CK |
2089 | |
2090 | /** | |
2091 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
2092 | * | |
2093 | * @adev: amdgpu_device pointer | |
2094 | * @bo_va: bo_va to store the address | |
2095 | * @mapping: the mapping to insert | |
2096 | * | |
2097 | * Insert a new mapping into all structures. | |
2098 | */ | |
2099 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2100 | struct amdgpu_bo_va *bo_va, | |
2101 | struct amdgpu_bo_va_mapping *mapping) | |
2102 | { | |
2103 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2104 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2105 | ||
aebc5e6f | 2106 | mapping->bo_va = bo_va; |
73fb16e7 CK |
2107 | list_add(&mapping->list, &bo_va->invalids); |
2108 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2109 | ||
2110 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2111 | amdgpu_vm_prt_get(adev); | |
2112 | ||
5a5011a7 | 2113 | if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv && |
862b8c57 | 2114 | !bo_va->base.moved) { |
862b8c57 | 2115 | list_move(&bo_va->base.vm_status, &vm->moved); |
73fb16e7 CK |
2116 | } |
2117 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2118 | } | |
2119 | ||
d38ceaf9 AD |
2120 | /** |
2121 | * amdgpu_vm_bo_map - map bo inside a vm | |
2122 | * | |
2123 | * @adev: amdgpu_device pointer | |
2124 | * @bo_va: bo_va to store the address | |
2125 | * @saddr: where to map the BO | |
2126 | * @offset: requested offset in the BO | |
00553cf8 | 2127 | * @size: BO size in bytes |
d38ceaf9 AD |
2128 | * @flags: attributes of pages (read/write/valid/etc.) |
2129 | * | |
2130 | * Add a mapping of the BO at the specefied addr into the VM. | |
7fc48e59 AG |
2131 | * |
2132 | * Returns: | |
2133 | * 0 for success, error for failure. | |
d38ceaf9 | 2134 | * |
49b02b18 | 2135 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2136 | */ |
2137 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2138 | struct amdgpu_bo_va *bo_va, | |
2139 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2140 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2141 | { |
a9f87f64 | 2142 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2143 | struct amdgpu_bo *bo = bo_va->base.bo; |
2144 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2145 | uint64_t eaddr; |
d38ceaf9 | 2146 | |
0be52de9 CK |
2147 | /* validate the parameters */ |
2148 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2149 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2150 | return -EINVAL; |
0be52de9 | 2151 | |
d38ceaf9 | 2152 | /* make sure object fit at this offset */ |
005ae95e | 2153 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2154 | if (saddr >= eaddr || |
ec681545 | 2155 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 2156 | return -EINVAL; |
d38ceaf9 | 2157 | |
d38ceaf9 AD |
2158 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2159 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2160 | ||
a9f87f64 CK |
2161 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2162 | if (tmp) { | |
d38ceaf9 AD |
2163 | /* bo and tmp overlap, invalid addr */ |
2164 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2165 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2166 | tmp->start, tmp->last + 1); |
663e4577 | 2167 | return -EINVAL; |
d38ceaf9 AD |
2168 | } |
2169 | ||
2170 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2171 | if (!mapping) |
2172 | return -ENOMEM; | |
d38ceaf9 | 2173 | |
a9f87f64 CK |
2174 | mapping->start = saddr; |
2175 | mapping->last = eaddr; | |
d38ceaf9 AD |
2176 | mapping->offset = offset; |
2177 | mapping->flags = flags; | |
2178 | ||
73fb16e7 | 2179 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
2180 | |
2181 | return 0; | |
2182 | } | |
2183 | ||
2184 | /** | |
2185 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2186 | * | |
2187 | * @adev: amdgpu_device pointer | |
2188 | * @bo_va: bo_va to store the address | |
2189 | * @saddr: where to map the BO | |
2190 | * @offset: requested offset in the BO | |
00553cf8 | 2191 | * @size: BO size in bytes |
80f95c57 CK |
2192 | * @flags: attributes of pages (read/write/valid/etc.) |
2193 | * | |
2194 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2195 | * mappings as we do so. | |
7fc48e59 AG |
2196 | * |
2197 | * Returns: | |
2198 | * 0 for success, error for failure. | |
80f95c57 CK |
2199 | * |
2200 | * Object has to be reserved and unreserved outside! | |
2201 | */ | |
2202 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2203 | struct amdgpu_bo_va *bo_va, | |
2204 | uint64_t saddr, uint64_t offset, | |
2205 | uint64_t size, uint64_t flags) | |
2206 | { | |
2207 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2208 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
2209 | uint64_t eaddr; |
2210 | int r; | |
2211 | ||
2212 | /* validate the parameters */ | |
2213 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2214 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2215 | return -EINVAL; | |
2216 | ||
2217 | /* make sure object fit at this offset */ | |
2218 | eaddr = saddr + size - 1; | |
2219 | if (saddr >= eaddr || | |
ec681545 | 2220 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
2221 | return -EINVAL; |
2222 | ||
2223 | /* Allocate all the needed memory */ | |
2224 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2225 | if (!mapping) | |
2226 | return -ENOMEM; | |
2227 | ||
ec681545 | 2228 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2229 | if (r) { |
2230 | kfree(mapping); | |
2231 | return r; | |
2232 | } | |
2233 | ||
2234 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2235 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2236 | ||
a9f87f64 CK |
2237 | mapping->start = saddr; |
2238 | mapping->last = eaddr; | |
80f95c57 CK |
2239 | mapping->offset = offset; |
2240 | mapping->flags = flags; | |
2241 | ||
73fb16e7 | 2242 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 2243 | |
d38ceaf9 | 2244 | return 0; |
d38ceaf9 AD |
2245 | } |
2246 | ||
2247 | /** | |
2248 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2249 | * | |
2250 | * @adev: amdgpu_device pointer | |
2251 | * @bo_va: bo_va to remove the address from | |
2252 | * @saddr: where to the BO is mapped | |
2253 | * | |
2254 | * Remove a mapping of the BO at the specefied addr from the VM. | |
7fc48e59 AG |
2255 | * |
2256 | * Returns: | |
2257 | * 0 for success, error for failure. | |
d38ceaf9 | 2258 | * |
49b02b18 | 2259 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2260 | */ |
2261 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2262 | struct amdgpu_bo_va *bo_va, | |
2263 | uint64_t saddr) | |
2264 | { | |
2265 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2266 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2267 | bool valid = true; |
d38ceaf9 | 2268 | |
6c7fc503 | 2269 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2270 | |
7fc11959 | 2271 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2272 | if (mapping->start == saddr) |
d38ceaf9 AD |
2273 | break; |
2274 | } | |
2275 | ||
7fc11959 CK |
2276 | if (&mapping->list == &bo_va->valids) { |
2277 | valid = false; | |
2278 | ||
2279 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2280 | if (mapping->start == saddr) |
7fc11959 CK |
2281 | break; |
2282 | } | |
2283 | ||
32b41ac2 | 2284 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2285 | return -ENOENT; |
d38ceaf9 | 2286 | } |
32b41ac2 | 2287 | |
d38ceaf9 | 2288 | list_del(&mapping->list); |
a9f87f64 | 2289 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2290 | mapping->bo_va = NULL; |
93e3e438 | 2291 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2292 | |
e17841b9 | 2293 | if (valid) |
d38ceaf9 | 2294 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2295 | else |
284710fa CK |
2296 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2297 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2298 | |
2299 | return 0; | |
2300 | } | |
2301 | ||
dc54d3d1 CK |
2302 | /** |
2303 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2304 | * | |
2305 | * @adev: amdgpu_device pointer | |
2306 | * @vm: VM structure to use | |
2307 | * @saddr: start of the range | |
2308 | * @size: size of the range | |
2309 | * | |
2310 | * Remove all mappings in a range, split them as appropriate. | |
7fc48e59 AG |
2311 | * |
2312 | * Returns: | |
2313 | * 0 for success, error for failure. | |
dc54d3d1 CK |
2314 | */ |
2315 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2316 | struct amdgpu_vm *vm, | |
2317 | uint64_t saddr, uint64_t size) | |
2318 | { | |
2319 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2320 | LIST_HEAD(removed); |
2321 | uint64_t eaddr; | |
2322 | ||
2323 | eaddr = saddr + size - 1; | |
2324 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2325 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2326 | ||
2327 | /* Allocate all the needed memory */ | |
2328 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2329 | if (!before) | |
2330 | return -ENOMEM; | |
27f6d610 | 2331 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2332 | |
2333 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2334 | if (!after) { | |
2335 | kfree(before); | |
2336 | return -ENOMEM; | |
2337 | } | |
27f6d610 | 2338 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2339 | |
2340 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2341 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2342 | while (tmp) { | |
dc54d3d1 | 2343 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2344 | if (tmp->start < saddr) { |
2345 | before->start = tmp->start; | |
2346 | before->last = saddr - 1; | |
dc54d3d1 CK |
2347 | before->offset = tmp->offset; |
2348 | before->flags = tmp->flags; | |
387f49e5 JZ |
2349 | before->bo_va = tmp->bo_va; |
2350 | list_add(&before->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2351 | } |
2352 | ||
2353 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2354 | if (tmp->last > eaddr) { |
2355 | after->start = eaddr + 1; | |
2356 | after->last = tmp->last; | |
dc54d3d1 | 2357 | after->offset = tmp->offset; |
a9f87f64 | 2358 | after->offset += after->start - tmp->start; |
dc54d3d1 | 2359 | after->flags = tmp->flags; |
387f49e5 JZ |
2360 | after->bo_va = tmp->bo_va; |
2361 | list_add(&after->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2362 | } |
2363 | ||
2364 | list_del(&tmp->list); | |
2365 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2366 | |
2367 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2368 | } |
2369 | ||
2370 | /* And free them up */ | |
2371 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2372 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2373 | list_del(&tmp->list); |
2374 | ||
a9f87f64 CK |
2375 | if (tmp->start < saddr) |
2376 | tmp->start = saddr; | |
2377 | if (tmp->last > eaddr) | |
2378 | tmp->last = eaddr; | |
dc54d3d1 | 2379 | |
aebc5e6f | 2380 | tmp->bo_va = NULL; |
dc54d3d1 CK |
2381 | list_add(&tmp->list, &vm->freed); |
2382 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2383 | } | |
2384 | ||
27f6d610 JZ |
2385 | /* Insert partial mapping before the range */ |
2386 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2387 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2388 | if (before->flags & AMDGPU_PTE_PRT) |
2389 | amdgpu_vm_prt_get(adev); | |
2390 | } else { | |
2391 | kfree(before); | |
2392 | } | |
2393 | ||
2394 | /* Insert partial mapping after the range */ | |
27f6d610 | 2395 | if (!list_empty(&after->list)) { |
a9f87f64 | 2396 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2397 | if (after->flags & AMDGPU_PTE_PRT) |
2398 | amdgpu_vm_prt_get(adev); | |
2399 | } else { | |
2400 | kfree(after); | |
2401 | } | |
2402 | ||
2403 | return 0; | |
2404 | } | |
2405 | ||
aebc5e6f CK |
2406 | /** |
2407 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2408 | * | |
2409 | * @vm: the requested VM | |
00553cf8 | 2410 | * @addr: the address |
aebc5e6f CK |
2411 | * |
2412 | * Find a mapping by it's address. | |
7fc48e59 AG |
2413 | * |
2414 | * Returns: | |
2415 | * The amdgpu_bo_va_mapping matching for addr or NULL | |
2416 | * | |
aebc5e6f CK |
2417 | */ |
2418 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2419 | uint64_t addr) | |
2420 | { | |
2421 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2422 | } | |
2423 | ||
8ab19ea6 CK |
2424 | /** |
2425 | * amdgpu_vm_bo_trace_cs - trace all reserved mappings | |
2426 | * | |
2427 | * @vm: the requested vm | |
2428 | * @ticket: CS ticket | |
2429 | * | |
2430 | * Trace all mappings of BOs reserved during a command submission. | |
2431 | */ | |
2432 | void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) | |
2433 | { | |
2434 | struct amdgpu_bo_va_mapping *mapping; | |
2435 | ||
2436 | if (!trace_amdgpu_vm_bo_cs_enabled()) | |
2437 | return; | |
2438 | ||
2439 | for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping; | |
2440 | mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) { | |
2441 | if (mapping->bo_va && mapping->bo_va->base.bo) { | |
2442 | struct amdgpu_bo *bo; | |
2443 | ||
2444 | bo = mapping->bo_va->base.bo; | |
52791eee | 2445 | if (dma_resv_locking_ctx(bo->tbo.base.resv) != |
0dbd555a | 2446 | ticket) |
8ab19ea6 CK |
2447 | continue; |
2448 | } | |
2449 | ||
2450 | trace_amdgpu_vm_bo_cs(mapping); | |
2451 | } | |
2452 | } | |
2453 | ||
d38ceaf9 AD |
2454 | /** |
2455 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2456 | * | |
2457 | * @adev: amdgpu_device pointer | |
2458 | * @bo_va: requested bo_va | |
2459 | * | |
8843dbbb | 2460 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2461 | * |
2462 | * Object have to be reserved! | |
2463 | */ | |
2464 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2465 | struct amdgpu_bo_va *bo_va) | |
2466 | { | |
2467 | struct amdgpu_bo_va_mapping *mapping, *next; | |
fbbf794c | 2468 | struct amdgpu_bo *bo = bo_va->base.bo; |
ec681545 | 2469 | struct amdgpu_vm *vm = bo_va->base.vm; |
646b9025 | 2470 | struct amdgpu_vm_bo_base **base; |
d38ceaf9 | 2471 | |
646b9025 | 2472 | if (bo) { |
5a5011a7 | 2473 | if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) |
646b9025 | 2474 | vm->bulk_moveable = false; |
fbbf794c | 2475 | |
646b9025 CK |
2476 | for (base = &bo_va->base.bo->vm_bo; *base; |
2477 | base = &(*base)->next) { | |
2478 | if (*base != &bo_va->base) | |
2479 | continue; | |
2480 | ||
2481 | *base = bo_va->base.next; | |
2482 | break; | |
2483 | } | |
2484 | } | |
d38ceaf9 | 2485 | |
c12a2ee5 | 2486 | spin_lock(&vm->invalidated_lock); |
ec681545 | 2487 | list_del(&bo_va->base.vm_status); |
c12a2ee5 | 2488 | spin_unlock(&vm->invalidated_lock); |
d38ceaf9 | 2489 | |
7fc11959 | 2490 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2491 | list_del(&mapping->list); |
a9f87f64 | 2492 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2493 | mapping->bo_va = NULL; |
93e3e438 | 2494 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2495 | list_add(&mapping->list, &vm->freed); |
2496 | } | |
2497 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2498 | list_del(&mapping->list); | |
a9f87f64 | 2499 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2500 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2501 | bo_va->last_pt_update); | |
d38ceaf9 | 2502 | } |
32b41ac2 | 2503 | |
f54d1867 | 2504 | dma_fence_put(bo_va->last_pt_update); |
df399b06 | 2505 | |
2506 | if (bo && bo_va->is_xgmi) { | |
2507 | mutex_lock(&adev->vm_manager.lock_pstate); | |
2508 | if (--adev->vm_manager.xgmi_map_counter == 0) | |
2509 | amdgpu_xgmi_set_pstate(adev, 0); | |
2510 | mutex_unlock(&adev->vm_manager.lock_pstate); | |
2511 | } | |
2512 | ||
d38ceaf9 | 2513 | kfree(bo_va); |
d38ceaf9 AD |
2514 | } |
2515 | ||
6ceeb144 CK |
2516 | /** |
2517 | * amdgpu_vm_evictable - check if we can evict a VM | |
2518 | * | |
2519 | * @bo: A page table of the VM. | |
2520 | * | |
2521 | * Check if it is possible to evict a VM. | |
2522 | */ | |
2523 | bool amdgpu_vm_evictable(struct amdgpu_bo *bo) | |
2524 | { | |
2525 | struct amdgpu_vm_bo_base *bo_base = bo->vm_bo; | |
2526 | ||
2527 | /* Page tables of a destroyed VM can go away immediately */ | |
2528 | if (!bo_base || !bo_base->vm) | |
2529 | return true; | |
2530 | ||
2531 | /* Don't evict VM page tables while they are busy */ | |
2532 | if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true)) | |
2533 | return false; | |
2534 | ||
b4ff0f8a CK |
2535 | /* Try to block ongoing updates */ |
2536 | if (!mutex_trylock(&bo_base->vm->eviction_lock)) | |
2537 | return false; | |
2538 | ||
90b69cdc CK |
2539 | /* Don't evict VM page tables while they are updated */ |
2540 | if (!dma_fence_is_signaled(bo_base->vm->last_direct) || | |
b4ff0f8a CK |
2541 | !dma_fence_is_signaled(bo_base->vm->last_delayed)) { |
2542 | mutex_unlock(&bo_base->vm->eviction_lock); | |
90b69cdc | 2543 | return false; |
b4ff0f8a | 2544 | } |
90b69cdc | 2545 | |
b4ff0f8a CK |
2546 | bo_base->vm->evicting = true; |
2547 | mutex_unlock(&bo_base->vm->eviction_lock); | |
6ceeb144 CK |
2548 | return true; |
2549 | } | |
2550 | ||
d38ceaf9 AD |
2551 | /** |
2552 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2553 | * | |
2554 | * @adev: amdgpu_device pointer | |
d38ceaf9 | 2555 | * @bo: amdgpu buffer object |
00553cf8 | 2556 | * @evicted: is the BO evicted |
d38ceaf9 | 2557 | * |
8843dbbb | 2558 | * Mark @bo as invalid. |
d38ceaf9 AD |
2559 | */ |
2560 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2561 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2562 | { |
ec681545 CK |
2563 | struct amdgpu_vm_bo_base *bo_base; |
2564 | ||
4bebccee CZ |
2565 | /* shadow bo doesn't have bo base, its validation needs its parent */ |
2566 | if (bo->parent && bo->parent->shadow == bo) | |
2567 | bo = bo->parent; | |
2568 | ||
646b9025 | 2569 | for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { |
3f3333f8 CK |
2570 | struct amdgpu_vm *vm = bo_base->vm; |
2571 | ||
5a5011a7 | 2572 | if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) { |
bcdc9fd6 | 2573 | amdgpu_vm_bo_evicted(bo_base); |
3f3333f8 CK |
2574 | continue; |
2575 | } | |
2576 | ||
bcdc9fd6 | 2577 | if (bo_base->moved) |
3f3333f8 | 2578 | continue; |
bcdc9fd6 | 2579 | bo_base->moved = true; |
3f3333f8 | 2580 | |
bcdc9fd6 CK |
2581 | if (bo->tbo.type == ttm_bo_type_kernel) |
2582 | amdgpu_vm_bo_relocated(bo_base); | |
5a5011a7 | 2583 | else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) |
bcdc9fd6 CK |
2584 | amdgpu_vm_bo_moved(bo_base); |
2585 | else | |
2586 | amdgpu_vm_bo_invalidated(bo_base); | |
d38ceaf9 AD |
2587 | } |
2588 | } | |
2589 | ||
7fc48e59 AG |
2590 | /** |
2591 | * amdgpu_vm_get_block_size - calculate VM page table size as power of two | |
2592 | * | |
2593 | * @vm_size: VM size | |
2594 | * | |
2595 | * Returns: | |
2596 | * VM page table as power of two | |
2597 | */ | |
bab4fee7 JZ |
2598 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2599 | { | |
2600 | /* Total bits covered by PD + PTs */ | |
2601 | unsigned bits = ilog2(vm_size) + 18; | |
2602 | ||
2603 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2604 | Above that split equal between PD and PTs */ | |
2605 | if (vm_size <= 8) | |
2606 | return (bits - 9); | |
2607 | else | |
2608 | return ((bits + 3) / 2); | |
2609 | } | |
2610 | ||
d07f14be RH |
2611 | /** |
2612 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2613 | * |
2614 | * @adev: amdgpu_device pointer | |
43370c4c | 2615 | * @min_vm_size: the minimum vm size in GB if it's set auto |
00553cf8 AG |
2616 | * @fragment_size_default: Default PTE fragment size |
2617 | * @max_level: max VMPT level | |
2618 | * @max_bits: max address space size in bits | |
2619 | * | |
bab4fee7 | 2620 | */ |
43370c4c | 2621 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, |
f3368128 CK |
2622 | uint32_t fragment_size_default, unsigned max_level, |
2623 | unsigned max_bits) | |
bab4fee7 | 2624 | { |
43370c4c FK |
2625 | unsigned int max_size = 1 << (max_bits - 30); |
2626 | unsigned int vm_size; | |
36539dce CK |
2627 | uint64_t tmp; |
2628 | ||
2629 | /* adjust vm size first */ | |
f3368128 | 2630 | if (amdgpu_vm_size != -1) { |
fdd5faaa | 2631 | vm_size = amdgpu_vm_size; |
f3368128 CK |
2632 | if (vm_size > max_size) { |
2633 | dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", | |
2634 | amdgpu_vm_size, max_size); | |
2635 | vm_size = max_size; | |
2636 | } | |
43370c4c FK |
2637 | } else { |
2638 | struct sysinfo si; | |
2639 | unsigned int phys_ram_gb; | |
2640 | ||
2641 | /* Optimal VM size depends on the amount of physical | |
2642 | * RAM available. Underlying requirements and | |
2643 | * assumptions: | |
2644 | * | |
2645 | * - Need to map system memory and VRAM from all GPUs | |
2646 | * - VRAM from other GPUs not known here | |
2647 | * - Assume VRAM <= system memory | |
2648 | * - On GFX8 and older, VM space can be segmented for | |
2649 | * different MTYPEs | |
2650 | * - Need to allow room for fragmentation, guard pages etc. | |
2651 | * | |
2652 | * This adds up to a rough guess of system memory x3. | |
2653 | * Round up to power of two to maximize the available | |
2654 | * VM size with the given page table size. | |
2655 | */ | |
2656 | si_meminfo(&si); | |
2657 | phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit + | |
2658 | (1 << 30) - 1) >> 30; | |
2659 | vm_size = roundup_pow_of_two( | |
2660 | min(max(phys_ram_gb * 3, min_vm_size), max_size)); | |
f3368128 | 2661 | } |
fdd5faaa CK |
2662 | |
2663 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
36539dce CK |
2664 | |
2665 | tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); | |
97489129 CK |
2666 | if (amdgpu_vm_block_size != -1) |
2667 | tmp >>= amdgpu_vm_block_size - 9; | |
36539dce CK |
2668 | tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; |
2669 | adev->vm_manager.num_level = min(max_level, (unsigned)tmp); | |
196f7489 CZ |
2670 | switch (adev->vm_manager.num_level) { |
2671 | case 3: | |
2672 | adev->vm_manager.root_level = AMDGPU_VM_PDB2; | |
2673 | break; | |
2674 | case 2: | |
2675 | adev->vm_manager.root_level = AMDGPU_VM_PDB1; | |
2676 | break; | |
2677 | case 1: | |
2678 | adev->vm_manager.root_level = AMDGPU_VM_PDB0; | |
2679 | break; | |
2680 | default: | |
2681 | dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n"); | |
2682 | } | |
b38f41eb | 2683 | /* block size depends on vm size and hw setup*/ |
97489129 | 2684 | if (amdgpu_vm_block_size != -1) |
bab4fee7 | 2685 | adev->vm_manager.block_size = |
97489129 CK |
2686 | min((unsigned)amdgpu_vm_block_size, max_bits |
2687 | - AMDGPU_GPU_PAGE_SHIFT | |
2688 | - 9 * adev->vm_manager.num_level); | |
2689 | else if (adev->vm_manager.num_level > 1) | |
2690 | adev->vm_manager.block_size = 9; | |
bab4fee7 | 2691 | else |
97489129 | 2692 | adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); |
bab4fee7 | 2693 | |
b38f41eb CK |
2694 | if (amdgpu_vm_fragment_size == -1) |
2695 | adev->vm_manager.fragment_size = fragment_size_default; | |
2696 | else | |
2697 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
d07f14be | 2698 | |
36539dce CK |
2699 | DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", |
2700 | vm_size, adev->vm_manager.num_level + 1, | |
2701 | adev->vm_manager.block_size, | |
fdd5faaa | 2702 | adev->vm_manager.fragment_size); |
bab4fee7 JZ |
2703 | } |
2704 | ||
56753e73 CK |
2705 | /** |
2706 | * amdgpu_vm_wait_idle - wait for the VM to become idle | |
2707 | * | |
2708 | * @vm: VM object to wait for | |
2709 | * @timeout: timeout to wait for VM to become idle | |
2710 | */ | |
2711 | long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout) | |
240cd9a6 | 2712 | { |
90b69cdc CK |
2713 | timeout = dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv, |
2714 | true, true, timeout); | |
2715 | if (timeout <= 0) | |
2716 | return timeout; | |
2717 | ||
2718 | timeout = dma_fence_wait_timeout(vm->last_direct, true, timeout); | |
2719 | if (timeout <= 0) | |
2720 | return timeout; | |
2721 | ||
2722 | return dma_fence_wait_timeout(vm->last_delayed, true, timeout); | |
240cd9a6 OZ |
2723 | } |
2724 | ||
d38ceaf9 AD |
2725 | /** |
2726 | * amdgpu_vm_init - initialize a vm instance | |
2727 | * | |
2728 | * @adev: amdgpu_device pointer | |
2729 | * @vm: requested vm | |
9a4b7d4c | 2730 | * @vm_context: Indicates if it GFX or Compute context |
00553cf8 | 2731 | * @pasid: Process address space identifier |
d38ceaf9 | 2732 | * |
8843dbbb | 2733 | * Init @vm fields. |
7fc48e59 AG |
2734 | * |
2735 | * Returns: | |
2736 | * 0 for success, error for failure. | |
d38ceaf9 | 2737 | */ |
9a4b7d4c | 2738 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 2739 | int vm_context, unsigned int pasid) |
d38ceaf9 | 2740 | { |
3216c6b7 | 2741 | struct amdgpu_bo_param bp; |
3f4299be | 2742 | struct amdgpu_bo *root; |
36bbf3bf | 2743 | int r, i; |
d38ceaf9 | 2744 | |
f808c13f | 2745 | vm->va = RB_ROOT_CACHED; |
36bbf3bf CZ |
2746 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2747 | vm->reserved_vmid[i] = NULL; | |
3f3333f8 | 2748 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2749 | INIT_LIST_HEAD(&vm->relocated); |
27c7b9ae | 2750 | INIT_LIST_HEAD(&vm->moved); |
806f043f | 2751 | INIT_LIST_HEAD(&vm->idle); |
c12a2ee5 CK |
2752 | INIT_LIST_HEAD(&vm->invalidated); |
2753 | spin_lock_init(&vm->invalidated_lock); | |
d38ceaf9 | 2754 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2755 | |
b3ac1766 | 2756 | |
a2cf3247 | 2757 | /* create scheduler entities for page table updates */ |
b3ac1766 | 2758 | r = drm_sched_entity_init(&vm->direct, DRM_SCHED_PRIORITY_NORMAL, |
0c88b430 ND |
2759 | adev->vm_manager.vm_pte_scheds, |
2760 | adev->vm_manager.vm_pte_num_scheds, NULL); | |
2bd9ccfa | 2761 | if (r) |
f566ceb1 | 2762 | return r; |
2bd9ccfa | 2763 | |
b3ac1766 | 2764 | r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL, |
0c88b430 ND |
2765 | adev->vm_manager.vm_pte_scheds, |
2766 | adev->vm_manager.vm_pte_num_scheds, NULL); | |
a2cf3247 CK |
2767 | if (r) |
2768 | goto error_free_direct; | |
2769 | ||
51ac7eec | 2770 | vm->pte_support_ats = false; |
f43ef951 | 2771 | vm->is_compute_context = false; |
51ac7eec YZ |
2772 | |
2773 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2774 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2775 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec | 2776 | |
741deade | 2777 | if (adev->asic_type == CHIP_RAVEN) |
51ac7eec | 2778 | vm->pte_support_ats = true; |
13307f7e | 2779 | } else { |
9a4b7d4c HK |
2780 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2781 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
13307f7e | 2782 | } |
9a4b7d4c HK |
2783 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2784 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
fc39d903 CK |
2785 | WARN_ONCE((vm->use_cpu_for_update && |
2786 | !amdgpu_gmc_vram_full_visible(&adev->gmc)), | |
9a4b7d4c | 2787 | "CPU update of VM recommended only for large BAR system\n"); |
6dd09027 CK |
2788 | |
2789 | if (vm->use_cpu_for_update) | |
2790 | vm->update_funcs = &amdgpu_vm_cpu_funcs; | |
2791 | else | |
2792 | vm->update_funcs = &amdgpu_vm_sdma_funcs; | |
d5884513 | 2793 | vm->last_update = NULL; |
90b69cdc CK |
2794 | vm->last_direct = dma_fence_get_stub(); |
2795 | vm->last_delayed = dma_fence_get_stub(); | |
05906dec | 2796 | |
b4ff0f8a CK |
2797 | mutex_init(&vm->eviction_lock); |
2798 | vm->evicting = false; | |
2799 | ||
061468c4 | 2800 | amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, &bp); |
03e9dee1 FK |
2801 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) |
2802 | bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW; | |
3f4299be | 2803 | r = amdgpu_bo_create(adev, &bp, &root); |
d38ceaf9 | 2804 | if (r) |
a2cf3247 | 2805 | goto error_free_delayed; |
2bd9ccfa | 2806 | |
3f4299be | 2807 | r = amdgpu_bo_reserve(root, true); |
d3aab672 CK |
2808 | if (r) |
2809 | goto error_free_root; | |
2810 | ||
52791eee | 2811 | r = dma_resv_reserve_shared(root->tbo.base.resv, 1); |
0aa7aa24 CK |
2812 | if (r) |
2813 | goto error_unreserve; | |
2814 | ||
1e293037 CK |
2815 | amdgpu_vm_bo_base_init(&vm->root.base, vm, root); |
2816 | ||
0f6064d6 | 2817 | r = amdgpu_vm_clear_bo(adev, vm, root, false); |
13307f7e CK |
2818 | if (r) |
2819 | goto error_unreserve; | |
2820 | ||
d3aab672 | 2821 | amdgpu_bo_unreserve(vm->root.base.bo); |
d38ceaf9 | 2822 | |
02208441 FK |
2823 | if (pasid) { |
2824 | unsigned long flags; | |
2825 | ||
2826 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2827 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2828 | GFP_ATOMIC); | |
2829 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2830 | if (r < 0) | |
2831 | goto error_free_root; | |
2832 | ||
2833 | vm->pasid = pasid; | |
0a096fb6 CK |
2834 | } |
2835 | ||
a2f14820 | 2836 | INIT_KFIFO(vm->faults); |
d38ceaf9 AD |
2837 | |
2838 | return 0; | |
2bd9ccfa | 2839 | |
13307f7e CK |
2840 | error_unreserve: |
2841 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2842 | ||
67003a15 | 2843 | error_free_root: |
3f3333f8 CK |
2844 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2845 | amdgpu_bo_unref(&vm->root.base.bo); | |
2846 | vm->root.base.bo = NULL; | |
2bd9ccfa | 2847 | |
a2cf3247 | 2848 | error_free_delayed: |
90b69cdc CK |
2849 | dma_fence_put(vm->last_direct); |
2850 | dma_fence_put(vm->last_delayed); | |
a2cf3247 CK |
2851 | drm_sched_entity_destroy(&vm->delayed); |
2852 | ||
2853 | error_free_direct: | |
2854 | drm_sched_entity_destroy(&vm->direct); | |
2bd9ccfa CK |
2855 | |
2856 | return r; | |
d38ceaf9 AD |
2857 | } |
2858 | ||
3680624e TH |
2859 | /** |
2860 | * amdgpu_vm_check_clean_reserved - check if a VM is clean | |
2861 | * | |
2862 | * @adev: amdgpu_device pointer | |
2863 | * @vm: the VM to check | |
2864 | * | |
2865 | * check all entries of the root PD, if any subsequent PDs are allocated, | |
2866 | * it means there are page table creating and filling, and is no a clean | |
2867 | * VM | |
2868 | * | |
2869 | * Returns: | |
2870 | * 0 if this VM is clean | |
2871 | */ | |
2872 | static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev, | |
2873 | struct amdgpu_vm *vm) | |
2874 | { | |
2875 | enum amdgpu_vm_level root = adev->vm_manager.root_level; | |
2876 | unsigned int entries = amdgpu_vm_num_entries(adev, root); | |
2877 | unsigned int i = 0; | |
2878 | ||
2879 | if (!(vm->root.entries)) | |
2880 | return 0; | |
2881 | ||
2882 | for (i = 0; i < entries; i++) { | |
2883 | if (vm->root.entries[i].base.bo) | |
2884 | return -EINVAL; | |
2885 | } | |
2886 | ||
2887 | return 0; | |
2888 | } | |
2889 | ||
b236fa1d FK |
2890 | /** |
2891 | * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM | |
2892 | * | |
7fc48e59 AG |
2893 | * @adev: amdgpu_device pointer |
2894 | * @vm: requested vm | |
1d614ded | 2895 | * @pasid: pasid to use |
7fc48e59 | 2896 | * |
b236fa1d FK |
2897 | * This only works on GFX VMs that don't have any BOs added and no |
2898 | * page tables allocated yet. | |
2899 | * | |
2900 | * Changes the following VM parameters: | |
2901 | * - use_cpu_for_update | |
2902 | * - pte_supports_ats | |
2903 | * - pasid (old PASID is released, because compute manages its own PASIDs) | |
2904 | * | |
2905 | * Reinitializes the page directory to reflect the changed ATS | |
b5d21aac | 2906 | * setting. |
b236fa1d | 2907 | * |
7fc48e59 AG |
2908 | * Returns: |
2909 | * 0 for success, -errno for errors. | |
b236fa1d | 2910 | */ |
fc39d903 CK |
2911 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
2912 | unsigned int pasid) | |
b236fa1d | 2913 | { |
741deade | 2914 | bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); |
b236fa1d FK |
2915 | int r; |
2916 | ||
2917 | r = amdgpu_bo_reserve(vm->root.base.bo, true); | |
2918 | if (r) | |
2919 | return r; | |
2920 | ||
2921 | /* Sanity checks */ | |
3680624e TH |
2922 | r = amdgpu_vm_check_clean_reserved(adev, vm); |
2923 | if (r) | |
1685b01a | 2924 | goto unreserve_bo; |
1685b01a OZ |
2925 | |
2926 | if (pasid) { | |
2927 | unsigned long flags; | |
2928 | ||
2929 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2930 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2931 | GFP_ATOMIC); | |
2932 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2933 | ||
2934 | if (r == -ENOSPC) | |
2935 | goto unreserve_bo; | |
2936 | r = 0; | |
b236fa1d FK |
2937 | } |
2938 | ||
2939 | /* Check if PD needs to be reinitialized and do it before | |
2940 | * changing any other state, in case it fails. | |
2941 | */ | |
2942 | if (pte_support_ats != vm->pte_support_ats) { | |
780637cb | 2943 | vm->pte_support_ats = pte_support_ats; |
0f6064d6 | 2944 | r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false); |
b236fa1d | 2945 | if (r) |
1685b01a | 2946 | goto free_idr; |
b236fa1d FK |
2947 | } |
2948 | ||
2949 | /* Update VM state */ | |
2950 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
2951 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
b236fa1d FK |
2952 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2953 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
fc39d903 CK |
2954 | WARN_ONCE((vm->use_cpu_for_update && |
2955 | !amdgpu_gmc_vram_full_visible(&adev->gmc)), | |
b236fa1d FK |
2956 | "CPU update of VM recommended only for large BAR system\n"); |
2957 | ||
108b4d92 GB |
2958 | if (vm->use_cpu_for_update) |
2959 | vm->update_funcs = &amdgpu_vm_cpu_funcs; | |
2960 | else | |
2961 | vm->update_funcs = &amdgpu_vm_sdma_funcs; | |
2962 | dma_fence_put(vm->last_update); | |
2963 | vm->last_update = NULL; | |
f43ef951 | 2964 | vm->is_compute_context = true; |
108b4d92 | 2965 | |
b236fa1d FK |
2966 | if (vm->pasid) { |
2967 | unsigned long flags; | |
2968 | ||
2969 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2970 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2971 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2972 | ||
1685b01a OZ |
2973 | /* Free the original amdgpu allocated pasid |
2974 | * Will be replaced with kfd allocated pasid | |
2975 | */ | |
2976 | amdgpu_pasid_free(vm->pasid); | |
b236fa1d FK |
2977 | vm->pasid = 0; |
2978 | } | |
2979 | ||
b5d21aac SL |
2980 | /* Free the shadow bo for compute VM */ |
2981 | amdgpu_bo_unref(&vm->root.base.bo->shadow); | |
2982 | ||
1685b01a OZ |
2983 | if (pasid) |
2984 | vm->pasid = pasid; | |
2985 | ||
2986 | goto unreserve_bo; | |
2987 | ||
2988 | free_idr: | |
2989 | if (pasid) { | |
2990 | unsigned long flags; | |
2991 | ||
2992 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2993 | idr_remove(&adev->vm_manager.pasid_idr, pasid); | |
2994 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2995 | } | |
2996 | unreserve_bo: | |
b236fa1d FK |
2997 | amdgpu_bo_unreserve(vm->root.base.bo); |
2998 | return r; | |
2999 | } | |
3000 | ||
bf47afba OZ |
3001 | /** |
3002 | * amdgpu_vm_release_compute - release a compute vm | |
3003 | * @adev: amdgpu_device pointer | |
3004 | * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute | |
3005 | * | |
3006 | * This is a correspondant of amdgpu_vm_make_compute. It decouples compute | |
3007 | * pasid from vm. Compute should stop use of vm after this call. | |
3008 | */ | |
3009 | void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
3010 | { | |
3011 | if (vm->pasid) { | |
3012 | unsigned long flags; | |
3013 | ||
3014 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3015 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3016 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3017 | } | |
3018 | vm->pasid = 0; | |
f43ef951 | 3019 | vm->is_compute_context = false; |
bf47afba OZ |
3020 | } |
3021 | ||
d38ceaf9 AD |
3022 | /** |
3023 | * amdgpu_vm_fini - tear down a vm instance | |
3024 | * | |
3025 | * @adev: amdgpu_device pointer | |
3026 | * @vm: requested vm | |
3027 | * | |
8843dbbb | 3028 | * Tear down @vm. |
d38ceaf9 AD |
3029 | * Unbind the VM and remove all bos from the vm bo list |
3030 | */ | |
3031 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
3032 | { | |
3033 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
132f34e4 | 3034 | bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt; |
2642cf11 | 3035 | struct amdgpu_bo *root; |
b65709a9 | 3036 | int i; |
d38ceaf9 | 3037 | |
ede0dd86 FK |
3038 | amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm); |
3039 | ||
b65709a9 CK |
3040 | root = amdgpu_bo_ref(vm->root.base.bo); |
3041 | amdgpu_bo_reserve(root, true); | |
02208441 FK |
3042 | if (vm->pasid) { |
3043 | unsigned long flags; | |
3044 | ||
3045 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3046 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3047 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
b65709a9 | 3048 | vm->pasid = 0; |
02208441 FK |
3049 | } |
3050 | ||
90b69cdc CK |
3051 | dma_fence_wait(vm->last_direct, false); |
3052 | dma_fence_put(vm->last_direct); | |
3053 | dma_fence_wait(vm->last_delayed, false); | |
3054 | dma_fence_put(vm->last_delayed); | |
3055 | ||
ee8bcc23 PP |
3056 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { |
3057 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { | |
3058 | amdgpu_vm_prt_fini(adev, vm); | |
3059 | prt_fini_needed = false; | |
3060 | } | |
3061 | ||
3062 | list_del(&mapping->list); | |
3063 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); | |
3064 | } | |
3065 | ||
b65709a9 CK |
3066 | amdgpu_vm_free_pts(adev, vm, NULL); |
3067 | amdgpu_bo_unreserve(root); | |
3068 | amdgpu_bo_unref(&root); | |
3069 | WARN_ON(vm->root.base.bo); | |
3070 | ||
a2cf3247 CK |
3071 | drm_sched_entity_destroy(&vm->direct); |
3072 | drm_sched_entity_destroy(&vm->delayed); | |
2bd9ccfa | 3073 | |
f808c13f | 3074 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
d38ceaf9 AD |
3075 | dev_err(adev->dev, "still active bo inside vm\n"); |
3076 | } | |
f808c13f DB |
3077 | rbtree_postorder_for_each_entry_safe(mapping, tmp, |
3078 | &vm->va.rb_root, rb) { | |
0af5c656 CK |
3079 | /* Don't remove the mapping here, we don't want to trigger a |
3080 | * rebalance and the tree is about to be destroyed anyway. | |
3081 | */ | |
d38ceaf9 | 3082 | list_del(&mapping->list); |
d38ceaf9 AD |
3083 | kfree(mapping); |
3084 | } | |
d38ceaf9 | 3085 | |
d5884513 | 3086 | dma_fence_put(vm->last_update); |
1e9ef26f | 3087 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
620f774f | 3088 | amdgpu_vmid_free_reserved(adev, vm, i); |
d38ceaf9 | 3089 | } |
ea89f8c9 | 3090 | |
a9a78b32 CK |
3091 | /** |
3092 | * amdgpu_vm_manager_init - init the VM manager | |
3093 | * | |
3094 | * @adev: amdgpu_device pointer | |
3095 | * | |
3096 | * Initialize the VM manager structures | |
3097 | */ | |
3098 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
3099 | { | |
620f774f | 3100 | unsigned i; |
a9a78b32 | 3101 | |
620f774f | 3102 | amdgpu_vmid_mgr_init(adev); |
2d55e45a | 3103 | |
f54d1867 CW |
3104 | adev->vm_manager.fence_context = |
3105 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
3106 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
3107 | adev->vm_manager.seqno[i] = 0; | |
3108 | ||
284710fa | 3109 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 3110 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
3111 | |
3112 | /* If not overridden by the user, by default, only in large BAR systems | |
3113 | * Compute VM tables will be updated by CPU | |
3114 | */ | |
3115 | #ifdef CONFIG_X86_64 | |
3116 | if (amdgpu_vm_update_mode == -1) { | |
c8c5e569 | 3117 | if (amdgpu_gmc_vram_full_visible(&adev->gmc)) |
9a4b7d4c HK |
3118 | adev->vm_manager.vm_update_mode = |
3119 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
3120 | else | |
3121 | adev->vm_manager.vm_update_mode = 0; | |
3122 | } else | |
3123 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
3124 | #else | |
3125 | adev->vm_manager.vm_update_mode = 0; | |
3126 | #endif | |
3127 | ||
02208441 FK |
3128 | idr_init(&adev->vm_manager.pasid_idr); |
3129 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
df399b06 | 3130 | |
3131 | adev->vm_manager.xgmi_map_counter = 0; | |
3132 | mutex_init(&adev->vm_manager.lock_pstate); | |
a9a78b32 CK |
3133 | } |
3134 | ||
ea89f8c9 CK |
3135 | /** |
3136 | * amdgpu_vm_manager_fini - cleanup VM manager | |
3137 | * | |
3138 | * @adev: amdgpu_device pointer | |
3139 | * | |
3140 | * Cleanup the VM manager and free resources. | |
3141 | */ | |
3142 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
3143 | { | |
02208441 FK |
3144 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); |
3145 | idr_destroy(&adev->vm_manager.pasid_idr); | |
3146 | ||
620f774f | 3147 | amdgpu_vmid_mgr_fini(adev); |
ea89f8c9 | 3148 | } |
cfbcacf4 | 3149 | |
7fc48e59 AG |
3150 | /** |
3151 | * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs. | |
3152 | * | |
3153 | * @dev: drm device pointer | |
3154 | * @data: drm_amdgpu_vm | |
3155 | * @filp: drm file pointer | |
3156 | * | |
3157 | * Returns: | |
3158 | * 0 for success, -errno for errors. | |
3159 | */ | |
cfbcacf4 CZ |
3160 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
3161 | { | |
3162 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
3163 | struct amdgpu_device *adev = dev->dev_private; |
3164 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
3165 | int r; | |
cfbcacf4 CZ |
3166 | |
3167 | switch (args->in.op) { | |
3168 | case AMDGPU_VM_OP_RESERVE_VMID: | |
fc39d903 CK |
3169 | /* We only have requirement to reserve vmid from gfxhub */ |
3170 | r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, | |
3171 | AMDGPU_GFXHUB_0); | |
1e9ef26f CZ |
3172 | if (r) |
3173 | return r; | |
3174 | break; | |
cfbcacf4 | 3175 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
a2d15ed7 | 3176 | amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0); |
cfbcacf4 CZ |
3177 | break; |
3178 | default: | |
3179 | return -EINVAL; | |
3180 | } | |
3181 | ||
3182 | return 0; | |
3183 | } | |
2aa37bf5 AG |
3184 | |
3185 | /** | |
3186 | * amdgpu_vm_get_task_info - Extracts task info for a PASID. | |
3187 | * | |
989edc69 | 3188 | * @adev: drm device pointer |
2aa37bf5 AG |
3189 | * @pasid: PASID identifier for VM |
3190 | * @task_info: task_info to fill. | |
3191 | */ | |
3192 | void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid, | |
3193 | struct amdgpu_task_info *task_info) | |
3194 | { | |
3195 | struct amdgpu_vm *vm; | |
0a5f49cb | 3196 | unsigned long flags; |
2aa37bf5 | 3197 | |
0a5f49cb | 3198 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); |
2aa37bf5 AG |
3199 | |
3200 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3201 | if (vm) | |
3202 | *task_info = vm->task_info; | |
3203 | ||
0a5f49cb | 3204 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); |
2aa37bf5 AG |
3205 | } |
3206 | ||
3207 | /** | |
3208 | * amdgpu_vm_set_task_info - Sets VMs task info. | |
3209 | * | |
3210 | * @vm: vm for which to set the info | |
3211 | */ | |
3212 | void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) | |
3213 | { | |
fc39d903 CK |
3214 | if (vm->task_info.pid) |
3215 | return; | |
2aa37bf5 | 3216 | |
fc39d903 CK |
3217 | vm->task_info.pid = current->pid; |
3218 | get_task_comm(vm->task_info.task_name, current); | |
3219 | ||
3220 | if (current->group_leader->mm != current->mm) | |
3221 | return; | |
3222 | ||
3223 | vm->task_info.tgid = current->group_leader->pid; | |
3224 | get_task_comm(vm->task_info.process_name, current->group_leader); | |
2aa37bf5 | 3225 | } |
ec671737 CK |
3226 | |
3227 | /** | |
3228 | * amdgpu_vm_handle_fault - graceful handling of VM faults. | |
3229 | * @adev: amdgpu device pointer | |
3230 | * @pasid: PASID of the VM | |
3231 | * @addr: Address of the fault | |
3232 | * | |
3233 | * Try to gracefully handle a VM fault. Return true if the fault was handled and | |
3234 | * shouldn't be reported any more. | |
3235 | */ | |
3236 | bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, unsigned int pasid, | |
3237 | uint64_t addr) | |
3238 | { | |
3239 | struct amdgpu_bo *root; | |
3240 | uint64_t value, flags; | |
3241 | struct amdgpu_vm *vm; | |
3242 | long r; | |
3243 | ||
3244 | spin_lock(&adev->vm_manager.pasid_lock); | |
3245 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3246 | if (vm) | |
3247 | root = amdgpu_bo_ref(vm->root.base.bo); | |
3248 | else | |
3249 | root = NULL; | |
3250 | spin_unlock(&adev->vm_manager.pasid_lock); | |
3251 | ||
3252 | if (!root) | |
3253 | return false; | |
3254 | ||
3255 | r = amdgpu_bo_reserve(root, true); | |
3256 | if (r) | |
3257 | goto error_unref; | |
3258 | ||
3259 | /* Double check that the VM still exists */ | |
3260 | spin_lock(&adev->vm_manager.pasid_lock); | |
3261 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3262 | if (vm && vm->root.base.bo != root) | |
3263 | vm = NULL; | |
3264 | spin_unlock(&adev->vm_manager.pasid_lock); | |
3265 | if (!vm) | |
3266 | goto error_unlock; | |
3267 | ||
3268 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
3269 | flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED | | |
3270 | AMDGPU_PTE_SYSTEM; | |
3271 | ||
b4672c8a AS |
3272 | if (vm->is_compute_context) { |
3273 | /* Intentionally setting invalid PTE flag | |
3274 | * combination to force a no-retry-fault | |
3275 | */ | |
3276 | flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | | |
3277 | AMDGPU_PTE_TF; | |
3278 | value = 0; | |
3279 | ||
3280 | } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) { | |
ec671737 CK |
3281 | /* Redirect the access to the dummy page */ |
3282 | value = adev->dummy_page_addr; | |
3283 | flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE | | |
3284 | AMDGPU_PTE_WRITEABLE; | |
b4672c8a | 3285 | |
ec671737 CK |
3286 | } else { |
3287 | /* Let the hw retry silently on the PTE */ | |
3288 | value = 0; | |
3289 | } | |
3290 | ||
3291 | r = amdgpu_vm_bo_update_mapping(adev, vm, true, NULL, addr, addr + 1, | |
3292 | flags, value, NULL, NULL); | |
3293 | if (r) | |
3294 | goto error_unlock; | |
3295 | ||
3296 | r = amdgpu_vm_update_pdes(adev, vm, true); | |
3297 | ||
3298 | error_unlock: | |
3299 | amdgpu_bo_unreserve(root); | |
3300 | if (r < 0) | |
3301 | DRM_ERROR("Can't handle page fault (%ld)\n", r); | |
3302 | ||
3303 | error_unref: | |
3304 | amdgpu_bo_unref(&root); | |
3305 | ||
3306 | return false; | |
3307 | } |