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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
02208441 | 30 | #include <linux/idr.h> |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "amdgpu_trace.h" | |
ede0dd86 | 35 | #include "amdgpu_amdkfd.h" |
c8c5e569 | 36 | #include "amdgpu_gmc.h" |
d38ceaf9 | 37 | |
7fc48e59 AG |
38 | /** |
39 | * DOC: GPUVM | |
40 | * | |
d38ceaf9 AD |
41 | * GPUVM is similar to the legacy gart on older asics, however |
42 | * rather than there being a single global gart table | |
43 | * for the entire GPU, there are multiple VM page tables active | |
44 | * at any given time. The VM page tables can contain a mix | |
45 | * vram pages and system memory pages and system memory pages | |
46 | * can be mapped as snooped (cached system pages) or unsnooped | |
47 | * (uncached system pages). | |
48 | * Each VM has an ID associated with it and there is a page table | |
49 | * associated with each VMID. When execting a command buffer, | |
50 | * the kernel tells the the ring what VMID to use for that command | |
51 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
52 | * The userspace drivers maintain their own address space and the kernel | |
53 | * sets up their pages tables accordingly when they submit their | |
54 | * command buffers and a VMID is assigned. | |
55 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
56 | * SI supports 16. | |
57 | */ | |
58 | ||
a9f87f64 CK |
59 | #define START(node) ((node)->start) |
60 | #define LAST(node) ((node)->last) | |
61 | ||
62 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
63 | START, LAST, static, amdgpu_vm_it) | |
64 | ||
65 | #undef START | |
66 | #undef LAST | |
67 | ||
7fc48e59 AG |
68 | /** |
69 | * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback | |
70 | */ | |
284710fa | 71 | struct amdgpu_prt_cb { |
7fc48e59 AG |
72 | |
73 | /** | |
74 | * @adev: amdgpu device | |
75 | */ | |
284710fa | 76 | struct amdgpu_device *adev; |
7fc48e59 AG |
77 | |
78 | /** | |
79 | * @cb: callback | |
80 | */ | |
284710fa CK |
81 | struct dma_fence_cb cb; |
82 | }; | |
83 | ||
50783147 CK |
84 | /** |
85 | * amdgpu_vm_level_shift - return the addr shift for each level | |
86 | * | |
87 | * @adev: amdgpu_device pointer | |
7fc48e59 | 88 | * @level: VMPT level |
50783147 | 89 | * |
7fc48e59 AG |
90 | * Returns: |
91 | * The number of bits the pfn needs to be right shifted for a level. | |
50783147 CK |
92 | */ |
93 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
94 | unsigned level) | |
95 | { | |
196f7489 CZ |
96 | unsigned shift = 0xff; |
97 | ||
98 | switch (level) { | |
99 | case AMDGPU_VM_PDB2: | |
100 | case AMDGPU_VM_PDB1: | |
101 | case AMDGPU_VM_PDB0: | |
102 | shift = 9 * (AMDGPU_VM_PDB0 - level) + | |
50783147 | 103 | adev->vm_manager.block_size; |
196f7489 CZ |
104 | break; |
105 | case AMDGPU_VM_PTB: | |
106 | shift = 0; | |
107 | break; | |
108 | default: | |
109 | dev_err(adev->dev, "the level%d isn't supported.\n", level); | |
110 | } | |
111 | ||
112 | return shift; | |
50783147 CK |
113 | } |
114 | ||
d38ceaf9 | 115 | /** |
72a7ec5c | 116 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
117 | * |
118 | * @adev: amdgpu_device pointer | |
7fc48e59 | 119 | * @level: VMPT level |
d38ceaf9 | 120 | * |
7fc48e59 AG |
121 | * Returns: |
122 | * The number of entries in a page directory or page table. | |
d38ceaf9 | 123 | */ |
72a7ec5c CK |
124 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
125 | unsigned level) | |
d38ceaf9 | 126 | { |
196f7489 CZ |
127 | unsigned shift = amdgpu_vm_level_shift(adev, |
128 | adev->vm_manager.root_level); | |
0410c5e5 | 129 | |
196f7489 | 130 | if (level == adev->vm_manager.root_level) |
72a7ec5c | 131 | /* For the root directory */ |
9ce2b991 | 132 | return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift; |
196f7489 | 133 | else if (level != AMDGPU_VM_PTB) |
0410c5e5 CK |
134 | /* Everything in between */ |
135 | return 512; | |
136 | else | |
72a7ec5c | 137 | /* For the page tables on the leaves */ |
36b32a68 | 138 | return AMDGPU_VM_PTE_COUNT(adev); |
d38ceaf9 AD |
139 | } |
140 | ||
780637cb CK |
141 | /** |
142 | * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD | |
143 | * | |
144 | * @adev: amdgpu_device pointer | |
145 | * | |
146 | * Returns: | |
147 | * The number of entries in the root page directory which needs the ATS setting. | |
148 | */ | |
149 | static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev) | |
150 | { | |
151 | unsigned shift; | |
152 | ||
153 | shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level); | |
154 | return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT); | |
155 | } | |
156 | ||
cb90b97b CK |
157 | /** |
158 | * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT | |
159 | * | |
160 | * @adev: amdgpu_device pointer | |
161 | * @level: VMPT level | |
162 | * | |
163 | * Returns: | |
164 | * The mask to extract the entry number of a PD/PT from an address. | |
165 | */ | |
166 | static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev, | |
167 | unsigned int level) | |
168 | { | |
169 | if (level <= adev->vm_manager.root_level) | |
170 | return 0xffffffff; | |
171 | else if (level != AMDGPU_VM_PTB) | |
172 | return 0x1ff; | |
173 | else | |
174 | return AMDGPU_VM_PTE_COUNT(adev) - 1; | |
175 | } | |
176 | ||
d38ceaf9 | 177 | /** |
72a7ec5c | 178 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
179 | * |
180 | * @adev: amdgpu_device pointer | |
7fc48e59 | 181 | * @level: VMPT level |
d38ceaf9 | 182 | * |
7fc48e59 AG |
183 | * Returns: |
184 | * The size of the BO for a page directory or page table in bytes. | |
d38ceaf9 | 185 | */ |
72a7ec5c | 186 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 187 | { |
72a7ec5c | 188 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
189 | } |
190 | ||
bcdc9fd6 CK |
191 | /** |
192 | * amdgpu_vm_bo_evicted - vm_bo is evicted | |
193 | * | |
194 | * @vm_bo: vm_bo which is evicted | |
195 | * | |
196 | * State for PDs/PTs and per VM BOs which are not at the location they should | |
197 | * be. | |
198 | */ | |
199 | static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) | |
200 | { | |
201 | struct amdgpu_vm *vm = vm_bo->vm; | |
202 | struct amdgpu_bo *bo = vm_bo->bo; | |
203 | ||
204 | vm_bo->moved = true; | |
205 | if (bo->tbo.type == ttm_bo_type_kernel) | |
206 | list_move(&vm_bo->vm_status, &vm->evicted); | |
207 | else | |
208 | list_move_tail(&vm_bo->vm_status, &vm->evicted); | |
209 | } | |
210 | ||
211 | /** | |
212 | * amdgpu_vm_bo_relocated - vm_bo is reloacted | |
213 | * | |
214 | * @vm_bo: vm_bo which is relocated | |
215 | * | |
216 | * State for PDs/PTs which needs to update their parent PD. | |
217 | */ | |
218 | static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) | |
219 | { | |
220 | list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); | |
221 | } | |
222 | ||
223 | /** | |
224 | * amdgpu_vm_bo_moved - vm_bo is moved | |
225 | * | |
226 | * @vm_bo: vm_bo which is moved | |
227 | * | |
228 | * State for per VM BOs which are moved, but that change is not yet reflected | |
229 | * in the page tables. | |
230 | */ | |
231 | static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) | |
232 | { | |
233 | list_move(&vm_bo->vm_status, &vm_bo->vm->moved); | |
234 | } | |
235 | ||
236 | /** | |
237 | * amdgpu_vm_bo_idle - vm_bo is idle | |
238 | * | |
239 | * @vm_bo: vm_bo which is now idle | |
240 | * | |
241 | * State for PDs/PTs and per VM BOs which have gone through the state machine | |
242 | * and are now idle. | |
243 | */ | |
244 | static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) | |
245 | { | |
246 | list_move(&vm_bo->vm_status, &vm_bo->vm->idle); | |
247 | vm_bo->moved = false; | |
248 | } | |
249 | ||
250 | /** | |
251 | * amdgpu_vm_bo_invalidated - vm_bo is invalidated | |
252 | * | |
253 | * @vm_bo: vm_bo which is now invalidated | |
254 | * | |
255 | * State for normal BOs which are invalidated and that change not yet reflected | |
256 | * in the PTs. | |
257 | */ | |
258 | static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) | |
259 | { | |
260 | spin_lock(&vm_bo->vm->invalidated_lock); | |
261 | list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated); | |
262 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
263 | } | |
264 | ||
265 | /** | |
266 | * amdgpu_vm_bo_done - vm_bo is done | |
267 | * | |
268 | * @vm_bo: vm_bo which is now done | |
269 | * | |
270 | * State for normal BOs which are invalidated and that change has been updated | |
271 | * in the PTs. | |
272 | */ | |
273 | static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) | |
274 | { | |
275 | spin_lock(&vm_bo->vm->invalidated_lock); | |
276 | list_del_init(&vm_bo->vm_status); | |
277 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
278 | } | |
279 | ||
c460f8a6 CK |
280 | /** |
281 | * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm | |
282 | * | |
283 | * @base: base structure for tracking BO usage in a VM | |
284 | * @vm: vm to which bo is to be added | |
285 | * @bo: amdgpu buffer object | |
286 | * | |
287 | * Initialize a bo_va_base structure and add it to the appropriate lists | |
288 | * | |
289 | */ | |
290 | static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, | |
291 | struct amdgpu_vm *vm, | |
292 | struct amdgpu_bo *bo) | |
293 | { | |
294 | base->vm = vm; | |
295 | base->bo = bo; | |
646b9025 | 296 | base->next = NULL; |
c460f8a6 CK |
297 | INIT_LIST_HEAD(&base->vm_status); |
298 | ||
299 | if (!bo) | |
300 | return; | |
646b9025 CK |
301 | base->next = bo->vm_bo; |
302 | bo->vm_bo = base; | |
c460f8a6 CK |
303 | |
304 | if (bo->tbo.resv != vm->root.base.bo->tbo.resv) | |
305 | return; | |
306 | ||
307 | vm->bulk_moveable = false; | |
308 | if (bo->tbo.type == ttm_bo_type_kernel) | |
bcdc9fd6 | 309 | amdgpu_vm_bo_relocated(base); |
c460f8a6 | 310 | else |
bcdc9fd6 | 311 | amdgpu_vm_bo_idle(base); |
c460f8a6 CK |
312 | |
313 | if (bo->preferred_domains & | |
314 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)) | |
315 | return; | |
316 | ||
317 | /* | |
318 | * we checked all the prerequisites, but it looks like this per vm bo | |
319 | * is currently evicted. add the bo to the evicted list to make sure it | |
320 | * is validated on next vm use to avoid fault. | |
321 | * */ | |
bcdc9fd6 | 322 | amdgpu_vm_bo_evicted(base); |
c460f8a6 CK |
323 | } |
324 | ||
ba79fde4 CK |
325 | /** |
326 | * amdgpu_vm_pt_parent - get the parent page directory | |
327 | * | |
328 | * @pt: child page table | |
329 | * | |
330 | * Helper to get the parent entry for the child page table. NULL if we are at | |
331 | * the root page directory. | |
332 | */ | |
333 | static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt) | |
334 | { | |
335 | struct amdgpu_bo *parent = pt->base.bo->parent; | |
336 | ||
337 | if (!parent) | |
338 | return NULL; | |
339 | ||
646b9025 | 340 | return container_of(parent->vm_bo, struct amdgpu_vm_pt, base); |
ba79fde4 CK |
341 | } |
342 | ||
73633e32 CK |
343 | /** |
344 | * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt | |
345 | */ | |
346 | struct amdgpu_vm_pt_cursor { | |
347 | uint64_t pfn; | |
348 | struct amdgpu_vm_pt *parent; | |
349 | struct amdgpu_vm_pt *entry; | |
350 | unsigned level; | |
351 | }; | |
352 | ||
353 | /** | |
354 | * amdgpu_vm_pt_start - start PD/PT walk | |
355 | * | |
356 | * @adev: amdgpu_device pointer | |
357 | * @vm: amdgpu_vm structure | |
358 | * @start: start address of the walk | |
359 | * @cursor: state to initialize | |
360 | * | |
361 | * Initialize a amdgpu_vm_pt_cursor to start a walk. | |
362 | */ | |
363 | static void amdgpu_vm_pt_start(struct amdgpu_device *adev, | |
364 | struct amdgpu_vm *vm, uint64_t start, | |
365 | struct amdgpu_vm_pt_cursor *cursor) | |
366 | { | |
367 | cursor->pfn = start; | |
368 | cursor->parent = NULL; | |
369 | cursor->entry = &vm->root; | |
370 | cursor->level = adev->vm_manager.root_level; | |
371 | } | |
372 | ||
373 | /** | |
374 | * amdgpu_vm_pt_descendant - go to child node | |
375 | * | |
376 | * @adev: amdgpu_device pointer | |
377 | * @cursor: current state | |
378 | * | |
379 | * Walk to the child node of the current node. | |
380 | * Returns: | |
381 | * True if the walk was possible, false otherwise. | |
382 | */ | |
383 | static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev, | |
384 | struct amdgpu_vm_pt_cursor *cursor) | |
385 | { | |
cb90b97b | 386 | unsigned mask, shift, idx; |
73633e32 CK |
387 | |
388 | if (!cursor->entry->entries) | |
389 | return false; | |
390 | ||
391 | BUG_ON(!cursor->entry->base.bo); | |
cb90b97b | 392 | mask = amdgpu_vm_entries_mask(adev, cursor->level); |
73633e32 CK |
393 | shift = amdgpu_vm_level_shift(adev, cursor->level); |
394 | ||
395 | ++cursor->level; | |
cb90b97b | 396 | idx = (cursor->pfn >> shift) & mask; |
73633e32 CK |
397 | cursor->parent = cursor->entry; |
398 | cursor->entry = &cursor->entry->entries[idx]; | |
399 | return true; | |
400 | } | |
401 | ||
402 | /** | |
403 | * amdgpu_vm_pt_sibling - go to sibling node | |
404 | * | |
405 | * @adev: amdgpu_device pointer | |
406 | * @cursor: current state | |
407 | * | |
408 | * Walk to the sibling node of the current node. | |
409 | * Returns: | |
410 | * True if the walk was possible, false otherwise. | |
411 | */ | |
412 | static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev, | |
413 | struct amdgpu_vm_pt_cursor *cursor) | |
414 | { | |
415 | unsigned shift, num_entries; | |
416 | ||
417 | /* Root doesn't have a sibling */ | |
418 | if (!cursor->parent) | |
419 | return false; | |
420 | ||
421 | /* Go to our parents and see if we got a sibling */ | |
422 | shift = amdgpu_vm_level_shift(adev, cursor->level - 1); | |
423 | num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1); | |
424 | ||
425 | if (cursor->entry == &cursor->parent->entries[num_entries - 1]) | |
426 | return false; | |
427 | ||
428 | cursor->pfn += 1ULL << shift; | |
429 | cursor->pfn &= ~((1ULL << shift) - 1); | |
430 | ++cursor->entry; | |
431 | return true; | |
432 | } | |
433 | ||
434 | /** | |
435 | * amdgpu_vm_pt_ancestor - go to parent node | |
436 | * | |
437 | * @cursor: current state | |
438 | * | |
439 | * Walk to the parent node of the current node. | |
440 | * Returns: | |
441 | * True if the walk was possible, false otherwise. | |
442 | */ | |
443 | static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor) | |
444 | { | |
445 | if (!cursor->parent) | |
446 | return false; | |
447 | ||
448 | --cursor->level; | |
449 | cursor->entry = cursor->parent; | |
450 | cursor->parent = amdgpu_vm_pt_parent(cursor->parent); | |
451 | return true; | |
452 | } | |
453 | ||
454 | /** | |
455 | * amdgpu_vm_pt_next - get next PD/PT in hieratchy | |
456 | * | |
457 | * @adev: amdgpu_device pointer | |
458 | * @cursor: current state | |
459 | * | |
460 | * Walk the PD/PT tree to the next node. | |
461 | */ | |
462 | static void amdgpu_vm_pt_next(struct amdgpu_device *adev, | |
463 | struct amdgpu_vm_pt_cursor *cursor) | |
464 | { | |
465 | /* First try a newborn child */ | |
466 | if (amdgpu_vm_pt_descendant(adev, cursor)) | |
467 | return; | |
468 | ||
469 | /* If that didn't worked try to find a sibling */ | |
470 | while (!amdgpu_vm_pt_sibling(adev, cursor)) { | |
471 | /* No sibling, go to our parents and grandparents */ | |
472 | if (!amdgpu_vm_pt_ancestor(cursor)) { | |
473 | cursor->pfn = ~0ll; | |
474 | return; | |
475 | } | |
476 | } | |
477 | } | |
478 | ||
73633e32 CK |
479 | /** |
480 | * amdgpu_vm_pt_first_dfs - start a deep first search | |
481 | * | |
482 | * @adev: amdgpu_device structure | |
483 | * @vm: amdgpu_vm structure | |
484 | * @cursor: state to initialize | |
485 | * | |
486 | * Starts a deep first traversal of the PD/PT tree. | |
487 | */ | |
488 | static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev, | |
489 | struct amdgpu_vm *vm, | |
e35fb064 | 490 | struct amdgpu_vm_pt_cursor *start, |
73633e32 CK |
491 | struct amdgpu_vm_pt_cursor *cursor) |
492 | { | |
e35fb064 CK |
493 | if (start) |
494 | *cursor = *start; | |
495 | else | |
496 | amdgpu_vm_pt_start(adev, vm, 0, cursor); | |
73633e32 CK |
497 | while (amdgpu_vm_pt_descendant(adev, cursor)); |
498 | } | |
499 | ||
e35fb064 CK |
500 | /** |
501 | * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue | |
502 | * | |
503 | * @start: starting point for the search | |
504 | * @entry: current entry | |
505 | * | |
506 | * Returns: | |
507 | * True when the search should continue, false otherwise. | |
508 | */ | |
509 | static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start, | |
510 | struct amdgpu_vm_pt *entry) | |
511 | { | |
512 | return entry && (!start || entry != start->entry); | |
513 | } | |
514 | ||
73633e32 CK |
515 | /** |
516 | * amdgpu_vm_pt_next_dfs - get the next node for a deep first search | |
517 | * | |
518 | * @adev: amdgpu_device structure | |
519 | * @cursor: current state | |
520 | * | |
521 | * Move the cursor to the next node in a deep first search. | |
522 | */ | |
523 | static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev, | |
524 | struct amdgpu_vm_pt_cursor *cursor) | |
525 | { | |
526 | if (!cursor->entry) | |
527 | return; | |
528 | ||
529 | if (!cursor->parent) | |
530 | cursor->entry = NULL; | |
531 | else if (amdgpu_vm_pt_sibling(adev, cursor)) | |
532 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
533 | else | |
534 | amdgpu_vm_pt_ancestor(cursor); | |
535 | } | |
536 | ||
537 | /** | |
538 | * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs | |
539 | */ | |
e35fb064 CK |
540 | #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \ |
541 | for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \ | |
73633e32 | 542 | (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\ |
e35fb064 CK |
543 | amdgpu_vm_pt_continue_dfs((start), (entry)); \ |
544 | (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor))) | |
73633e32 | 545 | |
d38ceaf9 | 546 | /** |
56467ebf | 547 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
548 | * |
549 | * @vm: vm providing the BOs | |
3c0eea6c | 550 | * @validated: head of validation list |
56467ebf | 551 | * @entry: entry to add |
d38ceaf9 AD |
552 | * |
553 | * Add the page directory to the list of BOs to | |
56467ebf | 554 | * validate for command submission. |
d38ceaf9 | 555 | */ |
56467ebf CK |
556 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
557 | struct list_head *validated, | |
558 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 559 | { |
56467ebf | 560 | entry->priority = 0; |
e83dfe4d | 561 | entry->tv.bo = &vm->root.base.bo->tbo; |
07daa8a0 CK |
562 | /* One for the VM updates, one for TTM and one for the CS job */ |
563 | entry->tv.num_shared = 3; | |
2f568dbd | 564 | entry->user_pages = NULL; |
56467ebf CK |
565 | list_add(&entry->tv.head, validated); |
566 | } | |
d38ceaf9 | 567 | |
b61857b5 CZ |
568 | void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo) |
569 | { | |
570 | struct amdgpu_bo *abo; | |
571 | struct amdgpu_vm_bo_base *bo_base; | |
572 | ||
573 | if (!amdgpu_bo_is_amdgpu_bo(bo)) | |
574 | return; | |
575 | ||
576 | if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT) | |
577 | return; | |
578 | ||
579 | abo = ttm_to_amdgpu_bo(bo); | |
580 | if (!abo->parent) | |
581 | return; | |
582 | for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) { | |
583 | struct amdgpu_vm *vm = bo_base->vm; | |
584 | ||
585 | if (abo->tbo.resv == vm->root.base.bo->tbo.resv) | |
586 | vm->bulk_moveable = false; | |
587 | } | |
588 | ||
589 | } | |
f921661b HR |
590 | /** |
591 | * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU | |
592 | * | |
593 | * @adev: amdgpu device pointer | |
594 | * @vm: vm providing the BOs | |
595 | * | |
596 | * Move all BOs to the end of LRU and remember their positions to put them | |
597 | * together. | |
598 | */ | |
599 | void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, | |
600 | struct amdgpu_vm *vm) | |
601 | { | |
602 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
603 | struct amdgpu_vm_bo_base *bo_base; | |
604 | ||
605 | if (vm->bulk_moveable) { | |
606 | spin_lock(&glob->lru_lock); | |
607 | ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move); | |
608 | spin_unlock(&glob->lru_lock); | |
609 | return; | |
610 | } | |
611 | ||
612 | memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move)); | |
613 | ||
614 | spin_lock(&glob->lru_lock); | |
615 | list_for_each_entry(bo_base, &vm->idle, vm_status) { | |
616 | struct amdgpu_bo *bo = bo_base->bo; | |
617 | ||
618 | if (!bo->parent) | |
619 | continue; | |
620 | ||
621 | ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move); | |
622 | if (bo->shadow) | |
623 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo, | |
624 | &vm->lru_bulk_move); | |
625 | } | |
626 | spin_unlock(&glob->lru_lock); | |
627 | ||
628 | vm->bulk_moveable = true; | |
629 | } | |
630 | ||
670fecc8 | 631 | /** |
f7da30d9 | 632 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
670fecc8 | 633 | * |
5a712a87 | 634 | * @adev: amdgpu device pointer |
56467ebf | 635 | * @vm: vm providing the BOs |
670fecc8 CK |
636 | * @validate: callback to do the validation |
637 | * @param: parameter for the validation callback | |
638 | * | |
639 | * Validate the page table BOs on command submission if neccessary. | |
7fc48e59 AG |
640 | * |
641 | * Returns: | |
642 | * Validation result. | |
670fecc8 | 643 | */ |
f7da30d9 CK |
644 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
645 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
646 | void *param) | |
670fecc8 | 647 | { |
91ccdd24 CK |
648 | struct amdgpu_vm_bo_base *bo_base, *tmp; |
649 | int r = 0; | |
670fecc8 | 650 | |
91ccdd24 CK |
651 | list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { |
652 | struct amdgpu_bo *bo = bo_base->bo; | |
670fecc8 | 653 | |
262b9c39 CK |
654 | r = validate(param, bo); |
655 | if (r) | |
656 | break; | |
670fecc8 | 657 | |
af4c0f65 | 658 | if (bo->tbo.type != ttm_bo_type_kernel) { |
bcdc9fd6 | 659 | amdgpu_vm_bo_moved(bo_base); |
af4c0f65 | 660 | } else { |
17cc5252 CK |
661 | if (vm->use_cpu_for_update) |
662 | r = amdgpu_bo_kmap(bo, NULL); | |
663 | else | |
664 | r = amdgpu_ttm_alloc_gart(&bo->tbo); | |
284dec43 CK |
665 | if (r) |
666 | break; | |
3d5fe658 CK |
667 | if (bo->shadow) { |
668 | r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo); | |
669 | if (r) | |
670 | break; | |
671 | } | |
bcdc9fd6 | 672 | amdgpu_vm_bo_relocated(bo_base); |
af4c0f65 | 673 | } |
670fecc8 CK |
674 | } |
675 | ||
91ccdd24 | 676 | return r; |
670fecc8 CK |
677 | } |
678 | ||
56467ebf | 679 | /** |
34d7be5d | 680 | * amdgpu_vm_ready - check VM is ready for updates |
56467ebf | 681 | * |
34d7be5d | 682 | * @vm: VM to check |
d38ceaf9 | 683 | * |
34d7be5d | 684 | * Check if all VM PDs/PTs are ready for updates |
7fc48e59 AG |
685 | * |
686 | * Returns: | |
687 | * True if eviction list is empty. | |
d38ceaf9 | 688 | */ |
3f3333f8 | 689 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
d38ceaf9 | 690 | { |
af4c0f65 | 691 | return list_empty(&vm->evicted); |
d711e139 CK |
692 | } |
693 | ||
13307f7e CK |
694 | /** |
695 | * amdgpu_vm_clear_bo - initially clear the PDs/PTs | |
696 | * | |
697 | * @adev: amdgpu_device pointer | |
7fc48e59 | 698 | * @vm: VM to clear BO from |
13307f7e | 699 | * @bo: BO to clear |
13307f7e CK |
700 | * |
701 | * Root PD needs to be reserved when calling this. | |
7fc48e59 AG |
702 | * |
703 | * Returns: | |
704 | * 0 on success, errno otherwise. | |
13307f7e CK |
705 | */ |
706 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
780637cb CK |
707 | struct amdgpu_vm *vm, |
708 | struct amdgpu_bo *bo) | |
13307f7e CK |
709 | { |
710 | struct ttm_operation_ctx ctx = { true, false }; | |
780637cb | 711 | unsigned level = adev->vm_manager.root_level; |
adc7e863 | 712 | struct amdgpu_vm_update_params params; |
780637cb | 713 | struct amdgpu_bo *ancestor = bo; |
4584312d | 714 | unsigned entries, ats_entries; |
4584312d | 715 | uint64_t addr; |
13307f7e CK |
716 | int r; |
717 | ||
780637cb CK |
718 | /* Figure out our place in the hierarchy */ |
719 | if (ancestor->parent) { | |
720 | ++level; | |
721 | while (ancestor->parent->parent) { | |
722 | ++level; | |
723 | ancestor = ancestor->parent; | |
724 | } | |
725 | } | |
726 | ||
4584312d | 727 | entries = amdgpu_bo_size(bo) / 8; |
780637cb CK |
728 | if (!vm->pte_support_ats) { |
729 | ats_entries = 0; | |
730 | ||
731 | } else if (!bo->parent) { | |
732 | ats_entries = amdgpu_vm_num_ats_entries(adev); | |
733 | ats_entries = min(ats_entries, entries); | |
734 | entries -= ats_entries; | |
4584312d | 735 | |
780637cb CK |
736 | } else { |
737 | struct amdgpu_vm_pt *pt; | |
738 | ||
739 | pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base); | |
740 | ats_entries = amdgpu_vm_num_ats_entries(adev); | |
741 | if ((pt - vm->root.entries) >= ats_entries) { | |
742 | ats_entries = 0; | |
4584312d CK |
743 | } else { |
744 | ats_entries = entries; | |
745 | entries = 0; | |
746 | } | |
13307f7e CK |
747 | } |
748 | ||
13307f7e CK |
749 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); |
750 | if (r) | |
83cd8397 | 751 | return r; |
13307f7e | 752 | |
284dec43 CK |
753 | r = amdgpu_ttm_alloc_gart(&bo->tbo); |
754 | if (r) | |
755 | return r; | |
756 | ||
83cd8397 CK |
757 | if (bo->shadow) { |
758 | r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement, | |
759 | &ctx); | |
760 | if (r) | |
761 | return r; | |
762 | ||
763 | r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo); | |
764 | if (r) | |
765 | return r; | |
766 | ||
767 | } | |
768 | ||
adc7e863 CK |
769 | memset(¶ms, 0, sizeof(params)); |
770 | params.adev = adev; | |
771 | params.vm = vm; | |
772 | ||
773 | r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_KFD, NULL); | |
13307f7e | 774 | if (r) |
83cd8397 | 775 | return r; |
13307f7e | 776 | |
adc7e863 CK |
777 | addr = 0; |
778 | if (ats_entries) { | |
779 | uint64_t ats_value; | |
83cd8397 | 780 | |
adc7e863 CK |
781 | ats_value = AMDGPU_PTE_DEFAULT_ATC; |
782 | if (level != AMDGPU_VM_PTB) | |
783 | ats_value |= AMDGPU_PDE_PTE; | |
4584312d | 784 | |
adc7e863 CK |
785 | r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries, |
786 | 0, ats_value); | |
787 | if (r) | |
788 | return r; | |
13307f7e | 789 | |
adc7e863 CK |
790 | addr += ats_entries * 8; |
791 | } | |
29e8357b | 792 | |
adc7e863 CK |
793 | if (entries) { |
794 | uint64_t value = 0; | |
13307f7e | 795 | |
adc7e863 CK |
796 | /* Workaround for fault priority problem on GMC9 */ |
797 | if (level == AMDGPU_VM_PTB && | |
798 | adev->asic_type >= CHIP_VEGA10) | |
799 | value = AMDGPU_PTE_EXECUTABLE; | |
e61736da | 800 | |
adc7e863 CK |
801 | r = vm->update_funcs->update(¶ms, bo, addr, 0, entries, |
802 | 0, value); | |
803 | if (r) | |
804 | return r; | |
805 | } | |
13307f7e | 806 | |
adc7e863 | 807 | return vm->update_funcs->commit(¶ms, NULL); |
13307f7e CK |
808 | } |
809 | ||
e21eb261 CK |
810 | /** |
811 | * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation | |
812 | * | |
813 | * @adev: amdgpu_device pointer | |
814 | * @vm: requesting vm | |
815 | * @bp: resulting BO allocation parameters | |
816 | */ | |
817 | static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
818 | int level, struct amdgpu_bo_param *bp) | |
819 | { | |
820 | memset(bp, 0, sizeof(*bp)); | |
821 | ||
822 | bp->size = amdgpu_vm_bo_size(adev, level); | |
823 | bp->byte_align = AMDGPU_GPU_PAGE_SIZE; | |
824 | bp->domain = AMDGPU_GEM_DOMAIN_VRAM; | |
284dec43 CK |
825 | bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain); |
826 | bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
827 | AMDGPU_GEM_CREATE_CPU_GTT_USWC; | |
e21eb261 CK |
828 | if (vm->use_cpu_for_update) |
829 | bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
03e9dee1 FK |
830 | else if (!vm->root.base.bo || vm->root.base.bo->shadow) |
831 | bp->flags |= AMDGPU_GEM_CREATE_SHADOW; | |
e21eb261 CK |
832 | bp->type = ttm_bo_type_kernel; |
833 | if (vm->root.base.bo) | |
834 | bp->resv = vm->root.base.bo->tbo.resv; | |
835 | } | |
836 | ||
663e4577 | 837 | /** |
98ae7f98 | 838 | * amdgpu_vm_alloc_pts - Allocate a specific page table |
663e4577 CK |
839 | * |
840 | * @adev: amdgpu_device pointer | |
841 | * @vm: VM to allocate page tables for | |
98ae7f98 | 842 | * @cursor: Which page table to allocate |
663e4577 | 843 | * |
98ae7f98 | 844 | * Make sure a specific page table or directory is allocated. |
7fc48e59 AG |
845 | * |
846 | * Returns: | |
98ae7f98 FK |
847 | * 1 if page table needed to be allocated, 0 if page table was already |
848 | * allocated, negative errno if an error occurred. | |
663e4577 | 849 | */ |
0ce15d6f CK |
850 | static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, |
851 | struct amdgpu_vm *vm, | |
852 | struct amdgpu_vm_pt_cursor *cursor) | |
663e4577 | 853 | { |
0ce15d6f CK |
854 | struct amdgpu_vm_pt *entry = cursor->entry; |
855 | struct amdgpu_bo_param bp; | |
d72a6887 | 856 | struct amdgpu_bo *pt; |
d72a6887 | 857 | int r; |
663e4577 | 858 | |
0ce15d6f CK |
859 | if (cursor->level < AMDGPU_VM_PTB && !entry->entries) { |
860 | unsigned num_entries; | |
663e4577 | 861 | |
0ce15d6f CK |
862 | num_entries = amdgpu_vm_num_entries(adev, cursor->level); |
863 | entry->entries = kvmalloc_array(num_entries, | |
864 | sizeof(*entry->entries), | |
865 | GFP_KERNEL | __GFP_ZERO); | |
866 | if (!entry->entries) | |
867 | return -ENOMEM; | |
4584312d CK |
868 | } |
869 | ||
0ce15d6f CK |
870 | if (entry->base.bo) |
871 | return 0; | |
d72a6887 | 872 | |
0ce15d6f | 873 | amdgpu_vm_bo_param(adev, vm, cursor->level, &bp); |
d72a6887 | 874 | |
0ce15d6f CK |
875 | r = amdgpu_bo_create(adev, &bp, &pt); |
876 | if (r) | |
877 | return r; | |
1e293037 | 878 | |
0ce15d6f CK |
879 | if (vm->use_cpu_for_update) { |
880 | r = amdgpu_bo_kmap(pt, NULL); | |
1e293037 CK |
881 | if (r) |
882 | goto error_free_pt; | |
d72a6887 CK |
883 | } |
884 | ||
0ce15d6f CK |
885 | /* Keep a reference to the root directory to avoid |
886 | * freeing them up in the wrong order. | |
887 | */ | |
888 | pt->parent = amdgpu_bo_ref(cursor->parent->base.bo); | |
889 | amdgpu_vm_bo_base_init(&entry->base, vm, pt); | |
890 | ||
891 | r = amdgpu_vm_clear_bo(adev, vm, pt); | |
892 | if (r) | |
893 | goto error_free_pt; | |
894 | ||
adc7e863 | 895 | return 0; |
d72a6887 CK |
896 | |
897 | error_free_pt: | |
898 | amdgpu_bo_unref(&pt->shadow); | |
899 | amdgpu_bo_unref(&pt); | |
900 | return r; | |
663e4577 CK |
901 | } |
902 | ||
e35fb064 CK |
903 | /** |
904 | * amdgpu_vm_free_table - fre one PD/PT | |
905 | * | |
906 | * @entry: PDE to free | |
907 | */ | |
908 | static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry) | |
909 | { | |
910 | if (entry->base.bo) { | |
911 | entry->base.bo->vm_bo = NULL; | |
912 | list_del(&entry->base.vm_status); | |
913 | amdgpu_bo_unref(&entry->base.bo->shadow); | |
914 | amdgpu_bo_unref(&entry->base.bo); | |
915 | } | |
916 | kvfree(entry->entries); | |
917 | entry->entries = NULL; | |
918 | } | |
919 | ||
229a37f8 CK |
920 | /** |
921 | * amdgpu_vm_free_pts - free PD/PT levels | |
922 | * | |
923 | * @adev: amdgpu device structure | |
769f846e | 924 | * @vm: amdgpu vm structure |
e35fb064 | 925 | * @start: optional cursor where to start freeing PDs/PTs |
229a37f8 CK |
926 | * |
927 | * Free the page directory or page table level and all sub levels. | |
928 | */ | |
929 | static void amdgpu_vm_free_pts(struct amdgpu_device *adev, | |
e35fb064 CK |
930 | struct amdgpu_vm *vm, |
931 | struct amdgpu_vm_pt_cursor *start) | |
229a37f8 CK |
932 | { |
933 | struct amdgpu_vm_pt_cursor cursor; | |
934 | struct amdgpu_vm_pt *entry; | |
935 | ||
e35fb064 | 936 | vm->bulk_moveable = false; |
229a37f8 | 937 | |
e35fb064 CK |
938 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) |
939 | amdgpu_vm_free_table(entry); | |
229a37f8 | 940 | |
e35fb064 CK |
941 | if (start) |
942 | amdgpu_vm_free_table(start->entry); | |
229a37f8 CK |
943 | } |
944 | ||
e59c0205 AX |
945 | /** |
946 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
947 | * | |
948 | * @adev: amdgpu_device pointer | |
949 | */ | |
950 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 951 | { |
a1255107 | 952 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
953 | bool has_compute_vm_bug; |
954 | struct amdgpu_ring *ring; | |
955 | int i; | |
93dcc37d | 956 | |
e59c0205 | 957 | has_compute_vm_bug = false; |
93dcc37d | 958 | |
2990a1fc | 959 | ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); |
e59c0205 AX |
960 | if (ip_block) { |
961 | /* Compute has a VM bug for GFX version < 7. | |
962 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
963 | if (ip_block->version->major <= 7) | |
964 | has_compute_vm_bug = true; | |
965 | else if (ip_block->version->major == 8) | |
966 | if (adev->gfx.mec_fw_version < 673) | |
967 | has_compute_vm_bug = true; | |
968 | } | |
93dcc37d | 969 | |
e59c0205 AX |
970 | for (i = 0; i < adev->num_rings; i++) { |
971 | ring = adev->rings[i]; | |
972 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
973 | /* only compute rings */ | |
974 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 975 | else |
e59c0205 | 976 | ring->has_compute_vm_bug = false; |
93dcc37d | 977 | } |
93dcc37d AD |
978 | } |
979 | ||
7fc48e59 AG |
980 | /** |
981 | * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job. | |
982 | * | |
983 | * @ring: ring on which the job will be submitted | |
984 | * @job: job to submit | |
985 | * | |
986 | * Returns: | |
987 | * True if sync is needed. | |
988 | */ | |
b9bf33d5 CZ |
989 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
990 | struct amdgpu_job *job) | |
e60f8db5 | 991 | { |
b9bf33d5 CZ |
992 | struct amdgpu_device *adev = ring->adev; |
993 | unsigned vmhub = ring->funcs->vmhub; | |
620f774f CK |
994 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
995 | struct amdgpu_vmid *id; | |
b9bf33d5 | 996 | bool gds_switch_needed; |
e59c0205 | 997 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 | 998 | |
c4f46f22 | 999 | if (job->vmid == 0) |
b9bf33d5 | 1000 | return false; |
c4f46f22 | 1001 | id = &id_mgr->ids[job->vmid]; |
b9bf33d5 CZ |
1002 | gds_switch_needed = ring->funcs->emit_gds_switch && ( |
1003 | id->gds_base != job->gds_base || | |
1004 | id->gds_size != job->gds_size || | |
1005 | id->gws_base != job->gws_base || | |
1006 | id->gws_size != job->gws_size || | |
1007 | id->oa_base != job->oa_base || | |
1008 | id->oa_size != job->oa_size); | |
e60f8db5 | 1009 | |
620f774f | 1010 | if (amdgpu_vmid_had_gpu_reset(adev, id)) |
b9bf33d5 | 1011 | return true; |
e60f8db5 | 1012 | |
bb37b67d | 1013 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
1014 | } |
1015 | ||
d38ceaf9 AD |
1016 | /** |
1017 | * amdgpu_vm_flush - hardware flush the vm | |
1018 | * | |
1019 | * @ring: ring to use for flush | |
00553cf8 | 1020 | * @job: related job |
7fc48e59 | 1021 | * @need_pipe_sync: is pipe sync needed |
d38ceaf9 | 1022 | * |
4ff37a83 | 1023 | * Emit a VM flush when it is necessary. |
7fc48e59 AG |
1024 | * |
1025 | * Returns: | |
1026 | * 0 on success, errno otherwise. | |
d38ceaf9 | 1027 | */ |
8fdf074f | 1028 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 1029 | { |
971fe9a9 | 1030 | struct amdgpu_device *adev = ring->adev; |
7645670d | 1031 | unsigned vmhub = ring->funcs->vmhub; |
620f774f | 1032 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
c4f46f22 | 1033 | struct amdgpu_vmid *id = &id_mgr->ids[job->vmid]; |
d564a06e | 1034 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
1035 | id->gds_base != job->gds_base || |
1036 | id->gds_size != job->gds_size || | |
1037 | id->gws_base != job->gws_base || | |
1038 | id->gws_size != job->gws_size || | |
1039 | id->oa_base != job->oa_base || | |
1040 | id->oa_size != job->oa_size); | |
de37e68a | 1041 | bool vm_flush_needed = job->vm_needs_flush; |
b3cd285f CK |
1042 | bool pasid_mapping_needed = id->pasid != job->pasid || |
1043 | !id->pasid_mapping || | |
1044 | !dma_fence_is_signaled(id->pasid_mapping); | |
1045 | struct dma_fence *fence = NULL; | |
c0e51931 | 1046 | unsigned patch_offset = 0; |
41d9eb2c | 1047 | int r; |
d564a06e | 1048 | |
620f774f | 1049 | if (amdgpu_vmid_had_gpu_reset(adev, id)) { |
f7d015b9 CK |
1050 | gds_switch_needed = true; |
1051 | vm_flush_needed = true; | |
b3cd285f | 1052 | pasid_mapping_needed = true; |
f7d015b9 | 1053 | } |
971fe9a9 | 1054 | |
b3cd285f | 1055 | gds_switch_needed &= !!ring->funcs->emit_gds_switch; |
d8de8260 AG |
1056 | vm_flush_needed &= !!ring->funcs->emit_vm_flush && |
1057 | job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET; | |
b3cd285f CK |
1058 | pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping && |
1059 | ring->funcs->emit_wreg; | |
1060 | ||
8fdf074f | 1061 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 1062 | return 0; |
41d9eb2c | 1063 | |
c0e51931 CK |
1064 | if (ring->funcs->init_cond_exec) |
1065 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 1066 | |
8fdf074f ML |
1067 | if (need_pipe_sync) |
1068 | amdgpu_ring_emit_pipeline_sync(ring); | |
1069 | ||
b3cd285f | 1070 | if (vm_flush_needed) { |
c4f46f22 | 1071 | trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr); |
c633c00b | 1072 | amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr); |
b3cd285f CK |
1073 | } |
1074 | ||
1075 | if (pasid_mapping_needed) | |
1076 | amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); | |
e9d672b2 | 1077 | |
b3cd285f | 1078 | if (vm_flush_needed || pasid_mapping_needed) { |
d240cd9e | 1079 | r = amdgpu_fence_emit(ring, &fence, 0); |
c0e51931 CK |
1080 | if (r) |
1081 | return r; | |
b3cd285f | 1082 | } |
e9d672b2 | 1083 | |
b3cd285f | 1084 | if (vm_flush_needed) { |
7645670d | 1085 | mutex_lock(&id_mgr->lock); |
c0e51931 | 1086 | dma_fence_put(id->last_flush); |
b3cd285f CK |
1087 | id->last_flush = dma_fence_get(fence); |
1088 | id->current_gpu_reset_count = | |
1089 | atomic_read(&adev->gpu_reset_counter); | |
7645670d | 1090 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 1091 | } |
e9d672b2 | 1092 | |
b3cd285f CK |
1093 | if (pasid_mapping_needed) { |
1094 | id->pasid = job->pasid; | |
1095 | dma_fence_put(id->pasid_mapping); | |
1096 | id->pasid_mapping = dma_fence_get(fence); | |
1097 | } | |
1098 | dma_fence_put(fence); | |
1099 | ||
7c4378f4 | 1100 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
1101 | id->gds_base = job->gds_base; |
1102 | id->gds_size = job->gds_size; | |
1103 | id->gws_base = job->gws_base; | |
1104 | id->gws_size = job->gws_size; | |
1105 | id->oa_base = job->oa_base; | |
1106 | id->oa_size = job->oa_size; | |
c4f46f22 | 1107 | amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base, |
c0e51931 CK |
1108 | job->gds_size, job->gws_base, |
1109 | job->gws_size, job->oa_base, | |
1110 | job->oa_size); | |
1111 | } | |
1112 | ||
1113 | if (ring->funcs->patch_cond_exec) | |
1114 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
1115 | ||
1116 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
1117 | if (ring->funcs->emit_switch_buffer) { | |
1118 | amdgpu_ring_emit_switch_buffer(ring); | |
1119 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 1120 | } |
41d9eb2c | 1121 | return 0; |
971fe9a9 CK |
1122 | } |
1123 | ||
d38ceaf9 AD |
1124 | /** |
1125 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
1126 | * | |
1127 | * @vm: requested vm | |
1128 | * @bo: requested buffer object | |
1129 | * | |
8843dbbb | 1130 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
1131 | * Search inside the @bos vm list for the requested vm |
1132 | * Returns the found bo_va or NULL if none is found | |
1133 | * | |
1134 | * Object has to be reserved! | |
7fc48e59 AG |
1135 | * |
1136 | * Returns: | |
1137 | * Found bo_va or NULL. | |
d38ceaf9 AD |
1138 | */ |
1139 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
1140 | struct amdgpu_bo *bo) | |
1141 | { | |
646b9025 | 1142 | struct amdgpu_vm_bo_base *base; |
d38ceaf9 | 1143 | |
646b9025 CK |
1144 | for (base = bo->vm_bo; base; base = base->next) { |
1145 | if (base->vm != vm) | |
1146 | continue; | |
1147 | ||
1148 | return container_of(base, struct amdgpu_bo_va, base); | |
d38ceaf9 AD |
1149 | } |
1150 | return NULL; | |
1151 | } | |
1152 | ||
d38ceaf9 | 1153 | /** |
b07c9d2a | 1154 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 1155 | * |
b07c9d2a | 1156 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
1157 | * @addr: the unmapped addr |
1158 | * | |
1159 | * Look up the physical address of the page that the pte resolves | |
7fc48e59 AG |
1160 | * to. |
1161 | * | |
1162 | * Returns: | |
1163 | * The pointer for the page table entry. | |
d38ceaf9 | 1164 | */ |
6dd09027 | 1165 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
1166 | { |
1167 | uint64_t result; | |
1168 | ||
de9ea7bd CK |
1169 | /* page table offset */ |
1170 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 1171 | |
de9ea7bd CK |
1172 | /* in case cpu page size != gpu page size*/ |
1173 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 1174 | |
b07c9d2a | 1175 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
1176 | |
1177 | return result; | |
1178 | } | |
1179 | ||
f8991bab | 1180 | /* |
6989f246 | 1181 | * amdgpu_vm_update_pde - update a single level in the hierarchy |
f8991bab | 1182 | * |
6989f246 | 1183 | * @param: parameters for the update |
f8991bab | 1184 | * @vm: requested vm |
194d2161 | 1185 | * @parent: parent directory |
6989f246 | 1186 | * @entry: entry to update |
f8991bab | 1187 | * |
6989f246 | 1188 | * Makes sure the requested entry in parent is up to date. |
f8991bab | 1189 | */ |
e6899d55 CK |
1190 | static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params, |
1191 | struct amdgpu_vm *vm, | |
1192 | struct amdgpu_vm_pt *parent, | |
1193 | struct amdgpu_vm_pt *entry) | |
d38ceaf9 | 1194 | { |
373ac645 | 1195 | struct amdgpu_bo *bo = parent->base.bo, *pbo; |
3de676d8 CK |
1196 | uint64_t pde, pt, flags; |
1197 | unsigned level; | |
d5fc5e82 | 1198 | |
373ac645 | 1199 | for (level = 0, pbo = bo->parent; pbo; ++level) |
3de676d8 CK |
1200 | pbo = pbo->parent; |
1201 | ||
196f7489 | 1202 | level += params->adev->vm_manager.root_level; |
24a8d289 | 1203 | amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags); |
373ac645 | 1204 | pde = (entry - parent->entries) * 8; |
e6899d55 | 1205 | return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags); |
d38ceaf9 AD |
1206 | } |
1207 | ||
92456b93 | 1208 | /* |
d4085ea9 | 1209 | * amdgpu_vm_invalidate_pds - mark all PDs as invalid |
92456b93 | 1210 | * |
7fc48e59 AG |
1211 | * @adev: amdgpu_device pointer |
1212 | * @vm: related vm | |
92456b93 CK |
1213 | * |
1214 | * Mark all PD level as invalid after an error. | |
1215 | */ | |
d4085ea9 CK |
1216 | static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev, |
1217 | struct amdgpu_vm *vm) | |
92456b93 | 1218 | { |
d4085ea9 CK |
1219 | struct amdgpu_vm_pt_cursor cursor; |
1220 | struct amdgpu_vm_pt *entry; | |
92456b93 | 1221 | |
e35fb064 | 1222 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry) |
d4085ea9 | 1223 | if (entry->base.bo && !entry->base.moved) |
bcdc9fd6 | 1224 | amdgpu_vm_bo_relocated(&entry->base); |
92456b93 CK |
1225 | } |
1226 | ||
194d2161 CK |
1227 | /* |
1228 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1229 | * | |
1230 | * @adev: amdgpu_device pointer | |
1231 | * @vm: requested vm | |
1232 | * | |
1233 | * Makes sure all directories are up to date. | |
7fc48e59 AG |
1234 | * |
1235 | * Returns: | |
1236 | * 0 for success, error for failure. | |
194d2161 CK |
1237 | */ |
1238 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1239 | struct amdgpu_vm *vm) | |
1240 | { | |
d1e29462 | 1241 | struct amdgpu_vm_update_params params; |
e6899d55 | 1242 | int r; |
92456b93 | 1243 | |
6989f246 CK |
1244 | if (list_empty(&vm->relocated)) |
1245 | return 0; | |
1246 | ||
6989f246 CK |
1247 | memset(¶ms, 0, sizeof(params)); |
1248 | params.adev = adev; | |
e6899d55 | 1249 | params.vm = vm; |
6989f246 | 1250 | |
e6899d55 CK |
1251 | r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_VM, NULL); |
1252 | if (r) | |
1253 | return r; | |
6989f246 | 1254 | |
ea09729c | 1255 | while (!list_empty(&vm->relocated)) { |
6989f246 | 1256 | struct amdgpu_vm_pt *pt, *entry; |
ea09729c | 1257 | |
ba79fde4 CK |
1258 | entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt, |
1259 | base.vm_status); | |
1260 | amdgpu_vm_bo_idle(&entry->base); | |
ea09729c | 1261 | |
ba79fde4 CK |
1262 | pt = amdgpu_vm_pt_parent(entry); |
1263 | if (!pt) | |
6989f246 | 1264 | continue; |
6989f246 | 1265 | |
e6899d55 | 1266 | r = amdgpu_vm_update_pde(¶ms, vm, pt, entry); |
6989f246 CK |
1267 | if (r) |
1268 | goto error; | |
68c62306 CK |
1269 | } |
1270 | ||
e6899d55 CK |
1271 | r = vm->update_funcs->commit(¶ms, &vm->last_update); |
1272 | if (r) | |
1273 | goto error; | |
6989f246 CK |
1274 | return 0; |
1275 | ||
1276 | error: | |
d4085ea9 | 1277 | amdgpu_vm_invalidate_pds(adev, vm); |
92456b93 | 1278 | return r; |
194d2161 CK |
1279 | } |
1280 | ||
cf2f0a37 | 1281 | /** |
e95b93ce | 1282 | * amdgpu_vm_update_flags - figure out flags for PTE updates |
cf2f0a37 | 1283 | * |
dfcd99f6 | 1284 | * Make sure to set the right flags for the PTEs at the desired level. |
cf2f0a37 | 1285 | */ |
d1e29462 | 1286 | static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params, |
e95b93ce CK |
1287 | struct amdgpu_bo *bo, unsigned level, |
1288 | uint64_t pe, uint64_t addr, | |
1289 | unsigned count, uint32_t incr, | |
1290 | uint64_t flags) | |
cf2f0a37 | 1291 | |
dfcd99f6 CK |
1292 | { |
1293 | if (level != AMDGPU_VM_PTB) { | |
cf2f0a37 | 1294 | flags |= AMDGPU_PDE_PTE; |
dfcd99f6 | 1295 | amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags); |
e95b93ce CK |
1296 | |
1297 | } else if (params->adev->asic_type >= CHIP_VEGA10 && | |
1298 | !(flags & AMDGPU_PTE_VALID) && | |
1299 | !(flags & AMDGPU_PTE_PRT)) { | |
1300 | ||
1301 | /* Workaround for fault priority problem on GMC9 */ | |
1302 | flags |= AMDGPU_PTE_EXECUTABLE; | |
cf2f0a37 AD |
1303 | } |
1304 | ||
c3546695 CK |
1305 | params->vm->update_funcs->update(params, bo, pe, addr, count, incr, |
1306 | flags); | |
dfcd99f6 CK |
1307 | } |
1308 | ||
1309 | /** | |
1310 | * amdgpu_vm_fragment - get fragment for PTEs | |
1311 | * | |
d1e29462 | 1312 | * @params: see amdgpu_vm_update_params definition |
dfcd99f6 CK |
1313 | * @start: first PTE to handle |
1314 | * @end: last PTE to handle | |
1315 | * @flags: hw mapping flags | |
1316 | * @frag: resulting fragment size | |
1317 | * @frag_end: end of this fragment | |
1318 | * | |
1319 | * Returns the first possible fragment for the start and end address. | |
1320 | */ | |
d1e29462 | 1321 | static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params, |
dfcd99f6 CK |
1322 | uint64_t start, uint64_t end, uint64_t flags, |
1323 | unsigned int *frag, uint64_t *frag_end) | |
1324 | { | |
1325 | /** | |
1326 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1327 | * field in the PTE. When this field is set to a non-zero value, page | |
1328 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1329 | * flags are considered valid for all PTEs within the fragment range | |
1330 | * and corresponding mappings are assumed to be physically contiguous. | |
1331 | * | |
1332 | * The L1 TLB can store a single PTE for the whole fragment, | |
1333 | * significantly increasing the space available for translation | |
1334 | * caching. This leads to large improvements in throughput when the | |
1335 | * TLB is under pressure. | |
1336 | * | |
1337 | * The L2 TLB distributes small and large fragments into two | |
1338 | * asymmetric partitions. The large fragment cache is significantly | |
1339 | * larger. Thus, we try to use large fragments wherever possible. | |
1340 | * Userspace can support this by aligning virtual base address and | |
1341 | * allocation size to the fragment size. | |
1b1d5c43 CK |
1342 | * |
1343 | * Starting with Vega10 the fragment size only controls the L1. The L2 | |
1344 | * is now directly feed with small/huge/giant pages from the walker. | |
dfcd99f6 | 1345 | */ |
1b1d5c43 CK |
1346 | unsigned max_frag; |
1347 | ||
1348 | if (params->adev->asic_type < CHIP_VEGA10) | |
1349 | max_frag = params->adev->vm_manager.fragment_size; | |
1350 | else | |
1351 | max_frag = 31; | |
dfcd99f6 CK |
1352 | |
1353 | /* system pages are non continuously */ | |
072b7a0b | 1354 | if (params->pages_addr) { |
dfcd99f6 CK |
1355 | *frag = 0; |
1356 | *frag_end = end; | |
ec5207c9 | 1357 | return; |
3cc1d3ea | 1358 | } |
cf2f0a37 | 1359 | |
dfcd99f6 CK |
1360 | /* This intentionally wraps around if no bit is set */ |
1361 | *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1); | |
1362 | if (*frag >= max_frag) { | |
1363 | *frag = max_frag; | |
1364 | *frag_end = end & ~((1ULL << max_frag) - 1); | |
1365 | } else { | |
1366 | *frag_end = start + (1 << *frag); | |
1367 | } | |
4e2cb640 CK |
1368 | } |
1369 | ||
d38ceaf9 AD |
1370 | /** |
1371 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1372 | * | |
d1e29462 | 1373 | * @params: see amdgpu_vm_update_params definition |
d38ceaf9 AD |
1374 | * @start: start of GPU address range |
1375 | * @end: end of GPU address range | |
677131a1 | 1376 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1377 | * @flags: mapping flags |
1378 | * | |
8843dbbb | 1379 | * Update the page tables in the range @start - @end. |
7fc48e59 AG |
1380 | * |
1381 | * Returns: | |
1382 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 | 1383 | */ |
d1e29462 | 1384 | static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, |
dfcd99f6 CK |
1385 | uint64_t start, uint64_t end, |
1386 | uint64_t dst, uint64_t flags) | |
d38ceaf9 | 1387 | { |
36b32a68 | 1388 | struct amdgpu_device *adev = params->adev; |
dfa70550 | 1389 | struct amdgpu_vm_pt_cursor cursor; |
dfcd99f6 CK |
1390 | uint64_t frag_start = start, frag_end; |
1391 | unsigned int frag; | |
0ce15d6f | 1392 | int r; |
dfcd99f6 CK |
1393 | |
1394 | /* figure out the initial fragment */ | |
1395 | amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end); | |
d38ceaf9 | 1396 | |
dfcd99f6 CK |
1397 | /* walk over the address space and update the PTs */ |
1398 | amdgpu_vm_pt_start(adev, params->vm, start, &cursor); | |
1399 | while (cursor.pfn < end) { | |
cb90b97b | 1400 | unsigned shift, parent_shift, mask; |
dfcd99f6 | 1401 | uint64_t incr, entry_end, pe_start; |
0ce15d6f | 1402 | struct amdgpu_bo *pt; |
cf2f0a37 | 1403 | |
0ce15d6f | 1404 | r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor); |
adc7e863 | 1405 | if (r) |
0ce15d6f CK |
1406 | return r; |
1407 | ||
1408 | pt = cursor.entry->base.bo; | |
4e2cb640 | 1409 | |
dfcd99f6 CK |
1410 | /* The root level can't be a huge page */ |
1411 | if (cursor.level == adev->vm_manager.root_level) { | |
1412 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1413 | return -ENOENT; | |
cf2f0a37 | 1414 | continue; |
dfa70550 | 1415 | } |
cf2f0a37 | 1416 | |
dfcd99f6 CK |
1417 | shift = amdgpu_vm_level_shift(adev, cursor.level); |
1418 | parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1); | |
8ce1f7e7 CK |
1419 | if (adev->asic_type < CHIP_VEGA10 && |
1420 | (flags & AMDGPU_PTE_VALID)) { | |
dfcd99f6 CK |
1421 | /* No huge page support before GMC v9 */ |
1422 | if (cursor.level != AMDGPU_VM_PTB) { | |
1423 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1424 | return -ENOENT; | |
1425 | continue; | |
1426 | } | |
1427 | } else if (frag < shift) { | |
1428 | /* We can't use this level when the fragment size is | |
1429 | * smaller than the address shift. Go to the next | |
1430 | * child entry and try again. | |
1431 | */ | |
1432 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1433 | return -ENOENT; | |
1434 | continue; | |
1954db15 FK |
1435 | } else if (frag >= parent_shift && |
1436 | cursor.level - 1 != adev->vm_manager.root_level) { | |
dfcd99f6 | 1437 | /* If the fragment size is even larger than the parent |
1954db15 FK |
1438 | * shift we should go up one level and check it again |
1439 | * unless one level up is the root level. | |
dfcd99f6 CK |
1440 | */ |
1441 | if (!amdgpu_vm_pt_ancestor(&cursor)) | |
1442 | return -ENOENT; | |
1443 | continue; | |
6849d47c RH |
1444 | } |
1445 | ||
dfcd99f6 | 1446 | /* Looks good so far, calculate parameters for the update */ |
9ce2b991 | 1447 | incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift; |
cb90b97b CK |
1448 | mask = amdgpu_vm_entries_mask(adev, cursor.level); |
1449 | pe_start = ((cursor.pfn >> shift) & mask) * 8; | |
9ce2b991 | 1450 | entry_end = (uint64_t)(mask + 1) << shift; |
dfcd99f6 CK |
1451 | entry_end += cursor.pfn & ~(entry_end - 1); |
1452 | entry_end = min(entry_end, end); | |
1453 | ||
1454 | do { | |
1455 | uint64_t upd_end = min(entry_end, frag_end); | |
1456 | unsigned nptes = (upd_end - frag_start) >> shift; | |
1457 | ||
e95b93ce CK |
1458 | amdgpu_vm_update_flags(params, pt, cursor.level, |
1459 | pe_start, dst, nptes, incr, | |
1460 | flags | AMDGPU_PTE_FRAG(frag)); | |
dfcd99f6 CK |
1461 | |
1462 | pe_start += nptes * 8; | |
9ce2b991 | 1463 | dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift; |
dfcd99f6 CK |
1464 | |
1465 | frag_start = upd_end; | |
1466 | if (frag_start >= frag_end) { | |
1467 | /* figure out the next fragment */ | |
1468 | amdgpu_vm_fragment(params, frag_start, end, | |
1469 | flags, &frag, &frag_end); | |
1470 | if (frag < shift) | |
1471 | break; | |
1472 | } | |
1473 | } while (frag_start < entry_end); | |
92696dd5 | 1474 | |
c1a17777 | 1475 | if (amdgpu_vm_pt_descendant(adev, &cursor)) { |
adc7bfe5 | 1476 | /* Free all child entries */ |
c1a17777 | 1477 | while (cursor.pfn < frag_start) { |
e35fb064 | 1478 | amdgpu_vm_free_pts(adev, params->vm, &cursor); |
c1a17777 CK |
1479 | amdgpu_vm_pt_next(adev, &cursor); |
1480 | } | |
1481 | ||
1482 | } else if (frag >= shift) { | |
1483 | /* or just move on to the next on the same level. */ | |
dfcd99f6 | 1484 | amdgpu_vm_pt_next(adev, &cursor); |
c1a17777 | 1485 | } |
92696dd5 | 1486 | } |
6849d47c RH |
1487 | |
1488 | return 0; | |
d38ceaf9 AD |
1489 | } |
1490 | ||
d38ceaf9 AD |
1491 | /** |
1492 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1493 | * | |
1494 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1495 | * @exclusive: fence we need to sync to |
fa3ab3c7 | 1496 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 | 1497 | * @vm: requested vm |
a14faa65 CK |
1498 | * @start: start of mapped range |
1499 | * @last: last mapped entry | |
1500 | * @flags: flags for the entries | |
d38ceaf9 | 1501 | * @addr: addr to set the area to |
d38ceaf9 AD |
1502 | * @fence: optional resulting fence |
1503 | * | |
a14faa65 | 1504 | * Fill in the page table entries between @start and @last. |
7fc48e59 AG |
1505 | * |
1506 | * Returns: | |
1507 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1508 | */ |
1509 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1510 | struct dma_fence *exclusive, |
fa3ab3c7 | 1511 | dma_addr_t *pages_addr, |
d38ceaf9 | 1512 | struct amdgpu_vm *vm, |
a14faa65 | 1513 | uint64_t start, uint64_t last, |
6b777607 | 1514 | uint64_t flags, uint64_t addr, |
f54d1867 | 1515 | struct dma_fence **fence) |
d38ceaf9 | 1516 | { |
d1e29462 | 1517 | struct amdgpu_vm_update_params params; |
c3546695 | 1518 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 AD |
1519 | int r; |
1520 | ||
afef8b8f CK |
1521 | memset(¶ms, 0, sizeof(params)); |
1522 | params.adev = adev; | |
49ac8a24 | 1523 | params.vm = vm; |
072b7a0b | 1524 | params.pages_addr = pages_addr; |
afef8b8f | 1525 | |
8db588d5 | 1526 | /* sync to everything except eviction fences on unmapping */ |
a33cab7a | 1527 | if (!(flags & AMDGPU_PTE_VALID)) |
8db588d5 | 1528 | owner = AMDGPU_FENCE_OWNER_KFD; |
a33cab7a | 1529 | |
c3546695 | 1530 | r = vm->update_funcs->prepare(¶ms, owner, exclusive); |
d71518b5 | 1531 | if (r) |
d38ceaf9 | 1532 | return r; |
d71518b5 | 1533 | |
dfcd99f6 | 1534 | r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags); |
cc28c4ed | 1535 | if (r) |
c3546695 | 1536 | return r; |
d5fc5e82 | 1537 | |
c3546695 | 1538 | return vm->update_funcs->commit(¶ms, fence); |
d38ceaf9 AD |
1539 | } |
1540 | ||
a14faa65 CK |
1541 | /** |
1542 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1543 | * | |
1544 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1545 | * @exclusive: fence we need to sync to |
8358dcee | 1546 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1547 | * @vm: requested vm |
1548 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1549 | * @flags: HW flags for the mapping |
a690aa0f | 1550 | * @bo_adev: amdgpu_device pointer that bo actually been allocated |
63e0ba40 | 1551 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1552 | * @fence: optional resulting fence |
1553 | * | |
1554 | * Split the mapping into smaller chunks so that each update fits | |
1555 | * into a SDMA IB. | |
7fc48e59 AG |
1556 | * |
1557 | * Returns: | |
1558 | * 0 for success, -EINVAL for failure. | |
a14faa65 CK |
1559 | */ |
1560 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1561 | struct dma_fence *exclusive, |
8358dcee | 1562 | dma_addr_t *pages_addr, |
a14faa65 CK |
1563 | struct amdgpu_vm *vm, |
1564 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1565 | uint64_t flags, |
a690aa0f | 1566 | struct amdgpu_device *bo_adev, |
63e0ba40 | 1567 | struct drm_mm_node *nodes, |
f54d1867 | 1568 | struct dma_fence **fence) |
a14faa65 | 1569 | { |
9fc8fc70 | 1570 | unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; |
570144c6 | 1571 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1572 | int r; |
1573 | ||
1574 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1575 | * but in case of something, we filter the flags in first place | |
1576 | */ | |
1577 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1578 | flags &= ~AMDGPU_PTE_READABLE; | |
1579 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1580 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1581 | ||
15b31c59 AX |
1582 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1583 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1584 | ||
b0fd18b0 AX |
1585 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1586 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1587 | ||
d0766e98 ZJ |
1588 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1589 | (adev->asic_type >= CHIP_VEGA10)) { | |
1590 | flags |= AMDGPU_PTE_PRT; | |
1591 | flags &= ~AMDGPU_PTE_VALID; | |
1592 | } | |
1593 | ||
a14faa65 CK |
1594 | trace_amdgpu_vm_bo_update(mapping); |
1595 | ||
63e0ba40 CK |
1596 | pfn = mapping->offset >> PAGE_SHIFT; |
1597 | if (nodes) { | |
1598 | while (pfn >= nodes->size) { | |
1599 | pfn -= nodes->size; | |
1600 | ++nodes; | |
1601 | } | |
fa3ab3c7 | 1602 | } |
a14faa65 | 1603 | |
63e0ba40 | 1604 | do { |
9fc8fc70 | 1605 | dma_addr_t *dma_addr = NULL; |
63e0ba40 CK |
1606 | uint64_t max_entries; |
1607 | uint64_t addr, last; | |
a14faa65 | 1608 | |
63e0ba40 CK |
1609 | if (nodes) { |
1610 | addr = nodes->start << PAGE_SHIFT; | |
1611 | max_entries = (nodes->size - pfn) * | |
463d2fe8 | 1612 | AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1613 | } else { |
1614 | addr = 0; | |
1615 | max_entries = S64_MAX; | |
1616 | } | |
a14faa65 | 1617 | |
63e0ba40 | 1618 | if (pages_addr) { |
9fc8fc70 CK |
1619 | uint64_t count; |
1620 | ||
38e624a1 | 1621 | for (count = 1; |
463d2fe8 | 1622 | count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
38e624a1 | 1623 | ++count) { |
9fc8fc70 CK |
1624 | uint64_t idx = pfn + count; |
1625 | ||
1626 | if (pages_addr[idx] != | |
1627 | (pages_addr[idx - 1] + PAGE_SIZE)) | |
1628 | break; | |
1629 | } | |
1630 | ||
1631 | if (count < min_linear_pages) { | |
1632 | addr = pfn << PAGE_SHIFT; | |
1633 | dma_addr = pages_addr; | |
1634 | } else { | |
1635 | addr = pages_addr[pfn]; | |
463d2fe8 | 1636 | max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
9fc8fc70 CK |
1637 | } |
1638 | ||
63e0ba40 | 1639 | } else if (flags & AMDGPU_PTE_VALID) { |
a690aa0f | 1640 | addr += bo_adev->vm_manager.vram_base_offset; |
9fc8fc70 | 1641 | addr += pfn << PAGE_SHIFT; |
63e0ba40 | 1642 | } |
63e0ba40 | 1643 | |
a9f87f64 | 1644 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
9fc8fc70 | 1645 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, |
a14faa65 CK |
1646 | start, last, flags, addr, |
1647 | fence); | |
1648 | if (r) | |
1649 | return r; | |
1650 | ||
463d2fe8 | 1651 | pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1652 | if (nodes && nodes->size == pfn) { |
1653 | pfn = 0; | |
1654 | ++nodes; | |
1655 | } | |
a14faa65 | 1656 | start = last + 1; |
63e0ba40 | 1657 | |
a9f87f64 | 1658 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1659 | |
1660 | return 0; | |
1661 | } | |
1662 | ||
d38ceaf9 AD |
1663 | /** |
1664 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1665 | * | |
1666 | * @adev: amdgpu_device pointer | |
1667 | * @bo_va: requested BO and VM object | |
99e124f4 | 1668 | * @clear: if true clear the entries |
d38ceaf9 AD |
1669 | * |
1670 | * Fill in the page table entries for @bo_va. | |
7fc48e59 AG |
1671 | * |
1672 | * Returns: | |
1673 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1674 | */ |
1675 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1676 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1677 | bool clear) |
d38ceaf9 | 1678 | { |
ec681545 CK |
1679 | struct amdgpu_bo *bo = bo_va->base.bo; |
1680 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1681 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1682 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 1683 | struct ttm_mem_reg *mem; |
63e0ba40 | 1684 | struct drm_mm_node *nodes; |
4e55eb38 | 1685 | struct dma_fence *exclusive, **last_update; |
9b638f97 | 1686 | uint64_t flags; |
86f7bae5 | 1687 | struct amdgpu_device *bo_adev = adev; |
d38ceaf9 AD |
1688 | int r; |
1689 | ||
7eb80427 | 1690 | if (clear || !bo) { |
99e124f4 | 1691 | mem = NULL; |
63e0ba40 | 1692 | nodes = NULL; |
99e124f4 CK |
1693 | exclusive = NULL; |
1694 | } else { | |
8358dcee CK |
1695 | struct ttm_dma_tt *ttm; |
1696 | ||
7eb80427 | 1697 | mem = &bo->tbo.mem; |
63e0ba40 CK |
1698 | nodes = mem->mm_node; |
1699 | if (mem->mem_type == TTM_PL_TT) { | |
7eb80427 | 1700 | ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm); |
8358dcee | 1701 | pages_addr = ttm->dma_address; |
9ab21462 | 1702 | } |
ec681545 | 1703 | exclusive = reservation_object_get_excl(bo->tbo.resv); |
d38ceaf9 AD |
1704 | } |
1705 | ||
a690aa0f | 1706 | if (bo) { |
ec681545 | 1707 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
a690aa0f | 1708 | bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); |
1709 | } else { | |
a5f6b5b1 | 1710 | flags = 0x0; |
a690aa0f | 1711 | } |
d38ceaf9 | 1712 | |
4e55eb38 CK |
1713 | if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) |
1714 | last_update = &vm->last_update; | |
1715 | else | |
1716 | last_update = &bo_va->last_pt_update; | |
1717 | ||
3d7d4d3a CK |
1718 | if (!clear && bo_va->base.moved) { |
1719 | bo_va->base.moved = false; | |
7fc11959 | 1720 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1721 | |
cb7b6ec2 CK |
1722 | } else if (bo_va->cleared != clear) { |
1723 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1724 | } |
7fc11959 CK |
1725 | |
1726 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
457e0fee | 1727 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
a690aa0f | 1728 | mapping, flags, bo_adev, nodes, |
4e55eb38 | 1729 | last_update); |
d38ceaf9 AD |
1730 | if (r) |
1731 | return r; | |
1732 | } | |
1733 | ||
cb7b6ec2 CK |
1734 | if (vm->use_cpu_for_update) { |
1735 | /* Flush HDP */ | |
1736 | mb(); | |
69882565 | 1737 | amdgpu_asic_flush_hdp(adev, NULL); |
d6c10f6b CK |
1738 | } |
1739 | ||
bb475839 JZ |
1740 | /* If the BO is not in its preferred location add it back to |
1741 | * the evicted list so that it gets validated again on the | |
1742 | * next command submission. | |
1743 | */ | |
806f043f CK |
1744 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
1745 | uint32_t mem_type = bo->tbo.mem.mem_type; | |
1746 | ||
1747 | if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type))) | |
bcdc9fd6 | 1748 | amdgpu_vm_bo_evicted(&bo_va->base); |
806f043f | 1749 | else |
bcdc9fd6 | 1750 | amdgpu_vm_bo_idle(&bo_va->base); |
c12a2ee5 | 1751 | } else { |
bcdc9fd6 | 1752 | amdgpu_vm_bo_done(&bo_va->base); |
806f043f | 1753 | } |
d38ceaf9 | 1754 | |
cb7b6ec2 CK |
1755 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1756 | bo_va->cleared = clear; | |
1757 | ||
1758 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1759 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1760 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1761 | } |
1762 | ||
d38ceaf9 AD |
1763 | return 0; |
1764 | } | |
1765 | ||
284710fa CK |
1766 | /** |
1767 | * amdgpu_vm_update_prt_state - update the global PRT state | |
7fc48e59 AG |
1768 | * |
1769 | * @adev: amdgpu_device pointer | |
284710fa CK |
1770 | */ |
1771 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1772 | { | |
1773 | unsigned long flags; | |
1774 | bool enable; | |
1775 | ||
1776 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1777 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
132f34e4 | 1778 | adev->gmc.gmc_funcs->set_prt(adev, enable); |
284710fa CK |
1779 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); |
1780 | } | |
1781 | ||
451bc8eb | 1782 | /** |
4388fc2a | 1783 | * amdgpu_vm_prt_get - add a PRT user |
7fc48e59 AG |
1784 | * |
1785 | * @adev: amdgpu_device pointer | |
451bc8eb CK |
1786 | */ |
1787 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1788 | { | |
132f34e4 | 1789 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1790 | return; |
1791 | ||
451bc8eb CK |
1792 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1793 | amdgpu_vm_update_prt_state(adev); | |
1794 | } | |
1795 | ||
0b15f2fc CK |
1796 | /** |
1797 | * amdgpu_vm_prt_put - drop a PRT user | |
7fc48e59 AG |
1798 | * |
1799 | * @adev: amdgpu_device pointer | |
0b15f2fc CK |
1800 | */ |
1801 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1802 | { | |
451bc8eb | 1803 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1804 | amdgpu_vm_update_prt_state(adev); |
1805 | } | |
1806 | ||
284710fa | 1807 | /** |
451bc8eb | 1808 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
7fc48e59 AG |
1809 | * |
1810 | * @fence: fence for the callback | |
00553cf8 | 1811 | * @_cb: the callback function |
284710fa CK |
1812 | */ |
1813 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1814 | { | |
1815 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1816 | ||
0b15f2fc | 1817 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1818 | kfree(cb); |
1819 | } | |
1820 | ||
451bc8eb CK |
1821 | /** |
1822 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
7fc48e59 AG |
1823 | * |
1824 | * @adev: amdgpu_device pointer | |
1825 | * @fence: fence for the callback | |
451bc8eb CK |
1826 | */ |
1827 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1828 | struct dma_fence *fence) | |
1829 | { | |
4388fc2a | 1830 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1831 | |
132f34e4 | 1832 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1833 | return; |
1834 | ||
1835 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1836 | if (!cb) { |
1837 | /* Last resort when we are OOM */ | |
1838 | if (fence) | |
1839 | dma_fence_wait(fence, false); | |
1840 | ||
486a68f5 | 1841 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1842 | } else { |
1843 | cb->adev = adev; | |
1844 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1845 | amdgpu_vm_prt_cb)) | |
1846 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1847 | } | |
1848 | } | |
1849 | ||
284710fa CK |
1850 | /** |
1851 | * amdgpu_vm_free_mapping - free a mapping | |
1852 | * | |
1853 | * @adev: amdgpu_device pointer | |
1854 | * @vm: requested vm | |
1855 | * @mapping: mapping to be freed | |
1856 | * @fence: fence of the unmap operation | |
1857 | * | |
1858 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1859 | */ | |
1860 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1861 | struct amdgpu_vm *vm, | |
1862 | struct amdgpu_bo_va_mapping *mapping, | |
1863 | struct dma_fence *fence) | |
1864 | { | |
451bc8eb CK |
1865 | if (mapping->flags & AMDGPU_PTE_PRT) |
1866 | amdgpu_vm_add_prt_cb(adev, fence); | |
1867 | kfree(mapping); | |
1868 | } | |
284710fa | 1869 | |
451bc8eb CK |
1870 | /** |
1871 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1872 | * | |
1873 | * @adev: amdgpu_device pointer | |
1874 | * @vm: requested vm | |
1875 | * | |
1876 | * Register a cleanup callback to disable PRT support after VM dies. | |
1877 | */ | |
1878 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1879 | { | |
3f3333f8 | 1880 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
451bc8eb CK |
1881 | struct dma_fence *excl, **shared; |
1882 | unsigned i, shared_count; | |
1883 | int r; | |
0b15f2fc | 1884 | |
451bc8eb CK |
1885 | r = reservation_object_get_fences_rcu(resv, &excl, |
1886 | &shared_count, &shared); | |
1887 | if (r) { | |
1888 | /* Not enough memory to grab the fence list, as last resort | |
1889 | * block for all the fences to complete. | |
1890 | */ | |
1891 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1892 | MAX_SCHEDULE_TIMEOUT); | |
1893 | return; | |
284710fa | 1894 | } |
451bc8eb CK |
1895 | |
1896 | /* Add a callback for each fence in the reservation object */ | |
1897 | amdgpu_vm_prt_get(adev); | |
1898 | amdgpu_vm_add_prt_cb(adev, excl); | |
1899 | ||
1900 | for (i = 0; i < shared_count; ++i) { | |
1901 | amdgpu_vm_prt_get(adev); | |
1902 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1903 | } | |
1904 | ||
1905 | kfree(shared); | |
284710fa CK |
1906 | } |
1907 | ||
d38ceaf9 AD |
1908 | /** |
1909 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1910 | * | |
1911 | * @adev: amdgpu_device pointer | |
1912 | * @vm: requested vm | |
f3467818 NH |
1913 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1914 | * or if an error occurred) | |
d38ceaf9 AD |
1915 | * |
1916 | * Make sure all freed BOs are cleared in the PT. | |
d38ceaf9 | 1917 | * PTs have to be reserved and mutex must be locked! |
7fc48e59 AG |
1918 | * |
1919 | * Returns: | |
1920 | * 0 for success. | |
1921 | * | |
d38ceaf9 AD |
1922 | */ |
1923 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1924 | struct amdgpu_vm *vm, |
1925 | struct dma_fence **fence) | |
d38ceaf9 AD |
1926 | { |
1927 | struct amdgpu_bo_va_mapping *mapping; | |
4584312d | 1928 | uint64_t init_pte_value = 0; |
f3467818 | 1929 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1930 | int r; |
1931 | ||
1932 | while (!list_empty(&vm->freed)) { | |
1933 | mapping = list_first_entry(&vm->freed, | |
1934 | struct amdgpu_bo_va_mapping, list); | |
1935 | list_del(&mapping->list); | |
e17841b9 | 1936 | |
ad9a5b78 CK |
1937 | if (vm->pte_support_ats && |
1938 | mapping->start < AMDGPU_GMC_HOLE_START) | |
6d16dac8 | 1939 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec | 1940 | |
570144c6 | 1941 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, |
fc6aa33d | 1942 | mapping->start, mapping->last, |
51ac7eec | 1943 | init_pte_value, 0, &f); |
f3467818 | 1944 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1945 | if (r) { |
f3467818 | 1946 | dma_fence_put(f); |
d38ceaf9 | 1947 | return r; |
284710fa | 1948 | } |
f3467818 | 1949 | } |
d38ceaf9 | 1950 | |
f3467818 NH |
1951 | if (fence && f) { |
1952 | dma_fence_put(*fence); | |
1953 | *fence = f; | |
1954 | } else { | |
1955 | dma_fence_put(f); | |
d38ceaf9 | 1956 | } |
f3467818 | 1957 | |
d38ceaf9 AD |
1958 | return 0; |
1959 | ||
1960 | } | |
1961 | ||
1962 | /** | |
73fb16e7 | 1963 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
1964 | * |
1965 | * @adev: amdgpu_device pointer | |
1966 | * @vm: requested vm | |
1967 | * | |
73fb16e7 | 1968 | * Make sure all BOs which are moved are updated in the PTs. |
7fc48e59 AG |
1969 | * |
1970 | * Returns: | |
1971 | * 0 for success. | |
d38ceaf9 | 1972 | * |
73fb16e7 | 1973 | * PTs have to be reserved! |
d38ceaf9 | 1974 | */ |
73fb16e7 | 1975 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 1976 | struct amdgpu_vm *vm) |
d38ceaf9 | 1977 | { |
789f3317 | 1978 | struct amdgpu_bo_va *bo_va, *tmp; |
c12a2ee5 | 1979 | struct reservation_object *resv; |
73fb16e7 | 1980 | bool clear; |
789f3317 | 1981 | int r; |
d38ceaf9 | 1982 | |
c12a2ee5 CK |
1983 | list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { |
1984 | /* Per VM BOs never need to bo cleared in the page tables */ | |
1985 | r = amdgpu_vm_bo_update(adev, bo_va, false); | |
1986 | if (r) | |
1987 | return r; | |
1988 | } | |
32b41ac2 | 1989 | |
c12a2ee5 CK |
1990 | spin_lock(&vm->invalidated_lock); |
1991 | while (!list_empty(&vm->invalidated)) { | |
1992 | bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, | |
1993 | base.vm_status); | |
1994 | resv = bo_va->base.bo->tbo.resv; | |
1995 | spin_unlock(&vm->invalidated_lock); | |
ec363e0d | 1996 | |
ec363e0d | 1997 | /* Try to reserve the BO to avoid clearing its ptes */ |
c12a2ee5 | 1998 | if (!amdgpu_vm_debug && reservation_object_trylock(resv)) |
ec363e0d CK |
1999 | clear = false; |
2000 | /* Somebody else is using the BO right now */ | |
2001 | else | |
2002 | clear = true; | |
73fb16e7 CK |
2003 | |
2004 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
c12a2ee5 | 2005 | if (r) |
d38ceaf9 AD |
2006 | return r; |
2007 | ||
c12a2ee5 | 2008 | if (!clear) |
ec363e0d | 2009 | reservation_object_unlock(resv); |
c12a2ee5 | 2010 | spin_lock(&vm->invalidated_lock); |
d38ceaf9 | 2011 | } |
c12a2ee5 | 2012 | spin_unlock(&vm->invalidated_lock); |
d38ceaf9 | 2013 | |
789f3317 | 2014 | return 0; |
d38ceaf9 AD |
2015 | } |
2016 | ||
2017 | /** | |
2018 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
2019 | * | |
2020 | * @adev: amdgpu_device pointer | |
2021 | * @vm: requested vm | |
2022 | * @bo: amdgpu buffer object | |
2023 | * | |
8843dbbb | 2024 | * Add @bo into the requested vm. |
d38ceaf9 | 2025 | * Add @bo to the list of bos associated with the vm |
7fc48e59 AG |
2026 | * |
2027 | * Returns: | |
2028 | * Newly added bo_va or NULL for failure | |
d38ceaf9 AD |
2029 | * |
2030 | * Object has to be reserved! | |
2031 | */ | |
2032 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
2033 | struct amdgpu_vm *vm, | |
2034 | struct amdgpu_bo *bo) | |
2035 | { | |
2036 | struct amdgpu_bo_va *bo_va; | |
2037 | ||
2038 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2039 | if (bo_va == NULL) { | |
2040 | return NULL; | |
2041 | } | |
3f4299be | 2042 | amdgpu_vm_bo_base_init(&bo_va->base, vm, bo); |
ec681545 | 2043 | |
d38ceaf9 | 2044 | bo_va->ref_count = 1; |
7fc11959 CK |
2045 | INIT_LIST_HEAD(&bo_va->valids); |
2046 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2047 | |
d38ceaf9 AD |
2048 | return bo_va; |
2049 | } | |
2050 | ||
73fb16e7 CK |
2051 | |
2052 | /** | |
2053 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
2054 | * | |
2055 | * @adev: amdgpu_device pointer | |
2056 | * @bo_va: bo_va to store the address | |
2057 | * @mapping: the mapping to insert | |
2058 | * | |
2059 | * Insert a new mapping into all structures. | |
2060 | */ | |
2061 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2062 | struct amdgpu_bo_va *bo_va, | |
2063 | struct amdgpu_bo_va_mapping *mapping) | |
2064 | { | |
2065 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2066 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2067 | ||
aebc5e6f | 2068 | mapping->bo_va = bo_va; |
73fb16e7 CK |
2069 | list_add(&mapping->list, &bo_va->invalids); |
2070 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2071 | ||
2072 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2073 | amdgpu_vm_prt_get(adev); | |
2074 | ||
862b8c57 CK |
2075 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv && |
2076 | !bo_va->base.moved) { | |
862b8c57 | 2077 | list_move(&bo_va->base.vm_status, &vm->moved); |
73fb16e7 CK |
2078 | } |
2079 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2080 | } | |
2081 | ||
d38ceaf9 AD |
2082 | /** |
2083 | * amdgpu_vm_bo_map - map bo inside a vm | |
2084 | * | |
2085 | * @adev: amdgpu_device pointer | |
2086 | * @bo_va: bo_va to store the address | |
2087 | * @saddr: where to map the BO | |
2088 | * @offset: requested offset in the BO | |
00553cf8 | 2089 | * @size: BO size in bytes |
d38ceaf9 AD |
2090 | * @flags: attributes of pages (read/write/valid/etc.) |
2091 | * | |
2092 | * Add a mapping of the BO at the specefied addr into the VM. | |
7fc48e59 AG |
2093 | * |
2094 | * Returns: | |
2095 | * 0 for success, error for failure. | |
d38ceaf9 | 2096 | * |
49b02b18 | 2097 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2098 | */ |
2099 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2100 | struct amdgpu_bo_va *bo_va, | |
2101 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2102 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2103 | { |
a9f87f64 | 2104 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2105 | struct amdgpu_bo *bo = bo_va->base.bo; |
2106 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2107 | uint64_t eaddr; |
d38ceaf9 | 2108 | |
0be52de9 CK |
2109 | /* validate the parameters */ |
2110 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2111 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2112 | return -EINVAL; |
0be52de9 | 2113 | |
d38ceaf9 | 2114 | /* make sure object fit at this offset */ |
005ae95e | 2115 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2116 | if (saddr >= eaddr || |
ec681545 | 2117 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 2118 | return -EINVAL; |
d38ceaf9 | 2119 | |
d38ceaf9 AD |
2120 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2121 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2122 | ||
a9f87f64 CK |
2123 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2124 | if (tmp) { | |
d38ceaf9 AD |
2125 | /* bo and tmp overlap, invalid addr */ |
2126 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2127 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2128 | tmp->start, tmp->last + 1); |
663e4577 | 2129 | return -EINVAL; |
d38ceaf9 AD |
2130 | } |
2131 | ||
2132 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2133 | if (!mapping) |
2134 | return -ENOMEM; | |
d38ceaf9 | 2135 | |
a9f87f64 CK |
2136 | mapping->start = saddr; |
2137 | mapping->last = eaddr; | |
d38ceaf9 AD |
2138 | mapping->offset = offset; |
2139 | mapping->flags = flags; | |
2140 | ||
73fb16e7 | 2141 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
2142 | |
2143 | return 0; | |
2144 | } | |
2145 | ||
2146 | /** | |
2147 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2148 | * | |
2149 | * @adev: amdgpu_device pointer | |
2150 | * @bo_va: bo_va to store the address | |
2151 | * @saddr: where to map the BO | |
2152 | * @offset: requested offset in the BO | |
00553cf8 | 2153 | * @size: BO size in bytes |
80f95c57 CK |
2154 | * @flags: attributes of pages (read/write/valid/etc.) |
2155 | * | |
2156 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2157 | * mappings as we do so. | |
7fc48e59 AG |
2158 | * |
2159 | * Returns: | |
2160 | * 0 for success, error for failure. | |
80f95c57 CK |
2161 | * |
2162 | * Object has to be reserved and unreserved outside! | |
2163 | */ | |
2164 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2165 | struct amdgpu_bo_va *bo_va, | |
2166 | uint64_t saddr, uint64_t offset, | |
2167 | uint64_t size, uint64_t flags) | |
2168 | { | |
2169 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2170 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
2171 | uint64_t eaddr; |
2172 | int r; | |
2173 | ||
2174 | /* validate the parameters */ | |
2175 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2176 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2177 | return -EINVAL; | |
2178 | ||
2179 | /* make sure object fit at this offset */ | |
2180 | eaddr = saddr + size - 1; | |
2181 | if (saddr >= eaddr || | |
ec681545 | 2182 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
2183 | return -EINVAL; |
2184 | ||
2185 | /* Allocate all the needed memory */ | |
2186 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2187 | if (!mapping) | |
2188 | return -ENOMEM; | |
2189 | ||
ec681545 | 2190 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2191 | if (r) { |
2192 | kfree(mapping); | |
2193 | return r; | |
2194 | } | |
2195 | ||
2196 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2197 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2198 | ||
a9f87f64 CK |
2199 | mapping->start = saddr; |
2200 | mapping->last = eaddr; | |
80f95c57 CK |
2201 | mapping->offset = offset; |
2202 | mapping->flags = flags; | |
2203 | ||
73fb16e7 | 2204 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 2205 | |
d38ceaf9 | 2206 | return 0; |
d38ceaf9 AD |
2207 | } |
2208 | ||
2209 | /** | |
2210 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2211 | * | |
2212 | * @adev: amdgpu_device pointer | |
2213 | * @bo_va: bo_va to remove the address from | |
2214 | * @saddr: where to the BO is mapped | |
2215 | * | |
2216 | * Remove a mapping of the BO at the specefied addr from the VM. | |
7fc48e59 AG |
2217 | * |
2218 | * Returns: | |
2219 | * 0 for success, error for failure. | |
d38ceaf9 | 2220 | * |
49b02b18 | 2221 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2222 | */ |
2223 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2224 | struct amdgpu_bo_va *bo_va, | |
2225 | uint64_t saddr) | |
2226 | { | |
2227 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2228 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2229 | bool valid = true; |
d38ceaf9 | 2230 | |
6c7fc503 | 2231 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2232 | |
7fc11959 | 2233 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2234 | if (mapping->start == saddr) |
d38ceaf9 AD |
2235 | break; |
2236 | } | |
2237 | ||
7fc11959 CK |
2238 | if (&mapping->list == &bo_va->valids) { |
2239 | valid = false; | |
2240 | ||
2241 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2242 | if (mapping->start == saddr) |
7fc11959 CK |
2243 | break; |
2244 | } | |
2245 | ||
32b41ac2 | 2246 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2247 | return -ENOENT; |
d38ceaf9 | 2248 | } |
32b41ac2 | 2249 | |
d38ceaf9 | 2250 | list_del(&mapping->list); |
a9f87f64 | 2251 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2252 | mapping->bo_va = NULL; |
93e3e438 | 2253 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2254 | |
e17841b9 | 2255 | if (valid) |
d38ceaf9 | 2256 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2257 | else |
284710fa CK |
2258 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2259 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2260 | |
2261 | return 0; | |
2262 | } | |
2263 | ||
dc54d3d1 CK |
2264 | /** |
2265 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2266 | * | |
2267 | * @adev: amdgpu_device pointer | |
2268 | * @vm: VM structure to use | |
2269 | * @saddr: start of the range | |
2270 | * @size: size of the range | |
2271 | * | |
2272 | * Remove all mappings in a range, split them as appropriate. | |
7fc48e59 AG |
2273 | * |
2274 | * Returns: | |
2275 | * 0 for success, error for failure. | |
dc54d3d1 CK |
2276 | */ |
2277 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2278 | struct amdgpu_vm *vm, | |
2279 | uint64_t saddr, uint64_t size) | |
2280 | { | |
2281 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2282 | LIST_HEAD(removed); |
2283 | uint64_t eaddr; | |
2284 | ||
2285 | eaddr = saddr + size - 1; | |
2286 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2287 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2288 | ||
2289 | /* Allocate all the needed memory */ | |
2290 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2291 | if (!before) | |
2292 | return -ENOMEM; | |
27f6d610 | 2293 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2294 | |
2295 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2296 | if (!after) { | |
2297 | kfree(before); | |
2298 | return -ENOMEM; | |
2299 | } | |
27f6d610 | 2300 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2301 | |
2302 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2303 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2304 | while (tmp) { | |
dc54d3d1 | 2305 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2306 | if (tmp->start < saddr) { |
2307 | before->start = tmp->start; | |
2308 | before->last = saddr - 1; | |
dc54d3d1 CK |
2309 | before->offset = tmp->offset; |
2310 | before->flags = tmp->flags; | |
387f49e5 JZ |
2311 | before->bo_va = tmp->bo_va; |
2312 | list_add(&before->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2313 | } |
2314 | ||
2315 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2316 | if (tmp->last > eaddr) { |
2317 | after->start = eaddr + 1; | |
2318 | after->last = tmp->last; | |
dc54d3d1 | 2319 | after->offset = tmp->offset; |
a9f87f64 | 2320 | after->offset += after->start - tmp->start; |
dc54d3d1 | 2321 | after->flags = tmp->flags; |
387f49e5 JZ |
2322 | after->bo_va = tmp->bo_va; |
2323 | list_add(&after->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2324 | } |
2325 | ||
2326 | list_del(&tmp->list); | |
2327 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2328 | |
2329 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2330 | } |
2331 | ||
2332 | /* And free them up */ | |
2333 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2334 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2335 | list_del(&tmp->list); |
2336 | ||
a9f87f64 CK |
2337 | if (tmp->start < saddr) |
2338 | tmp->start = saddr; | |
2339 | if (tmp->last > eaddr) | |
2340 | tmp->last = eaddr; | |
dc54d3d1 | 2341 | |
aebc5e6f | 2342 | tmp->bo_va = NULL; |
dc54d3d1 CK |
2343 | list_add(&tmp->list, &vm->freed); |
2344 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2345 | } | |
2346 | ||
27f6d610 JZ |
2347 | /* Insert partial mapping before the range */ |
2348 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2349 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2350 | if (before->flags & AMDGPU_PTE_PRT) |
2351 | amdgpu_vm_prt_get(adev); | |
2352 | } else { | |
2353 | kfree(before); | |
2354 | } | |
2355 | ||
2356 | /* Insert partial mapping after the range */ | |
27f6d610 | 2357 | if (!list_empty(&after->list)) { |
a9f87f64 | 2358 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2359 | if (after->flags & AMDGPU_PTE_PRT) |
2360 | amdgpu_vm_prt_get(adev); | |
2361 | } else { | |
2362 | kfree(after); | |
2363 | } | |
2364 | ||
2365 | return 0; | |
2366 | } | |
2367 | ||
aebc5e6f CK |
2368 | /** |
2369 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2370 | * | |
2371 | * @vm: the requested VM | |
00553cf8 | 2372 | * @addr: the address |
aebc5e6f CK |
2373 | * |
2374 | * Find a mapping by it's address. | |
7fc48e59 AG |
2375 | * |
2376 | * Returns: | |
2377 | * The amdgpu_bo_va_mapping matching for addr or NULL | |
2378 | * | |
aebc5e6f CK |
2379 | */ |
2380 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2381 | uint64_t addr) | |
2382 | { | |
2383 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2384 | } | |
2385 | ||
8ab19ea6 CK |
2386 | /** |
2387 | * amdgpu_vm_bo_trace_cs - trace all reserved mappings | |
2388 | * | |
2389 | * @vm: the requested vm | |
2390 | * @ticket: CS ticket | |
2391 | * | |
2392 | * Trace all mappings of BOs reserved during a command submission. | |
2393 | */ | |
2394 | void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) | |
2395 | { | |
2396 | struct amdgpu_bo_va_mapping *mapping; | |
2397 | ||
2398 | if (!trace_amdgpu_vm_bo_cs_enabled()) | |
2399 | return; | |
2400 | ||
2401 | for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping; | |
2402 | mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) { | |
2403 | if (mapping->bo_va && mapping->bo_va->base.bo) { | |
2404 | struct amdgpu_bo *bo; | |
2405 | ||
2406 | bo = mapping->bo_va->base.bo; | |
2407 | if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket) | |
2408 | continue; | |
2409 | } | |
2410 | ||
2411 | trace_amdgpu_vm_bo_cs(mapping); | |
2412 | } | |
2413 | } | |
2414 | ||
d38ceaf9 AD |
2415 | /** |
2416 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2417 | * | |
2418 | * @adev: amdgpu_device pointer | |
2419 | * @bo_va: requested bo_va | |
2420 | * | |
8843dbbb | 2421 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2422 | * |
2423 | * Object have to be reserved! | |
2424 | */ | |
2425 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2426 | struct amdgpu_bo_va *bo_va) | |
2427 | { | |
2428 | struct amdgpu_bo_va_mapping *mapping, *next; | |
fbbf794c | 2429 | struct amdgpu_bo *bo = bo_va->base.bo; |
ec681545 | 2430 | struct amdgpu_vm *vm = bo_va->base.vm; |
646b9025 | 2431 | struct amdgpu_vm_bo_base **base; |
d38ceaf9 | 2432 | |
646b9025 CK |
2433 | if (bo) { |
2434 | if (bo->tbo.resv == vm->root.base.bo->tbo.resv) | |
2435 | vm->bulk_moveable = false; | |
fbbf794c | 2436 | |
646b9025 CK |
2437 | for (base = &bo_va->base.bo->vm_bo; *base; |
2438 | base = &(*base)->next) { | |
2439 | if (*base != &bo_va->base) | |
2440 | continue; | |
2441 | ||
2442 | *base = bo_va->base.next; | |
2443 | break; | |
2444 | } | |
2445 | } | |
d38ceaf9 | 2446 | |
c12a2ee5 | 2447 | spin_lock(&vm->invalidated_lock); |
ec681545 | 2448 | list_del(&bo_va->base.vm_status); |
c12a2ee5 | 2449 | spin_unlock(&vm->invalidated_lock); |
d38ceaf9 | 2450 | |
7fc11959 | 2451 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2452 | list_del(&mapping->list); |
a9f87f64 | 2453 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2454 | mapping->bo_va = NULL; |
93e3e438 | 2455 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2456 | list_add(&mapping->list, &vm->freed); |
2457 | } | |
2458 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2459 | list_del(&mapping->list); | |
a9f87f64 | 2460 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2461 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2462 | bo_va->last_pt_update); | |
d38ceaf9 | 2463 | } |
32b41ac2 | 2464 | |
f54d1867 | 2465 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2466 | kfree(bo_va); |
d38ceaf9 AD |
2467 | } |
2468 | ||
2469 | /** | |
2470 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2471 | * | |
2472 | * @adev: amdgpu_device pointer | |
d38ceaf9 | 2473 | * @bo: amdgpu buffer object |
00553cf8 | 2474 | * @evicted: is the BO evicted |
d38ceaf9 | 2475 | * |
8843dbbb | 2476 | * Mark @bo as invalid. |
d38ceaf9 AD |
2477 | */ |
2478 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2479 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2480 | { |
ec681545 CK |
2481 | struct amdgpu_vm_bo_base *bo_base; |
2482 | ||
4bebccee CZ |
2483 | /* shadow bo doesn't have bo base, its validation needs its parent */ |
2484 | if (bo->parent && bo->parent->shadow == bo) | |
2485 | bo = bo->parent; | |
2486 | ||
646b9025 | 2487 | for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { |
3f3333f8 CK |
2488 | struct amdgpu_vm *vm = bo_base->vm; |
2489 | ||
3f3333f8 | 2490 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
bcdc9fd6 | 2491 | amdgpu_vm_bo_evicted(bo_base); |
3f3333f8 CK |
2492 | continue; |
2493 | } | |
2494 | ||
bcdc9fd6 | 2495 | if (bo_base->moved) |
3f3333f8 | 2496 | continue; |
bcdc9fd6 | 2497 | bo_base->moved = true; |
3f3333f8 | 2498 | |
bcdc9fd6 CK |
2499 | if (bo->tbo.type == ttm_bo_type_kernel) |
2500 | amdgpu_vm_bo_relocated(bo_base); | |
2501 | else if (bo->tbo.resv == vm->root.base.bo->tbo.resv) | |
2502 | amdgpu_vm_bo_moved(bo_base); | |
2503 | else | |
2504 | amdgpu_vm_bo_invalidated(bo_base); | |
d38ceaf9 AD |
2505 | } |
2506 | } | |
2507 | ||
7fc48e59 AG |
2508 | /** |
2509 | * amdgpu_vm_get_block_size - calculate VM page table size as power of two | |
2510 | * | |
2511 | * @vm_size: VM size | |
2512 | * | |
2513 | * Returns: | |
2514 | * VM page table as power of two | |
2515 | */ | |
bab4fee7 JZ |
2516 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2517 | { | |
2518 | /* Total bits covered by PD + PTs */ | |
2519 | unsigned bits = ilog2(vm_size) + 18; | |
2520 | ||
2521 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2522 | Above that split equal between PD and PTs */ | |
2523 | if (vm_size <= 8) | |
2524 | return (bits - 9); | |
2525 | else | |
2526 | return ((bits + 3) / 2); | |
2527 | } | |
2528 | ||
d07f14be RH |
2529 | /** |
2530 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2531 | * |
2532 | * @adev: amdgpu_device pointer | |
43370c4c | 2533 | * @min_vm_size: the minimum vm size in GB if it's set auto |
00553cf8 AG |
2534 | * @fragment_size_default: Default PTE fragment size |
2535 | * @max_level: max VMPT level | |
2536 | * @max_bits: max address space size in bits | |
2537 | * | |
bab4fee7 | 2538 | */ |
43370c4c | 2539 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, |
f3368128 CK |
2540 | uint32_t fragment_size_default, unsigned max_level, |
2541 | unsigned max_bits) | |
bab4fee7 | 2542 | { |
43370c4c FK |
2543 | unsigned int max_size = 1 << (max_bits - 30); |
2544 | unsigned int vm_size; | |
36539dce CK |
2545 | uint64_t tmp; |
2546 | ||
2547 | /* adjust vm size first */ | |
f3368128 | 2548 | if (amdgpu_vm_size != -1) { |
fdd5faaa | 2549 | vm_size = amdgpu_vm_size; |
f3368128 CK |
2550 | if (vm_size > max_size) { |
2551 | dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", | |
2552 | amdgpu_vm_size, max_size); | |
2553 | vm_size = max_size; | |
2554 | } | |
43370c4c FK |
2555 | } else { |
2556 | struct sysinfo si; | |
2557 | unsigned int phys_ram_gb; | |
2558 | ||
2559 | /* Optimal VM size depends on the amount of physical | |
2560 | * RAM available. Underlying requirements and | |
2561 | * assumptions: | |
2562 | * | |
2563 | * - Need to map system memory and VRAM from all GPUs | |
2564 | * - VRAM from other GPUs not known here | |
2565 | * - Assume VRAM <= system memory | |
2566 | * - On GFX8 and older, VM space can be segmented for | |
2567 | * different MTYPEs | |
2568 | * - Need to allow room for fragmentation, guard pages etc. | |
2569 | * | |
2570 | * This adds up to a rough guess of system memory x3. | |
2571 | * Round up to power of two to maximize the available | |
2572 | * VM size with the given page table size. | |
2573 | */ | |
2574 | si_meminfo(&si); | |
2575 | phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit + | |
2576 | (1 << 30) - 1) >> 30; | |
2577 | vm_size = roundup_pow_of_two( | |
2578 | min(max(phys_ram_gb * 3, min_vm_size), max_size)); | |
f3368128 | 2579 | } |
fdd5faaa CK |
2580 | |
2581 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
36539dce CK |
2582 | |
2583 | tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); | |
97489129 CK |
2584 | if (amdgpu_vm_block_size != -1) |
2585 | tmp >>= amdgpu_vm_block_size - 9; | |
36539dce CK |
2586 | tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; |
2587 | adev->vm_manager.num_level = min(max_level, (unsigned)tmp); | |
196f7489 CZ |
2588 | switch (adev->vm_manager.num_level) { |
2589 | case 3: | |
2590 | adev->vm_manager.root_level = AMDGPU_VM_PDB2; | |
2591 | break; | |
2592 | case 2: | |
2593 | adev->vm_manager.root_level = AMDGPU_VM_PDB1; | |
2594 | break; | |
2595 | case 1: | |
2596 | adev->vm_manager.root_level = AMDGPU_VM_PDB0; | |
2597 | break; | |
2598 | default: | |
2599 | dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n"); | |
2600 | } | |
b38f41eb | 2601 | /* block size depends on vm size and hw setup*/ |
97489129 | 2602 | if (amdgpu_vm_block_size != -1) |
bab4fee7 | 2603 | adev->vm_manager.block_size = |
97489129 CK |
2604 | min((unsigned)amdgpu_vm_block_size, max_bits |
2605 | - AMDGPU_GPU_PAGE_SHIFT | |
2606 | - 9 * adev->vm_manager.num_level); | |
2607 | else if (adev->vm_manager.num_level > 1) | |
2608 | adev->vm_manager.block_size = 9; | |
bab4fee7 | 2609 | else |
97489129 | 2610 | adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); |
bab4fee7 | 2611 | |
b38f41eb CK |
2612 | if (amdgpu_vm_fragment_size == -1) |
2613 | adev->vm_manager.fragment_size = fragment_size_default; | |
2614 | else | |
2615 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
d07f14be | 2616 | |
36539dce CK |
2617 | DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", |
2618 | vm_size, adev->vm_manager.num_level + 1, | |
2619 | adev->vm_manager.block_size, | |
fdd5faaa | 2620 | adev->vm_manager.fragment_size); |
bab4fee7 JZ |
2621 | } |
2622 | ||
56753e73 CK |
2623 | /** |
2624 | * amdgpu_vm_wait_idle - wait for the VM to become idle | |
2625 | * | |
2626 | * @vm: VM object to wait for | |
2627 | * @timeout: timeout to wait for VM to become idle | |
2628 | */ | |
2629 | long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout) | |
2630 | { | |
2631 | return reservation_object_wait_timeout_rcu(vm->root.base.bo->tbo.resv, | |
2632 | true, true, timeout); | |
2633 | } | |
2634 | ||
d38ceaf9 AD |
2635 | /** |
2636 | * amdgpu_vm_init - initialize a vm instance | |
2637 | * | |
2638 | * @adev: amdgpu_device pointer | |
2639 | * @vm: requested vm | |
9a4b7d4c | 2640 | * @vm_context: Indicates if it GFX or Compute context |
00553cf8 | 2641 | * @pasid: Process address space identifier |
d38ceaf9 | 2642 | * |
8843dbbb | 2643 | * Init @vm fields. |
7fc48e59 AG |
2644 | * |
2645 | * Returns: | |
2646 | * 0 for success, error for failure. | |
d38ceaf9 | 2647 | */ |
9a4b7d4c | 2648 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 2649 | int vm_context, unsigned int pasid) |
d38ceaf9 | 2650 | { |
3216c6b7 | 2651 | struct amdgpu_bo_param bp; |
3f4299be | 2652 | struct amdgpu_bo *root; |
36bbf3bf | 2653 | int r, i; |
d38ceaf9 | 2654 | |
f808c13f | 2655 | vm->va = RB_ROOT_CACHED; |
36bbf3bf CZ |
2656 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2657 | vm->reserved_vmid[i] = NULL; | |
3f3333f8 | 2658 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2659 | INIT_LIST_HEAD(&vm->relocated); |
27c7b9ae | 2660 | INIT_LIST_HEAD(&vm->moved); |
806f043f | 2661 | INIT_LIST_HEAD(&vm->idle); |
c12a2ee5 CK |
2662 | INIT_LIST_HEAD(&vm->invalidated); |
2663 | spin_lock_init(&vm->invalidated_lock); | |
d38ceaf9 | 2664 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2665 | |
2bd9ccfa | 2666 | /* create scheduler entity for page table updates */ |
3798e9a6 CK |
2667 | r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs, |
2668 | adev->vm_manager.vm_pte_num_rqs, NULL); | |
2bd9ccfa | 2669 | if (r) |
f566ceb1 | 2670 | return r; |
2bd9ccfa | 2671 | |
51ac7eec YZ |
2672 | vm->pte_support_ats = false; |
2673 | ||
2674 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2675 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2676 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec | 2677 | |
741deade | 2678 | if (adev->asic_type == CHIP_RAVEN) |
51ac7eec | 2679 | vm->pte_support_ats = true; |
13307f7e | 2680 | } else { |
9a4b7d4c HK |
2681 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2682 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
13307f7e | 2683 | } |
9a4b7d4c HK |
2684 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2685 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
0855c9c9 | 2686 | WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)), |
9a4b7d4c | 2687 | "CPU update of VM recommended only for large BAR system\n"); |
6dd09027 CK |
2688 | |
2689 | if (vm->use_cpu_for_update) | |
2690 | vm->update_funcs = &amdgpu_vm_cpu_funcs; | |
2691 | else | |
2692 | vm->update_funcs = &amdgpu_vm_sdma_funcs; | |
d5884513 | 2693 | vm->last_update = NULL; |
05906dec | 2694 | |
e21eb261 | 2695 | amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp); |
03e9dee1 FK |
2696 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) |
2697 | bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW; | |
3f4299be | 2698 | r = amdgpu_bo_create(adev, &bp, &root); |
d38ceaf9 | 2699 | if (r) |
2bd9ccfa CK |
2700 | goto error_free_sched_entity; |
2701 | ||
3f4299be | 2702 | r = amdgpu_bo_reserve(root, true); |
d3aab672 CK |
2703 | if (r) |
2704 | goto error_free_root; | |
2705 | ||
0aa7aa24 CK |
2706 | r = reservation_object_reserve_shared(root->tbo.resv, 1); |
2707 | if (r) | |
2708 | goto error_unreserve; | |
2709 | ||
1e293037 CK |
2710 | amdgpu_vm_bo_base_init(&vm->root.base, vm, root); |
2711 | ||
780637cb | 2712 | r = amdgpu_vm_clear_bo(adev, vm, root); |
13307f7e CK |
2713 | if (r) |
2714 | goto error_unreserve; | |
2715 | ||
d3aab672 | 2716 | amdgpu_bo_unreserve(vm->root.base.bo); |
d38ceaf9 | 2717 | |
02208441 FK |
2718 | if (pasid) { |
2719 | unsigned long flags; | |
2720 | ||
2721 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2722 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2723 | GFP_ATOMIC); | |
2724 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2725 | if (r < 0) | |
2726 | goto error_free_root; | |
2727 | ||
2728 | vm->pasid = pasid; | |
0a096fb6 CK |
2729 | } |
2730 | ||
a2f14820 | 2731 | INIT_KFIFO(vm->faults); |
d38ceaf9 AD |
2732 | |
2733 | return 0; | |
2bd9ccfa | 2734 | |
13307f7e CK |
2735 | error_unreserve: |
2736 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2737 | ||
67003a15 | 2738 | error_free_root: |
3f3333f8 CK |
2739 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2740 | amdgpu_bo_unref(&vm->root.base.bo); | |
2741 | vm->root.base.bo = NULL; | |
2bd9ccfa CK |
2742 | |
2743 | error_free_sched_entity: | |
cdc50176 | 2744 | drm_sched_entity_destroy(&vm->entity); |
2bd9ccfa CK |
2745 | |
2746 | return r; | |
d38ceaf9 AD |
2747 | } |
2748 | ||
b236fa1d FK |
2749 | /** |
2750 | * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM | |
2751 | * | |
7fc48e59 AG |
2752 | * @adev: amdgpu_device pointer |
2753 | * @vm: requested vm | |
2754 | * | |
b236fa1d FK |
2755 | * This only works on GFX VMs that don't have any BOs added and no |
2756 | * page tables allocated yet. | |
2757 | * | |
2758 | * Changes the following VM parameters: | |
2759 | * - use_cpu_for_update | |
2760 | * - pte_supports_ats | |
2761 | * - pasid (old PASID is released, because compute manages its own PASIDs) | |
2762 | * | |
2763 | * Reinitializes the page directory to reflect the changed ATS | |
b5d21aac | 2764 | * setting. |
b236fa1d | 2765 | * |
7fc48e59 AG |
2766 | * Returns: |
2767 | * 0 for success, -errno for errors. | |
b236fa1d | 2768 | */ |
1685b01a | 2769 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid) |
b236fa1d | 2770 | { |
741deade | 2771 | bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); |
b236fa1d FK |
2772 | int r; |
2773 | ||
2774 | r = amdgpu_bo_reserve(vm->root.base.bo, true); | |
2775 | if (r) | |
2776 | return r; | |
2777 | ||
2778 | /* Sanity checks */ | |
2779 | if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) { | |
2780 | r = -EINVAL; | |
1685b01a OZ |
2781 | goto unreserve_bo; |
2782 | } | |
2783 | ||
2784 | if (pasid) { | |
2785 | unsigned long flags; | |
2786 | ||
2787 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2788 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2789 | GFP_ATOMIC); | |
2790 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2791 | ||
2792 | if (r == -ENOSPC) | |
2793 | goto unreserve_bo; | |
2794 | r = 0; | |
b236fa1d FK |
2795 | } |
2796 | ||
2797 | /* Check if PD needs to be reinitialized and do it before | |
2798 | * changing any other state, in case it fails. | |
2799 | */ | |
2800 | if (pte_support_ats != vm->pte_support_ats) { | |
780637cb CK |
2801 | vm->pte_support_ats = pte_support_ats; |
2802 | r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo); | |
b236fa1d | 2803 | if (r) |
1685b01a | 2804 | goto free_idr; |
b236fa1d FK |
2805 | } |
2806 | ||
2807 | /* Update VM state */ | |
2808 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
2809 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
b236fa1d FK |
2810 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2811 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
0855c9c9 | 2812 | WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)), |
b236fa1d FK |
2813 | "CPU update of VM recommended only for large BAR system\n"); |
2814 | ||
2815 | if (vm->pasid) { | |
2816 | unsigned long flags; | |
2817 | ||
2818 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2819 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2820 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2821 | ||
1685b01a OZ |
2822 | /* Free the original amdgpu allocated pasid |
2823 | * Will be replaced with kfd allocated pasid | |
2824 | */ | |
2825 | amdgpu_pasid_free(vm->pasid); | |
b236fa1d FK |
2826 | vm->pasid = 0; |
2827 | } | |
2828 | ||
b5d21aac SL |
2829 | /* Free the shadow bo for compute VM */ |
2830 | amdgpu_bo_unref(&vm->root.base.bo->shadow); | |
2831 | ||
1685b01a OZ |
2832 | if (pasid) |
2833 | vm->pasid = pasid; | |
2834 | ||
2835 | goto unreserve_bo; | |
2836 | ||
2837 | free_idr: | |
2838 | if (pasid) { | |
2839 | unsigned long flags; | |
2840 | ||
2841 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2842 | idr_remove(&adev->vm_manager.pasid_idr, pasid); | |
2843 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2844 | } | |
2845 | unreserve_bo: | |
b236fa1d FK |
2846 | amdgpu_bo_unreserve(vm->root.base.bo); |
2847 | return r; | |
2848 | } | |
2849 | ||
bf47afba OZ |
2850 | /** |
2851 | * amdgpu_vm_release_compute - release a compute vm | |
2852 | * @adev: amdgpu_device pointer | |
2853 | * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute | |
2854 | * | |
2855 | * This is a correspondant of amdgpu_vm_make_compute. It decouples compute | |
2856 | * pasid from vm. Compute should stop use of vm after this call. | |
2857 | */ | |
2858 | void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2859 | { | |
2860 | if (vm->pasid) { | |
2861 | unsigned long flags; | |
2862 | ||
2863 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2864 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2865 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2866 | } | |
2867 | vm->pasid = 0; | |
2868 | } | |
2869 | ||
d38ceaf9 AD |
2870 | /** |
2871 | * amdgpu_vm_fini - tear down a vm instance | |
2872 | * | |
2873 | * @adev: amdgpu_device pointer | |
2874 | * @vm: requested vm | |
2875 | * | |
8843dbbb | 2876 | * Tear down @vm. |
d38ceaf9 AD |
2877 | * Unbind the VM and remove all bos from the vm bo list |
2878 | */ | |
2879 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2880 | { | |
2881 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
132f34e4 | 2882 | bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt; |
2642cf11 | 2883 | struct amdgpu_bo *root; |
2642cf11 | 2884 | int i, r; |
d38ceaf9 | 2885 | |
ede0dd86 FK |
2886 | amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm); |
2887 | ||
02208441 FK |
2888 | if (vm->pasid) { |
2889 | unsigned long flags; | |
2890 | ||
2891 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2892 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2893 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2894 | } | |
2895 | ||
cdc50176 | 2896 | drm_sched_entity_destroy(&vm->entity); |
2bd9ccfa | 2897 | |
f808c13f | 2898 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
d38ceaf9 AD |
2899 | dev_err(adev->dev, "still active bo inside vm\n"); |
2900 | } | |
f808c13f DB |
2901 | rbtree_postorder_for_each_entry_safe(mapping, tmp, |
2902 | &vm->va.rb_root, rb) { | |
0af5c656 CK |
2903 | /* Don't remove the mapping here, we don't want to trigger a |
2904 | * rebalance and the tree is about to be destroyed anyway. | |
2905 | */ | |
d38ceaf9 | 2906 | list_del(&mapping->list); |
d38ceaf9 AD |
2907 | kfree(mapping); |
2908 | } | |
2909 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2910 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2911 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2912 | prt_fini_needed = false; |
451bc8eb | 2913 | } |
284710fa | 2914 | |
d38ceaf9 | 2915 | list_del(&mapping->list); |
451bc8eb | 2916 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2917 | } |
2918 | ||
2642cf11 CK |
2919 | root = amdgpu_bo_ref(vm->root.base.bo); |
2920 | r = amdgpu_bo_reserve(root, true); | |
2921 | if (r) { | |
2922 | dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); | |
2923 | } else { | |
e35fb064 | 2924 | amdgpu_vm_free_pts(adev, vm, NULL); |
2642cf11 CK |
2925 | amdgpu_bo_unreserve(root); |
2926 | } | |
2927 | amdgpu_bo_unref(&root); | |
e35fb064 | 2928 | WARN_ON(vm->root.base.bo); |
d5884513 | 2929 | dma_fence_put(vm->last_update); |
1e9ef26f | 2930 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
620f774f | 2931 | amdgpu_vmid_free_reserved(adev, vm, i); |
d38ceaf9 | 2932 | } |
ea89f8c9 | 2933 | |
a9a78b32 CK |
2934 | /** |
2935 | * amdgpu_vm_manager_init - init the VM manager | |
2936 | * | |
2937 | * @adev: amdgpu_device pointer | |
2938 | * | |
2939 | * Initialize the VM manager structures | |
2940 | */ | |
2941 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2942 | { | |
620f774f | 2943 | unsigned i; |
a9a78b32 | 2944 | |
620f774f | 2945 | amdgpu_vmid_mgr_init(adev); |
2d55e45a | 2946 | |
f54d1867 CW |
2947 | adev->vm_manager.fence_context = |
2948 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2949 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2950 | adev->vm_manager.seqno[i] = 0; | |
2951 | ||
284710fa | 2952 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2953 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
2954 | |
2955 | /* If not overridden by the user, by default, only in large BAR systems | |
2956 | * Compute VM tables will be updated by CPU | |
2957 | */ | |
2958 | #ifdef CONFIG_X86_64 | |
2959 | if (amdgpu_vm_update_mode == -1) { | |
c8c5e569 | 2960 | if (amdgpu_gmc_vram_full_visible(&adev->gmc)) |
9a4b7d4c HK |
2961 | adev->vm_manager.vm_update_mode = |
2962 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
2963 | else | |
2964 | adev->vm_manager.vm_update_mode = 0; | |
2965 | } else | |
2966 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
2967 | #else | |
2968 | adev->vm_manager.vm_update_mode = 0; | |
2969 | #endif | |
2970 | ||
02208441 FK |
2971 | idr_init(&adev->vm_manager.pasid_idr); |
2972 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
a9a78b32 CK |
2973 | } |
2974 | ||
ea89f8c9 CK |
2975 | /** |
2976 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2977 | * | |
2978 | * @adev: amdgpu_device pointer | |
2979 | * | |
2980 | * Cleanup the VM manager and free resources. | |
2981 | */ | |
2982 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2983 | { | |
02208441 FK |
2984 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); |
2985 | idr_destroy(&adev->vm_manager.pasid_idr); | |
2986 | ||
620f774f | 2987 | amdgpu_vmid_mgr_fini(adev); |
ea89f8c9 | 2988 | } |
cfbcacf4 | 2989 | |
7fc48e59 AG |
2990 | /** |
2991 | * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs. | |
2992 | * | |
2993 | * @dev: drm device pointer | |
2994 | * @data: drm_amdgpu_vm | |
2995 | * @filp: drm file pointer | |
2996 | * | |
2997 | * Returns: | |
2998 | * 0 for success, -errno for errors. | |
2999 | */ | |
cfbcacf4 CZ |
3000 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
3001 | { | |
3002 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
3003 | struct amdgpu_device *adev = dev->dev_private; |
3004 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
3005 | int r; | |
cfbcacf4 CZ |
3006 | |
3007 | switch (args->in.op) { | |
3008 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f | 3009 | /* current, we only have requirement to reserve vmid from gfxhub */ |
620f774f | 3010 | r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
1e9ef26f CZ |
3011 | if (r) |
3012 | return r; | |
3013 | break; | |
cfbcacf4 | 3014 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
620f774f | 3015 | amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
3016 | break; |
3017 | default: | |
3018 | return -EINVAL; | |
3019 | } | |
3020 | ||
3021 | return 0; | |
3022 | } | |
2aa37bf5 AG |
3023 | |
3024 | /** | |
3025 | * amdgpu_vm_get_task_info - Extracts task info for a PASID. | |
3026 | * | |
989edc69 | 3027 | * @adev: drm device pointer |
2aa37bf5 AG |
3028 | * @pasid: PASID identifier for VM |
3029 | * @task_info: task_info to fill. | |
3030 | */ | |
3031 | void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid, | |
3032 | struct amdgpu_task_info *task_info) | |
3033 | { | |
3034 | struct amdgpu_vm *vm; | |
0a5f49cb | 3035 | unsigned long flags; |
2aa37bf5 | 3036 | |
0a5f49cb | 3037 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); |
2aa37bf5 AG |
3038 | |
3039 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3040 | if (vm) | |
3041 | *task_info = vm->task_info; | |
3042 | ||
0a5f49cb | 3043 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); |
2aa37bf5 AG |
3044 | } |
3045 | ||
3046 | /** | |
3047 | * amdgpu_vm_set_task_info - Sets VMs task info. | |
3048 | * | |
3049 | * @vm: vm for which to set the info | |
3050 | */ | |
3051 | void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) | |
3052 | { | |
3053 | if (!vm->task_info.pid) { | |
3054 | vm->task_info.pid = current->pid; | |
3055 | get_task_comm(vm->task_info.task_name, current); | |
3056 | ||
3057 | if (current->group_leader->mm == current->mm) { | |
3058 | vm->task_info.tgid = current->group_leader->pid; | |
3059 | get_task_comm(vm->task_info.process_name, current->group_leader); | |
3060 | } | |
3061 | } | |
3062 | } |