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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
1fbb2e92 | 28 | #include <linux/fence-array.h> |
d38ceaf9 AD |
29 | #include <drm/drmP.h> |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu.h" | |
32 | #include "amdgpu_trace.h" | |
33 | ||
34 | /* | |
35 | * GPUVM | |
36 | * GPUVM is similar to the legacy gart on older asics, however | |
37 | * rather than there being a single global gart table | |
38 | * for the entire GPU, there are multiple VM page tables active | |
39 | * at any given time. The VM page tables can contain a mix | |
40 | * vram pages and system memory pages and system memory pages | |
41 | * can be mapped as snooped (cached system pages) or unsnooped | |
42 | * (uncached system pages). | |
43 | * Each VM has an ID associated with it and there is a page table | |
44 | * associated with each VMID. When execting a command buffer, | |
45 | * the kernel tells the the ring what VMID to use for that command | |
46 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
47 | * The userspace drivers maintain their own address space and the kernel | |
48 | * sets up their pages tables accordingly when they submit their | |
49 | * command buffers and a VMID is assigned. | |
50 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
51 | * SI supports 16. | |
52 | */ | |
53 | ||
4ff37a83 CK |
54 | /* Special value that no flush is necessary */ |
55 | #define AMDGPU_VM_NO_FLUSH (~0ll) | |
56 | ||
f4833c4f HK |
57 | /* Local structure. Encapsulate some VM table update parameters to reduce |
58 | * the number of function parameters | |
59 | */ | |
29efc4f5 | 60 | struct amdgpu_pte_update_params { |
27c5f36f CK |
61 | /* amdgpu device we do this update for */ |
62 | struct amdgpu_device *adev; | |
f4833c4f HK |
63 | /* address where to copy page table entries from */ |
64 | uint64_t src; | |
65 | /* DMA addresses to use for mapping */ | |
66 | dma_addr_t *pages_addr; | |
67 | /* indirect buffer to fill with commands */ | |
68 | struct amdgpu_ib *ib; | |
69 | }; | |
70 | ||
d38ceaf9 AD |
71 | /** |
72 | * amdgpu_vm_num_pde - return the number of page directory entries | |
73 | * | |
74 | * @adev: amdgpu_device pointer | |
75 | * | |
8843dbbb | 76 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
77 | */ |
78 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
79 | { | |
80 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
81 | } | |
82 | ||
83 | /** | |
84 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
85 | * | |
86 | * @adev: amdgpu_device pointer | |
87 | * | |
8843dbbb | 88 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
89 | */ |
90 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
91 | { | |
92 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
93 | } | |
94 | ||
95 | /** | |
56467ebf | 96 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
97 | * |
98 | * @vm: vm providing the BOs | |
3c0eea6c | 99 | * @validated: head of validation list |
56467ebf | 100 | * @entry: entry to add |
d38ceaf9 AD |
101 | * |
102 | * Add the page directory to the list of BOs to | |
56467ebf | 103 | * validate for command submission. |
d38ceaf9 | 104 | */ |
56467ebf CK |
105 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
106 | struct list_head *validated, | |
107 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 108 | { |
56467ebf | 109 | entry->robj = vm->page_directory; |
56467ebf CK |
110 | entry->priority = 0; |
111 | entry->tv.bo = &vm->page_directory->tbo; | |
112 | entry->tv.shared = true; | |
2f568dbd | 113 | entry->user_pages = NULL; |
56467ebf CK |
114 | list_add(&entry->tv.head, validated); |
115 | } | |
d38ceaf9 | 116 | |
56467ebf | 117 | /** |
ee1782c3 | 118 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf | 119 | * |
5a712a87 | 120 | * @adev: amdgpu device pointer |
56467ebf | 121 | * @vm: vm providing the BOs |
3c0eea6c | 122 | * @duplicates: head of duplicates list |
d38ceaf9 | 123 | * |
ee1782c3 CK |
124 | * Add the page directory to the BO duplicates list |
125 | * for command submission. | |
d38ceaf9 | 126 | */ |
5a712a87 CK |
127 | void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
128 | struct list_head *duplicates) | |
d38ceaf9 | 129 | { |
5a712a87 | 130 | uint64_t num_evictions; |
ee1782c3 | 131 | unsigned i; |
d38ceaf9 | 132 | |
5a712a87 CK |
133 | /* We only need to validate the page tables |
134 | * if they aren't already valid. | |
135 | */ | |
136 | num_evictions = atomic64_read(&adev->num_evictions); | |
137 | if (num_evictions == vm->last_eviction_counter) | |
138 | return; | |
139 | ||
d38ceaf9 | 140 | /* add the vm page table to the list */ |
ee1782c3 CK |
141 | for (i = 0; i <= vm->max_pde_used; ++i) { |
142 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
143 | ||
144 | if (!entry->robj) | |
d38ceaf9 AD |
145 | continue; |
146 | ||
ee1782c3 | 147 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 148 | } |
eceb8a15 CK |
149 | |
150 | } | |
151 | ||
152 | /** | |
153 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
154 | * | |
155 | * @adev: amdgpu device instance | |
156 | * @vm: vm providing the BOs | |
157 | * | |
158 | * Move the PT BOs to the tail of the LRU. | |
159 | */ | |
160 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
161 | struct amdgpu_vm *vm) | |
162 | { | |
163 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
164 | unsigned i; | |
165 | ||
166 | spin_lock(&glob->lru_lock); | |
167 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
168 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
169 | ||
170 | if (!entry->robj) | |
171 | continue; | |
172 | ||
173 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
174 | } | |
175 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
176 | } |
177 | ||
192b7dcb CZ |
178 | static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev, |
179 | struct amdgpu_vm_id *id) | |
180 | { | |
181 | return id->current_gpu_reset_count != | |
182 | atomic_read(&adev->gpu_reset_counter) ? true : false; | |
183 | } | |
184 | ||
d38ceaf9 AD |
185 | /** |
186 | * amdgpu_vm_grab_id - allocate the next free VMID | |
187 | * | |
d38ceaf9 | 188 | * @vm: vm to allocate id for |
7f8a5290 CK |
189 | * @ring: ring we want to submit job to |
190 | * @sync: sync object where we add dependencies | |
94dd0a4a | 191 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 192 | * |
7f8a5290 | 193 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 194 | */ |
7f8a5290 | 195 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 | 196 | struct amdgpu_sync *sync, struct fence *fence, |
fd53be30 | 197 | struct amdgpu_job *job) |
d38ceaf9 | 198 | { |
d38ceaf9 | 199 | struct amdgpu_device *adev = ring->adev; |
090b767e | 200 | uint64_t fence_context = adev->fence_context + ring->idx; |
4ff37a83 | 201 | struct fence *updates = sync->last_vm_update; |
8d76001e | 202 | struct amdgpu_vm_id *id, *idle; |
1fbb2e92 CK |
203 | struct fence **fences; |
204 | unsigned i; | |
205 | int r = 0; | |
206 | ||
207 | fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids, | |
208 | GFP_KERNEL); | |
209 | if (!fences) | |
210 | return -ENOMEM; | |
d38ceaf9 | 211 | |
94dd0a4a CK |
212 | mutex_lock(&adev->vm_manager.lock); |
213 | ||
36fd7c5c | 214 | /* Check if we have an idle VMID */ |
1fbb2e92 | 215 | i = 0; |
8d76001e | 216 | list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) { |
1fbb2e92 CK |
217 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
218 | if (!fences[i]) | |
36fd7c5c | 219 | break; |
1fbb2e92 | 220 | ++i; |
36fd7c5c CK |
221 | } |
222 | ||
1fbb2e92 | 223 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
8d76001e | 224 | if (&idle->list == &adev->vm_manager.ids_lru) { |
1fbb2e92 CK |
225 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
226 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
227 | struct fence_array *array; | |
228 | unsigned j; | |
229 | ||
230 | for (j = 0; j < i; ++j) | |
231 | fence_get(fences[j]); | |
232 | ||
233 | array = fence_array_create(i, fences, fence_context, | |
234 | seqno, true); | |
235 | if (!array) { | |
236 | for (j = 0; j < i; ++j) | |
237 | fence_put(fences[j]); | |
238 | kfree(fences); | |
239 | r = -ENOMEM; | |
240 | goto error; | |
241 | } | |
242 | ||
243 | ||
244 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
245 | fence_put(&array->base); | |
246 | if (r) | |
247 | goto error; | |
248 | ||
249 | mutex_unlock(&adev->vm_manager.lock); | |
250 | return 0; | |
251 | ||
252 | } | |
253 | kfree(fences); | |
254 | ||
fd53be30 | 255 | job->vm_needs_flush = true; |
1fbb2e92 CK |
256 | /* Check if we can use a VMID already assigned to this VM */ |
257 | i = ring->idx; | |
258 | do { | |
259 | struct fence *flushed; | |
260 | ||
261 | id = vm->ids[i++]; | |
262 | if (i == AMDGPU_MAX_RINGS) | |
263 | i = 0; | |
8d76001e | 264 | |
1fbb2e92 CK |
265 | /* Check all the prerequisites to using this VMID */ |
266 | if (!id) | |
267 | continue; | |
192b7dcb | 268 | if (amdgpu_vm_is_gpu_reset(adev, id)) |
6adb0513 | 269 | continue; |
1fbb2e92 CK |
270 | |
271 | if (atomic64_read(&id->owner) != vm->client_id) | |
272 | continue; | |
273 | ||
fd53be30 | 274 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
275 | continue; |
276 | ||
090b767e CK |
277 | if (!id->last_flush) |
278 | continue; | |
279 | ||
280 | if (id->last_flush->context != fence_context && | |
281 | !fence_is_signaled(id->last_flush)) | |
1fbb2e92 CK |
282 | continue; |
283 | ||
284 | flushed = id->flushed_updates; | |
285 | if (updates && | |
286 | (!flushed || fence_is_later(updates, flushed))) | |
287 | continue; | |
288 | ||
3dab83be CK |
289 | /* Good we can use this VMID. Remember this submission as |
290 | * user of the VMID. | |
291 | */ | |
1fbb2e92 CK |
292 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
293 | if (r) | |
294 | goto error; | |
8d76001e | 295 | |
6adb0513 | 296 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
1fbb2e92 CK |
297 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
298 | vm->ids[ring->idx] = id; | |
8d76001e | 299 | |
fd53be30 CZ |
300 | job->vm_id = id - adev->vm_manager.ids; |
301 | job->vm_needs_flush = false; | |
0c0fdf14 | 302 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
8d76001e | 303 | |
1fbb2e92 CK |
304 | mutex_unlock(&adev->vm_manager.lock); |
305 | return 0; | |
8d76001e | 306 | |
1fbb2e92 | 307 | } while (i != ring->idx); |
8d76001e | 308 | |
1fbb2e92 CK |
309 | /* Still no ID to use? Then use the idle one found earlier */ |
310 | id = idle; | |
8e9fbeb5 | 311 | |
1fbb2e92 CK |
312 | /* Remember this submission as user of the VMID */ |
313 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
314 | if (r) |
315 | goto error; | |
94dd0a4a | 316 | |
832a902f CK |
317 | fence_put(id->first); |
318 | id->first = fence_get(fence); | |
94dd0a4a | 319 | |
41d9eb2c CK |
320 | fence_put(id->last_flush); |
321 | id->last_flush = NULL; | |
322 | ||
832a902f CK |
323 | fence_put(id->flushed_updates); |
324 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 325 | |
fd53be30 | 326 | id->pd_gpu_addr = job->vm_pd_addr; |
b46b8a87 | 327 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
832a902f | 328 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
0ea54b9b | 329 | atomic64_set(&id->owner, vm->client_id); |
832a902f | 330 | vm->ids[ring->idx] = id; |
d38ceaf9 | 331 | |
fd53be30 | 332 | job->vm_id = id - adev->vm_manager.ids; |
0c0fdf14 | 333 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
832a902f CK |
334 | |
335 | error: | |
94dd0a4a | 336 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 337 | return r; |
d38ceaf9 AD |
338 | } |
339 | ||
93dcc37d AD |
340 | static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) |
341 | { | |
342 | struct amdgpu_device *adev = ring->adev; | |
343 | const struct amdgpu_ip_block_version *ip_block; | |
344 | ||
345 | if (ring->type != AMDGPU_RING_TYPE_COMPUTE) | |
346 | /* only compute rings */ | |
347 | return false; | |
348 | ||
349 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
350 | if (!ip_block) | |
351 | return false; | |
352 | ||
353 | if (ip_block->major <= 7) { | |
354 | /* gfx7 has no workaround */ | |
355 | return true; | |
356 | } else if (ip_block->major == 8) { | |
357 | if (adev->gfx.mec_fw_version >= 673) | |
358 | /* gfx8 is fixed in MEC firmware 673 */ | |
359 | return false; | |
360 | else | |
361 | return true; | |
362 | } | |
363 | return false; | |
364 | } | |
365 | ||
d38ceaf9 AD |
366 | /** |
367 | * amdgpu_vm_flush - hardware flush the vm | |
368 | * | |
369 | * @ring: ring to use for flush | |
cffadc83 | 370 | * @vm_id: vmid number to use |
4ff37a83 | 371 | * @pd_addr: address of the page directory |
d38ceaf9 | 372 | * |
4ff37a83 | 373 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 374 | */ |
fd53be30 | 375 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) |
d38ceaf9 | 376 | { |
971fe9a9 | 377 | struct amdgpu_device *adev = ring->adev; |
fd53be30 | 378 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id]; |
d564a06e | 379 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
380 | id->gds_base != job->gds_base || |
381 | id->gds_size != job->gds_size || | |
382 | id->gws_base != job->gws_base || | |
383 | id->gws_size != job->gws_size || | |
384 | id->oa_base != job->oa_base || | |
385 | id->oa_size != job->oa_size); | |
41d9eb2c | 386 | int r; |
d564a06e CK |
387 | |
388 | if (ring->funcs->emit_pipeline_sync && ( | |
fd53be30 | 389 | job->vm_needs_flush || gds_switch_needed || |
93dcc37d | 390 | amdgpu_vm_ring_has_compute_vm_bug(ring))) |
d564a06e | 391 | amdgpu_ring_emit_pipeline_sync(ring); |
971fe9a9 | 392 | |
aa1c8900 CZ |
393 | if (ring->funcs->emit_vm_flush && (job->vm_needs_flush || |
394 | amdgpu_vm_is_gpu_reset(adev, id))) { | |
41d9eb2c CK |
395 | struct fence *fence; |
396 | ||
fd53be30 CZ |
397 | trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id); |
398 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
41d9eb2c | 399 | |
3dab83be CK |
400 | r = amdgpu_fence_emit(ring, &fence); |
401 | if (r) | |
402 | return r; | |
403 | ||
41d9eb2c | 404 | mutex_lock(&adev->vm_manager.lock); |
3dab83be CK |
405 | fence_put(id->last_flush); |
406 | id->last_flush = fence; | |
41d9eb2c | 407 | mutex_unlock(&adev->vm_manager.lock); |
d38ceaf9 | 408 | } |
cffadc83 | 409 | |
d564a06e | 410 | if (gds_switch_needed) { |
fd53be30 CZ |
411 | id->gds_base = job->gds_base; |
412 | id->gds_size = job->gds_size; | |
413 | id->gws_base = job->gws_base; | |
414 | id->gws_size = job->gws_size; | |
415 | id->oa_base = job->oa_base; | |
416 | id->oa_size = job->oa_size; | |
417 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, | |
418 | job->gds_base, job->gds_size, | |
419 | job->gws_base, job->gws_size, | |
420 | job->oa_base, job->oa_size); | |
971fe9a9 | 421 | } |
41d9eb2c CK |
422 | |
423 | return 0; | |
971fe9a9 CK |
424 | } |
425 | ||
426 | /** | |
427 | * amdgpu_vm_reset_id - reset VMID to zero | |
428 | * | |
429 | * @adev: amdgpu device structure | |
430 | * @vm_id: vmid number to use | |
431 | * | |
432 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
433 | */ | |
434 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
435 | { | |
bcb1ba35 CK |
436 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
437 | ||
438 | id->gds_base = 0; | |
439 | id->gds_size = 0; | |
440 | id->gws_base = 0; | |
441 | id->gws_size = 0; | |
442 | id->oa_base = 0; | |
443 | id->oa_size = 0; | |
d38ceaf9 AD |
444 | } |
445 | ||
d38ceaf9 AD |
446 | /** |
447 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
448 | * | |
449 | * @vm: requested vm | |
450 | * @bo: requested buffer object | |
451 | * | |
8843dbbb | 452 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
453 | * Search inside the @bos vm list for the requested vm |
454 | * Returns the found bo_va or NULL if none is found | |
455 | * | |
456 | * Object has to be reserved! | |
457 | */ | |
458 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
459 | struct amdgpu_bo *bo) | |
460 | { | |
461 | struct amdgpu_bo_va *bo_va; | |
462 | ||
463 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
464 | if (bo_va->vm == vm) { | |
465 | return bo_va; | |
466 | } | |
467 | } | |
468 | return NULL; | |
469 | } | |
470 | ||
471 | /** | |
472 | * amdgpu_vm_update_pages - helper to call the right asic function | |
473 | * | |
29efc4f5 | 474 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
475 | * @pe: addr of the page entry |
476 | * @addr: dst addr to write into pe | |
477 | * @count: number of page entries to update | |
478 | * @incr: increase next addr by incr bytes | |
479 | * @flags: hw access flags | |
d38ceaf9 AD |
480 | * |
481 | * Traces the parameters and calls the right asic functions | |
482 | * to setup the page table using the DMA. | |
483 | */ | |
27c5f36f | 484 | static void amdgpu_vm_update_pages(struct amdgpu_pte_update_params *params, |
d38ceaf9 AD |
485 | uint64_t pe, uint64_t addr, |
486 | unsigned count, uint32_t incr, | |
9ab21462 | 487 | uint32_t flags) |
d38ceaf9 AD |
488 | { |
489 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
490 | ||
29efc4f5 | 491 | if (params->src) { |
27c5f36f | 492 | amdgpu_vm_copy_pte(params->adev, params->ib, |
29efc4f5 | 493 | pe, (params->src + (addr >> 12) * 8), count); |
d38ceaf9 | 494 | |
29efc4f5 | 495 | } else if (params->pages_addr) { |
27c5f36f | 496 | amdgpu_vm_write_pte(params->adev, params->ib, |
29efc4f5 | 497 | params->pages_addr, |
f4833c4f | 498 | pe, addr, count, incr, flags); |
b07c9d2a CK |
499 | |
500 | } else if (count < 3) { | |
27c5f36f | 501 | amdgpu_vm_write_pte(params->adev, params->ib, NULL, pe, addr, |
b07c9d2a | 502 | count, incr, flags); |
d38ceaf9 AD |
503 | |
504 | } else { | |
27c5f36f | 505 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
506 | count, incr, flags); |
507 | } | |
508 | } | |
509 | ||
510 | /** | |
511 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
512 | * | |
513 | * @adev: amdgpu_device pointer | |
514 | * @bo: bo to clear | |
ef9f0a83 CZ |
515 | * |
516 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
517 | */ |
518 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 519 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
520 | struct amdgpu_bo *bo) |
521 | { | |
2d55e45a | 522 | struct amdgpu_ring *ring; |
4af9f07c | 523 | struct fence *fence = NULL; |
d71518b5 | 524 | struct amdgpu_job *job; |
29efc4f5 | 525 | struct amdgpu_pte_update_params params; |
d38ceaf9 AD |
526 | unsigned entries; |
527 | uint64_t addr; | |
528 | int r; | |
529 | ||
2d55e45a CK |
530 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
531 | ||
ca952613 | 532 | r = reservation_object_reserve_shared(bo->tbo.resv); |
533 | if (r) | |
534 | return r; | |
535 | ||
d38ceaf9 AD |
536 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
537 | if (r) | |
ef9f0a83 | 538 | goto error; |
d38ceaf9 AD |
539 | |
540 | addr = amdgpu_bo_gpu_offset(bo); | |
541 | entries = amdgpu_bo_size(bo) / 8; | |
542 | ||
d71518b5 CK |
543 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
544 | if (r) | |
ef9f0a83 | 545 | goto error; |
d38ceaf9 | 546 | |
27c5f36f CK |
547 | memset(¶ms, 0, sizeof(params)); |
548 | params.adev = adev; | |
29efc4f5 | 549 | params.ib = &job->ibs[0]; |
27c5f36f | 550 | amdgpu_vm_update_pages(¶ms, addr, 0, entries, 0, 0); |
d71518b5 CK |
551 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
552 | ||
553 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
554 | r = amdgpu_job_submit(job, ring, &vm->entity, |
555 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
556 | if (r) |
557 | goto error_free; | |
558 | ||
d71518b5 | 559 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 560 | fence_put(fence); |
cadf97b1 | 561 | return 0; |
ef9f0a83 | 562 | |
d38ceaf9 | 563 | error_free: |
d71518b5 | 564 | amdgpu_job_free(job); |
d38ceaf9 | 565 | |
ef9f0a83 | 566 | error: |
d38ceaf9 AD |
567 | return r; |
568 | } | |
569 | ||
570 | /** | |
b07c9d2a | 571 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 572 | * |
b07c9d2a | 573 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
574 | * @addr: the unmapped addr |
575 | * | |
576 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 577 | * to and return the pointer for the page table entry. |
d38ceaf9 | 578 | */ |
b07c9d2a | 579 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
580 | { |
581 | uint64_t result; | |
582 | ||
b07c9d2a CK |
583 | if (pages_addr) { |
584 | /* page table offset */ | |
585 | result = pages_addr[addr >> PAGE_SHIFT]; | |
586 | ||
587 | /* in case cpu page size != gpu page size*/ | |
588 | result |= addr & (~PAGE_MASK); | |
589 | ||
590 | } else { | |
591 | /* No mapping required */ | |
592 | result = addr; | |
593 | } | |
d38ceaf9 | 594 | |
b07c9d2a | 595 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
596 | |
597 | return result; | |
598 | } | |
599 | ||
600 | /** | |
601 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
602 | * | |
603 | * @adev: amdgpu_device pointer | |
604 | * @vm: requested vm | |
605 | * @start: start of GPU address range | |
606 | * @end: end of GPU address range | |
607 | * | |
608 | * Allocates new page tables if necessary | |
8843dbbb | 609 | * and updates the page directory. |
d38ceaf9 | 610 | * Returns 0 for success, error for failure. |
d38ceaf9 AD |
611 | */ |
612 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
613 | struct amdgpu_vm *vm) | |
614 | { | |
2d55e45a | 615 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
616 | struct amdgpu_bo *pd = vm->page_directory; |
617 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
618 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
619 | uint64_t last_pde = ~0, last_pt = ~0; | |
620 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 621 | struct amdgpu_job *job; |
29efc4f5 | 622 | struct amdgpu_pte_update_params params; |
4af9f07c | 623 | struct fence *fence = NULL; |
d5fc5e82 | 624 | |
d38ceaf9 AD |
625 | int r; |
626 | ||
2d55e45a CK |
627 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
628 | ||
d38ceaf9 AD |
629 | /* padding, etc. */ |
630 | ndw = 64; | |
631 | ||
632 | /* assume the worst case */ | |
633 | ndw += vm->max_pde_used * 6; | |
634 | ||
d71518b5 CK |
635 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
636 | if (r) | |
d38ceaf9 | 637 | return r; |
d71518b5 | 638 | |
27c5f36f CK |
639 | memset(¶ms, 0, sizeof(params)); |
640 | params.adev = adev; | |
29efc4f5 | 641 | params.ib = &job->ibs[0]; |
d38ceaf9 AD |
642 | |
643 | /* walk over the address space and update the page directory */ | |
644 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 645 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
646 | uint64_t pde, pt; |
647 | ||
648 | if (bo == NULL) | |
649 | continue; | |
650 | ||
651 | pt = amdgpu_bo_gpu_offset(bo); | |
652 | if (vm->page_tables[pt_idx].addr == pt) | |
653 | continue; | |
654 | vm->page_tables[pt_idx].addr = pt; | |
655 | ||
656 | pde = pd_addr + pt_idx * 8; | |
657 | if (((last_pde + 8 * count) != pde) || | |
658 | ((last_pt + incr * count) != pt)) { | |
659 | ||
660 | if (count) { | |
27c5f36f CK |
661 | amdgpu_vm_update_pages(¶ms, last_pde, |
662 | last_pt, count, incr, | |
9ab21462 | 663 | AMDGPU_PTE_VALID); |
d38ceaf9 AD |
664 | } |
665 | ||
666 | count = 1; | |
667 | last_pde = pde; | |
668 | last_pt = pt; | |
669 | } else { | |
670 | ++count; | |
671 | } | |
672 | } | |
673 | ||
674 | if (count) | |
27c5f36f | 675 | amdgpu_vm_update_pages(¶ms, last_pde, last_pt, |
f4833c4f | 676 | count, incr, AMDGPU_PTE_VALID); |
d38ceaf9 | 677 | |
29efc4f5 CK |
678 | if (params.ib->length_dw != 0) { |
679 | amdgpu_ring_pad_ib(ring, params.ib); | |
e86f9cee CK |
680 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
681 | AMDGPU_FENCE_OWNER_VM); | |
29efc4f5 | 682 | WARN_ON(params.ib->length_dw > ndw); |
2bd9ccfa CK |
683 | r = amdgpu_job_submit(job, ring, &vm->entity, |
684 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
685 | if (r) |
686 | goto error_free; | |
05906dec | 687 | |
4af9f07c | 688 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
689 | fence_put(vm->page_directory_fence); |
690 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 691 | fence_put(fence); |
d5fc5e82 | 692 | |
d71518b5 CK |
693 | } else { |
694 | amdgpu_job_free(job); | |
d5fc5e82 | 695 | } |
d38ceaf9 AD |
696 | |
697 | return 0; | |
d5fc5e82 CZ |
698 | |
699 | error_free: | |
d71518b5 | 700 | amdgpu_job_free(job); |
4af9f07c | 701 | return r; |
d38ceaf9 AD |
702 | } |
703 | ||
d38ceaf9 AD |
704 | /** |
705 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
706 | * | |
29efc4f5 | 707 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
708 | * @vm: requested vm |
709 | * @start: start of GPU address range | |
710 | * @end: end of GPU address range | |
677131a1 | 711 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
712 | * @flags: mapping flags |
713 | * | |
8843dbbb | 714 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 715 | */ |
27c5f36f | 716 | static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 717 | struct amdgpu_vm *vm, |
a1e08d3b CK |
718 | uint64_t start, uint64_t end, |
719 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 720 | { |
31f6c1fe CK |
721 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
722 | ||
92696dd5 | 723 | uint64_t cur_pe_start, cur_nptes, cur_dst; |
677131a1 | 724 | uint64_t addr; /* next GPU address to be updated */ |
21718497 AX |
725 | uint64_t pt_idx; |
726 | struct amdgpu_bo *pt; | |
727 | unsigned nptes; /* next number of ptes to be updated */ | |
728 | uint64_t next_pe_start; | |
729 | ||
730 | /* initialize the variables */ | |
731 | addr = start; | |
732 | pt_idx = addr >> amdgpu_vm_block_size; | |
733 | pt = vm->page_tables[pt_idx].entry.robj; | |
734 | ||
735 | if ((addr & ~mask) == (end & ~mask)) | |
736 | nptes = end - addr; | |
737 | else | |
738 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
739 | ||
740 | cur_pe_start = amdgpu_bo_gpu_offset(pt); | |
741 | cur_pe_start += (addr & mask) * 8; | |
92696dd5 | 742 | cur_nptes = nptes; |
21718497 AX |
743 | cur_dst = dst; |
744 | ||
745 | /* for next ptb*/ | |
746 | addr += nptes; | |
747 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
d38ceaf9 AD |
748 | |
749 | /* walk over the address space and update the page tables */ | |
21718497 AX |
750 | while (addr < end) { |
751 | pt_idx = addr >> amdgpu_vm_block_size; | |
752 | pt = vm->page_tables[pt_idx].entry.robj; | |
d38ceaf9 AD |
753 | |
754 | if ((addr & ~mask) == (end & ~mask)) | |
755 | nptes = end - addr; | |
756 | else | |
757 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
758 | ||
677131a1 AX |
759 | next_pe_start = amdgpu_bo_gpu_offset(pt); |
760 | next_pe_start += (addr & mask) * 8; | |
d38ceaf9 | 761 | |
92696dd5 | 762 | if ((cur_pe_start + 8 * cur_nptes) == next_pe_start) { |
3a6f8e0c | 763 | /* The next ptb is consecutive to current ptb. |
92696dd5 | 764 | * Don't call amdgpu_vm_update_pages now. |
3a6f8e0c AX |
765 | * Will update two ptbs together in future. |
766 | */ | |
92696dd5 | 767 | cur_nptes += nptes; |
3a6f8e0c | 768 | } else { |
92696dd5 CK |
769 | amdgpu_vm_update_pages(params, cur_pe_start, cur_dst, |
770 | cur_nptes, AMDGPU_GPU_PAGE_SIZE, | |
771 | flags); | |
d38ceaf9 | 772 | |
677131a1 | 773 | cur_pe_start = next_pe_start; |
92696dd5 | 774 | cur_nptes = nptes; |
677131a1 | 775 | cur_dst = dst; |
d38ceaf9 AD |
776 | } |
777 | ||
21718497 | 778 | /* for next ptb*/ |
d38ceaf9 AD |
779 | addr += nptes; |
780 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
781 | } | |
782 | ||
92696dd5 CK |
783 | amdgpu_vm_update_pages(params, cur_pe_start, cur_dst, cur_nptes, |
784 | AMDGPU_GPU_PAGE_SIZE, flags); | |
785 | } | |
786 | ||
787 | /* | |
788 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
789 | * | |
790 | * @params: see amdgpu_pte_update_params definition | |
791 | * @vm: requested vm | |
792 | * @start: first PTE to handle | |
793 | * @end: last PTE to handle | |
794 | * @dst: addr those PTEs should point to | |
795 | * @flags: hw mapping flags | |
796 | */ | |
797 | static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, | |
798 | struct amdgpu_vm *vm, | |
799 | uint64_t start, uint64_t end, | |
800 | uint64_t dst, uint32_t flags) | |
801 | { | |
802 | /** | |
803 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
804 | * field in the PTE. When this field is set to a non-zero value, page | |
805 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
806 | * flags are considered valid for all PTEs within the fragment range | |
807 | * and corresponding mappings are assumed to be physically contiguous. | |
808 | * | |
809 | * The L1 TLB can store a single PTE for the whole fragment, | |
810 | * significantly increasing the space available for translation | |
811 | * caching. This leads to large improvements in throughput when the | |
812 | * TLB is under pressure. | |
813 | * | |
814 | * The L2 TLB distributes small and large fragments into two | |
815 | * asymmetric partitions. The large fragment cache is significantly | |
816 | * larger. Thus, we try to use large fragments wherever possible. | |
817 | * Userspace can support this by aligning virtual base address and | |
818 | * allocation size to the fragment size. | |
819 | */ | |
820 | ||
e2b84e4b | 821 | const uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG; |
92696dd5 CK |
822 | |
823 | uint64_t frag_start = ALIGN(start, frag_align); | |
824 | uint64_t frag_end = end & ~(frag_align - 1); | |
825 | ||
e2b84e4b CK |
826 | uint32_t frag; |
827 | ||
92696dd5 CK |
828 | /* system pages are non continuously */ |
829 | if (params->src || params->pages_addr || !(flags & AMDGPU_PTE_VALID) || | |
830 | (frag_start >= frag_end)) { | |
831 | ||
832 | amdgpu_vm_update_ptes(params, vm, start, end, dst, flags); | |
833 | return; | |
834 | } | |
835 | ||
e2b84e4b CK |
836 | /* use more than 64KB fragment size if possible */ |
837 | frag = lower_32_bits(frag_start | frag_end); | |
838 | frag = likely(frag) ? __ffs(frag) : 31; | |
839 | ||
92696dd5 CK |
840 | /* handle the 4K area at the beginning */ |
841 | if (start != frag_start) { | |
842 | amdgpu_vm_update_ptes(params, vm, start, frag_start, | |
843 | dst, flags); | |
844 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; | |
845 | } | |
846 | ||
847 | /* handle the area in the middle */ | |
848 | amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst, | |
e2b84e4b | 849 | flags | AMDGPU_PTE_FRAG(frag)); |
92696dd5 CK |
850 | |
851 | /* handle the 4K area at the end */ | |
852 | if (frag_end != end) { | |
853 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
854 | amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags); | |
855 | } | |
d38ceaf9 AD |
856 | } |
857 | ||
d38ceaf9 AD |
858 | /** |
859 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
860 | * | |
861 | * @adev: amdgpu_device pointer | |
3cabaa54 | 862 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
863 | * @src: address where to copy page table entries from |
864 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 865 | * @vm: requested vm |
a14faa65 CK |
866 | * @start: start of mapped range |
867 | * @last: last mapped entry | |
868 | * @flags: flags for the entries | |
d38ceaf9 | 869 | * @addr: addr to set the area to |
d38ceaf9 AD |
870 | * @fence: optional resulting fence |
871 | * | |
a14faa65 | 872 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 873 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
874 | */ |
875 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
3cabaa54 | 876 | struct fence *exclusive, |
fa3ab3c7 CK |
877 | uint64_t src, |
878 | dma_addr_t *pages_addr, | |
d38ceaf9 | 879 | struct amdgpu_vm *vm, |
a14faa65 CK |
880 | uint64_t start, uint64_t last, |
881 | uint32_t flags, uint64_t addr, | |
882 | struct fence **fence) | |
d38ceaf9 | 883 | { |
2d55e45a | 884 | struct amdgpu_ring *ring; |
a1e08d3b | 885 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 886 | unsigned nptes, ncmds, ndw; |
d71518b5 | 887 | struct amdgpu_job *job; |
29efc4f5 | 888 | struct amdgpu_pte_update_params params; |
4af9f07c | 889 | struct fence *f = NULL; |
d38ceaf9 AD |
890 | int r; |
891 | ||
2d55e45a | 892 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 893 | |
29efc4f5 | 894 | memset(¶ms, 0, sizeof(params)); |
27c5f36f | 895 | params.adev = adev; |
29efc4f5 CK |
896 | params.src = src; |
897 | params.pages_addr = pages_addr; | |
2d55e45a | 898 | |
a1e08d3b CK |
899 | /* sync to everything on unmapping */ |
900 | if (!(flags & AMDGPU_PTE_VALID)) | |
901 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
902 | ||
a14faa65 | 903 | nptes = last - start + 1; |
d38ceaf9 AD |
904 | |
905 | /* | |
906 | * reserve space for one command every (1 << BLOCK_SIZE) | |
907 | * entries or 2k dwords (whatever is smaller) | |
908 | */ | |
909 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
910 | ||
911 | /* padding, etc. */ | |
912 | ndw = 64; | |
913 | ||
b0456f93 | 914 | if (src) { |
d38ceaf9 AD |
915 | /* only copy commands needed */ |
916 | ndw += ncmds * 7; | |
917 | ||
b0456f93 CK |
918 | } else if (pages_addr) { |
919 | /* copy commands needed */ | |
920 | ndw += ncmds * 7; | |
d38ceaf9 | 921 | |
b0456f93 | 922 | /* and also PTEs */ |
d38ceaf9 AD |
923 | ndw += nptes * 2; |
924 | ||
925 | } else { | |
926 | /* set page commands needed */ | |
927 | ndw += ncmds * 10; | |
928 | ||
929 | /* two extra commands for begin/end of fragment */ | |
930 | ndw += 2 * 10; | |
931 | } | |
932 | ||
d71518b5 CK |
933 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
934 | if (r) | |
d38ceaf9 | 935 | return r; |
d71518b5 | 936 | |
29efc4f5 | 937 | params.ib = &job->ibs[0]; |
d5fc5e82 | 938 | |
b0456f93 CK |
939 | if (!src && pages_addr) { |
940 | uint64_t *pte; | |
941 | unsigned i; | |
942 | ||
943 | /* Put the PTEs at the end of the IB. */ | |
944 | i = ndw - nptes * 2; | |
945 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
946 | params.src = job->ibs->gpu_addr + i * 4; | |
947 | ||
948 | for (i = 0; i < nptes; ++i) { | |
949 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
950 | AMDGPU_GPU_PAGE_SIZE); | |
951 | pte[i] |= flags; | |
952 | } | |
953 | } | |
954 | ||
3cabaa54 CK |
955 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
956 | if (r) | |
957 | goto error_free; | |
958 | ||
e86f9cee | 959 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
960 | owner); |
961 | if (r) | |
962 | goto error_free; | |
d38ceaf9 | 963 | |
a1e08d3b CK |
964 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
965 | if (r) | |
966 | goto error_free; | |
967 | ||
92696dd5 | 968 | amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags); |
d38ceaf9 | 969 | |
29efc4f5 CK |
970 | amdgpu_ring_pad_ib(ring, params.ib); |
971 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
972 | r = amdgpu_job_submit(job, ring, &vm->entity, |
973 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
974 | if (r) |
975 | goto error_free; | |
d38ceaf9 | 976 | |
bf60efd3 | 977 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
978 | if (fence) { |
979 | fence_put(*fence); | |
980 | *fence = fence_get(f); | |
981 | } | |
281b4223 | 982 | fence_put(f); |
d38ceaf9 | 983 | return 0; |
d5fc5e82 CZ |
984 | |
985 | error_free: | |
d71518b5 | 986 | amdgpu_job_free(job); |
4af9f07c | 987 | return r; |
d38ceaf9 AD |
988 | } |
989 | ||
a14faa65 CK |
990 | /** |
991 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
992 | * | |
993 | * @adev: amdgpu_device pointer | |
3cabaa54 | 994 | * @exclusive: fence we need to sync to |
8358dcee CK |
995 | * @gtt_flags: flags as they are used for GTT |
996 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
997 | * @vm: requested vm |
998 | * @mapping: mapped range and flags to use for the update | |
999 | * @addr: addr to set the area to | |
8358dcee | 1000 | * @flags: HW flags for the mapping |
a14faa65 CK |
1001 | * @fence: optional resulting fence |
1002 | * | |
1003 | * Split the mapping into smaller chunks so that each update fits | |
1004 | * into a SDMA IB. | |
1005 | * Returns 0 for success, -EINVAL for failure. | |
1006 | */ | |
1007 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
3cabaa54 | 1008 | struct fence *exclusive, |
a14faa65 | 1009 | uint32_t gtt_flags, |
8358dcee | 1010 | dma_addr_t *pages_addr, |
a14faa65 CK |
1011 | struct amdgpu_vm *vm, |
1012 | struct amdgpu_bo_va_mapping *mapping, | |
fa3ab3c7 CK |
1013 | uint32_t flags, uint64_t addr, |
1014 | struct fence **fence) | |
a14faa65 CK |
1015 | { |
1016 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
1017 | ||
fa3ab3c7 | 1018 | uint64_t src = 0, start = mapping->it.start; |
a14faa65 CK |
1019 | int r; |
1020 | ||
1021 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1022 | * but in case of something, we filter the flags in first place | |
1023 | */ | |
1024 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1025 | flags &= ~AMDGPU_PTE_READABLE; | |
1026 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1027 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1028 | ||
1029 | trace_amdgpu_vm_bo_update(mapping); | |
1030 | ||
8358dcee | 1031 | if (pages_addr) { |
fa3ab3c7 CK |
1032 | if (flags == gtt_flags) |
1033 | src = adev->gart.table_addr + (addr >> 12) * 8; | |
fa3ab3c7 CK |
1034 | addr = 0; |
1035 | } | |
a14faa65 CK |
1036 | addr += mapping->offset; |
1037 | ||
8358dcee | 1038 | if (!pages_addr || src) |
3cabaa54 CK |
1039 | return amdgpu_vm_bo_update_mapping(adev, exclusive, |
1040 | src, pages_addr, vm, | |
a14faa65 CK |
1041 | start, mapping->it.last, |
1042 | flags, addr, fence); | |
1043 | ||
1044 | while (start != mapping->it.last + 1) { | |
1045 | uint64_t last; | |
1046 | ||
fb29b57c | 1047 | last = min((uint64_t)mapping->it.last, start + max_size - 1); |
3cabaa54 CK |
1048 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1049 | src, pages_addr, vm, | |
a14faa65 CK |
1050 | start, last, flags, addr, |
1051 | fence); | |
1052 | if (r) | |
1053 | return r; | |
1054 | ||
1055 | start = last + 1; | |
fb29b57c | 1056 | addr += max_size * AMDGPU_GPU_PAGE_SIZE; |
a14faa65 CK |
1057 | } |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
d38ceaf9 AD |
1062 | /** |
1063 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1064 | * | |
1065 | * @adev: amdgpu_device pointer | |
1066 | * @bo_va: requested BO and VM object | |
1067 | * @mem: ttm mem | |
1068 | * | |
1069 | * Fill in the page table entries for @bo_va. | |
1070 | * Returns 0 for success, -EINVAL for failure. | |
1071 | * | |
1072 | * Object have to be reserved and mutex must be locked! | |
1073 | */ | |
1074 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1075 | struct amdgpu_bo_va *bo_va, | |
1076 | struct ttm_mem_reg *mem) | |
1077 | { | |
1078 | struct amdgpu_vm *vm = bo_va->vm; | |
1079 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1080 | dma_addr_t *pages_addr = NULL; |
fa3ab3c7 | 1081 | uint32_t gtt_flags, flags; |
3cabaa54 | 1082 | struct fence *exclusive; |
d38ceaf9 AD |
1083 | uint64_t addr; |
1084 | int r; | |
1085 | ||
1086 | if (mem) { | |
8358dcee CK |
1087 | struct ttm_dma_tt *ttm; |
1088 | ||
b7d698d7 | 1089 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
1090 | switch (mem->mem_type) { |
1091 | case TTM_PL_TT: | |
8358dcee CK |
1092 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1093 | ttm_dma_tt, ttm); | |
1094 | pages_addr = ttm->dma_address; | |
9ab21462 CK |
1095 | break; |
1096 | ||
1097 | case TTM_PL_VRAM: | |
d38ceaf9 | 1098 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
1099 | break; |
1100 | ||
1101 | default: | |
1102 | break; | |
1103 | } | |
3cabaa54 CK |
1104 | |
1105 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); | |
d38ceaf9 AD |
1106 | } else { |
1107 | addr = 0; | |
3cabaa54 | 1108 | exclusive = NULL; |
d38ceaf9 AD |
1109 | } |
1110 | ||
d38ceaf9 | 1111 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
fa3ab3c7 | 1112 | gtt_flags = (adev == bo_va->bo->adev) ? flags : 0; |
d38ceaf9 | 1113 | |
7fc11959 CK |
1114 | spin_lock(&vm->status_lock); |
1115 | if (!list_empty(&bo_va->vm_status)) | |
1116 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1117 | spin_unlock(&vm->status_lock); | |
1118 | ||
1119 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1120 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1121 | gtt_flags, pages_addr, vm, | |
8358dcee CK |
1122 | mapping, flags, addr, |
1123 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
1124 | if (r) |
1125 | return r; | |
1126 | } | |
1127 | ||
d6c10f6b CK |
1128 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1129 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1130 | trace_amdgpu_vm_bo_mapping(mapping); | |
1131 | ||
1132 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1133 | trace_amdgpu_vm_bo_mapping(mapping); | |
1134 | } | |
1135 | ||
d38ceaf9 | 1136 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1137 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1138 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
1139 | if (!mem) |
1140 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
1141 | spin_unlock(&vm->status_lock); |
1142 | ||
1143 | return 0; | |
1144 | } | |
1145 | ||
1146 | /** | |
1147 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1148 | * | |
1149 | * @adev: amdgpu_device pointer | |
1150 | * @vm: requested vm | |
1151 | * | |
1152 | * Make sure all freed BOs are cleared in the PT. | |
1153 | * Returns 0 for success. | |
1154 | * | |
1155 | * PTs have to be reserved and mutex must be locked! | |
1156 | */ | |
1157 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
1158 | struct amdgpu_vm *vm) | |
1159 | { | |
1160 | struct amdgpu_bo_va_mapping *mapping; | |
1161 | int r; | |
1162 | ||
1163 | while (!list_empty(&vm->freed)) { | |
1164 | mapping = list_first_entry(&vm->freed, | |
1165 | struct amdgpu_bo_va_mapping, list); | |
1166 | list_del(&mapping->list); | |
e17841b9 | 1167 | |
3cabaa54 | 1168 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping, |
fa3ab3c7 | 1169 | 0, 0, NULL); |
d38ceaf9 AD |
1170 | kfree(mapping); |
1171 | if (r) | |
1172 | return r; | |
1173 | ||
1174 | } | |
1175 | return 0; | |
1176 | ||
1177 | } | |
1178 | ||
1179 | /** | |
1180 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1181 | * | |
1182 | * @adev: amdgpu_device pointer | |
1183 | * @vm: requested vm | |
1184 | * | |
1185 | * Make sure all invalidated BOs are cleared in the PT. | |
1186 | * Returns 0 for success. | |
1187 | * | |
1188 | * PTs have to be reserved and mutex must be locked! | |
1189 | */ | |
1190 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1191 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1192 | { |
cfe2c978 | 1193 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1194 | int r = 0; |
d38ceaf9 AD |
1195 | |
1196 | spin_lock(&vm->status_lock); | |
1197 | while (!list_empty(&vm->invalidated)) { | |
1198 | bo_va = list_first_entry(&vm->invalidated, | |
1199 | struct amdgpu_bo_va, vm_status); | |
1200 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1201 | |
d38ceaf9 AD |
1202 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
1203 | if (r) | |
1204 | return r; | |
1205 | ||
1206 | spin_lock(&vm->status_lock); | |
1207 | } | |
1208 | spin_unlock(&vm->status_lock); | |
1209 | ||
cfe2c978 | 1210 | if (bo_va) |
bb1e38a4 | 1211 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1212 | |
1213 | return r; | |
d38ceaf9 AD |
1214 | } |
1215 | ||
1216 | /** | |
1217 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1218 | * | |
1219 | * @adev: amdgpu_device pointer | |
1220 | * @vm: requested vm | |
1221 | * @bo: amdgpu buffer object | |
1222 | * | |
8843dbbb | 1223 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1224 | * Add @bo to the list of bos associated with the vm |
1225 | * Returns newly added bo_va or NULL for failure | |
1226 | * | |
1227 | * Object has to be reserved! | |
1228 | */ | |
1229 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1230 | struct amdgpu_vm *vm, | |
1231 | struct amdgpu_bo *bo) | |
1232 | { | |
1233 | struct amdgpu_bo_va *bo_va; | |
1234 | ||
1235 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1236 | if (bo_va == NULL) { | |
1237 | return NULL; | |
1238 | } | |
1239 | bo_va->vm = vm; | |
1240 | bo_va->bo = bo; | |
d38ceaf9 AD |
1241 | bo_va->ref_count = 1; |
1242 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1243 | INIT_LIST_HEAD(&bo_va->valids); |
1244 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1245 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1246 | |
d38ceaf9 | 1247 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1248 | |
1249 | return bo_va; | |
1250 | } | |
1251 | ||
1252 | /** | |
1253 | * amdgpu_vm_bo_map - map bo inside a vm | |
1254 | * | |
1255 | * @adev: amdgpu_device pointer | |
1256 | * @bo_va: bo_va to store the address | |
1257 | * @saddr: where to map the BO | |
1258 | * @offset: requested offset in the BO | |
1259 | * @flags: attributes of pages (read/write/valid/etc.) | |
1260 | * | |
1261 | * Add a mapping of the BO at the specefied addr into the VM. | |
1262 | * Returns 0 for success, error for failure. | |
1263 | * | |
49b02b18 | 1264 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1265 | */ |
1266 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1267 | struct amdgpu_bo_va *bo_va, | |
1268 | uint64_t saddr, uint64_t offset, | |
1269 | uint64_t size, uint32_t flags) | |
1270 | { | |
1271 | struct amdgpu_bo_va_mapping *mapping; | |
1272 | struct amdgpu_vm *vm = bo_va->vm; | |
1273 | struct interval_tree_node *it; | |
1274 | unsigned last_pfn, pt_idx; | |
1275 | uint64_t eaddr; | |
1276 | int r; | |
1277 | ||
0be52de9 CK |
1278 | /* validate the parameters */ |
1279 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1280 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1281 | return -EINVAL; |
0be52de9 | 1282 | |
d38ceaf9 | 1283 | /* make sure object fit at this offset */ |
005ae95e | 1284 | eaddr = saddr + size - 1; |
49b02b18 | 1285 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1286 | return -EINVAL; |
d38ceaf9 AD |
1287 | |
1288 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1289 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1290 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1291 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1292 | return -EINVAL; |
1293 | } | |
1294 | ||
d38ceaf9 AD |
1295 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1296 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1297 | ||
005ae95e | 1298 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
d38ceaf9 AD |
1299 | if (it) { |
1300 | struct amdgpu_bo_va_mapping *tmp; | |
1301 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1302 | /* bo and tmp overlap, invalid addr */ | |
1303 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1304 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1305 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1306 | r = -EINVAL; |
f48b2659 | 1307 | goto error; |
d38ceaf9 AD |
1308 | } |
1309 | ||
1310 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1311 | if (!mapping) { | |
d38ceaf9 | 1312 | r = -ENOMEM; |
f48b2659 | 1313 | goto error; |
d38ceaf9 AD |
1314 | } |
1315 | ||
1316 | INIT_LIST_HEAD(&mapping->list); | |
1317 | mapping->it.start = saddr; | |
005ae95e | 1318 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1319 | mapping->offset = offset; |
1320 | mapping->flags = flags; | |
1321 | ||
7fc11959 | 1322 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 AD |
1323 | interval_tree_insert(&mapping->it, &vm->va); |
1324 | ||
1325 | /* Make sure the page tables are allocated */ | |
1326 | saddr >>= amdgpu_vm_block_size; | |
1327 | eaddr >>= amdgpu_vm_block_size; | |
1328 | ||
1329 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1330 | ||
1331 | if (eaddr > vm->max_pde_used) | |
1332 | vm->max_pde_used = eaddr; | |
1333 | ||
d38ceaf9 AD |
1334 | /* walk over the address space and allocate the page tables */ |
1335 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1336 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1337 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1338 | struct amdgpu_bo *pt; |
1339 | ||
ee1782c3 CK |
1340 | entry = &vm->page_tables[pt_idx].entry; |
1341 | if (entry->robj) | |
d38ceaf9 AD |
1342 | continue; |
1343 | ||
d38ceaf9 AD |
1344 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1345 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d | 1346 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f CZ |
1347 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
1348 | AMDGPU_GEM_CREATE_SHADOW, | |
bf60efd3 | 1349 | NULL, resv, &pt); |
49b02b18 | 1350 | if (r) |
d38ceaf9 | 1351 | goto error_free; |
49b02b18 | 1352 | |
82b9c55b CK |
1353 | /* Keep a reference to the page table to avoid freeing |
1354 | * them up in the wrong order. | |
1355 | */ | |
1356 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1357 | ||
2bd9ccfa | 1358 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 AD |
1359 | if (r) { |
1360 | amdgpu_bo_unref(&pt); | |
1361 | goto error_free; | |
1362 | } | |
1363 | ||
ee1782c3 | 1364 | entry->robj = pt; |
ee1782c3 CK |
1365 | entry->priority = 0; |
1366 | entry->tv.bo = &entry->robj->tbo; | |
1367 | entry->tv.shared = true; | |
2f568dbd | 1368 | entry->user_pages = NULL; |
d38ceaf9 | 1369 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1370 | } |
1371 | ||
d38ceaf9 AD |
1372 | return 0; |
1373 | ||
1374 | error_free: | |
d38ceaf9 AD |
1375 | list_del(&mapping->list); |
1376 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1377 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1378 | kfree(mapping); |
1379 | ||
f48b2659 | 1380 | error: |
d38ceaf9 AD |
1381 | return r; |
1382 | } | |
1383 | ||
1384 | /** | |
1385 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1386 | * | |
1387 | * @adev: amdgpu_device pointer | |
1388 | * @bo_va: bo_va to remove the address from | |
1389 | * @saddr: where to the BO is mapped | |
1390 | * | |
1391 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1392 | * Returns 0 for success, error for failure. | |
1393 | * | |
49b02b18 | 1394 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1395 | */ |
1396 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1397 | struct amdgpu_bo_va *bo_va, | |
1398 | uint64_t saddr) | |
1399 | { | |
1400 | struct amdgpu_bo_va_mapping *mapping; | |
1401 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1402 | bool valid = true; |
d38ceaf9 | 1403 | |
6c7fc503 | 1404 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1405 | |
7fc11959 | 1406 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1407 | if (mapping->it.start == saddr) |
1408 | break; | |
1409 | } | |
1410 | ||
7fc11959 CK |
1411 | if (&mapping->list == &bo_va->valids) { |
1412 | valid = false; | |
1413 | ||
1414 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1415 | if (mapping->it.start == saddr) | |
1416 | break; | |
1417 | } | |
1418 | ||
32b41ac2 | 1419 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1420 | return -ENOENT; |
d38ceaf9 | 1421 | } |
32b41ac2 | 1422 | |
d38ceaf9 AD |
1423 | list_del(&mapping->list); |
1424 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1425 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1426 | |
e17841b9 | 1427 | if (valid) |
d38ceaf9 | 1428 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1429 | else |
d38ceaf9 | 1430 | kfree(mapping); |
d38ceaf9 AD |
1431 | |
1432 | return 0; | |
1433 | } | |
1434 | ||
1435 | /** | |
1436 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1437 | * | |
1438 | * @adev: amdgpu_device pointer | |
1439 | * @bo_va: requested bo_va | |
1440 | * | |
8843dbbb | 1441 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1442 | * |
1443 | * Object have to be reserved! | |
1444 | */ | |
1445 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1446 | struct amdgpu_bo_va *bo_va) | |
1447 | { | |
1448 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1449 | struct amdgpu_vm *vm = bo_va->vm; | |
1450 | ||
1451 | list_del(&bo_va->bo_list); | |
1452 | ||
d38ceaf9 AD |
1453 | spin_lock(&vm->status_lock); |
1454 | list_del(&bo_va->vm_status); | |
1455 | spin_unlock(&vm->status_lock); | |
1456 | ||
7fc11959 | 1457 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1458 | list_del(&mapping->list); |
1459 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1460 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1461 | list_add(&mapping->list, &vm->freed); |
1462 | } | |
1463 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1464 | list_del(&mapping->list); | |
1465 | interval_tree_remove(&mapping->it, &vm->va); | |
1466 | kfree(mapping); | |
d38ceaf9 | 1467 | } |
32b41ac2 | 1468 | |
bb1e38a4 | 1469 | fence_put(bo_va->last_pt_update); |
d38ceaf9 | 1470 | kfree(bo_va); |
d38ceaf9 AD |
1471 | } |
1472 | ||
1473 | /** | |
1474 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1475 | * | |
1476 | * @adev: amdgpu_device pointer | |
1477 | * @vm: requested vm | |
1478 | * @bo: amdgpu buffer object | |
1479 | * | |
8843dbbb | 1480 | * Mark @bo as invalid. |
d38ceaf9 AD |
1481 | */ |
1482 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1483 | struct amdgpu_bo *bo) | |
1484 | { | |
1485 | struct amdgpu_bo_va *bo_va; | |
1486 | ||
1487 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1488 | spin_lock(&bo_va->vm->status_lock); |
1489 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1490 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1491 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1492 | } |
1493 | } | |
1494 | ||
1495 | /** | |
1496 | * amdgpu_vm_init - initialize a vm instance | |
1497 | * | |
1498 | * @adev: amdgpu_device pointer | |
1499 | * @vm: requested vm | |
1500 | * | |
8843dbbb | 1501 | * Init @vm fields. |
d38ceaf9 AD |
1502 | */ |
1503 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1504 | { | |
1505 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1506 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1507 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1508 | unsigned ring_instance; |
1509 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1510 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1511 | int i, r; |
1512 | ||
bcb1ba35 CK |
1513 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1514 | vm->ids[i] = NULL; | |
d38ceaf9 | 1515 | vm->va = RB_ROOT; |
031e2983 | 1516 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
d38ceaf9 AD |
1517 | spin_lock_init(&vm->status_lock); |
1518 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1519 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1520 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 1521 | |
d38ceaf9 AD |
1522 | pd_size = amdgpu_vm_directory_size(adev); |
1523 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1524 | ||
1525 | /* allocate page table array */ | |
9571e1d8 | 1526 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1527 | if (vm->page_tables == NULL) { |
1528 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1529 | return -ENOMEM; | |
1530 | } | |
1531 | ||
2bd9ccfa | 1532 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1533 | |
1534 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1535 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1536 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1537 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1538 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1539 | rq, amdgpu_sched_jobs); | |
1540 | if (r) | |
1541 | return r; | |
1542 | ||
05906dec BN |
1543 | vm->page_directory_fence = NULL; |
1544 | ||
d38ceaf9 | 1545 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d | 1546 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f CZ |
1547 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
1548 | AMDGPU_GEM_CREATE_SHADOW, | |
72d7668b | 1549 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1550 | if (r) |
2bd9ccfa CK |
1551 | goto error_free_sched_entity; |
1552 | ||
ef9f0a83 | 1553 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1554 | if (r) |
1555 | goto error_free_page_directory; | |
1556 | ||
1557 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
ef9f0a83 | 1558 | amdgpu_bo_unreserve(vm->page_directory); |
2bd9ccfa CK |
1559 | if (r) |
1560 | goto error_free_page_directory; | |
5a712a87 | 1561 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
d38ceaf9 AD |
1562 | |
1563 | return 0; | |
2bd9ccfa CK |
1564 | |
1565 | error_free_page_directory: | |
1566 | amdgpu_bo_unref(&vm->page_directory); | |
1567 | vm->page_directory = NULL; | |
1568 | ||
1569 | error_free_sched_entity: | |
1570 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1571 | ||
1572 | return r; | |
d38ceaf9 AD |
1573 | } |
1574 | ||
1575 | /** | |
1576 | * amdgpu_vm_fini - tear down a vm instance | |
1577 | * | |
1578 | * @adev: amdgpu_device pointer | |
1579 | * @vm: requested vm | |
1580 | * | |
8843dbbb | 1581 | * Tear down @vm. |
d38ceaf9 AD |
1582 | * Unbind the VM and remove all bos from the vm bo list |
1583 | */ | |
1584 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1585 | { | |
1586 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1587 | int i; | |
1588 | ||
2d55e45a | 1589 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1590 | |
d38ceaf9 AD |
1591 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1592 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1593 | } | |
1594 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1595 | list_del(&mapping->list); | |
1596 | interval_tree_remove(&mapping->it, &vm->va); | |
1597 | kfree(mapping); | |
1598 | } | |
1599 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1600 | list_del(&mapping->list); | |
1601 | kfree(mapping); | |
1602 | } | |
1603 | ||
1baa439f CZ |
1604 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) { |
1605 | if (vm->page_tables[i].entry.robj && | |
1606 | vm->page_tables[i].entry.robj->shadow) | |
1607 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj->shadow); | |
ee1782c3 | 1608 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
1baa439f | 1609 | } |
9571e1d8 | 1610 | drm_free_large(vm->page_tables); |
d38ceaf9 | 1611 | |
1baa439f CZ |
1612 | if (vm->page_directory->shadow) |
1613 | amdgpu_bo_unref(&vm->page_directory->shadow); | |
d38ceaf9 | 1614 | amdgpu_bo_unref(&vm->page_directory); |
05906dec | 1615 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1616 | } |
ea89f8c9 | 1617 | |
a9a78b32 CK |
1618 | /** |
1619 | * amdgpu_vm_manager_init - init the VM manager | |
1620 | * | |
1621 | * @adev: amdgpu_device pointer | |
1622 | * | |
1623 | * Initialize the VM manager structures | |
1624 | */ | |
1625 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1626 | { | |
1627 | unsigned i; | |
1628 | ||
1629 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1630 | ||
1631 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1632 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1633 | amdgpu_vm_reset_id(adev, i); | |
832a902f | 1634 | amdgpu_sync_create(&adev->vm_manager.ids[i].active); |
a9a78b32 CK |
1635 | list_add_tail(&adev->vm_manager.ids[i].list, |
1636 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1637 | } |
2d55e45a | 1638 | |
1fbb2e92 CK |
1639 | adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); |
1640 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | |
1641 | adev->vm_manager.seqno[i] = 0; | |
1642 | ||
2d55e45a | 1643 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 1644 | atomic64_set(&adev->vm_manager.client_counter, 0); |
a9a78b32 CK |
1645 | } |
1646 | ||
ea89f8c9 CK |
1647 | /** |
1648 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1649 | * | |
1650 | * @adev: amdgpu_device pointer | |
1651 | * | |
1652 | * Cleanup the VM manager and free resources. | |
1653 | */ | |
1654 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1655 | { | |
1656 | unsigned i; | |
1657 | ||
bcb1ba35 CK |
1658 | for (i = 0; i < AMDGPU_NUM_VM; ++i) { |
1659 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; | |
1660 | ||
832a902f CK |
1661 | fence_put(adev->vm_manager.ids[i].first); |
1662 | amdgpu_sync_free(&adev->vm_manager.ids[i].active); | |
bcb1ba35 CK |
1663 | fence_put(id->flushed_updates); |
1664 | } | |
ea89f8c9 | 1665 | } |