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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
1fbb2e92 | 28 | #include <linux/fence-array.h> |
d38ceaf9 AD |
29 | #include <drm/drmP.h> |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu.h" | |
32 | #include "amdgpu_trace.h" | |
33 | ||
34 | /* | |
35 | * GPUVM | |
36 | * GPUVM is similar to the legacy gart on older asics, however | |
37 | * rather than there being a single global gart table | |
38 | * for the entire GPU, there are multiple VM page tables active | |
39 | * at any given time. The VM page tables can contain a mix | |
40 | * vram pages and system memory pages and system memory pages | |
41 | * can be mapped as snooped (cached system pages) or unsnooped | |
42 | * (uncached system pages). | |
43 | * Each VM has an ID associated with it and there is a page table | |
44 | * associated with each VMID. When execting a command buffer, | |
45 | * the kernel tells the the ring what VMID to use for that command | |
46 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
47 | * The userspace drivers maintain their own address space and the kernel | |
48 | * sets up their pages tables accordingly when they submit their | |
49 | * command buffers and a VMID is assigned. | |
50 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
51 | * SI supports 16. | |
52 | */ | |
53 | ||
4ff37a83 CK |
54 | /* Special value that no flush is necessary */ |
55 | #define AMDGPU_VM_NO_FLUSH (~0ll) | |
56 | ||
f4833c4f HK |
57 | /* Local structure. Encapsulate some VM table update parameters to reduce |
58 | * the number of function parameters | |
59 | */ | |
29efc4f5 | 60 | struct amdgpu_pte_update_params { |
27c5f36f CK |
61 | /* amdgpu device we do this update for */ |
62 | struct amdgpu_device *adev; | |
f4833c4f HK |
63 | /* address where to copy page table entries from */ |
64 | uint64_t src; | |
f4833c4f HK |
65 | /* indirect buffer to fill with commands */ |
66 | struct amdgpu_ib *ib; | |
67 | }; | |
68 | ||
d38ceaf9 AD |
69 | /** |
70 | * amdgpu_vm_num_pde - return the number of page directory entries | |
71 | * | |
72 | * @adev: amdgpu_device pointer | |
73 | * | |
8843dbbb | 74 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
75 | */ |
76 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
77 | { | |
78 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
79 | } | |
80 | ||
81 | /** | |
82 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
83 | * | |
84 | * @adev: amdgpu_device pointer | |
85 | * | |
8843dbbb | 86 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
87 | */ |
88 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
89 | { | |
90 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
91 | } | |
92 | ||
93 | /** | |
56467ebf | 94 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
95 | * |
96 | * @vm: vm providing the BOs | |
3c0eea6c | 97 | * @validated: head of validation list |
56467ebf | 98 | * @entry: entry to add |
d38ceaf9 AD |
99 | * |
100 | * Add the page directory to the list of BOs to | |
56467ebf | 101 | * validate for command submission. |
d38ceaf9 | 102 | */ |
56467ebf CK |
103 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
104 | struct list_head *validated, | |
105 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 106 | { |
56467ebf | 107 | entry->robj = vm->page_directory; |
56467ebf CK |
108 | entry->priority = 0; |
109 | entry->tv.bo = &vm->page_directory->tbo; | |
110 | entry->tv.shared = true; | |
2f568dbd | 111 | entry->user_pages = NULL; |
56467ebf CK |
112 | list_add(&entry->tv.head, validated); |
113 | } | |
d38ceaf9 | 114 | |
56467ebf | 115 | /** |
ee1782c3 | 116 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf | 117 | * |
5a712a87 | 118 | * @adev: amdgpu device pointer |
56467ebf | 119 | * @vm: vm providing the BOs |
3c0eea6c | 120 | * @duplicates: head of duplicates list |
d38ceaf9 | 121 | * |
ee1782c3 CK |
122 | * Add the page directory to the BO duplicates list |
123 | * for command submission. | |
d38ceaf9 | 124 | */ |
5a712a87 CK |
125 | void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
126 | struct list_head *duplicates) | |
d38ceaf9 | 127 | { |
5a712a87 | 128 | uint64_t num_evictions; |
ee1782c3 | 129 | unsigned i; |
d38ceaf9 | 130 | |
5a712a87 CK |
131 | /* We only need to validate the page tables |
132 | * if they aren't already valid. | |
133 | */ | |
134 | num_evictions = atomic64_read(&adev->num_evictions); | |
135 | if (num_evictions == vm->last_eviction_counter) | |
136 | return; | |
137 | ||
d38ceaf9 | 138 | /* add the vm page table to the list */ |
ee1782c3 CK |
139 | for (i = 0; i <= vm->max_pde_used; ++i) { |
140 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
141 | ||
142 | if (!entry->robj) | |
d38ceaf9 AD |
143 | continue; |
144 | ||
ee1782c3 | 145 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 146 | } |
eceb8a15 CK |
147 | |
148 | } | |
149 | ||
150 | /** | |
151 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
152 | * | |
153 | * @adev: amdgpu device instance | |
154 | * @vm: vm providing the BOs | |
155 | * | |
156 | * Move the PT BOs to the tail of the LRU. | |
157 | */ | |
158 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
159 | struct amdgpu_vm *vm) | |
160 | { | |
161 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
162 | unsigned i; | |
163 | ||
164 | spin_lock(&glob->lru_lock); | |
165 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
166 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
167 | ||
168 | if (!entry->robj) | |
169 | continue; | |
170 | ||
171 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
172 | } | |
173 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
174 | } |
175 | ||
192b7dcb CZ |
176 | static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev, |
177 | struct amdgpu_vm_id *id) | |
178 | { | |
179 | return id->current_gpu_reset_count != | |
180 | atomic_read(&adev->gpu_reset_counter) ? true : false; | |
181 | } | |
182 | ||
d38ceaf9 AD |
183 | /** |
184 | * amdgpu_vm_grab_id - allocate the next free VMID | |
185 | * | |
d38ceaf9 | 186 | * @vm: vm to allocate id for |
7f8a5290 CK |
187 | * @ring: ring we want to submit job to |
188 | * @sync: sync object where we add dependencies | |
94dd0a4a | 189 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 190 | * |
7f8a5290 | 191 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 192 | */ |
7f8a5290 | 193 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 | 194 | struct amdgpu_sync *sync, struct fence *fence, |
fd53be30 | 195 | struct amdgpu_job *job) |
d38ceaf9 | 196 | { |
d38ceaf9 | 197 | struct amdgpu_device *adev = ring->adev; |
090b767e | 198 | uint64_t fence_context = adev->fence_context + ring->idx; |
4ff37a83 | 199 | struct fence *updates = sync->last_vm_update; |
8d76001e | 200 | struct amdgpu_vm_id *id, *idle; |
1fbb2e92 CK |
201 | struct fence **fences; |
202 | unsigned i; | |
203 | int r = 0; | |
204 | ||
205 | fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids, | |
206 | GFP_KERNEL); | |
207 | if (!fences) | |
208 | return -ENOMEM; | |
d38ceaf9 | 209 | |
94dd0a4a CK |
210 | mutex_lock(&adev->vm_manager.lock); |
211 | ||
36fd7c5c | 212 | /* Check if we have an idle VMID */ |
1fbb2e92 | 213 | i = 0; |
8d76001e | 214 | list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) { |
1fbb2e92 CK |
215 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
216 | if (!fences[i]) | |
36fd7c5c | 217 | break; |
1fbb2e92 | 218 | ++i; |
36fd7c5c CK |
219 | } |
220 | ||
1fbb2e92 | 221 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
8d76001e | 222 | if (&idle->list == &adev->vm_manager.ids_lru) { |
1fbb2e92 CK |
223 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
224 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
225 | struct fence_array *array; | |
226 | unsigned j; | |
227 | ||
228 | for (j = 0; j < i; ++j) | |
229 | fence_get(fences[j]); | |
230 | ||
231 | array = fence_array_create(i, fences, fence_context, | |
232 | seqno, true); | |
233 | if (!array) { | |
234 | for (j = 0; j < i; ++j) | |
235 | fence_put(fences[j]); | |
236 | kfree(fences); | |
237 | r = -ENOMEM; | |
238 | goto error; | |
239 | } | |
240 | ||
241 | ||
242 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
243 | fence_put(&array->base); | |
244 | if (r) | |
245 | goto error; | |
246 | ||
247 | mutex_unlock(&adev->vm_manager.lock); | |
248 | return 0; | |
249 | ||
250 | } | |
251 | kfree(fences); | |
252 | ||
fd53be30 | 253 | job->vm_needs_flush = true; |
1fbb2e92 CK |
254 | /* Check if we can use a VMID already assigned to this VM */ |
255 | i = ring->idx; | |
256 | do { | |
257 | struct fence *flushed; | |
258 | ||
259 | id = vm->ids[i++]; | |
260 | if (i == AMDGPU_MAX_RINGS) | |
261 | i = 0; | |
8d76001e | 262 | |
1fbb2e92 CK |
263 | /* Check all the prerequisites to using this VMID */ |
264 | if (!id) | |
265 | continue; | |
192b7dcb | 266 | if (amdgpu_vm_is_gpu_reset(adev, id)) |
6adb0513 | 267 | continue; |
1fbb2e92 CK |
268 | |
269 | if (atomic64_read(&id->owner) != vm->client_id) | |
270 | continue; | |
271 | ||
fd53be30 | 272 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
273 | continue; |
274 | ||
090b767e CK |
275 | if (!id->last_flush) |
276 | continue; | |
277 | ||
278 | if (id->last_flush->context != fence_context && | |
279 | !fence_is_signaled(id->last_flush)) | |
1fbb2e92 CK |
280 | continue; |
281 | ||
282 | flushed = id->flushed_updates; | |
283 | if (updates && | |
284 | (!flushed || fence_is_later(updates, flushed))) | |
285 | continue; | |
286 | ||
3dab83be CK |
287 | /* Good we can use this VMID. Remember this submission as |
288 | * user of the VMID. | |
289 | */ | |
1fbb2e92 CK |
290 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
291 | if (r) | |
292 | goto error; | |
8d76001e | 293 | |
6adb0513 | 294 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
1fbb2e92 CK |
295 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
296 | vm->ids[ring->idx] = id; | |
8d76001e | 297 | |
fd53be30 CZ |
298 | job->vm_id = id - adev->vm_manager.ids; |
299 | job->vm_needs_flush = false; | |
0c0fdf14 | 300 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
8d76001e | 301 | |
1fbb2e92 CK |
302 | mutex_unlock(&adev->vm_manager.lock); |
303 | return 0; | |
8d76001e | 304 | |
1fbb2e92 | 305 | } while (i != ring->idx); |
8d76001e | 306 | |
1fbb2e92 CK |
307 | /* Still no ID to use? Then use the idle one found earlier */ |
308 | id = idle; | |
8e9fbeb5 | 309 | |
1fbb2e92 CK |
310 | /* Remember this submission as user of the VMID */ |
311 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
312 | if (r) |
313 | goto error; | |
94dd0a4a | 314 | |
832a902f CK |
315 | fence_put(id->first); |
316 | id->first = fence_get(fence); | |
94dd0a4a | 317 | |
41d9eb2c CK |
318 | fence_put(id->last_flush); |
319 | id->last_flush = NULL; | |
320 | ||
832a902f CK |
321 | fence_put(id->flushed_updates); |
322 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 323 | |
fd53be30 | 324 | id->pd_gpu_addr = job->vm_pd_addr; |
b46b8a87 | 325 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
832a902f | 326 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
0ea54b9b | 327 | atomic64_set(&id->owner, vm->client_id); |
832a902f | 328 | vm->ids[ring->idx] = id; |
d38ceaf9 | 329 | |
fd53be30 | 330 | job->vm_id = id - adev->vm_manager.ids; |
0c0fdf14 | 331 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
832a902f CK |
332 | |
333 | error: | |
94dd0a4a | 334 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 335 | return r; |
d38ceaf9 AD |
336 | } |
337 | ||
93dcc37d AD |
338 | static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) |
339 | { | |
340 | struct amdgpu_device *adev = ring->adev; | |
341 | const struct amdgpu_ip_block_version *ip_block; | |
342 | ||
343 | if (ring->type != AMDGPU_RING_TYPE_COMPUTE) | |
344 | /* only compute rings */ | |
345 | return false; | |
346 | ||
347 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
348 | if (!ip_block) | |
349 | return false; | |
350 | ||
351 | if (ip_block->major <= 7) { | |
352 | /* gfx7 has no workaround */ | |
353 | return true; | |
354 | } else if (ip_block->major == 8) { | |
355 | if (adev->gfx.mec_fw_version >= 673) | |
356 | /* gfx8 is fixed in MEC firmware 673 */ | |
357 | return false; | |
358 | else | |
359 | return true; | |
360 | } | |
361 | return false; | |
362 | } | |
363 | ||
d38ceaf9 AD |
364 | /** |
365 | * amdgpu_vm_flush - hardware flush the vm | |
366 | * | |
367 | * @ring: ring to use for flush | |
cffadc83 | 368 | * @vm_id: vmid number to use |
4ff37a83 | 369 | * @pd_addr: address of the page directory |
d38ceaf9 | 370 | * |
4ff37a83 | 371 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 372 | */ |
fd53be30 | 373 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) |
d38ceaf9 | 374 | { |
971fe9a9 | 375 | struct amdgpu_device *adev = ring->adev; |
fd53be30 | 376 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id]; |
d564a06e | 377 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
378 | id->gds_base != job->gds_base || |
379 | id->gds_size != job->gds_size || | |
380 | id->gws_base != job->gws_base || | |
381 | id->gws_size != job->gws_size || | |
382 | id->oa_base != job->oa_base || | |
383 | id->oa_size != job->oa_size); | |
41d9eb2c | 384 | int r; |
d564a06e CK |
385 | |
386 | if (ring->funcs->emit_pipeline_sync && ( | |
fd53be30 | 387 | job->vm_needs_flush || gds_switch_needed || |
93dcc37d | 388 | amdgpu_vm_ring_has_compute_vm_bug(ring))) |
d564a06e | 389 | amdgpu_ring_emit_pipeline_sync(ring); |
971fe9a9 | 390 | |
aa1c8900 CZ |
391 | if (ring->funcs->emit_vm_flush && (job->vm_needs_flush || |
392 | amdgpu_vm_is_gpu_reset(adev, id))) { | |
41d9eb2c CK |
393 | struct fence *fence; |
394 | ||
fd53be30 CZ |
395 | trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id); |
396 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
41d9eb2c | 397 | |
3dab83be CK |
398 | r = amdgpu_fence_emit(ring, &fence); |
399 | if (r) | |
400 | return r; | |
401 | ||
41d9eb2c | 402 | mutex_lock(&adev->vm_manager.lock); |
3dab83be CK |
403 | fence_put(id->last_flush); |
404 | id->last_flush = fence; | |
41d9eb2c | 405 | mutex_unlock(&adev->vm_manager.lock); |
d38ceaf9 | 406 | } |
cffadc83 | 407 | |
d564a06e | 408 | if (gds_switch_needed) { |
fd53be30 CZ |
409 | id->gds_base = job->gds_base; |
410 | id->gds_size = job->gds_size; | |
411 | id->gws_base = job->gws_base; | |
412 | id->gws_size = job->gws_size; | |
413 | id->oa_base = job->oa_base; | |
414 | id->oa_size = job->oa_size; | |
415 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, | |
416 | job->gds_base, job->gds_size, | |
417 | job->gws_base, job->gws_size, | |
418 | job->oa_base, job->oa_size); | |
971fe9a9 | 419 | } |
41d9eb2c CK |
420 | |
421 | return 0; | |
971fe9a9 CK |
422 | } |
423 | ||
424 | /** | |
425 | * amdgpu_vm_reset_id - reset VMID to zero | |
426 | * | |
427 | * @adev: amdgpu device structure | |
428 | * @vm_id: vmid number to use | |
429 | * | |
430 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
431 | */ | |
432 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
433 | { | |
bcb1ba35 CK |
434 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
435 | ||
436 | id->gds_base = 0; | |
437 | id->gds_size = 0; | |
438 | id->gws_base = 0; | |
439 | id->gws_size = 0; | |
440 | id->oa_base = 0; | |
441 | id->oa_size = 0; | |
d38ceaf9 AD |
442 | } |
443 | ||
d38ceaf9 AD |
444 | /** |
445 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
446 | * | |
447 | * @vm: requested vm | |
448 | * @bo: requested buffer object | |
449 | * | |
8843dbbb | 450 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
451 | * Search inside the @bos vm list for the requested vm |
452 | * Returns the found bo_va or NULL if none is found | |
453 | * | |
454 | * Object has to be reserved! | |
455 | */ | |
456 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
457 | struct amdgpu_bo *bo) | |
458 | { | |
459 | struct amdgpu_bo_va *bo_va; | |
460 | ||
461 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
462 | if (bo_va->vm == vm) { | |
463 | return bo_va; | |
464 | } | |
465 | } | |
466 | return NULL; | |
467 | } | |
468 | ||
469 | /** | |
470 | * amdgpu_vm_update_pages - helper to call the right asic function | |
471 | * | |
29efc4f5 | 472 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
473 | * @pe: addr of the page entry |
474 | * @addr: dst addr to write into pe | |
475 | * @count: number of page entries to update | |
476 | * @incr: increase next addr by incr bytes | |
477 | * @flags: hw access flags | |
d38ceaf9 AD |
478 | * |
479 | * Traces the parameters and calls the right asic functions | |
480 | * to setup the page table using the DMA. | |
481 | */ | |
27c5f36f | 482 | static void amdgpu_vm_update_pages(struct amdgpu_pte_update_params *params, |
d38ceaf9 AD |
483 | uint64_t pe, uint64_t addr, |
484 | unsigned count, uint32_t incr, | |
9ab21462 | 485 | uint32_t flags) |
d38ceaf9 AD |
486 | { |
487 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
488 | ||
29efc4f5 | 489 | if (params->src) { |
27c5f36f | 490 | amdgpu_vm_copy_pte(params->adev, params->ib, |
29efc4f5 | 491 | pe, (params->src + (addr >> 12) * 8), count); |
d38ceaf9 | 492 | |
b07c9d2a | 493 | } else if (count < 3) { |
27c5f36f | 494 | amdgpu_vm_write_pte(params->adev, params->ib, NULL, pe, addr, |
b07c9d2a | 495 | count, incr, flags); |
d38ceaf9 AD |
496 | |
497 | } else { | |
27c5f36f | 498 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
499 | count, incr, flags); |
500 | } | |
501 | } | |
502 | ||
503 | /** | |
504 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
505 | * | |
506 | * @adev: amdgpu_device pointer | |
507 | * @bo: bo to clear | |
ef9f0a83 CZ |
508 | * |
509 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
510 | */ |
511 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 512 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
513 | struct amdgpu_bo *bo) |
514 | { | |
2d55e45a | 515 | struct amdgpu_ring *ring; |
4af9f07c | 516 | struct fence *fence = NULL; |
d71518b5 | 517 | struct amdgpu_job *job; |
29efc4f5 | 518 | struct amdgpu_pte_update_params params; |
d38ceaf9 AD |
519 | unsigned entries; |
520 | uint64_t addr; | |
521 | int r; | |
522 | ||
2d55e45a CK |
523 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
524 | ||
ca952613 | 525 | r = reservation_object_reserve_shared(bo->tbo.resv); |
526 | if (r) | |
527 | return r; | |
528 | ||
d38ceaf9 AD |
529 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
530 | if (r) | |
ef9f0a83 | 531 | goto error; |
d38ceaf9 AD |
532 | |
533 | addr = amdgpu_bo_gpu_offset(bo); | |
534 | entries = amdgpu_bo_size(bo) / 8; | |
535 | ||
d71518b5 CK |
536 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
537 | if (r) | |
ef9f0a83 | 538 | goto error; |
d38ceaf9 | 539 | |
27c5f36f CK |
540 | memset(¶ms, 0, sizeof(params)); |
541 | params.adev = adev; | |
29efc4f5 | 542 | params.ib = &job->ibs[0]; |
27c5f36f | 543 | amdgpu_vm_update_pages(¶ms, addr, 0, entries, 0, 0); |
d71518b5 CK |
544 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
545 | ||
546 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
547 | r = amdgpu_job_submit(job, ring, &vm->entity, |
548 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
549 | if (r) |
550 | goto error_free; | |
551 | ||
d71518b5 | 552 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 553 | fence_put(fence); |
cadf97b1 | 554 | return 0; |
ef9f0a83 | 555 | |
d38ceaf9 | 556 | error_free: |
d71518b5 | 557 | amdgpu_job_free(job); |
d38ceaf9 | 558 | |
ef9f0a83 | 559 | error: |
d38ceaf9 AD |
560 | return r; |
561 | } | |
562 | ||
563 | /** | |
b07c9d2a | 564 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 565 | * |
b07c9d2a | 566 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
567 | * @addr: the unmapped addr |
568 | * | |
569 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 570 | * to and return the pointer for the page table entry. |
d38ceaf9 | 571 | */ |
b07c9d2a | 572 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
573 | { |
574 | uint64_t result; | |
575 | ||
b07c9d2a CK |
576 | if (pages_addr) { |
577 | /* page table offset */ | |
578 | result = pages_addr[addr >> PAGE_SHIFT]; | |
579 | ||
580 | /* in case cpu page size != gpu page size*/ | |
581 | result |= addr & (~PAGE_MASK); | |
582 | ||
583 | } else { | |
584 | /* No mapping required */ | |
585 | result = addr; | |
586 | } | |
d38ceaf9 | 587 | |
b07c9d2a | 588 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
589 | |
590 | return result; | |
591 | } | |
592 | ||
593 | /** | |
594 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
595 | * | |
596 | * @adev: amdgpu_device pointer | |
597 | * @vm: requested vm | |
598 | * @start: start of GPU address range | |
599 | * @end: end of GPU address range | |
600 | * | |
601 | * Allocates new page tables if necessary | |
8843dbbb | 602 | * and updates the page directory. |
d38ceaf9 | 603 | * Returns 0 for success, error for failure. |
d38ceaf9 AD |
604 | */ |
605 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
606 | struct amdgpu_vm *vm) | |
607 | { | |
2d55e45a | 608 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
609 | struct amdgpu_bo *pd = vm->page_directory; |
610 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
611 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
612 | uint64_t last_pde = ~0, last_pt = ~0; | |
613 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 614 | struct amdgpu_job *job; |
29efc4f5 | 615 | struct amdgpu_pte_update_params params; |
4af9f07c | 616 | struct fence *fence = NULL; |
d5fc5e82 | 617 | |
d38ceaf9 AD |
618 | int r; |
619 | ||
2d55e45a CK |
620 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
621 | ||
d38ceaf9 AD |
622 | /* padding, etc. */ |
623 | ndw = 64; | |
624 | ||
625 | /* assume the worst case */ | |
626 | ndw += vm->max_pde_used * 6; | |
627 | ||
d71518b5 CK |
628 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
629 | if (r) | |
d38ceaf9 | 630 | return r; |
d71518b5 | 631 | |
27c5f36f CK |
632 | memset(¶ms, 0, sizeof(params)); |
633 | params.adev = adev; | |
29efc4f5 | 634 | params.ib = &job->ibs[0]; |
d38ceaf9 AD |
635 | |
636 | /* walk over the address space and update the page directory */ | |
637 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 638 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
639 | uint64_t pde, pt; |
640 | ||
641 | if (bo == NULL) | |
642 | continue; | |
643 | ||
644 | pt = amdgpu_bo_gpu_offset(bo); | |
645 | if (vm->page_tables[pt_idx].addr == pt) | |
646 | continue; | |
647 | vm->page_tables[pt_idx].addr = pt; | |
648 | ||
649 | pde = pd_addr + pt_idx * 8; | |
650 | if (((last_pde + 8 * count) != pde) || | |
651 | ((last_pt + incr * count) != pt)) { | |
652 | ||
653 | if (count) { | |
27c5f36f CK |
654 | amdgpu_vm_update_pages(¶ms, last_pde, |
655 | last_pt, count, incr, | |
9ab21462 | 656 | AMDGPU_PTE_VALID); |
d38ceaf9 AD |
657 | } |
658 | ||
659 | count = 1; | |
660 | last_pde = pde; | |
661 | last_pt = pt; | |
662 | } else { | |
663 | ++count; | |
664 | } | |
665 | } | |
666 | ||
667 | if (count) | |
27c5f36f | 668 | amdgpu_vm_update_pages(¶ms, last_pde, last_pt, |
f4833c4f | 669 | count, incr, AMDGPU_PTE_VALID); |
d38ceaf9 | 670 | |
29efc4f5 CK |
671 | if (params.ib->length_dw != 0) { |
672 | amdgpu_ring_pad_ib(ring, params.ib); | |
e86f9cee CK |
673 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
674 | AMDGPU_FENCE_OWNER_VM); | |
29efc4f5 | 675 | WARN_ON(params.ib->length_dw > ndw); |
2bd9ccfa CK |
676 | r = amdgpu_job_submit(job, ring, &vm->entity, |
677 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
678 | if (r) |
679 | goto error_free; | |
05906dec | 680 | |
4af9f07c | 681 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
682 | fence_put(vm->page_directory_fence); |
683 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 684 | fence_put(fence); |
d5fc5e82 | 685 | |
d71518b5 CK |
686 | } else { |
687 | amdgpu_job_free(job); | |
d5fc5e82 | 688 | } |
d38ceaf9 AD |
689 | |
690 | return 0; | |
d5fc5e82 CZ |
691 | |
692 | error_free: | |
d71518b5 | 693 | amdgpu_job_free(job); |
4af9f07c | 694 | return r; |
d38ceaf9 AD |
695 | } |
696 | ||
d38ceaf9 AD |
697 | /** |
698 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
699 | * | |
29efc4f5 | 700 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
701 | * @vm: requested vm |
702 | * @start: start of GPU address range | |
703 | * @end: end of GPU address range | |
677131a1 | 704 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
705 | * @flags: mapping flags |
706 | * | |
8843dbbb | 707 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 708 | */ |
27c5f36f | 709 | static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 710 | struct amdgpu_vm *vm, |
a1e08d3b CK |
711 | uint64_t start, uint64_t end, |
712 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 713 | { |
31f6c1fe CK |
714 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
715 | ||
92696dd5 | 716 | uint64_t cur_pe_start, cur_nptes, cur_dst; |
677131a1 | 717 | uint64_t addr; /* next GPU address to be updated */ |
21718497 AX |
718 | uint64_t pt_idx; |
719 | struct amdgpu_bo *pt; | |
720 | unsigned nptes; /* next number of ptes to be updated */ | |
721 | uint64_t next_pe_start; | |
722 | ||
723 | /* initialize the variables */ | |
724 | addr = start; | |
725 | pt_idx = addr >> amdgpu_vm_block_size; | |
726 | pt = vm->page_tables[pt_idx].entry.robj; | |
727 | ||
728 | if ((addr & ~mask) == (end & ~mask)) | |
729 | nptes = end - addr; | |
730 | else | |
731 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
732 | ||
733 | cur_pe_start = amdgpu_bo_gpu_offset(pt); | |
734 | cur_pe_start += (addr & mask) * 8; | |
92696dd5 | 735 | cur_nptes = nptes; |
21718497 AX |
736 | cur_dst = dst; |
737 | ||
738 | /* for next ptb*/ | |
739 | addr += nptes; | |
740 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
d38ceaf9 AD |
741 | |
742 | /* walk over the address space and update the page tables */ | |
21718497 AX |
743 | while (addr < end) { |
744 | pt_idx = addr >> amdgpu_vm_block_size; | |
745 | pt = vm->page_tables[pt_idx].entry.robj; | |
d38ceaf9 AD |
746 | |
747 | if ((addr & ~mask) == (end & ~mask)) | |
748 | nptes = end - addr; | |
749 | else | |
750 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
751 | ||
677131a1 AX |
752 | next_pe_start = amdgpu_bo_gpu_offset(pt); |
753 | next_pe_start += (addr & mask) * 8; | |
d38ceaf9 | 754 | |
92696dd5 | 755 | if ((cur_pe_start + 8 * cur_nptes) == next_pe_start) { |
3a6f8e0c | 756 | /* The next ptb is consecutive to current ptb. |
92696dd5 | 757 | * Don't call amdgpu_vm_update_pages now. |
3a6f8e0c AX |
758 | * Will update two ptbs together in future. |
759 | */ | |
92696dd5 | 760 | cur_nptes += nptes; |
3a6f8e0c | 761 | } else { |
92696dd5 CK |
762 | amdgpu_vm_update_pages(params, cur_pe_start, cur_dst, |
763 | cur_nptes, AMDGPU_GPU_PAGE_SIZE, | |
764 | flags); | |
d38ceaf9 | 765 | |
677131a1 | 766 | cur_pe_start = next_pe_start; |
92696dd5 | 767 | cur_nptes = nptes; |
677131a1 | 768 | cur_dst = dst; |
d38ceaf9 AD |
769 | } |
770 | ||
21718497 | 771 | /* for next ptb*/ |
d38ceaf9 AD |
772 | addr += nptes; |
773 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
774 | } | |
775 | ||
92696dd5 CK |
776 | amdgpu_vm_update_pages(params, cur_pe_start, cur_dst, cur_nptes, |
777 | AMDGPU_GPU_PAGE_SIZE, flags); | |
778 | } | |
779 | ||
780 | /* | |
781 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
782 | * | |
783 | * @params: see amdgpu_pte_update_params definition | |
784 | * @vm: requested vm | |
785 | * @start: first PTE to handle | |
786 | * @end: last PTE to handle | |
787 | * @dst: addr those PTEs should point to | |
788 | * @flags: hw mapping flags | |
789 | */ | |
790 | static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, | |
791 | struct amdgpu_vm *vm, | |
792 | uint64_t start, uint64_t end, | |
793 | uint64_t dst, uint32_t flags) | |
794 | { | |
795 | /** | |
796 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
797 | * field in the PTE. When this field is set to a non-zero value, page | |
798 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
799 | * flags are considered valid for all PTEs within the fragment range | |
800 | * and corresponding mappings are assumed to be physically contiguous. | |
801 | * | |
802 | * The L1 TLB can store a single PTE for the whole fragment, | |
803 | * significantly increasing the space available for translation | |
804 | * caching. This leads to large improvements in throughput when the | |
805 | * TLB is under pressure. | |
806 | * | |
807 | * The L2 TLB distributes small and large fragments into two | |
808 | * asymmetric partitions. The large fragment cache is significantly | |
809 | * larger. Thus, we try to use large fragments wherever possible. | |
810 | * Userspace can support this by aligning virtual base address and | |
811 | * allocation size to the fragment size. | |
812 | */ | |
813 | ||
e2b84e4b | 814 | const uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG; |
92696dd5 CK |
815 | |
816 | uint64_t frag_start = ALIGN(start, frag_align); | |
817 | uint64_t frag_end = end & ~(frag_align - 1); | |
818 | ||
e2b84e4b CK |
819 | uint32_t frag; |
820 | ||
92696dd5 | 821 | /* system pages are non continuously */ |
b7fc2cbd | 822 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
92696dd5 CK |
823 | (frag_start >= frag_end)) { |
824 | ||
825 | amdgpu_vm_update_ptes(params, vm, start, end, dst, flags); | |
826 | return; | |
827 | } | |
828 | ||
e2b84e4b CK |
829 | /* use more than 64KB fragment size if possible */ |
830 | frag = lower_32_bits(frag_start | frag_end); | |
831 | frag = likely(frag) ? __ffs(frag) : 31; | |
832 | ||
92696dd5 CK |
833 | /* handle the 4K area at the beginning */ |
834 | if (start != frag_start) { | |
835 | amdgpu_vm_update_ptes(params, vm, start, frag_start, | |
836 | dst, flags); | |
837 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; | |
838 | } | |
839 | ||
840 | /* handle the area in the middle */ | |
841 | amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst, | |
e2b84e4b | 842 | flags | AMDGPU_PTE_FRAG(frag)); |
92696dd5 CK |
843 | |
844 | /* handle the 4K area at the end */ | |
845 | if (frag_end != end) { | |
846 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
847 | amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags); | |
848 | } | |
d38ceaf9 AD |
849 | } |
850 | ||
d38ceaf9 AD |
851 | /** |
852 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
853 | * | |
854 | * @adev: amdgpu_device pointer | |
3cabaa54 | 855 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
856 | * @src: address where to copy page table entries from |
857 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 858 | * @vm: requested vm |
a14faa65 CK |
859 | * @start: start of mapped range |
860 | * @last: last mapped entry | |
861 | * @flags: flags for the entries | |
d38ceaf9 | 862 | * @addr: addr to set the area to |
d38ceaf9 AD |
863 | * @fence: optional resulting fence |
864 | * | |
a14faa65 | 865 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 866 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
867 | */ |
868 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
3cabaa54 | 869 | struct fence *exclusive, |
fa3ab3c7 CK |
870 | uint64_t src, |
871 | dma_addr_t *pages_addr, | |
d38ceaf9 | 872 | struct amdgpu_vm *vm, |
a14faa65 CK |
873 | uint64_t start, uint64_t last, |
874 | uint32_t flags, uint64_t addr, | |
875 | struct fence **fence) | |
d38ceaf9 | 876 | { |
2d55e45a | 877 | struct amdgpu_ring *ring; |
a1e08d3b | 878 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 879 | unsigned nptes, ncmds, ndw; |
d71518b5 | 880 | struct amdgpu_job *job; |
29efc4f5 | 881 | struct amdgpu_pte_update_params params; |
4af9f07c | 882 | struct fence *f = NULL; |
d38ceaf9 AD |
883 | int r; |
884 | ||
2d55e45a | 885 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 886 | |
29efc4f5 | 887 | memset(¶ms, 0, sizeof(params)); |
27c5f36f | 888 | params.adev = adev; |
29efc4f5 | 889 | params.src = src; |
2d55e45a | 890 | |
a1e08d3b CK |
891 | /* sync to everything on unmapping */ |
892 | if (!(flags & AMDGPU_PTE_VALID)) | |
893 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
894 | ||
a14faa65 | 895 | nptes = last - start + 1; |
d38ceaf9 AD |
896 | |
897 | /* | |
898 | * reserve space for one command every (1 << BLOCK_SIZE) | |
899 | * entries or 2k dwords (whatever is smaller) | |
900 | */ | |
901 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
902 | ||
903 | /* padding, etc. */ | |
904 | ndw = 64; | |
905 | ||
b0456f93 | 906 | if (src) { |
d38ceaf9 AD |
907 | /* only copy commands needed */ |
908 | ndw += ncmds * 7; | |
909 | ||
b0456f93 CK |
910 | } else if (pages_addr) { |
911 | /* copy commands needed */ | |
912 | ndw += ncmds * 7; | |
d38ceaf9 | 913 | |
b0456f93 | 914 | /* and also PTEs */ |
d38ceaf9 AD |
915 | ndw += nptes * 2; |
916 | ||
917 | } else { | |
918 | /* set page commands needed */ | |
919 | ndw += ncmds * 10; | |
920 | ||
921 | /* two extra commands for begin/end of fragment */ | |
922 | ndw += 2 * 10; | |
923 | } | |
924 | ||
d71518b5 CK |
925 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
926 | if (r) | |
d38ceaf9 | 927 | return r; |
d71518b5 | 928 | |
29efc4f5 | 929 | params.ib = &job->ibs[0]; |
d5fc5e82 | 930 | |
b0456f93 CK |
931 | if (!src && pages_addr) { |
932 | uint64_t *pte; | |
933 | unsigned i; | |
934 | ||
935 | /* Put the PTEs at the end of the IB. */ | |
936 | i = ndw - nptes * 2; | |
937 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
938 | params.src = job->ibs->gpu_addr + i * 4; | |
939 | ||
940 | for (i = 0; i < nptes; ++i) { | |
941 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
942 | AMDGPU_GPU_PAGE_SIZE); | |
943 | pte[i] |= flags; | |
944 | } | |
945 | } | |
946 | ||
3cabaa54 CK |
947 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
948 | if (r) | |
949 | goto error_free; | |
950 | ||
e86f9cee | 951 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
952 | owner); |
953 | if (r) | |
954 | goto error_free; | |
d38ceaf9 | 955 | |
a1e08d3b CK |
956 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
957 | if (r) | |
958 | goto error_free; | |
959 | ||
92696dd5 | 960 | amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags); |
d38ceaf9 | 961 | |
29efc4f5 CK |
962 | amdgpu_ring_pad_ib(ring, params.ib); |
963 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
964 | r = amdgpu_job_submit(job, ring, &vm->entity, |
965 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
966 | if (r) |
967 | goto error_free; | |
d38ceaf9 | 968 | |
bf60efd3 | 969 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
970 | if (fence) { |
971 | fence_put(*fence); | |
972 | *fence = fence_get(f); | |
973 | } | |
281b4223 | 974 | fence_put(f); |
d38ceaf9 | 975 | return 0; |
d5fc5e82 CZ |
976 | |
977 | error_free: | |
d71518b5 | 978 | amdgpu_job_free(job); |
4af9f07c | 979 | return r; |
d38ceaf9 AD |
980 | } |
981 | ||
a14faa65 CK |
982 | /** |
983 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
984 | * | |
985 | * @adev: amdgpu_device pointer | |
3cabaa54 | 986 | * @exclusive: fence we need to sync to |
8358dcee CK |
987 | * @gtt_flags: flags as they are used for GTT |
988 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
989 | * @vm: requested vm |
990 | * @mapping: mapped range and flags to use for the update | |
991 | * @addr: addr to set the area to | |
8358dcee | 992 | * @flags: HW flags for the mapping |
a14faa65 CK |
993 | * @fence: optional resulting fence |
994 | * | |
995 | * Split the mapping into smaller chunks so that each update fits | |
996 | * into a SDMA IB. | |
997 | * Returns 0 for success, -EINVAL for failure. | |
998 | */ | |
999 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
3cabaa54 | 1000 | struct fence *exclusive, |
a14faa65 | 1001 | uint32_t gtt_flags, |
8358dcee | 1002 | dma_addr_t *pages_addr, |
a14faa65 CK |
1003 | struct amdgpu_vm *vm, |
1004 | struct amdgpu_bo_va_mapping *mapping, | |
fa3ab3c7 CK |
1005 | uint32_t flags, uint64_t addr, |
1006 | struct fence **fence) | |
a14faa65 CK |
1007 | { |
1008 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
1009 | ||
fa3ab3c7 | 1010 | uint64_t src = 0, start = mapping->it.start; |
a14faa65 CK |
1011 | int r; |
1012 | ||
1013 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1014 | * but in case of something, we filter the flags in first place | |
1015 | */ | |
1016 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1017 | flags &= ~AMDGPU_PTE_READABLE; | |
1018 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1019 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1020 | ||
1021 | trace_amdgpu_vm_bo_update(mapping); | |
1022 | ||
8358dcee | 1023 | if (pages_addr) { |
fa3ab3c7 CK |
1024 | if (flags == gtt_flags) |
1025 | src = adev->gart.table_addr + (addr >> 12) * 8; | |
fa3ab3c7 CK |
1026 | addr = 0; |
1027 | } | |
a14faa65 CK |
1028 | addr += mapping->offset; |
1029 | ||
8358dcee | 1030 | if (!pages_addr || src) |
3cabaa54 CK |
1031 | return amdgpu_vm_bo_update_mapping(adev, exclusive, |
1032 | src, pages_addr, vm, | |
a14faa65 CK |
1033 | start, mapping->it.last, |
1034 | flags, addr, fence); | |
1035 | ||
1036 | while (start != mapping->it.last + 1) { | |
1037 | uint64_t last; | |
1038 | ||
fb29b57c | 1039 | last = min((uint64_t)mapping->it.last, start + max_size - 1); |
3cabaa54 CK |
1040 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1041 | src, pages_addr, vm, | |
a14faa65 CK |
1042 | start, last, flags, addr, |
1043 | fence); | |
1044 | if (r) | |
1045 | return r; | |
1046 | ||
1047 | start = last + 1; | |
fb29b57c | 1048 | addr += max_size * AMDGPU_GPU_PAGE_SIZE; |
a14faa65 CK |
1049 | } |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | ||
d38ceaf9 AD |
1054 | /** |
1055 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1056 | * | |
1057 | * @adev: amdgpu_device pointer | |
1058 | * @bo_va: requested BO and VM object | |
1059 | * @mem: ttm mem | |
1060 | * | |
1061 | * Fill in the page table entries for @bo_va. | |
1062 | * Returns 0 for success, -EINVAL for failure. | |
1063 | * | |
1064 | * Object have to be reserved and mutex must be locked! | |
1065 | */ | |
1066 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1067 | struct amdgpu_bo_va *bo_va, | |
1068 | struct ttm_mem_reg *mem) | |
1069 | { | |
1070 | struct amdgpu_vm *vm = bo_va->vm; | |
1071 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1072 | dma_addr_t *pages_addr = NULL; |
fa3ab3c7 | 1073 | uint32_t gtt_flags, flags; |
3cabaa54 | 1074 | struct fence *exclusive; |
d38ceaf9 AD |
1075 | uint64_t addr; |
1076 | int r; | |
1077 | ||
1078 | if (mem) { | |
8358dcee CK |
1079 | struct ttm_dma_tt *ttm; |
1080 | ||
b7d698d7 | 1081 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
1082 | switch (mem->mem_type) { |
1083 | case TTM_PL_TT: | |
8358dcee CK |
1084 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1085 | ttm_dma_tt, ttm); | |
1086 | pages_addr = ttm->dma_address; | |
9ab21462 CK |
1087 | break; |
1088 | ||
1089 | case TTM_PL_VRAM: | |
d38ceaf9 | 1090 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
1091 | break; |
1092 | ||
1093 | default: | |
1094 | break; | |
1095 | } | |
3cabaa54 CK |
1096 | |
1097 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); | |
d38ceaf9 AD |
1098 | } else { |
1099 | addr = 0; | |
3cabaa54 | 1100 | exclusive = NULL; |
d38ceaf9 AD |
1101 | } |
1102 | ||
d38ceaf9 | 1103 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
fa3ab3c7 | 1104 | gtt_flags = (adev == bo_va->bo->adev) ? flags : 0; |
d38ceaf9 | 1105 | |
7fc11959 CK |
1106 | spin_lock(&vm->status_lock); |
1107 | if (!list_empty(&bo_va->vm_status)) | |
1108 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1109 | spin_unlock(&vm->status_lock); | |
1110 | ||
1111 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1112 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1113 | gtt_flags, pages_addr, vm, | |
8358dcee CK |
1114 | mapping, flags, addr, |
1115 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
1116 | if (r) |
1117 | return r; | |
1118 | } | |
1119 | ||
d6c10f6b CK |
1120 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1121 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1122 | trace_amdgpu_vm_bo_mapping(mapping); | |
1123 | ||
1124 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1125 | trace_amdgpu_vm_bo_mapping(mapping); | |
1126 | } | |
1127 | ||
d38ceaf9 | 1128 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1129 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1130 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
1131 | if (!mem) |
1132 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
1133 | spin_unlock(&vm->status_lock); |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | /** | |
1139 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1140 | * | |
1141 | * @adev: amdgpu_device pointer | |
1142 | * @vm: requested vm | |
1143 | * | |
1144 | * Make sure all freed BOs are cleared in the PT. | |
1145 | * Returns 0 for success. | |
1146 | * | |
1147 | * PTs have to be reserved and mutex must be locked! | |
1148 | */ | |
1149 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
1150 | struct amdgpu_vm *vm) | |
1151 | { | |
1152 | struct amdgpu_bo_va_mapping *mapping; | |
1153 | int r; | |
1154 | ||
1155 | while (!list_empty(&vm->freed)) { | |
1156 | mapping = list_first_entry(&vm->freed, | |
1157 | struct amdgpu_bo_va_mapping, list); | |
1158 | list_del(&mapping->list); | |
e17841b9 | 1159 | |
3cabaa54 | 1160 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping, |
fa3ab3c7 | 1161 | 0, 0, NULL); |
d38ceaf9 AD |
1162 | kfree(mapping); |
1163 | if (r) | |
1164 | return r; | |
1165 | ||
1166 | } | |
1167 | return 0; | |
1168 | ||
1169 | } | |
1170 | ||
1171 | /** | |
1172 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1173 | * | |
1174 | * @adev: amdgpu_device pointer | |
1175 | * @vm: requested vm | |
1176 | * | |
1177 | * Make sure all invalidated BOs are cleared in the PT. | |
1178 | * Returns 0 for success. | |
1179 | * | |
1180 | * PTs have to be reserved and mutex must be locked! | |
1181 | */ | |
1182 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1183 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1184 | { |
cfe2c978 | 1185 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1186 | int r = 0; |
d38ceaf9 AD |
1187 | |
1188 | spin_lock(&vm->status_lock); | |
1189 | while (!list_empty(&vm->invalidated)) { | |
1190 | bo_va = list_first_entry(&vm->invalidated, | |
1191 | struct amdgpu_bo_va, vm_status); | |
1192 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1193 | |
d38ceaf9 AD |
1194 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
1195 | if (r) | |
1196 | return r; | |
1197 | ||
1198 | spin_lock(&vm->status_lock); | |
1199 | } | |
1200 | spin_unlock(&vm->status_lock); | |
1201 | ||
cfe2c978 | 1202 | if (bo_va) |
bb1e38a4 | 1203 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1204 | |
1205 | return r; | |
d38ceaf9 AD |
1206 | } |
1207 | ||
1208 | /** | |
1209 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1210 | * | |
1211 | * @adev: amdgpu_device pointer | |
1212 | * @vm: requested vm | |
1213 | * @bo: amdgpu buffer object | |
1214 | * | |
8843dbbb | 1215 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1216 | * Add @bo to the list of bos associated with the vm |
1217 | * Returns newly added bo_va or NULL for failure | |
1218 | * | |
1219 | * Object has to be reserved! | |
1220 | */ | |
1221 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1222 | struct amdgpu_vm *vm, | |
1223 | struct amdgpu_bo *bo) | |
1224 | { | |
1225 | struct amdgpu_bo_va *bo_va; | |
1226 | ||
1227 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1228 | if (bo_va == NULL) { | |
1229 | return NULL; | |
1230 | } | |
1231 | bo_va->vm = vm; | |
1232 | bo_va->bo = bo; | |
d38ceaf9 AD |
1233 | bo_va->ref_count = 1; |
1234 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1235 | INIT_LIST_HEAD(&bo_va->valids); |
1236 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1237 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1238 | |
d38ceaf9 | 1239 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1240 | |
1241 | return bo_va; | |
1242 | } | |
1243 | ||
1244 | /** | |
1245 | * amdgpu_vm_bo_map - map bo inside a vm | |
1246 | * | |
1247 | * @adev: amdgpu_device pointer | |
1248 | * @bo_va: bo_va to store the address | |
1249 | * @saddr: where to map the BO | |
1250 | * @offset: requested offset in the BO | |
1251 | * @flags: attributes of pages (read/write/valid/etc.) | |
1252 | * | |
1253 | * Add a mapping of the BO at the specefied addr into the VM. | |
1254 | * Returns 0 for success, error for failure. | |
1255 | * | |
49b02b18 | 1256 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1257 | */ |
1258 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1259 | struct amdgpu_bo_va *bo_va, | |
1260 | uint64_t saddr, uint64_t offset, | |
1261 | uint64_t size, uint32_t flags) | |
1262 | { | |
1263 | struct amdgpu_bo_va_mapping *mapping; | |
1264 | struct amdgpu_vm *vm = bo_va->vm; | |
1265 | struct interval_tree_node *it; | |
1266 | unsigned last_pfn, pt_idx; | |
1267 | uint64_t eaddr; | |
1268 | int r; | |
1269 | ||
0be52de9 CK |
1270 | /* validate the parameters */ |
1271 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1272 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1273 | return -EINVAL; |
0be52de9 | 1274 | |
d38ceaf9 | 1275 | /* make sure object fit at this offset */ |
005ae95e | 1276 | eaddr = saddr + size - 1; |
49b02b18 | 1277 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1278 | return -EINVAL; |
d38ceaf9 AD |
1279 | |
1280 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1281 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1282 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1283 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1284 | return -EINVAL; |
1285 | } | |
1286 | ||
d38ceaf9 AD |
1287 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1288 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1289 | ||
005ae95e | 1290 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
d38ceaf9 AD |
1291 | if (it) { |
1292 | struct amdgpu_bo_va_mapping *tmp; | |
1293 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1294 | /* bo and tmp overlap, invalid addr */ | |
1295 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1296 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1297 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1298 | r = -EINVAL; |
f48b2659 | 1299 | goto error; |
d38ceaf9 AD |
1300 | } |
1301 | ||
1302 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1303 | if (!mapping) { | |
d38ceaf9 | 1304 | r = -ENOMEM; |
f48b2659 | 1305 | goto error; |
d38ceaf9 AD |
1306 | } |
1307 | ||
1308 | INIT_LIST_HEAD(&mapping->list); | |
1309 | mapping->it.start = saddr; | |
005ae95e | 1310 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1311 | mapping->offset = offset; |
1312 | mapping->flags = flags; | |
1313 | ||
7fc11959 | 1314 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 AD |
1315 | interval_tree_insert(&mapping->it, &vm->va); |
1316 | ||
1317 | /* Make sure the page tables are allocated */ | |
1318 | saddr >>= amdgpu_vm_block_size; | |
1319 | eaddr >>= amdgpu_vm_block_size; | |
1320 | ||
1321 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1322 | ||
1323 | if (eaddr > vm->max_pde_used) | |
1324 | vm->max_pde_used = eaddr; | |
1325 | ||
d38ceaf9 AD |
1326 | /* walk over the address space and allocate the page tables */ |
1327 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1328 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1329 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1330 | struct amdgpu_bo *pt; |
1331 | ||
ee1782c3 CK |
1332 | entry = &vm->page_tables[pt_idx].entry; |
1333 | if (entry->robj) | |
d38ceaf9 AD |
1334 | continue; |
1335 | ||
d38ceaf9 AD |
1336 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1337 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d | 1338 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f CZ |
1339 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
1340 | AMDGPU_GEM_CREATE_SHADOW, | |
bf60efd3 | 1341 | NULL, resv, &pt); |
49b02b18 | 1342 | if (r) |
d38ceaf9 | 1343 | goto error_free; |
49b02b18 | 1344 | |
82b9c55b CK |
1345 | /* Keep a reference to the page table to avoid freeing |
1346 | * them up in the wrong order. | |
1347 | */ | |
1348 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1349 | ||
2bd9ccfa | 1350 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 AD |
1351 | if (r) { |
1352 | amdgpu_bo_unref(&pt); | |
1353 | goto error_free; | |
1354 | } | |
1355 | ||
ee1782c3 | 1356 | entry->robj = pt; |
ee1782c3 CK |
1357 | entry->priority = 0; |
1358 | entry->tv.bo = &entry->robj->tbo; | |
1359 | entry->tv.shared = true; | |
2f568dbd | 1360 | entry->user_pages = NULL; |
d38ceaf9 | 1361 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1362 | } |
1363 | ||
d38ceaf9 AD |
1364 | return 0; |
1365 | ||
1366 | error_free: | |
d38ceaf9 AD |
1367 | list_del(&mapping->list); |
1368 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1369 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1370 | kfree(mapping); |
1371 | ||
f48b2659 | 1372 | error: |
d38ceaf9 AD |
1373 | return r; |
1374 | } | |
1375 | ||
1376 | /** | |
1377 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1378 | * | |
1379 | * @adev: amdgpu_device pointer | |
1380 | * @bo_va: bo_va to remove the address from | |
1381 | * @saddr: where to the BO is mapped | |
1382 | * | |
1383 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1384 | * Returns 0 for success, error for failure. | |
1385 | * | |
49b02b18 | 1386 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1387 | */ |
1388 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1389 | struct amdgpu_bo_va *bo_va, | |
1390 | uint64_t saddr) | |
1391 | { | |
1392 | struct amdgpu_bo_va_mapping *mapping; | |
1393 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1394 | bool valid = true; |
d38ceaf9 | 1395 | |
6c7fc503 | 1396 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1397 | |
7fc11959 | 1398 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1399 | if (mapping->it.start == saddr) |
1400 | break; | |
1401 | } | |
1402 | ||
7fc11959 CK |
1403 | if (&mapping->list == &bo_va->valids) { |
1404 | valid = false; | |
1405 | ||
1406 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1407 | if (mapping->it.start == saddr) | |
1408 | break; | |
1409 | } | |
1410 | ||
32b41ac2 | 1411 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1412 | return -ENOENT; |
d38ceaf9 | 1413 | } |
32b41ac2 | 1414 | |
d38ceaf9 AD |
1415 | list_del(&mapping->list); |
1416 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1417 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1418 | |
e17841b9 | 1419 | if (valid) |
d38ceaf9 | 1420 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1421 | else |
d38ceaf9 | 1422 | kfree(mapping); |
d38ceaf9 AD |
1423 | |
1424 | return 0; | |
1425 | } | |
1426 | ||
1427 | /** | |
1428 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1429 | * | |
1430 | * @adev: amdgpu_device pointer | |
1431 | * @bo_va: requested bo_va | |
1432 | * | |
8843dbbb | 1433 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1434 | * |
1435 | * Object have to be reserved! | |
1436 | */ | |
1437 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1438 | struct amdgpu_bo_va *bo_va) | |
1439 | { | |
1440 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1441 | struct amdgpu_vm *vm = bo_va->vm; | |
1442 | ||
1443 | list_del(&bo_va->bo_list); | |
1444 | ||
d38ceaf9 AD |
1445 | spin_lock(&vm->status_lock); |
1446 | list_del(&bo_va->vm_status); | |
1447 | spin_unlock(&vm->status_lock); | |
1448 | ||
7fc11959 | 1449 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1450 | list_del(&mapping->list); |
1451 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1452 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1453 | list_add(&mapping->list, &vm->freed); |
1454 | } | |
1455 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1456 | list_del(&mapping->list); | |
1457 | interval_tree_remove(&mapping->it, &vm->va); | |
1458 | kfree(mapping); | |
d38ceaf9 | 1459 | } |
32b41ac2 | 1460 | |
bb1e38a4 | 1461 | fence_put(bo_va->last_pt_update); |
d38ceaf9 | 1462 | kfree(bo_va); |
d38ceaf9 AD |
1463 | } |
1464 | ||
1465 | /** | |
1466 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1467 | * | |
1468 | * @adev: amdgpu_device pointer | |
1469 | * @vm: requested vm | |
1470 | * @bo: amdgpu buffer object | |
1471 | * | |
8843dbbb | 1472 | * Mark @bo as invalid. |
d38ceaf9 AD |
1473 | */ |
1474 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1475 | struct amdgpu_bo *bo) | |
1476 | { | |
1477 | struct amdgpu_bo_va *bo_va; | |
1478 | ||
1479 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1480 | spin_lock(&bo_va->vm->status_lock); |
1481 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1482 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1483 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1484 | } |
1485 | } | |
1486 | ||
1487 | /** | |
1488 | * amdgpu_vm_init - initialize a vm instance | |
1489 | * | |
1490 | * @adev: amdgpu_device pointer | |
1491 | * @vm: requested vm | |
1492 | * | |
8843dbbb | 1493 | * Init @vm fields. |
d38ceaf9 AD |
1494 | */ |
1495 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1496 | { | |
1497 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1498 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1499 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1500 | unsigned ring_instance; |
1501 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1502 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1503 | int i, r; |
1504 | ||
bcb1ba35 CK |
1505 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1506 | vm->ids[i] = NULL; | |
d38ceaf9 | 1507 | vm->va = RB_ROOT; |
031e2983 | 1508 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
d38ceaf9 AD |
1509 | spin_lock_init(&vm->status_lock); |
1510 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1511 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1512 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 1513 | |
d38ceaf9 AD |
1514 | pd_size = amdgpu_vm_directory_size(adev); |
1515 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1516 | ||
1517 | /* allocate page table array */ | |
9571e1d8 | 1518 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1519 | if (vm->page_tables == NULL) { |
1520 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1521 | return -ENOMEM; | |
1522 | } | |
1523 | ||
2bd9ccfa | 1524 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1525 | |
1526 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1527 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1528 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1529 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1530 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1531 | rq, amdgpu_sched_jobs); | |
1532 | if (r) | |
1533 | return r; | |
1534 | ||
05906dec BN |
1535 | vm->page_directory_fence = NULL; |
1536 | ||
d38ceaf9 | 1537 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d | 1538 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f CZ |
1539 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
1540 | AMDGPU_GEM_CREATE_SHADOW, | |
72d7668b | 1541 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1542 | if (r) |
2bd9ccfa CK |
1543 | goto error_free_sched_entity; |
1544 | ||
ef9f0a83 | 1545 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1546 | if (r) |
1547 | goto error_free_page_directory; | |
1548 | ||
1549 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
ef9f0a83 | 1550 | amdgpu_bo_unreserve(vm->page_directory); |
2bd9ccfa CK |
1551 | if (r) |
1552 | goto error_free_page_directory; | |
5a712a87 | 1553 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
d38ceaf9 AD |
1554 | |
1555 | return 0; | |
2bd9ccfa CK |
1556 | |
1557 | error_free_page_directory: | |
1558 | amdgpu_bo_unref(&vm->page_directory); | |
1559 | vm->page_directory = NULL; | |
1560 | ||
1561 | error_free_sched_entity: | |
1562 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1563 | ||
1564 | return r; | |
d38ceaf9 AD |
1565 | } |
1566 | ||
1567 | /** | |
1568 | * amdgpu_vm_fini - tear down a vm instance | |
1569 | * | |
1570 | * @adev: amdgpu_device pointer | |
1571 | * @vm: requested vm | |
1572 | * | |
8843dbbb | 1573 | * Tear down @vm. |
d38ceaf9 AD |
1574 | * Unbind the VM and remove all bos from the vm bo list |
1575 | */ | |
1576 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1577 | { | |
1578 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1579 | int i; | |
1580 | ||
2d55e45a | 1581 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1582 | |
d38ceaf9 AD |
1583 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1584 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1585 | } | |
1586 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1587 | list_del(&mapping->list); | |
1588 | interval_tree_remove(&mapping->it, &vm->va); | |
1589 | kfree(mapping); | |
1590 | } | |
1591 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1592 | list_del(&mapping->list); | |
1593 | kfree(mapping); | |
1594 | } | |
1595 | ||
1baa439f CZ |
1596 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) { |
1597 | if (vm->page_tables[i].entry.robj && | |
1598 | vm->page_tables[i].entry.robj->shadow) | |
1599 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj->shadow); | |
ee1782c3 | 1600 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
1baa439f | 1601 | } |
9571e1d8 | 1602 | drm_free_large(vm->page_tables); |
d38ceaf9 | 1603 | |
1baa439f CZ |
1604 | if (vm->page_directory->shadow) |
1605 | amdgpu_bo_unref(&vm->page_directory->shadow); | |
d38ceaf9 | 1606 | amdgpu_bo_unref(&vm->page_directory); |
05906dec | 1607 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1608 | } |
ea89f8c9 | 1609 | |
a9a78b32 CK |
1610 | /** |
1611 | * amdgpu_vm_manager_init - init the VM manager | |
1612 | * | |
1613 | * @adev: amdgpu_device pointer | |
1614 | * | |
1615 | * Initialize the VM manager structures | |
1616 | */ | |
1617 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1618 | { | |
1619 | unsigned i; | |
1620 | ||
1621 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1622 | ||
1623 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1624 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1625 | amdgpu_vm_reset_id(adev, i); | |
832a902f | 1626 | amdgpu_sync_create(&adev->vm_manager.ids[i].active); |
a9a78b32 CK |
1627 | list_add_tail(&adev->vm_manager.ids[i].list, |
1628 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1629 | } |
2d55e45a | 1630 | |
1fbb2e92 CK |
1631 | adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); |
1632 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | |
1633 | adev->vm_manager.seqno[i] = 0; | |
1634 | ||
2d55e45a | 1635 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 1636 | atomic64_set(&adev->vm_manager.client_counter, 0); |
a9a78b32 CK |
1637 | } |
1638 | ||
ea89f8c9 CK |
1639 | /** |
1640 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1641 | * | |
1642 | * @adev: amdgpu_device pointer | |
1643 | * | |
1644 | * Cleanup the VM manager and free resources. | |
1645 | */ | |
1646 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1647 | { | |
1648 | unsigned i; | |
1649 | ||
bcb1ba35 CK |
1650 | for (i = 0; i < AMDGPU_NUM_VM; ++i) { |
1651 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; | |
1652 | ||
832a902f CK |
1653 | fence_put(adev->vm_manager.ids[i].first); |
1654 | amdgpu_sync_free(&adev->vm_manager.ids[i].active); | |
bcb1ba35 CK |
1655 | fence_put(id->flushed_updates); |
1656 | } | |
ea89f8c9 | 1657 | } |