]>
Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
4ff37a83 CK |
53 | /* Special value that no flush is necessary */ |
54 | #define AMDGPU_VM_NO_FLUSH (~0ll) | |
55 | ||
d38ceaf9 AD |
56 | /** |
57 | * amdgpu_vm_num_pde - return the number of page directory entries | |
58 | * | |
59 | * @adev: amdgpu_device pointer | |
60 | * | |
8843dbbb | 61 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
62 | */ |
63 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
64 | { | |
65 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
66 | } | |
67 | ||
68 | /** | |
69 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
70 | * | |
71 | * @adev: amdgpu_device pointer | |
72 | * | |
8843dbbb | 73 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
74 | */ |
75 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
76 | { | |
77 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
78 | } | |
79 | ||
80 | /** | |
56467ebf | 81 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
82 | * |
83 | * @vm: vm providing the BOs | |
3c0eea6c | 84 | * @validated: head of validation list |
56467ebf | 85 | * @entry: entry to add |
d38ceaf9 AD |
86 | * |
87 | * Add the page directory to the list of BOs to | |
56467ebf | 88 | * validate for command submission. |
d38ceaf9 | 89 | */ |
56467ebf CK |
90 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
91 | struct list_head *validated, | |
92 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 93 | { |
56467ebf | 94 | entry->robj = vm->page_directory; |
56467ebf CK |
95 | entry->priority = 0; |
96 | entry->tv.bo = &vm->page_directory->tbo; | |
97 | entry->tv.shared = true; | |
2f568dbd | 98 | entry->user_pages = NULL; |
56467ebf CK |
99 | list_add(&entry->tv.head, validated); |
100 | } | |
d38ceaf9 | 101 | |
56467ebf | 102 | /** |
ee1782c3 | 103 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf CK |
104 | * |
105 | * @vm: vm providing the BOs | |
3c0eea6c | 106 | * @duplicates: head of duplicates list |
d38ceaf9 | 107 | * |
ee1782c3 CK |
108 | * Add the page directory to the BO duplicates list |
109 | * for command submission. | |
d38ceaf9 | 110 | */ |
ee1782c3 | 111 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates) |
d38ceaf9 | 112 | { |
ee1782c3 | 113 | unsigned i; |
d38ceaf9 AD |
114 | |
115 | /* add the vm page table to the list */ | |
ee1782c3 CK |
116 | for (i = 0; i <= vm->max_pde_used; ++i) { |
117 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
118 | ||
119 | if (!entry->robj) | |
d38ceaf9 AD |
120 | continue; |
121 | ||
ee1782c3 | 122 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 123 | } |
eceb8a15 CK |
124 | |
125 | } | |
126 | ||
127 | /** | |
128 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
129 | * | |
130 | * @adev: amdgpu device instance | |
131 | * @vm: vm providing the BOs | |
132 | * | |
133 | * Move the PT BOs to the tail of the LRU. | |
134 | */ | |
135 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
136 | struct amdgpu_vm *vm) | |
137 | { | |
138 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
139 | unsigned i; | |
140 | ||
141 | spin_lock(&glob->lru_lock); | |
142 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
143 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
144 | ||
145 | if (!entry->robj) | |
146 | continue; | |
147 | ||
148 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
149 | } | |
150 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
151 | } |
152 | ||
153 | /** | |
154 | * amdgpu_vm_grab_id - allocate the next free VMID | |
155 | * | |
d38ceaf9 | 156 | * @vm: vm to allocate id for |
7f8a5290 CK |
157 | * @ring: ring we want to submit job to |
158 | * @sync: sync object where we add dependencies | |
94dd0a4a | 159 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 160 | * |
7f8a5290 | 161 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 162 | */ |
7f8a5290 | 163 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 CK |
164 | struct amdgpu_sync *sync, struct fence *fence, |
165 | unsigned *vm_id, uint64_t *vm_pd_addr) | |
d38ceaf9 | 166 | { |
4ff37a83 | 167 | uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); |
d38ceaf9 | 168 | struct amdgpu_device *adev = ring->adev; |
bcb1ba35 | 169 | struct amdgpu_vm_id *id = vm->ids[ring->idx]; |
4ff37a83 | 170 | struct fence *updates = sync->last_vm_update; |
a9a78b32 | 171 | int r; |
d38ceaf9 | 172 | |
94dd0a4a CK |
173 | mutex_lock(&adev->vm_manager.lock); |
174 | ||
d38ceaf9 | 175 | /* check if the id is still valid */ |
bcb1ba35 | 176 | if (id) { |
4ff37a83 | 177 | struct fence *flushed = id->flushed_updates; |
bcb1ba35 CK |
178 | long owner = atomic_long_read(&id->owner); |
179 | bool usable = pd_addr == id->pd_gpu_addr; | |
1c16c0a7 | 180 | |
bcb1ba35 CK |
181 | if (owner != (long)&vm->ids[ring->idx]) |
182 | usable = false; | |
183 | else if (!flushed) | |
184 | usable = false; | |
4ff37a83 | 185 | else if (!updates) |
bcb1ba35 | 186 | usable = true; |
4ff37a83 | 187 | else |
bcb1ba35 | 188 | usable = !fence_is_later(updates, flushed); |
4ff37a83 | 189 | |
bcb1ba35 | 190 | if (usable) { |
4ff37a83 | 191 | |
bcb1ba35 | 192 | r = amdgpu_sync_fence(ring->adev, sync, id->active); |
a8bd1bec CK |
193 | if (r) { |
194 | mutex_unlock(&adev->vm_manager.lock); | |
195 | return r; | |
196 | } | |
197 | ||
bcb1ba35 CK |
198 | fence_put(id->active); |
199 | id->active = fence_get(fence); | |
4ff37a83 | 200 | |
bcb1ba35 | 201 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
d38ceaf9 | 202 | |
bcb1ba35 | 203 | *vm_id = id - adev->vm_manager.ids; |
4ff37a83 | 204 | *vm_pd_addr = AMDGPU_VM_NO_FLUSH; |
22073fe7 CK |
205 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, |
206 | *vm_pd_addr); | |
d38ceaf9 | 207 | |
94dd0a4a | 208 | mutex_unlock(&adev->vm_manager.lock); |
7f8a5290 | 209 | return 0; |
d38ceaf9 | 210 | } |
d38ceaf9 AD |
211 | } |
212 | ||
bcb1ba35 CK |
213 | id = list_first_entry(&adev->vm_manager.ids_lru, |
214 | struct amdgpu_vm_id, | |
215 | list); | |
7f8a5290 | 216 | |
bcb1ba35 CK |
217 | if (id->active && !fence_is_signaled(id->active)) { |
218 | struct amdgpu_vm_id *tmp; | |
8e9fbeb5 | 219 | struct list_head *head = &adev->vm_manager.ids_lru; |
bcb1ba35 CK |
220 | |
221 | list_for_each_entry_safe(id, tmp, &adev->vm_manager.ids_lru, | |
222 | list) { | |
223 | if (id->active && fence_is_signaled(id->active)) { | |
224 | list_move(&id->list, head); | |
225 | head = &id->list; | |
8e9fbeb5 CZ |
226 | } |
227 | } | |
bcb1ba35 CK |
228 | id = list_first_entry(&adev->vm_manager.ids_lru, |
229 | struct amdgpu_vm_id, | |
230 | list); | |
8e9fbeb5 CZ |
231 | } |
232 | ||
bcb1ba35 | 233 | r = amdgpu_sync_fence(ring->adev, sync, id->active); |
4ff37a83 | 234 | if (!r) { |
bcb1ba35 CK |
235 | fence_put(id->active); |
236 | id->active = fence_get(fence); | |
94dd0a4a | 237 | |
4ff37a83 CK |
238 | fence_put(id->flushed_updates); |
239 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 240 | |
4ff37a83 | 241 | id->pd_gpu_addr = pd_addr; |
94dd0a4a | 242 | |
bcb1ba35 CK |
243 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
244 | atomic_long_set(&id->owner, (long)&vm->ids[ring->idx]); | |
245 | vm->ids[ring->idx] = id; | |
4ff37a83 | 246 | |
bcb1ba35 | 247 | *vm_id = id - adev->vm_manager.ids; |
4ff37a83 | 248 | *vm_pd_addr = pd_addr; |
22073fe7 | 249 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); |
d38ceaf9 AD |
250 | } |
251 | ||
94dd0a4a | 252 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 253 | return r; |
d38ceaf9 AD |
254 | } |
255 | ||
256 | /** | |
257 | * amdgpu_vm_flush - hardware flush the vm | |
258 | * | |
259 | * @ring: ring to use for flush | |
cffadc83 | 260 | * @vm_id: vmid number to use |
4ff37a83 | 261 | * @pd_addr: address of the page directory |
d38ceaf9 | 262 | * |
4ff37a83 | 263 | * Emit a VM flush when it is necessary. |
d38ceaf9 AD |
264 | */ |
265 | void amdgpu_vm_flush(struct amdgpu_ring *ring, | |
cffadc83 CK |
266 | unsigned vm_id, uint64_t pd_addr, |
267 | uint32_t gds_base, uint32_t gds_size, | |
268 | uint32_t gws_base, uint32_t gws_size, | |
269 | uint32_t oa_base, uint32_t oa_size) | |
d38ceaf9 | 270 | { |
971fe9a9 | 271 | struct amdgpu_device *adev = ring->adev; |
bcb1ba35 | 272 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
d564a06e | 273 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
bcb1ba35 CK |
274 | id->gds_base != gds_base || |
275 | id->gds_size != gds_size || | |
276 | id->gws_base != gws_base || | |
277 | id->gws_size != gws_size || | |
278 | id->oa_base != oa_base || | |
279 | id->oa_size != oa_size); | |
d564a06e CK |
280 | |
281 | if (ring->funcs->emit_pipeline_sync && ( | |
282 | pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed)) | |
283 | amdgpu_ring_emit_pipeline_sync(ring); | |
971fe9a9 | 284 | |
4ff37a83 | 285 | if (pd_addr != AMDGPU_VM_NO_FLUSH) { |
cffadc83 CK |
286 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); |
287 | amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); | |
d38ceaf9 | 288 | } |
cffadc83 | 289 | |
d564a06e | 290 | if (gds_switch_needed) { |
bcb1ba35 CK |
291 | id->gds_base = gds_base; |
292 | id->gds_size = gds_size; | |
293 | id->gws_base = gws_base; | |
294 | id->gws_size = gws_size; | |
295 | id->oa_base = oa_base; | |
296 | id->oa_size = oa_size; | |
cffadc83 CK |
297 | amdgpu_ring_emit_gds_switch(ring, vm_id, |
298 | gds_base, gds_size, | |
299 | gws_base, gws_size, | |
300 | oa_base, oa_size); | |
971fe9a9 CK |
301 | } |
302 | } | |
303 | ||
304 | /** | |
305 | * amdgpu_vm_reset_id - reset VMID to zero | |
306 | * | |
307 | * @adev: amdgpu device structure | |
308 | * @vm_id: vmid number to use | |
309 | * | |
310 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
311 | */ | |
312 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
313 | { | |
bcb1ba35 CK |
314 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
315 | ||
316 | id->gds_base = 0; | |
317 | id->gds_size = 0; | |
318 | id->gws_base = 0; | |
319 | id->gws_size = 0; | |
320 | id->oa_base = 0; | |
321 | id->oa_size = 0; | |
d38ceaf9 AD |
322 | } |
323 | ||
d38ceaf9 AD |
324 | /** |
325 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
326 | * | |
327 | * @vm: requested vm | |
328 | * @bo: requested buffer object | |
329 | * | |
8843dbbb | 330 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
331 | * Search inside the @bos vm list for the requested vm |
332 | * Returns the found bo_va or NULL if none is found | |
333 | * | |
334 | * Object has to be reserved! | |
335 | */ | |
336 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
337 | struct amdgpu_bo *bo) | |
338 | { | |
339 | struct amdgpu_bo_va *bo_va; | |
340 | ||
341 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
342 | if (bo_va->vm == vm) { | |
343 | return bo_va; | |
344 | } | |
345 | } | |
346 | return NULL; | |
347 | } | |
348 | ||
349 | /** | |
350 | * amdgpu_vm_update_pages - helper to call the right asic function | |
351 | * | |
352 | * @adev: amdgpu_device pointer | |
fa3ab3c7 CK |
353 | * @src: address where to copy page table entries from |
354 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 AD |
355 | * @ib: indirect buffer to fill with commands |
356 | * @pe: addr of the page entry | |
357 | * @addr: dst addr to write into pe | |
358 | * @count: number of page entries to update | |
359 | * @incr: increase next addr by incr bytes | |
360 | * @flags: hw access flags | |
d38ceaf9 AD |
361 | * |
362 | * Traces the parameters and calls the right asic functions | |
363 | * to setup the page table using the DMA. | |
364 | */ | |
365 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
fa3ab3c7 CK |
366 | uint64_t src, |
367 | dma_addr_t *pages_addr, | |
d38ceaf9 AD |
368 | struct amdgpu_ib *ib, |
369 | uint64_t pe, uint64_t addr, | |
370 | unsigned count, uint32_t incr, | |
9ab21462 | 371 | uint32_t flags) |
d38ceaf9 AD |
372 | { |
373 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
374 | ||
fa3ab3c7 CK |
375 | if (src) { |
376 | src += (addr >> 12) * 8; | |
d38ceaf9 AD |
377 | amdgpu_vm_copy_pte(adev, ib, pe, src, count); |
378 | ||
fa3ab3c7 | 379 | } else if (pages_addr) { |
b07c9d2a CK |
380 | amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr, |
381 | count, incr, flags); | |
382 | ||
383 | } else if (count < 3) { | |
384 | amdgpu_vm_write_pte(adev, ib, NULL, pe, addr, | |
385 | count, incr, flags); | |
d38ceaf9 AD |
386 | |
387 | } else { | |
388 | amdgpu_vm_set_pte_pde(adev, ib, pe, addr, | |
389 | count, incr, flags); | |
390 | } | |
391 | } | |
392 | ||
393 | /** | |
394 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
395 | * | |
396 | * @adev: amdgpu_device pointer | |
397 | * @bo: bo to clear | |
ef9f0a83 CZ |
398 | * |
399 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
400 | */ |
401 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 402 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
403 | struct amdgpu_bo *bo) |
404 | { | |
2d55e45a | 405 | struct amdgpu_ring *ring; |
4af9f07c | 406 | struct fence *fence = NULL; |
d71518b5 | 407 | struct amdgpu_job *job; |
d38ceaf9 AD |
408 | unsigned entries; |
409 | uint64_t addr; | |
410 | int r; | |
411 | ||
2d55e45a CK |
412 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
413 | ||
ca952613 | 414 | r = reservation_object_reserve_shared(bo->tbo.resv); |
415 | if (r) | |
416 | return r; | |
417 | ||
d38ceaf9 AD |
418 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
419 | if (r) | |
ef9f0a83 | 420 | goto error; |
d38ceaf9 AD |
421 | |
422 | addr = amdgpu_bo_gpu_offset(bo); | |
423 | entries = amdgpu_bo_size(bo) / 8; | |
424 | ||
d71518b5 CK |
425 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
426 | if (r) | |
ef9f0a83 | 427 | goto error; |
d38ceaf9 | 428 | |
fa3ab3c7 | 429 | amdgpu_vm_update_pages(adev, 0, NULL, &job->ibs[0], addr, 0, entries, |
d71518b5 CK |
430 | 0, 0); |
431 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); | |
432 | ||
433 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
434 | r = amdgpu_job_submit(job, ring, &vm->entity, |
435 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
436 | if (r) |
437 | goto error_free; | |
438 | ||
d71518b5 | 439 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 440 | fence_put(fence); |
cadf97b1 | 441 | return 0; |
ef9f0a83 | 442 | |
d38ceaf9 | 443 | error_free: |
d71518b5 | 444 | amdgpu_job_free(job); |
d38ceaf9 | 445 | |
ef9f0a83 | 446 | error: |
d38ceaf9 AD |
447 | return r; |
448 | } | |
449 | ||
450 | /** | |
b07c9d2a | 451 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 452 | * |
b07c9d2a | 453 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
454 | * @addr: the unmapped addr |
455 | * | |
456 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 457 | * to and return the pointer for the page table entry. |
d38ceaf9 | 458 | */ |
b07c9d2a | 459 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
460 | { |
461 | uint64_t result; | |
462 | ||
b07c9d2a CK |
463 | if (pages_addr) { |
464 | /* page table offset */ | |
465 | result = pages_addr[addr >> PAGE_SHIFT]; | |
466 | ||
467 | /* in case cpu page size != gpu page size*/ | |
468 | result |= addr & (~PAGE_MASK); | |
469 | ||
470 | } else { | |
471 | /* No mapping required */ | |
472 | result = addr; | |
473 | } | |
d38ceaf9 | 474 | |
b07c9d2a | 475 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
476 | |
477 | return result; | |
478 | } | |
479 | ||
480 | /** | |
481 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
482 | * | |
483 | * @adev: amdgpu_device pointer | |
484 | * @vm: requested vm | |
485 | * @start: start of GPU address range | |
486 | * @end: end of GPU address range | |
487 | * | |
488 | * Allocates new page tables if necessary | |
8843dbbb | 489 | * and updates the page directory. |
d38ceaf9 | 490 | * Returns 0 for success, error for failure. |
d38ceaf9 AD |
491 | */ |
492 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
493 | struct amdgpu_vm *vm) | |
494 | { | |
2d55e45a | 495 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
496 | struct amdgpu_bo *pd = vm->page_directory; |
497 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
498 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
499 | uint64_t last_pde = ~0, last_pt = ~0; | |
500 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 501 | struct amdgpu_job *job; |
d5fc5e82 | 502 | struct amdgpu_ib *ib; |
4af9f07c | 503 | struct fence *fence = NULL; |
d5fc5e82 | 504 | |
d38ceaf9 AD |
505 | int r; |
506 | ||
2d55e45a CK |
507 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
508 | ||
d38ceaf9 AD |
509 | /* padding, etc. */ |
510 | ndw = 64; | |
511 | ||
512 | /* assume the worst case */ | |
513 | ndw += vm->max_pde_used * 6; | |
514 | ||
d71518b5 CK |
515 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
516 | if (r) | |
d38ceaf9 | 517 | return r; |
d71518b5 CK |
518 | |
519 | ib = &job->ibs[0]; | |
d38ceaf9 AD |
520 | |
521 | /* walk over the address space and update the page directory */ | |
522 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 523 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
524 | uint64_t pde, pt; |
525 | ||
526 | if (bo == NULL) | |
527 | continue; | |
528 | ||
529 | pt = amdgpu_bo_gpu_offset(bo); | |
530 | if (vm->page_tables[pt_idx].addr == pt) | |
531 | continue; | |
532 | vm->page_tables[pt_idx].addr = pt; | |
533 | ||
534 | pde = pd_addr + pt_idx * 8; | |
535 | if (((last_pde + 8 * count) != pde) || | |
536 | ((last_pt + incr * count) != pt)) { | |
537 | ||
538 | if (count) { | |
fa3ab3c7 | 539 | amdgpu_vm_update_pages(adev, 0, NULL, ib, |
9ab21462 CK |
540 | last_pde, last_pt, |
541 | count, incr, | |
542 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
543 | } |
544 | ||
545 | count = 1; | |
546 | last_pde = pde; | |
547 | last_pt = pt; | |
548 | } else { | |
549 | ++count; | |
550 | } | |
551 | } | |
552 | ||
553 | if (count) | |
fa3ab3c7 | 554 | amdgpu_vm_update_pages(adev, 0, NULL, ib, last_pde, last_pt, |
9ab21462 | 555 | count, incr, AMDGPU_PTE_VALID); |
d38ceaf9 | 556 | |
d5fc5e82 | 557 | if (ib->length_dw != 0) { |
9e5d5309 | 558 | amdgpu_ring_pad_ib(ring, ib); |
e86f9cee CK |
559 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
560 | AMDGPU_FENCE_OWNER_VM); | |
d5fc5e82 | 561 | WARN_ON(ib->length_dw > ndw); |
2bd9ccfa CK |
562 | r = amdgpu_job_submit(job, ring, &vm->entity, |
563 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
564 | if (r) |
565 | goto error_free; | |
05906dec | 566 | |
4af9f07c | 567 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
568 | fence_put(vm->page_directory_fence); |
569 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 570 | fence_put(fence); |
d5fc5e82 | 571 | |
d71518b5 CK |
572 | } else { |
573 | amdgpu_job_free(job); | |
d5fc5e82 | 574 | } |
d38ceaf9 AD |
575 | |
576 | return 0; | |
d5fc5e82 CZ |
577 | |
578 | error_free: | |
d71518b5 | 579 | amdgpu_job_free(job); |
4af9f07c | 580 | return r; |
d38ceaf9 AD |
581 | } |
582 | ||
583 | /** | |
584 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
585 | * | |
586 | * @adev: amdgpu_device pointer | |
fa3ab3c7 CK |
587 | * @src: address where to copy page table entries from |
588 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 AD |
589 | * @ib: IB for the update |
590 | * @pe_start: first PTE to handle | |
591 | * @pe_end: last PTE to handle | |
592 | * @addr: addr those PTEs should point to | |
593 | * @flags: hw mapping flags | |
d38ceaf9 AD |
594 | */ |
595 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
fa3ab3c7 CK |
596 | uint64_t src, |
597 | dma_addr_t *pages_addr, | |
d38ceaf9 AD |
598 | struct amdgpu_ib *ib, |
599 | uint64_t pe_start, uint64_t pe_end, | |
9ab21462 | 600 | uint64_t addr, uint32_t flags) |
d38ceaf9 AD |
601 | { |
602 | /** | |
603 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
604 | * field in the PTE. When this field is set to a non-zero value, page | |
605 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
606 | * flags are considered valid for all PTEs within the fragment range | |
607 | * and corresponding mappings are assumed to be physically contiguous. | |
608 | * | |
609 | * The L1 TLB can store a single PTE for the whole fragment, | |
610 | * significantly increasing the space available for translation | |
611 | * caching. This leads to large improvements in throughput when the | |
612 | * TLB is under pressure. | |
613 | * | |
614 | * The L2 TLB distributes small and large fragments into two | |
615 | * asymmetric partitions. The large fragment cache is significantly | |
616 | * larger. Thus, we try to use large fragments wherever possible. | |
617 | * Userspace can support this by aligning virtual base address and | |
618 | * allocation size to the fragment size. | |
619 | */ | |
620 | ||
621 | /* SI and newer are optimized for 64KB */ | |
622 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
623 | uint64_t frag_align = 0x80; | |
624 | ||
625 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
626 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
627 | ||
628 | unsigned count; | |
629 | ||
31f6c1fe CK |
630 | /* Abort early if there isn't anything to do */ |
631 | if (pe_start == pe_end) | |
632 | return; | |
633 | ||
d38ceaf9 | 634 | /* system pages are non continuously */ |
fa3ab3c7 CK |
635 | if (src || pages_addr || !(flags & AMDGPU_PTE_VALID) || |
636 | (frag_start >= frag_end)) { | |
d38ceaf9 AD |
637 | |
638 | count = (pe_end - pe_start) / 8; | |
fa3ab3c7 | 639 | amdgpu_vm_update_pages(adev, src, pages_addr, ib, pe_start, |
9ab21462 CK |
640 | addr, count, AMDGPU_GPU_PAGE_SIZE, |
641 | flags); | |
d38ceaf9 AD |
642 | return; |
643 | } | |
644 | ||
645 | /* handle the 4K area at the beginning */ | |
646 | if (pe_start != frag_start) { | |
647 | count = (frag_start - pe_start) / 8; | |
fa3ab3c7 | 648 | amdgpu_vm_update_pages(adev, 0, NULL, ib, pe_start, addr, |
9ab21462 | 649 | count, AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
650 | addr += AMDGPU_GPU_PAGE_SIZE * count; |
651 | } | |
652 | ||
653 | /* handle the area in the middle */ | |
654 | count = (frag_end - frag_start) / 8; | |
fa3ab3c7 | 655 | amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_start, addr, count, |
9ab21462 | 656 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags); |
d38ceaf9 AD |
657 | |
658 | /* handle the 4K area at the end */ | |
659 | if (frag_end != pe_end) { | |
660 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
661 | count = (pe_end - frag_end) / 8; | |
fa3ab3c7 | 662 | amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_end, addr, |
9ab21462 | 663 | count, AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
664 | } |
665 | } | |
666 | ||
667 | /** | |
668 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
669 | * | |
670 | * @adev: amdgpu_device pointer | |
fa3ab3c7 CK |
671 | * @src: address where to copy page table entries from |
672 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 AD |
673 | * @vm: requested vm |
674 | * @start: start of GPU address range | |
675 | * @end: end of GPU address range | |
676 | * @dst: destination address to map to | |
677 | * @flags: mapping flags | |
678 | * | |
8843dbbb | 679 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 680 | */ |
a1e08d3b | 681 | static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, |
fa3ab3c7 CK |
682 | uint64_t src, |
683 | dma_addr_t *pages_addr, | |
a1e08d3b CK |
684 | struct amdgpu_vm *vm, |
685 | struct amdgpu_ib *ib, | |
686 | uint64_t start, uint64_t end, | |
687 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 688 | { |
31f6c1fe CK |
689 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
690 | ||
691 | uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0; | |
d38ceaf9 AD |
692 | uint64_t addr; |
693 | ||
694 | /* walk over the address space and update the page tables */ | |
695 | for (addr = start; addr < end; ) { | |
696 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | |
ee1782c3 | 697 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 | 698 | unsigned nptes; |
31f6c1fe | 699 | uint64_t pe_start; |
d38ceaf9 AD |
700 | |
701 | if ((addr & ~mask) == (end & ~mask)) | |
702 | nptes = end - addr; | |
703 | else | |
704 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
705 | ||
31f6c1fe CK |
706 | pe_start = amdgpu_bo_gpu_offset(pt); |
707 | pe_start += (addr & mask) * 8; | |
d38ceaf9 | 708 | |
31f6c1fe | 709 | if (last_pe_end != pe_start) { |
d38ceaf9 | 710 | |
fa3ab3c7 | 711 | amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, |
31f6c1fe CK |
712 | last_pe_start, last_pe_end, |
713 | last_dst, flags); | |
d38ceaf9 | 714 | |
31f6c1fe CK |
715 | last_pe_start = pe_start; |
716 | last_pe_end = pe_start + 8 * nptes; | |
d38ceaf9 AD |
717 | last_dst = dst; |
718 | } else { | |
31f6c1fe | 719 | last_pe_end += 8 * nptes; |
d38ceaf9 AD |
720 | } |
721 | ||
722 | addr += nptes; | |
723 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
724 | } | |
725 | ||
fa3ab3c7 CK |
726 | amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, last_pe_start, |
727 | last_pe_end, last_dst, flags); | |
d38ceaf9 AD |
728 | } |
729 | ||
d38ceaf9 AD |
730 | /** |
731 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
732 | * | |
733 | * @adev: amdgpu_device pointer | |
fa3ab3c7 CK |
734 | * @src: address where to copy page table entries from |
735 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 736 | * @vm: requested vm |
a14faa65 CK |
737 | * @start: start of mapped range |
738 | * @last: last mapped entry | |
739 | * @flags: flags for the entries | |
d38ceaf9 | 740 | * @addr: addr to set the area to |
d38ceaf9 AD |
741 | * @fence: optional resulting fence |
742 | * | |
a14faa65 | 743 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 744 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
745 | */ |
746 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
fa3ab3c7 CK |
747 | uint64_t src, |
748 | dma_addr_t *pages_addr, | |
d38ceaf9 | 749 | struct amdgpu_vm *vm, |
a14faa65 CK |
750 | uint64_t start, uint64_t last, |
751 | uint32_t flags, uint64_t addr, | |
752 | struct fence **fence) | |
d38ceaf9 | 753 | { |
2d55e45a | 754 | struct amdgpu_ring *ring; |
a1e08d3b | 755 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 756 | unsigned nptes, ncmds, ndw; |
d71518b5 | 757 | struct amdgpu_job *job; |
d5fc5e82 | 758 | struct amdgpu_ib *ib; |
4af9f07c | 759 | struct fence *f = NULL; |
d38ceaf9 AD |
760 | int r; |
761 | ||
2d55e45a CK |
762 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
763 | ||
a1e08d3b CK |
764 | /* sync to everything on unmapping */ |
765 | if (!(flags & AMDGPU_PTE_VALID)) | |
766 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
767 | ||
a14faa65 | 768 | nptes = last - start + 1; |
d38ceaf9 AD |
769 | |
770 | /* | |
771 | * reserve space for one command every (1 << BLOCK_SIZE) | |
772 | * entries or 2k dwords (whatever is smaller) | |
773 | */ | |
774 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
775 | ||
776 | /* padding, etc. */ | |
777 | ndw = 64; | |
778 | ||
fa3ab3c7 | 779 | if (src) { |
d38ceaf9 AD |
780 | /* only copy commands needed */ |
781 | ndw += ncmds * 7; | |
782 | ||
fa3ab3c7 | 783 | } else if (pages_addr) { |
d38ceaf9 AD |
784 | /* header for write data commands */ |
785 | ndw += ncmds * 4; | |
786 | ||
787 | /* body of write data command */ | |
788 | ndw += nptes * 2; | |
789 | ||
790 | } else { | |
791 | /* set page commands needed */ | |
792 | ndw += ncmds * 10; | |
793 | ||
794 | /* two extra commands for begin/end of fragment */ | |
795 | ndw += 2 * 10; | |
796 | } | |
797 | ||
d71518b5 CK |
798 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
799 | if (r) | |
d38ceaf9 | 800 | return r; |
d71518b5 CK |
801 | |
802 | ib = &job->ibs[0]; | |
d5fc5e82 | 803 | |
e86f9cee | 804 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
805 | owner); |
806 | if (r) | |
807 | goto error_free; | |
d38ceaf9 | 808 | |
a1e08d3b CK |
809 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
810 | if (r) | |
811 | goto error_free; | |
812 | ||
fa3ab3c7 CK |
813 | amdgpu_vm_update_ptes(adev, src, pages_addr, vm, ib, start, |
814 | last + 1, addr, flags); | |
d38ceaf9 | 815 | |
9e5d5309 | 816 | amdgpu_ring_pad_ib(ring, ib); |
d5fc5e82 | 817 | WARN_ON(ib->length_dw > ndw); |
2bd9ccfa CK |
818 | r = amdgpu_job_submit(job, ring, &vm->entity, |
819 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
820 | if (r) |
821 | goto error_free; | |
d38ceaf9 | 822 | |
bf60efd3 | 823 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
824 | if (fence) { |
825 | fence_put(*fence); | |
826 | *fence = fence_get(f); | |
827 | } | |
281b4223 | 828 | fence_put(f); |
d38ceaf9 | 829 | return 0; |
d5fc5e82 CZ |
830 | |
831 | error_free: | |
d71518b5 | 832 | amdgpu_job_free(job); |
4af9f07c | 833 | return r; |
d38ceaf9 AD |
834 | } |
835 | ||
a14faa65 CK |
836 | /** |
837 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
838 | * | |
839 | * @adev: amdgpu_device pointer | |
8358dcee CK |
840 | * @gtt_flags: flags as they are used for GTT |
841 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
842 | * @vm: requested vm |
843 | * @mapping: mapped range and flags to use for the update | |
844 | * @addr: addr to set the area to | |
8358dcee | 845 | * @flags: HW flags for the mapping |
a14faa65 CK |
846 | * @fence: optional resulting fence |
847 | * | |
848 | * Split the mapping into smaller chunks so that each update fits | |
849 | * into a SDMA IB. | |
850 | * Returns 0 for success, -EINVAL for failure. | |
851 | */ | |
852 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
a14faa65 | 853 | uint32_t gtt_flags, |
8358dcee | 854 | dma_addr_t *pages_addr, |
a14faa65 CK |
855 | struct amdgpu_vm *vm, |
856 | struct amdgpu_bo_va_mapping *mapping, | |
fa3ab3c7 CK |
857 | uint32_t flags, uint64_t addr, |
858 | struct fence **fence) | |
a14faa65 CK |
859 | { |
860 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
861 | ||
fa3ab3c7 | 862 | uint64_t src = 0, start = mapping->it.start; |
a14faa65 CK |
863 | int r; |
864 | ||
865 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
866 | * but in case of something, we filter the flags in first place | |
867 | */ | |
868 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
869 | flags &= ~AMDGPU_PTE_READABLE; | |
870 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
871 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
872 | ||
873 | trace_amdgpu_vm_bo_update(mapping); | |
874 | ||
8358dcee | 875 | if (pages_addr) { |
fa3ab3c7 CK |
876 | if (flags == gtt_flags) |
877 | src = adev->gart.table_addr + (addr >> 12) * 8; | |
fa3ab3c7 CK |
878 | addr = 0; |
879 | } | |
a14faa65 CK |
880 | addr += mapping->offset; |
881 | ||
8358dcee | 882 | if (!pages_addr || src) |
fa3ab3c7 | 883 | return amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm, |
a14faa65 CK |
884 | start, mapping->it.last, |
885 | flags, addr, fence); | |
886 | ||
887 | while (start != mapping->it.last + 1) { | |
888 | uint64_t last; | |
889 | ||
fb29b57c | 890 | last = min((uint64_t)mapping->it.last, start + max_size - 1); |
fa3ab3c7 | 891 | r = amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm, |
a14faa65 CK |
892 | start, last, flags, addr, |
893 | fence); | |
894 | if (r) | |
895 | return r; | |
896 | ||
897 | start = last + 1; | |
fb29b57c | 898 | addr += max_size * AMDGPU_GPU_PAGE_SIZE; |
a14faa65 CK |
899 | } |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
d38ceaf9 AD |
904 | /** |
905 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
906 | * | |
907 | * @adev: amdgpu_device pointer | |
908 | * @bo_va: requested BO and VM object | |
909 | * @mem: ttm mem | |
910 | * | |
911 | * Fill in the page table entries for @bo_va. | |
912 | * Returns 0 for success, -EINVAL for failure. | |
913 | * | |
914 | * Object have to be reserved and mutex must be locked! | |
915 | */ | |
916 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
917 | struct amdgpu_bo_va *bo_va, | |
918 | struct ttm_mem_reg *mem) | |
919 | { | |
920 | struct amdgpu_vm *vm = bo_va->vm; | |
921 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 922 | dma_addr_t *pages_addr = NULL; |
fa3ab3c7 | 923 | uint32_t gtt_flags, flags; |
d38ceaf9 AD |
924 | uint64_t addr; |
925 | int r; | |
926 | ||
927 | if (mem) { | |
8358dcee CK |
928 | struct ttm_dma_tt *ttm; |
929 | ||
b7d698d7 | 930 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
931 | switch (mem->mem_type) { |
932 | case TTM_PL_TT: | |
8358dcee CK |
933 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
934 | ttm_dma_tt, ttm); | |
935 | pages_addr = ttm->dma_address; | |
9ab21462 CK |
936 | break; |
937 | ||
938 | case TTM_PL_VRAM: | |
d38ceaf9 | 939 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
940 | break; |
941 | ||
942 | default: | |
943 | break; | |
944 | } | |
d38ceaf9 AD |
945 | } else { |
946 | addr = 0; | |
947 | } | |
948 | ||
d38ceaf9 | 949 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
fa3ab3c7 | 950 | gtt_flags = (adev == bo_va->bo->adev) ? flags : 0; |
d38ceaf9 | 951 | |
7fc11959 CK |
952 | spin_lock(&vm->status_lock); |
953 | if (!list_empty(&bo_va->vm_status)) | |
954 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
955 | spin_unlock(&vm->status_lock); | |
956 | ||
957 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
8358dcee CK |
958 | r = amdgpu_vm_bo_split_mapping(adev, gtt_flags, pages_addr, vm, |
959 | mapping, flags, addr, | |
960 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
961 | if (r) |
962 | return r; | |
963 | } | |
964 | ||
d6c10f6b CK |
965 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
966 | list_for_each_entry(mapping, &bo_va->valids, list) | |
967 | trace_amdgpu_vm_bo_mapping(mapping); | |
968 | ||
969 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
970 | trace_amdgpu_vm_bo_mapping(mapping); | |
971 | } | |
972 | ||
d38ceaf9 | 973 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 974 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 975 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
976 | if (!mem) |
977 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
978 | spin_unlock(&vm->status_lock); |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
983 | /** | |
984 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
985 | * | |
986 | * @adev: amdgpu_device pointer | |
987 | * @vm: requested vm | |
988 | * | |
989 | * Make sure all freed BOs are cleared in the PT. | |
990 | * Returns 0 for success. | |
991 | * | |
992 | * PTs have to be reserved and mutex must be locked! | |
993 | */ | |
994 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
995 | struct amdgpu_vm *vm) | |
996 | { | |
997 | struct amdgpu_bo_va_mapping *mapping; | |
998 | int r; | |
999 | ||
1000 | while (!list_empty(&vm->freed)) { | |
1001 | mapping = list_first_entry(&vm->freed, | |
1002 | struct amdgpu_bo_va_mapping, list); | |
1003 | list_del(&mapping->list); | |
e17841b9 | 1004 | |
8358dcee | 1005 | r = amdgpu_vm_bo_split_mapping(adev, 0, NULL, vm, mapping, |
fa3ab3c7 | 1006 | 0, 0, NULL); |
d38ceaf9 AD |
1007 | kfree(mapping); |
1008 | if (r) | |
1009 | return r; | |
1010 | ||
1011 | } | |
1012 | return 0; | |
1013 | ||
1014 | } | |
1015 | ||
1016 | /** | |
1017 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1018 | * | |
1019 | * @adev: amdgpu_device pointer | |
1020 | * @vm: requested vm | |
1021 | * | |
1022 | * Make sure all invalidated BOs are cleared in the PT. | |
1023 | * Returns 0 for success. | |
1024 | * | |
1025 | * PTs have to be reserved and mutex must be locked! | |
1026 | */ | |
1027 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1028 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1029 | { |
cfe2c978 | 1030 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1031 | int r = 0; |
d38ceaf9 AD |
1032 | |
1033 | spin_lock(&vm->status_lock); | |
1034 | while (!list_empty(&vm->invalidated)) { | |
1035 | bo_va = list_first_entry(&vm->invalidated, | |
1036 | struct amdgpu_bo_va, vm_status); | |
1037 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1038 | |
d38ceaf9 AD |
1039 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
1040 | if (r) | |
1041 | return r; | |
1042 | ||
1043 | spin_lock(&vm->status_lock); | |
1044 | } | |
1045 | spin_unlock(&vm->status_lock); | |
1046 | ||
cfe2c978 | 1047 | if (bo_va) |
bb1e38a4 | 1048 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1049 | |
1050 | return r; | |
d38ceaf9 AD |
1051 | } |
1052 | ||
1053 | /** | |
1054 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1055 | * | |
1056 | * @adev: amdgpu_device pointer | |
1057 | * @vm: requested vm | |
1058 | * @bo: amdgpu buffer object | |
1059 | * | |
8843dbbb | 1060 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1061 | * Add @bo to the list of bos associated with the vm |
1062 | * Returns newly added bo_va or NULL for failure | |
1063 | * | |
1064 | * Object has to be reserved! | |
1065 | */ | |
1066 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1067 | struct amdgpu_vm *vm, | |
1068 | struct amdgpu_bo *bo) | |
1069 | { | |
1070 | struct amdgpu_bo_va *bo_va; | |
1071 | ||
1072 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1073 | if (bo_va == NULL) { | |
1074 | return NULL; | |
1075 | } | |
1076 | bo_va->vm = vm; | |
1077 | bo_va->bo = bo; | |
d38ceaf9 AD |
1078 | bo_va->ref_count = 1; |
1079 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1080 | INIT_LIST_HEAD(&bo_va->valids); |
1081 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1082 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1083 | |
d38ceaf9 | 1084 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1085 | |
1086 | return bo_va; | |
1087 | } | |
1088 | ||
1089 | /** | |
1090 | * amdgpu_vm_bo_map - map bo inside a vm | |
1091 | * | |
1092 | * @adev: amdgpu_device pointer | |
1093 | * @bo_va: bo_va to store the address | |
1094 | * @saddr: where to map the BO | |
1095 | * @offset: requested offset in the BO | |
1096 | * @flags: attributes of pages (read/write/valid/etc.) | |
1097 | * | |
1098 | * Add a mapping of the BO at the specefied addr into the VM. | |
1099 | * Returns 0 for success, error for failure. | |
1100 | * | |
49b02b18 | 1101 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1102 | */ |
1103 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1104 | struct amdgpu_bo_va *bo_va, | |
1105 | uint64_t saddr, uint64_t offset, | |
1106 | uint64_t size, uint32_t flags) | |
1107 | { | |
1108 | struct amdgpu_bo_va_mapping *mapping; | |
1109 | struct amdgpu_vm *vm = bo_va->vm; | |
1110 | struct interval_tree_node *it; | |
1111 | unsigned last_pfn, pt_idx; | |
1112 | uint64_t eaddr; | |
1113 | int r; | |
1114 | ||
0be52de9 CK |
1115 | /* validate the parameters */ |
1116 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1117 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1118 | return -EINVAL; |
0be52de9 | 1119 | |
d38ceaf9 | 1120 | /* make sure object fit at this offset */ |
005ae95e | 1121 | eaddr = saddr + size - 1; |
49b02b18 | 1122 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1123 | return -EINVAL; |
d38ceaf9 AD |
1124 | |
1125 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1126 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1127 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1128 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1129 | return -EINVAL; |
1130 | } | |
1131 | ||
d38ceaf9 AD |
1132 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1133 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1134 | ||
005ae95e | 1135 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
d38ceaf9 AD |
1136 | if (it) { |
1137 | struct amdgpu_bo_va_mapping *tmp; | |
1138 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1139 | /* bo and tmp overlap, invalid addr */ | |
1140 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1141 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1142 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1143 | r = -EINVAL; |
f48b2659 | 1144 | goto error; |
d38ceaf9 AD |
1145 | } |
1146 | ||
1147 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1148 | if (!mapping) { | |
d38ceaf9 | 1149 | r = -ENOMEM; |
f48b2659 | 1150 | goto error; |
d38ceaf9 AD |
1151 | } |
1152 | ||
1153 | INIT_LIST_HEAD(&mapping->list); | |
1154 | mapping->it.start = saddr; | |
005ae95e | 1155 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1156 | mapping->offset = offset; |
1157 | mapping->flags = flags; | |
1158 | ||
7fc11959 | 1159 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 AD |
1160 | interval_tree_insert(&mapping->it, &vm->va); |
1161 | ||
1162 | /* Make sure the page tables are allocated */ | |
1163 | saddr >>= amdgpu_vm_block_size; | |
1164 | eaddr >>= amdgpu_vm_block_size; | |
1165 | ||
1166 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1167 | ||
1168 | if (eaddr > vm->max_pde_used) | |
1169 | vm->max_pde_used = eaddr; | |
1170 | ||
d38ceaf9 AD |
1171 | /* walk over the address space and allocate the page tables */ |
1172 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1173 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1174 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1175 | struct amdgpu_bo *pt; |
1176 | ||
ee1782c3 CK |
1177 | entry = &vm->page_tables[pt_idx].entry; |
1178 | if (entry->robj) | |
d38ceaf9 AD |
1179 | continue; |
1180 | ||
d38ceaf9 AD |
1181 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1182 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1183 | AMDGPU_GEM_DOMAIN_VRAM, |
1184 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 | 1185 | NULL, resv, &pt); |
49b02b18 | 1186 | if (r) |
d38ceaf9 | 1187 | goto error_free; |
49b02b18 | 1188 | |
82b9c55b CK |
1189 | /* Keep a reference to the page table to avoid freeing |
1190 | * them up in the wrong order. | |
1191 | */ | |
1192 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1193 | ||
2bd9ccfa | 1194 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 AD |
1195 | if (r) { |
1196 | amdgpu_bo_unref(&pt); | |
1197 | goto error_free; | |
1198 | } | |
1199 | ||
ee1782c3 | 1200 | entry->robj = pt; |
ee1782c3 CK |
1201 | entry->priority = 0; |
1202 | entry->tv.bo = &entry->robj->tbo; | |
1203 | entry->tv.shared = true; | |
2f568dbd | 1204 | entry->user_pages = NULL; |
d38ceaf9 | 1205 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1206 | } |
1207 | ||
d38ceaf9 AD |
1208 | return 0; |
1209 | ||
1210 | error_free: | |
d38ceaf9 AD |
1211 | list_del(&mapping->list); |
1212 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1213 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1214 | kfree(mapping); |
1215 | ||
f48b2659 | 1216 | error: |
d38ceaf9 AD |
1217 | return r; |
1218 | } | |
1219 | ||
1220 | /** | |
1221 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1222 | * | |
1223 | * @adev: amdgpu_device pointer | |
1224 | * @bo_va: bo_va to remove the address from | |
1225 | * @saddr: where to the BO is mapped | |
1226 | * | |
1227 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1228 | * Returns 0 for success, error for failure. | |
1229 | * | |
49b02b18 | 1230 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1231 | */ |
1232 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1233 | struct amdgpu_bo_va *bo_va, | |
1234 | uint64_t saddr) | |
1235 | { | |
1236 | struct amdgpu_bo_va_mapping *mapping; | |
1237 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1238 | bool valid = true; |
d38ceaf9 | 1239 | |
6c7fc503 | 1240 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1241 | |
7fc11959 | 1242 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1243 | if (mapping->it.start == saddr) |
1244 | break; | |
1245 | } | |
1246 | ||
7fc11959 CK |
1247 | if (&mapping->list == &bo_va->valids) { |
1248 | valid = false; | |
1249 | ||
1250 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1251 | if (mapping->it.start == saddr) | |
1252 | break; | |
1253 | } | |
1254 | ||
32b41ac2 | 1255 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1256 | return -ENOENT; |
d38ceaf9 | 1257 | } |
32b41ac2 | 1258 | |
d38ceaf9 AD |
1259 | list_del(&mapping->list); |
1260 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1261 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1262 | |
e17841b9 | 1263 | if (valid) |
d38ceaf9 | 1264 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1265 | else |
d38ceaf9 | 1266 | kfree(mapping); |
d38ceaf9 AD |
1267 | |
1268 | return 0; | |
1269 | } | |
1270 | ||
1271 | /** | |
1272 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1273 | * | |
1274 | * @adev: amdgpu_device pointer | |
1275 | * @bo_va: requested bo_va | |
1276 | * | |
8843dbbb | 1277 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1278 | * |
1279 | * Object have to be reserved! | |
1280 | */ | |
1281 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1282 | struct amdgpu_bo_va *bo_va) | |
1283 | { | |
1284 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1285 | struct amdgpu_vm *vm = bo_va->vm; | |
1286 | ||
1287 | list_del(&bo_va->bo_list); | |
1288 | ||
d38ceaf9 AD |
1289 | spin_lock(&vm->status_lock); |
1290 | list_del(&bo_va->vm_status); | |
1291 | spin_unlock(&vm->status_lock); | |
1292 | ||
7fc11959 | 1293 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1294 | list_del(&mapping->list); |
1295 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1296 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1297 | list_add(&mapping->list, &vm->freed); |
1298 | } | |
1299 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1300 | list_del(&mapping->list); | |
1301 | interval_tree_remove(&mapping->it, &vm->va); | |
1302 | kfree(mapping); | |
d38ceaf9 | 1303 | } |
32b41ac2 | 1304 | |
bb1e38a4 | 1305 | fence_put(bo_va->last_pt_update); |
d38ceaf9 | 1306 | kfree(bo_va); |
d38ceaf9 AD |
1307 | } |
1308 | ||
1309 | /** | |
1310 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1311 | * | |
1312 | * @adev: amdgpu_device pointer | |
1313 | * @vm: requested vm | |
1314 | * @bo: amdgpu buffer object | |
1315 | * | |
8843dbbb | 1316 | * Mark @bo as invalid. |
d38ceaf9 AD |
1317 | */ |
1318 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1319 | struct amdgpu_bo *bo) | |
1320 | { | |
1321 | struct amdgpu_bo_va *bo_va; | |
1322 | ||
1323 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1324 | spin_lock(&bo_va->vm->status_lock); |
1325 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1326 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1327 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1328 | } |
1329 | } | |
1330 | ||
1331 | /** | |
1332 | * amdgpu_vm_init - initialize a vm instance | |
1333 | * | |
1334 | * @adev: amdgpu_device pointer | |
1335 | * @vm: requested vm | |
1336 | * | |
8843dbbb | 1337 | * Init @vm fields. |
d38ceaf9 AD |
1338 | */ |
1339 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1340 | { | |
1341 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1342 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1343 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1344 | unsigned ring_instance; |
1345 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1346 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1347 | int i, r; |
1348 | ||
bcb1ba35 CK |
1349 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1350 | vm->ids[i] = NULL; | |
d38ceaf9 AD |
1351 | vm->va = RB_ROOT; |
1352 | spin_lock_init(&vm->status_lock); | |
1353 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1354 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1355 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 1356 | |
d38ceaf9 AD |
1357 | pd_size = amdgpu_vm_directory_size(adev); |
1358 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1359 | ||
1360 | /* allocate page table array */ | |
9571e1d8 | 1361 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1362 | if (vm->page_tables == NULL) { |
1363 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1364 | return -ENOMEM; | |
1365 | } | |
1366 | ||
2bd9ccfa | 1367 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1368 | |
1369 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1370 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1371 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1372 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1373 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1374 | rq, amdgpu_sched_jobs); | |
1375 | if (r) | |
1376 | return r; | |
1377 | ||
05906dec BN |
1378 | vm->page_directory_fence = NULL; |
1379 | ||
d38ceaf9 | 1380 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1381 | AMDGPU_GEM_DOMAIN_VRAM, |
1382 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1383 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1384 | if (r) |
2bd9ccfa CK |
1385 | goto error_free_sched_entity; |
1386 | ||
ef9f0a83 | 1387 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1388 | if (r) |
1389 | goto error_free_page_directory; | |
1390 | ||
1391 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
ef9f0a83 | 1392 | amdgpu_bo_unreserve(vm->page_directory); |
2bd9ccfa CK |
1393 | if (r) |
1394 | goto error_free_page_directory; | |
d38ceaf9 AD |
1395 | |
1396 | return 0; | |
2bd9ccfa CK |
1397 | |
1398 | error_free_page_directory: | |
1399 | amdgpu_bo_unref(&vm->page_directory); | |
1400 | vm->page_directory = NULL; | |
1401 | ||
1402 | error_free_sched_entity: | |
1403 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1404 | ||
1405 | return r; | |
d38ceaf9 AD |
1406 | } |
1407 | ||
1408 | /** | |
1409 | * amdgpu_vm_fini - tear down a vm instance | |
1410 | * | |
1411 | * @adev: amdgpu_device pointer | |
1412 | * @vm: requested vm | |
1413 | * | |
8843dbbb | 1414 | * Tear down @vm. |
d38ceaf9 AD |
1415 | * Unbind the VM and remove all bos from the vm bo list |
1416 | */ | |
1417 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1418 | { | |
1419 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1420 | int i; | |
1421 | ||
2d55e45a | 1422 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1423 | |
d38ceaf9 AD |
1424 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1425 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1426 | } | |
1427 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1428 | list_del(&mapping->list); | |
1429 | interval_tree_remove(&mapping->it, &vm->va); | |
1430 | kfree(mapping); | |
1431 | } | |
1432 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1433 | list_del(&mapping->list); | |
1434 | kfree(mapping); | |
1435 | } | |
1436 | ||
1437 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
ee1782c3 | 1438 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
9571e1d8 | 1439 | drm_free_large(vm->page_tables); |
d38ceaf9 AD |
1440 | |
1441 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1442 | fence_put(vm->page_directory_fence); |
20250215 | 1443 | |
d38ceaf9 | 1444 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
bcb1ba35 | 1445 | struct amdgpu_vm_id *id = vm->ids[i]; |
1c16c0a7 | 1446 | |
bcb1ba35 CK |
1447 | if (!id) |
1448 | continue; | |
1449 | ||
1450 | atomic_long_cmpxchg(&id->owner, (long)&vm->ids[i], 0); | |
d38ceaf9 | 1451 | } |
d38ceaf9 | 1452 | } |
ea89f8c9 | 1453 | |
a9a78b32 CK |
1454 | /** |
1455 | * amdgpu_vm_manager_init - init the VM manager | |
1456 | * | |
1457 | * @adev: amdgpu_device pointer | |
1458 | * | |
1459 | * Initialize the VM manager structures | |
1460 | */ | |
1461 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1462 | { | |
1463 | unsigned i; | |
1464 | ||
1465 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1466 | ||
1467 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1468 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1469 | amdgpu_vm_reset_id(adev, i); | |
a9a78b32 CK |
1470 | list_add_tail(&adev->vm_manager.ids[i].list, |
1471 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1472 | } |
2d55e45a CK |
1473 | |
1474 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); | |
a9a78b32 CK |
1475 | } |
1476 | ||
ea89f8c9 CK |
1477 | /** |
1478 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1479 | * | |
1480 | * @adev: amdgpu_device pointer | |
1481 | * | |
1482 | * Cleanup the VM manager and free resources. | |
1483 | */ | |
1484 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1485 | { | |
1486 | unsigned i; | |
1487 | ||
bcb1ba35 CK |
1488 | for (i = 0; i < AMDGPU_NUM_VM; ++i) { |
1489 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; | |
1490 | ||
1491 | fence_put(id->active); | |
1492 | fence_put(id->flushed_updates); | |
1493 | } | |
ea89f8c9 | 1494 | } |