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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
d38ceaf9 AD |
30 | #include <drm/drmP.h> |
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
33 | #include "amdgpu_trace.h" | |
34 | ||
35 | /* | |
36 | * GPUVM | |
37 | * GPUVM is similar to the legacy gart on older asics, however | |
38 | * rather than there being a single global gart table | |
39 | * for the entire GPU, there are multiple VM page tables active | |
40 | * at any given time. The VM page tables can contain a mix | |
41 | * vram pages and system memory pages and system memory pages | |
42 | * can be mapped as snooped (cached system pages) or unsnooped | |
43 | * (uncached system pages). | |
44 | * Each VM has an ID associated with it and there is a page table | |
45 | * associated with each VMID. When execting a command buffer, | |
46 | * the kernel tells the the ring what VMID to use for that command | |
47 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
48 | * The userspace drivers maintain their own address space and the kernel | |
49 | * sets up their pages tables accordingly when they submit their | |
50 | * command buffers and a VMID is assigned. | |
51 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
52 | * SI supports 16. | |
53 | */ | |
54 | ||
a9f87f64 CK |
55 | #define START(node) ((node)->start) |
56 | #define LAST(node) ((node)->last) | |
57 | ||
58 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
59 | START, LAST, static, amdgpu_vm_it) | |
60 | ||
61 | #undef START | |
62 | #undef LAST | |
63 | ||
f4833c4f HK |
64 | /* Local structure. Encapsulate some VM table update parameters to reduce |
65 | * the number of function parameters | |
66 | */ | |
29efc4f5 | 67 | struct amdgpu_pte_update_params { |
27c5f36f CK |
68 | /* amdgpu device we do this update for */ |
69 | struct amdgpu_device *adev; | |
49ac8a24 CK |
70 | /* optional amdgpu_vm we do this update for */ |
71 | struct amdgpu_vm *vm; | |
f4833c4f HK |
72 | /* address where to copy page table entries from */ |
73 | uint64_t src; | |
f4833c4f HK |
74 | /* indirect buffer to fill with commands */ |
75 | struct amdgpu_ib *ib; | |
afef8b8f CK |
76 | /* Function which actually does the update */ |
77 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
78 | uint64_t addr, unsigned count, uint32_t incr, | |
6b777607 | 79 | uint64_t flags); |
4c7e8855 CZ |
80 | /* indicate update pt or its shadow */ |
81 | bool shadow; | |
f4833c4f HK |
82 | }; |
83 | ||
284710fa CK |
84 | /* Helper to disable partial resident texture feature from a fence callback */ |
85 | struct amdgpu_prt_cb { | |
86 | struct amdgpu_device *adev; | |
87 | struct dma_fence_cb cb; | |
88 | }; | |
89 | ||
d38ceaf9 | 90 | /** |
72a7ec5c | 91 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
92 | * |
93 | * @adev: amdgpu_device pointer | |
94 | * | |
72a7ec5c | 95 | * Calculate the number of entries in a page directory or page table. |
d38ceaf9 | 96 | */ |
72a7ec5c CK |
97 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
98 | unsigned level) | |
d38ceaf9 | 99 | { |
72a7ec5c CK |
100 | if (level == 0) |
101 | /* For the root directory */ | |
102 | return adev->vm_manager.max_pfn >> | |
36b32a68 ZJ |
103 | (adev->vm_manager.block_size * |
104 | adev->vm_manager.num_level); | |
72a7ec5c CK |
105 | else if (level == adev->vm_manager.num_level) |
106 | /* For the page tables on the leaves */ | |
36b32a68 | 107 | return AMDGPU_VM_PTE_COUNT(adev); |
72a7ec5c CK |
108 | else |
109 | /* Everything in between */ | |
36b32a68 | 110 | return 1 << adev->vm_manager.block_size; |
d38ceaf9 AD |
111 | } |
112 | ||
113 | /** | |
72a7ec5c | 114 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
115 | * |
116 | * @adev: amdgpu_device pointer | |
117 | * | |
72a7ec5c | 118 | * Calculate the size of the BO for a page directory or page table in bytes. |
d38ceaf9 | 119 | */ |
72a7ec5c | 120 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 121 | { |
72a7ec5c | 122 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
123 | } |
124 | ||
125 | /** | |
56467ebf | 126 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
127 | * |
128 | * @vm: vm providing the BOs | |
3c0eea6c | 129 | * @validated: head of validation list |
56467ebf | 130 | * @entry: entry to add |
d38ceaf9 AD |
131 | * |
132 | * Add the page directory to the list of BOs to | |
56467ebf | 133 | * validate for command submission. |
d38ceaf9 | 134 | */ |
56467ebf CK |
135 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
136 | struct list_head *validated, | |
137 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 138 | { |
67003a15 | 139 | entry->robj = vm->root.bo; |
56467ebf | 140 | entry->priority = 0; |
67003a15 | 141 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 142 | entry->tv.shared = true; |
2f568dbd | 143 | entry->user_pages = NULL; |
56467ebf CK |
144 | list_add(&entry->tv.head, validated); |
145 | } | |
d38ceaf9 | 146 | |
670fecc8 CK |
147 | /** |
148 | * amdgpu_vm_validate_layer - validate a single page table level | |
149 | * | |
150 | * @parent: parent page table level | |
151 | * @validate: callback to do the validation | |
152 | * @param: parameter for the validation callback | |
153 | * | |
154 | * Validate the page table BOs on command submission if neccessary. | |
155 | */ | |
156 | static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent, | |
157 | int (*validate)(void *, struct amdgpu_bo *), | |
158 | void *param) | |
159 | { | |
160 | unsigned i; | |
161 | int r; | |
162 | ||
163 | if (!parent->entries) | |
164 | return 0; | |
165 | ||
166 | for (i = 0; i <= parent->last_entry_used; ++i) { | |
167 | struct amdgpu_vm_pt *entry = &parent->entries[i]; | |
168 | ||
169 | if (!entry->bo) | |
170 | continue; | |
171 | ||
172 | r = validate(param, entry->bo); | |
173 | if (r) | |
174 | return r; | |
175 | ||
176 | /* | |
177 | * Recurse into the sub directory. This is harmless because we | |
178 | * have only a maximum of 5 layers. | |
179 | */ | |
180 | r = amdgpu_vm_validate_level(entry, validate, param); | |
181 | if (r) | |
182 | return r; | |
183 | } | |
184 | ||
185 | return r; | |
186 | } | |
187 | ||
56467ebf | 188 | /** |
f7da30d9 | 189 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
56467ebf | 190 | * |
5a712a87 | 191 | * @adev: amdgpu device pointer |
56467ebf | 192 | * @vm: vm providing the BOs |
f7da30d9 CK |
193 | * @validate: callback to do the validation |
194 | * @param: parameter for the validation callback | |
d38ceaf9 | 195 | * |
f7da30d9 | 196 | * Validate the page table BOs on command submission if neccessary. |
d38ceaf9 | 197 | */ |
f7da30d9 CK |
198 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
199 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
200 | void *param) | |
d38ceaf9 | 201 | { |
5a712a87 | 202 | uint64_t num_evictions; |
d38ceaf9 | 203 | |
5a712a87 CK |
204 | /* We only need to validate the page tables |
205 | * if they aren't already valid. | |
206 | */ | |
207 | num_evictions = atomic64_read(&adev->num_evictions); | |
208 | if (num_evictions == vm->last_eviction_counter) | |
f7da30d9 | 209 | return 0; |
5a712a87 | 210 | |
670fecc8 | 211 | return amdgpu_vm_validate_level(&vm->root, validate, param); |
eceb8a15 CK |
212 | } |
213 | ||
214 | /** | |
d711e139 | 215 | * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail |
eceb8a15 CK |
216 | * |
217 | * @adev: amdgpu device instance | |
218 | * @vm: vm providing the BOs | |
219 | * | |
220 | * Move the PT BOs to the tail of the LRU. | |
221 | */ | |
d711e139 | 222 | static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent) |
eceb8a15 | 223 | { |
eceb8a15 CK |
224 | unsigned i; |
225 | ||
d711e139 CK |
226 | if (!parent->entries) |
227 | return; | |
eceb8a15 | 228 | |
d711e139 CK |
229 | for (i = 0; i <= parent->last_entry_used; ++i) { |
230 | struct amdgpu_vm_pt *entry = &parent->entries[i]; | |
231 | ||
232 | if (!entry->bo) | |
eceb8a15 CK |
233 | continue; |
234 | ||
d711e139 CK |
235 | ttm_bo_move_to_lru_tail(&entry->bo->tbo); |
236 | amdgpu_vm_move_level_in_lru(entry); | |
eceb8a15 | 237 | } |
d711e139 CK |
238 | } |
239 | ||
240 | /** | |
241 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
242 | * | |
243 | * @adev: amdgpu device instance | |
244 | * @vm: vm providing the BOs | |
245 | * | |
246 | * Move the PT BOs to the tail of the LRU. | |
247 | */ | |
248 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
249 | struct amdgpu_vm *vm) | |
250 | { | |
251 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
252 | ||
253 | spin_lock(&glob->lru_lock); | |
254 | amdgpu_vm_move_level_in_lru(&vm->root); | |
eceb8a15 | 255 | spin_unlock(&glob->lru_lock); |
d38ceaf9 AD |
256 | } |
257 | ||
f566ceb1 CK |
258 | /** |
259 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels | |
260 | * | |
261 | * @adev: amdgpu_device pointer | |
262 | * @vm: requested vm | |
263 | * @saddr: start of the address range | |
264 | * @eaddr: end of the address range | |
265 | * | |
266 | * Make sure the page directories and page tables are allocated | |
267 | */ | |
268 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
269 | struct amdgpu_vm *vm, | |
270 | struct amdgpu_vm_pt *parent, | |
271 | uint64_t saddr, uint64_t eaddr, | |
272 | unsigned level) | |
273 | { | |
274 | unsigned shift = (adev->vm_manager.num_level - level) * | |
36b32a68 | 275 | adev->vm_manager.block_size; |
f566ceb1 CK |
276 | unsigned pt_idx, from, to; |
277 | int r; | |
278 | ||
279 | if (!parent->entries) { | |
280 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
281 | ||
282 | parent->entries = drm_calloc_large(num_entries, | |
283 | sizeof(struct amdgpu_vm_pt)); | |
284 | if (!parent->entries) | |
285 | return -ENOMEM; | |
286 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
287 | } | |
288 | ||
1866bac8 FK |
289 | from = saddr >> shift; |
290 | to = eaddr >> shift; | |
291 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
292 | to >= amdgpu_vm_num_entries(adev, level)) | |
293 | return -EINVAL; | |
f566ceb1 CK |
294 | |
295 | if (to > parent->last_entry_used) | |
296 | parent->last_entry_used = to; | |
297 | ||
298 | ++level; | |
1866bac8 FK |
299 | saddr = saddr & ((1 << shift) - 1); |
300 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 CK |
301 | |
302 | /* walk over the address space and allocate the page tables */ | |
303 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
304 | struct reservation_object *resv = vm->root.bo->tbo.resv; | |
305 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
306 | struct amdgpu_bo *pt; | |
307 | ||
308 | if (!entry->bo) { | |
309 | r = amdgpu_bo_create(adev, | |
310 | amdgpu_vm_bo_size(adev, level), | |
311 | AMDGPU_GPU_PAGE_SIZE, true, | |
312 | AMDGPU_GEM_DOMAIN_VRAM, | |
313 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
314 | AMDGPU_GEM_CREATE_SHADOW | | |
315 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
316 | AMDGPU_GEM_CREATE_VRAM_CLEARED, | |
317 | NULL, resv, &pt); | |
318 | if (r) | |
319 | return r; | |
320 | ||
321 | /* Keep a reference to the root directory to avoid | |
322 | * freeing them up in the wrong order. | |
323 | */ | |
324 | pt->parent = amdgpu_bo_ref(vm->root.bo); | |
325 | ||
326 | entry->bo = pt; | |
327 | entry->addr = 0; | |
328 | } | |
329 | ||
330 | if (level < adev->vm_manager.num_level) { | |
1866bac8 FK |
331 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
332 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
333 | ((1 << shift) - 1); | |
334 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
335 | sub_eaddr, level); | |
f566ceb1 CK |
336 | if (r) |
337 | return r; | |
338 | } | |
339 | } | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
663e4577 CK |
344 | /** |
345 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
346 | * | |
347 | * @adev: amdgpu_device pointer | |
348 | * @vm: VM to allocate page tables for | |
349 | * @saddr: Start address which needs to be allocated | |
350 | * @size: Size from start address we need. | |
351 | * | |
352 | * Make sure the page tables are allocated. | |
353 | */ | |
354 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
355 | struct amdgpu_vm *vm, | |
356 | uint64_t saddr, uint64_t size) | |
357 | { | |
22770e5a | 358 | uint64_t last_pfn; |
663e4577 | 359 | uint64_t eaddr; |
663e4577 CK |
360 | |
361 | /* validate the parameters */ | |
362 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
363 | return -EINVAL; | |
364 | ||
365 | eaddr = saddr + size - 1; | |
366 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
367 | if (last_pfn >= adev->vm_manager.max_pfn) { | |
22770e5a | 368 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", |
663e4577 CK |
369 | last_pfn, adev->vm_manager.max_pfn); |
370 | return -EINVAL; | |
371 | } | |
372 | ||
373 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
374 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
375 | ||
f566ceb1 | 376 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); |
663e4577 CK |
377 | } |
378 | ||
641e9400 CK |
379 | /** |
380 | * amdgpu_vm_had_gpu_reset - check if reset occured since last use | |
381 | * | |
382 | * @adev: amdgpu_device pointer | |
383 | * @id: VMID structure | |
384 | * | |
385 | * Check if GPU reset occured since last use of the VMID. | |
386 | */ | |
387 | static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev, | |
388 | struct amdgpu_vm_id *id) | |
192b7dcb CZ |
389 | { |
390 | return id->current_gpu_reset_count != | |
641e9400 | 391 | atomic_read(&adev->gpu_reset_counter); |
192b7dcb CZ |
392 | } |
393 | ||
d38ceaf9 AD |
394 | /** |
395 | * amdgpu_vm_grab_id - allocate the next free VMID | |
396 | * | |
d38ceaf9 | 397 | * @vm: vm to allocate id for |
7f8a5290 CK |
398 | * @ring: ring we want to submit job to |
399 | * @sync: sync object where we add dependencies | |
94dd0a4a | 400 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 401 | * |
7f8a5290 | 402 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 403 | */ |
7f8a5290 | 404 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
f54d1867 | 405 | struct amdgpu_sync *sync, struct dma_fence *fence, |
fd53be30 | 406 | struct amdgpu_job *job) |
d38ceaf9 | 407 | { |
d38ceaf9 | 408 | struct amdgpu_device *adev = ring->adev; |
2e819849 | 409 | unsigned vmhub = ring->funcs->vmhub; |
7645670d | 410 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
090b767e | 411 | uint64_t fence_context = adev->fence_context + ring->idx; |
f54d1867 | 412 | struct dma_fence *updates = sync->last_vm_update; |
8d76001e | 413 | struct amdgpu_vm_id *id, *idle; |
f54d1867 | 414 | struct dma_fence **fences; |
1fbb2e92 CK |
415 | unsigned i; |
416 | int r = 0; | |
417 | ||
7645670d | 418 | fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); |
1fbb2e92 CK |
419 | if (!fences) |
420 | return -ENOMEM; | |
d38ceaf9 | 421 | |
7645670d | 422 | mutex_lock(&id_mgr->lock); |
94dd0a4a | 423 | |
36fd7c5c | 424 | /* Check if we have an idle VMID */ |
1fbb2e92 | 425 | i = 0; |
7645670d | 426 | list_for_each_entry(idle, &id_mgr->ids_lru, list) { |
1fbb2e92 CK |
427 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
428 | if (!fences[i]) | |
36fd7c5c | 429 | break; |
1fbb2e92 | 430 | ++i; |
36fd7c5c CK |
431 | } |
432 | ||
1fbb2e92 | 433 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
7645670d | 434 | if (&idle->list == &id_mgr->ids_lru) { |
1fbb2e92 CK |
435 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
436 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
f54d1867 | 437 | struct dma_fence_array *array; |
1fbb2e92 CK |
438 | unsigned j; |
439 | ||
440 | for (j = 0; j < i; ++j) | |
f54d1867 | 441 | dma_fence_get(fences[j]); |
1fbb2e92 | 442 | |
f54d1867 | 443 | array = dma_fence_array_create(i, fences, fence_context, |
1fbb2e92 CK |
444 | seqno, true); |
445 | if (!array) { | |
446 | for (j = 0; j < i; ++j) | |
f54d1867 | 447 | dma_fence_put(fences[j]); |
1fbb2e92 CK |
448 | kfree(fences); |
449 | r = -ENOMEM; | |
450 | goto error; | |
451 | } | |
452 | ||
453 | ||
454 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
f54d1867 | 455 | dma_fence_put(&array->base); |
1fbb2e92 CK |
456 | if (r) |
457 | goto error; | |
458 | ||
7645670d | 459 | mutex_unlock(&id_mgr->lock); |
1fbb2e92 CK |
460 | return 0; |
461 | ||
462 | } | |
463 | kfree(fences); | |
464 | ||
87c910d8 | 465 | job->vm_needs_flush = false; |
1fbb2e92 | 466 | /* Check if we can use a VMID already assigned to this VM */ |
7645670d | 467 | list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) { |
f54d1867 | 468 | struct dma_fence *flushed; |
87c910d8 | 469 | bool needs_flush = false; |
1fbb2e92 | 470 | |
1fbb2e92 | 471 | /* Check all the prerequisites to using this VMID */ |
641e9400 | 472 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
6adb0513 | 473 | continue; |
1fbb2e92 CK |
474 | |
475 | if (atomic64_read(&id->owner) != vm->client_id) | |
476 | continue; | |
477 | ||
fd53be30 | 478 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
479 | continue; |
480 | ||
87c910d8 CK |
481 | if (!id->last_flush || |
482 | (id->last_flush->context != fence_context && | |
483 | !dma_fence_is_signaled(id->last_flush))) | |
484 | needs_flush = true; | |
1fbb2e92 CK |
485 | |
486 | flushed = id->flushed_updates; | |
87c910d8 CK |
487 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) |
488 | needs_flush = true; | |
489 | ||
490 | /* Concurrent flushes are only possible starting with Vega10 */ | |
491 | if (adev->asic_type < CHIP_VEGA10 && needs_flush) | |
1fbb2e92 CK |
492 | continue; |
493 | ||
3dab83be CK |
494 | /* Good we can use this VMID. Remember this submission as |
495 | * user of the VMID. | |
496 | */ | |
1fbb2e92 CK |
497 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
498 | if (r) | |
499 | goto error; | |
8d76001e | 500 | |
87c910d8 CK |
501 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) { |
502 | dma_fence_put(id->flushed_updates); | |
503 | id->flushed_updates = dma_fence_get(updates); | |
504 | } | |
8d76001e | 505 | |
87c910d8 CK |
506 | if (needs_flush) |
507 | goto needs_flush; | |
508 | else | |
509 | goto no_flush_needed; | |
8d76001e | 510 | |
4f618e73 | 511 | }; |
8d76001e | 512 | |
1fbb2e92 CK |
513 | /* Still no ID to use? Then use the idle one found earlier */ |
514 | id = idle; | |
8e9fbeb5 | 515 | |
1fbb2e92 CK |
516 | /* Remember this submission as user of the VMID */ |
517 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
518 | if (r) |
519 | goto error; | |
94dd0a4a | 520 | |
87c910d8 | 521 | id->pd_gpu_addr = job->vm_pd_addr; |
f54d1867 CW |
522 | dma_fence_put(id->flushed_updates); |
523 | id->flushed_updates = dma_fence_get(updates); | |
b46b8a87 | 524 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
0ea54b9b | 525 | atomic64_set(&id->owner, vm->client_id); |
d38ceaf9 | 526 | |
87c910d8 CK |
527 | needs_flush: |
528 | job->vm_needs_flush = true; | |
529 | dma_fence_put(id->last_flush); | |
530 | id->last_flush = NULL; | |
531 | ||
532 | no_flush_needed: | |
533 | list_move_tail(&id->list, &id_mgr->ids_lru); | |
534 | ||
7645670d | 535 | job->vm_id = id - id_mgr->ids; |
c5296d14 | 536 | trace_amdgpu_vm_grab_id(vm, ring, job); |
832a902f CK |
537 | |
538 | error: | |
7645670d | 539 | mutex_unlock(&id_mgr->lock); |
a9a78b32 | 540 | return r; |
d38ceaf9 AD |
541 | } |
542 | ||
93dcc37d AD |
543 | static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) |
544 | { | |
545 | struct amdgpu_device *adev = ring->adev; | |
a1255107 | 546 | const struct amdgpu_ip_block *ip_block; |
93dcc37d | 547 | |
21cd942e | 548 | if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) |
93dcc37d AD |
549 | /* only compute rings */ |
550 | return false; | |
551 | ||
552 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
553 | if (!ip_block) | |
554 | return false; | |
555 | ||
a1255107 | 556 | if (ip_block->version->major <= 7) { |
93dcc37d AD |
557 | /* gfx7 has no workaround */ |
558 | return true; | |
a1255107 | 559 | } else if (ip_block->version->major == 8) { |
93dcc37d AD |
560 | if (adev->gfx.mec_fw_version >= 673) |
561 | /* gfx8 is fixed in MEC firmware 673 */ | |
562 | return false; | |
563 | else | |
564 | return true; | |
565 | } | |
566 | return false; | |
567 | } | |
568 | ||
e60f8db5 AX |
569 | static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) |
570 | { | |
571 | u64 addr = mc_addr; | |
572 | ||
f75e237c CK |
573 | if (adev->gart.gart_funcs->adjust_mc_addr) |
574 | addr = adev->gart.gart_funcs->adjust_mc_addr(adev, addr); | |
e60f8db5 AX |
575 | |
576 | return addr; | |
577 | } | |
578 | ||
d38ceaf9 AD |
579 | /** |
580 | * amdgpu_vm_flush - hardware flush the vm | |
581 | * | |
582 | * @ring: ring to use for flush | |
cffadc83 | 583 | * @vm_id: vmid number to use |
4ff37a83 | 584 | * @pd_addr: address of the page directory |
d38ceaf9 | 585 | * |
4ff37a83 | 586 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 587 | */ |
fd53be30 | 588 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) |
d38ceaf9 | 589 | { |
971fe9a9 | 590 | struct amdgpu_device *adev = ring->adev; |
7645670d CK |
591 | unsigned vmhub = ring->funcs->vmhub; |
592 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
593 | struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id]; | |
d564a06e | 594 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
595 | id->gds_base != job->gds_base || |
596 | id->gds_size != job->gds_size || | |
597 | id->gws_base != job->gws_base || | |
598 | id->gws_size != job->gws_size || | |
599 | id->oa_base != job->oa_base || | |
600 | id->oa_size != job->oa_size); | |
f7d015b9 CK |
601 | bool vm_flush_needed = job->vm_needs_flush || |
602 | amdgpu_vm_ring_has_compute_vm_bug(ring); | |
c0e51931 | 603 | unsigned patch_offset = 0; |
41d9eb2c | 604 | int r; |
d564a06e | 605 | |
f7d015b9 CK |
606 | if (amdgpu_vm_had_gpu_reset(adev, id)) { |
607 | gds_switch_needed = true; | |
608 | vm_flush_needed = true; | |
609 | } | |
971fe9a9 | 610 | |
f7d015b9 CK |
611 | if (!vm_flush_needed && !gds_switch_needed) |
612 | return 0; | |
41d9eb2c | 613 | |
c0e51931 CK |
614 | if (ring->funcs->init_cond_exec) |
615 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 616 | |
30514dec | 617 | if (ring->funcs->emit_pipeline_sync && !job->need_pipeline_sync) |
c0e51931 | 618 | amdgpu_ring_emit_pipeline_sync(ring); |
3dab83be | 619 | |
f7d015b9 | 620 | if (ring->funcs->emit_vm_flush && vm_flush_needed) { |
c0e51931 CK |
621 | u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr); |
622 | struct dma_fence *fence; | |
41d9eb2c | 623 | |
5f1bcf51 | 624 | trace_amdgpu_vm_flush(ring, job->vm_id, pd_addr); |
c0e51931 | 625 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr); |
e9d672b2 | 626 | |
c0e51931 CK |
627 | r = amdgpu_fence_emit(ring, &fence); |
628 | if (r) | |
629 | return r; | |
e9d672b2 | 630 | |
7645670d | 631 | mutex_lock(&id_mgr->lock); |
c0e51931 CK |
632 | dma_fence_put(id->last_flush); |
633 | id->last_flush = fence; | |
7645670d | 634 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 635 | } |
e9d672b2 | 636 | |
c0e51931 CK |
637 | if (gds_switch_needed) { |
638 | id->gds_base = job->gds_base; | |
639 | id->gds_size = job->gds_size; | |
640 | id->gws_base = job->gws_base; | |
641 | id->gws_size = job->gws_size; | |
642 | id->oa_base = job->oa_base; | |
643 | id->oa_size = job->oa_size; | |
644 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base, | |
645 | job->gds_size, job->gws_base, | |
646 | job->gws_size, job->oa_base, | |
647 | job->oa_size); | |
648 | } | |
649 | ||
650 | if (ring->funcs->patch_cond_exec) | |
651 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
652 | ||
653 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
654 | if (ring->funcs->emit_switch_buffer) { | |
655 | amdgpu_ring_emit_switch_buffer(ring); | |
656 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 657 | } |
41d9eb2c | 658 | return 0; |
971fe9a9 CK |
659 | } |
660 | ||
661 | /** | |
662 | * amdgpu_vm_reset_id - reset VMID to zero | |
663 | * | |
664 | * @adev: amdgpu device structure | |
665 | * @vm_id: vmid number to use | |
666 | * | |
667 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
668 | */ | |
7645670d CK |
669 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
670 | unsigned vmid) | |
971fe9a9 | 671 | { |
7645670d CK |
672 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
673 | struct amdgpu_vm_id *id = &id_mgr->ids[vmid]; | |
bcb1ba35 CK |
674 | |
675 | id->gds_base = 0; | |
676 | id->gds_size = 0; | |
677 | id->gws_base = 0; | |
678 | id->gws_size = 0; | |
679 | id->oa_base = 0; | |
680 | id->oa_size = 0; | |
d38ceaf9 AD |
681 | } |
682 | ||
d38ceaf9 AD |
683 | /** |
684 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
685 | * | |
686 | * @vm: requested vm | |
687 | * @bo: requested buffer object | |
688 | * | |
8843dbbb | 689 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
690 | * Search inside the @bos vm list for the requested vm |
691 | * Returns the found bo_va or NULL if none is found | |
692 | * | |
693 | * Object has to be reserved! | |
694 | */ | |
695 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
696 | struct amdgpu_bo *bo) | |
697 | { | |
698 | struct amdgpu_bo_va *bo_va; | |
699 | ||
700 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
701 | if (bo_va->vm == vm) { | |
702 | return bo_va; | |
703 | } | |
704 | } | |
705 | return NULL; | |
706 | } | |
707 | ||
708 | /** | |
afef8b8f | 709 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 710 | * |
29efc4f5 | 711 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
712 | * @pe: addr of the page entry |
713 | * @addr: dst addr to write into pe | |
714 | * @count: number of page entries to update | |
715 | * @incr: increase next addr by incr bytes | |
716 | * @flags: hw access flags | |
d38ceaf9 AD |
717 | * |
718 | * Traces the parameters and calls the right asic functions | |
719 | * to setup the page table using the DMA. | |
720 | */ | |
afef8b8f CK |
721 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
722 | uint64_t pe, uint64_t addr, | |
723 | unsigned count, uint32_t incr, | |
6b777607 | 724 | uint64_t flags) |
d38ceaf9 | 725 | { |
ec2f05f0 | 726 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 727 | |
afef8b8f | 728 | if (count < 3) { |
de9ea7bd CK |
729 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
730 | addr | flags, count, incr); | |
d38ceaf9 AD |
731 | |
732 | } else { | |
27c5f36f | 733 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
734 | count, incr, flags); |
735 | } | |
736 | } | |
737 | ||
afef8b8f CK |
738 | /** |
739 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
740 | * | |
741 | * @params: see amdgpu_pte_update_params definition | |
742 | * @pe: addr of the page entry | |
743 | * @addr: dst addr to write into pe | |
744 | * @count: number of page entries to update | |
745 | * @incr: increase next addr by incr bytes | |
746 | * @flags: hw access flags | |
747 | * | |
748 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
749 | */ | |
750 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
751 | uint64_t pe, uint64_t addr, | |
752 | unsigned count, uint32_t incr, | |
6b777607 | 753 | uint64_t flags) |
afef8b8f | 754 | { |
ec2f05f0 | 755 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 756 | |
ec2f05f0 CK |
757 | |
758 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
759 | ||
760 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
761 | } |
762 | ||
d38ceaf9 | 763 | /** |
b07c9d2a | 764 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 765 | * |
b07c9d2a | 766 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
767 | * @addr: the unmapped addr |
768 | * | |
769 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 770 | * to and return the pointer for the page table entry. |
d38ceaf9 | 771 | */ |
de9ea7bd | 772 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
773 | { |
774 | uint64_t result; | |
775 | ||
de9ea7bd CK |
776 | /* page table offset */ |
777 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 778 | |
de9ea7bd CK |
779 | /* in case cpu page size != gpu page size*/ |
780 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 781 | |
b07c9d2a | 782 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
783 | |
784 | return result; | |
785 | } | |
786 | ||
f8991bab | 787 | /* |
194d2161 | 788 | * amdgpu_vm_update_level - update a single level in the hierarchy |
f8991bab CK |
789 | * |
790 | * @adev: amdgpu_device pointer | |
791 | * @vm: requested vm | |
194d2161 | 792 | * @parent: parent directory |
f8991bab | 793 | * |
194d2161 | 794 | * Makes sure all entries in @parent are up to date. |
f8991bab CK |
795 | * Returns 0 for success, error for failure. |
796 | */ | |
194d2161 CK |
797 | static int amdgpu_vm_update_level(struct amdgpu_device *adev, |
798 | struct amdgpu_vm *vm, | |
799 | struct amdgpu_vm_pt *parent, | |
800 | unsigned level) | |
d38ceaf9 | 801 | { |
f8991bab | 802 | struct amdgpu_bo *shadow; |
2d55e45a | 803 | struct amdgpu_ring *ring; |
f8991bab | 804 | uint64_t pd_addr, shadow_addr; |
194d2161 | 805 | uint32_t incr = amdgpu_vm_bo_size(adev, level + 1); |
f8991bab | 806 | uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; |
d38ceaf9 | 807 | unsigned count = 0, pt_idx, ndw; |
d71518b5 | 808 | struct amdgpu_job *job; |
29efc4f5 | 809 | struct amdgpu_pte_update_params params; |
f54d1867 | 810 | struct dma_fence *fence = NULL; |
d5fc5e82 | 811 | |
d38ceaf9 AD |
812 | int r; |
813 | ||
194d2161 CK |
814 | if (!parent->entries) |
815 | return 0; | |
2d55e45a CK |
816 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
817 | ||
d38ceaf9 AD |
818 | /* padding, etc. */ |
819 | ndw = 64; | |
820 | ||
821 | /* assume the worst case */ | |
194d2161 | 822 | ndw += parent->last_entry_used * 6; |
d38ceaf9 | 823 | |
194d2161 CK |
824 | pd_addr = amdgpu_bo_gpu_offset(parent->bo); |
825 | ||
826 | shadow = parent->bo->shadow; | |
f8991bab CK |
827 | if (shadow) { |
828 | r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); | |
829 | if (r) | |
830 | return r; | |
831 | shadow_addr = amdgpu_bo_gpu_offset(shadow); | |
832 | ndw *= 2; | |
833 | } else { | |
834 | shadow_addr = 0; | |
835 | } | |
836 | ||
d71518b5 CK |
837 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
838 | if (r) | |
d38ceaf9 | 839 | return r; |
d71518b5 | 840 | |
27c5f36f CK |
841 | memset(¶ms, 0, sizeof(params)); |
842 | params.adev = adev; | |
29efc4f5 | 843 | params.ib = &job->ibs[0]; |
d38ceaf9 | 844 | |
194d2161 CK |
845 | /* walk over the address space and update the directory */ |
846 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
847 | struct amdgpu_bo *bo = parent->entries[pt_idx].bo; | |
d38ceaf9 AD |
848 | uint64_t pde, pt; |
849 | ||
850 | if (bo == NULL) | |
851 | continue; | |
852 | ||
0fc8683e | 853 | if (bo->shadow) { |
f8991bab | 854 | struct amdgpu_bo *pt_shadow = bo->shadow; |
0fc8683e | 855 | |
f8991bab CK |
856 | r = amdgpu_ttm_bind(&pt_shadow->tbo, |
857 | &pt_shadow->tbo.mem); | |
0fc8683e CK |
858 | if (r) |
859 | return r; | |
860 | } | |
861 | ||
d38ceaf9 | 862 | pt = amdgpu_bo_gpu_offset(bo); |
194d2161 | 863 | if (parent->entries[pt_idx].addr == pt) |
f8991bab CK |
864 | continue; |
865 | ||
194d2161 | 866 | parent->entries[pt_idx].addr = pt; |
d38ceaf9 AD |
867 | |
868 | pde = pd_addr + pt_idx * 8; | |
869 | if (((last_pde + 8 * count) != pde) || | |
96105e53 CK |
870 | ((last_pt + incr * count) != pt) || |
871 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
d38ceaf9 AD |
872 | |
873 | if (count) { | |
e60f8db5 AX |
874 | uint64_t pt_addr = |
875 | amdgpu_vm_adjust_mc_addr(adev, last_pt); | |
876 | ||
f8991bab CK |
877 | if (shadow) |
878 | amdgpu_vm_do_set_ptes(¶ms, | |
879 | last_shadow, | |
e60f8db5 | 880 | pt_addr, count, |
f8991bab CK |
881 | incr, |
882 | AMDGPU_PTE_VALID); | |
883 | ||
afef8b8f | 884 | amdgpu_vm_do_set_ptes(¶ms, last_pde, |
e60f8db5 | 885 | pt_addr, count, incr, |
afef8b8f | 886 | AMDGPU_PTE_VALID); |
d38ceaf9 AD |
887 | } |
888 | ||
889 | count = 1; | |
890 | last_pde = pde; | |
f8991bab | 891 | last_shadow = shadow_addr + pt_idx * 8; |
d38ceaf9 AD |
892 | last_pt = pt; |
893 | } else { | |
894 | ++count; | |
895 | } | |
896 | } | |
897 | ||
f8991bab | 898 | if (count) { |
e60f8db5 AX |
899 | uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt); |
900 | ||
67003a15 | 901 | if (vm->root.bo->shadow) |
e60f8db5 | 902 | amdgpu_vm_do_set_ptes(¶ms, last_shadow, pt_addr, |
f8991bab CK |
903 | count, incr, AMDGPU_PTE_VALID); |
904 | ||
e60f8db5 | 905 | amdgpu_vm_do_set_ptes(¶ms, last_pde, pt_addr, |
afef8b8f | 906 | count, incr, AMDGPU_PTE_VALID); |
f8991bab | 907 | } |
d38ceaf9 | 908 | |
f8991bab CK |
909 | if (params.ib->length_dw == 0) { |
910 | amdgpu_job_free(job); | |
194d2161 CK |
911 | } else { |
912 | amdgpu_ring_pad_ib(ring, params.ib); | |
913 | amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv, | |
e86f9cee | 914 | AMDGPU_FENCE_OWNER_VM); |
194d2161 CK |
915 | if (shadow) |
916 | amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv, | |
917 | AMDGPU_FENCE_OWNER_VM); | |
05906dec | 918 | |
194d2161 CK |
919 | WARN_ON(params.ib->length_dw > ndw); |
920 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
921 | AMDGPU_FENCE_OWNER_VM, &fence); | |
922 | if (r) | |
923 | goto error_free; | |
924 | ||
925 | amdgpu_bo_fence(parent->bo, fence, true); | |
926 | dma_fence_put(vm->last_dir_update); | |
927 | vm->last_dir_update = dma_fence_get(fence); | |
928 | dma_fence_put(fence); | |
929 | } | |
930 | /* | |
931 | * Recurse into the subdirectories. This recursion is harmless because | |
932 | * we only have a maximum of 5 layers. | |
933 | */ | |
934 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
935 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
936 | ||
937 | if (!entry->bo) | |
938 | continue; | |
d5fc5e82 | 939 | |
194d2161 CK |
940 | r = amdgpu_vm_update_level(adev, vm, entry, level + 1); |
941 | if (r) | |
942 | return r; | |
943 | } | |
d38ceaf9 AD |
944 | |
945 | return 0; | |
d5fc5e82 CZ |
946 | |
947 | error_free: | |
d71518b5 | 948 | amdgpu_job_free(job); |
4af9f07c | 949 | return r; |
d38ceaf9 AD |
950 | } |
951 | ||
194d2161 CK |
952 | /* |
953 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
954 | * | |
955 | * @adev: amdgpu_device pointer | |
956 | * @vm: requested vm | |
957 | * | |
958 | * Makes sure all directories are up to date. | |
959 | * Returns 0 for success, error for failure. | |
960 | */ | |
961 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
962 | struct amdgpu_vm *vm) | |
963 | { | |
964 | return amdgpu_vm_update_level(adev, vm, &vm->root, 0); | |
965 | } | |
966 | ||
4e2cb640 CK |
967 | /** |
968 | * amdgpu_vm_find_pt - find the page table for an address | |
969 | * | |
970 | * @p: see amdgpu_pte_update_params definition | |
971 | * @addr: virtual address in question | |
972 | * | |
973 | * Find the page table BO for a virtual address, return NULL when none found. | |
974 | */ | |
975 | static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p, | |
976 | uint64_t addr) | |
977 | { | |
978 | struct amdgpu_vm_pt *entry = &p->vm->root; | |
979 | unsigned idx, level = p->adev->vm_manager.num_level; | |
980 | ||
981 | while (entry->entries) { | |
36b32a68 | 982 | idx = addr >> (p->adev->vm_manager.block_size * level--); |
4e2cb640 CK |
983 | idx %= amdgpu_bo_size(entry->bo) / 8; |
984 | entry = &entry->entries[idx]; | |
985 | } | |
986 | ||
987 | if (level) | |
988 | return NULL; | |
989 | ||
990 | return entry->bo; | |
991 | } | |
992 | ||
d38ceaf9 AD |
993 | /** |
994 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
995 | * | |
29efc4f5 | 996 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
997 | * @vm: requested vm |
998 | * @start: start of GPU address range | |
999 | * @end: end of GPU address range | |
677131a1 | 1000 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1001 | * @flags: mapping flags |
1002 | * | |
8843dbbb | 1003 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 1004 | */ |
27c5f36f | 1005 | static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1006 | uint64_t start, uint64_t end, |
6b777607 | 1007 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1008 | { |
36b32a68 ZJ |
1009 | struct amdgpu_device *adev = params->adev; |
1010 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1011 | |
92696dd5 | 1012 | uint64_t cur_pe_start, cur_nptes, cur_dst; |
677131a1 | 1013 | uint64_t addr; /* next GPU address to be updated */ |
21718497 AX |
1014 | struct amdgpu_bo *pt; |
1015 | unsigned nptes; /* next number of ptes to be updated */ | |
1016 | uint64_t next_pe_start; | |
1017 | ||
1018 | /* initialize the variables */ | |
1019 | addr = start; | |
4e2cb640 | 1020 | pt = amdgpu_vm_get_pt(params, addr); |
1866bac8 FK |
1021 | if (!pt) { |
1022 | pr_err("PT not found, aborting update_ptes\n"); | |
4e2cb640 | 1023 | return; |
1866bac8 | 1024 | } |
4e2cb640 | 1025 | |
4c7e8855 CZ |
1026 | if (params->shadow) { |
1027 | if (!pt->shadow) | |
1028 | return; | |
914b4dce | 1029 | pt = pt->shadow; |
4c7e8855 | 1030 | } |
21718497 AX |
1031 | if ((addr & ~mask) == (end & ~mask)) |
1032 | nptes = end - addr; | |
1033 | else | |
36b32a68 | 1034 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
21718497 AX |
1035 | |
1036 | cur_pe_start = amdgpu_bo_gpu_offset(pt); | |
1037 | cur_pe_start += (addr & mask) * 8; | |
92696dd5 | 1038 | cur_nptes = nptes; |
21718497 AX |
1039 | cur_dst = dst; |
1040 | ||
1041 | /* for next ptb*/ | |
1042 | addr += nptes; | |
1043 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
d38ceaf9 AD |
1044 | |
1045 | /* walk over the address space and update the page tables */ | |
21718497 | 1046 | while (addr < end) { |
4e2cb640 | 1047 | pt = amdgpu_vm_get_pt(params, addr); |
1866bac8 FK |
1048 | if (!pt) { |
1049 | pr_err("PT not found, aborting update_ptes\n"); | |
4e2cb640 | 1050 | return; |
1866bac8 | 1051 | } |
4e2cb640 | 1052 | |
4c7e8855 CZ |
1053 | if (params->shadow) { |
1054 | if (!pt->shadow) | |
1055 | return; | |
914b4dce | 1056 | pt = pt->shadow; |
4c7e8855 | 1057 | } |
d38ceaf9 AD |
1058 | |
1059 | if ((addr & ~mask) == (end & ~mask)) | |
1060 | nptes = end - addr; | |
1061 | else | |
36b32a68 | 1062 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1063 | |
677131a1 AX |
1064 | next_pe_start = amdgpu_bo_gpu_offset(pt); |
1065 | next_pe_start += (addr & mask) * 8; | |
d38ceaf9 | 1066 | |
96105e53 CK |
1067 | if ((cur_pe_start + 8 * cur_nptes) == next_pe_start && |
1068 | ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
3a6f8e0c | 1069 | /* The next ptb is consecutive to current ptb. |
afef8b8f | 1070 | * Don't call the update function now. |
3a6f8e0c AX |
1071 | * Will update two ptbs together in future. |
1072 | */ | |
92696dd5 | 1073 | cur_nptes += nptes; |
3a6f8e0c | 1074 | } else { |
afef8b8f CK |
1075 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
1076 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 | 1077 | |
677131a1 | 1078 | cur_pe_start = next_pe_start; |
92696dd5 | 1079 | cur_nptes = nptes; |
677131a1 | 1080 | cur_dst = dst; |
d38ceaf9 AD |
1081 | } |
1082 | ||
21718497 | 1083 | /* for next ptb*/ |
d38ceaf9 AD |
1084 | addr += nptes; |
1085 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
1086 | } | |
1087 | ||
afef8b8f CK |
1088 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
1089 | AMDGPU_GPU_PAGE_SIZE, flags); | |
92696dd5 CK |
1090 | } |
1091 | ||
1092 | /* | |
1093 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1094 | * | |
1095 | * @params: see amdgpu_pte_update_params definition | |
1096 | * @vm: requested vm | |
1097 | * @start: first PTE to handle | |
1098 | * @end: last PTE to handle | |
1099 | * @dst: addr those PTEs should point to | |
1100 | * @flags: hw mapping flags | |
1101 | */ | |
1102 | static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, | |
92696dd5 | 1103 | uint64_t start, uint64_t end, |
6b777607 | 1104 | uint64_t dst, uint64_t flags) |
92696dd5 CK |
1105 | { |
1106 | /** | |
1107 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1108 | * field in the PTE. When this field is set to a non-zero value, page | |
1109 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1110 | * flags are considered valid for all PTEs within the fragment range | |
1111 | * and corresponding mappings are assumed to be physically contiguous. | |
1112 | * | |
1113 | * The L1 TLB can store a single PTE for the whole fragment, | |
1114 | * significantly increasing the space available for translation | |
1115 | * caching. This leads to large improvements in throughput when the | |
1116 | * TLB is under pressure. | |
1117 | * | |
1118 | * The L2 TLB distributes small and large fragments into two | |
1119 | * asymmetric partitions. The large fragment cache is significantly | |
1120 | * larger. Thus, we try to use large fragments wherever possible. | |
1121 | * Userspace can support this by aligning virtual base address and | |
1122 | * allocation size to the fragment size. | |
1123 | */ | |
1124 | ||
8036617e CK |
1125 | /* SI and newer are optimized for 64KB */ |
1126 | uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG); | |
1127 | uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG; | |
92696dd5 CK |
1128 | |
1129 | uint64_t frag_start = ALIGN(start, frag_align); | |
1130 | uint64_t frag_end = end & ~(frag_align - 1); | |
1131 | ||
1132 | /* system pages are non continuously */ | |
b7fc2cbd | 1133 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
92696dd5 CK |
1134 | (frag_start >= frag_end)) { |
1135 | ||
49ac8a24 | 1136 | amdgpu_vm_update_ptes(params, start, end, dst, flags); |
92696dd5 CK |
1137 | return; |
1138 | } | |
1139 | ||
1140 | /* handle the 4K area at the beginning */ | |
1141 | if (start != frag_start) { | |
49ac8a24 | 1142 | amdgpu_vm_update_ptes(params, start, frag_start, |
92696dd5 CK |
1143 | dst, flags); |
1144 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; | |
1145 | } | |
1146 | ||
1147 | /* handle the area in the middle */ | |
49ac8a24 | 1148 | amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, |
8036617e | 1149 | flags | frag_flags); |
92696dd5 CK |
1150 | |
1151 | /* handle the 4K area at the end */ | |
1152 | if (frag_end != end) { | |
1153 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
49ac8a24 | 1154 | amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); |
92696dd5 | 1155 | } |
d38ceaf9 AD |
1156 | } |
1157 | ||
d38ceaf9 AD |
1158 | /** |
1159 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1160 | * | |
1161 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1162 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
1163 | * @src: address where to copy page table entries from |
1164 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 1165 | * @vm: requested vm |
a14faa65 CK |
1166 | * @start: start of mapped range |
1167 | * @last: last mapped entry | |
1168 | * @flags: flags for the entries | |
d38ceaf9 | 1169 | * @addr: addr to set the area to |
d38ceaf9 AD |
1170 | * @fence: optional resulting fence |
1171 | * | |
a14faa65 | 1172 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 1173 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
1174 | */ |
1175 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1176 | struct dma_fence *exclusive, |
fa3ab3c7 CK |
1177 | uint64_t src, |
1178 | dma_addr_t *pages_addr, | |
d38ceaf9 | 1179 | struct amdgpu_vm *vm, |
a14faa65 | 1180 | uint64_t start, uint64_t last, |
6b777607 | 1181 | uint64_t flags, uint64_t addr, |
f54d1867 | 1182 | struct dma_fence **fence) |
d38ceaf9 | 1183 | { |
2d55e45a | 1184 | struct amdgpu_ring *ring; |
a1e08d3b | 1185 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1186 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1187 | struct amdgpu_job *job; |
29efc4f5 | 1188 | struct amdgpu_pte_update_params params; |
f54d1867 | 1189 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1190 | int r; |
1191 | ||
afef8b8f CK |
1192 | memset(¶ms, 0, sizeof(params)); |
1193 | params.adev = adev; | |
49ac8a24 | 1194 | params.vm = vm; |
afef8b8f CK |
1195 | params.src = src; |
1196 | ||
2d55e45a | 1197 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 1198 | |
a1e08d3b CK |
1199 | /* sync to everything on unmapping */ |
1200 | if (!(flags & AMDGPU_PTE_VALID)) | |
1201 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1202 | ||
a14faa65 | 1203 | nptes = last - start + 1; |
d38ceaf9 AD |
1204 | |
1205 | /* | |
1206 | * reserve space for one command every (1 << BLOCK_SIZE) | |
1207 | * entries or 2k dwords (whatever is smaller) | |
1208 | */ | |
36b32a68 | 1209 | ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1; |
d38ceaf9 AD |
1210 | |
1211 | /* padding, etc. */ | |
1212 | ndw = 64; | |
1213 | ||
b0456f93 | 1214 | if (src) { |
d38ceaf9 AD |
1215 | /* only copy commands needed */ |
1216 | ndw += ncmds * 7; | |
1217 | ||
afef8b8f CK |
1218 | params.func = amdgpu_vm_do_copy_ptes; |
1219 | ||
b0456f93 CK |
1220 | } else if (pages_addr) { |
1221 | /* copy commands needed */ | |
1222 | ndw += ncmds * 7; | |
d38ceaf9 | 1223 | |
b0456f93 | 1224 | /* and also PTEs */ |
d38ceaf9 AD |
1225 | ndw += nptes * 2; |
1226 | ||
afef8b8f CK |
1227 | params.func = amdgpu_vm_do_copy_ptes; |
1228 | ||
d38ceaf9 AD |
1229 | } else { |
1230 | /* set page commands needed */ | |
1231 | ndw += ncmds * 10; | |
1232 | ||
1233 | /* two extra commands for begin/end of fragment */ | |
1234 | ndw += 2 * 10; | |
afef8b8f CK |
1235 | |
1236 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1237 | } |
1238 | ||
d71518b5 CK |
1239 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1240 | if (r) | |
d38ceaf9 | 1241 | return r; |
d71518b5 | 1242 | |
29efc4f5 | 1243 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1244 | |
b0456f93 CK |
1245 | if (!src && pages_addr) { |
1246 | uint64_t *pte; | |
1247 | unsigned i; | |
1248 | ||
1249 | /* Put the PTEs at the end of the IB. */ | |
1250 | i = ndw - nptes * 2; | |
1251 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1252 | params.src = job->ibs->gpu_addr + i * 4; | |
1253 | ||
1254 | for (i = 0; i < nptes; ++i) { | |
1255 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1256 | AMDGPU_GPU_PAGE_SIZE); | |
1257 | pte[i] |= flags; | |
1258 | } | |
d7a4ac66 | 1259 | addr = 0; |
b0456f93 CK |
1260 | } |
1261 | ||
3cabaa54 CK |
1262 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
1263 | if (r) | |
1264 | goto error_free; | |
1265 | ||
67003a15 | 1266 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv, |
a1e08d3b CK |
1267 | owner); |
1268 | if (r) | |
1269 | goto error_free; | |
d38ceaf9 | 1270 | |
67003a15 | 1271 | r = reservation_object_reserve_shared(vm->root.bo->tbo.resv); |
a1e08d3b CK |
1272 | if (r) |
1273 | goto error_free; | |
1274 | ||
4c7e8855 | 1275 | params.shadow = true; |
49ac8a24 | 1276 | amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
4c7e8855 | 1277 | params.shadow = false; |
49ac8a24 | 1278 | amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
d38ceaf9 | 1279 | |
29efc4f5 CK |
1280 | amdgpu_ring_pad_ib(ring, params.ib); |
1281 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1282 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1283 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1284 | if (r) |
1285 | goto error_free; | |
d38ceaf9 | 1286 | |
67003a15 | 1287 | amdgpu_bo_fence(vm->root.bo, f, true); |
284710fa CK |
1288 | dma_fence_put(*fence); |
1289 | *fence = f; | |
d38ceaf9 | 1290 | return 0; |
d5fc5e82 CZ |
1291 | |
1292 | error_free: | |
d71518b5 | 1293 | amdgpu_job_free(job); |
4af9f07c | 1294 | return r; |
d38ceaf9 AD |
1295 | } |
1296 | ||
a14faa65 CK |
1297 | /** |
1298 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1299 | * | |
1300 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1301 | * @exclusive: fence we need to sync to |
8358dcee CK |
1302 | * @gtt_flags: flags as they are used for GTT |
1303 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
1304 | * @vm: requested vm |
1305 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1306 | * @flags: HW flags for the mapping |
63e0ba40 | 1307 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1308 | * @fence: optional resulting fence |
1309 | * | |
1310 | * Split the mapping into smaller chunks so that each update fits | |
1311 | * into a SDMA IB. | |
1312 | * Returns 0 for success, -EINVAL for failure. | |
1313 | */ | |
1314 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1315 | struct dma_fence *exclusive, |
6b777607 | 1316 | uint64_t gtt_flags, |
8358dcee | 1317 | dma_addr_t *pages_addr, |
a14faa65 CK |
1318 | struct amdgpu_vm *vm, |
1319 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1320 | uint64_t flags, |
63e0ba40 | 1321 | struct drm_mm_node *nodes, |
f54d1867 | 1322 | struct dma_fence **fence) |
a14faa65 | 1323 | { |
a9f87f64 | 1324 | uint64_t pfn, src = 0, start = mapping->start; |
a14faa65 CK |
1325 | int r; |
1326 | ||
1327 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1328 | * but in case of something, we filter the flags in first place | |
1329 | */ | |
1330 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1331 | flags &= ~AMDGPU_PTE_READABLE; | |
1332 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1333 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1334 | ||
15b31c59 AX |
1335 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1336 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1337 | ||
b0fd18b0 AX |
1338 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1339 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1340 | ||
d0766e98 ZJ |
1341 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1342 | (adev->asic_type >= CHIP_VEGA10)) { | |
1343 | flags |= AMDGPU_PTE_PRT; | |
1344 | flags &= ~AMDGPU_PTE_VALID; | |
1345 | } | |
1346 | ||
a14faa65 CK |
1347 | trace_amdgpu_vm_bo_update(mapping); |
1348 | ||
63e0ba40 CK |
1349 | pfn = mapping->offset >> PAGE_SHIFT; |
1350 | if (nodes) { | |
1351 | while (pfn >= nodes->size) { | |
1352 | pfn -= nodes->size; | |
1353 | ++nodes; | |
1354 | } | |
fa3ab3c7 | 1355 | } |
a14faa65 | 1356 | |
63e0ba40 CK |
1357 | do { |
1358 | uint64_t max_entries; | |
1359 | uint64_t addr, last; | |
a14faa65 | 1360 | |
63e0ba40 CK |
1361 | if (nodes) { |
1362 | addr = nodes->start << PAGE_SHIFT; | |
1363 | max_entries = (nodes->size - pfn) * | |
1364 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1365 | } else { | |
1366 | addr = 0; | |
1367 | max_entries = S64_MAX; | |
1368 | } | |
a14faa65 | 1369 | |
63e0ba40 CK |
1370 | if (pages_addr) { |
1371 | if (flags == gtt_flags) | |
1372 | src = adev->gart.table_addr + | |
1373 | (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8; | |
1374 | else | |
1375 | max_entries = min(max_entries, 16ull * 1024ull); | |
1376 | addr = 0; | |
1377 | } else if (flags & AMDGPU_PTE_VALID) { | |
1378 | addr += adev->vm_manager.vram_base_offset; | |
1379 | } | |
1380 | addr += pfn << PAGE_SHIFT; | |
1381 | ||
a9f87f64 | 1382 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
3cabaa54 CK |
1383 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1384 | src, pages_addr, vm, | |
a14faa65 CK |
1385 | start, last, flags, addr, |
1386 | fence); | |
1387 | if (r) | |
1388 | return r; | |
1389 | ||
63e0ba40 CK |
1390 | pfn += last - start + 1; |
1391 | if (nodes && nodes->size == pfn) { | |
1392 | pfn = 0; | |
1393 | ++nodes; | |
1394 | } | |
a14faa65 | 1395 | start = last + 1; |
63e0ba40 | 1396 | |
a9f87f64 | 1397 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1398 | |
1399 | return 0; | |
1400 | } | |
1401 | ||
d38ceaf9 AD |
1402 | /** |
1403 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1404 | * | |
1405 | * @adev: amdgpu_device pointer | |
1406 | * @bo_va: requested BO and VM object | |
99e124f4 | 1407 | * @clear: if true clear the entries |
d38ceaf9 AD |
1408 | * |
1409 | * Fill in the page table entries for @bo_va. | |
1410 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1411 | */ |
1412 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1413 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1414 | bool clear) |
d38ceaf9 AD |
1415 | { |
1416 | struct amdgpu_vm *vm = bo_va->vm; | |
1417 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1418 | dma_addr_t *pages_addr = NULL; |
6b777607 | 1419 | uint64_t gtt_flags, flags; |
99e124f4 | 1420 | struct ttm_mem_reg *mem; |
63e0ba40 | 1421 | struct drm_mm_node *nodes; |
f54d1867 | 1422 | struct dma_fence *exclusive; |
d38ceaf9 AD |
1423 | int r; |
1424 | ||
a5f6b5b1 | 1425 | if (clear || !bo_va->bo) { |
99e124f4 | 1426 | mem = NULL; |
63e0ba40 | 1427 | nodes = NULL; |
99e124f4 CK |
1428 | exclusive = NULL; |
1429 | } else { | |
8358dcee CK |
1430 | struct ttm_dma_tt *ttm; |
1431 | ||
99e124f4 | 1432 | mem = &bo_va->bo->tbo.mem; |
63e0ba40 CK |
1433 | nodes = mem->mm_node; |
1434 | if (mem->mem_type == TTM_PL_TT) { | |
8358dcee CK |
1435 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1436 | ttm_dma_tt, ttm); | |
1437 | pages_addr = ttm->dma_address; | |
9ab21462 | 1438 | } |
3cabaa54 | 1439 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); |
d38ceaf9 AD |
1440 | } |
1441 | ||
a5f6b5b1 CK |
1442 | if (bo_va->bo) { |
1443 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); | |
1444 | gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && | |
1445 | adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? | |
1446 | flags : 0; | |
1447 | } else { | |
1448 | flags = 0x0; | |
1449 | gtt_flags = ~0x0; | |
1450 | } | |
d38ceaf9 | 1451 | |
7fc11959 CK |
1452 | spin_lock(&vm->status_lock); |
1453 | if (!list_empty(&bo_va->vm_status)) | |
1454 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1455 | spin_unlock(&vm->status_lock); | |
1456 | ||
1457 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1458 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1459 | gtt_flags, pages_addr, vm, | |
63e0ba40 | 1460 | mapping, flags, nodes, |
8358dcee | 1461 | &bo_va->last_pt_update); |
d38ceaf9 AD |
1462 | if (r) |
1463 | return r; | |
1464 | } | |
1465 | ||
d6c10f6b CK |
1466 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1467 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1468 | trace_amdgpu_vm_bo_mapping(mapping); | |
1469 | ||
1470 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1471 | trace_amdgpu_vm_bo_mapping(mapping); | |
1472 | } | |
1473 | ||
d38ceaf9 | 1474 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1475 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1476 | list_del_init(&bo_va->vm_status); |
99e124f4 | 1477 | if (clear) |
7fc11959 | 1478 | list_add(&bo_va->vm_status, &vm->cleared); |
d38ceaf9 AD |
1479 | spin_unlock(&vm->status_lock); |
1480 | ||
1481 | return 0; | |
1482 | } | |
1483 | ||
284710fa CK |
1484 | /** |
1485 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1486 | */ | |
1487 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1488 | { | |
1489 | unsigned long flags; | |
1490 | bool enable; | |
1491 | ||
1492 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1493 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
284710fa CK |
1494 | adev->gart.gart_funcs->set_prt(adev, enable); |
1495 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
1496 | } | |
1497 | ||
451bc8eb | 1498 | /** |
4388fc2a | 1499 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1500 | */ |
1501 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1502 | { | |
4388fc2a CK |
1503 | if (!adev->gart.gart_funcs->set_prt) |
1504 | return; | |
1505 | ||
451bc8eb CK |
1506 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1507 | amdgpu_vm_update_prt_state(adev); | |
1508 | } | |
1509 | ||
0b15f2fc CK |
1510 | /** |
1511 | * amdgpu_vm_prt_put - drop a PRT user | |
1512 | */ | |
1513 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1514 | { | |
451bc8eb | 1515 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1516 | amdgpu_vm_update_prt_state(adev); |
1517 | } | |
1518 | ||
284710fa | 1519 | /** |
451bc8eb | 1520 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1521 | */ |
1522 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1523 | { | |
1524 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1525 | ||
0b15f2fc | 1526 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1527 | kfree(cb); |
1528 | } | |
1529 | ||
451bc8eb CK |
1530 | /** |
1531 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1532 | */ | |
1533 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1534 | struct dma_fence *fence) | |
1535 | { | |
4388fc2a | 1536 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1537 | |
4388fc2a CK |
1538 | if (!adev->gart.gart_funcs->set_prt) |
1539 | return; | |
1540 | ||
1541 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1542 | if (!cb) { |
1543 | /* Last resort when we are OOM */ | |
1544 | if (fence) | |
1545 | dma_fence_wait(fence, false); | |
1546 | ||
486a68f5 | 1547 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1548 | } else { |
1549 | cb->adev = adev; | |
1550 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1551 | amdgpu_vm_prt_cb)) | |
1552 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1553 | } | |
1554 | } | |
1555 | ||
284710fa CK |
1556 | /** |
1557 | * amdgpu_vm_free_mapping - free a mapping | |
1558 | * | |
1559 | * @adev: amdgpu_device pointer | |
1560 | * @vm: requested vm | |
1561 | * @mapping: mapping to be freed | |
1562 | * @fence: fence of the unmap operation | |
1563 | * | |
1564 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1565 | */ | |
1566 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1567 | struct amdgpu_vm *vm, | |
1568 | struct amdgpu_bo_va_mapping *mapping, | |
1569 | struct dma_fence *fence) | |
1570 | { | |
451bc8eb CK |
1571 | if (mapping->flags & AMDGPU_PTE_PRT) |
1572 | amdgpu_vm_add_prt_cb(adev, fence); | |
1573 | kfree(mapping); | |
1574 | } | |
284710fa | 1575 | |
451bc8eb CK |
1576 | /** |
1577 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1578 | * | |
1579 | * @adev: amdgpu_device pointer | |
1580 | * @vm: requested vm | |
1581 | * | |
1582 | * Register a cleanup callback to disable PRT support after VM dies. | |
1583 | */ | |
1584 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1585 | { | |
67003a15 | 1586 | struct reservation_object *resv = vm->root.bo->tbo.resv; |
451bc8eb CK |
1587 | struct dma_fence *excl, **shared; |
1588 | unsigned i, shared_count; | |
1589 | int r; | |
0b15f2fc | 1590 | |
451bc8eb CK |
1591 | r = reservation_object_get_fences_rcu(resv, &excl, |
1592 | &shared_count, &shared); | |
1593 | if (r) { | |
1594 | /* Not enough memory to grab the fence list, as last resort | |
1595 | * block for all the fences to complete. | |
1596 | */ | |
1597 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1598 | MAX_SCHEDULE_TIMEOUT); | |
1599 | return; | |
284710fa | 1600 | } |
451bc8eb CK |
1601 | |
1602 | /* Add a callback for each fence in the reservation object */ | |
1603 | amdgpu_vm_prt_get(adev); | |
1604 | amdgpu_vm_add_prt_cb(adev, excl); | |
1605 | ||
1606 | for (i = 0; i < shared_count; ++i) { | |
1607 | amdgpu_vm_prt_get(adev); | |
1608 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1609 | } | |
1610 | ||
1611 | kfree(shared); | |
284710fa CK |
1612 | } |
1613 | ||
d38ceaf9 AD |
1614 | /** |
1615 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1616 | * | |
1617 | * @adev: amdgpu_device pointer | |
1618 | * @vm: requested vm | |
f3467818 NH |
1619 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1620 | * or if an error occurred) | |
d38ceaf9 AD |
1621 | * |
1622 | * Make sure all freed BOs are cleared in the PT. | |
1623 | * Returns 0 for success. | |
1624 | * | |
1625 | * PTs have to be reserved and mutex must be locked! | |
1626 | */ | |
1627 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1628 | struct amdgpu_vm *vm, |
1629 | struct dma_fence **fence) | |
d38ceaf9 AD |
1630 | { |
1631 | struct amdgpu_bo_va_mapping *mapping; | |
f3467818 | 1632 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1633 | int r; |
1634 | ||
1635 | while (!list_empty(&vm->freed)) { | |
1636 | mapping = list_first_entry(&vm->freed, | |
1637 | struct amdgpu_bo_va_mapping, list); | |
1638 | list_del(&mapping->list); | |
e17841b9 | 1639 | |
fc6aa33d CK |
1640 | r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm, |
1641 | mapping->start, mapping->last, | |
1642 | 0, 0, &f); | |
f3467818 | 1643 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1644 | if (r) { |
f3467818 | 1645 | dma_fence_put(f); |
d38ceaf9 | 1646 | return r; |
284710fa | 1647 | } |
f3467818 | 1648 | } |
d38ceaf9 | 1649 | |
f3467818 NH |
1650 | if (fence && f) { |
1651 | dma_fence_put(*fence); | |
1652 | *fence = f; | |
1653 | } else { | |
1654 | dma_fence_put(f); | |
d38ceaf9 | 1655 | } |
f3467818 | 1656 | |
d38ceaf9 AD |
1657 | return 0; |
1658 | ||
1659 | } | |
1660 | ||
1661 | /** | |
1662 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1663 | * | |
1664 | * @adev: amdgpu_device pointer | |
1665 | * @vm: requested vm | |
1666 | * | |
1667 | * Make sure all invalidated BOs are cleared in the PT. | |
1668 | * Returns 0 for success. | |
1669 | * | |
1670 | * PTs have to be reserved and mutex must be locked! | |
1671 | */ | |
1672 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1673 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1674 | { |
cfe2c978 | 1675 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1676 | int r = 0; |
d38ceaf9 AD |
1677 | |
1678 | spin_lock(&vm->status_lock); | |
1679 | while (!list_empty(&vm->invalidated)) { | |
1680 | bo_va = list_first_entry(&vm->invalidated, | |
1681 | struct amdgpu_bo_va, vm_status); | |
1682 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1683 | |
99e124f4 | 1684 | r = amdgpu_vm_bo_update(adev, bo_va, true); |
d38ceaf9 AD |
1685 | if (r) |
1686 | return r; | |
1687 | ||
1688 | spin_lock(&vm->status_lock); | |
1689 | } | |
1690 | spin_unlock(&vm->status_lock); | |
1691 | ||
cfe2c978 | 1692 | if (bo_va) |
bb1e38a4 | 1693 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1694 | |
1695 | return r; | |
d38ceaf9 AD |
1696 | } |
1697 | ||
1698 | /** | |
1699 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1700 | * | |
1701 | * @adev: amdgpu_device pointer | |
1702 | * @vm: requested vm | |
1703 | * @bo: amdgpu buffer object | |
1704 | * | |
8843dbbb | 1705 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1706 | * Add @bo to the list of bos associated with the vm |
1707 | * Returns newly added bo_va or NULL for failure | |
1708 | * | |
1709 | * Object has to be reserved! | |
1710 | */ | |
1711 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1712 | struct amdgpu_vm *vm, | |
1713 | struct amdgpu_bo *bo) | |
1714 | { | |
1715 | struct amdgpu_bo_va *bo_va; | |
1716 | ||
1717 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1718 | if (bo_va == NULL) { | |
1719 | return NULL; | |
1720 | } | |
1721 | bo_va->vm = vm; | |
1722 | bo_va->bo = bo; | |
d38ceaf9 AD |
1723 | bo_va->ref_count = 1; |
1724 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1725 | INIT_LIST_HEAD(&bo_va->valids); |
1726 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1727 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1728 | |
a5f6b5b1 CK |
1729 | if (bo) |
1730 | list_add_tail(&bo_va->bo_list, &bo->va); | |
d38ceaf9 AD |
1731 | |
1732 | return bo_va; | |
1733 | } | |
1734 | ||
1735 | /** | |
1736 | * amdgpu_vm_bo_map - map bo inside a vm | |
1737 | * | |
1738 | * @adev: amdgpu_device pointer | |
1739 | * @bo_va: bo_va to store the address | |
1740 | * @saddr: where to map the BO | |
1741 | * @offset: requested offset in the BO | |
1742 | * @flags: attributes of pages (read/write/valid/etc.) | |
1743 | * | |
1744 | * Add a mapping of the BO at the specefied addr into the VM. | |
1745 | * Returns 0 for success, error for failure. | |
1746 | * | |
49b02b18 | 1747 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1748 | */ |
1749 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1750 | struct amdgpu_bo_va *bo_va, | |
1751 | uint64_t saddr, uint64_t offset, | |
268c3001 | 1752 | uint64_t size, uint64_t flags) |
d38ceaf9 | 1753 | { |
a9f87f64 | 1754 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
d38ceaf9 | 1755 | struct amdgpu_vm *vm = bo_va->vm; |
d38ceaf9 | 1756 | uint64_t eaddr; |
d38ceaf9 | 1757 | |
0be52de9 CK |
1758 | /* validate the parameters */ |
1759 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1760 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1761 | return -EINVAL; |
0be52de9 | 1762 | |
d38ceaf9 | 1763 | /* make sure object fit at this offset */ |
005ae95e | 1764 | eaddr = saddr + size - 1; |
a5f6b5b1 CK |
1765 | if (saddr >= eaddr || |
1766 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
d38ceaf9 | 1767 | return -EINVAL; |
d38ceaf9 | 1768 | |
d38ceaf9 AD |
1769 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1770 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1771 | ||
a9f87f64 CK |
1772 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
1773 | if (tmp) { | |
d38ceaf9 AD |
1774 | /* bo and tmp overlap, invalid addr */ |
1775 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
a9f87f64 CK |
1776 | "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr, |
1777 | tmp->start, tmp->last + 1); | |
663e4577 | 1778 | return -EINVAL; |
d38ceaf9 AD |
1779 | } |
1780 | ||
1781 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
1782 | if (!mapping) |
1783 | return -ENOMEM; | |
d38ceaf9 AD |
1784 | |
1785 | INIT_LIST_HEAD(&mapping->list); | |
a9f87f64 CK |
1786 | mapping->start = saddr; |
1787 | mapping->last = eaddr; | |
d38ceaf9 AD |
1788 | mapping->offset = offset; |
1789 | mapping->flags = flags; | |
1790 | ||
7fc11959 | 1791 | list_add(&mapping->list, &bo_va->invalids); |
a9f87f64 | 1792 | amdgpu_vm_it_insert(mapping, &vm->va); |
80f95c57 CK |
1793 | |
1794 | if (flags & AMDGPU_PTE_PRT) | |
1795 | amdgpu_vm_prt_get(adev); | |
1796 | ||
1797 | return 0; | |
1798 | } | |
1799 | ||
1800 | /** | |
1801 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
1802 | * | |
1803 | * @adev: amdgpu_device pointer | |
1804 | * @bo_va: bo_va to store the address | |
1805 | * @saddr: where to map the BO | |
1806 | * @offset: requested offset in the BO | |
1807 | * @flags: attributes of pages (read/write/valid/etc.) | |
1808 | * | |
1809 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
1810 | * mappings as we do so. | |
1811 | * Returns 0 for success, error for failure. | |
1812 | * | |
1813 | * Object has to be reserved and unreserved outside! | |
1814 | */ | |
1815 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
1816 | struct amdgpu_bo_va *bo_va, | |
1817 | uint64_t saddr, uint64_t offset, | |
1818 | uint64_t size, uint64_t flags) | |
1819 | { | |
1820 | struct amdgpu_bo_va_mapping *mapping; | |
1821 | struct amdgpu_vm *vm = bo_va->vm; | |
1822 | uint64_t eaddr; | |
1823 | int r; | |
1824 | ||
1825 | /* validate the parameters */ | |
1826 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
1827 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
1828 | return -EINVAL; | |
1829 | ||
1830 | /* make sure object fit at this offset */ | |
1831 | eaddr = saddr + size - 1; | |
1832 | if (saddr >= eaddr || | |
1833 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
1834 | return -EINVAL; | |
1835 | ||
1836 | /* Allocate all the needed memory */ | |
1837 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1838 | if (!mapping) | |
1839 | return -ENOMEM; | |
1840 | ||
1841 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size); | |
1842 | if (r) { | |
1843 | kfree(mapping); | |
1844 | return r; | |
1845 | } | |
1846 | ||
1847 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
1848 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1849 | ||
a9f87f64 CK |
1850 | mapping->start = saddr; |
1851 | mapping->last = eaddr; | |
80f95c57 CK |
1852 | mapping->offset = offset; |
1853 | mapping->flags = flags; | |
1854 | ||
1855 | list_add(&mapping->list, &bo_va->invalids); | |
a9f87f64 | 1856 | amdgpu_vm_it_insert(mapping, &vm->va); |
d38ceaf9 | 1857 | |
4388fc2a CK |
1858 | if (flags & AMDGPU_PTE_PRT) |
1859 | amdgpu_vm_prt_get(adev); | |
1860 | ||
d38ceaf9 | 1861 | return 0; |
d38ceaf9 AD |
1862 | } |
1863 | ||
1864 | /** | |
1865 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1866 | * | |
1867 | * @adev: amdgpu_device pointer | |
1868 | * @bo_va: bo_va to remove the address from | |
1869 | * @saddr: where to the BO is mapped | |
1870 | * | |
1871 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1872 | * Returns 0 for success, error for failure. | |
1873 | * | |
49b02b18 | 1874 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1875 | */ |
1876 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1877 | struct amdgpu_bo_va *bo_va, | |
1878 | uint64_t saddr) | |
1879 | { | |
1880 | struct amdgpu_bo_va_mapping *mapping; | |
1881 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1882 | bool valid = true; |
d38ceaf9 | 1883 | |
6c7fc503 | 1884 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1885 | |
7fc11959 | 1886 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 1887 | if (mapping->start == saddr) |
d38ceaf9 AD |
1888 | break; |
1889 | } | |
1890 | ||
7fc11959 CK |
1891 | if (&mapping->list == &bo_va->valids) { |
1892 | valid = false; | |
1893 | ||
1894 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 1895 | if (mapping->start == saddr) |
7fc11959 CK |
1896 | break; |
1897 | } | |
1898 | ||
32b41ac2 | 1899 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1900 | return -ENOENT; |
d38ceaf9 | 1901 | } |
32b41ac2 | 1902 | |
d38ceaf9 | 1903 | list_del(&mapping->list); |
a9f87f64 | 1904 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 1905 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1906 | |
e17841b9 | 1907 | if (valid) |
d38ceaf9 | 1908 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1909 | else |
284710fa CK |
1910 | amdgpu_vm_free_mapping(adev, vm, mapping, |
1911 | bo_va->last_pt_update); | |
d38ceaf9 AD |
1912 | |
1913 | return 0; | |
1914 | } | |
1915 | ||
dc54d3d1 CK |
1916 | /** |
1917 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
1918 | * | |
1919 | * @adev: amdgpu_device pointer | |
1920 | * @vm: VM structure to use | |
1921 | * @saddr: start of the range | |
1922 | * @size: size of the range | |
1923 | * | |
1924 | * Remove all mappings in a range, split them as appropriate. | |
1925 | * Returns 0 for success, error for failure. | |
1926 | */ | |
1927 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
1928 | struct amdgpu_vm *vm, | |
1929 | uint64_t saddr, uint64_t size) | |
1930 | { | |
1931 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
1932 | LIST_HEAD(removed); |
1933 | uint64_t eaddr; | |
1934 | ||
1935 | eaddr = saddr + size - 1; | |
1936 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
1937 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1938 | ||
1939 | /* Allocate all the needed memory */ | |
1940 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
1941 | if (!before) | |
1942 | return -ENOMEM; | |
27f6d610 | 1943 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
1944 | |
1945 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
1946 | if (!after) { | |
1947 | kfree(before); | |
1948 | return -ENOMEM; | |
1949 | } | |
27f6d610 | 1950 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
1951 | |
1952 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
1953 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
1954 | while (tmp) { | |
dc54d3d1 | 1955 | /* Remember mapping split at the start */ |
a9f87f64 CK |
1956 | if (tmp->start < saddr) { |
1957 | before->start = tmp->start; | |
1958 | before->last = saddr - 1; | |
dc54d3d1 CK |
1959 | before->offset = tmp->offset; |
1960 | before->flags = tmp->flags; | |
1961 | list_add(&before->list, &tmp->list); | |
1962 | } | |
1963 | ||
1964 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
1965 | if (tmp->last > eaddr) { |
1966 | after->start = eaddr + 1; | |
1967 | after->last = tmp->last; | |
dc54d3d1 | 1968 | after->offset = tmp->offset; |
a9f87f64 | 1969 | after->offset += after->start - tmp->start; |
dc54d3d1 CK |
1970 | after->flags = tmp->flags; |
1971 | list_add(&after->list, &tmp->list); | |
1972 | } | |
1973 | ||
1974 | list_del(&tmp->list); | |
1975 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
1976 | |
1977 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
1978 | } |
1979 | ||
1980 | /* And free them up */ | |
1981 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 1982 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
1983 | list_del(&tmp->list); |
1984 | ||
a9f87f64 CK |
1985 | if (tmp->start < saddr) |
1986 | tmp->start = saddr; | |
1987 | if (tmp->last > eaddr) | |
1988 | tmp->last = eaddr; | |
dc54d3d1 CK |
1989 | |
1990 | list_add(&tmp->list, &vm->freed); | |
1991 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
1992 | } | |
1993 | ||
27f6d610 JZ |
1994 | /* Insert partial mapping before the range */ |
1995 | if (!list_empty(&before->list)) { | |
a9f87f64 | 1996 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
1997 | if (before->flags & AMDGPU_PTE_PRT) |
1998 | amdgpu_vm_prt_get(adev); | |
1999 | } else { | |
2000 | kfree(before); | |
2001 | } | |
2002 | ||
2003 | /* Insert partial mapping after the range */ | |
27f6d610 | 2004 | if (!list_empty(&after->list)) { |
a9f87f64 | 2005 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2006 | if (after->flags & AMDGPU_PTE_PRT) |
2007 | amdgpu_vm_prt_get(adev); | |
2008 | } else { | |
2009 | kfree(after); | |
2010 | } | |
2011 | ||
2012 | return 0; | |
2013 | } | |
2014 | ||
d38ceaf9 AD |
2015 | /** |
2016 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2017 | * | |
2018 | * @adev: amdgpu_device pointer | |
2019 | * @bo_va: requested bo_va | |
2020 | * | |
8843dbbb | 2021 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2022 | * |
2023 | * Object have to be reserved! | |
2024 | */ | |
2025 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2026 | struct amdgpu_bo_va *bo_va) | |
2027 | { | |
2028 | struct amdgpu_bo_va_mapping *mapping, *next; | |
2029 | struct amdgpu_vm *vm = bo_va->vm; | |
2030 | ||
2031 | list_del(&bo_va->bo_list); | |
2032 | ||
d38ceaf9 AD |
2033 | spin_lock(&vm->status_lock); |
2034 | list_del(&bo_va->vm_status); | |
2035 | spin_unlock(&vm->status_lock); | |
2036 | ||
7fc11959 | 2037 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2038 | list_del(&mapping->list); |
a9f87f64 | 2039 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2040 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2041 | list_add(&mapping->list, &vm->freed); |
2042 | } | |
2043 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2044 | list_del(&mapping->list); | |
a9f87f64 | 2045 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2046 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2047 | bo_va->last_pt_update); | |
d38ceaf9 | 2048 | } |
32b41ac2 | 2049 | |
f54d1867 | 2050 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2051 | kfree(bo_va); |
d38ceaf9 AD |
2052 | } |
2053 | ||
2054 | /** | |
2055 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2056 | * | |
2057 | * @adev: amdgpu_device pointer | |
2058 | * @vm: requested vm | |
2059 | * @bo: amdgpu buffer object | |
2060 | * | |
8843dbbb | 2061 | * Mark @bo as invalid. |
d38ceaf9 AD |
2062 | */ |
2063 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
2064 | struct amdgpu_bo *bo) | |
2065 | { | |
2066 | struct amdgpu_bo_va *bo_va; | |
2067 | ||
2068 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
2069 | spin_lock(&bo_va->vm->status_lock); |
2070 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 2071 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 2072 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
2073 | } |
2074 | } | |
2075 | ||
bab4fee7 JZ |
2076 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2077 | { | |
2078 | /* Total bits covered by PD + PTs */ | |
2079 | unsigned bits = ilog2(vm_size) + 18; | |
2080 | ||
2081 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2082 | Above that split equal between PD and PTs */ | |
2083 | if (vm_size <= 8) | |
2084 | return (bits - 9); | |
2085 | else | |
2086 | return ((bits + 3) / 2); | |
2087 | } | |
2088 | ||
2089 | /** | |
2090 | * amdgpu_vm_adjust_size - adjust vm size and block size | |
2091 | * | |
2092 | * @adev: amdgpu_device pointer | |
2093 | * @vm_size: the default vm size if it's set auto | |
2094 | */ | |
2095 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) | |
2096 | { | |
2097 | /* adjust vm size firstly */ | |
2098 | if (amdgpu_vm_size == -1) | |
2099 | adev->vm_manager.vm_size = vm_size; | |
2100 | else | |
2101 | adev->vm_manager.vm_size = amdgpu_vm_size; | |
2102 | ||
2103 | /* block size depends on vm size */ | |
2104 | if (amdgpu_vm_block_size == -1) | |
2105 | adev->vm_manager.block_size = | |
2106 | amdgpu_vm_get_block_size(adev->vm_manager.vm_size); | |
2107 | else | |
2108 | adev->vm_manager.block_size = amdgpu_vm_block_size; | |
2109 | ||
2110 | DRM_INFO("vm size is %llu GB, block size is %u-bit\n", | |
2111 | adev->vm_manager.vm_size, adev->vm_manager.block_size); | |
2112 | } | |
2113 | ||
d38ceaf9 AD |
2114 | /** |
2115 | * amdgpu_vm_init - initialize a vm instance | |
2116 | * | |
2117 | * @adev: amdgpu_device pointer | |
2118 | * @vm: requested vm | |
2119 | * | |
8843dbbb | 2120 | * Init @vm fields. |
d38ceaf9 AD |
2121 | */ |
2122 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2123 | { | |
2124 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
36b32a68 | 2125 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2126 | unsigned ring_instance; |
2127 | struct amdgpu_ring *ring; | |
2bd9ccfa | 2128 | struct amd_sched_rq *rq; |
4f618e73 | 2129 | int r; |
d38ceaf9 | 2130 | |
d38ceaf9 | 2131 | vm->va = RB_ROOT; |
031e2983 | 2132 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
d38ceaf9 AD |
2133 | spin_lock_init(&vm->status_lock); |
2134 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 2135 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 2136 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2137 | |
2bd9ccfa | 2138 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2139 | |
2140 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2141 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2142 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
2143 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
2144 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
2145 | rq, amdgpu_sched_jobs); | |
2146 | if (r) | |
f566ceb1 | 2147 | return r; |
2bd9ccfa | 2148 | |
a24960f3 | 2149 | vm->last_dir_update = NULL; |
05906dec | 2150 | |
f566ceb1 | 2151 | r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, |
857d913d | 2152 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f | 2153 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
03f48dd5 | 2154 | AMDGPU_GEM_CREATE_SHADOW | |
617859e0 CK |
2155 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
2156 | AMDGPU_GEM_CREATE_VRAM_CLEARED, | |
67003a15 | 2157 | NULL, NULL, &vm->root.bo); |
d38ceaf9 | 2158 | if (r) |
2bd9ccfa CK |
2159 | goto error_free_sched_entity; |
2160 | ||
67003a15 | 2161 | r = amdgpu_bo_reserve(vm->root.bo, false); |
2bd9ccfa | 2162 | if (r) |
67003a15 | 2163 | goto error_free_root; |
2bd9ccfa | 2164 | |
5a712a87 | 2165 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
67003a15 | 2166 | amdgpu_bo_unreserve(vm->root.bo); |
d38ceaf9 AD |
2167 | |
2168 | return 0; | |
2bd9ccfa | 2169 | |
67003a15 CK |
2170 | error_free_root: |
2171 | amdgpu_bo_unref(&vm->root.bo->shadow); | |
2172 | amdgpu_bo_unref(&vm->root.bo); | |
2173 | vm->root.bo = NULL; | |
2bd9ccfa CK |
2174 | |
2175 | error_free_sched_entity: | |
2176 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
2177 | ||
2178 | return r; | |
d38ceaf9 AD |
2179 | } |
2180 | ||
f566ceb1 CK |
2181 | /** |
2182 | * amdgpu_vm_free_levels - free PD/PT levels | |
2183 | * | |
2184 | * @level: PD/PT starting level to free | |
2185 | * | |
2186 | * Free the page directory or page table level and all sub levels. | |
2187 | */ | |
2188 | static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) | |
2189 | { | |
2190 | unsigned i; | |
2191 | ||
2192 | if (level->bo) { | |
2193 | amdgpu_bo_unref(&level->bo->shadow); | |
2194 | amdgpu_bo_unref(&level->bo); | |
2195 | } | |
2196 | ||
2197 | if (level->entries) | |
2198 | for (i = 0; i <= level->last_entry_used; i++) | |
2199 | amdgpu_vm_free_levels(&level->entries[i]); | |
2200 | ||
2201 | drm_free_large(level->entries); | |
2202 | } | |
2203 | ||
d38ceaf9 AD |
2204 | /** |
2205 | * amdgpu_vm_fini - tear down a vm instance | |
2206 | * | |
2207 | * @adev: amdgpu_device pointer | |
2208 | * @vm: requested vm | |
2209 | * | |
8843dbbb | 2210 | * Tear down @vm. |
d38ceaf9 AD |
2211 | * Unbind the VM and remove all bos from the vm bo list |
2212 | */ | |
2213 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2214 | { | |
2215 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
4388fc2a | 2216 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
d38ceaf9 | 2217 | |
2d55e45a | 2218 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 2219 | |
d38ceaf9 AD |
2220 | if (!RB_EMPTY_ROOT(&vm->va)) { |
2221 | dev_err(adev->dev, "still active bo inside vm\n"); | |
2222 | } | |
a9f87f64 | 2223 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) { |
d38ceaf9 | 2224 | list_del(&mapping->list); |
a9f87f64 | 2225 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2226 | kfree(mapping); |
2227 | } | |
2228 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2229 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2230 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2231 | prt_fini_needed = false; |
451bc8eb | 2232 | } |
284710fa | 2233 | |
d38ceaf9 | 2234 | list_del(&mapping->list); |
451bc8eb | 2235 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2236 | } |
2237 | ||
f566ceb1 | 2238 | amdgpu_vm_free_levels(&vm->root); |
a24960f3 | 2239 | dma_fence_put(vm->last_dir_update); |
d38ceaf9 | 2240 | } |
ea89f8c9 | 2241 | |
a9a78b32 CK |
2242 | /** |
2243 | * amdgpu_vm_manager_init - init the VM manager | |
2244 | * | |
2245 | * @adev: amdgpu_device pointer | |
2246 | * | |
2247 | * Initialize the VM manager structures | |
2248 | */ | |
2249 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2250 | { | |
7645670d CK |
2251 | unsigned i, j; |
2252 | ||
2253 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
2254 | struct amdgpu_vm_id_manager *id_mgr = | |
2255 | &adev->vm_manager.id_mgr[i]; | |
a9a78b32 | 2256 | |
7645670d CK |
2257 | mutex_init(&id_mgr->lock); |
2258 | INIT_LIST_HEAD(&id_mgr->ids_lru); | |
a9a78b32 | 2259 | |
7645670d CK |
2260 | /* skip over VMID 0, since it is the system VM */ |
2261 | for (j = 1; j < id_mgr->num_ids; ++j) { | |
2262 | amdgpu_vm_reset_id(adev, i, j); | |
2263 | amdgpu_sync_create(&id_mgr->ids[i].active); | |
2264 | list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); | |
2265 | } | |
971fe9a9 | 2266 | } |
2d55e45a | 2267 | |
f54d1867 CW |
2268 | adev->vm_manager.fence_context = |
2269 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2270 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2271 | adev->vm_manager.seqno[i] = 0; | |
2272 | ||
7645670d | 2273 | |
2d55e45a | 2274 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 2275 | atomic64_set(&adev->vm_manager.client_counter, 0); |
284710fa | 2276 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2277 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
a9a78b32 CK |
2278 | } |
2279 | ||
ea89f8c9 CK |
2280 | /** |
2281 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2282 | * | |
2283 | * @adev: amdgpu_device pointer | |
2284 | * | |
2285 | * Cleanup the VM manager and free resources. | |
2286 | */ | |
2287 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2288 | { | |
7645670d | 2289 | unsigned i, j; |
ea89f8c9 | 2290 | |
7645670d CK |
2291 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
2292 | struct amdgpu_vm_id_manager *id_mgr = | |
2293 | &adev->vm_manager.id_mgr[i]; | |
bcb1ba35 | 2294 | |
7645670d CK |
2295 | mutex_destroy(&id_mgr->lock); |
2296 | for (j = 0; j < AMDGPU_NUM_VM; ++j) { | |
2297 | struct amdgpu_vm_id *id = &id_mgr->ids[j]; | |
2298 | ||
2299 | amdgpu_sync_free(&id->active); | |
2300 | dma_fence_put(id->flushed_updates); | |
2301 | dma_fence_put(id->last_flush); | |
2302 | } | |
bcb1ba35 | 2303 | } |
ea89f8c9 | 2304 | } |