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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
1fbb2e92 | 28 | #include <linux/fence-array.h> |
d38ceaf9 AD |
29 | #include <drm/drmP.h> |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu.h" | |
32 | #include "amdgpu_trace.h" | |
33 | ||
34 | /* | |
35 | * GPUVM | |
36 | * GPUVM is similar to the legacy gart on older asics, however | |
37 | * rather than there being a single global gart table | |
38 | * for the entire GPU, there are multiple VM page tables active | |
39 | * at any given time. The VM page tables can contain a mix | |
40 | * vram pages and system memory pages and system memory pages | |
41 | * can be mapped as snooped (cached system pages) or unsnooped | |
42 | * (uncached system pages). | |
43 | * Each VM has an ID associated with it and there is a page table | |
44 | * associated with each VMID. When execting a command buffer, | |
45 | * the kernel tells the the ring what VMID to use for that command | |
46 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
47 | * The userspace drivers maintain their own address space and the kernel | |
48 | * sets up their pages tables accordingly when they submit their | |
49 | * command buffers and a VMID is assigned. | |
50 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
51 | * SI supports 16. | |
52 | */ | |
53 | ||
f4833c4f HK |
54 | /* Local structure. Encapsulate some VM table update parameters to reduce |
55 | * the number of function parameters | |
56 | */ | |
29efc4f5 | 57 | struct amdgpu_pte_update_params { |
27c5f36f CK |
58 | /* amdgpu device we do this update for */ |
59 | struct amdgpu_device *adev; | |
f4833c4f HK |
60 | /* address where to copy page table entries from */ |
61 | uint64_t src; | |
f4833c4f HK |
62 | /* indirect buffer to fill with commands */ |
63 | struct amdgpu_ib *ib; | |
64 | }; | |
65 | ||
d38ceaf9 AD |
66 | /** |
67 | * amdgpu_vm_num_pde - return the number of page directory entries | |
68 | * | |
69 | * @adev: amdgpu_device pointer | |
70 | * | |
8843dbbb | 71 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
72 | */ |
73 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
74 | { | |
75 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
76 | } | |
77 | ||
78 | /** | |
79 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
80 | * | |
81 | * @adev: amdgpu_device pointer | |
82 | * | |
8843dbbb | 83 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
84 | */ |
85 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
86 | { | |
87 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
88 | } | |
89 | ||
90 | /** | |
56467ebf | 91 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
92 | * |
93 | * @vm: vm providing the BOs | |
3c0eea6c | 94 | * @validated: head of validation list |
56467ebf | 95 | * @entry: entry to add |
d38ceaf9 AD |
96 | * |
97 | * Add the page directory to the list of BOs to | |
56467ebf | 98 | * validate for command submission. |
d38ceaf9 | 99 | */ |
56467ebf CK |
100 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
101 | struct list_head *validated, | |
102 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 103 | { |
56467ebf | 104 | entry->robj = vm->page_directory; |
56467ebf CK |
105 | entry->priority = 0; |
106 | entry->tv.bo = &vm->page_directory->tbo; | |
107 | entry->tv.shared = true; | |
2f568dbd | 108 | entry->user_pages = NULL; |
56467ebf CK |
109 | list_add(&entry->tv.head, validated); |
110 | } | |
d38ceaf9 | 111 | |
56467ebf | 112 | /** |
ee1782c3 | 113 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf | 114 | * |
5a712a87 | 115 | * @adev: amdgpu device pointer |
56467ebf | 116 | * @vm: vm providing the BOs |
3c0eea6c | 117 | * @duplicates: head of duplicates list |
d38ceaf9 | 118 | * |
ee1782c3 CK |
119 | * Add the page directory to the BO duplicates list |
120 | * for command submission. | |
d38ceaf9 | 121 | */ |
5a712a87 CK |
122 | void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
123 | struct list_head *duplicates) | |
d38ceaf9 | 124 | { |
5a712a87 | 125 | uint64_t num_evictions; |
ee1782c3 | 126 | unsigned i; |
d38ceaf9 | 127 | |
5a712a87 CK |
128 | /* We only need to validate the page tables |
129 | * if they aren't already valid. | |
130 | */ | |
131 | num_evictions = atomic64_read(&adev->num_evictions); | |
132 | if (num_evictions == vm->last_eviction_counter) | |
133 | return; | |
134 | ||
d38ceaf9 | 135 | /* add the vm page table to the list */ |
ee1782c3 CK |
136 | for (i = 0; i <= vm->max_pde_used; ++i) { |
137 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
138 | ||
139 | if (!entry->robj) | |
d38ceaf9 AD |
140 | continue; |
141 | ||
ee1782c3 | 142 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 143 | } |
eceb8a15 CK |
144 | |
145 | } | |
146 | ||
147 | /** | |
148 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
149 | * | |
150 | * @adev: amdgpu device instance | |
151 | * @vm: vm providing the BOs | |
152 | * | |
153 | * Move the PT BOs to the tail of the LRU. | |
154 | */ | |
155 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
156 | struct amdgpu_vm *vm) | |
157 | { | |
158 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
159 | unsigned i; | |
160 | ||
161 | spin_lock(&glob->lru_lock); | |
162 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
163 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
164 | ||
165 | if (!entry->robj) | |
166 | continue; | |
167 | ||
168 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
169 | } | |
170 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
171 | } |
172 | ||
192b7dcb CZ |
173 | static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev, |
174 | struct amdgpu_vm_id *id) | |
175 | { | |
176 | return id->current_gpu_reset_count != | |
177 | atomic_read(&adev->gpu_reset_counter) ? true : false; | |
178 | } | |
179 | ||
d38ceaf9 AD |
180 | /** |
181 | * amdgpu_vm_grab_id - allocate the next free VMID | |
182 | * | |
d38ceaf9 | 183 | * @vm: vm to allocate id for |
7f8a5290 CK |
184 | * @ring: ring we want to submit job to |
185 | * @sync: sync object where we add dependencies | |
94dd0a4a | 186 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 187 | * |
7f8a5290 | 188 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 189 | */ |
7f8a5290 | 190 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 | 191 | struct amdgpu_sync *sync, struct fence *fence, |
fd53be30 | 192 | struct amdgpu_job *job) |
d38ceaf9 | 193 | { |
d38ceaf9 | 194 | struct amdgpu_device *adev = ring->adev; |
090b767e | 195 | uint64_t fence_context = adev->fence_context + ring->idx; |
4ff37a83 | 196 | struct fence *updates = sync->last_vm_update; |
8d76001e | 197 | struct amdgpu_vm_id *id, *idle; |
1fbb2e92 CK |
198 | struct fence **fences; |
199 | unsigned i; | |
200 | int r = 0; | |
201 | ||
202 | fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids, | |
203 | GFP_KERNEL); | |
204 | if (!fences) | |
205 | return -ENOMEM; | |
d38ceaf9 | 206 | |
94dd0a4a CK |
207 | mutex_lock(&adev->vm_manager.lock); |
208 | ||
36fd7c5c | 209 | /* Check if we have an idle VMID */ |
1fbb2e92 | 210 | i = 0; |
8d76001e | 211 | list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) { |
1fbb2e92 CK |
212 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
213 | if (!fences[i]) | |
36fd7c5c | 214 | break; |
1fbb2e92 | 215 | ++i; |
36fd7c5c CK |
216 | } |
217 | ||
1fbb2e92 | 218 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
8d76001e | 219 | if (&idle->list == &adev->vm_manager.ids_lru) { |
1fbb2e92 CK |
220 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
221 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
222 | struct fence_array *array; | |
223 | unsigned j; | |
224 | ||
225 | for (j = 0; j < i; ++j) | |
226 | fence_get(fences[j]); | |
227 | ||
228 | array = fence_array_create(i, fences, fence_context, | |
229 | seqno, true); | |
230 | if (!array) { | |
231 | for (j = 0; j < i; ++j) | |
232 | fence_put(fences[j]); | |
233 | kfree(fences); | |
234 | r = -ENOMEM; | |
235 | goto error; | |
236 | } | |
237 | ||
238 | ||
239 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
240 | fence_put(&array->base); | |
241 | if (r) | |
242 | goto error; | |
243 | ||
244 | mutex_unlock(&adev->vm_manager.lock); | |
245 | return 0; | |
246 | ||
247 | } | |
248 | kfree(fences); | |
249 | ||
fd53be30 | 250 | job->vm_needs_flush = true; |
1fbb2e92 CK |
251 | /* Check if we can use a VMID already assigned to this VM */ |
252 | i = ring->idx; | |
253 | do { | |
254 | struct fence *flushed; | |
255 | ||
256 | id = vm->ids[i++]; | |
257 | if (i == AMDGPU_MAX_RINGS) | |
258 | i = 0; | |
8d76001e | 259 | |
1fbb2e92 CK |
260 | /* Check all the prerequisites to using this VMID */ |
261 | if (!id) | |
262 | continue; | |
192b7dcb | 263 | if (amdgpu_vm_is_gpu_reset(adev, id)) |
6adb0513 | 264 | continue; |
1fbb2e92 CK |
265 | |
266 | if (atomic64_read(&id->owner) != vm->client_id) | |
267 | continue; | |
268 | ||
fd53be30 | 269 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
270 | continue; |
271 | ||
090b767e CK |
272 | if (!id->last_flush) |
273 | continue; | |
274 | ||
275 | if (id->last_flush->context != fence_context && | |
276 | !fence_is_signaled(id->last_flush)) | |
1fbb2e92 CK |
277 | continue; |
278 | ||
279 | flushed = id->flushed_updates; | |
280 | if (updates && | |
281 | (!flushed || fence_is_later(updates, flushed))) | |
282 | continue; | |
283 | ||
3dab83be CK |
284 | /* Good we can use this VMID. Remember this submission as |
285 | * user of the VMID. | |
286 | */ | |
1fbb2e92 CK |
287 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
288 | if (r) | |
289 | goto error; | |
8d76001e | 290 | |
6adb0513 | 291 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
1fbb2e92 CK |
292 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
293 | vm->ids[ring->idx] = id; | |
8d76001e | 294 | |
fd53be30 CZ |
295 | job->vm_id = id - adev->vm_manager.ids; |
296 | job->vm_needs_flush = false; | |
0c0fdf14 | 297 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
8d76001e | 298 | |
1fbb2e92 CK |
299 | mutex_unlock(&adev->vm_manager.lock); |
300 | return 0; | |
8d76001e | 301 | |
1fbb2e92 | 302 | } while (i != ring->idx); |
8d76001e | 303 | |
1fbb2e92 CK |
304 | /* Still no ID to use? Then use the idle one found earlier */ |
305 | id = idle; | |
8e9fbeb5 | 306 | |
1fbb2e92 CK |
307 | /* Remember this submission as user of the VMID */ |
308 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
309 | if (r) |
310 | goto error; | |
94dd0a4a | 311 | |
832a902f CK |
312 | fence_put(id->first); |
313 | id->first = fence_get(fence); | |
94dd0a4a | 314 | |
41d9eb2c CK |
315 | fence_put(id->last_flush); |
316 | id->last_flush = NULL; | |
317 | ||
832a902f CK |
318 | fence_put(id->flushed_updates); |
319 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 320 | |
fd53be30 | 321 | id->pd_gpu_addr = job->vm_pd_addr; |
b46b8a87 | 322 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
832a902f | 323 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
0ea54b9b | 324 | atomic64_set(&id->owner, vm->client_id); |
832a902f | 325 | vm->ids[ring->idx] = id; |
d38ceaf9 | 326 | |
fd53be30 | 327 | job->vm_id = id - adev->vm_manager.ids; |
0c0fdf14 | 328 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
832a902f CK |
329 | |
330 | error: | |
94dd0a4a | 331 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 332 | return r; |
d38ceaf9 AD |
333 | } |
334 | ||
93dcc37d AD |
335 | static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) |
336 | { | |
337 | struct amdgpu_device *adev = ring->adev; | |
338 | const struct amdgpu_ip_block_version *ip_block; | |
339 | ||
340 | if (ring->type != AMDGPU_RING_TYPE_COMPUTE) | |
341 | /* only compute rings */ | |
342 | return false; | |
343 | ||
344 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
345 | if (!ip_block) | |
346 | return false; | |
347 | ||
348 | if (ip_block->major <= 7) { | |
349 | /* gfx7 has no workaround */ | |
350 | return true; | |
351 | } else if (ip_block->major == 8) { | |
352 | if (adev->gfx.mec_fw_version >= 673) | |
353 | /* gfx8 is fixed in MEC firmware 673 */ | |
354 | return false; | |
355 | else | |
356 | return true; | |
357 | } | |
358 | return false; | |
359 | } | |
360 | ||
d38ceaf9 AD |
361 | /** |
362 | * amdgpu_vm_flush - hardware flush the vm | |
363 | * | |
364 | * @ring: ring to use for flush | |
cffadc83 | 365 | * @vm_id: vmid number to use |
4ff37a83 | 366 | * @pd_addr: address of the page directory |
d38ceaf9 | 367 | * |
4ff37a83 | 368 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 369 | */ |
fd53be30 | 370 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) |
d38ceaf9 | 371 | { |
971fe9a9 | 372 | struct amdgpu_device *adev = ring->adev; |
fd53be30 | 373 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id]; |
d564a06e | 374 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
375 | id->gds_base != job->gds_base || |
376 | id->gds_size != job->gds_size || | |
377 | id->gws_base != job->gws_base || | |
378 | id->gws_size != job->gws_size || | |
379 | id->oa_base != job->oa_base || | |
380 | id->oa_size != job->oa_size); | |
41d9eb2c | 381 | int r; |
d564a06e CK |
382 | |
383 | if (ring->funcs->emit_pipeline_sync && ( | |
fd53be30 | 384 | job->vm_needs_flush || gds_switch_needed || |
93dcc37d | 385 | amdgpu_vm_ring_has_compute_vm_bug(ring))) |
d564a06e | 386 | amdgpu_ring_emit_pipeline_sync(ring); |
971fe9a9 | 387 | |
aa1c8900 CZ |
388 | if (ring->funcs->emit_vm_flush && (job->vm_needs_flush || |
389 | amdgpu_vm_is_gpu_reset(adev, id))) { | |
41d9eb2c CK |
390 | struct fence *fence; |
391 | ||
fd53be30 CZ |
392 | trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id); |
393 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
41d9eb2c | 394 | |
3dab83be CK |
395 | r = amdgpu_fence_emit(ring, &fence); |
396 | if (r) | |
397 | return r; | |
398 | ||
41d9eb2c | 399 | mutex_lock(&adev->vm_manager.lock); |
3dab83be CK |
400 | fence_put(id->last_flush); |
401 | id->last_flush = fence; | |
41d9eb2c | 402 | mutex_unlock(&adev->vm_manager.lock); |
d38ceaf9 | 403 | } |
cffadc83 | 404 | |
d564a06e | 405 | if (gds_switch_needed) { |
fd53be30 CZ |
406 | id->gds_base = job->gds_base; |
407 | id->gds_size = job->gds_size; | |
408 | id->gws_base = job->gws_base; | |
409 | id->gws_size = job->gws_size; | |
410 | id->oa_base = job->oa_base; | |
411 | id->oa_size = job->oa_size; | |
412 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, | |
413 | job->gds_base, job->gds_size, | |
414 | job->gws_base, job->gws_size, | |
415 | job->oa_base, job->oa_size); | |
971fe9a9 | 416 | } |
41d9eb2c CK |
417 | |
418 | return 0; | |
971fe9a9 CK |
419 | } |
420 | ||
421 | /** | |
422 | * amdgpu_vm_reset_id - reset VMID to zero | |
423 | * | |
424 | * @adev: amdgpu device structure | |
425 | * @vm_id: vmid number to use | |
426 | * | |
427 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
428 | */ | |
429 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
430 | { | |
bcb1ba35 CK |
431 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
432 | ||
433 | id->gds_base = 0; | |
434 | id->gds_size = 0; | |
435 | id->gws_base = 0; | |
436 | id->gws_size = 0; | |
437 | id->oa_base = 0; | |
438 | id->oa_size = 0; | |
d38ceaf9 AD |
439 | } |
440 | ||
d38ceaf9 AD |
441 | /** |
442 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
443 | * | |
444 | * @vm: requested vm | |
445 | * @bo: requested buffer object | |
446 | * | |
8843dbbb | 447 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
448 | * Search inside the @bos vm list for the requested vm |
449 | * Returns the found bo_va or NULL if none is found | |
450 | * | |
451 | * Object has to be reserved! | |
452 | */ | |
453 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
454 | struct amdgpu_bo *bo) | |
455 | { | |
456 | struct amdgpu_bo_va *bo_va; | |
457 | ||
458 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
459 | if (bo_va->vm == vm) { | |
460 | return bo_va; | |
461 | } | |
462 | } | |
463 | return NULL; | |
464 | } | |
465 | ||
466 | /** | |
467 | * amdgpu_vm_update_pages - helper to call the right asic function | |
468 | * | |
29efc4f5 | 469 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
470 | * @pe: addr of the page entry |
471 | * @addr: dst addr to write into pe | |
472 | * @count: number of page entries to update | |
473 | * @incr: increase next addr by incr bytes | |
474 | * @flags: hw access flags | |
d38ceaf9 AD |
475 | * |
476 | * Traces the parameters and calls the right asic functions | |
477 | * to setup the page table using the DMA. | |
478 | */ | |
27c5f36f | 479 | static void amdgpu_vm_update_pages(struct amdgpu_pte_update_params *params, |
d38ceaf9 AD |
480 | uint64_t pe, uint64_t addr, |
481 | unsigned count, uint32_t incr, | |
9ab21462 | 482 | uint32_t flags) |
d38ceaf9 AD |
483 | { |
484 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
485 | ||
29efc4f5 | 486 | if (params->src) { |
27c5f36f | 487 | amdgpu_vm_copy_pte(params->adev, params->ib, |
29efc4f5 | 488 | pe, (params->src + (addr >> 12) * 8), count); |
d38ceaf9 | 489 | |
b07c9d2a | 490 | } else if (count < 3) { |
de9ea7bd CK |
491 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
492 | addr | flags, count, incr); | |
d38ceaf9 AD |
493 | |
494 | } else { | |
27c5f36f | 495 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
496 | count, incr, flags); |
497 | } | |
498 | } | |
499 | ||
500 | /** | |
501 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
502 | * | |
503 | * @adev: amdgpu_device pointer | |
504 | * @bo: bo to clear | |
ef9f0a83 CZ |
505 | * |
506 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
507 | */ |
508 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 509 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
510 | struct amdgpu_bo *bo) |
511 | { | |
2d55e45a | 512 | struct amdgpu_ring *ring; |
4af9f07c | 513 | struct fence *fence = NULL; |
d71518b5 | 514 | struct amdgpu_job *job; |
29efc4f5 | 515 | struct amdgpu_pte_update_params params; |
d38ceaf9 AD |
516 | unsigned entries; |
517 | uint64_t addr; | |
518 | int r; | |
519 | ||
2d55e45a CK |
520 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
521 | ||
ca952613 | 522 | r = reservation_object_reserve_shared(bo->tbo.resv); |
523 | if (r) | |
524 | return r; | |
525 | ||
d38ceaf9 AD |
526 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
527 | if (r) | |
ef9f0a83 | 528 | goto error; |
d38ceaf9 AD |
529 | |
530 | addr = amdgpu_bo_gpu_offset(bo); | |
531 | entries = amdgpu_bo_size(bo) / 8; | |
532 | ||
d71518b5 CK |
533 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
534 | if (r) | |
ef9f0a83 | 535 | goto error; |
d38ceaf9 | 536 | |
27c5f36f CK |
537 | memset(¶ms, 0, sizeof(params)); |
538 | params.adev = adev; | |
29efc4f5 | 539 | params.ib = &job->ibs[0]; |
27c5f36f | 540 | amdgpu_vm_update_pages(¶ms, addr, 0, entries, 0, 0); |
d71518b5 CK |
541 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
542 | ||
543 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
544 | r = amdgpu_job_submit(job, ring, &vm->entity, |
545 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
546 | if (r) |
547 | goto error_free; | |
548 | ||
d71518b5 | 549 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 550 | fence_put(fence); |
cadf97b1 | 551 | return 0; |
ef9f0a83 | 552 | |
d38ceaf9 | 553 | error_free: |
d71518b5 | 554 | amdgpu_job_free(job); |
d38ceaf9 | 555 | |
ef9f0a83 | 556 | error: |
d38ceaf9 AD |
557 | return r; |
558 | } | |
559 | ||
560 | /** | |
b07c9d2a | 561 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 562 | * |
b07c9d2a | 563 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
564 | * @addr: the unmapped addr |
565 | * | |
566 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 567 | * to and return the pointer for the page table entry. |
d38ceaf9 | 568 | */ |
de9ea7bd | 569 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
570 | { |
571 | uint64_t result; | |
572 | ||
de9ea7bd CK |
573 | /* page table offset */ |
574 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 575 | |
de9ea7bd CK |
576 | /* in case cpu page size != gpu page size*/ |
577 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 578 | |
b07c9d2a | 579 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
580 | |
581 | return result; | |
582 | } | |
583 | ||
584 | /** | |
585 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
586 | * | |
587 | * @adev: amdgpu_device pointer | |
588 | * @vm: requested vm | |
589 | * @start: start of GPU address range | |
590 | * @end: end of GPU address range | |
591 | * | |
592 | * Allocates new page tables if necessary | |
8843dbbb | 593 | * and updates the page directory. |
d38ceaf9 | 594 | * Returns 0 for success, error for failure. |
d38ceaf9 AD |
595 | */ |
596 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
597 | struct amdgpu_vm *vm) | |
598 | { | |
2d55e45a | 599 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
600 | struct amdgpu_bo *pd = vm->page_directory; |
601 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
602 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
603 | uint64_t last_pde = ~0, last_pt = ~0; | |
604 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 605 | struct amdgpu_job *job; |
29efc4f5 | 606 | struct amdgpu_pte_update_params params; |
4af9f07c | 607 | struct fence *fence = NULL; |
d5fc5e82 | 608 | |
d38ceaf9 AD |
609 | int r; |
610 | ||
2d55e45a CK |
611 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
612 | ||
d38ceaf9 AD |
613 | /* padding, etc. */ |
614 | ndw = 64; | |
615 | ||
616 | /* assume the worst case */ | |
617 | ndw += vm->max_pde_used * 6; | |
618 | ||
d71518b5 CK |
619 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
620 | if (r) | |
d38ceaf9 | 621 | return r; |
d71518b5 | 622 | |
27c5f36f CK |
623 | memset(¶ms, 0, sizeof(params)); |
624 | params.adev = adev; | |
29efc4f5 | 625 | params.ib = &job->ibs[0]; |
d38ceaf9 AD |
626 | |
627 | /* walk over the address space and update the page directory */ | |
628 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 629 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
630 | uint64_t pde, pt; |
631 | ||
632 | if (bo == NULL) | |
633 | continue; | |
634 | ||
635 | pt = amdgpu_bo_gpu_offset(bo); | |
636 | if (vm->page_tables[pt_idx].addr == pt) | |
637 | continue; | |
638 | vm->page_tables[pt_idx].addr = pt; | |
639 | ||
640 | pde = pd_addr + pt_idx * 8; | |
641 | if (((last_pde + 8 * count) != pde) || | |
642 | ((last_pt + incr * count) != pt)) { | |
643 | ||
644 | if (count) { | |
27c5f36f CK |
645 | amdgpu_vm_update_pages(¶ms, last_pde, |
646 | last_pt, count, incr, | |
9ab21462 | 647 | AMDGPU_PTE_VALID); |
d38ceaf9 AD |
648 | } |
649 | ||
650 | count = 1; | |
651 | last_pde = pde; | |
652 | last_pt = pt; | |
653 | } else { | |
654 | ++count; | |
655 | } | |
656 | } | |
657 | ||
658 | if (count) | |
27c5f36f | 659 | amdgpu_vm_update_pages(¶ms, last_pde, last_pt, |
f4833c4f | 660 | count, incr, AMDGPU_PTE_VALID); |
d38ceaf9 | 661 | |
29efc4f5 CK |
662 | if (params.ib->length_dw != 0) { |
663 | amdgpu_ring_pad_ib(ring, params.ib); | |
e86f9cee CK |
664 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
665 | AMDGPU_FENCE_OWNER_VM); | |
29efc4f5 | 666 | WARN_ON(params.ib->length_dw > ndw); |
2bd9ccfa CK |
667 | r = amdgpu_job_submit(job, ring, &vm->entity, |
668 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
669 | if (r) |
670 | goto error_free; | |
05906dec | 671 | |
4af9f07c | 672 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
673 | fence_put(vm->page_directory_fence); |
674 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 675 | fence_put(fence); |
d5fc5e82 | 676 | |
d71518b5 CK |
677 | } else { |
678 | amdgpu_job_free(job); | |
d5fc5e82 | 679 | } |
d38ceaf9 AD |
680 | |
681 | return 0; | |
d5fc5e82 CZ |
682 | |
683 | error_free: | |
d71518b5 | 684 | amdgpu_job_free(job); |
4af9f07c | 685 | return r; |
d38ceaf9 AD |
686 | } |
687 | ||
d38ceaf9 AD |
688 | /** |
689 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
690 | * | |
29efc4f5 | 691 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
692 | * @vm: requested vm |
693 | * @start: start of GPU address range | |
694 | * @end: end of GPU address range | |
677131a1 | 695 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
696 | * @flags: mapping flags |
697 | * | |
8843dbbb | 698 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 699 | */ |
27c5f36f | 700 | static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 701 | struct amdgpu_vm *vm, |
a1e08d3b CK |
702 | uint64_t start, uint64_t end, |
703 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 704 | { |
31f6c1fe CK |
705 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
706 | ||
92696dd5 | 707 | uint64_t cur_pe_start, cur_nptes, cur_dst; |
677131a1 | 708 | uint64_t addr; /* next GPU address to be updated */ |
21718497 AX |
709 | uint64_t pt_idx; |
710 | struct amdgpu_bo *pt; | |
711 | unsigned nptes; /* next number of ptes to be updated */ | |
712 | uint64_t next_pe_start; | |
713 | ||
714 | /* initialize the variables */ | |
715 | addr = start; | |
716 | pt_idx = addr >> amdgpu_vm_block_size; | |
717 | pt = vm->page_tables[pt_idx].entry.robj; | |
718 | ||
719 | if ((addr & ~mask) == (end & ~mask)) | |
720 | nptes = end - addr; | |
721 | else | |
722 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
723 | ||
724 | cur_pe_start = amdgpu_bo_gpu_offset(pt); | |
725 | cur_pe_start += (addr & mask) * 8; | |
92696dd5 | 726 | cur_nptes = nptes; |
21718497 AX |
727 | cur_dst = dst; |
728 | ||
729 | /* for next ptb*/ | |
730 | addr += nptes; | |
731 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
d38ceaf9 AD |
732 | |
733 | /* walk over the address space and update the page tables */ | |
21718497 AX |
734 | while (addr < end) { |
735 | pt_idx = addr >> amdgpu_vm_block_size; | |
736 | pt = vm->page_tables[pt_idx].entry.robj; | |
d38ceaf9 AD |
737 | |
738 | if ((addr & ~mask) == (end & ~mask)) | |
739 | nptes = end - addr; | |
740 | else | |
741 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
742 | ||
677131a1 AX |
743 | next_pe_start = amdgpu_bo_gpu_offset(pt); |
744 | next_pe_start += (addr & mask) * 8; | |
d38ceaf9 | 745 | |
92696dd5 | 746 | if ((cur_pe_start + 8 * cur_nptes) == next_pe_start) { |
3a6f8e0c | 747 | /* The next ptb is consecutive to current ptb. |
92696dd5 | 748 | * Don't call amdgpu_vm_update_pages now. |
3a6f8e0c AX |
749 | * Will update two ptbs together in future. |
750 | */ | |
92696dd5 | 751 | cur_nptes += nptes; |
3a6f8e0c | 752 | } else { |
92696dd5 CK |
753 | amdgpu_vm_update_pages(params, cur_pe_start, cur_dst, |
754 | cur_nptes, AMDGPU_GPU_PAGE_SIZE, | |
755 | flags); | |
d38ceaf9 | 756 | |
677131a1 | 757 | cur_pe_start = next_pe_start; |
92696dd5 | 758 | cur_nptes = nptes; |
677131a1 | 759 | cur_dst = dst; |
d38ceaf9 AD |
760 | } |
761 | ||
21718497 | 762 | /* for next ptb*/ |
d38ceaf9 AD |
763 | addr += nptes; |
764 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
765 | } | |
766 | ||
92696dd5 CK |
767 | amdgpu_vm_update_pages(params, cur_pe_start, cur_dst, cur_nptes, |
768 | AMDGPU_GPU_PAGE_SIZE, flags); | |
769 | } | |
770 | ||
771 | /* | |
772 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
773 | * | |
774 | * @params: see amdgpu_pte_update_params definition | |
775 | * @vm: requested vm | |
776 | * @start: first PTE to handle | |
777 | * @end: last PTE to handle | |
778 | * @dst: addr those PTEs should point to | |
779 | * @flags: hw mapping flags | |
780 | */ | |
781 | static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, | |
782 | struct amdgpu_vm *vm, | |
783 | uint64_t start, uint64_t end, | |
784 | uint64_t dst, uint32_t flags) | |
785 | { | |
786 | /** | |
787 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
788 | * field in the PTE. When this field is set to a non-zero value, page | |
789 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
790 | * flags are considered valid for all PTEs within the fragment range | |
791 | * and corresponding mappings are assumed to be physically contiguous. | |
792 | * | |
793 | * The L1 TLB can store a single PTE for the whole fragment, | |
794 | * significantly increasing the space available for translation | |
795 | * caching. This leads to large improvements in throughput when the | |
796 | * TLB is under pressure. | |
797 | * | |
798 | * The L2 TLB distributes small and large fragments into two | |
799 | * asymmetric partitions. The large fragment cache is significantly | |
800 | * larger. Thus, we try to use large fragments wherever possible. | |
801 | * Userspace can support this by aligning virtual base address and | |
802 | * allocation size to the fragment size. | |
803 | */ | |
804 | ||
e2b84e4b | 805 | const uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG; |
92696dd5 CK |
806 | |
807 | uint64_t frag_start = ALIGN(start, frag_align); | |
808 | uint64_t frag_end = end & ~(frag_align - 1); | |
809 | ||
e2b84e4b CK |
810 | uint32_t frag; |
811 | ||
92696dd5 | 812 | /* system pages are non continuously */ |
b7fc2cbd | 813 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
92696dd5 CK |
814 | (frag_start >= frag_end)) { |
815 | ||
816 | amdgpu_vm_update_ptes(params, vm, start, end, dst, flags); | |
817 | return; | |
818 | } | |
819 | ||
e2b84e4b CK |
820 | /* use more than 64KB fragment size if possible */ |
821 | frag = lower_32_bits(frag_start | frag_end); | |
822 | frag = likely(frag) ? __ffs(frag) : 31; | |
823 | ||
92696dd5 CK |
824 | /* handle the 4K area at the beginning */ |
825 | if (start != frag_start) { | |
826 | amdgpu_vm_update_ptes(params, vm, start, frag_start, | |
827 | dst, flags); | |
828 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; | |
829 | } | |
830 | ||
831 | /* handle the area in the middle */ | |
832 | amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst, | |
e2b84e4b | 833 | flags | AMDGPU_PTE_FRAG(frag)); |
92696dd5 CK |
834 | |
835 | /* handle the 4K area at the end */ | |
836 | if (frag_end != end) { | |
837 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
838 | amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags); | |
839 | } | |
d38ceaf9 AD |
840 | } |
841 | ||
d38ceaf9 AD |
842 | /** |
843 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
844 | * | |
845 | * @adev: amdgpu_device pointer | |
3cabaa54 | 846 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
847 | * @src: address where to copy page table entries from |
848 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 849 | * @vm: requested vm |
a14faa65 CK |
850 | * @start: start of mapped range |
851 | * @last: last mapped entry | |
852 | * @flags: flags for the entries | |
d38ceaf9 | 853 | * @addr: addr to set the area to |
d38ceaf9 AD |
854 | * @fence: optional resulting fence |
855 | * | |
a14faa65 | 856 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 857 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
858 | */ |
859 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
3cabaa54 | 860 | struct fence *exclusive, |
fa3ab3c7 CK |
861 | uint64_t src, |
862 | dma_addr_t *pages_addr, | |
d38ceaf9 | 863 | struct amdgpu_vm *vm, |
a14faa65 CK |
864 | uint64_t start, uint64_t last, |
865 | uint32_t flags, uint64_t addr, | |
866 | struct fence **fence) | |
d38ceaf9 | 867 | { |
2d55e45a | 868 | struct amdgpu_ring *ring; |
a1e08d3b | 869 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 870 | unsigned nptes, ncmds, ndw; |
d71518b5 | 871 | struct amdgpu_job *job; |
29efc4f5 | 872 | struct amdgpu_pte_update_params params; |
4af9f07c | 873 | struct fence *f = NULL; |
d38ceaf9 AD |
874 | int r; |
875 | ||
2d55e45a | 876 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 877 | |
29efc4f5 | 878 | memset(¶ms, 0, sizeof(params)); |
27c5f36f | 879 | params.adev = adev; |
29efc4f5 | 880 | params.src = src; |
2d55e45a | 881 | |
a1e08d3b CK |
882 | /* sync to everything on unmapping */ |
883 | if (!(flags & AMDGPU_PTE_VALID)) | |
884 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
885 | ||
a14faa65 | 886 | nptes = last - start + 1; |
d38ceaf9 AD |
887 | |
888 | /* | |
889 | * reserve space for one command every (1 << BLOCK_SIZE) | |
890 | * entries or 2k dwords (whatever is smaller) | |
891 | */ | |
892 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
893 | ||
894 | /* padding, etc. */ | |
895 | ndw = 64; | |
896 | ||
b0456f93 | 897 | if (src) { |
d38ceaf9 AD |
898 | /* only copy commands needed */ |
899 | ndw += ncmds * 7; | |
900 | ||
b0456f93 CK |
901 | } else if (pages_addr) { |
902 | /* copy commands needed */ | |
903 | ndw += ncmds * 7; | |
d38ceaf9 | 904 | |
b0456f93 | 905 | /* and also PTEs */ |
d38ceaf9 AD |
906 | ndw += nptes * 2; |
907 | ||
908 | } else { | |
909 | /* set page commands needed */ | |
910 | ndw += ncmds * 10; | |
911 | ||
912 | /* two extra commands for begin/end of fragment */ | |
913 | ndw += 2 * 10; | |
914 | } | |
915 | ||
d71518b5 CK |
916 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
917 | if (r) | |
d38ceaf9 | 918 | return r; |
d71518b5 | 919 | |
29efc4f5 | 920 | params.ib = &job->ibs[0]; |
d5fc5e82 | 921 | |
b0456f93 CK |
922 | if (!src && pages_addr) { |
923 | uint64_t *pte; | |
924 | unsigned i; | |
925 | ||
926 | /* Put the PTEs at the end of the IB. */ | |
927 | i = ndw - nptes * 2; | |
928 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
929 | params.src = job->ibs->gpu_addr + i * 4; | |
930 | ||
931 | for (i = 0; i < nptes; ++i) { | |
932 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
933 | AMDGPU_GPU_PAGE_SIZE); | |
934 | pte[i] |= flags; | |
935 | } | |
936 | } | |
937 | ||
3cabaa54 CK |
938 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
939 | if (r) | |
940 | goto error_free; | |
941 | ||
e86f9cee | 942 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
943 | owner); |
944 | if (r) | |
945 | goto error_free; | |
d38ceaf9 | 946 | |
a1e08d3b CK |
947 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
948 | if (r) | |
949 | goto error_free; | |
950 | ||
92696dd5 | 951 | amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags); |
d38ceaf9 | 952 | |
29efc4f5 CK |
953 | amdgpu_ring_pad_ib(ring, params.ib); |
954 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
955 | r = amdgpu_job_submit(job, ring, &vm->entity, |
956 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
957 | if (r) |
958 | goto error_free; | |
d38ceaf9 | 959 | |
bf60efd3 | 960 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
961 | if (fence) { |
962 | fence_put(*fence); | |
963 | *fence = fence_get(f); | |
964 | } | |
281b4223 | 965 | fence_put(f); |
d38ceaf9 | 966 | return 0; |
d5fc5e82 CZ |
967 | |
968 | error_free: | |
d71518b5 | 969 | amdgpu_job_free(job); |
4af9f07c | 970 | return r; |
d38ceaf9 AD |
971 | } |
972 | ||
a14faa65 CK |
973 | /** |
974 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
975 | * | |
976 | * @adev: amdgpu_device pointer | |
3cabaa54 | 977 | * @exclusive: fence we need to sync to |
8358dcee CK |
978 | * @gtt_flags: flags as they are used for GTT |
979 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
980 | * @vm: requested vm |
981 | * @mapping: mapped range and flags to use for the update | |
982 | * @addr: addr to set the area to | |
8358dcee | 983 | * @flags: HW flags for the mapping |
a14faa65 CK |
984 | * @fence: optional resulting fence |
985 | * | |
986 | * Split the mapping into smaller chunks so that each update fits | |
987 | * into a SDMA IB. | |
988 | * Returns 0 for success, -EINVAL for failure. | |
989 | */ | |
990 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
3cabaa54 | 991 | struct fence *exclusive, |
a14faa65 | 992 | uint32_t gtt_flags, |
8358dcee | 993 | dma_addr_t *pages_addr, |
a14faa65 CK |
994 | struct amdgpu_vm *vm, |
995 | struct amdgpu_bo_va_mapping *mapping, | |
fa3ab3c7 CK |
996 | uint32_t flags, uint64_t addr, |
997 | struct fence **fence) | |
a14faa65 CK |
998 | { |
999 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
1000 | ||
fa3ab3c7 | 1001 | uint64_t src = 0, start = mapping->it.start; |
a14faa65 CK |
1002 | int r; |
1003 | ||
1004 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1005 | * but in case of something, we filter the flags in first place | |
1006 | */ | |
1007 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1008 | flags &= ~AMDGPU_PTE_READABLE; | |
1009 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1010 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1011 | ||
1012 | trace_amdgpu_vm_bo_update(mapping); | |
1013 | ||
8358dcee | 1014 | if (pages_addr) { |
fa3ab3c7 CK |
1015 | if (flags == gtt_flags) |
1016 | src = adev->gart.table_addr + (addr >> 12) * 8; | |
fa3ab3c7 CK |
1017 | addr = 0; |
1018 | } | |
a14faa65 CK |
1019 | addr += mapping->offset; |
1020 | ||
8358dcee | 1021 | if (!pages_addr || src) |
3cabaa54 CK |
1022 | return amdgpu_vm_bo_update_mapping(adev, exclusive, |
1023 | src, pages_addr, vm, | |
a14faa65 CK |
1024 | start, mapping->it.last, |
1025 | flags, addr, fence); | |
1026 | ||
1027 | while (start != mapping->it.last + 1) { | |
1028 | uint64_t last; | |
1029 | ||
fb29b57c | 1030 | last = min((uint64_t)mapping->it.last, start + max_size - 1); |
3cabaa54 CK |
1031 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1032 | src, pages_addr, vm, | |
a14faa65 CK |
1033 | start, last, flags, addr, |
1034 | fence); | |
1035 | if (r) | |
1036 | return r; | |
1037 | ||
1038 | start = last + 1; | |
fb29b57c | 1039 | addr += max_size * AMDGPU_GPU_PAGE_SIZE; |
a14faa65 CK |
1040 | } |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
d38ceaf9 AD |
1045 | /** |
1046 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1047 | * | |
1048 | * @adev: amdgpu_device pointer | |
1049 | * @bo_va: requested BO and VM object | |
1050 | * @mem: ttm mem | |
1051 | * | |
1052 | * Fill in the page table entries for @bo_va. | |
1053 | * Returns 0 for success, -EINVAL for failure. | |
1054 | * | |
1055 | * Object have to be reserved and mutex must be locked! | |
1056 | */ | |
1057 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1058 | struct amdgpu_bo_va *bo_va, | |
1059 | struct ttm_mem_reg *mem) | |
1060 | { | |
1061 | struct amdgpu_vm *vm = bo_va->vm; | |
1062 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1063 | dma_addr_t *pages_addr = NULL; |
fa3ab3c7 | 1064 | uint32_t gtt_flags, flags; |
3cabaa54 | 1065 | struct fence *exclusive; |
d38ceaf9 AD |
1066 | uint64_t addr; |
1067 | int r; | |
1068 | ||
1069 | if (mem) { | |
8358dcee CK |
1070 | struct ttm_dma_tt *ttm; |
1071 | ||
b7d698d7 | 1072 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
1073 | switch (mem->mem_type) { |
1074 | case TTM_PL_TT: | |
8358dcee CK |
1075 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1076 | ttm_dma_tt, ttm); | |
1077 | pages_addr = ttm->dma_address; | |
9ab21462 CK |
1078 | break; |
1079 | ||
1080 | case TTM_PL_VRAM: | |
d38ceaf9 | 1081 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
1082 | break; |
1083 | ||
1084 | default: | |
1085 | break; | |
1086 | } | |
3cabaa54 CK |
1087 | |
1088 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); | |
d38ceaf9 AD |
1089 | } else { |
1090 | addr = 0; | |
3cabaa54 | 1091 | exclusive = NULL; |
d38ceaf9 AD |
1092 | } |
1093 | ||
d38ceaf9 | 1094 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
fa3ab3c7 | 1095 | gtt_flags = (adev == bo_va->bo->adev) ? flags : 0; |
d38ceaf9 | 1096 | |
7fc11959 CK |
1097 | spin_lock(&vm->status_lock); |
1098 | if (!list_empty(&bo_va->vm_status)) | |
1099 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1100 | spin_unlock(&vm->status_lock); | |
1101 | ||
1102 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1103 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1104 | gtt_flags, pages_addr, vm, | |
8358dcee CK |
1105 | mapping, flags, addr, |
1106 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
1107 | if (r) |
1108 | return r; | |
1109 | } | |
1110 | ||
d6c10f6b CK |
1111 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1112 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1113 | trace_amdgpu_vm_bo_mapping(mapping); | |
1114 | ||
1115 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1116 | trace_amdgpu_vm_bo_mapping(mapping); | |
1117 | } | |
1118 | ||
d38ceaf9 | 1119 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1120 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1121 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
1122 | if (!mem) |
1123 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
1124 | spin_unlock(&vm->status_lock); |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | /** | |
1130 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1131 | * | |
1132 | * @adev: amdgpu_device pointer | |
1133 | * @vm: requested vm | |
1134 | * | |
1135 | * Make sure all freed BOs are cleared in the PT. | |
1136 | * Returns 0 for success. | |
1137 | * | |
1138 | * PTs have to be reserved and mutex must be locked! | |
1139 | */ | |
1140 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
1141 | struct amdgpu_vm *vm) | |
1142 | { | |
1143 | struct amdgpu_bo_va_mapping *mapping; | |
1144 | int r; | |
1145 | ||
1146 | while (!list_empty(&vm->freed)) { | |
1147 | mapping = list_first_entry(&vm->freed, | |
1148 | struct amdgpu_bo_va_mapping, list); | |
1149 | list_del(&mapping->list); | |
e17841b9 | 1150 | |
3cabaa54 | 1151 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping, |
fa3ab3c7 | 1152 | 0, 0, NULL); |
d38ceaf9 AD |
1153 | kfree(mapping); |
1154 | if (r) | |
1155 | return r; | |
1156 | ||
1157 | } | |
1158 | return 0; | |
1159 | ||
1160 | } | |
1161 | ||
1162 | /** | |
1163 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1164 | * | |
1165 | * @adev: amdgpu_device pointer | |
1166 | * @vm: requested vm | |
1167 | * | |
1168 | * Make sure all invalidated BOs are cleared in the PT. | |
1169 | * Returns 0 for success. | |
1170 | * | |
1171 | * PTs have to be reserved and mutex must be locked! | |
1172 | */ | |
1173 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1174 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1175 | { |
cfe2c978 | 1176 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1177 | int r = 0; |
d38ceaf9 AD |
1178 | |
1179 | spin_lock(&vm->status_lock); | |
1180 | while (!list_empty(&vm->invalidated)) { | |
1181 | bo_va = list_first_entry(&vm->invalidated, | |
1182 | struct amdgpu_bo_va, vm_status); | |
1183 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1184 | |
d38ceaf9 AD |
1185 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
1186 | if (r) | |
1187 | return r; | |
1188 | ||
1189 | spin_lock(&vm->status_lock); | |
1190 | } | |
1191 | spin_unlock(&vm->status_lock); | |
1192 | ||
cfe2c978 | 1193 | if (bo_va) |
bb1e38a4 | 1194 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1195 | |
1196 | return r; | |
d38ceaf9 AD |
1197 | } |
1198 | ||
1199 | /** | |
1200 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1201 | * | |
1202 | * @adev: amdgpu_device pointer | |
1203 | * @vm: requested vm | |
1204 | * @bo: amdgpu buffer object | |
1205 | * | |
8843dbbb | 1206 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1207 | * Add @bo to the list of bos associated with the vm |
1208 | * Returns newly added bo_va or NULL for failure | |
1209 | * | |
1210 | * Object has to be reserved! | |
1211 | */ | |
1212 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1213 | struct amdgpu_vm *vm, | |
1214 | struct amdgpu_bo *bo) | |
1215 | { | |
1216 | struct amdgpu_bo_va *bo_va; | |
1217 | ||
1218 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1219 | if (bo_va == NULL) { | |
1220 | return NULL; | |
1221 | } | |
1222 | bo_va->vm = vm; | |
1223 | bo_va->bo = bo; | |
d38ceaf9 AD |
1224 | bo_va->ref_count = 1; |
1225 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1226 | INIT_LIST_HEAD(&bo_va->valids); |
1227 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1228 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1229 | |
d38ceaf9 | 1230 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1231 | |
1232 | return bo_va; | |
1233 | } | |
1234 | ||
1235 | /** | |
1236 | * amdgpu_vm_bo_map - map bo inside a vm | |
1237 | * | |
1238 | * @adev: amdgpu_device pointer | |
1239 | * @bo_va: bo_va to store the address | |
1240 | * @saddr: where to map the BO | |
1241 | * @offset: requested offset in the BO | |
1242 | * @flags: attributes of pages (read/write/valid/etc.) | |
1243 | * | |
1244 | * Add a mapping of the BO at the specefied addr into the VM. | |
1245 | * Returns 0 for success, error for failure. | |
1246 | * | |
49b02b18 | 1247 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1248 | */ |
1249 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1250 | struct amdgpu_bo_va *bo_va, | |
1251 | uint64_t saddr, uint64_t offset, | |
1252 | uint64_t size, uint32_t flags) | |
1253 | { | |
1254 | struct amdgpu_bo_va_mapping *mapping; | |
1255 | struct amdgpu_vm *vm = bo_va->vm; | |
1256 | struct interval_tree_node *it; | |
1257 | unsigned last_pfn, pt_idx; | |
1258 | uint64_t eaddr; | |
1259 | int r; | |
1260 | ||
0be52de9 CK |
1261 | /* validate the parameters */ |
1262 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1263 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1264 | return -EINVAL; |
0be52de9 | 1265 | |
d38ceaf9 | 1266 | /* make sure object fit at this offset */ |
005ae95e | 1267 | eaddr = saddr + size - 1; |
49b02b18 | 1268 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1269 | return -EINVAL; |
d38ceaf9 AD |
1270 | |
1271 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1272 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1273 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1274 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1275 | return -EINVAL; |
1276 | } | |
1277 | ||
d38ceaf9 AD |
1278 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1279 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1280 | ||
005ae95e | 1281 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
d38ceaf9 AD |
1282 | if (it) { |
1283 | struct amdgpu_bo_va_mapping *tmp; | |
1284 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1285 | /* bo and tmp overlap, invalid addr */ | |
1286 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1287 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1288 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1289 | r = -EINVAL; |
f48b2659 | 1290 | goto error; |
d38ceaf9 AD |
1291 | } |
1292 | ||
1293 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1294 | if (!mapping) { | |
d38ceaf9 | 1295 | r = -ENOMEM; |
f48b2659 | 1296 | goto error; |
d38ceaf9 AD |
1297 | } |
1298 | ||
1299 | INIT_LIST_HEAD(&mapping->list); | |
1300 | mapping->it.start = saddr; | |
005ae95e | 1301 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1302 | mapping->offset = offset; |
1303 | mapping->flags = flags; | |
1304 | ||
7fc11959 | 1305 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 AD |
1306 | interval_tree_insert(&mapping->it, &vm->va); |
1307 | ||
1308 | /* Make sure the page tables are allocated */ | |
1309 | saddr >>= amdgpu_vm_block_size; | |
1310 | eaddr >>= amdgpu_vm_block_size; | |
1311 | ||
1312 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1313 | ||
1314 | if (eaddr > vm->max_pde_used) | |
1315 | vm->max_pde_used = eaddr; | |
1316 | ||
d38ceaf9 AD |
1317 | /* walk over the address space and allocate the page tables */ |
1318 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1319 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1320 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1321 | struct amdgpu_bo *pt; |
1322 | ||
ee1782c3 CK |
1323 | entry = &vm->page_tables[pt_idx].entry; |
1324 | if (entry->robj) | |
d38ceaf9 AD |
1325 | continue; |
1326 | ||
d38ceaf9 AD |
1327 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1328 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d | 1329 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f CZ |
1330 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
1331 | AMDGPU_GEM_CREATE_SHADOW, | |
bf60efd3 | 1332 | NULL, resv, &pt); |
49b02b18 | 1333 | if (r) |
d38ceaf9 | 1334 | goto error_free; |
49b02b18 | 1335 | |
82b9c55b CK |
1336 | /* Keep a reference to the page table to avoid freeing |
1337 | * them up in the wrong order. | |
1338 | */ | |
1339 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1340 | ||
2bd9ccfa | 1341 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 AD |
1342 | if (r) { |
1343 | amdgpu_bo_unref(&pt); | |
1344 | goto error_free; | |
1345 | } | |
1346 | ||
ee1782c3 | 1347 | entry->robj = pt; |
ee1782c3 CK |
1348 | entry->priority = 0; |
1349 | entry->tv.bo = &entry->robj->tbo; | |
1350 | entry->tv.shared = true; | |
2f568dbd | 1351 | entry->user_pages = NULL; |
d38ceaf9 | 1352 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1353 | } |
1354 | ||
d38ceaf9 AD |
1355 | return 0; |
1356 | ||
1357 | error_free: | |
d38ceaf9 AD |
1358 | list_del(&mapping->list); |
1359 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1360 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1361 | kfree(mapping); |
1362 | ||
f48b2659 | 1363 | error: |
d38ceaf9 AD |
1364 | return r; |
1365 | } | |
1366 | ||
1367 | /** | |
1368 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1369 | * | |
1370 | * @adev: amdgpu_device pointer | |
1371 | * @bo_va: bo_va to remove the address from | |
1372 | * @saddr: where to the BO is mapped | |
1373 | * | |
1374 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1375 | * Returns 0 for success, error for failure. | |
1376 | * | |
49b02b18 | 1377 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1378 | */ |
1379 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1380 | struct amdgpu_bo_va *bo_va, | |
1381 | uint64_t saddr) | |
1382 | { | |
1383 | struct amdgpu_bo_va_mapping *mapping; | |
1384 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1385 | bool valid = true; |
d38ceaf9 | 1386 | |
6c7fc503 | 1387 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1388 | |
7fc11959 | 1389 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1390 | if (mapping->it.start == saddr) |
1391 | break; | |
1392 | } | |
1393 | ||
7fc11959 CK |
1394 | if (&mapping->list == &bo_va->valids) { |
1395 | valid = false; | |
1396 | ||
1397 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1398 | if (mapping->it.start == saddr) | |
1399 | break; | |
1400 | } | |
1401 | ||
32b41ac2 | 1402 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1403 | return -ENOENT; |
d38ceaf9 | 1404 | } |
32b41ac2 | 1405 | |
d38ceaf9 AD |
1406 | list_del(&mapping->list); |
1407 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1408 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1409 | |
e17841b9 | 1410 | if (valid) |
d38ceaf9 | 1411 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1412 | else |
d38ceaf9 | 1413 | kfree(mapping); |
d38ceaf9 AD |
1414 | |
1415 | return 0; | |
1416 | } | |
1417 | ||
1418 | /** | |
1419 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1420 | * | |
1421 | * @adev: amdgpu_device pointer | |
1422 | * @bo_va: requested bo_va | |
1423 | * | |
8843dbbb | 1424 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1425 | * |
1426 | * Object have to be reserved! | |
1427 | */ | |
1428 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1429 | struct amdgpu_bo_va *bo_va) | |
1430 | { | |
1431 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1432 | struct amdgpu_vm *vm = bo_va->vm; | |
1433 | ||
1434 | list_del(&bo_va->bo_list); | |
1435 | ||
d38ceaf9 AD |
1436 | spin_lock(&vm->status_lock); |
1437 | list_del(&bo_va->vm_status); | |
1438 | spin_unlock(&vm->status_lock); | |
1439 | ||
7fc11959 | 1440 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1441 | list_del(&mapping->list); |
1442 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1443 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1444 | list_add(&mapping->list, &vm->freed); |
1445 | } | |
1446 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1447 | list_del(&mapping->list); | |
1448 | interval_tree_remove(&mapping->it, &vm->va); | |
1449 | kfree(mapping); | |
d38ceaf9 | 1450 | } |
32b41ac2 | 1451 | |
bb1e38a4 | 1452 | fence_put(bo_va->last_pt_update); |
d38ceaf9 | 1453 | kfree(bo_va); |
d38ceaf9 AD |
1454 | } |
1455 | ||
1456 | /** | |
1457 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1458 | * | |
1459 | * @adev: amdgpu_device pointer | |
1460 | * @vm: requested vm | |
1461 | * @bo: amdgpu buffer object | |
1462 | * | |
8843dbbb | 1463 | * Mark @bo as invalid. |
d38ceaf9 AD |
1464 | */ |
1465 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1466 | struct amdgpu_bo *bo) | |
1467 | { | |
1468 | struct amdgpu_bo_va *bo_va; | |
1469 | ||
1470 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1471 | spin_lock(&bo_va->vm->status_lock); |
1472 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1473 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1474 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1475 | } |
1476 | } | |
1477 | ||
1478 | /** | |
1479 | * amdgpu_vm_init - initialize a vm instance | |
1480 | * | |
1481 | * @adev: amdgpu_device pointer | |
1482 | * @vm: requested vm | |
1483 | * | |
8843dbbb | 1484 | * Init @vm fields. |
d38ceaf9 AD |
1485 | */ |
1486 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1487 | { | |
1488 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1489 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1490 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1491 | unsigned ring_instance; |
1492 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1493 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1494 | int i, r; |
1495 | ||
bcb1ba35 CK |
1496 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1497 | vm->ids[i] = NULL; | |
d38ceaf9 | 1498 | vm->va = RB_ROOT; |
031e2983 | 1499 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
d38ceaf9 AD |
1500 | spin_lock_init(&vm->status_lock); |
1501 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1502 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1503 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 1504 | |
d38ceaf9 AD |
1505 | pd_size = amdgpu_vm_directory_size(adev); |
1506 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1507 | ||
1508 | /* allocate page table array */ | |
9571e1d8 | 1509 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1510 | if (vm->page_tables == NULL) { |
1511 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1512 | return -ENOMEM; | |
1513 | } | |
1514 | ||
2bd9ccfa | 1515 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1516 | |
1517 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1518 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1519 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1520 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1521 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1522 | rq, amdgpu_sched_jobs); | |
1523 | if (r) | |
1524 | return r; | |
1525 | ||
05906dec BN |
1526 | vm->page_directory_fence = NULL; |
1527 | ||
d38ceaf9 | 1528 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d | 1529 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f CZ |
1530 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
1531 | AMDGPU_GEM_CREATE_SHADOW, | |
72d7668b | 1532 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1533 | if (r) |
2bd9ccfa CK |
1534 | goto error_free_sched_entity; |
1535 | ||
ef9f0a83 | 1536 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1537 | if (r) |
1538 | goto error_free_page_directory; | |
1539 | ||
1540 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
ef9f0a83 | 1541 | amdgpu_bo_unreserve(vm->page_directory); |
2bd9ccfa CK |
1542 | if (r) |
1543 | goto error_free_page_directory; | |
5a712a87 | 1544 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
d38ceaf9 AD |
1545 | |
1546 | return 0; | |
2bd9ccfa CK |
1547 | |
1548 | error_free_page_directory: | |
1549 | amdgpu_bo_unref(&vm->page_directory); | |
1550 | vm->page_directory = NULL; | |
1551 | ||
1552 | error_free_sched_entity: | |
1553 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1554 | ||
1555 | return r; | |
d38ceaf9 AD |
1556 | } |
1557 | ||
1558 | /** | |
1559 | * amdgpu_vm_fini - tear down a vm instance | |
1560 | * | |
1561 | * @adev: amdgpu_device pointer | |
1562 | * @vm: requested vm | |
1563 | * | |
8843dbbb | 1564 | * Tear down @vm. |
d38ceaf9 AD |
1565 | * Unbind the VM and remove all bos from the vm bo list |
1566 | */ | |
1567 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1568 | { | |
1569 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1570 | int i; | |
1571 | ||
2d55e45a | 1572 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1573 | |
d38ceaf9 AD |
1574 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1575 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1576 | } | |
1577 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1578 | list_del(&mapping->list); | |
1579 | interval_tree_remove(&mapping->it, &vm->va); | |
1580 | kfree(mapping); | |
1581 | } | |
1582 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1583 | list_del(&mapping->list); | |
1584 | kfree(mapping); | |
1585 | } | |
1586 | ||
1baa439f CZ |
1587 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) { |
1588 | if (vm->page_tables[i].entry.robj && | |
1589 | vm->page_tables[i].entry.robj->shadow) | |
1590 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj->shadow); | |
ee1782c3 | 1591 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
1baa439f | 1592 | } |
9571e1d8 | 1593 | drm_free_large(vm->page_tables); |
d38ceaf9 | 1594 | |
1baa439f CZ |
1595 | if (vm->page_directory->shadow) |
1596 | amdgpu_bo_unref(&vm->page_directory->shadow); | |
d38ceaf9 | 1597 | amdgpu_bo_unref(&vm->page_directory); |
05906dec | 1598 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1599 | } |
ea89f8c9 | 1600 | |
a9a78b32 CK |
1601 | /** |
1602 | * amdgpu_vm_manager_init - init the VM manager | |
1603 | * | |
1604 | * @adev: amdgpu_device pointer | |
1605 | * | |
1606 | * Initialize the VM manager structures | |
1607 | */ | |
1608 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1609 | { | |
1610 | unsigned i; | |
1611 | ||
1612 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1613 | ||
1614 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1615 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1616 | amdgpu_vm_reset_id(adev, i); | |
832a902f | 1617 | amdgpu_sync_create(&adev->vm_manager.ids[i].active); |
a9a78b32 CK |
1618 | list_add_tail(&adev->vm_manager.ids[i].list, |
1619 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1620 | } |
2d55e45a | 1621 | |
1fbb2e92 CK |
1622 | adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); |
1623 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | |
1624 | adev->vm_manager.seqno[i] = 0; | |
1625 | ||
2d55e45a | 1626 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 1627 | atomic64_set(&adev->vm_manager.client_counter, 0); |
a9a78b32 CK |
1628 | } |
1629 | ||
ea89f8c9 CK |
1630 | /** |
1631 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1632 | * | |
1633 | * @adev: amdgpu_device pointer | |
1634 | * | |
1635 | * Cleanup the VM manager and free resources. | |
1636 | */ | |
1637 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1638 | { | |
1639 | unsigned i; | |
1640 | ||
bcb1ba35 CK |
1641 | for (i = 0; i < AMDGPU_NUM_VM; ++i) { |
1642 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; | |
1643 | ||
832a902f CK |
1644 | fence_put(adev->vm_manager.ids[i].first); |
1645 | amdgpu_sync_free(&adev->vm_manager.ids[i].active); | |
bcb1ba35 CK |
1646 | fence_put(id->flushed_updates); |
1647 | } | |
ea89f8c9 | 1648 | } |