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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
d38ceaf9 AD |
30 | #include <drm/drmP.h> |
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
33 | #include "amdgpu_trace.h" | |
34 | ||
35 | /* | |
36 | * GPUVM | |
37 | * GPUVM is similar to the legacy gart on older asics, however | |
38 | * rather than there being a single global gart table | |
39 | * for the entire GPU, there are multiple VM page tables active | |
40 | * at any given time. The VM page tables can contain a mix | |
41 | * vram pages and system memory pages and system memory pages | |
42 | * can be mapped as snooped (cached system pages) or unsnooped | |
43 | * (uncached system pages). | |
44 | * Each VM has an ID associated with it and there is a page table | |
45 | * associated with each VMID. When execting a command buffer, | |
46 | * the kernel tells the the ring what VMID to use for that command | |
47 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
48 | * The userspace drivers maintain their own address space and the kernel | |
49 | * sets up their pages tables accordingly when they submit their | |
50 | * command buffers and a VMID is assigned. | |
51 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
52 | * SI supports 16. | |
53 | */ | |
54 | ||
a9f87f64 CK |
55 | #define START(node) ((node)->start) |
56 | #define LAST(node) ((node)->last) | |
57 | ||
58 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
59 | START, LAST, static, amdgpu_vm_it) | |
60 | ||
61 | #undef START | |
62 | #undef LAST | |
63 | ||
f4833c4f HK |
64 | /* Local structure. Encapsulate some VM table update parameters to reduce |
65 | * the number of function parameters | |
66 | */ | |
29efc4f5 | 67 | struct amdgpu_pte_update_params { |
27c5f36f CK |
68 | /* amdgpu device we do this update for */ |
69 | struct amdgpu_device *adev; | |
49ac8a24 CK |
70 | /* optional amdgpu_vm we do this update for */ |
71 | struct amdgpu_vm *vm; | |
f4833c4f HK |
72 | /* address where to copy page table entries from */ |
73 | uint64_t src; | |
f4833c4f HK |
74 | /* indirect buffer to fill with commands */ |
75 | struct amdgpu_ib *ib; | |
afef8b8f CK |
76 | /* Function which actually does the update */ |
77 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
78 | uint64_t addr, unsigned count, uint32_t incr, | |
6b777607 | 79 | uint64_t flags); |
4c7e8855 CZ |
80 | /* indicate update pt or its shadow */ |
81 | bool shadow; | |
f4833c4f HK |
82 | }; |
83 | ||
284710fa CK |
84 | /* Helper to disable partial resident texture feature from a fence callback */ |
85 | struct amdgpu_prt_cb { | |
86 | struct amdgpu_device *adev; | |
87 | struct dma_fence_cb cb; | |
88 | }; | |
89 | ||
d38ceaf9 | 90 | /** |
72a7ec5c | 91 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
92 | * |
93 | * @adev: amdgpu_device pointer | |
94 | * | |
72a7ec5c | 95 | * Calculate the number of entries in a page directory or page table. |
d38ceaf9 | 96 | */ |
72a7ec5c CK |
97 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
98 | unsigned level) | |
d38ceaf9 | 99 | { |
72a7ec5c CK |
100 | if (level == 0) |
101 | /* For the root directory */ | |
102 | return adev->vm_manager.max_pfn >> | |
36b32a68 ZJ |
103 | (adev->vm_manager.block_size * |
104 | adev->vm_manager.num_level); | |
72a7ec5c CK |
105 | else if (level == adev->vm_manager.num_level) |
106 | /* For the page tables on the leaves */ | |
36b32a68 | 107 | return AMDGPU_VM_PTE_COUNT(adev); |
72a7ec5c CK |
108 | else |
109 | /* Everything in between */ | |
36b32a68 | 110 | return 1 << adev->vm_manager.block_size; |
d38ceaf9 AD |
111 | } |
112 | ||
113 | /** | |
72a7ec5c | 114 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
115 | * |
116 | * @adev: amdgpu_device pointer | |
117 | * | |
72a7ec5c | 118 | * Calculate the size of the BO for a page directory or page table in bytes. |
d38ceaf9 | 119 | */ |
72a7ec5c | 120 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 121 | { |
72a7ec5c | 122 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
123 | } |
124 | ||
125 | /** | |
56467ebf | 126 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
127 | * |
128 | * @vm: vm providing the BOs | |
3c0eea6c | 129 | * @validated: head of validation list |
56467ebf | 130 | * @entry: entry to add |
d38ceaf9 AD |
131 | * |
132 | * Add the page directory to the list of BOs to | |
56467ebf | 133 | * validate for command submission. |
d38ceaf9 | 134 | */ |
56467ebf CK |
135 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
136 | struct list_head *validated, | |
137 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 138 | { |
67003a15 | 139 | entry->robj = vm->root.bo; |
56467ebf | 140 | entry->priority = 0; |
67003a15 | 141 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 142 | entry->tv.shared = true; |
2f568dbd | 143 | entry->user_pages = NULL; |
56467ebf CK |
144 | list_add(&entry->tv.head, validated); |
145 | } | |
d38ceaf9 | 146 | |
670fecc8 CK |
147 | /** |
148 | * amdgpu_vm_validate_layer - validate a single page table level | |
149 | * | |
150 | * @parent: parent page table level | |
151 | * @validate: callback to do the validation | |
152 | * @param: parameter for the validation callback | |
153 | * | |
154 | * Validate the page table BOs on command submission if neccessary. | |
155 | */ | |
156 | static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent, | |
157 | int (*validate)(void *, struct amdgpu_bo *), | |
158 | void *param) | |
159 | { | |
160 | unsigned i; | |
161 | int r; | |
162 | ||
163 | if (!parent->entries) | |
164 | return 0; | |
165 | ||
166 | for (i = 0; i <= parent->last_entry_used; ++i) { | |
167 | struct amdgpu_vm_pt *entry = &parent->entries[i]; | |
168 | ||
169 | if (!entry->bo) | |
170 | continue; | |
171 | ||
172 | r = validate(param, entry->bo); | |
173 | if (r) | |
174 | return r; | |
175 | ||
176 | /* | |
177 | * Recurse into the sub directory. This is harmless because we | |
178 | * have only a maximum of 5 layers. | |
179 | */ | |
180 | r = amdgpu_vm_validate_level(entry, validate, param); | |
181 | if (r) | |
182 | return r; | |
183 | } | |
184 | ||
185 | return r; | |
186 | } | |
187 | ||
56467ebf | 188 | /** |
f7da30d9 | 189 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
56467ebf | 190 | * |
5a712a87 | 191 | * @adev: amdgpu device pointer |
56467ebf | 192 | * @vm: vm providing the BOs |
f7da30d9 CK |
193 | * @validate: callback to do the validation |
194 | * @param: parameter for the validation callback | |
d38ceaf9 | 195 | * |
f7da30d9 | 196 | * Validate the page table BOs on command submission if neccessary. |
d38ceaf9 | 197 | */ |
f7da30d9 CK |
198 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
199 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
200 | void *param) | |
d38ceaf9 | 201 | { |
5a712a87 | 202 | uint64_t num_evictions; |
d38ceaf9 | 203 | |
5a712a87 CK |
204 | /* We only need to validate the page tables |
205 | * if they aren't already valid. | |
206 | */ | |
207 | num_evictions = atomic64_read(&adev->num_evictions); | |
208 | if (num_evictions == vm->last_eviction_counter) | |
f7da30d9 | 209 | return 0; |
5a712a87 | 210 | |
670fecc8 | 211 | return amdgpu_vm_validate_level(&vm->root, validate, param); |
eceb8a15 CK |
212 | } |
213 | ||
214 | /** | |
d711e139 | 215 | * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail |
eceb8a15 CK |
216 | * |
217 | * @adev: amdgpu device instance | |
218 | * @vm: vm providing the BOs | |
219 | * | |
220 | * Move the PT BOs to the tail of the LRU. | |
221 | */ | |
d711e139 | 222 | static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent) |
eceb8a15 | 223 | { |
eceb8a15 CK |
224 | unsigned i; |
225 | ||
d711e139 CK |
226 | if (!parent->entries) |
227 | return; | |
eceb8a15 | 228 | |
d711e139 CK |
229 | for (i = 0; i <= parent->last_entry_used; ++i) { |
230 | struct amdgpu_vm_pt *entry = &parent->entries[i]; | |
231 | ||
232 | if (!entry->bo) | |
eceb8a15 CK |
233 | continue; |
234 | ||
d711e139 CK |
235 | ttm_bo_move_to_lru_tail(&entry->bo->tbo); |
236 | amdgpu_vm_move_level_in_lru(entry); | |
eceb8a15 | 237 | } |
d711e139 CK |
238 | } |
239 | ||
240 | /** | |
241 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
242 | * | |
243 | * @adev: amdgpu device instance | |
244 | * @vm: vm providing the BOs | |
245 | * | |
246 | * Move the PT BOs to the tail of the LRU. | |
247 | */ | |
248 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
249 | struct amdgpu_vm *vm) | |
250 | { | |
251 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
252 | ||
253 | spin_lock(&glob->lru_lock); | |
254 | amdgpu_vm_move_level_in_lru(&vm->root); | |
eceb8a15 | 255 | spin_unlock(&glob->lru_lock); |
d38ceaf9 AD |
256 | } |
257 | ||
f566ceb1 CK |
258 | /** |
259 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels | |
260 | * | |
261 | * @adev: amdgpu_device pointer | |
262 | * @vm: requested vm | |
263 | * @saddr: start of the address range | |
264 | * @eaddr: end of the address range | |
265 | * | |
266 | * Make sure the page directories and page tables are allocated | |
267 | */ | |
268 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
269 | struct amdgpu_vm *vm, | |
270 | struct amdgpu_vm_pt *parent, | |
271 | uint64_t saddr, uint64_t eaddr, | |
272 | unsigned level) | |
273 | { | |
274 | unsigned shift = (adev->vm_manager.num_level - level) * | |
36b32a68 | 275 | adev->vm_manager.block_size; |
f566ceb1 CK |
276 | unsigned pt_idx, from, to; |
277 | int r; | |
278 | ||
279 | if (!parent->entries) { | |
280 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
281 | ||
282 | parent->entries = drm_calloc_large(num_entries, | |
283 | sizeof(struct amdgpu_vm_pt)); | |
284 | if (!parent->entries) | |
285 | return -ENOMEM; | |
286 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
287 | } | |
288 | ||
1866bac8 FK |
289 | from = saddr >> shift; |
290 | to = eaddr >> shift; | |
291 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
292 | to >= amdgpu_vm_num_entries(adev, level)) | |
293 | return -EINVAL; | |
f566ceb1 CK |
294 | |
295 | if (to > parent->last_entry_used) | |
296 | parent->last_entry_used = to; | |
297 | ||
298 | ++level; | |
1866bac8 FK |
299 | saddr = saddr & ((1 << shift) - 1); |
300 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 CK |
301 | |
302 | /* walk over the address space and allocate the page tables */ | |
303 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
304 | struct reservation_object *resv = vm->root.bo->tbo.resv; | |
305 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
306 | struct amdgpu_bo *pt; | |
307 | ||
308 | if (!entry->bo) { | |
309 | r = amdgpu_bo_create(adev, | |
310 | amdgpu_vm_bo_size(adev, level), | |
311 | AMDGPU_GPU_PAGE_SIZE, true, | |
312 | AMDGPU_GEM_DOMAIN_VRAM, | |
313 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
314 | AMDGPU_GEM_CREATE_SHADOW | | |
315 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
316 | AMDGPU_GEM_CREATE_VRAM_CLEARED, | |
317 | NULL, resv, &pt); | |
318 | if (r) | |
319 | return r; | |
320 | ||
321 | /* Keep a reference to the root directory to avoid | |
322 | * freeing them up in the wrong order. | |
323 | */ | |
324 | pt->parent = amdgpu_bo_ref(vm->root.bo); | |
325 | ||
326 | entry->bo = pt; | |
327 | entry->addr = 0; | |
328 | } | |
329 | ||
330 | if (level < adev->vm_manager.num_level) { | |
1866bac8 FK |
331 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
332 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
333 | ((1 << shift) - 1); | |
334 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
335 | sub_eaddr, level); | |
f566ceb1 CK |
336 | if (r) |
337 | return r; | |
338 | } | |
339 | } | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
663e4577 CK |
344 | /** |
345 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
346 | * | |
347 | * @adev: amdgpu_device pointer | |
348 | * @vm: VM to allocate page tables for | |
349 | * @saddr: Start address which needs to be allocated | |
350 | * @size: Size from start address we need. | |
351 | * | |
352 | * Make sure the page tables are allocated. | |
353 | */ | |
354 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
355 | struct amdgpu_vm *vm, | |
356 | uint64_t saddr, uint64_t size) | |
357 | { | |
22770e5a | 358 | uint64_t last_pfn; |
663e4577 | 359 | uint64_t eaddr; |
663e4577 CK |
360 | |
361 | /* validate the parameters */ | |
362 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
363 | return -EINVAL; | |
364 | ||
365 | eaddr = saddr + size - 1; | |
366 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
367 | if (last_pfn >= adev->vm_manager.max_pfn) { | |
22770e5a | 368 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", |
663e4577 CK |
369 | last_pfn, adev->vm_manager.max_pfn); |
370 | return -EINVAL; | |
371 | } | |
372 | ||
373 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
374 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
375 | ||
f566ceb1 | 376 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); |
663e4577 CK |
377 | } |
378 | ||
641e9400 CK |
379 | /** |
380 | * amdgpu_vm_had_gpu_reset - check if reset occured since last use | |
381 | * | |
382 | * @adev: amdgpu_device pointer | |
383 | * @id: VMID structure | |
384 | * | |
385 | * Check if GPU reset occured since last use of the VMID. | |
386 | */ | |
387 | static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev, | |
388 | struct amdgpu_vm_id *id) | |
192b7dcb CZ |
389 | { |
390 | return id->current_gpu_reset_count != | |
641e9400 | 391 | atomic_read(&adev->gpu_reset_counter); |
192b7dcb CZ |
392 | } |
393 | ||
7a63eb23 CZ |
394 | static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub) |
395 | { | |
396 | return !!vm->reserved_vmid[vmhub]; | |
397 | } | |
398 | ||
399 | /* idr_mgr->lock must be held */ | |
400 | static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, | |
401 | struct amdgpu_ring *ring, | |
402 | struct amdgpu_sync *sync, | |
403 | struct dma_fence *fence, | |
404 | struct amdgpu_job *job) | |
405 | { | |
406 | struct amdgpu_device *adev = ring->adev; | |
407 | unsigned vmhub = ring->funcs->vmhub; | |
408 | uint64_t fence_context = adev->fence_context + ring->idx; | |
409 | struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub]; | |
410 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
411 | struct dma_fence *updates = sync->last_vm_update; | |
412 | int r = 0; | |
413 | struct dma_fence *flushed, *tmp; | |
414 | bool needs_flush = false; | |
415 | ||
416 | flushed = id->flushed_updates; | |
417 | if ((amdgpu_vm_had_gpu_reset(adev, id)) || | |
418 | (atomic64_read(&id->owner) != vm->client_id) || | |
419 | (job->vm_pd_addr != id->pd_gpu_addr) || | |
420 | (updates && (!flushed || updates->context != flushed->context || | |
421 | dma_fence_is_later(updates, flushed))) || | |
422 | (!id->last_flush || (id->last_flush->context != fence_context && | |
423 | !dma_fence_is_signaled(id->last_flush)))) { | |
424 | needs_flush = true; | |
425 | /* to prevent one context starved by another context */ | |
426 | id->pd_gpu_addr = 0; | |
427 | tmp = amdgpu_sync_peek_fence(&id->active, ring); | |
428 | if (tmp) { | |
429 | r = amdgpu_sync_fence(adev, sync, tmp); | |
430 | return r; | |
431 | } | |
432 | } | |
433 | ||
434 | /* Good we can use this VMID. Remember this submission as | |
435 | * user of the VMID. | |
436 | */ | |
437 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
438 | if (r) | |
439 | goto out; | |
440 | ||
441 | if (updates && (!flushed || updates->context != flushed->context || | |
442 | dma_fence_is_later(updates, flushed))) { | |
443 | dma_fence_put(id->flushed_updates); | |
444 | id->flushed_updates = dma_fence_get(updates); | |
445 | } | |
446 | id->pd_gpu_addr = job->vm_pd_addr; | |
7a63eb23 CZ |
447 | atomic64_set(&id->owner, vm->client_id); |
448 | job->vm_needs_flush = needs_flush; | |
449 | if (needs_flush) { | |
450 | dma_fence_put(id->last_flush); | |
451 | id->last_flush = NULL; | |
452 | } | |
453 | job->vm_id = id - id_mgr->ids; | |
454 | trace_amdgpu_vm_grab_id(vm, ring, job); | |
455 | out: | |
456 | return r; | |
457 | } | |
458 | ||
d38ceaf9 AD |
459 | /** |
460 | * amdgpu_vm_grab_id - allocate the next free VMID | |
461 | * | |
d38ceaf9 | 462 | * @vm: vm to allocate id for |
7f8a5290 CK |
463 | * @ring: ring we want to submit job to |
464 | * @sync: sync object where we add dependencies | |
94dd0a4a | 465 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 466 | * |
7f8a5290 | 467 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 468 | */ |
7f8a5290 | 469 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
f54d1867 | 470 | struct amdgpu_sync *sync, struct dma_fence *fence, |
fd53be30 | 471 | struct amdgpu_job *job) |
d38ceaf9 | 472 | { |
d38ceaf9 | 473 | struct amdgpu_device *adev = ring->adev; |
2e819849 | 474 | unsigned vmhub = ring->funcs->vmhub; |
7645670d | 475 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
090b767e | 476 | uint64_t fence_context = adev->fence_context + ring->idx; |
f54d1867 | 477 | struct dma_fence *updates = sync->last_vm_update; |
8d76001e | 478 | struct amdgpu_vm_id *id, *idle; |
f54d1867 | 479 | struct dma_fence **fences; |
1fbb2e92 CK |
480 | unsigned i; |
481 | int r = 0; | |
482 | ||
7a63eb23 CZ |
483 | mutex_lock(&id_mgr->lock); |
484 | if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) { | |
485 | r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job); | |
486 | mutex_unlock(&id_mgr->lock); | |
487 | return r; | |
488 | } | |
7645670d | 489 | fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); |
7a63eb23 CZ |
490 | if (!fences) { |
491 | mutex_unlock(&id_mgr->lock); | |
1fbb2e92 | 492 | return -ENOMEM; |
7a63eb23 | 493 | } |
36fd7c5c | 494 | /* Check if we have an idle VMID */ |
1fbb2e92 | 495 | i = 0; |
7645670d | 496 | list_for_each_entry(idle, &id_mgr->ids_lru, list) { |
1fbb2e92 CK |
497 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
498 | if (!fences[i]) | |
36fd7c5c | 499 | break; |
1fbb2e92 | 500 | ++i; |
36fd7c5c CK |
501 | } |
502 | ||
1fbb2e92 | 503 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
7645670d | 504 | if (&idle->list == &id_mgr->ids_lru) { |
1fbb2e92 CK |
505 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
506 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
f54d1867 | 507 | struct dma_fence_array *array; |
1fbb2e92 CK |
508 | unsigned j; |
509 | ||
510 | for (j = 0; j < i; ++j) | |
f54d1867 | 511 | dma_fence_get(fences[j]); |
1fbb2e92 | 512 | |
f54d1867 | 513 | array = dma_fence_array_create(i, fences, fence_context, |
1fbb2e92 CK |
514 | seqno, true); |
515 | if (!array) { | |
516 | for (j = 0; j < i; ++j) | |
f54d1867 | 517 | dma_fence_put(fences[j]); |
1fbb2e92 CK |
518 | kfree(fences); |
519 | r = -ENOMEM; | |
520 | goto error; | |
521 | } | |
522 | ||
523 | ||
524 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
f54d1867 | 525 | dma_fence_put(&array->base); |
1fbb2e92 CK |
526 | if (r) |
527 | goto error; | |
528 | ||
7645670d | 529 | mutex_unlock(&id_mgr->lock); |
1fbb2e92 CK |
530 | return 0; |
531 | ||
532 | } | |
533 | kfree(fences); | |
534 | ||
87c910d8 | 535 | job->vm_needs_flush = false; |
1fbb2e92 | 536 | /* Check if we can use a VMID already assigned to this VM */ |
7645670d | 537 | list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) { |
f54d1867 | 538 | struct dma_fence *flushed; |
87c910d8 | 539 | bool needs_flush = false; |
1fbb2e92 | 540 | |
1fbb2e92 | 541 | /* Check all the prerequisites to using this VMID */ |
641e9400 | 542 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
6adb0513 | 543 | continue; |
1fbb2e92 CK |
544 | |
545 | if (atomic64_read(&id->owner) != vm->client_id) | |
546 | continue; | |
547 | ||
fd53be30 | 548 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
549 | continue; |
550 | ||
87c910d8 CK |
551 | if (!id->last_flush || |
552 | (id->last_flush->context != fence_context && | |
553 | !dma_fence_is_signaled(id->last_flush))) | |
554 | needs_flush = true; | |
1fbb2e92 CK |
555 | |
556 | flushed = id->flushed_updates; | |
87c910d8 CK |
557 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) |
558 | needs_flush = true; | |
559 | ||
560 | /* Concurrent flushes are only possible starting with Vega10 */ | |
561 | if (adev->asic_type < CHIP_VEGA10 && needs_flush) | |
1fbb2e92 CK |
562 | continue; |
563 | ||
3dab83be CK |
564 | /* Good we can use this VMID. Remember this submission as |
565 | * user of the VMID. | |
566 | */ | |
1fbb2e92 CK |
567 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
568 | if (r) | |
569 | goto error; | |
8d76001e | 570 | |
87c910d8 CK |
571 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) { |
572 | dma_fence_put(id->flushed_updates); | |
573 | id->flushed_updates = dma_fence_get(updates); | |
574 | } | |
8d76001e | 575 | |
87c910d8 CK |
576 | if (needs_flush) |
577 | goto needs_flush; | |
578 | else | |
579 | goto no_flush_needed; | |
8d76001e | 580 | |
4f618e73 | 581 | }; |
8d76001e | 582 | |
1fbb2e92 CK |
583 | /* Still no ID to use? Then use the idle one found earlier */ |
584 | id = idle; | |
8e9fbeb5 | 585 | |
1fbb2e92 CK |
586 | /* Remember this submission as user of the VMID */ |
587 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
588 | if (r) |
589 | goto error; | |
94dd0a4a | 590 | |
87c910d8 | 591 | id->pd_gpu_addr = job->vm_pd_addr; |
f54d1867 CW |
592 | dma_fence_put(id->flushed_updates); |
593 | id->flushed_updates = dma_fence_get(updates); | |
0ea54b9b | 594 | atomic64_set(&id->owner, vm->client_id); |
d38ceaf9 | 595 | |
87c910d8 CK |
596 | needs_flush: |
597 | job->vm_needs_flush = true; | |
598 | dma_fence_put(id->last_flush); | |
599 | id->last_flush = NULL; | |
600 | ||
601 | no_flush_needed: | |
602 | list_move_tail(&id->list, &id_mgr->ids_lru); | |
603 | ||
7645670d | 604 | job->vm_id = id - id_mgr->ids; |
c5296d14 | 605 | trace_amdgpu_vm_grab_id(vm, ring, job); |
832a902f CK |
606 | |
607 | error: | |
7645670d | 608 | mutex_unlock(&id_mgr->lock); |
a9a78b32 | 609 | return r; |
d38ceaf9 AD |
610 | } |
611 | ||
1e9ef26f CZ |
612 | static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev, |
613 | struct amdgpu_vm *vm, | |
614 | unsigned vmhub) | |
615 | { | |
616 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
617 | ||
618 | mutex_lock(&id_mgr->lock); | |
619 | if (vm->reserved_vmid[vmhub]) { | |
620 | list_add(&vm->reserved_vmid[vmhub]->list, | |
621 | &id_mgr->ids_lru); | |
622 | vm->reserved_vmid[vmhub] = NULL; | |
c3505770 | 623 | atomic_dec(&id_mgr->reserved_vmid_num); |
1e9ef26f CZ |
624 | } |
625 | mutex_unlock(&id_mgr->lock); | |
626 | } | |
627 | ||
628 | static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev, | |
629 | struct amdgpu_vm *vm, | |
630 | unsigned vmhub) | |
631 | { | |
632 | struct amdgpu_vm_id_manager *id_mgr; | |
633 | struct amdgpu_vm_id *idle; | |
634 | int r = 0; | |
635 | ||
636 | id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
637 | mutex_lock(&id_mgr->lock); | |
638 | if (vm->reserved_vmid[vmhub]) | |
639 | goto unlock; | |
c3505770 CZ |
640 | if (atomic_inc_return(&id_mgr->reserved_vmid_num) > |
641 | AMDGPU_VM_MAX_RESERVED_VMID) { | |
642 | DRM_ERROR("Over limitation of reserved vmid\n"); | |
643 | atomic_dec(&id_mgr->reserved_vmid_num); | |
644 | r = -EINVAL; | |
645 | goto unlock; | |
646 | } | |
1e9ef26f CZ |
647 | /* Select the first entry VMID */ |
648 | idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list); | |
649 | list_del_init(&idle->list); | |
650 | vm->reserved_vmid[vmhub] = idle; | |
651 | mutex_unlock(&id_mgr->lock); | |
652 | ||
653 | return 0; | |
654 | unlock: | |
655 | mutex_unlock(&id_mgr->lock); | |
656 | return r; | |
657 | } | |
658 | ||
b9bf33d5 CZ |
659 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
660 | struct amdgpu_job *job) | |
661 | { | |
662 | struct amdgpu_device *adev = ring->adev; | |
663 | unsigned vmhub = ring->funcs->vmhub; | |
664 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
665 | struct amdgpu_vm_id *id; | |
666 | bool gds_switch_needed; | |
667 | bool vm_flush_needed = job->vm_needs_flush || | |
dd684d31 | 668 | amdgpu_ring_has_compute_vm_bug(ring); |
b9bf33d5 CZ |
669 | |
670 | if (job->vm_id == 0) | |
671 | return false; | |
672 | id = &id_mgr->ids[job->vm_id]; | |
673 | gds_switch_needed = ring->funcs->emit_gds_switch && ( | |
674 | id->gds_base != job->gds_base || | |
675 | id->gds_size != job->gds_size || | |
676 | id->gws_base != job->gws_base || | |
677 | id->gws_size != job->gws_size || | |
678 | id->oa_base != job->oa_base || | |
679 | id->oa_size != job->oa_size); | |
680 | ||
681 | if (amdgpu_vm_had_gpu_reset(adev, id)) | |
682 | return true; | |
683 | if (!vm_flush_needed && !gds_switch_needed) | |
684 | return false; | |
685 | return true; | |
686 | } | |
687 | ||
d38ceaf9 AD |
688 | /** |
689 | * amdgpu_vm_flush - hardware flush the vm | |
690 | * | |
691 | * @ring: ring to use for flush | |
cffadc83 | 692 | * @vm_id: vmid number to use |
4ff37a83 | 693 | * @pd_addr: address of the page directory |
d38ceaf9 | 694 | * |
4ff37a83 | 695 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 696 | */ |
fd53be30 | 697 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) |
d38ceaf9 | 698 | { |
971fe9a9 | 699 | struct amdgpu_device *adev = ring->adev; |
7645670d CK |
700 | unsigned vmhub = ring->funcs->vmhub; |
701 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
702 | struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id]; | |
d564a06e | 703 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
704 | id->gds_base != job->gds_base || |
705 | id->gds_size != job->gds_size || | |
706 | id->gws_base != job->gws_base || | |
707 | id->gws_size != job->gws_size || | |
708 | id->oa_base != job->oa_base || | |
709 | id->oa_size != job->oa_size); | |
de37e68a | 710 | bool vm_flush_needed = job->vm_needs_flush; |
c0e51931 | 711 | unsigned patch_offset = 0; |
41d9eb2c | 712 | int r; |
d564a06e | 713 | |
f7d015b9 CK |
714 | if (amdgpu_vm_had_gpu_reset(adev, id)) { |
715 | gds_switch_needed = true; | |
716 | vm_flush_needed = true; | |
717 | } | |
971fe9a9 | 718 | |
f7d015b9 CK |
719 | if (!vm_flush_needed && !gds_switch_needed) |
720 | return 0; | |
41d9eb2c | 721 | |
c0e51931 CK |
722 | if (ring->funcs->init_cond_exec) |
723 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 724 | |
f7d015b9 | 725 | if (ring->funcs->emit_vm_flush && vm_flush_needed) { |
c0e51931 | 726 | struct dma_fence *fence; |
41d9eb2c | 727 | |
9a94f5a5 CK |
728 | trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr); |
729 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
e9d672b2 | 730 | |
c0e51931 CK |
731 | r = amdgpu_fence_emit(ring, &fence); |
732 | if (r) | |
733 | return r; | |
e9d672b2 | 734 | |
7645670d | 735 | mutex_lock(&id_mgr->lock); |
c0e51931 CK |
736 | dma_fence_put(id->last_flush); |
737 | id->last_flush = fence; | |
bea39672 | 738 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
7645670d | 739 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 740 | } |
e9d672b2 | 741 | |
ca7962d8 | 742 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
743 | id->gds_base = job->gds_base; |
744 | id->gds_size = job->gds_size; | |
745 | id->gws_base = job->gws_base; | |
746 | id->gws_size = job->gws_size; | |
747 | id->oa_base = job->oa_base; | |
748 | id->oa_size = job->oa_size; | |
749 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base, | |
750 | job->gds_size, job->gws_base, | |
751 | job->gws_size, job->oa_base, | |
752 | job->oa_size); | |
753 | } | |
754 | ||
755 | if (ring->funcs->patch_cond_exec) | |
756 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
757 | ||
758 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
759 | if (ring->funcs->emit_switch_buffer) { | |
760 | amdgpu_ring_emit_switch_buffer(ring); | |
761 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 762 | } |
41d9eb2c | 763 | return 0; |
971fe9a9 CK |
764 | } |
765 | ||
766 | /** | |
767 | * amdgpu_vm_reset_id - reset VMID to zero | |
768 | * | |
769 | * @adev: amdgpu device structure | |
770 | * @vm_id: vmid number to use | |
771 | * | |
772 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
773 | */ | |
7645670d CK |
774 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
775 | unsigned vmid) | |
971fe9a9 | 776 | { |
7645670d CK |
777 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
778 | struct amdgpu_vm_id *id = &id_mgr->ids[vmid]; | |
bcb1ba35 | 779 | |
32601d48 | 780 | atomic64_set(&id->owner, 0); |
bcb1ba35 CK |
781 | id->gds_base = 0; |
782 | id->gds_size = 0; | |
783 | id->gws_base = 0; | |
784 | id->gws_size = 0; | |
785 | id->oa_base = 0; | |
786 | id->oa_size = 0; | |
d38ceaf9 AD |
787 | } |
788 | ||
32601d48 CK |
789 | /** |
790 | * amdgpu_vm_reset_all_id - reset VMID to zero | |
791 | * | |
792 | * @adev: amdgpu device structure | |
793 | * | |
794 | * Reset VMID to force flush on next use | |
795 | */ | |
796 | void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev) | |
797 | { | |
798 | unsigned i, j; | |
799 | ||
800 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
801 | struct amdgpu_vm_id_manager *id_mgr = | |
802 | &adev->vm_manager.id_mgr[i]; | |
803 | ||
804 | for (j = 1; j < id_mgr->num_ids; ++j) | |
805 | amdgpu_vm_reset_id(adev, i, j); | |
806 | } | |
807 | } | |
808 | ||
d38ceaf9 AD |
809 | /** |
810 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
811 | * | |
812 | * @vm: requested vm | |
813 | * @bo: requested buffer object | |
814 | * | |
8843dbbb | 815 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
816 | * Search inside the @bos vm list for the requested vm |
817 | * Returns the found bo_va or NULL if none is found | |
818 | * | |
819 | * Object has to be reserved! | |
820 | */ | |
821 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
822 | struct amdgpu_bo *bo) | |
823 | { | |
824 | struct amdgpu_bo_va *bo_va; | |
825 | ||
826 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
827 | if (bo_va->vm == vm) { | |
828 | return bo_va; | |
829 | } | |
830 | } | |
831 | return NULL; | |
832 | } | |
833 | ||
834 | /** | |
afef8b8f | 835 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 836 | * |
29efc4f5 | 837 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
838 | * @pe: addr of the page entry |
839 | * @addr: dst addr to write into pe | |
840 | * @count: number of page entries to update | |
841 | * @incr: increase next addr by incr bytes | |
842 | * @flags: hw access flags | |
d38ceaf9 AD |
843 | * |
844 | * Traces the parameters and calls the right asic functions | |
845 | * to setup the page table using the DMA. | |
846 | */ | |
afef8b8f CK |
847 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
848 | uint64_t pe, uint64_t addr, | |
849 | unsigned count, uint32_t incr, | |
6b777607 | 850 | uint64_t flags) |
d38ceaf9 | 851 | { |
ec2f05f0 | 852 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 853 | |
afef8b8f | 854 | if (count < 3) { |
de9ea7bd CK |
855 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
856 | addr | flags, count, incr); | |
d38ceaf9 AD |
857 | |
858 | } else { | |
27c5f36f | 859 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
860 | count, incr, flags); |
861 | } | |
862 | } | |
863 | ||
afef8b8f CK |
864 | /** |
865 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
866 | * | |
867 | * @params: see amdgpu_pte_update_params definition | |
868 | * @pe: addr of the page entry | |
869 | * @addr: dst addr to write into pe | |
870 | * @count: number of page entries to update | |
871 | * @incr: increase next addr by incr bytes | |
872 | * @flags: hw access flags | |
873 | * | |
874 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
875 | */ | |
876 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
877 | uint64_t pe, uint64_t addr, | |
878 | unsigned count, uint32_t incr, | |
6b777607 | 879 | uint64_t flags) |
afef8b8f | 880 | { |
ec2f05f0 | 881 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 882 | |
ec2f05f0 CK |
883 | |
884 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
885 | ||
886 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
887 | } |
888 | ||
d38ceaf9 | 889 | /** |
b07c9d2a | 890 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 891 | * |
b07c9d2a | 892 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
893 | * @addr: the unmapped addr |
894 | * | |
895 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 896 | * to and return the pointer for the page table entry. |
d38ceaf9 | 897 | */ |
de9ea7bd | 898 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
899 | { |
900 | uint64_t result; | |
901 | ||
de9ea7bd CK |
902 | /* page table offset */ |
903 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 904 | |
de9ea7bd CK |
905 | /* in case cpu page size != gpu page size*/ |
906 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 907 | |
b07c9d2a | 908 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
909 | |
910 | return result; | |
911 | } | |
912 | ||
f8991bab | 913 | /* |
194d2161 | 914 | * amdgpu_vm_update_level - update a single level in the hierarchy |
f8991bab CK |
915 | * |
916 | * @adev: amdgpu_device pointer | |
917 | * @vm: requested vm | |
194d2161 | 918 | * @parent: parent directory |
f8991bab | 919 | * |
194d2161 | 920 | * Makes sure all entries in @parent are up to date. |
f8991bab CK |
921 | * Returns 0 for success, error for failure. |
922 | */ | |
194d2161 CK |
923 | static int amdgpu_vm_update_level(struct amdgpu_device *adev, |
924 | struct amdgpu_vm *vm, | |
925 | struct amdgpu_vm_pt *parent, | |
926 | unsigned level) | |
d38ceaf9 | 927 | { |
f8991bab | 928 | struct amdgpu_bo *shadow; |
2d55e45a | 929 | struct amdgpu_ring *ring; |
f8991bab | 930 | uint64_t pd_addr, shadow_addr; |
194d2161 | 931 | uint32_t incr = amdgpu_vm_bo_size(adev, level + 1); |
f8991bab | 932 | uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; |
d38ceaf9 | 933 | unsigned count = 0, pt_idx, ndw; |
d71518b5 | 934 | struct amdgpu_job *job; |
29efc4f5 | 935 | struct amdgpu_pte_update_params params; |
f54d1867 | 936 | struct dma_fence *fence = NULL; |
d5fc5e82 | 937 | |
d38ceaf9 AD |
938 | int r; |
939 | ||
194d2161 CK |
940 | if (!parent->entries) |
941 | return 0; | |
2d55e45a CK |
942 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
943 | ||
d38ceaf9 AD |
944 | /* padding, etc. */ |
945 | ndw = 64; | |
946 | ||
947 | /* assume the worst case */ | |
194d2161 | 948 | ndw += parent->last_entry_used * 6; |
d38ceaf9 | 949 | |
194d2161 CK |
950 | pd_addr = amdgpu_bo_gpu_offset(parent->bo); |
951 | ||
952 | shadow = parent->bo->shadow; | |
f8991bab CK |
953 | if (shadow) { |
954 | r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); | |
955 | if (r) | |
956 | return r; | |
957 | shadow_addr = amdgpu_bo_gpu_offset(shadow); | |
958 | ndw *= 2; | |
959 | } else { | |
960 | shadow_addr = 0; | |
961 | } | |
962 | ||
d71518b5 CK |
963 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
964 | if (r) | |
d38ceaf9 | 965 | return r; |
d71518b5 | 966 | |
27c5f36f CK |
967 | memset(¶ms, 0, sizeof(params)); |
968 | params.adev = adev; | |
29efc4f5 | 969 | params.ib = &job->ibs[0]; |
d38ceaf9 | 970 | |
194d2161 CK |
971 | /* walk over the address space and update the directory */ |
972 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
973 | struct amdgpu_bo *bo = parent->entries[pt_idx].bo; | |
d38ceaf9 AD |
974 | uint64_t pde, pt; |
975 | ||
976 | if (bo == NULL) | |
977 | continue; | |
978 | ||
0fc8683e | 979 | if (bo->shadow) { |
f8991bab | 980 | struct amdgpu_bo *pt_shadow = bo->shadow; |
0fc8683e | 981 | |
f8991bab CK |
982 | r = amdgpu_ttm_bind(&pt_shadow->tbo, |
983 | &pt_shadow->tbo.mem); | |
0fc8683e CK |
984 | if (r) |
985 | return r; | |
986 | } | |
987 | ||
d38ceaf9 | 988 | pt = amdgpu_bo_gpu_offset(bo); |
194d2161 | 989 | if (parent->entries[pt_idx].addr == pt) |
f8991bab CK |
990 | continue; |
991 | ||
194d2161 | 992 | parent->entries[pt_idx].addr = pt; |
d38ceaf9 AD |
993 | |
994 | pde = pd_addr + pt_idx * 8; | |
995 | if (((last_pde + 8 * count) != pde) || | |
96105e53 CK |
996 | ((last_pt + incr * count) != pt) || |
997 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
d38ceaf9 AD |
998 | |
999 | if (count) { | |
b1166325 | 1000 | uint64_t entry; |
e60f8db5 | 1001 | |
b1166325 | 1002 | entry = amdgpu_gart_get_vm_pde(adev, last_pt); |
f8991bab CK |
1003 | if (shadow) |
1004 | amdgpu_vm_do_set_ptes(¶ms, | |
1005 | last_shadow, | |
b1166325 | 1006 | entry, count, |
f8991bab CK |
1007 | incr, |
1008 | AMDGPU_PTE_VALID); | |
1009 | ||
afef8b8f | 1010 | amdgpu_vm_do_set_ptes(¶ms, last_pde, |
b1166325 | 1011 | entry, count, incr, |
afef8b8f | 1012 | AMDGPU_PTE_VALID); |
d38ceaf9 AD |
1013 | } |
1014 | ||
1015 | count = 1; | |
1016 | last_pde = pde; | |
f8991bab | 1017 | last_shadow = shadow_addr + pt_idx * 8; |
d38ceaf9 AD |
1018 | last_pt = pt; |
1019 | } else { | |
1020 | ++count; | |
1021 | } | |
1022 | } | |
1023 | ||
f8991bab | 1024 | if (count) { |
b1166325 CK |
1025 | uint64_t entry; |
1026 | ||
1027 | entry = amdgpu_gart_get_vm_pde(adev, last_pt); | |
e60f8db5 | 1028 | |
67003a15 | 1029 | if (vm->root.bo->shadow) |
b1166325 | 1030 | amdgpu_vm_do_set_ptes(¶ms, last_shadow, entry, |
f8991bab CK |
1031 | count, incr, AMDGPU_PTE_VALID); |
1032 | ||
b1166325 | 1033 | amdgpu_vm_do_set_ptes(¶ms, last_pde, entry, |
afef8b8f | 1034 | count, incr, AMDGPU_PTE_VALID); |
f8991bab | 1035 | } |
d38ceaf9 | 1036 | |
f8991bab CK |
1037 | if (params.ib->length_dw == 0) { |
1038 | amdgpu_job_free(job); | |
194d2161 CK |
1039 | } else { |
1040 | amdgpu_ring_pad_ib(ring, params.ib); | |
1041 | amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv, | |
e86f9cee | 1042 | AMDGPU_FENCE_OWNER_VM); |
194d2161 CK |
1043 | if (shadow) |
1044 | amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv, | |
1045 | AMDGPU_FENCE_OWNER_VM); | |
05906dec | 1046 | |
194d2161 CK |
1047 | WARN_ON(params.ib->length_dw > ndw); |
1048 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
1049 | AMDGPU_FENCE_OWNER_VM, &fence); | |
1050 | if (r) | |
1051 | goto error_free; | |
1052 | ||
1053 | amdgpu_bo_fence(parent->bo, fence, true); | |
1054 | dma_fence_put(vm->last_dir_update); | |
1055 | vm->last_dir_update = dma_fence_get(fence); | |
1056 | dma_fence_put(fence); | |
1057 | } | |
1058 | /* | |
1059 | * Recurse into the subdirectories. This recursion is harmless because | |
1060 | * we only have a maximum of 5 layers. | |
1061 | */ | |
1062 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
1063 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
1064 | ||
1065 | if (!entry->bo) | |
1066 | continue; | |
d5fc5e82 | 1067 | |
194d2161 CK |
1068 | r = amdgpu_vm_update_level(adev, vm, entry, level + 1); |
1069 | if (r) | |
1070 | return r; | |
1071 | } | |
d38ceaf9 AD |
1072 | |
1073 | return 0; | |
d5fc5e82 CZ |
1074 | |
1075 | error_free: | |
d71518b5 | 1076 | amdgpu_job_free(job); |
4af9f07c | 1077 | return r; |
d38ceaf9 AD |
1078 | } |
1079 | ||
92456b93 CK |
1080 | /* |
1081 | * amdgpu_vm_invalidate_level - mark all PD levels as invalid | |
1082 | * | |
1083 | * @parent: parent PD | |
1084 | * | |
1085 | * Mark all PD level as invalid after an error. | |
1086 | */ | |
1087 | static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent) | |
1088 | { | |
1089 | unsigned pt_idx; | |
1090 | ||
1091 | /* | |
1092 | * Recurse into the subdirectories. This recursion is harmless because | |
1093 | * we only have a maximum of 5 layers. | |
1094 | */ | |
1095 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
1096 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
1097 | ||
1098 | if (!entry->bo) | |
1099 | continue; | |
1100 | ||
1101 | entry->addr = ~0ULL; | |
1102 | amdgpu_vm_invalidate_level(entry); | |
1103 | } | |
1104 | } | |
1105 | ||
194d2161 CK |
1106 | /* |
1107 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1108 | * | |
1109 | * @adev: amdgpu_device pointer | |
1110 | * @vm: requested vm | |
1111 | * | |
1112 | * Makes sure all directories are up to date. | |
1113 | * Returns 0 for success, error for failure. | |
1114 | */ | |
1115 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1116 | struct amdgpu_vm *vm) | |
1117 | { | |
92456b93 CK |
1118 | int r; |
1119 | ||
1120 | r = amdgpu_vm_update_level(adev, vm, &vm->root, 0); | |
1121 | if (r) | |
1122 | amdgpu_vm_invalidate_level(&vm->root); | |
1123 | ||
1124 | return r; | |
194d2161 CK |
1125 | } |
1126 | ||
4e2cb640 CK |
1127 | /** |
1128 | * amdgpu_vm_find_pt - find the page table for an address | |
1129 | * | |
1130 | * @p: see amdgpu_pte_update_params definition | |
1131 | * @addr: virtual address in question | |
1132 | * | |
1133 | * Find the page table BO for a virtual address, return NULL when none found. | |
1134 | */ | |
1135 | static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p, | |
1136 | uint64_t addr) | |
1137 | { | |
1138 | struct amdgpu_vm_pt *entry = &p->vm->root; | |
1139 | unsigned idx, level = p->adev->vm_manager.num_level; | |
1140 | ||
1141 | while (entry->entries) { | |
36b32a68 | 1142 | idx = addr >> (p->adev->vm_manager.block_size * level--); |
4e2cb640 CK |
1143 | idx %= amdgpu_bo_size(entry->bo) / 8; |
1144 | entry = &entry->entries[idx]; | |
1145 | } | |
1146 | ||
1147 | if (level) | |
1148 | return NULL; | |
1149 | ||
1150 | return entry->bo; | |
1151 | } | |
1152 | ||
d38ceaf9 AD |
1153 | /** |
1154 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1155 | * | |
29efc4f5 | 1156 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1157 | * @vm: requested vm |
1158 | * @start: start of GPU address range | |
1159 | * @end: end of GPU address range | |
677131a1 | 1160 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1161 | * @flags: mapping flags |
1162 | * | |
8843dbbb | 1163 | * Update the page tables in the range @start - @end. |
cc28c4ed | 1164 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 | 1165 | */ |
cc28c4ed | 1166 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1167 | uint64_t start, uint64_t end, |
6b777607 | 1168 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1169 | { |
36b32a68 ZJ |
1170 | struct amdgpu_device *adev = params->adev; |
1171 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1172 | |
92696dd5 | 1173 | uint64_t cur_pe_start, cur_nptes, cur_dst; |
677131a1 | 1174 | uint64_t addr; /* next GPU address to be updated */ |
21718497 AX |
1175 | struct amdgpu_bo *pt; |
1176 | unsigned nptes; /* next number of ptes to be updated */ | |
1177 | uint64_t next_pe_start; | |
1178 | ||
1179 | /* initialize the variables */ | |
1180 | addr = start; | |
4e2cb640 | 1181 | pt = amdgpu_vm_get_pt(params, addr); |
1866bac8 FK |
1182 | if (!pt) { |
1183 | pr_err("PT not found, aborting update_ptes\n"); | |
cc28c4ed | 1184 | return -EINVAL; |
1866bac8 | 1185 | } |
4e2cb640 | 1186 | |
4c7e8855 CZ |
1187 | if (params->shadow) { |
1188 | if (!pt->shadow) | |
cc28c4ed | 1189 | return 0; |
914b4dce | 1190 | pt = pt->shadow; |
4c7e8855 | 1191 | } |
21718497 AX |
1192 | if ((addr & ~mask) == (end & ~mask)) |
1193 | nptes = end - addr; | |
1194 | else | |
36b32a68 | 1195 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
21718497 AX |
1196 | |
1197 | cur_pe_start = amdgpu_bo_gpu_offset(pt); | |
1198 | cur_pe_start += (addr & mask) * 8; | |
92696dd5 | 1199 | cur_nptes = nptes; |
21718497 AX |
1200 | cur_dst = dst; |
1201 | ||
1202 | /* for next ptb*/ | |
1203 | addr += nptes; | |
1204 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
d38ceaf9 AD |
1205 | |
1206 | /* walk over the address space and update the page tables */ | |
21718497 | 1207 | while (addr < end) { |
4e2cb640 | 1208 | pt = amdgpu_vm_get_pt(params, addr); |
1866bac8 FK |
1209 | if (!pt) { |
1210 | pr_err("PT not found, aborting update_ptes\n"); | |
cc28c4ed | 1211 | return -EINVAL; |
1866bac8 | 1212 | } |
4e2cb640 | 1213 | |
4c7e8855 CZ |
1214 | if (params->shadow) { |
1215 | if (!pt->shadow) | |
cc28c4ed | 1216 | return 0; |
914b4dce | 1217 | pt = pt->shadow; |
4c7e8855 | 1218 | } |
d38ceaf9 AD |
1219 | |
1220 | if ((addr & ~mask) == (end & ~mask)) | |
1221 | nptes = end - addr; | |
1222 | else | |
36b32a68 | 1223 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1224 | |
677131a1 AX |
1225 | next_pe_start = amdgpu_bo_gpu_offset(pt); |
1226 | next_pe_start += (addr & mask) * 8; | |
d38ceaf9 | 1227 | |
96105e53 CK |
1228 | if ((cur_pe_start + 8 * cur_nptes) == next_pe_start && |
1229 | ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
3a6f8e0c | 1230 | /* The next ptb is consecutive to current ptb. |
afef8b8f | 1231 | * Don't call the update function now. |
3a6f8e0c AX |
1232 | * Will update two ptbs together in future. |
1233 | */ | |
92696dd5 | 1234 | cur_nptes += nptes; |
3a6f8e0c | 1235 | } else { |
afef8b8f CK |
1236 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
1237 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 | 1238 | |
677131a1 | 1239 | cur_pe_start = next_pe_start; |
92696dd5 | 1240 | cur_nptes = nptes; |
677131a1 | 1241 | cur_dst = dst; |
d38ceaf9 AD |
1242 | } |
1243 | ||
21718497 | 1244 | /* for next ptb*/ |
d38ceaf9 AD |
1245 | addr += nptes; |
1246 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
1247 | } | |
1248 | ||
afef8b8f CK |
1249 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
1250 | AMDGPU_GPU_PAGE_SIZE, flags); | |
cc28c4ed HK |
1251 | |
1252 | return 0; | |
92696dd5 CK |
1253 | } |
1254 | ||
1255 | /* | |
1256 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1257 | * | |
1258 | * @params: see amdgpu_pte_update_params definition | |
1259 | * @vm: requested vm | |
1260 | * @start: first PTE to handle | |
1261 | * @end: last PTE to handle | |
1262 | * @dst: addr those PTEs should point to | |
1263 | * @flags: hw mapping flags | |
cc28c4ed | 1264 | * Returns 0 for success, -EINVAL for failure. |
92696dd5 | 1265 | */ |
cc28c4ed | 1266 | static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, |
92696dd5 | 1267 | uint64_t start, uint64_t end, |
6b777607 | 1268 | uint64_t dst, uint64_t flags) |
92696dd5 | 1269 | { |
cc28c4ed HK |
1270 | int r; |
1271 | ||
92696dd5 CK |
1272 | /** |
1273 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1274 | * field in the PTE. When this field is set to a non-zero value, page | |
1275 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1276 | * flags are considered valid for all PTEs within the fragment range | |
1277 | * and corresponding mappings are assumed to be physically contiguous. | |
1278 | * | |
1279 | * The L1 TLB can store a single PTE for the whole fragment, | |
1280 | * significantly increasing the space available for translation | |
1281 | * caching. This leads to large improvements in throughput when the | |
1282 | * TLB is under pressure. | |
1283 | * | |
1284 | * The L2 TLB distributes small and large fragments into two | |
1285 | * asymmetric partitions. The large fragment cache is significantly | |
1286 | * larger. Thus, we try to use large fragments wherever possible. | |
1287 | * Userspace can support this by aligning virtual base address and | |
1288 | * allocation size to the fragment size. | |
1289 | */ | |
1290 | ||
8036617e CK |
1291 | /* SI and newer are optimized for 64KB */ |
1292 | uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG); | |
1293 | uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG; | |
92696dd5 CK |
1294 | |
1295 | uint64_t frag_start = ALIGN(start, frag_align); | |
1296 | uint64_t frag_end = end & ~(frag_align - 1); | |
1297 | ||
1298 | /* system pages are non continuously */ | |
b7fc2cbd | 1299 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
cc28c4ed HK |
1300 | (frag_start >= frag_end)) |
1301 | return amdgpu_vm_update_ptes(params, start, end, dst, flags); | |
92696dd5 CK |
1302 | |
1303 | /* handle the 4K area at the beginning */ | |
1304 | if (start != frag_start) { | |
cc28c4ed HK |
1305 | r = amdgpu_vm_update_ptes(params, start, frag_start, |
1306 | dst, flags); | |
1307 | if (r) | |
1308 | return r; | |
92696dd5 CK |
1309 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; |
1310 | } | |
1311 | ||
1312 | /* handle the area in the middle */ | |
cc28c4ed HK |
1313 | r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, |
1314 | flags | frag_flags); | |
1315 | if (r) | |
1316 | return r; | |
92696dd5 CK |
1317 | |
1318 | /* handle the 4K area at the end */ | |
1319 | if (frag_end != end) { | |
1320 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
cc28c4ed | 1321 | r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); |
92696dd5 | 1322 | } |
cc28c4ed | 1323 | return r; |
d38ceaf9 AD |
1324 | } |
1325 | ||
d38ceaf9 AD |
1326 | /** |
1327 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1328 | * | |
1329 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1330 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
1331 | * @src: address where to copy page table entries from |
1332 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 1333 | * @vm: requested vm |
a14faa65 CK |
1334 | * @start: start of mapped range |
1335 | * @last: last mapped entry | |
1336 | * @flags: flags for the entries | |
d38ceaf9 | 1337 | * @addr: addr to set the area to |
d38ceaf9 AD |
1338 | * @fence: optional resulting fence |
1339 | * | |
a14faa65 | 1340 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 1341 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
1342 | */ |
1343 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1344 | struct dma_fence *exclusive, |
fa3ab3c7 CK |
1345 | uint64_t src, |
1346 | dma_addr_t *pages_addr, | |
d38ceaf9 | 1347 | struct amdgpu_vm *vm, |
a14faa65 | 1348 | uint64_t start, uint64_t last, |
6b777607 | 1349 | uint64_t flags, uint64_t addr, |
f54d1867 | 1350 | struct dma_fence **fence) |
d38ceaf9 | 1351 | { |
2d55e45a | 1352 | struct amdgpu_ring *ring; |
a1e08d3b | 1353 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1354 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1355 | struct amdgpu_job *job; |
29efc4f5 | 1356 | struct amdgpu_pte_update_params params; |
f54d1867 | 1357 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1358 | int r; |
1359 | ||
afef8b8f CK |
1360 | memset(¶ms, 0, sizeof(params)); |
1361 | params.adev = adev; | |
49ac8a24 | 1362 | params.vm = vm; |
afef8b8f CK |
1363 | params.src = src; |
1364 | ||
2d55e45a | 1365 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 1366 | |
a1e08d3b CK |
1367 | /* sync to everything on unmapping */ |
1368 | if (!(flags & AMDGPU_PTE_VALID)) | |
1369 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1370 | ||
a14faa65 | 1371 | nptes = last - start + 1; |
d38ceaf9 AD |
1372 | |
1373 | /* | |
1374 | * reserve space for one command every (1 << BLOCK_SIZE) | |
1375 | * entries or 2k dwords (whatever is smaller) | |
1376 | */ | |
36b32a68 | 1377 | ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1; |
d38ceaf9 AD |
1378 | |
1379 | /* padding, etc. */ | |
1380 | ndw = 64; | |
1381 | ||
b0456f93 | 1382 | if (src) { |
d38ceaf9 AD |
1383 | /* only copy commands needed */ |
1384 | ndw += ncmds * 7; | |
1385 | ||
afef8b8f CK |
1386 | params.func = amdgpu_vm_do_copy_ptes; |
1387 | ||
b0456f93 CK |
1388 | } else if (pages_addr) { |
1389 | /* copy commands needed */ | |
1390 | ndw += ncmds * 7; | |
d38ceaf9 | 1391 | |
b0456f93 | 1392 | /* and also PTEs */ |
d38ceaf9 AD |
1393 | ndw += nptes * 2; |
1394 | ||
afef8b8f CK |
1395 | params.func = amdgpu_vm_do_copy_ptes; |
1396 | ||
d38ceaf9 AD |
1397 | } else { |
1398 | /* set page commands needed */ | |
1399 | ndw += ncmds * 10; | |
1400 | ||
1401 | /* two extra commands for begin/end of fragment */ | |
1402 | ndw += 2 * 10; | |
afef8b8f CK |
1403 | |
1404 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1405 | } |
1406 | ||
d71518b5 CK |
1407 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1408 | if (r) | |
d38ceaf9 | 1409 | return r; |
d71518b5 | 1410 | |
29efc4f5 | 1411 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1412 | |
b0456f93 CK |
1413 | if (!src && pages_addr) { |
1414 | uint64_t *pte; | |
1415 | unsigned i; | |
1416 | ||
1417 | /* Put the PTEs at the end of the IB. */ | |
1418 | i = ndw - nptes * 2; | |
1419 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1420 | params.src = job->ibs->gpu_addr + i * 4; | |
1421 | ||
1422 | for (i = 0; i < nptes; ++i) { | |
1423 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1424 | AMDGPU_GPU_PAGE_SIZE); | |
1425 | pte[i] |= flags; | |
1426 | } | |
d7a4ac66 | 1427 | addr = 0; |
b0456f93 CK |
1428 | } |
1429 | ||
3cabaa54 CK |
1430 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
1431 | if (r) | |
1432 | goto error_free; | |
1433 | ||
67003a15 | 1434 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv, |
a1e08d3b CK |
1435 | owner); |
1436 | if (r) | |
1437 | goto error_free; | |
d38ceaf9 | 1438 | |
67003a15 | 1439 | r = reservation_object_reserve_shared(vm->root.bo->tbo.resv); |
a1e08d3b CK |
1440 | if (r) |
1441 | goto error_free; | |
1442 | ||
4c7e8855 | 1443 | params.shadow = true; |
cc28c4ed HK |
1444 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
1445 | if (r) | |
1446 | goto error_free; | |
4c7e8855 | 1447 | params.shadow = false; |
cc28c4ed HK |
1448 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
1449 | if (r) | |
1450 | goto error_free; | |
d38ceaf9 | 1451 | |
29efc4f5 CK |
1452 | amdgpu_ring_pad_ib(ring, params.ib); |
1453 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1454 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1455 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1456 | if (r) |
1457 | goto error_free; | |
d38ceaf9 | 1458 | |
67003a15 | 1459 | amdgpu_bo_fence(vm->root.bo, f, true); |
284710fa CK |
1460 | dma_fence_put(*fence); |
1461 | *fence = f; | |
d38ceaf9 | 1462 | return 0; |
d5fc5e82 CZ |
1463 | |
1464 | error_free: | |
d71518b5 | 1465 | amdgpu_job_free(job); |
4af9f07c | 1466 | return r; |
d38ceaf9 AD |
1467 | } |
1468 | ||
a14faa65 CK |
1469 | /** |
1470 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1471 | * | |
1472 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1473 | * @exclusive: fence we need to sync to |
8358dcee CK |
1474 | * @gtt_flags: flags as they are used for GTT |
1475 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
1476 | * @vm: requested vm |
1477 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1478 | * @flags: HW flags for the mapping |
63e0ba40 | 1479 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1480 | * @fence: optional resulting fence |
1481 | * | |
1482 | * Split the mapping into smaller chunks so that each update fits | |
1483 | * into a SDMA IB. | |
1484 | * Returns 0 for success, -EINVAL for failure. | |
1485 | */ | |
1486 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1487 | struct dma_fence *exclusive, |
6b777607 | 1488 | uint64_t gtt_flags, |
8358dcee | 1489 | dma_addr_t *pages_addr, |
a14faa65 CK |
1490 | struct amdgpu_vm *vm, |
1491 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1492 | uint64_t flags, |
63e0ba40 | 1493 | struct drm_mm_node *nodes, |
f54d1867 | 1494 | struct dma_fence **fence) |
a14faa65 | 1495 | { |
a9f87f64 | 1496 | uint64_t pfn, src = 0, start = mapping->start; |
a14faa65 CK |
1497 | int r; |
1498 | ||
1499 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1500 | * but in case of something, we filter the flags in first place | |
1501 | */ | |
1502 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1503 | flags &= ~AMDGPU_PTE_READABLE; | |
1504 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1505 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1506 | ||
15b31c59 AX |
1507 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1508 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1509 | ||
b0fd18b0 AX |
1510 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1511 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1512 | ||
d0766e98 ZJ |
1513 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1514 | (adev->asic_type >= CHIP_VEGA10)) { | |
1515 | flags |= AMDGPU_PTE_PRT; | |
1516 | flags &= ~AMDGPU_PTE_VALID; | |
1517 | } | |
1518 | ||
a14faa65 CK |
1519 | trace_amdgpu_vm_bo_update(mapping); |
1520 | ||
63e0ba40 CK |
1521 | pfn = mapping->offset >> PAGE_SHIFT; |
1522 | if (nodes) { | |
1523 | while (pfn >= nodes->size) { | |
1524 | pfn -= nodes->size; | |
1525 | ++nodes; | |
1526 | } | |
fa3ab3c7 | 1527 | } |
a14faa65 | 1528 | |
63e0ba40 CK |
1529 | do { |
1530 | uint64_t max_entries; | |
1531 | uint64_t addr, last; | |
a14faa65 | 1532 | |
63e0ba40 CK |
1533 | if (nodes) { |
1534 | addr = nodes->start << PAGE_SHIFT; | |
1535 | max_entries = (nodes->size - pfn) * | |
1536 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1537 | } else { | |
1538 | addr = 0; | |
1539 | max_entries = S64_MAX; | |
1540 | } | |
a14faa65 | 1541 | |
63e0ba40 CK |
1542 | if (pages_addr) { |
1543 | if (flags == gtt_flags) | |
1544 | src = adev->gart.table_addr + | |
1545 | (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8; | |
1546 | else | |
1547 | max_entries = min(max_entries, 16ull * 1024ull); | |
1548 | addr = 0; | |
1549 | } else if (flags & AMDGPU_PTE_VALID) { | |
1550 | addr += adev->vm_manager.vram_base_offset; | |
1551 | } | |
1552 | addr += pfn << PAGE_SHIFT; | |
1553 | ||
a9f87f64 | 1554 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
3cabaa54 CK |
1555 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1556 | src, pages_addr, vm, | |
a14faa65 CK |
1557 | start, last, flags, addr, |
1558 | fence); | |
1559 | if (r) | |
1560 | return r; | |
1561 | ||
63e0ba40 CK |
1562 | pfn += last - start + 1; |
1563 | if (nodes && nodes->size == pfn) { | |
1564 | pfn = 0; | |
1565 | ++nodes; | |
1566 | } | |
a14faa65 | 1567 | start = last + 1; |
63e0ba40 | 1568 | |
a9f87f64 | 1569 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1570 | |
1571 | return 0; | |
1572 | } | |
1573 | ||
d38ceaf9 AD |
1574 | /** |
1575 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1576 | * | |
1577 | * @adev: amdgpu_device pointer | |
1578 | * @bo_va: requested BO and VM object | |
99e124f4 | 1579 | * @clear: if true clear the entries |
d38ceaf9 AD |
1580 | * |
1581 | * Fill in the page table entries for @bo_va. | |
1582 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1583 | */ |
1584 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1585 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1586 | bool clear) |
d38ceaf9 AD |
1587 | { |
1588 | struct amdgpu_vm *vm = bo_va->vm; | |
1589 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1590 | dma_addr_t *pages_addr = NULL; |
6b777607 | 1591 | uint64_t gtt_flags, flags; |
99e124f4 | 1592 | struct ttm_mem_reg *mem; |
63e0ba40 | 1593 | struct drm_mm_node *nodes; |
f54d1867 | 1594 | struct dma_fence *exclusive; |
d38ceaf9 AD |
1595 | int r; |
1596 | ||
a5f6b5b1 | 1597 | if (clear || !bo_va->bo) { |
99e124f4 | 1598 | mem = NULL; |
63e0ba40 | 1599 | nodes = NULL; |
99e124f4 CK |
1600 | exclusive = NULL; |
1601 | } else { | |
8358dcee CK |
1602 | struct ttm_dma_tt *ttm; |
1603 | ||
99e124f4 | 1604 | mem = &bo_va->bo->tbo.mem; |
63e0ba40 CK |
1605 | nodes = mem->mm_node; |
1606 | if (mem->mem_type == TTM_PL_TT) { | |
8358dcee CK |
1607 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1608 | ttm_dma_tt, ttm); | |
1609 | pages_addr = ttm->dma_address; | |
9ab21462 | 1610 | } |
3cabaa54 | 1611 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); |
d38ceaf9 AD |
1612 | } |
1613 | ||
a5f6b5b1 CK |
1614 | if (bo_va->bo) { |
1615 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); | |
1616 | gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && | |
1617 | adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? | |
1618 | flags : 0; | |
1619 | } else { | |
1620 | flags = 0x0; | |
1621 | gtt_flags = ~0x0; | |
1622 | } | |
d38ceaf9 | 1623 | |
7fc11959 CK |
1624 | spin_lock(&vm->status_lock); |
1625 | if (!list_empty(&bo_va->vm_status)) | |
1626 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1627 | spin_unlock(&vm->status_lock); | |
1628 | ||
1629 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1630 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1631 | gtt_flags, pages_addr, vm, | |
63e0ba40 | 1632 | mapping, flags, nodes, |
8358dcee | 1633 | &bo_va->last_pt_update); |
d38ceaf9 AD |
1634 | if (r) |
1635 | return r; | |
1636 | } | |
1637 | ||
d6c10f6b CK |
1638 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1639 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1640 | trace_amdgpu_vm_bo_mapping(mapping); | |
1641 | ||
1642 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1643 | trace_amdgpu_vm_bo_mapping(mapping); | |
1644 | } | |
1645 | ||
d38ceaf9 | 1646 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1647 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1648 | list_del_init(&bo_va->vm_status); |
99e124f4 | 1649 | if (clear) |
7fc11959 | 1650 | list_add(&bo_va->vm_status, &vm->cleared); |
d38ceaf9 AD |
1651 | spin_unlock(&vm->status_lock); |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
284710fa CK |
1656 | /** |
1657 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1658 | */ | |
1659 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1660 | { | |
1661 | unsigned long flags; | |
1662 | bool enable; | |
1663 | ||
1664 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1665 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
284710fa CK |
1666 | adev->gart.gart_funcs->set_prt(adev, enable); |
1667 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
1668 | } | |
1669 | ||
451bc8eb | 1670 | /** |
4388fc2a | 1671 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1672 | */ |
1673 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1674 | { | |
4388fc2a CK |
1675 | if (!adev->gart.gart_funcs->set_prt) |
1676 | return; | |
1677 | ||
451bc8eb CK |
1678 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1679 | amdgpu_vm_update_prt_state(adev); | |
1680 | } | |
1681 | ||
0b15f2fc CK |
1682 | /** |
1683 | * amdgpu_vm_prt_put - drop a PRT user | |
1684 | */ | |
1685 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1686 | { | |
451bc8eb | 1687 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1688 | amdgpu_vm_update_prt_state(adev); |
1689 | } | |
1690 | ||
284710fa | 1691 | /** |
451bc8eb | 1692 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1693 | */ |
1694 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1695 | { | |
1696 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1697 | ||
0b15f2fc | 1698 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1699 | kfree(cb); |
1700 | } | |
1701 | ||
451bc8eb CK |
1702 | /** |
1703 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1704 | */ | |
1705 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1706 | struct dma_fence *fence) | |
1707 | { | |
4388fc2a | 1708 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1709 | |
4388fc2a CK |
1710 | if (!adev->gart.gart_funcs->set_prt) |
1711 | return; | |
1712 | ||
1713 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1714 | if (!cb) { |
1715 | /* Last resort when we are OOM */ | |
1716 | if (fence) | |
1717 | dma_fence_wait(fence, false); | |
1718 | ||
486a68f5 | 1719 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1720 | } else { |
1721 | cb->adev = adev; | |
1722 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1723 | amdgpu_vm_prt_cb)) | |
1724 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1725 | } | |
1726 | } | |
1727 | ||
284710fa CK |
1728 | /** |
1729 | * amdgpu_vm_free_mapping - free a mapping | |
1730 | * | |
1731 | * @adev: amdgpu_device pointer | |
1732 | * @vm: requested vm | |
1733 | * @mapping: mapping to be freed | |
1734 | * @fence: fence of the unmap operation | |
1735 | * | |
1736 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1737 | */ | |
1738 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1739 | struct amdgpu_vm *vm, | |
1740 | struct amdgpu_bo_va_mapping *mapping, | |
1741 | struct dma_fence *fence) | |
1742 | { | |
451bc8eb CK |
1743 | if (mapping->flags & AMDGPU_PTE_PRT) |
1744 | amdgpu_vm_add_prt_cb(adev, fence); | |
1745 | kfree(mapping); | |
1746 | } | |
284710fa | 1747 | |
451bc8eb CK |
1748 | /** |
1749 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1750 | * | |
1751 | * @adev: amdgpu_device pointer | |
1752 | * @vm: requested vm | |
1753 | * | |
1754 | * Register a cleanup callback to disable PRT support after VM dies. | |
1755 | */ | |
1756 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1757 | { | |
67003a15 | 1758 | struct reservation_object *resv = vm->root.bo->tbo.resv; |
451bc8eb CK |
1759 | struct dma_fence *excl, **shared; |
1760 | unsigned i, shared_count; | |
1761 | int r; | |
0b15f2fc | 1762 | |
451bc8eb CK |
1763 | r = reservation_object_get_fences_rcu(resv, &excl, |
1764 | &shared_count, &shared); | |
1765 | if (r) { | |
1766 | /* Not enough memory to grab the fence list, as last resort | |
1767 | * block for all the fences to complete. | |
1768 | */ | |
1769 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1770 | MAX_SCHEDULE_TIMEOUT); | |
1771 | return; | |
284710fa | 1772 | } |
451bc8eb CK |
1773 | |
1774 | /* Add a callback for each fence in the reservation object */ | |
1775 | amdgpu_vm_prt_get(adev); | |
1776 | amdgpu_vm_add_prt_cb(adev, excl); | |
1777 | ||
1778 | for (i = 0; i < shared_count; ++i) { | |
1779 | amdgpu_vm_prt_get(adev); | |
1780 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1781 | } | |
1782 | ||
1783 | kfree(shared); | |
284710fa CK |
1784 | } |
1785 | ||
d38ceaf9 AD |
1786 | /** |
1787 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1788 | * | |
1789 | * @adev: amdgpu_device pointer | |
1790 | * @vm: requested vm | |
f3467818 NH |
1791 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1792 | * or if an error occurred) | |
d38ceaf9 AD |
1793 | * |
1794 | * Make sure all freed BOs are cleared in the PT. | |
1795 | * Returns 0 for success. | |
1796 | * | |
1797 | * PTs have to be reserved and mutex must be locked! | |
1798 | */ | |
1799 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1800 | struct amdgpu_vm *vm, |
1801 | struct dma_fence **fence) | |
d38ceaf9 AD |
1802 | { |
1803 | struct amdgpu_bo_va_mapping *mapping; | |
f3467818 | 1804 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1805 | int r; |
1806 | ||
1807 | while (!list_empty(&vm->freed)) { | |
1808 | mapping = list_first_entry(&vm->freed, | |
1809 | struct amdgpu_bo_va_mapping, list); | |
1810 | list_del(&mapping->list); | |
e17841b9 | 1811 | |
fc6aa33d CK |
1812 | r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm, |
1813 | mapping->start, mapping->last, | |
1814 | 0, 0, &f); | |
f3467818 | 1815 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1816 | if (r) { |
f3467818 | 1817 | dma_fence_put(f); |
d38ceaf9 | 1818 | return r; |
284710fa | 1819 | } |
f3467818 | 1820 | } |
d38ceaf9 | 1821 | |
f3467818 NH |
1822 | if (fence && f) { |
1823 | dma_fence_put(*fence); | |
1824 | *fence = f; | |
1825 | } else { | |
1826 | dma_fence_put(f); | |
d38ceaf9 | 1827 | } |
f3467818 | 1828 | |
d38ceaf9 AD |
1829 | return 0; |
1830 | ||
1831 | } | |
1832 | ||
1833 | /** | |
1834 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1835 | * | |
1836 | * @adev: amdgpu_device pointer | |
1837 | * @vm: requested vm | |
1838 | * | |
1839 | * Make sure all invalidated BOs are cleared in the PT. | |
1840 | * Returns 0 for success. | |
1841 | * | |
1842 | * PTs have to be reserved and mutex must be locked! | |
1843 | */ | |
1844 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1845 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1846 | { |
cfe2c978 | 1847 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1848 | int r = 0; |
d38ceaf9 AD |
1849 | |
1850 | spin_lock(&vm->status_lock); | |
1851 | while (!list_empty(&vm->invalidated)) { | |
1852 | bo_va = list_first_entry(&vm->invalidated, | |
1853 | struct amdgpu_bo_va, vm_status); | |
1854 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1855 | |
99e124f4 | 1856 | r = amdgpu_vm_bo_update(adev, bo_va, true); |
d38ceaf9 AD |
1857 | if (r) |
1858 | return r; | |
1859 | ||
1860 | spin_lock(&vm->status_lock); | |
1861 | } | |
1862 | spin_unlock(&vm->status_lock); | |
1863 | ||
cfe2c978 | 1864 | if (bo_va) |
bb1e38a4 | 1865 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1866 | |
1867 | return r; | |
d38ceaf9 AD |
1868 | } |
1869 | ||
1870 | /** | |
1871 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1872 | * | |
1873 | * @adev: amdgpu_device pointer | |
1874 | * @vm: requested vm | |
1875 | * @bo: amdgpu buffer object | |
1876 | * | |
8843dbbb | 1877 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1878 | * Add @bo to the list of bos associated with the vm |
1879 | * Returns newly added bo_va or NULL for failure | |
1880 | * | |
1881 | * Object has to be reserved! | |
1882 | */ | |
1883 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1884 | struct amdgpu_vm *vm, | |
1885 | struct amdgpu_bo *bo) | |
1886 | { | |
1887 | struct amdgpu_bo_va *bo_va; | |
1888 | ||
1889 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1890 | if (bo_va == NULL) { | |
1891 | return NULL; | |
1892 | } | |
1893 | bo_va->vm = vm; | |
1894 | bo_va->bo = bo; | |
d38ceaf9 AD |
1895 | bo_va->ref_count = 1; |
1896 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1897 | INIT_LIST_HEAD(&bo_va->valids); |
1898 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1899 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1900 | |
a5f6b5b1 CK |
1901 | if (bo) |
1902 | list_add_tail(&bo_va->bo_list, &bo->va); | |
d38ceaf9 AD |
1903 | |
1904 | return bo_va; | |
1905 | } | |
1906 | ||
1907 | /** | |
1908 | * amdgpu_vm_bo_map - map bo inside a vm | |
1909 | * | |
1910 | * @adev: amdgpu_device pointer | |
1911 | * @bo_va: bo_va to store the address | |
1912 | * @saddr: where to map the BO | |
1913 | * @offset: requested offset in the BO | |
1914 | * @flags: attributes of pages (read/write/valid/etc.) | |
1915 | * | |
1916 | * Add a mapping of the BO at the specefied addr into the VM. | |
1917 | * Returns 0 for success, error for failure. | |
1918 | * | |
49b02b18 | 1919 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1920 | */ |
1921 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1922 | struct amdgpu_bo_va *bo_va, | |
1923 | uint64_t saddr, uint64_t offset, | |
268c3001 | 1924 | uint64_t size, uint64_t flags) |
d38ceaf9 | 1925 | { |
a9f87f64 | 1926 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
d38ceaf9 | 1927 | struct amdgpu_vm *vm = bo_va->vm; |
d38ceaf9 | 1928 | uint64_t eaddr; |
d38ceaf9 | 1929 | |
0be52de9 CK |
1930 | /* validate the parameters */ |
1931 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1932 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1933 | return -EINVAL; |
0be52de9 | 1934 | |
d38ceaf9 | 1935 | /* make sure object fit at this offset */ |
005ae95e | 1936 | eaddr = saddr + size - 1; |
a5f6b5b1 CK |
1937 | if (saddr >= eaddr || |
1938 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
d38ceaf9 | 1939 | return -EINVAL; |
d38ceaf9 | 1940 | |
d38ceaf9 AD |
1941 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1942 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1943 | ||
a9f87f64 CK |
1944 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
1945 | if (tmp) { | |
d38ceaf9 AD |
1946 | /* bo and tmp overlap, invalid addr */ |
1947 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
a9f87f64 CK |
1948 | "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr, |
1949 | tmp->start, tmp->last + 1); | |
663e4577 | 1950 | return -EINVAL; |
d38ceaf9 AD |
1951 | } |
1952 | ||
1953 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
1954 | if (!mapping) |
1955 | return -ENOMEM; | |
d38ceaf9 AD |
1956 | |
1957 | INIT_LIST_HEAD(&mapping->list); | |
a9f87f64 CK |
1958 | mapping->start = saddr; |
1959 | mapping->last = eaddr; | |
d38ceaf9 AD |
1960 | mapping->offset = offset; |
1961 | mapping->flags = flags; | |
1962 | ||
7fc11959 | 1963 | list_add(&mapping->list, &bo_va->invalids); |
a9f87f64 | 1964 | amdgpu_vm_it_insert(mapping, &vm->va); |
80f95c57 CK |
1965 | |
1966 | if (flags & AMDGPU_PTE_PRT) | |
1967 | amdgpu_vm_prt_get(adev); | |
1968 | ||
1969 | return 0; | |
1970 | } | |
1971 | ||
1972 | /** | |
1973 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
1974 | * | |
1975 | * @adev: amdgpu_device pointer | |
1976 | * @bo_va: bo_va to store the address | |
1977 | * @saddr: where to map the BO | |
1978 | * @offset: requested offset in the BO | |
1979 | * @flags: attributes of pages (read/write/valid/etc.) | |
1980 | * | |
1981 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
1982 | * mappings as we do so. | |
1983 | * Returns 0 for success, error for failure. | |
1984 | * | |
1985 | * Object has to be reserved and unreserved outside! | |
1986 | */ | |
1987 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
1988 | struct amdgpu_bo_va *bo_va, | |
1989 | uint64_t saddr, uint64_t offset, | |
1990 | uint64_t size, uint64_t flags) | |
1991 | { | |
1992 | struct amdgpu_bo_va_mapping *mapping; | |
1993 | struct amdgpu_vm *vm = bo_va->vm; | |
1994 | uint64_t eaddr; | |
1995 | int r; | |
1996 | ||
1997 | /* validate the parameters */ | |
1998 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
1999 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2000 | return -EINVAL; | |
2001 | ||
2002 | /* make sure object fit at this offset */ | |
2003 | eaddr = saddr + size - 1; | |
2004 | if (saddr >= eaddr || | |
2005 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
2006 | return -EINVAL; | |
2007 | ||
2008 | /* Allocate all the needed memory */ | |
2009 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2010 | if (!mapping) | |
2011 | return -ENOMEM; | |
2012 | ||
2013 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size); | |
2014 | if (r) { | |
2015 | kfree(mapping); | |
2016 | return r; | |
2017 | } | |
2018 | ||
2019 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2020 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2021 | ||
a9f87f64 CK |
2022 | mapping->start = saddr; |
2023 | mapping->last = eaddr; | |
80f95c57 CK |
2024 | mapping->offset = offset; |
2025 | mapping->flags = flags; | |
2026 | ||
2027 | list_add(&mapping->list, &bo_va->invalids); | |
a9f87f64 | 2028 | amdgpu_vm_it_insert(mapping, &vm->va); |
d38ceaf9 | 2029 | |
4388fc2a CK |
2030 | if (flags & AMDGPU_PTE_PRT) |
2031 | amdgpu_vm_prt_get(adev); | |
2032 | ||
d38ceaf9 | 2033 | return 0; |
d38ceaf9 AD |
2034 | } |
2035 | ||
2036 | /** | |
2037 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2038 | * | |
2039 | * @adev: amdgpu_device pointer | |
2040 | * @bo_va: bo_va to remove the address from | |
2041 | * @saddr: where to the BO is mapped | |
2042 | * | |
2043 | * Remove a mapping of the BO at the specefied addr from the VM. | |
2044 | * Returns 0 for success, error for failure. | |
2045 | * | |
49b02b18 | 2046 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2047 | */ |
2048 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2049 | struct amdgpu_bo_va *bo_va, | |
2050 | uint64_t saddr) | |
2051 | { | |
2052 | struct amdgpu_bo_va_mapping *mapping; | |
2053 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 2054 | bool valid = true; |
d38ceaf9 | 2055 | |
6c7fc503 | 2056 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2057 | |
7fc11959 | 2058 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2059 | if (mapping->start == saddr) |
d38ceaf9 AD |
2060 | break; |
2061 | } | |
2062 | ||
7fc11959 CK |
2063 | if (&mapping->list == &bo_va->valids) { |
2064 | valid = false; | |
2065 | ||
2066 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2067 | if (mapping->start == saddr) |
7fc11959 CK |
2068 | break; |
2069 | } | |
2070 | ||
32b41ac2 | 2071 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2072 | return -ENOENT; |
d38ceaf9 | 2073 | } |
32b41ac2 | 2074 | |
d38ceaf9 | 2075 | list_del(&mapping->list); |
a9f87f64 | 2076 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2077 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2078 | |
e17841b9 | 2079 | if (valid) |
d38ceaf9 | 2080 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2081 | else |
284710fa CK |
2082 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2083 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2084 | |
2085 | return 0; | |
2086 | } | |
2087 | ||
dc54d3d1 CK |
2088 | /** |
2089 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2090 | * | |
2091 | * @adev: amdgpu_device pointer | |
2092 | * @vm: VM structure to use | |
2093 | * @saddr: start of the range | |
2094 | * @size: size of the range | |
2095 | * | |
2096 | * Remove all mappings in a range, split them as appropriate. | |
2097 | * Returns 0 for success, error for failure. | |
2098 | */ | |
2099 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2100 | struct amdgpu_vm *vm, | |
2101 | uint64_t saddr, uint64_t size) | |
2102 | { | |
2103 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2104 | LIST_HEAD(removed); |
2105 | uint64_t eaddr; | |
2106 | ||
2107 | eaddr = saddr + size - 1; | |
2108 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2109 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2110 | ||
2111 | /* Allocate all the needed memory */ | |
2112 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2113 | if (!before) | |
2114 | return -ENOMEM; | |
27f6d610 | 2115 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2116 | |
2117 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2118 | if (!after) { | |
2119 | kfree(before); | |
2120 | return -ENOMEM; | |
2121 | } | |
27f6d610 | 2122 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2123 | |
2124 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2125 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2126 | while (tmp) { | |
dc54d3d1 | 2127 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2128 | if (tmp->start < saddr) { |
2129 | before->start = tmp->start; | |
2130 | before->last = saddr - 1; | |
dc54d3d1 CK |
2131 | before->offset = tmp->offset; |
2132 | before->flags = tmp->flags; | |
2133 | list_add(&before->list, &tmp->list); | |
2134 | } | |
2135 | ||
2136 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2137 | if (tmp->last > eaddr) { |
2138 | after->start = eaddr + 1; | |
2139 | after->last = tmp->last; | |
dc54d3d1 | 2140 | after->offset = tmp->offset; |
a9f87f64 | 2141 | after->offset += after->start - tmp->start; |
dc54d3d1 CK |
2142 | after->flags = tmp->flags; |
2143 | list_add(&after->list, &tmp->list); | |
2144 | } | |
2145 | ||
2146 | list_del(&tmp->list); | |
2147 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2148 | |
2149 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2150 | } |
2151 | ||
2152 | /* And free them up */ | |
2153 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2154 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2155 | list_del(&tmp->list); |
2156 | ||
a9f87f64 CK |
2157 | if (tmp->start < saddr) |
2158 | tmp->start = saddr; | |
2159 | if (tmp->last > eaddr) | |
2160 | tmp->last = eaddr; | |
dc54d3d1 CK |
2161 | |
2162 | list_add(&tmp->list, &vm->freed); | |
2163 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2164 | } | |
2165 | ||
27f6d610 JZ |
2166 | /* Insert partial mapping before the range */ |
2167 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2168 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2169 | if (before->flags & AMDGPU_PTE_PRT) |
2170 | amdgpu_vm_prt_get(adev); | |
2171 | } else { | |
2172 | kfree(before); | |
2173 | } | |
2174 | ||
2175 | /* Insert partial mapping after the range */ | |
27f6d610 | 2176 | if (!list_empty(&after->list)) { |
a9f87f64 | 2177 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2178 | if (after->flags & AMDGPU_PTE_PRT) |
2179 | amdgpu_vm_prt_get(adev); | |
2180 | } else { | |
2181 | kfree(after); | |
2182 | } | |
2183 | ||
2184 | return 0; | |
2185 | } | |
2186 | ||
d38ceaf9 AD |
2187 | /** |
2188 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2189 | * | |
2190 | * @adev: amdgpu_device pointer | |
2191 | * @bo_va: requested bo_va | |
2192 | * | |
8843dbbb | 2193 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2194 | * |
2195 | * Object have to be reserved! | |
2196 | */ | |
2197 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2198 | struct amdgpu_bo_va *bo_va) | |
2199 | { | |
2200 | struct amdgpu_bo_va_mapping *mapping, *next; | |
2201 | struct amdgpu_vm *vm = bo_va->vm; | |
2202 | ||
2203 | list_del(&bo_va->bo_list); | |
2204 | ||
d38ceaf9 AD |
2205 | spin_lock(&vm->status_lock); |
2206 | list_del(&bo_va->vm_status); | |
2207 | spin_unlock(&vm->status_lock); | |
2208 | ||
7fc11959 | 2209 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2210 | list_del(&mapping->list); |
a9f87f64 | 2211 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2212 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2213 | list_add(&mapping->list, &vm->freed); |
2214 | } | |
2215 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2216 | list_del(&mapping->list); | |
a9f87f64 | 2217 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2218 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2219 | bo_va->last_pt_update); | |
d38ceaf9 | 2220 | } |
32b41ac2 | 2221 | |
f54d1867 | 2222 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2223 | kfree(bo_va); |
d38ceaf9 AD |
2224 | } |
2225 | ||
2226 | /** | |
2227 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2228 | * | |
2229 | * @adev: amdgpu_device pointer | |
2230 | * @vm: requested vm | |
2231 | * @bo: amdgpu buffer object | |
2232 | * | |
8843dbbb | 2233 | * Mark @bo as invalid. |
d38ceaf9 AD |
2234 | */ |
2235 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
2236 | struct amdgpu_bo *bo) | |
2237 | { | |
2238 | struct amdgpu_bo_va *bo_va; | |
2239 | ||
2240 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
2241 | spin_lock(&bo_va->vm->status_lock); |
2242 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 2243 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 2244 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
2245 | } |
2246 | } | |
2247 | ||
bab4fee7 JZ |
2248 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2249 | { | |
2250 | /* Total bits covered by PD + PTs */ | |
2251 | unsigned bits = ilog2(vm_size) + 18; | |
2252 | ||
2253 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2254 | Above that split equal between PD and PTs */ | |
2255 | if (vm_size <= 8) | |
2256 | return (bits - 9); | |
2257 | else | |
2258 | return ((bits + 3) / 2); | |
2259 | } | |
2260 | ||
2261 | /** | |
2262 | * amdgpu_vm_adjust_size - adjust vm size and block size | |
2263 | * | |
2264 | * @adev: amdgpu_device pointer | |
2265 | * @vm_size: the default vm size if it's set auto | |
2266 | */ | |
2267 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) | |
2268 | { | |
2269 | /* adjust vm size firstly */ | |
2270 | if (amdgpu_vm_size == -1) | |
2271 | adev->vm_manager.vm_size = vm_size; | |
2272 | else | |
2273 | adev->vm_manager.vm_size = amdgpu_vm_size; | |
2274 | ||
2275 | /* block size depends on vm size */ | |
2276 | if (amdgpu_vm_block_size == -1) | |
2277 | adev->vm_manager.block_size = | |
2278 | amdgpu_vm_get_block_size(adev->vm_manager.vm_size); | |
2279 | else | |
2280 | adev->vm_manager.block_size = amdgpu_vm_block_size; | |
2281 | ||
2282 | DRM_INFO("vm size is %llu GB, block size is %u-bit\n", | |
2283 | adev->vm_manager.vm_size, adev->vm_manager.block_size); | |
2284 | } | |
2285 | ||
d38ceaf9 AD |
2286 | /** |
2287 | * amdgpu_vm_init - initialize a vm instance | |
2288 | * | |
2289 | * @adev: amdgpu_device pointer | |
2290 | * @vm: requested vm | |
2291 | * | |
8843dbbb | 2292 | * Init @vm fields. |
d38ceaf9 AD |
2293 | */ |
2294 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2295 | { | |
2296 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
36b32a68 | 2297 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2298 | unsigned ring_instance; |
2299 | struct amdgpu_ring *ring; | |
2bd9ccfa | 2300 | struct amd_sched_rq *rq; |
36bbf3bf | 2301 | int r, i; |
d38ceaf9 | 2302 | |
d38ceaf9 | 2303 | vm->va = RB_ROOT; |
031e2983 | 2304 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
36bbf3bf CZ |
2305 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2306 | vm->reserved_vmid[i] = NULL; | |
d38ceaf9 AD |
2307 | spin_lock_init(&vm->status_lock); |
2308 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 2309 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 2310 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2311 | |
2bd9ccfa | 2312 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2313 | |
2314 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2315 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2316 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
2317 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
2318 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
2319 | rq, amdgpu_sched_jobs); | |
2320 | if (r) | |
f566ceb1 | 2321 | return r; |
2bd9ccfa | 2322 | |
a24960f3 | 2323 | vm->last_dir_update = NULL; |
05906dec | 2324 | |
f566ceb1 | 2325 | r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, |
857d913d | 2326 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f | 2327 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
03f48dd5 | 2328 | AMDGPU_GEM_CREATE_SHADOW | |
617859e0 CK |
2329 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
2330 | AMDGPU_GEM_CREATE_VRAM_CLEARED, | |
67003a15 | 2331 | NULL, NULL, &vm->root.bo); |
d38ceaf9 | 2332 | if (r) |
2bd9ccfa CK |
2333 | goto error_free_sched_entity; |
2334 | ||
67003a15 | 2335 | r = amdgpu_bo_reserve(vm->root.bo, false); |
2bd9ccfa | 2336 | if (r) |
67003a15 | 2337 | goto error_free_root; |
2bd9ccfa | 2338 | |
5a712a87 | 2339 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
67003a15 | 2340 | amdgpu_bo_unreserve(vm->root.bo); |
d38ceaf9 AD |
2341 | |
2342 | return 0; | |
2bd9ccfa | 2343 | |
67003a15 CK |
2344 | error_free_root: |
2345 | amdgpu_bo_unref(&vm->root.bo->shadow); | |
2346 | amdgpu_bo_unref(&vm->root.bo); | |
2347 | vm->root.bo = NULL; | |
2bd9ccfa CK |
2348 | |
2349 | error_free_sched_entity: | |
2350 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
2351 | ||
2352 | return r; | |
d38ceaf9 AD |
2353 | } |
2354 | ||
f566ceb1 CK |
2355 | /** |
2356 | * amdgpu_vm_free_levels - free PD/PT levels | |
2357 | * | |
2358 | * @level: PD/PT starting level to free | |
2359 | * | |
2360 | * Free the page directory or page table level and all sub levels. | |
2361 | */ | |
2362 | static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) | |
2363 | { | |
2364 | unsigned i; | |
2365 | ||
2366 | if (level->bo) { | |
2367 | amdgpu_bo_unref(&level->bo->shadow); | |
2368 | amdgpu_bo_unref(&level->bo); | |
2369 | } | |
2370 | ||
2371 | if (level->entries) | |
2372 | for (i = 0; i <= level->last_entry_used; i++) | |
2373 | amdgpu_vm_free_levels(&level->entries[i]); | |
2374 | ||
2375 | drm_free_large(level->entries); | |
2376 | } | |
2377 | ||
d38ceaf9 AD |
2378 | /** |
2379 | * amdgpu_vm_fini - tear down a vm instance | |
2380 | * | |
2381 | * @adev: amdgpu_device pointer | |
2382 | * @vm: requested vm | |
2383 | * | |
8843dbbb | 2384 | * Tear down @vm. |
d38ceaf9 AD |
2385 | * Unbind the VM and remove all bos from the vm bo list |
2386 | */ | |
2387 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2388 | { | |
2389 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
4388fc2a | 2390 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
36bbf3bf | 2391 | int i; |
d38ceaf9 | 2392 | |
2d55e45a | 2393 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 2394 | |
d38ceaf9 AD |
2395 | if (!RB_EMPTY_ROOT(&vm->va)) { |
2396 | dev_err(adev->dev, "still active bo inside vm\n"); | |
2397 | } | |
a9f87f64 | 2398 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) { |
d38ceaf9 | 2399 | list_del(&mapping->list); |
a9f87f64 | 2400 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2401 | kfree(mapping); |
2402 | } | |
2403 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2404 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2405 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2406 | prt_fini_needed = false; |
451bc8eb | 2407 | } |
284710fa | 2408 | |
d38ceaf9 | 2409 | list_del(&mapping->list); |
451bc8eb | 2410 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2411 | } |
2412 | ||
f566ceb1 | 2413 | amdgpu_vm_free_levels(&vm->root); |
a24960f3 | 2414 | dma_fence_put(vm->last_dir_update); |
1e9ef26f CZ |
2415 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2416 | amdgpu_vm_free_reserved_vmid(adev, vm, i); | |
d38ceaf9 | 2417 | } |
ea89f8c9 | 2418 | |
a9a78b32 CK |
2419 | /** |
2420 | * amdgpu_vm_manager_init - init the VM manager | |
2421 | * | |
2422 | * @adev: amdgpu_device pointer | |
2423 | * | |
2424 | * Initialize the VM manager structures | |
2425 | */ | |
2426 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2427 | { | |
7645670d CK |
2428 | unsigned i, j; |
2429 | ||
2430 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
2431 | struct amdgpu_vm_id_manager *id_mgr = | |
2432 | &adev->vm_manager.id_mgr[i]; | |
a9a78b32 | 2433 | |
7645670d CK |
2434 | mutex_init(&id_mgr->lock); |
2435 | INIT_LIST_HEAD(&id_mgr->ids_lru); | |
c3505770 | 2436 | atomic_set(&id_mgr->reserved_vmid_num, 0); |
a9a78b32 | 2437 | |
7645670d CK |
2438 | /* skip over VMID 0, since it is the system VM */ |
2439 | for (j = 1; j < id_mgr->num_ids; ++j) { | |
2440 | amdgpu_vm_reset_id(adev, i, j); | |
2441 | amdgpu_sync_create(&id_mgr->ids[i].active); | |
2442 | list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); | |
2443 | } | |
971fe9a9 | 2444 | } |
2d55e45a | 2445 | |
f54d1867 CW |
2446 | adev->vm_manager.fence_context = |
2447 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2448 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2449 | adev->vm_manager.seqno[i] = 0; | |
2450 | ||
2d55e45a | 2451 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 2452 | atomic64_set(&adev->vm_manager.client_counter, 0); |
284710fa | 2453 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2454 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
a9a78b32 CK |
2455 | } |
2456 | ||
ea89f8c9 CK |
2457 | /** |
2458 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2459 | * | |
2460 | * @adev: amdgpu_device pointer | |
2461 | * | |
2462 | * Cleanup the VM manager and free resources. | |
2463 | */ | |
2464 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2465 | { | |
7645670d | 2466 | unsigned i, j; |
ea89f8c9 | 2467 | |
7645670d CK |
2468 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
2469 | struct amdgpu_vm_id_manager *id_mgr = | |
2470 | &adev->vm_manager.id_mgr[i]; | |
bcb1ba35 | 2471 | |
7645670d CK |
2472 | mutex_destroy(&id_mgr->lock); |
2473 | for (j = 0; j < AMDGPU_NUM_VM; ++j) { | |
2474 | struct amdgpu_vm_id *id = &id_mgr->ids[j]; | |
2475 | ||
2476 | amdgpu_sync_free(&id->active); | |
2477 | dma_fence_put(id->flushed_updates); | |
2478 | dma_fence_put(id->last_flush); | |
2479 | } | |
bcb1ba35 | 2480 | } |
ea89f8c9 | 2481 | } |
cfbcacf4 CZ |
2482 | |
2483 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
2484 | { | |
2485 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
2486 | struct amdgpu_device *adev = dev->dev_private; |
2487 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
2488 | int r; | |
cfbcacf4 CZ |
2489 | |
2490 | switch (args->in.op) { | |
2491 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f CZ |
2492 | /* current, we only have requirement to reserve vmid from gfxhub */ |
2493 | r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm, | |
2494 | AMDGPU_GFXHUB); | |
2495 | if (r) | |
2496 | return r; | |
2497 | break; | |
cfbcacf4 | 2498 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
1e9ef26f | 2499 | amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
2500 | break; |
2501 | default: | |
2502 | return -EINVAL; | |
2503 | } | |
2504 | ||
2505 | return 0; | |
2506 | } |