]>
Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
4ff37a83 CK |
53 | /* Special value that no flush is necessary */ |
54 | #define AMDGPU_VM_NO_FLUSH (~0ll) | |
55 | ||
d38ceaf9 AD |
56 | /** |
57 | * amdgpu_vm_num_pde - return the number of page directory entries | |
58 | * | |
59 | * @adev: amdgpu_device pointer | |
60 | * | |
8843dbbb | 61 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
62 | */ |
63 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
64 | { | |
65 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
66 | } | |
67 | ||
68 | /** | |
69 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
70 | * | |
71 | * @adev: amdgpu_device pointer | |
72 | * | |
8843dbbb | 73 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
74 | */ |
75 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
76 | { | |
77 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
78 | } | |
79 | ||
80 | /** | |
56467ebf | 81 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
82 | * |
83 | * @vm: vm providing the BOs | |
3c0eea6c | 84 | * @validated: head of validation list |
56467ebf | 85 | * @entry: entry to add |
d38ceaf9 AD |
86 | * |
87 | * Add the page directory to the list of BOs to | |
56467ebf | 88 | * validate for command submission. |
d38ceaf9 | 89 | */ |
56467ebf CK |
90 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
91 | struct list_head *validated, | |
92 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 93 | { |
56467ebf | 94 | entry->robj = vm->page_directory; |
56467ebf CK |
95 | entry->priority = 0; |
96 | entry->tv.bo = &vm->page_directory->tbo; | |
97 | entry->tv.shared = true; | |
2f568dbd | 98 | entry->user_pages = NULL; |
56467ebf CK |
99 | list_add(&entry->tv.head, validated); |
100 | } | |
d38ceaf9 | 101 | |
56467ebf | 102 | /** |
ee1782c3 | 103 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf CK |
104 | * |
105 | * @vm: vm providing the BOs | |
3c0eea6c | 106 | * @duplicates: head of duplicates list |
d38ceaf9 | 107 | * |
ee1782c3 CK |
108 | * Add the page directory to the BO duplicates list |
109 | * for command submission. | |
d38ceaf9 | 110 | */ |
ee1782c3 | 111 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates) |
d38ceaf9 | 112 | { |
ee1782c3 | 113 | unsigned i; |
d38ceaf9 AD |
114 | |
115 | /* add the vm page table to the list */ | |
ee1782c3 CK |
116 | for (i = 0; i <= vm->max_pde_used; ++i) { |
117 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
118 | ||
119 | if (!entry->robj) | |
d38ceaf9 AD |
120 | continue; |
121 | ||
ee1782c3 | 122 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 123 | } |
eceb8a15 CK |
124 | |
125 | } | |
126 | ||
127 | /** | |
128 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
129 | * | |
130 | * @adev: amdgpu device instance | |
131 | * @vm: vm providing the BOs | |
132 | * | |
133 | * Move the PT BOs to the tail of the LRU. | |
134 | */ | |
135 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
136 | struct amdgpu_vm *vm) | |
137 | { | |
138 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
139 | unsigned i; | |
140 | ||
141 | spin_lock(&glob->lru_lock); | |
142 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
143 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
144 | ||
145 | if (!entry->robj) | |
146 | continue; | |
147 | ||
148 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
149 | } | |
150 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
151 | } |
152 | ||
153 | /** | |
154 | * amdgpu_vm_grab_id - allocate the next free VMID | |
155 | * | |
d38ceaf9 | 156 | * @vm: vm to allocate id for |
7f8a5290 CK |
157 | * @ring: ring we want to submit job to |
158 | * @sync: sync object where we add dependencies | |
94dd0a4a | 159 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 160 | * |
7f8a5290 | 161 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 162 | */ |
7f8a5290 | 163 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 CK |
164 | struct amdgpu_sync *sync, struct fence *fence, |
165 | unsigned *vm_id, uint64_t *vm_pd_addr) | |
d38ceaf9 | 166 | { |
4ff37a83 | 167 | uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); |
d38ceaf9 | 168 | struct amdgpu_device *adev = ring->adev; |
4ff37a83 CK |
169 | struct amdgpu_vm_id *id = &vm->ids[ring->idx]; |
170 | struct fence *updates = sync->last_vm_update; | |
a9a78b32 | 171 | int r; |
d38ceaf9 | 172 | |
94dd0a4a CK |
173 | mutex_lock(&adev->vm_manager.lock); |
174 | ||
d38ceaf9 | 175 | /* check if the id is still valid */ |
4ff37a83 CK |
176 | if (id->mgr_id) { |
177 | struct fence *flushed = id->flushed_updates; | |
178 | bool is_later; | |
1c16c0a7 CK |
179 | long owner; |
180 | ||
4ff37a83 CK |
181 | if (!flushed) |
182 | is_later = true; | |
183 | else if (!updates) | |
184 | is_later = false; | |
185 | else | |
186 | is_later = fence_is_later(updates, flushed); | |
187 | ||
188 | owner = atomic_long_read(&id->mgr_id->owner); | |
189 | if (!is_later && owner == (long)id && | |
190 | pd_addr == id->pd_gpu_addr) { | |
191 | ||
a8bd1bec CK |
192 | r = amdgpu_sync_fence(ring->adev, sync, |
193 | id->mgr_id->active); | |
194 | if (r) { | |
195 | mutex_unlock(&adev->vm_manager.lock); | |
196 | return r; | |
197 | } | |
198 | ||
4ff37a83 CK |
199 | fence_put(id->mgr_id->active); |
200 | id->mgr_id->active = fence_get(fence); | |
201 | ||
202 | list_move_tail(&id->mgr_id->list, | |
203 | &adev->vm_manager.ids_lru); | |
d38ceaf9 | 204 | |
4ff37a83 CK |
205 | *vm_id = id->mgr_id - adev->vm_manager.ids; |
206 | *vm_pd_addr = AMDGPU_VM_NO_FLUSH; | |
22073fe7 CK |
207 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, |
208 | *vm_pd_addr); | |
d38ceaf9 | 209 | |
94dd0a4a | 210 | mutex_unlock(&adev->vm_manager.lock); |
7f8a5290 | 211 | return 0; |
d38ceaf9 | 212 | } |
d38ceaf9 AD |
213 | } |
214 | ||
4ff37a83 CK |
215 | id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru, |
216 | struct amdgpu_vm_manager_id, | |
217 | list); | |
7f8a5290 | 218 | |
4ff37a83 CK |
219 | r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active); |
220 | if (!r) { | |
221 | fence_put(id->mgr_id->active); | |
222 | id->mgr_id->active = fence_get(fence); | |
94dd0a4a | 223 | |
4ff37a83 CK |
224 | fence_put(id->flushed_updates); |
225 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 226 | |
4ff37a83 | 227 | id->pd_gpu_addr = pd_addr; |
94dd0a4a | 228 | |
4ff37a83 CK |
229 | list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru); |
230 | atomic_long_set(&id->mgr_id->owner, (long)id); | |
231 | ||
232 | *vm_id = id->mgr_id - adev->vm_manager.ids; | |
233 | *vm_pd_addr = pd_addr; | |
22073fe7 | 234 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); |
d38ceaf9 AD |
235 | } |
236 | ||
94dd0a4a | 237 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 238 | return r; |
d38ceaf9 AD |
239 | } |
240 | ||
241 | /** | |
242 | * amdgpu_vm_flush - hardware flush the vm | |
243 | * | |
244 | * @ring: ring to use for flush | |
cffadc83 | 245 | * @vm_id: vmid number to use |
4ff37a83 | 246 | * @pd_addr: address of the page directory |
d38ceaf9 | 247 | * |
4ff37a83 | 248 | * Emit a VM flush when it is necessary. |
d38ceaf9 AD |
249 | */ |
250 | void amdgpu_vm_flush(struct amdgpu_ring *ring, | |
cffadc83 CK |
251 | unsigned vm_id, uint64_t pd_addr, |
252 | uint32_t gds_base, uint32_t gds_size, | |
253 | uint32_t gws_base, uint32_t gws_size, | |
254 | uint32_t oa_base, uint32_t oa_size) | |
d38ceaf9 | 255 | { |
971fe9a9 CK |
256 | struct amdgpu_device *adev = ring->adev; |
257 | struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; | |
d564a06e CK |
258 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
259 | mgr_id->gds_base != gds_base || | |
260 | mgr_id->gds_size != gds_size || | |
261 | mgr_id->gws_base != gws_base || | |
262 | mgr_id->gws_size != gws_size || | |
263 | mgr_id->oa_base != oa_base || | |
264 | mgr_id->oa_size != oa_size); | |
265 | ||
266 | if (ring->funcs->emit_pipeline_sync && ( | |
267 | pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed)) | |
268 | amdgpu_ring_emit_pipeline_sync(ring); | |
971fe9a9 | 269 | |
4ff37a83 | 270 | if (pd_addr != AMDGPU_VM_NO_FLUSH) { |
cffadc83 CK |
271 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); |
272 | amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); | |
d38ceaf9 | 273 | } |
cffadc83 | 274 | |
d564a06e | 275 | if (gds_switch_needed) { |
971fe9a9 CK |
276 | mgr_id->gds_base = gds_base; |
277 | mgr_id->gds_size = gds_size; | |
278 | mgr_id->gws_base = gws_base; | |
279 | mgr_id->gws_size = gws_size; | |
280 | mgr_id->oa_base = oa_base; | |
281 | mgr_id->oa_size = oa_size; | |
cffadc83 CK |
282 | amdgpu_ring_emit_gds_switch(ring, vm_id, |
283 | gds_base, gds_size, | |
284 | gws_base, gws_size, | |
285 | oa_base, oa_size); | |
971fe9a9 CK |
286 | } |
287 | } | |
288 | ||
289 | /** | |
290 | * amdgpu_vm_reset_id - reset VMID to zero | |
291 | * | |
292 | * @adev: amdgpu device structure | |
293 | * @vm_id: vmid number to use | |
294 | * | |
295 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
296 | */ | |
297 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
298 | { | |
299 | struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; | |
300 | ||
301 | mgr_id->gds_base = 0; | |
302 | mgr_id->gds_size = 0; | |
303 | mgr_id->gws_base = 0; | |
304 | mgr_id->gws_size = 0; | |
305 | mgr_id->oa_base = 0; | |
306 | mgr_id->oa_size = 0; | |
d38ceaf9 AD |
307 | } |
308 | ||
d38ceaf9 AD |
309 | /** |
310 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
311 | * | |
312 | * @vm: requested vm | |
313 | * @bo: requested buffer object | |
314 | * | |
8843dbbb | 315 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
316 | * Search inside the @bos vm list for the requested vm |
317 | * Returns the found bo_va or NULL if none is found | |
318 | * | |
319 | * Object has to be reserved! | |
320 | */ | |
321 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
322 | struct amdgpu_bo *bo) | |
323 | { | |
324 | struct amdgpu_bo_va *bo_va; | |
325 | ||
326 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
327 | if (bo_va->vm == vm) { | |
328 | return bo_va; | |
329 | } | |
330 | } | |
331 | return NULL; | |
332 | } | |
333 | ||
334 | /** | |
335 | * amdgpu_vm_update_pages - helper to call the right asic function | |
336 | * | |
337 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
338 | * @gtt: GART instance to use for mapping |
339 | * @gtt_flags: GTT hw access flags | |
d38ceaf9 AD |
340 | * @ib: indirect buffer to fill with commands |
341 | * @pe: addr of the page entry | |
342 | * @addr: dst addr to write into pe | |
343 | * @count: number of page entries to update | |
344 | * @incr: increase next addr by incr bytes | |
345 | * @flags: hw access flags | |
d38ceaf9 AD |
346 | * |
347 | * Traces the parameters and calls the right asic functions | |
348 | * to setup the page table using the DMA. | |
349 | */ | |
350 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
9ab21462 CK |
351 | struct amdgpu_gart *gtt, |
352 | uint32_t gtt_flags, | |
d38ceaf9 AD |
353 | struct amdgpu_ib *ib, |
354 | uint64_t pe, uint64_t addr, | |
355 | unsigned count, uint32_t incr, | |
9ab21462 | 356 | uint32_t flags) |
d38ceaf9 AD |
357 | { |
358 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
359 | ||
9ab21462 CK |
360 | if ((gtt == &adev->gart) && (flags == gtt_flags)) { |
361 | uint64_t src = gtt->table_addr + (addr >> 12) * 8; | |
d38ceaf9 AD |
362 | amdgpu_vm_copy_pte(adev, ib, pe, src, count); |
363 | ||
9ab21462 CK |
364 | } else if (gtt) { |
365 | dma_addr_t *pages_addr = gtt->pages_addr; | |
b07c9d2a CK |
366 | amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr, |
367 | count, incr, flags); | |
368 | ||
369 | } else if (count < 3) { | |
370 | amdgpu_vm_write_pte(adev, ib, NULL, pe, addr, | |
371 | count, incr, flags); | |
d38ceaf9 AD |
372 | |
373 | } else { | |
374 | amdgpu_vm_set_pte_pde(adev, ib, pe, addr, | |
375 | count, incr, flags); | |
376 | } | |
377 | } | |
378 | ||
379 | /** | |
380 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
381 | * | |
382 | * @adev: amdgpu_device pointer | |
383 | * @bo: bo to clear | |
ef9f0a83 CZ |
384 | * |
385 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
386 | */ |
387 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 388 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
389 | struct amdgpu_bo *bo) |
390 | { | |
2d55e45a | 391 | struct amdgpu_ring *ring; |
4af9f07c | 392 | struct fence *fence = NULL; |
d71518b5 | 393 | struct amdgpu_job *job; |
d38ceaf9 AD |
394 | unsigned entries; |
395 | uint64_t addr; | |
396 | int r; | |
397 | ||
2d55e45a CK |
398 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
399 | ||
ca952613 | 400 | r = reservation_object_reserve_shared(bo->tbo.resv); |
401 | if (r) | |
402 | return r; | |
403 | ||
d38ceaf9 AD |
404 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
405 | if (r) | |
ef9f0a83 | 406 | goto error; |
d38ceaf9 AD |
407 | |
408 | addr = amdgpu_bo_gpu_offset(bo); | |
409 | entries = amdgpu_bo_size(bo) / 8; | |
410 | ||
d71518b5 CK |
411 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
412 | if (r) | |
ef9f0a83 | 413 | goto error; |
d38ceaf9 | 414 | |
d71518b5 CK |
415 | amdgpu_vm_update_pages(adev, NULL, 0, &job->ibs[0], addr, 0, entries, |
416 | 0, 0); | |
417 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); | |
418 | ||
419 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
420 | r = amdgpu_job_submit(job, ring, &vm->entity, |
421 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
422 | if (r) |
423 | goto error_free; | |
424 | ||
d71518b5 | 425 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 426 | fence_put(fence); |
cadf97b1 | 427 | return 0; |
ef9f0a83 | 428 | |
d38ceaf9 | 429 | error_free: |
d71518b5 | 430 | amdgpu_job_free(job); |
d38ceaf9 | 431 | |
ef9f0a83 | 432 | error: |
d38ceaf9 AD |
433 | return r; |
434 | } | |
435 | ||
436 | /** | |
b07c9d2a | 437 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 438 | * |
b07c9d2a | 439 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
440 | * @addr: the unmapped addr |
441 | * | |
442 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 443 | * to and return the pointer for the page table entry. |
d38ceaf9 | 444 | */ |
b07c9d2a | 445 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
446 | { |
447 | uint64_t result; | |
448 | ||
b07c9d2a CK |
449 | if (pages_addr) { |
450 | /* page table offset */ | |
451 | result = pages_addr[addr >> PAGE_SHIFT]; | |
452 | ||
453 | /* in case cpu page size != gpu page size*/ | |
454 | result |= addr & (~PAGE_MASK); | |
455 | ||
456 | } else { | |
457 | /* No mapping required */ | |
458 | result = addr; | |
459 | } | |
d38ceaf9 | 460 | |
b07c9d2a | 461 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
462 | |
463 | return result; | |
464 | } | |
465 | ||
466 | /** | |
467 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
468 | * | |
469 | * @adev: amdgpu_device pointer | |
470 | * @vm: requested vm | |
471 | * @start: start of GPU address range | |
472 | * @end: end of GPU address range | |
473 | * | |
474 | * Allocates new page tables if necessary | |
8843dbbb | 475 | * and updates the page directory. |
d38ceaf9 | 476 | * Returns 0 for success, error for failure. |
d38ceaf9 AD |
477 | */ |
478 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
479 | struct amdgpu_vm *vm) | |
480 | { | |
2d55e45a | 481 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
482 | struct amdgpu_bo *pd = vm->page_directory; |
483 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
484 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
485 | uint64_t last_pde = ~0, last_pt = ~0; | |
486 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 487 | struct amdgpu_job *job; |
d5fc5e82 | 488 | struct amdgpu_ib *ib; |
4af9f07c | 489 | struct fence *fence = NULL; |
d5fc5e82 | 490 | |
d38ceaf9 AD |
491 | int r; |
492 | ||
2d55e45a CK |
493 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
494 | ||
d38ceaf9 AD |
495 | /* padding, etc. */ |
496 | ndw = 64; | |
497 | ||
498 | /* assume the worst case */ | |
499 | ndw += vm->max_pde_used * 6; | |
500 | ||
d71518b5 CK |
501 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
502 | if (r) | |
d38ceaf9 | 503 | return r; |
d71518b5 CK |
504 | |
505 | ib = &job->ibs[0]; | |
d38ceaf9 AD |
506 | |
507 | /* walk over the address space and update the page directory */ | |
508 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 509 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
510 | uint64_t pde, pt; |
511 | ||
512 | if (bo == NULL) | |
513 | continue; | |
514 | ||
515 | pt = amdgpu_bo_gpu_offset(bo); | |
516 | if (vm->page_tables[pt_idx].addr == pt) | |
517 | continue; | |
518 | vm->page_tables[pt_idx].addr = pt; | |
519 | ||
520 | pde = pd_addr + pt_idx * 8; | |
521 | if (((last_pde + 8 * count) != pde) || | |
522 | ((last_pt + incr * count) != pt)) { | |
523 | ||
524 | if (count) { | |
9ab21462 CK |
525 | amdgpu_vm_update_pages(adev, NULL, 0, ib, |
526 | last_pde, last_pt, | |
527 | count, incr, | |
528 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
529 | } |
530 | ||
531 | count = 1; | |
532 | last_pde = pde; | |
533 | last_pt = pt; | |
534 | } else { | |
535 | ++count; | |
536 | } | |
537 | } | |
538 | ||
539 | if (count) | |
9ab21462 CK |
540 | amdgpu_vm_update_pages(adev, NULL, 0, ib, last_pde, last_pt, |
541 | count, incr, AMDGPU_PTE_VALID); | |
d38ceaf9 | 542 | |
d5fc5e82 | 543 | if (ib->length_dw != 0) { |
9e5d5309 | 544 | amdgpu_ring_pad_ib(ring, ib); |
e86f9cee CK |
545 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
546 | AMDGPU_FENCE_OWNER_VM); | |
d5fc5e82 | 547 | WARN_ON(ib->length_dw > ndw); |
2bd9ccfa CK |
548 | r = amdgpu_job_submit(job, ring, &vm->entity, |
549 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
550 | if (r) |
551 | goto error_free; | |
05906dec | 552 | |
4af9f07c | 553 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
554 | fence_put(vm->page_directory_fence); |
555 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 556 | fence_put(fence); |
d5fc5e82 | 557 | |
d71518b5 CK |
558 | } else { |
559 | amdgpu_job_free(job); | |
d5fc5e82 | 560 | } |
d38ceaf9 AD |
561 | |
562 | return 0; | |
d5fc5e82 CZ |
563 | |
564 | error_free: | |
d71518b5 | 565 | amdgpu_job_free(job); |
4af9f07c | 566 | return r; |
d38ceaf9 AD |
567 | } |
568 | ||
569 | /** | |
570 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
571 | * | |
572 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
573 | * @gtt: GART instance to use for mapping |
574 | * @gtt_flags: GTT hw mapping flags | |
d38ceaf9 AD |
575 | * @ib: IB for the update |
576 | * @pe_start: first PTE to handle | |
577 | * @pe_end: last PTE to handle | |
578 | * @addr: addr those PTEs should point to | |
579 | * @flags: hw mapping flags | |
d38ceaf9 AD |
580 | */ |
581 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
9ab21462 CK |
582 | struct amdgpu_gart *gtt, |
583 | uint32_t gtt_flags, | |
d38ceaf9 AD |
584 | struct amdgpu_ib *ib, |
585 | uint64_t pe_start, uint64_t pe_end, | |
9ab21462 | 586 | uint64_t addr, uint32_t flags) |
d38ceaf9 AD |
587 | { |
588 | /** | |
589 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
590 | * field in the PTE. When this field is set to a non-zero value, page | |
591 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
592 | * flags are considered valid for all PTEs within the fragment range | |
593 | * and corresponding mappings are assumed to be physically contiguous. | |
594 | * | |
595 | * The L1 TLB can store a single PTE for the whole fragment, | |
596 | * significantly increasing the space available for translation | |
597 | * caching. This leads to large improvements in throughput when the | |
598 | * TLB is under pressure. | |
599 | * | |
600 | * The L2 TLB distributes small and large fragments into two | |
601 | * asymmetric partitions. The large fragment cache is significantly | |
602 | * larger. Thus, we try to use large fragments wherever possible. | |
603 | * Userspace can support this by aligning virtual base address and | |
604 | * allocation size to the fragment size. | |
605 | */ | |
606 | ||
607 | /* SI and newer are optimized for 64KB */ | |
608 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
609 | uint64_t frag_align = 0x80; | |
610 | ||
611 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
612 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
613 | ||
614 | unsigned count; | |
615 | ||
31f6c1fe CK |
616 | /* Abort early if there isn't anything to do */ |
617 | if (pe_start == pe_end) | |
618 | return; | |
619 | ||
d38ceaf9 | 620 | /* system pages are non continuously */ |
9ab21462 | 621 | if (gtt || !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) { |
d38ceaf9 AD |
622 | |
623 | count = (pe_end - pe_start) / 8; | |
9ab21462 CK |
624 | amdgpu_vm_update_pages(adev, gtt, gtt_flags, ib, pe_start, |
625 | addr, count, AMDGPU_GPU_PAGE_SIZE, | |
626 | flags); | |
d38ceaf9 AD |
627 | return; |
628 | } | |
629 | ||
630 | /* handle the 4K area at the beginning */ | |
631 | if (pe_start != frag_start) { | |
632 | count = (frag_start - pe_start) / 8; | |
9ab21462 CK |
633 | amdgpu_vm_update_pages(adev, NULL, 0, ib, pe_start, addr, |
634 | count, AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
635 | addr += AMDGPU_GPU_PAGE_SIZE * count; |
636 | } | |
637 | ||
638 | /* handle the area in the middle */ | |
639 | count = (frag_end - frag_start) / 8; | |
9ab21462 CK |
640 | amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_start, addr, count, |
641 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags); | |
d38ceaf9 AD |
642 | |
643 | /* handle the 4K area at the end */ | |
644 | if (frag_end != pe_end) { | |
645 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
646 | count = (pe_end - frag_end) / 8; | |
9ab21462 CK |
647 | amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_end, addr, |
648 | count, AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
649 | } |
650 | } | |
651 | ||
652 | /** | |
653 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
654 | * | |
655 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
656 | * @gtt: GART instance to use for mapping |
657 | * @gtt_flags: GTT hw mapping flags | |
d38ceaf9 AD |
658 | * @vm: requested vm |
659 | * @start: start of GPU address range | |
660 | * @end: end of GPU address range | |
661 | * @dst: destination address to map to | |
662 | * @flags: mapping flags | |
663 | * | |
8843dbbb | 664 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 665 | */ |
a1e08d3b CK |
666 | static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, |
667 | struct amdgpu_gart *gtt, | |
668 | uint32_t gtt_flags, | |
669 | struct amdgpu_vm *vm, | |
670 | struct amdgpu_ib *ib, | |
671 | uint64_t start, uint64_t end, | |
672 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 673 | { |
31f6c1fe CK |
674 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
675 | ||
676 | uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0; | |
d38ceaf9 AD |
677 | uint64_t addr; |
678 | ||
679 | /* walk over the address space and update the page tables */ | |
680 | for (addr = start; addr < end; ) { | |
681 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | |
ee1782c3 | 682 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 | 683 | unsigned nptes; |
31f6c1fe | 684 | uint64_t pe_start; |
d38ceaf9 AD |
685 | |
686 | if ((addr & ~mask) == (end & ~mask)) | |
687 | nptes = end - addr; | |
688 | else | |
689 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
690 | ||
31f6c1fe CK |
691 | pe_start = amdgpu_bo_gpu_offset(pt); |
692 | pe_start += (addr & mask) * 8; | |
d38ceaf9 | 693 | |
31f6c1fe | 694 | if (last_pe_end != pe_start) { |
d38ceaf9 | 695 | |
31f6c1fe CK |
696 | amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib, |
697 | last_pe_start, last_pe_end, | |
698 | last_dst, flags); | |
d38ceaf9 | 699 | |
31f6c1fe CK |
700 | last_pe_start = pe_start; |
701 | last_pe_end = pe_start + 8 * nptes; | |
d38ceaf9 AD |
702 | last_dst = dst; |
703 | } else { | |
31f6c1fe | 704 | last_pe_end += 8 * nptes; |
d38ceaf9 AD |
705 | } |
706 | ||
707 | addr += nptes; | |
708 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
709 | } | |
710 | ||
31f6c1fe CK |
711 | amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib, |
712 | last_pe_start, last_pe_end, | |
713 | last_dst, flags); | |
d38ceaf9 AD |
714 | } |
715 | ||
d38ceaf9 AD |
716 | /** |
717 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
718 | * | |
719 | * @adev: amdgpu_device pointer | |
9ab21462 | 720 | * @gtt: GART instance to use for mapping |
a14faa65 | 721 | * @gtt_flags: flags as they are used for GTT |
d38ceaf9 | 722 | * @vm: requested vm |
a14faa65 CK |
723 | * @start: start of mapped range |
724 | * @last: last mapped entry | |
725 | * @flags: flags for the entries | |
d38ceaf9 | 726 | * @addr: addr to set the area to |
d38ceaf9 AD |
727 | * @fence: optional resulting fence |
728 | * | |
a14faa65 | 729 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 730 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
731 | */ |
732 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
9ab21462 CK |
733 | struct amdgpu_gart *gtt, |
734 | uint32_t gtt_flags, | |
d38ceaf9 | 735 | struct amdgpu_vm *vm, |
a14faa65 CK |
736 | uint64_t start, uint64_t last, |
737 | uint32_t flags, uint64_t addr, | |
738 | struct fence **fence) | |
d38ceaf9 | 739 | { |
2d55e45a | 740 | struct amdgpu_ring *ring; |
a1e08d3b | 741 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 742 | unsigned nptes, ncmds, ndw; |
d71518b5 | 743 | struct amdgpu_job *job; |
d5fc5e82 | 744 | struct amdgpu_ib *ib; |
4af9f07c | 745 | struct fence *f = NULL; |
d38ceaf9 AD |
746 | int r; |
747 | ||
2d55e45a CK |
748 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
749 | ||
a1e08d3b CK |
750 | /* sync to everything on unmapping */ |
751 | if (!(flags & AMDGPU_PTE_VALID)) | |
752 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
753 | ||
a14faa65 | 754 | nptes = last - start + 1; |
d38ceaf9 AD |
755 | |
756 | /* | |
757 | * reserve space for one command every (1 << BLOCK_SIZE) | |
758 | * entries or 2k dwords (whatever is smaller) | |
759 | */ | |
760 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
761 | ||
762 | /* padding, etc. */ | |
763 | ndw = 64; | |
764 | ||
9ab21462 | 765 | if ((gtt == &adev->gart) && (flags == gtt_flags)) { |
d38ceaf9 AD |
766 | /* only copy commands needed */ |
767 | ndw += ncmds * 7; | |
768 | ||
9ab21462 | 769 | } else if (gtt) { |
d38ceaf9 AD |
770 | /* header for write data commands */ |
771 | ndw += ncmds * 4; | |
772 | ||
773 | /* body of write data command */ | |
774 | ndw += nptes * 2; | |
775 | ||
776 | } else { | |
777 | /* set page commands needed */ | |
778 | ndw += ncmds * 10; | |
779 | ||
780 | /* two extra commands for begin/end of fragment */ | |
781 | ndw += 2 * 10; | |
782 | } | |
783 | ||
d71518b5 CK |
784 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
785 | if (r) | |
d38ceaf9 | 786 | return r; |
d71518b5 CK |
787 | |
788 | ib = &job->ibs[0]; | |
d5fc5e82 | 789 | |
e86f9cee | 790 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
791 | owner); |
792 | if (r) | |
793 | goto error_free; | |
d38ceaf9 | 794 | |
a1e08d3b CK |
795 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
796 | if (r) | |
797 | goto error_free; | |
798 | ||
799 | amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start, last + 1, | |
800 | addr, flags); | |
d38ceaf9 | 801 | |
9e5d5309 | 802 | amdgpu_ring_pad_ib(ring, ib); |
d5fc5e82 | 803 | WARN_ON(ib->length_dw > ndw); |
2bd9ccfa CK |
804 | r = amdgpu_job_submit(job, ring, &vm->entity, |
805 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
806 | if (r) |
807 | goto error_free; | |
d38ceaf9 | 808 | |
bf60efd3 | 809 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
810 | if (fence) { |
811 | fence_put(*fence); | |
812 | *fence = fence_get(f); | |
813 | } | |
281b4223 | 814 | fence_put(f); |
d38ceaf9 | 815 | return 0; |
d5fc5e82 CZ |
816 | |
817 | error_free: | |
d71518b5 | 818 | amdgpu_job_free(job); |
4af9f07c | 819 | return r; |
d38ceaf9 AD |
820 | } |
821 | ||
a14faa65 CK |
822 | /** |
823 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
824 | * | |
825 | * @adev: amdgpu_device pointer | |
826 | * @gtt: GART instance to use for mapping | |
827 | * @vm: requested vm | |
828 | * @mapping: mapped range and flags to use for the update | |
829 | * @addr: addr to set the area to | |
830 | * @gtt_flags: flags as they are used for GTT | |
831 | * @fence: optional resulting fence | |
832 | * | |
833 | * Split the mapping into smaller chunks so that each update fits | |
834 | * into a SDMA IB. | |
835 | * Returns 0 for success, -EINVAL for failure. | |
836 | */ | |
837 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
838 | struct amdgpu_gart *gtt, | |
839 | uint32_t gtt_flags, | |
840 | struct amdgpu_vm *vm, | |
841 | struct amdgpu_bo_va_mapping *mapping, | |
842 | uint64_t addr, struct fence **fence) | |
843 | { | |
844 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
845 | ||
846 | uint64_t start = mapping->it.start; | |
847 | uint32_t flags = gtt_flags; | |
848 | int r; | |
849 | ||
850 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
851 | * but in case of something, we filter the flags in first place | |
852 | */ | |
853 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
854 | flags &= ~AMDGPU_PTE_READABLE; | |
855 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
856 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
857 | ||
858 | trace_amdgpu_vm_bo_update(mapping); | |
859 | ||
860 | addr += mapping->offset; | |
861 | ||
862 | if (!gtt || ((gtt == &adev->gart) && (flags == gtt_flags))) | |
863 | return amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm, | |
864 | start, mapping->it.last, | |
865 | flags, addr, fence); | |
866 | ||
867 | while (start != mapping->it.last + 1) { | |
868 | uint64_t last; | |
869 | ||
fb29b57c | 870 | last = min((uint64_t)mapping->it.last, start + max_size - 1); |
a14faa65 CK |
871 | r = amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm, |
872 | start, last, flags, addr, | |
873 | fence); | |
874 | if (r) | |
875 | return r; | |
876 | ||
877 | start = last + 1; | |
fb29b57c | 878 | addr += max_size * AMDGPU_GPU_PAGE_SIZE; |
a14faa65 CK |
879 | } |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
d38ceaf9 AD |
884 | /** |
885 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
886 | * | |
887 | * @adev: amdgpu_device pointer | |
888 | * @bo_va: requested BO and VM object | |
889 | * @mem: ttm mem | |
890 | * | |
891 | * Fill in the page table entries for @bo_va. | |
892 | * Returns 0 for success, -EINVAL for failure. | |
893 | * | |
894 | * Object have to be reserved and mutex must be locked! | |
895 | */ | |
896 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
897 | struct amdgpu_bo_va *bo_va, | |
898 | struct ttm_mem_reg *mem) | |
899 | { | |
900 | struct amdgpu_vm *vm = bo_va->vm; | |
901 | struct amdgpu_bo_va_mapping *mapping; | |
9ab21462 | 902 | struct amdgpu_gart *gtt = NULL; |
d38ceaf9 AD |
903 | uint32_t flags; |
904 | uint64_t addr; | |
905 | int r; | |
906 | ||
907 | if (mem) { | |
b7d698d7 | 908 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
909 | switch (mem->mem_type) { |
910 | case TTM_PL_TT: | |
911 | gtt = &bo_va->bo->adev->gart; | |
912 | break; | |
913 | ||
914 | case TTM_PL_VRAM: | |
d38ceaf9 | 915 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
916 | break; |
917 | ||
918 | default: | |
919 | break; | |
920 | } | |
d38ceaf9 AD |
921 | } else { |
922 | addr = 0; | |
923 | } | |
924 | ||
d38ceaf9 AD |
925 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
926 | ||
7fc11959 CK |
927 | spin_lock(&vm->status_lock); |
928 | if (!list_empty(&bo_va->vm_status)) | |
929 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
930 | spin_unlock(&vm->status_lock); | |
931 | ||
932 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a14faa65 CK |
933 | r = amdgpu_vm_bo_split_mapping(adev, gtt, flags, vm, mapping, addr, |
934 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
935 | if (r) |
936 | return r; | |
937 | } | |
938 | ||
d6c10f6b CK |
939 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
940 | list_for_each_entry(mapping, &bo_va->valids, list) | |
941 | trace_amdgpu_vm_bo_mapping(mapping); | |
942 | ||
943 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
944 | trace_amdgpu_vm_bo_mapping(mapping); | |
945 | } | |
946 | ||
d38ceaf9 | 947 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 948 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 949 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
950 | if (!mem) |
951 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
952 | spin_unlock(&vm->status_lock); |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
957 | /** | |
958 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
959 | * | |
960 | * @adev: amdgpu_device pointer | |
961 | * @vm: requested vm | |
962 | * | |
963 | * Make sure all freed BOs are cleared in the PT. | |
964 | * Returns 0 for success. | |
965 | * | |
966 | * PTs have to be reserved and mutex must be locked! | |
967 | */ | |
968 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
969 | struct amdgpu_vm *vm) | |
970 | { | |
971 | struct amdgpu_bo_va_mapping *mapping; | |
972 | int r; | |
973 | ||
974 | while (!list_empty(&vm->freed)) { | |
975 | mapping = list_first_entry(&vm->freed, | |
976 | struct amdgpu_bo_va_mapping, list); | |
977 | list_del(&mapping->list); | |
e17841b9 | 978 | |
a14faa65 CK |
979 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, vm, mapping, |
980 | 0, NULL); | |
d38ceaf9 AD |
981 | kfree(mapping); |
982 | if (r) | |
983 | return r; | |
984 | ||
985 | } | |
986 | return 0; | |
987 | ||
988 | } | |
989 | ||
990 | /** | |
991 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
992 | * | |
993 | * @adev: amdgpu_device pointer | |
994 | * @vm: requested vm | |
995 | * | |
996 | * Make sure all invalidated BOs are cleared in the PT. | |
997 | * Returns 0 for success. | |
998 | * | |
999 | * PTs have to be reserved and mutex must be locked! | |
1000 | */ | |
1001 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1002 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1003 | { |
cfe2c978 | 1004 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1005 | int r = 0; |
d38ceaf9 AD |
1006 | |
1007 | spin_lock(&vm->status_lock); | |
1008 | while (!list_empty(&vm->invalidated)) { | |
1009 | bo_va = list_first_entry(&vm->invalidated, | |
1010 | struct amdgpu_bo_va, vm_status); | |
1011 | spin_unlock(&vm->status_lock); | |
69b576a1 | 1012 | mutex_lock(&bo_va->mutex); |
d38ceaf9 | 1013 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
69b576a1 | 1014 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 AD |
1015 | if (r) |
1016 | return r; | |
1017 | ||
1018 | spin_lock(&vm->status_lock); | |
1019 | } | |
1020 | spin_unlock(&vm->status_lock); | |
1021 | ||
cfe2c978 | 1022 | if (bo_va) |
bb1e38a4 | 1023 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1024 | |
1025 | return r; | |
d38ceaf9 AD |
1026 | } |
1027 | ||
1028 | /** | |
1029 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1030 | * | |
1031 | * @adev: amdgpu_device pointer | |
1032 | * @vm: requested vm | |
1033 | * @bo: amdgpu buffer object | |
1034 | * | |
8843dbbb | 1035 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1036 | * Add @bo to the list of bos associated with the vm |
1037 | * Returns newly added bo_va or NULL for failure | |
1038 | * | |
1039 | * Object has to be reserved! | |
1040 | */ | |
1041 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1042 | struct amdgpu_vm *vm, | |
1043 | struct amdgpu_bo *bo) | |
1044 | { | |
1045 | struct amdgpu_bo_va *bo_va; | |
1046 | ||
1047 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1048 | if (bo_va == NULL) { | |
1049 | return NULL; | |
1050 | } | |
1051 | bo_va->vm = vm; | |
1052 | bo_va->bo = bo; | |
d38ceaf9 AD |
1053 | bo_va->ref_count = 1; |
1054 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1055 | INIT_LIST_HEAD(&bo_va->valids); |
1056 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1057 | INIT_LIST_HEAD(&bo_va->vm_status); |
69b576a1 | 1058 | mutex_init(&bo_va->mutex); |
d38ceaf9 | 1059 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1060 | |
1061 | return bo_va; | |
1062 | } | |
1063 | ||
1064 | /** | |
1065 | * amdgpu_vm_bo_map - map bo inside a vm | |
1066 | * | |
1067 | * @adev: amdgpu_device pointer | |
1068 | * @bo_va: bo_va to store the address | |
1069 | * @saddr: where to map the BO | |
1070 | * @offset: requested offset in the BO | |
1071 | * @flags: attributes of pages (read/write/valid/etc.) | |
1072 | * | |
1073 | * Add a mapping of the BO at the specefied addr into the VM. | |
1074 | * Returns 0 for success, error for failure. | |
1075 | * | |
49b02b18 | 1076 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1077 | */ |
1078 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1079 | struct amdgpu_bo_va *bo_va, | |
1080 | uint64_t saddr, uint64_t offset, | |
1081 | uint64_t size, uint32_t flags) | |
1082 | { | |
1083 | struct amdgpu_bo_va_mapping *mapping; | |
1084 | struct amdgpu_vm *vm = bo_va->vm; | |
1085 | struct interval_tree_node *it; | |
1086 | unsigned last_pfn, pt_idx; | |
1087 | uint64_t eaddr; | |
1088 | int r; | |
1089 | ||
0be52de9 CK |
1090 | /* validate the parameters */ |
1091 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1092 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1093 | return -EINVAL; |
0be52de9 | 1094 | |
d38ceaf9 | 1095 | /* make sure object fit at this offset */ |
005ae95e | 1096 | eaddr = saddr + size - 1; |
49b02b18 | 1097 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1098 | return -EINVAL; |
d38ceaf9 AD |
1099 | |
1100 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1101 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1102 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1103 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1104 | return -EINVAL; |
1105 | } | |
1106 | ||
d38ceaf9 AD |
1107 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1108 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1109 | ||
c25867df | 1110 | spin_lock(&vm->it_lock); |
005ae95e | 1111 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
c25867df | 1112 | spin_unlock(&vm->it_lock); |
d38ceaf9 AD |
1113 | if (it) { |
1114 | struct amdgpu_bo_va_mapping *tmp; | |
1115 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1116 | /* bo and tmp overlap, invalid addr */ | |
1117 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1118 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1119 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1120 | r = -EINVAL; |
f48b2659 | 1121 | goto error; |
d38ceaf9 AD |
1122 | } |
1123 | ||
1124 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1125 | if (!mapping) { | |
d38ceaf9 | 1126 | r = -ENOMEM; |
f48b2659 | 1127 | goto error; |
d38ceaf9 AD |
1128 | } |
1129 | ||
1130 | INIT_LIST_HEAD(&mapping->list); | |
1131 | mapping->it.start = saddr; | |
005ae95e | 1132 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1133 | mapping->offset = offset; |
1134 | mapping->flags = flags; | |
1135 | ||
69b576a1 | 1136 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1137 | list_add(&mapping->list, &bo_va->invalids); |
69b576a1 | 1138 | mutex_unlock(&bo_va->mutex); |
c25867df | 1139 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1140 | interval_tree_insert(&mapping->it, &vm->va); |
c25867df | 1141 | spin_unlock(&vm->it_lock); |
93e3e438 | 1142 | trace_amdgpu_vm_bo_map(bo_va, mapping); |
d38ceaf9 AD |
1143 | |
1144 | /* Make sure the page tables are allocated */ | |
1145 | saddr >>= amdgpu_vm_block_size; | |
1146 | eaddr >>= amdgpu_vm_block_size; | |
1147 | ||
1148 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1149 | ||
1150 | if (eaddr > vm->max_pde_used) | |
1151 | vm->max_pde_used = eaddr; | |
1152 | ||
d38ceaf9 AD |
1153 | /* walk over the address space and allocate the page tables */ |
1154 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1155 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1156 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1157 | struct amdgpu_bo *pt; |
1158 | ||
ee1782c3 CK |
1159 | entry = &vm->page_tables[pt_idx].entry; |
1160 | if (entry->robj) | |
d38ceaf9 AD |
1161 | continue; |
1162 | ||
d38ceaf9 AD |
1163 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1164 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1165 | AMDGPU_GEM_DOMAIN_VRAM, |
1166 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 | 1167 | NULL, resv, &pt); |
49b02b18 | 1168 | if (r) |
d38ceaf9 | 1169 | goto error_free; |
49b02b18 | 1170 | |
82b9c55b CK |
1171 | /* Keep a reference to the page table to avoid freeing |
1172 | * them up in the wrong order. | |
1173 | */ | |
1174 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1175 | ||
2bd9ccfa | 1176 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 AD |
1177 | if (r) { |
1178 | amdgpu_bo_unref(&pt); | |
1179 | goto error_free; | |
1180 | } | |
1181 | ||
ee1782c3 | 1182 | entry->robj = pt; |
ee1782c3 CK |
1183 | entry->priority = 0; |
1184 | entry->tv.bo = &entry->robj->tbo; | |
1185 | entry->tv.shared = true; | |
2f568dbd | 1186 | entry->user_pages = NULL; |
d38ceaf9 | 1187 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1188 | } |
1189 | ||
d38ceaf9 AD |
1190 | return 0; |
1191 | ||
1192 | error_free: | |
d38ceaf9 | 1193 | list_del(&mapping->list); |
c25867df | 1194 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1195 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1196 | spin_unlock(&vm->it_lock); |
93e3e438 | 1197 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1198 | kfree(mapping); |
1199 | ||
f48b2659 | 1200 | error: |
d38ceaf9 AD |
1201 | return r; |
1202 | } | |
1203 | ||
1204 | /** | |
1205 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1206 | * | |
1207 | * @adev: amdgpu_device pointer | |
1208 | * @bo_va: bo_va to remove the address from | |
1209 | * @saddr: where to the BO is mapped | |
1210 | * | |
1211 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1212 | * Returns 0 for success, error for failure. | |
1213 | * | |
49b02b18 | 1214 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1215 | */ |
1216 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1217 | struct amdgpu_bo_va *bo_va, | |
1218 | uint64_t saddr) | |
1219 | { | |
1220 | struct amdgpu_bo_va_mapping *mapping; | |
1221 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1222 | bool valid = true; |
d38ceaf9 | 1223 | |
6c7fc503 | 1224 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
69b576a1 | 1225 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1226 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1227 | if (mapping->it.start == saddr) |
1228 | break; | |
1229 | } | |
1230 | ||
7fc11959 CK |
1231 | if (&mapping->list == &bo_va->valids) { |
1232 | valid = false; | |
1233 | ||
1234 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1235 | if (mapping->it.start == saddr) | |
1236 | break; | |
1237 | } | |
1238 | ||
69b576a1 CZ |
1239 | if (&mapping->list == &bo_va->invalids) { |
1240 | mutex_unlock(&bo_va->mutex); | |
7fc11959 | 1241 | return -ENOENT; |
69b576a1 | 1242 | } |
d38ceaf9 | 1243 | } |
69b576a1 | 1244 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 | 1245 | list_del(&mapping->list); |
c25867df | 1246 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1247 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1248 | spin_unlock(&vm->it_lock); |
93e3e438 | 1249 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1250 | |
e17841b9 | 1251 | if (valid) |
d38ceaf9 | 1252 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1253 | else |
d38ceaf9 | 1254 | kfree(mapping); |
d38ceaf9 AD |
1255 | |
1256 | return 0; | |
1257 | } | |
1258 | ||
1259 | /** | |
1260 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1261 | * | |
1262 | * @adev: amdgpu_device pointer | |
1263 | * @bo_va: requested bo_va | |
1264 | * | |
8843dbbb | 1265 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1266 | * |
1267 | * Object have to be reserved! | |
1268 | */ | |
1269 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1270 | struct amdgpu_bo_va *bo_va) | |
1271 | { | |
1272 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1273 | struct amdgpu_vm *vm = bo_va->vm; | |
1274 | ||
1275 | list_del(&bo_va->bo_list); | |
1276 | ||
d38ceaf9 AD |
1277 | spin_lock(&vm->status_lock); |
1278 | list_del(&bo_va->vm_status); | |
1279 | spin_unlock(&vm->status_lock); | |
1280 | ||
7fc11959 | 1281 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 1282 | list_del(&mapping->list); |
c25867df | 1283 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1284 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1285 | spin_unlock(&vm->it_lock); |
93e3e438 | 1286 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1287 | list_add(&mapping->list, &vm->freed); |
1288 | } | |
1289 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1290 | list_del(&mapping->list); | |
c25867df | 1291 | spin_lock(&vm->it_lock); |
7fc11959 | 1292 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1293 | spin_unlock(&vm->it_lock); |
7fc11959 | 1294 | kfree(mapping); |
d38ceaf9 | 1295 | } |
bb1e38a4 | 1296 | fence_put(bo_va->last_pt_update); |
69b576a1 | 1297 | mutex_destroy(&bo_va->mutex); |
d38ceaf9 | 1298 | kfree(bo_va); |
d38ceaf9 AD |
1299 | } |
1300 | ||
1301 | /** | |
1302 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1303 | * | |
1304 | * @adev: amdgpu_device pointer | |
1305 | * @vm: requested vm | |
1306 | * @bo: amdgpu buffer object | |
1307 | * | |
8843dbbb | 1308 | * Mark @bo as invalid. |
d38ceaf9 AD |
1309 | */ |
1310 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1311 | struct amdgpu_bo *bo) | |
1312 | { | |
1313 | struct amdgpu_bo_va *bo_va; | |
1314 | ||
1315 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1316 | spin_lock(&bo_va->vm->status_lock); |
1317 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1318 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1319 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1320 | } |
1321 | } | |
1322 | ||
1323 | /** | |
1324 | * amdgpu_vm_init - initialize a vm instance | |
1325 | * | |
1326 | * @adev: amdgpu_device pointer | |
1327 | * @vm: requested vm | |
1328 | * | |
8843dbbb | 1329 | * Init @vm fields. |
d38ceaf9 AD |
1330 | */ |
1331 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1332 | { | |
1333 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1334 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1335 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1336 | unsigned ring_instance; |
1337 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1338 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1339 | int i, r; |
1340 | ||
1341 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4ff37a83 | 1342 | vm->ids[i].mgr_id = NULL; |
d38ceaf9 | 1343 | vm->ids[i].flushed_updates = NULL; |
d38ceaf9 | 1344 | } |
d38ceaf9 AD |
1345 | vm->va = RB_ROOT; |
1346 | spin_lock_init(&vm->status_lock); | |
1347 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1348 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1349 | INIT_LIST_HEAD(&vm->freed); |
c25867df | 1350 | spin_lock_init(&vm->it_lock); |
d38ceaf9 AD |
1351 | pd_size = amdgpu_vm_directory_size(adev); |
1352 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1353 | ||
1354 | /* allocate page table array */ | |
9571e1d8 | 1355 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1356 | if (vm->page_tables == NULL) { |
1357 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1358 | return -ENOMEM; | |
1359 | } | |
1360 | ||
2bd9ccfa | 1361 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1362 | |
1363 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1364 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1365 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1366 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1367 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1368 | rq, amdgpu_sched_jobs); | |
1369 | if (r) | |
1370 | return r; | |
1371 | ||
05906dec BN |
1372 | vm->page_directory_fence = NULL; |
1373 | ||
d38ceaf9 | 1374 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1375 | AMDGPU_GEM_DOMAIN_VRAM, |
1376 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1377 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1378 | if (r) |
2bd9ccfa CK |
1379 | goto error_free_sched_entity; |
1380 | ||
ef9f0a83 | 1381 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1382 | if (r) |
1383 | goto error_free_page_directory; | |
1384 | ||
1385 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
ef9f0a83 | 1386 | amdgpu_bo_unreserve(vm->page_directory); |
2bd9ccfa CK |
1387 | if (r) |
1388 | goto error_free_page_directory; | |
d38ceaf9 AD |
1389 | |
1390 | return 0; | |
2bd9ccfa CK |
1391 | |
1392 | error_free_page_directory: | |
1393 | amdgpu_bo_unref(&vm->page_directory); | |
1394 | vm->page_directory = NULL; | |
1395 | ||
1396 | error_free_sched_entity: | |
1397 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1398 | ||
1399 | return r; | |
d38ceaf9 AD |
1400 | } |
1401 | ||
1402 | /** | |
1403 | * amdgpu_vm_fini - tear down a vm instance | |
1404 | * | |
1405 | * @adev: amdgpu_device pointer | |
1406 | * @vm: requested vm | |
1407 | * | |
8843dbbb | 1408 | * Tear down @vm. |
d38ceaf9 AD |
1409 | * Unbind the VM and remove all bos from the vm bo list |
1410 | */ | |
1411 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1412 | { | |
1413 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1414 | int i; | |
1415 | ||
2d55e45a | 1416 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1417 | |
d38ceaf9 AD |
1418 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1419 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1420 | } | |
1421 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1422 | list_del(&mapping->list); | |
1423 | interval_tree_remove(&mapping->it, &vm->va); | |
1424 | kfree(mapping); | |
1425 | } | |
1426 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1427 | list_del(&mapping->list); | |
1428 | kfree(mapping); | |
1429 | } | |
1430 | ||
1431 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
ee1782c3 | 1432 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
9571e1d8 | 1433 | drm_free_large(vm->page_tables); |
d38ceaf9 AD |
1434 | |
1435 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1436 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1437 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4ff37a83 | 1438 | struct amdgpu_vm_id *id = &vm->ids[i]; |
1c16c0a7 | 1439 | |
4ff37a83 CK |
1440 | if (id->mgr_id) |
1441 | atomic_long_cmpxchg(&id->mgr_id->owner, | |
1442 | (long)id, 0); | |
1443 | fence_put(id->flushed_updates); | |
d38ceaf9 | 1444 | } |
d38ceaf9 | 1445 | } |
ea89f8c9 | 1446 | |
a9a78b32 CK |
1447 | /** |
1448 | * amdgpu_vm_manager_init - init the VM manager | |
1449 | * | |
1450 | * @adev: amdgpu_device pointer | |
1451 | * | |
1452 | * Initialize the VM manager structures | |
1453 | */ | |
1454 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1455 | { | |
1456 | unsigned i; | |
1457 | ||
1458 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1459 | ||
1460 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1461 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1462 | amdgpu_vm_reset_id(adev, i); | |
a9a78b32 CK |
1463 | list_add_tail(&adev->vm_manager.ids[i].list, |
1464 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1465 | } |
2d55e45a CK |
1466 | |
1467 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); | |
a9a78b32 CK |
1468 | } |
1469 | ||
ea89f8c9 CK |
1470 | /** |
1471 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1472 | * | |
1473 | * @adev: amdgpu_device pointer | |
1474 | * | |
1475 | * Cleanup the VM manager and free resources. | |
1476 | */ | |
1477 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1478 | { | |
1479 | unsigned i; | |
1480 | ||
1481 | for (i = 0; i < AMDGPU_NUM_VM; ++i) | |
1c16c0a7 | 1482 | fence_put(adev->vm_manager.ids[i].active); |
ea89f8c9 | 1483 | } |