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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
02208441 | 30 | #include <linux/idr.h> |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "amdgpu_trace.h" | |
35 | ||
36 | /* | |
37 | * GPUVM | |
38 | * GPUVM is similar to the legacy gart on older asics, however | |
39 | * rather than there being a single global gart table | |
40 | * for the entire GPU, there are multiple VM page tables active | |
41 | * at any given time. The VM page tables can contain a mix | |
42 | * vram pages and system memory pages and system memory pages | |
43 | * can be mapped as snooped (cached system pages) or unsnooped | |
44 | * (uncached system pages). | |
45 | * Each VM has an ID associated with it and there is a page table | |
46 | * associated with each VMID. When execting a command buffer, | |
47 | * the kernel tells the the ring what VMID to use for that command | |
48 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
49 | * The userspace drivers maintain their own address space and the kernel | |
50 | * sets up their pages tables accordingly when they submit their | |
51 | * command buffers and a VMID is assigned. | |
52 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
53 | * SI supports 16. | |
54 | */ | |
55 | ||
a9f87f64 CK |
56 | #define START(node) ((node)->start) |
57 | #define LAST(node) ((node)->last) | |
58 | ||
59 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
60 | START, LAST, static, amdgpu_vm_it) | |
61 | ||
62 | #undef START | |
63 | #undef LAST | |
64 | ||
f4833c4f HK |
65 | /* Local structure. Encapsulate some VM table update parameters to reduce |
66 | * the number of function parameters | |
67 | */ | |
29efc4f5 | 68 | struct amdgpu_pte_update_params { |
27c5f36f CK |
69 | /* amdgpu device we do this update for */ |
70 | struct amdgpu_device *adev; | |
49ac8a24 CK |
71 | /* optional amdgpu_vm we do this update for */ |
72 | struct amdgpu_vm *vm; | |
f4833c4f HK |
73 | /* address where to copy page table entries from */ |
74 | uint64_t src; | |
f4833c4f HK |
75 | /* indirect buffer to fill with commands */ |
76 | struct amdgpu_ib *ib; | |
afef8b8f | 77 | /* Function which actually does the update */ |
373ac645 CK |
78 | void (*func)(struct amdgpu_pte_update_params *params, |
79 | struct amdgpu_bo *bo, uint64_t pe, | |
afef8b8f | 80 | uint64_t addr, unsigned count, uint32_t incr, |
6b777607 | 81 | uint64_t flags); |
b4d42511 HK |
82 | /* The next two are used during VM update by CPU |
83 | * DMA addresses to use for mapping | |
84 | * Kernel pointer of PD/PT BO that needs to be updated | |
85 | */ | |
86 | dma_addr_t *pages_addr; | |
87 | void *kptr; | |
f4833c4f HK |
88 | }; |
89 | ||
284710fa CK |
90 | /* Helper to disable partial resident texture feature from a fence callback */ |
91 | struct amdgpu_prt_cb { | |
92 | struct amdgpu_device *adev; | |
93 | struct dma_fence_cb cb; | |
94 | }; | |
95 | ||
50783147 CK |
96 | /** |
97 | * amdgpu_vm_level_shift - return the addr shift for each level | |
98 | * | |
99 | * @adev: amdgpu_device pointer | |
100 | * | |
101 | * Returns the number of bits the pfn needs to be right shifted for a level. | |
102 | */ | |
103 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
104 | unsigned level) | |
105 | { | |
196f7489 CZ |
106 | unsigned shift = 0xff; |
107 | ||
108 | switch (level) { | |
109 | case AMDGPU_VM_PDB2: | |
110 | case AMDGPU_VM_PDB1: | |
111 | case AMDGPU_VM_PDB0: | |
112 | shift = 9 * (AMDGPU_VM_PDB0 - level) + | |
50783147 | 113 | adev->vm_manager.block_size; |
196f7489 CZ |
114 | break; |
115 | case AMDGPU_VM_PTB: | |
116 | shift = 0; | |
117 | break; | |
118 | default: | |
119 | dev_err(adev->dev, "the level%d isn't supported.\n", level); | |
120 | } | |
121 | ||
122 | return shift; | |
50783147 CK |
123 | } |
124 | ||
d38ceaf9 | 125 | /** |
72a7ec5c | 126 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
127 | * |
128 | * @adev: amdgpu_device pointer | |
129 | * | |
72a7ec5c | 130 | * Calculate the number of entries in a page directory or page table. |
d38ceaf9 | 131 | */ |
72a7ec5c CK |
132 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
133 | unsigned level) | |
d38ceaf9 | 134 | { |
196f7489 CZ |
135 | unsigned shift = amdgpu_vm_level_shift(adev, |
136 | adev->vm_manager.root_level); | |
0410c5e5 | 137 | |
196f7489 | 138 | if (level == adev->vm_manager.root_level) |
72a7ec5c | 139 | /* For the root directory */ |
0410c5e5 | 140 | return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; |
196f7489 | 141 | else if (level != AMDGPU_VM_PTB) |
0410c5e5 CK |
142 | /* Everything in between */ |
143 | return 512; | |
144 | else | |
72a7ec5c | 145 | /* For the page tables on the leaves */ |
36b32a68 | 146 | return AMDGPU_VM_PTE_COUNT(adev); |
d38ceaf9 AD |
147 | } |
148 | ||
149 | /** | |
72a7ec5c | 150 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
151 | * |
152 | * @adev: amdgpu_device pointer | |
153 | * | |
72a7ec5c | 154 | * Calculate the size of the BO for a page directory or page table in bytes. |
d38ceaf9 | 155 | */ |
72a7ec5c | 156 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 157 | { |
72a7ec5c | 158 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
159 | } |
160 | ||
161 | /** | |
56467ebf | 162 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
163 | * |
164 | * @vm: vm providing the BOs | |
3c0eea6c | 165 | * @validated: head of validation list |
56467ebf | 166 | * @entry: entry to add |
d38ceaf9 AD |
167 | * |
168 | * Add the page directory to the list of BOs to | |
56467ebf | 169 | * validate for command submission. |
d38ceaf9 | 170 | */ |
56467ebf CK |
171 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
172 | struct list_head *validated, | |
173 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 174 | { |
3f3333f8 | 175 | entry->robj = vm->root.base.bo; |
56467ebf | 176 | entry->priority = 0; |
67003a15 | 177 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 178 | entry->tv.shared = true; |
2f568dbd | 179 | entry->user_pages = NULL; |
56467ebf CK |
180 | list_add(&entry->tv.head, validated); |
181 | } | |
d38ceaf9 | 182 | |
670fecc8 | 183 | /** |
f7da30d9 | 184 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
670fecc8 | 185 | * |
5a712a87 | 186 | * @adev: amdgpu device pointer |
56467ebf | 187 | * @vm: vm providing the BOs |
670fecc8 CK |
188 | * @validate: callback to do the validation |
189 | * @param: parameter for the validation callback | |
190 | * | |
191 | * Validate the page table BOs on command submission if neccessary. | |
192 | */ | |
f7da30d9 CK |
193 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
194 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
195 | void *param) | |
670fecc8 | 196 | { |
3f3333f8 | 197 | struct ttm_bo_global *glob = adev->mman.bdev.glob; |
670fecc8 CK |
198 | int r; |
199 | ||
3f3333f8 CK |
200 | spin_lock(&vm->status_lock); |
201 | while (!list_empty(&vm->evicted)) { | |
202 | struct amdgpu_vm_bo_base *bo_base; | |
203 | struct amdgpu_bo *bo; | |
670fecc8 | 204 | |
3f3333f8 CK |
205 | bo_base = list_first_entry(&vm->evicted, |
206 | struct amdgpu_vm_bo_base, | |
207 | vm_status); | |
208 | spin_unlock(&vm->status_lock); | |
670fecc8 | 209 | |
3f3333f8 CK |
210 | bo = bo_base->bo; |
211 | BUG_ON(!bo); | |
212 | if (bo->parent) { | |
213 | r = validate(param, bo); | |
214 | if (r) | |
215 | return r; | |
670fecc8 | 216 | |
3f3333f8 CK |
217 | spin_lock(&glob->lru_lock); |
218 | ttm_bo_move_to_lru_tail(&bo->tbo); | |
219 | if (bo->shadow) | |
220 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo); | |
221 | spin_unlock(&glob->lru_lock); | |
222 | } | |
670fecc8 | 223 | |
73fb16e7 CK |
224 | if (bo->tbo.type == ttm_bo_type_kernel && |
225 | vm->use_cpu_for_update) { | |
3f3333f8 CK |
226 | r = amdgpu_bo_kmap(bo, NULL); |
227 | if (r) | |
228 | return r; | |
229 | } | |
b6369225 | 230 | |
3f3333f8 | 231 | spin_lock(&vm->status_lock); |
73fb16e7 CK |
232 | if (bo->tbo.type != ttm_bo_type_kernel) |
233 | list_move(&bo_base->vm_status, &vm->moved); | |
234 | else | |
235 | list_move(&bo_base->vm_status, &vm->relocated); | |
670fecc8 | 236 | } |
3f3333f8 | 237 | spin_unlock(&vm->status_lock); |
670fecc8 | 238 | |
34d7be5d | 239 | return 0; |
670fecc8 CK |
240 | } |
241 | ||
56467ebf | 242 | /** |
34d7be5d | 243 | * amdgpu_vm_ready - check VM is ready for updates |
56467ebf | 244 | * |
34d7be5d | 245 | * @vm: VM to check |
d38ceaf9 | 246 | * |
34d7be5d | 247 | * Check if all VM PDs/PTs are ready for updates |
d38ceaf9 | 248 | */ |
3f3333f8 | 249 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
d38ceaf9 | 250 | { |
3f3333f8 | 251 | bool ready; |
d38ceaf9 | 252 | |
3f3333f8 CK |
253 | spin_lock(&vm->status_lock); |
254 | ready = list_empty(&vm->evicted); | |
255 | spin_unlock(&vm->status_lock); | |
5a712a87 | 256 | |
3f3333f8 | 257 | return ready; |
d711e139 CK |
258 | } |
259 | ||
13307f7e CK |
260 | /** |
261 | * amdgpu_vm_clear_bo - initially clear the PDs/PTs | |
262 | * | |
263 | * @adev: amdgpu_device pointer | |
264 | * @bo: BO to clear | |
265 | * @level: level this BO is at | |
266 | * | |
267 | * Root PD needs to be reserved when calling this. | |
268 | */ | |
269 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
4584312d CK |
270 | struct amdgpu_vm *vm, struct amdgpu_bo *bo, |
271 | unsigned level, bool pte_support_ats) | |
13307f7e CK |
272 | { |
273 | struct ttm_operation_ctx ctx = { true, false }; | |
274 | struct dma_fence *fence = NULL; | |
4584312d | 275 | unsigned entries, ats_entries; |
13307f7e CK |
276 | struct amdgpu_ring *ring; |
277 | struct amdgpu_job *job; | |
4584312d | 278 | uint64_t addr; |
13307f7e CK |
279 | int r; |
280 | ||
4584312d CK |
281 | addr = amdgpu_bo_gpu_offset(bo); |
282 | entries = amdgpu_bo_size(bo) / 8; | |
283 | ||
284 | if (pte_support_ats) { | |
285 | if (level == adev->vm_manager.root_level) { | |
286 | ats_entries = amdgpu_vm_level_shift(adev, level); | |
287 | ats_entries += AMDGPU_GPU_PAGE_SHIFT; | |
288 | ats_entries = AMDGPU_VA_HOLE_START >> ats_entries; | |
289 | ats_entries = min(ats_entries, entries); | |
290 | entries -= ats_entries; | |
291 | } else { | |
292 | ats_entries = entries; | |
293 | entries = 0; | |
294 | } | |
13307f7e | 295 | } else { |
4584312d | 296 | ats_entries = 0; |
13307f7e CK |
297 | } |
298 | ||
299 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); | |
300 | ||
301 | r = reservation_object_reserve_shared(bo->tbo.resv); | |
302 | if (r) | |
303 | return r; | |
304 | ||
305 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | |
306 | if (r) | |
307 | goto error; | |
308 | ||
13307f7e CK |
309 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
310 | if (r) | |
311 | goto error; | |
312 | ||
4584312d CK |
313 | if (ats_entries) { |
314 | uint64_t ats_value; | |
315 | ||
316 | ats_value = AMDGPU_PTE_DEFAULT_ATC; | |
317 | if (level != AMDGPU_VM_PTB) | |
318 | ats_value |= AMDGPU_PDE_PTE; | |
319 | ||
320 | amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, | |
321 | ats_entries, 0, ats_value); | |
322 | addr += ats_entries * 8; | |
323 | } | |
324 | ||
325 | if (entries) | |
326 | amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, | |
327 | entries, 0, 0); | |
328 | ||
13307f7e CK |
329 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
330 | ||
331 | WARN_ON(job->ibs[0].length_dw > 64); | |
332 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
333 | AMDGPU_FENCE_OWNER_UNDEFINED, &fence); | |
334 | if (r) | |
335 | goto error_free; | |
336 | ||
337 | amdgpu_bo_fence(bo, fence, true); | |
338 | dma_fence_put(fence); | |
339 | return 0; | |
340 | ||
341 | error_free: | |
342 | amdgpu_job_free(job); | |
343 | ||
344 | error: | |
345 | return r; | |
346 | } | |
347 | ||
d711e139 | 348 | /** |
f566ceb1 CK |
349 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels |
350 | * | |
351 | * @adev: amdgpu_device pointer | |
352 | * @vm: requested vm | |
353 | * @saddr: start of the address range | |
354 | * @eaddr: end of the address range | |
355 | * | |
356 | * Make sure the page directories and page tables are allocated | |
357 | */ | |
358 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
359 | struct amdgpu_vm *vm, | |
360 | struct amdgpu_vm_pt *parent, | |
361 | uint64_t saddr, uint64_t eaddr, | |
4584312d | 362 | unsigned level, bool ats) |
f566ceb1 | 363 | { |
50783147 | 364 | unsigned shift = amdgpu_vm_level_shift(adev, level); |
f566ceb1 | 365 | unsigned pt_idx, from, to; |
3c824172 | 366 | u64 flags; |
13307f7e | 367 | int r; |
f566ceb1 CK |
368 | |
369 | if (!parent->entries) { | |
370 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
371 | ||
2098105e MH |
372 | parent->entries = kvmalloc_array(num_entries, |
373 | sizeof(struct amdgpu_vm_pt), | |
374 | GFP_KERNEL | __GFP_ZERO); | |
f566ceb1 CK |
375 | if (!parent->entries) |
376 | return -ENOMEM; | |
377 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
378 | } | |
379 | ||
1866bac8 FK |
380 | from = saddr >> shift; |
381 | to = eaddr >> shift; | |
382 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
383 | to >= amdgpu_vm_num_entries(adev, level)) | |
384 | return -EINVAL; | |
f566ceb1 | 385 | |
f566ceb1 | 386 | ++level; |
1866bac8 FK |
387 | saddr = saddr & ((1 << shift) - 1); |
388 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 | 389 | |
13307f7e | 390 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; |
3c824172 HK |
391 | if (vm->use_cpu_for_update) |
392 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
393 | else | |
394 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
395 | AMDGPU_GEM_CREATE_SHADOW); | |
396 | ||
f566ceb1 CK |
397 | /* walk over the address space and allocate the page tables */ |
398 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
3f3333f8 | 399 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
f566ceb1 CK |
400 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
401 | struct amdgpu_bo *pt; | |
402 | ||
3f3333f8 | 403 | if (!entry->base.bo) { |
f566ceb1 CK |
404 | r = amdgpu_bo_create(adev, |
405 | amdgpu_vm_bo_size(adev, level), | |
406 | AMDGPU_GPU_PAGE_SIZE, true, | |
13307f7e | 407 | AMDGPU_GEM_DOMAIN_VRAM, flags, |
8febe617 | 408 | NULL, resv, &pt); |
f566ceb1 CK |
409 | if (r) |
410 | return r; | |
411 | ||
4584312d | 412 | r = amdgpu_vm_clear_bo(adev, vm, pt, level, ats); |
13307f7e | 413 | if (r) { |
e5197a4c | 414 | amdgpu_bo_unref(&pt->shadow); |
13307f7e CK |
415 | amdgpu_bo_unref(&pt); |
416 | return r; | |
417 | } | |
418 | ||
0a096fb6 CK |
419 | if (vm->use_cpu_for_update) { |
420 | r = amdgpu_bo_kmap(pt, NULL); | |
421 | if (r) { | |
e5197a4c | 422 | amdgpu_bo_unref(&pt->shadow); |
0a096fb6 CK |
423 | amdgpu_bo_unref(&pt); |
424 | return r; | |
425 | } | |
426 | } | |
427 | ||
f566ceb1 CK |
428 | /* Keep a reference to the root directory to avoid |
429 | * freeing them up in the wrong order. | |
430 | */ | |
0f2fc435 | 431 | pt->parent = amdgpu_bo_ref(parent->base.bo); |
f566ceb1 | 432 | |
3f3333f8 CK |
433 | entry->base.vm = vm; |
434 | entry->base.bo = pt; | |
435 | list_add_tail(&entry->base.bo_list, &pt->va); | |
ea09729c CK |
436 | spin_lock(&vm->status_lock); |
437 | list_add(&entry->base.vm_status, &vm->relocated); | |
438 | spin_unlock(&vm->status_lock); | |
f566ceb1 CK |
439 | } |
440 | ||
196f7489 | 441 | if (level < AMDGPU_VM_PTB) { |
1866bac8 FK |
442 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
443 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
444 | ((1 << shift) - 1); | |
445 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
4584312d | 446 | sub_eaddr, level, ats); |
f566ceb1 CK |
447 | if (r) |
448 | return r; | |
449 | } | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
663e4577 CK |
455 | /** |
456 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
457 | * | |
458 | * @adev: amdgpu_device pointer | |
459 | * @vm: VM to allocate page tables for | |
460 | * @saddr: Start address which needs to be allocated | |
461 | * @size: Size from start address we need. | |
462 | * | |
463 | * Make sure the page tables are allocated. | |
464 | */ | |
465 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
466 | struct amdgpu_vm *vm, | |
467 | uint64_t saddr, uint64_t size) | |
468 | { | |
663e4577 | 469 | uint64_t eaddr; |
4584312d | 470 | bool ats = false; |
663e4577 CK |
471 | |
472 | /* validate the parameters */ | |
473 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
474 | return -EINVAL; | |
475 | ||
476 | eaddr = saddr + size - 1; | |
4584312d CK |
477 | |
478 | if (vm->pte_support_ats) | |
479 | ats = saddr < AMDGPU_VA_HOLE_START; | |
663e4577 CK |
480 | |
481 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
482 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
483 | ||
4584312d CK |
484 | if (eaddr >= adev->vm_manager.max_pfn) { |
485 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", | |
486 | eaddr, adev->vm_manager.max_pfn); | |
487 | return -EINVAL; | |
488 | } | |
489 | ||
196f7489 | 490 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, |
4584312d | 491 | adev->vm_manager.root_level, ats); |
663e4577 CK |
492 | } |
493 | ||
e59c0205 AX |
494 | /** |
495 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
496 | * | |
497 | * @adev: amdgpu_device pointer | |
498 | */ | |
499 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 500 | { |
a1255107 | 501 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
502 | bool has_compute_vm_bug; |
503 | struct amdgpu_ring *ring; | |
504 | int i; | |
93dcc37d | 505 | |
e59c0205 | 506 | has_compute_vm_bug = false; |
93dcc37d | 507 | |
2990a1fc | 508 | ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); |
e59c0205 AX |
509 | if (ip_block) { |
510 | /* Compute has a VM bug for GFX version < 7. | |
511 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
512 | if (ip_block->version->major <= 7) | |
513 | has_compute_vm_bug = true; | |
514 | else if (ip_block->version->major == 8) | |
515 | if (adev->gfx.mec_fw_version < 673) | |
516 | has_compute_vm_bug = true; | |
517 | } | |
93dcc37d | 518 | |
e59c0205 AX |
519 | for (i = 0; i < adev->num_rings; i++) { |
520 | ring = adev->rings[i]; | |
521 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
522 | /* only compute rings */ | |
523 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 524 | else |
e59c0205 | 525 | ring->has_compute_vm_bug = false; |
93dcc37d | 526 | } |
93dcc37d AD |
527 | } |
528 | ||
b9bf33d5 CZ |
529 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
530 | struct amdgpu_job *job) | |
e60f8db5 | 531 | { |
b9bf33d5 CZ |
532 | struct amdgpu_device *adev = ring->adev; |
533 | unsigned vmhub = ring->funcs->vmhub; | |
620f774f CK |
534 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
535 | struct amdgpu_vmid *id; | |
b9bf33d5 | 536 | bool gds_switch_needed; |
e59c0205 | 537 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 | 538 | |
c4f46f22 | 539 | if (job->vmid == 0) |
b9bf33d5 | 540 | return false; |
c4f46f22 | 541 | id = &id_mgr->ids[job->vmid]; |
b9bf33d5 CZ |
542 | gds_switch_needed = ring->funcs->emit_gds_switch && ( |
543 | id->gds_base != job->gds_base || | |
544 | id->gds_size != job->gds_size || | |
545 | id->gws_base != job->gws_base || | |
546 | id->gws_size != job->gws_size || | |
547 | id->oa_base != job->oa_base || | |
548 | id->oa_size != job->oa_size); | |
e60f8db5 | 549 | |
620f774f | 550 | if (amdgpu_vmid_had_gpu_reset(adev, id)) |
b9bf33d5 | 551 | return true; |
e60f8db5 | 552 | |
bb37b67d | 553 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
554 | } |
555 | ||
9a4b7d4c HK |
556 | static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) |
557 | { | |
770d13b1 | 558 | return (adev->gmc.real_vram_size == adev->gmc.visible_vram_size); |
e60f8db5 AX |
559 | } |
560 | ||
d38ceaf9 AD |
561 | /** |
562 | * amdgpu_vm_flush - hardware flush the vm | |
563 | * | |
564 | * @ring: ring to use for flush | |
c4f46f22 | 565 | * @vmid: vmid number to use |
4ff37a83 | 566 | * @pd_addr: address of the page directory |
d38ceaf9 | 567 | * |
4ff37a83 | 568 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 569 | */ |
8fdf074f | 570 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 571 | { |
971fe9a9 | 572 | struct amdgpu_device *adev = ring->adev; |
7645670d | 573 | unsigned vmhub = ring->funcs->vmhub; |
620f774f | 574 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
c4f46f22 | 575 | struct amdgpu_vmid *id = &id_mgr->ids[job->vmid]; |
d564a06e | 576 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
577 | id->gds_base != job->gds_base || |
578 | id->gds_size != job->gds_size || | |
579 | id->gws_base != job->gws_base || | |
580 | id->gws_size != job->gws_size || | |
581 | id->oa_base != job->oa_base || | |
582 | id->oa_size != job->oa_size); | |
de37e68a | 583 | bool vm_flush_needed = job->vm_needs_flush; |
c0e51931 | 584 | unsigned patch_offset = 0; |
41d9eb2c | 585 | int r; |
d564a06e | 586 | |
620f774f | 587 | if (amdgpu_vmid_had_gpu_reset(adev, id)) { |
f7d015b9 CK |
588 | gds_switch_needed = true; |
589 | vm_flush_needed = true; | |
590 | } | |
971fe9a9 | 591 | |
8fdf074f | 592 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 593 | return 0; |
41d9eb2c | 594 | |
c0e51931 CK |
595 | if (ring->funcs->init_cond_exec) |
596 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 597 | |
8fdf074f ML |
598 | if (need_pipe_sync) |
599 | amdgpu_ring_emit_pipeline_sync(ring); | |
600 | ||
f7d015b9 | 601 | if (ring->funcs->emit_vm_flush && vm_flush_needed) { |
c0e51931 | 602 | struct dma_fence *fence; |
41d9eb2c | 603 | |
c4f46f22 | 604 | trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr); |
5a4633c4 CK |
605 | amdgpu_ring_emit_vm_flush(ring, job->vmid, job->pasid, |
606 | job->vm_pd_addr); | |
e9d672b2 | 607 | |
c0e51931 CK |
608 | r = amdgpu_fence_emit(ring, &fence); |
609 | if (r) | |
610 | return r; | |
e9d672b2 | 611 | |
7645670d | 612 | mutex_lock(&id_mgr->lock); |
c0e51931 CK |
613 | dma_fence_put(id->last_flush); |
614 | id->last_flush = fence; | |
bea39672 | 615 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
7645670d | 616 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 617 | } |
e9d672b2 | 618 | |
7c4378f4 | 619 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
620 | id->gds_base = job->gds_base; |
621 | id->gds_size = job->gds_size; | |
622 | id->gws_base = job->gws_base; | |
623 | id->gws_size = job->gws_size; | |
624 | id->oa_base = job->oa_base; | |
625 | id->oa_size = job->oa_size; | |
c4f46f22 | 626 | amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base, |
c0e51931 CK |
627 | job->gds_size, job->gws_base, |
628 | job->gws_size, job->oa_base, | |
629 | job->oa_size); | |
630 | } | |
631 | ||
632 | if (ring->funcs->patch_cond_exec) | |
633 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
634 | ||
635 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
636 | if (ring->funcs->emit_switch_buffer) { | |
637 | amdgpu_ring_emit_switch_buffer(ring); | |
638 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 639 | } |
41d9eb2c | 640 | return 0; |
971fe9a9 CK |
641 | } |
642 | ||
d38ceaf9 AD |
643 | /** |
644 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
645 | * | |
646 | * @vm: requested vm | |
647 | * @bo: requested buffer object | |
648 | * | |
8843dbbb | 649 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
650 | * Search inside the @bos vm list for the requested vm |
651 | * Returns the found bo_va or NULL if none is found | |
652 | * | |
653 | * Object has to be reserved! | |
654 | */ | |
655 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
656 | struct amdgpu_bo *bo) | |
657 | { | |
658 | struct amdgpu_bo_va *bo_va; | |
659 | ||
ec681545 CK |
660 | list_for_each_entry(bo_va, &bo->va, base.bo_list) { |
661 | if (bo_va->base.vm == vm) { | |
d38ceaf9 AD |
662 | return bo_va; |
663 | } | |
664 | } | |
665 | return NULL; | |
666 | } | |
667 | ||
668 | /** | |
afef8b8f | 669 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 670 | * |
29efc4f5 | 671 | * @params: see amdgpu_pte_update_params definition |
373ac645 | 672 | * @bo: PD/PT to update |
d38ceaf9 AD |
673 | * @pe: addr of the page entry |
674 | * @addr: dst addr to write into pe | |
675 | * @count: number of page entries to update | |
676 | * @incr: increase next addr by incr bytes | |
677 | * @flags: hw access flags | |
d38ceaf9 AD |
678 | * |
679 | * Traces the parameters and calls the right asic functions | |
680 | * to setup the page table using the DMA. | |
681 | */ | |
afef8b8f | 682 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
373ac645 | 683 | struct amdgpu_bo *bo, |
afef8b8f CK |
684 | uint64_t pe, uint64_t addr, |
685 | unsigned count, uint32_t incr, | |
6b777607 | 686 | uint64_t flags) |
d38ceaf9 | 687 | { |
373ac645 | 688 | pe += amdgpu_bo_gpu_offset(bo); |
ec2f05f0 | 689 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 690 | |
afef8b8f | 691 | if (count < 3) { |
de9ea7bd CK |
692 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
693 | addr | flags, count, incr); | |
d38ceaf9 AD |
694 | |
695 | } else { | |
27c5f36f | 696 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
697 | count, incr, flags); |
698 | } | |
699 | } | |
700 | ||
afef8b8f CK |
701 | /** |
702 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
703 | * | |
704 | * @params: see amdgpu_pte_update_params definition | |
373ac645 | 705 | * @bo: PD/PT to update |
afef8b8f CK |
706 | * @pe: addr of the page entry |
707 | * @addr: dst addr to write into pe | |
708 | * @count: number of page entries to update | |
709 | * @incr: increase next addr by incr bytes | |
710 | * @flags: hw access flags | |
711 | * | |
712 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
713 | */ | |
714 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
373ac645 | 715 | struct amdgpu_bo *bo, |
afef8b8f CK |
716 | uint64_t pe, uint64_t addr, |
717 | unsigned count, uint32_t incr, | |
6b777607 | 718 | uint64_t flags) |
afef8b8f | 719 | { |
ec2f05f0 | 720 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 721 | |
373ac645 | 722 | pe += amdgpu_bo_gpu_offset(bo); |
ec2f05f0 CK |
723 | trace_amdgpu_vm_copy_ptes(pe, src, count); |
724 | ||
725 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
726 | } |
727 | ||
d38ceaf9 | 728 | /** |
b07c9d2a | 729 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 730 | * |
b07c9d2a | 731 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
732 | * @addr: the unmapped addr |
733 | * | |
734 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 735 | * to and return the pointer for the page table entry. |
d38ceaf9 | 736 | */ |
de9ea7bd | 737 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
738 | { |
739 | uint64_t result; | |
740 | ||
de9ea7bd CK |
741 | /* page table offset */ |
742 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 743 | |
de9ea7bd CK |
744 | /* in case cpu page size != gpu page size*/ |
745 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 746 | |
b07c9d2a | 747 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
748 | |
749 | return result; | |
750 | } | |
751 | ||
3c824172 HK |
752 | /** |
753 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU | |
754 | * | |
755 | * @params: see amdgpu_pte_update_params definition | |
373ac645 | 756 | * @bo: PD/PT to update |
3c824172 HK |
757 | * @pe: kmap addr of the page entry |
758 | * @addr: dst addr to write into pe | |
759 | * @count: number of page entries to update | |
760 | * @incr: increase next addr by incr bytes | |
761 | * @flags: hw access flags | |
762 | * | |
763 | * Write count number of PT/PD entries directly. | |
764 | */ | |
765 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, | |
373ac645 | 766 | struct amdgpu_bo *bo, |
3c824172 HK |
767 | uint64_t pe, uint64_t addr, |
768 | unsigned count, uint32_t incr, | |
769 | uint64_t flags) | |
770 | { | |
771 | unsigned int i; | |
b4d42511 | 772 | uint64_t value; |
3c824172 | 773 | |
373ac645 CK |
774 | pe += (unsigned long)amdgpu_bo_kptr(bo); |
775 | ||
03918b36 CK |
776 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
777 | ||
3c824172 | 778 | for (i = 0; i < count; i++) { |
b4d42511 HK |
779 | value = params->pages_addr ? |
780 | amdgpu_vm_map_gart(params->pages_addr, addr) : | |
781 | addr; | |
132f34e4 CK |
782 | amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe, |
783 | i, value, flags); | |
3c824172 HK |
784 | addr += incr; |
785 | } | |
3c824172 HK |
786 | } |
787 | ||
a33cab7a CK |
788 | static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
789 | void *owner) | |
3c824172 HK |
790 | { |
791 | struct amdgpu_sync sync; | |
792 | int r; | |
793 | ||
794 | amdgpu_sync_create(&sync); | |
177ae09b | 795 | amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false); |
3c824172 HK |
796 | r = amdgpu_sync_wait(&sync, true); |
797 | amdgpu_sync_free(&sync); | |
798 | ||
799 | return r; | |
800 | } | |
801 | ||
f8991bab | 802 | /* |
6989f246 | 803 | * amdgpu_vm_update_pde - update a single level in the hierarchy |
f8991bab | 804 | * |
6989f246 | 805 | * @param: parameters for the update |
f8991bab | 806 | * @vm: requested vm |
194d2161 | 807 | * @parent: parent directory |
6989f246 | 808 | * @entry: entry to update |
f8991bab | 809 | * |
6989f246 | 810 | * Makes sure the requested entry in parent is up to date. |
f8991bab | 811 | */ |
6989f246 CK |
812 | static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, |
813 | struct amdgpu_vm *vm, | |
814 | struct amdgpu_vm_pt *parent, | |
815 | struct amdgpu_vm_pt *entry) | |
d38ceaf9 | 816 | { |
373ac645 | 817 | struct amdgpu_bo *bo = parent->base.bo, *pbo; |
3de676d8 CK |
818 | uint64_t pde, pt, flags; |
819 | unsigned level; | |
d5fc5e82 | 820 | |
6989f246 CK |
821 | /* Don't update huge pages here */ |
822 | if (entry->huge) | |
823 | return; | |
d38ceaf9 | 824 | |
373ac645 | 825 | for (level = 0, pbo = bo->parent; pbo; ++level) |
3de676d8 CK |
826 | pbo = pbo->parent; |
827 | ||
196f7489 | 828 | level += params->adev->vm_manager.root_level; |
373ac645 | 829 | pt = amdgpu_bo_gpu_offset(entry->base.bo); |
3de676d8 | 830 | flags = AMDGPU_PTE_VALID; |
132f34e4 | 831 | amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags); |
373ac645 CK |
832 | pde = (entry - parent->entries) * 8; |
833 | if (bo->shadow) | |
834 | params->func(params, bo->shadow, pde, pt, 1, 0, flags); | |
835 | params->func(params, bo, pde, pt, 1, 0, flags); | |
d38ceaf9 AD |
836 | } |
837 | ||
92456b93 CK |
838 | /* |
839 | * amdgpu_vm_invalidate_level - mark all PD levels as invalid | |
840 | * | |
841 | * @parent: parent PD | |
842 | * | |
843 | * Mark all PD level as invalid after an error. | |
844 | */ | |
8f19cd78 CK |
845 | static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev, |
846 | struct amdgpu_vm *vm, | |
847 | struct amdgpu_vm_pt *parent, | |
848 | unsigned level) | |
92456b93 | 849 | { |
8f19cd78 | 850 | unsigned pt_idx, num_entries; |
92456b93 CK |
851 | |
852 | /* | |
853 | * Recurse into the subdirectories. This recursion is harmless because | |
854 | * we only have a maximum of 5 layers. | |
855 | */ | |
8f19cd78 CK |
856 | num_entries = amdgpu_vm_num_entries(adev, level); |
857 | for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) { | |
92456b93 CK |
858 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
859 | ||
3f3333f8 | 860 | if (!entry->base.bo) |
92456b93 CK |
861 | continue; |
862 | ||
ea09729c | 863 | spin_lock(&vm->status_lock); |
481c2e94 CK |
864 | if (list_empty(&entry->base.vm_status)) |
865 | list_add(&entry->base.vm_status, &vm->relocated); | |
ea09729c | 866 | spin_unlock(&vm->status_lock); |
8f19cd78 | 867 | amdgpu_vm_invalidate_level(adev, vm, entry, level + 1); |
92456b93 CK |
868 | } |
869 | } | |
870 | ||
194d2161 CK |
871 | /* |
872 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
873 | * | |
874 | * @adev: amdgpu_device pointer | |
875 | * @vm: requested vm | |
876 | * | |
877 | * Makes sure all directories are up to date. | |
878 | * Returns 0 for success, error for failure. | |
879 | */ | |
880 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
881 | struct amdgpu_vm *vm) | |
882 | { | |
6989f246 CK |
883 | struct amdgpu_pte_update_params params; |
884 | struct amdgpu_job *job; | |
885 | unsigned ndw = 0; | |
78aa02c7 | 886 | int r = 0; |
92456b93 | 887 | |
6989f246 CK |
888 | if (list_empty(&vm->relocated)) |
889 | return 0; | |
890 | ||
891 | restart: | |
892 | memset(¶ms, 0, sizeof(params)); | |
893 | params.adev = adev; | |
894 | ||
895 | if (vm->use_cpu_for_update) { | |
896 | r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); | |
897 | if (unlikely(r)) | |
898 | return r; | |
899 | ||
900 | params.func = amdgpu_vm_cpu_set_ptes; | |
901 | } else { | |
902 | ndw = 512 * 8; | |
903 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
904 | if (r) | |
905 | return r; | |
906 | ||
907 | params.ib = &job->ibs[0]; | |
908 | params.func = amdgpu_vm_do_set_ptes; | |
909 | } | |
910 | ||
ea09729c CK |
911 | spin_lock(&vm->status_lock); |
912 | while (!list_empty(&vm->relocated)) { | |
6989f246 CK |
913 | struct amdgpu_vm_bo_base *bo_base, *parent; |
914 | struct amdgpu_vm_pt *pt, *entry; | |
ea09729c CK |
915 | struct amdgpu_bo *bo; |
916 | ||
917 | bo_base = list_first_entry(&vm->relocated, | |
918 | struct amdgpu_vm_bo_base, | |
919 | vm_status); | |
6989f246 | 920 | list_del_init(&bo_base->vm_status); |
ea09729c CK |
921 | spin_unlock(&vm->status_lock); |
922 | ||
923 | bo = bo_base->bo->parent; | |
6989f246 | 924 | if (!bo) { |
ea09729c | 925 | spin_lock(&vm->status_lock); |
6989f246 | 926 | continue; |
ea09729c | 927 | } |
6989f246 CK |
928 | |
929 | parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base, | |
930 | bo_list); | |
931 | pt = container_of(parent, struct amdgpu_vm_pt, base); | |
932 | entry = container_of(bo_base, struct amdgpu_vm_pt, base); | |
933 | ||
934 | amdgpu_vm_update_pde(¶ms, vm, pt, entry); | |
935 | ||
936 | spin_lock(&vm->status_lock); | |
937 | if (!vm->use_cpu_for_update && | |
938 | (ndw - params.ib->length_dw) < 32) | |
939 | break; | |
ea09729c CK |
940 | } |
941 | spin_unlock(&vm->status_lock); | |
92456b93 | 942 | |
68c62306 CK |
943 | if (vm->use_cpu_for_update) { |
944 | /* Flush HDP */ | |
945 | mb(); | |
69882565 | 946 | amdgpu_asic_flush_hdp(adev, NULL); |
6989f246 CK |
947 | } else if (params.ib->length_dw == 0) { |
948 | amdgpu_job_free(job); | |
949 | } else { | |
950 | struct amdgpu_bo *root = vm->root.base.bo; | |
951 | struct amdgpu_ring *ring; | |
952 | struct dma_fence *fence; | |
953 | ||
954 | ring = container_of(vm->entity.sched, struct amdgpu_ring, | |
955 | sched); | |
956 | ||
957 | amdgpu_ring_pad_ib(ring, params.ib); | |
958 | amdgpu_sync_resv(adev, &job->sync, root->tbo.resv, | |
959 | AMDGPU_FENCE_OWNER_VM, false); | |
6989f246 CK |
960 | WARN_ON(params.ib->length_dw > ndw); |
961 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
962 | AMDGPU_FENCE_OWNER_VM, &fence); | |
963 | if (r) | |
964 | goto error; | |
965 | ||
966 | amdgpu_bo_fence(root, fence, true); | |
967 | dma_fence_put(vm->last_update); | |
968 | vm->last_update = fence; | |
68c62306 CK |
969 | } |
970 | ||
6989f246 CK |
971 | if (!list_empty(&vm->relocated)) |
972 | goto restart; | |
973 | ||
974 | return 0; | |
975 | ||
976 | error: | |
196f7489 CZ |
977 | amdgpu_vm_invalidate_level(adev, vm, &vm->root, |
978 | adev->vm_manager.root_level); | |
6989f246 | 979 | amdgpu_job_free(job); |
92456b93 | 980 | return r; |
194d2161 CK |
981 | } |
982 | ||
4e2cb640 | 983 | /** |
cf2f0a37 | 984 | * amdgpu_vm_find_entry - find the entry for an address |
4e2cb640 CK |
985 | * |
986 | * @p: see amdgpu_pte_update_params definition | |
987 | * @addr: virtual address in question | |
cf2f0a37 AD |
988 | * @entry: resulting entry or NULL |
989 | * @parent: parent entry | |
4e2cb640 | 990 | * |
cf2f0a37 | 991 | * Find the vm_pt entry and it's parent for the given address. |
4e2cb640 | 992 | */ |
cf2f0a37 AD |
993 | void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, |
994 | struct amdgpu_vm_pt **entry, | |
995 | struct amdgpu_vm_pt **parent) | |
4e2cb640 | 996 | { |
196f7489 | 997 | unsigned level = p->adev->vm_manager.root_level; |
4e2cb640 | 998 | |
cf2f0a37 AD |
999 | *parent = NULL; |
1000 | *entry = &p->vm->root; | |
1001 | while ((*entry)->entries) { | |
e3a1b32a | 1002 | unsigned shift = amdgpu_vm_level_shift(p->adev, level++); |
50783147 | 1003 | |
cf2f0a37 | 1004 | *parent = *entry; |
e3a1b32a CK |
1005 | *entry = &(*entry)->entries[addr >> shift]; |
1006 | addr &= (1ULL << shift) - 1; | |
4e2cb640 CK |
1007 | } |
1008 | ||
196f7489 | 1009 | if (level != AMDGPU_VM_PTB) |
cf2f0a37 AD |
1010 | *entry = NULL; |
1011 | } | |
1012 | ||
1013 | /** | |
1014 | * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages | |
1015 | * | |
1016 | * @p: see amdgpu_pte_update_params definition | |
1017 | * @entry: vm_pt entry to check | |
1018 | * @parent: parent entry | |
1019 | * @nptes: number of PTEs updated with this operation | |
1020 | * @dst: destination address where the PTEs should point to | |
1021 | * @flags: access flags fro the PTEs | |
1022 | * | |
1023 | * Check if we can update the PD with a huge page. | |
1024 | */ | |
ec5207c9 CK |
1025 | static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, |
1026 | struct amdgpu_vm_pt *entry, | |
1027 | struct amdgpu_vm_pt *parent, | |
1028 | unsigned nptes, uint64_t dst, | |
1029 | uint64_t flags) | |
cf2f0a37 | 1030 | { |
373ac645 | 1031 | uint64_t pde; |
cf2f0a37 AD |
1032 | |
1033 | /* In the case of a mixed PT the PDE must point to it*/ | |
3cc1d3ea CK |
1034 | if (p->adev->asic_type >= CHIP_VEGA10 && !p->src && |
1035 | nptes == AMDGPU_VM_PTE_COUNT(p->adev)) { | |
4ab4016a | 1036 | /* Set the huge page flag to stop scanning at this PDE */ |
cf2f0a37 AD |
1037 | flags |= AMDGPU_PDE_PTE; |
1038 | } | |
1039 | ||
3cc1d3ea CK |
1040 | if (!(flags & AMDGPU_PDE_PTE)) { |
1041 | if (entry->huge) { | |
1042 | /* Add the entry to the relocated list to update it. */ | |
1043 | entry->huge = false; | |
1044 | spin_lock(&p->vm->status_lock); | |
1045 | list_move(&entry->base.vm_status, &p->vm->relocated); | |
1046 | spin_unlock(&p->vm->status_lock); | |
1047 | } | |
ec5207c9 | 1048 | return; |
3cc1d3ea | 1049 | } |
cf2f0a37 | 1050 | |
3cc1d3ea | 1051 | entry->huge = true; |
132f34e4 | 1052 | amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags); |
3de676d8 | 1053 | |
373ac645 CK |
1054 | pde = (entry - parent->entries) * 8; |
1055 | if (parent->base.bo->shadow) | |
1056 | p->func(p, parent->base.bo->shadow, pde, dst, 1, 0, flags); | |
1057 | p->func(p, parent->base.bo, pde, dst, 1, 0, flags); | |
4e2cb640 CK |
1058 | } |
1059 | ||
d38ceaf9 AD |
1060 | /** |
1061 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1062 | * | |
29efc4f5 | 1063 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1064 | * @vm: requested vm |
1065 | * @start: start of GPU address range | |
1066 | * @end: end of GPU address range | |
677131a1 | 1067 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1068 | * @flags: mapping flags |
1069 | * | |
8843dbbb | 1070 | * Update the page tables in the range @start - @end. |
cc28c4ed | 1071 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 | 1072 | */ |
cc28c4ed | 1073 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1074 | uint64_t start, uint64_t end, |
6b777607 | 1075 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1076 | { |
36b32a68 ZJ |
1077 | struct amdgpu_device *adev = params->adev; |
1078 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1079 | |
301654a4 | 1080 | uint64_t addr, pe_start; |
21718497 | 1081 | struct amdgpu_bo *pt; |
301654a4 | 1082 | unsigned nptes; |
d38ceaf9 AD |
1083 | |
1084 | /* walk over the address space and update the page tables */ | |
cf2f0a37 AD |
1085 | for (addr = start; addr < end; addr += nptes, |
1086 | dst += nptes * AMDGPU_GPU_PAGE_SIZE) { | |
1087 | struct amdgpu_vm_pt *entry, *parent; | |
1088 | ||
1089 | amdgpu_vm_get_entry(params, addr, &entry, &parent); | |
1090 | if (!entry) | |
1091 | return -ENOENT; | |
4e2cb640 | 1092 | |
d38ceaf9 AD |
1093 | if ((addr & ~mask) == (end & ~mask)) |
1094 | nptes = end - addr; | |
1095 | else | |
36b32a68 | 1096 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1097 | |
ec5207c9 CK |
1098 | amdgpu_vm_handle_huge_pages(params, entry, parent, |
1099 | nptes, dst, flags); | |
4ab4016a | 1100 | /* We don't need to update PTEs for huge pages */ |
78eb2f0c | 1101 | if (entry->huge) |
cf2f0a37 AD |
1102 | continue; |
1103 | ||
3f3333f8 | 1104 | pt = entry->base.bo; |
373ac645 CK |
1105 | pe_start = (addr & mask) * 8; |
1106 | if (pt->shadow) | |
1107 | params->func(params, pt->shadow, pe_start, dst, nptes, | |
1108 | AMDGPU_GPU_PAGE_SIZE, flags); | |
1109 | params->func(params, pt, pe_start, dst, nptes, | |
301654a4 | 1110 | AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
1111 | } |
1112 | ||
cc28c4ed | 1113 | return 0; |
92696dd5 CK |
1114 | } |
1115 | ||
1116 | /* | |
1117 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1118 | * | |
1119 | * @params: see amdgpu_pte_update_params definition | |
1120 | * @vm: requested vm | |
1121 | * @start: first PTE to handle | |
1122 | * @end: last PTE to handle | |
1123 | * @dst: addr those PTEs should point to | |
1124 | * @flags: hw mapping flags | |
cc28c4ed | 1125 | * Returns 0 for success, -EINVAL for failure. |
92696dd5 | 1126 | */ |
cc28c4ed | 1127 | static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, |
92696dd5 | 1128 | uint64_t start, uint64_t end, |
6b777607 | 1129 | uint64_t dst, uint64_t flags) |
92696dd5 CK |
1130 | { |
1131 | /** | |
1132 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1133 | * field in the PTE. When this field is set to a non-zero value, page | |
1134 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1135 | * flags are considered valid for all PTEs within the fragment range | |
1136 | * and corresponding mappings are assumed to be physically contiguous. | |
1137 | * | |
1138 | * The L1 TLB can store a single PTE for the whole fragment, | |
1139 | * significantly increasing the space available for translation | |
1140 | * caching. This leads to large improvements in throughput when the | |
1141 | * TLB is under pressure. | |
1142 | * | |
1143 | * The L2 TLB distributes small and large fragments into two | |
1144 | * asymmetric partitions. The large fragment cache is significantly | |
1145 | * larger. Thus, we try to use large fragments wherever possible. | |
1146 | * Userspace can support this by aligning virtual base address and | |
1147 | * allocation size to the fragment size. | |
1148 | */ | |
6849d47c RH |
1149 | unsigned max_frag = params->adev->vm_manager.fragment_size; |
1150 | int r; | |
92696dd5 CK |
1151 | |
1152 | /* system pages are non continuously */ | |
6849d47c | 1153 | if (params->src || !(flags & AMDGPU_PTE_VALID)) |
cc28c4ed | 1154 | return amdgpu_vm_update_ptes(params, start, end, dst, flags); |
92696dd5 | 1155 | |
6849d47c RH |
1156 | while (start != end) { |
1157 | uint64_t frag_flags, frag_end; | |
1158 | unsigned frag; | |
1159 | ||
1160 | /* This intentionally wraps around if no bit is set */ | |
1161 | frag = min((unsigned)ffs(start) - 1, | |
1162 | (unsigned)fls64(end - start) - 1); | |
1163 | if (frag >= max_frag) { | |
1164 | frag_flags = AMDGPU_PTE_FRAG(max_frag); | |
1165 | frag_end = end & ~((1ULL << max_frag) - 1); | |
1166 | } else { | |
1167 | frag_flags = AMDGPU_PTE_FRAG(frag); | |
1168 | frag_end = start + (1 << frag); | |
1169 | } | |
1170 | ||
1171 | r = amdgpu_vm_update_ptes(params, start, frag_end, dst, | |
1172 | flags | frag_flags); | |
cc28c4ed HK |
1173 | if (r) |
1174 | return r; | |
92696dd5 | 1175 | |
6849d47c RH |
1176 | dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE; |
1177 | start = frag_end; | |
92696dd5 | 1178 | } |
6849d47c RH |
1179 | |
1180 | return 0; | |
d38ceaf9 AD |
1181 | } |
1182 | ||
d38ceaf9 AD |
1183 | /** |
1184 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1185 | * | |
1186 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1187 | * @exclusive: fence we need to sync to |
fa3ab3c7 | 1188 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 | 1189 | * @vm: requested vm |
a14faa65 CK |
1190 | * @start: start of mapped range |
1191 | * @last: last mapped entry | |
1192 | * @flags: flags for the entries | |
d38ceaf9 | 1193 | * @addr: addr to set the area to |
d38ceaf9 AD |
1194 | * @fence: optional resulting fence |
1195 | * | |
a14faa65 | 1196 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 1197 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
1198 | */ |
1199 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1200 | struct dma_fence *exclusive, |
fa3ab3c7 | 1201 | dma_addr_t *pages_addr, |
d38ceaf9 | 1202 | struct amdgpu_vm *vm, |
a14faa65 | 1203 | uint64_t start, uint64_t last, |
6b777607 | 1204 | uint64_t flags, uint64_t addr, |
f54d1867 | 1205 | struct dma_fence **fence) |
d38ceaf9 | 1206 | { |
2d55e45a | 1207 | struct amdgpu_ring *ring; |
a1e08d3b | 1208 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1209 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1210 | struct amdgpu_job *job; |
29efc4f5 | 1211 | struct amdgpu_pte_update_params params; |
f54d1867 | 1212 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1213 | int r; |
1214 | ||
afef8b8f CK |
1215 | memset(¶ms, 0, sizeof(params)); |
1216 | params.adev = adev; | |
49ac8a24 | 1217 | params.vm = vm; |
afef8b8f | 1218 | |
a33cab7a CK |
1219 | /* sync to everything on unmapping */ |
1220 | if (!(flags & AMDGPU_PTE_VALID)) | |
1221 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1222 | ||
b4d42511 HK |
1223 | if (vm->use_cpu_for_update) { |
1224 | /* params.src is used as flag to indicate system Memory */ | |
1225 | if (pages_addr) | |
1226 | params.src = ~0; | |
1227 | ||
1228 | /* Wait for PT BOs to be free. PTs share the same resv. object | |
1229 | * as the root PD BO | |
1230 | */ | |
a33cab7a | 1231 | r = amdgpu_vm_wait_pd(adev, vm, owner); |
b4d42511 HK |
1232 | if (unlikely(r)) |
1233 | return r; | |
1234 | ||
1235 | params.func = amdgpu_vm_cpu_set_ptes; | |
1236 | params.pages_addr = pages_addr; | |
b4d42511 HK |
1237 | return amdgpu_vm_frag_ptes(¶ms, start, last + 1, |
1238 | addr, flags); | |
1239 | } | |
1240 | ||
2d55e45a | 1241 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 1242 | |
a14faa65 | 1243 | nptes = last - start + 1; |
d38ceaf9 AD |
1244 | |
1245 | /* | |
86209523 | 1246 | * reserve space for two commands every (1 << BLOCK_SIZE) |
d38ceaf9 | 1247 | * entries or 2k dwords (whatever is smaller) |
86209523 BN |
1248 | * |
1249 | * The second command is for the shadow pagetables. | |
d38ceaf9 | 1250 | */ |
104bd2ca ED |
1251 | if (vm->root.base.bo->shadow) |
1252 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2; | |
1253 | else | |
1254 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1); | |
d38ceaf9 AD |
1255 | |
1256 | /* padding, etc. */ | |
1257 | ndw = 64; | |
1258 | ||
570144c6 | 1259 | if (pages_addr) { |
b0456f93 | 1260 | /* copy commands needed */ |
e6d92197 | 1261 | ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; |
d38ceaf9 | 1262 | |
b0456f93 | 1263 | /* and also PTEs */ |
d38ceaf9 AD |
1264 | ndw += nptes * 2; |
1265 | ||
afef8b8f CK |
1266 | params.func = amdgpu_vm_do_copy_ptes; |
1267 | ||
d38ceaf9 AD |
1268 | } else { |
1269 | /* set page commands needed */ | |
44e1baeb | 1270 | ndw += ncmds * 10; |
d38ceaf9 | 1271 | |
6849d47c | 1272 | /* extra commands for begin/end fragments */ |
44e1baeb | 1273 | ndw += 2 * 10 * adev->vm_manager.fragment_size; |
afef8b8f CK |
1274 | |
1275 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1276 | } |
1277 | ||
d71518b5 CK |
1278 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1279 | if (r) | |
d38ceaf9 | 1280 | return r; |
d71518b5 | 1281 | |
29efc4f5 | 1282 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1283 | |
570144c6 | 1284 | if (pages_addr) { |
b0456f93 CK |
1285 | uint64_t *pte; |
1286 | unsigned i; | |
1287 | ||
1288 | /* Put the PTEs at the end of the IB. */ | |
1289 | i = ndw - nptes * 2; | |
1290 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1291 | params.src = job->ibs->gpu_addr + i * 4; | |
1292 | ||
1293 | for (i = 0; i < nptes; ++i) { | |
1294 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1295 | AMDGPU_GPU_PAGE_SIZE); | |
1296 | pte[i] |= flags; | |
1297 | } | |
d7a4ac66 | 1298 | addr = 0; |
b0456f93 CK |
1299 | } |
1300 | ||
cebb52b7 | 1301 | r = amdgpu_sync_fence(adev, &job->sync, exclusive, false); |
3cabaa54 CK |
1302 | if (r) |
1303 | goto error_free; | |
1304 | ||
3f3333f8 | 1305 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, |
177ae09b | 1306 | owner, false); |
a1e08d3b CK |
1307 | if (r) |
1308 | goto error_free; | |
d38ceaf9 | 1309 | |
3f3333f8 | 1310 | r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv); |
a1e08d3b CK |
1311 | if (r) |
1312 | goto error_free; | |
1313 | ||
cc28c4ed HK |
1314 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
1315 | if (r) | |
1316 | goto error_free; | |
d38ceaf9 | 1317 | |
29efc4f5 CK |
1318 | amdgpu_ring_pad_ib(ring, params.ib); |
1319 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1320 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1321 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1322 | if (r) |
1323 | goto error_free; | |
d38ceaf9 | 1324 | |
3f3333f8 | 1325 | amdgpu_bo_fence(vm->root.base.bo, f, true); |
284710fa CK |
1326 | dma_fence_put(*fence); |
1327 | *fence = f; | |
d38ceaf9 | 1328 | return 0; |
d5fc5e82 CZ |
1329 | |
1330 | error_free: | |
d71518b5 | 1331 | amdgpu_job_free(job); |
4af9f07c | 1332 | return r; |
d38ceaf9 AD |
1333 | } |
1334 | ||
a14faa65 CK |
1335 | /** |
1336 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1337 | * | |
1338 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1339 | * @exclusive: fence we need to sync to |
8358dcee | 1340 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1341 | * @vm: requested vm |
1342 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1343 | * @flags: HW flags for the mapping |
63e0ba40 | 1344 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1345 | * @fence: optional resulting fence |
1346 | * | |
1347 | * Split the mapping into smaller chunks so that each update fits | |
1348 | * into a SDMA IB. | |
1349 | * Returns 0 for success, -EINVAL for failure. | |
1350 | */ | |
1351 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1352 | struct dma_fence *exclusive, |
8358dcee | 1353 | dma_addr_t *pages_addr, |
a14faa65 CK |
1354 | struct amdgpu_vm *vm, |
1355 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1356 | uint64_t flags, |
63e0ba40 | 1357 | struct drm_mm_node *nodes, |
f54d1867 | 1358 | struct dma_fence **fence) |
a14faa65 | 1359 | { |
9fc8fc70 | 1360 | unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; |
570144c6 | 1361 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1362 | int r; |
1363 | ||
1364 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1365 | * but in case of something, we filter the flags in first place | |
1366 | */ | |
1367 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1368 | flags &= ~AMDGPU_PTE_READABLE; | |
1369 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1370 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1371 | ||
15b31c59 AX |
1372 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1373 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1374 | ||
b0fd18b0 AX |
1375 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1376 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1377 | ||
d0766e98 ZJ |
1378 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1379 | (adev->asic_type >= CHIP_VEGA10)) { | |
1380 | flags |= AMDGPU_PTE_PRT; | |
1381 | flags &= ~AMDGPU_PTE_VALID; | |
1382 | } | |
1383 | ||
a14faa65 CK |
1384 | trace_amdgpu_vm_bo_update(mapping); |
1385 | ||
63e0ba40 CK |
1386 | pfn = mapping->offset >> PAGE_SHIFT; |
1387 | if (nodes) { | |
1388 | while (pfn >= nodes->size) { | |
1389 | pfn -= nodes->size; | |
1390 | ++nodes; | |
1391 | } | |
fa3ab3c7 | 1392 | } |
a14faa65 | 1393 | |
63e0ba40 | 1394 | do { |
9fc8fc70 | 1395 | dma_addr_t *dma_addr = NULL; |
63e0ba40 CK |
1396 | uint64_t max_entries; |
1397 | uint64_t addr, last; | |
a14faa65 | 1398 | |
63e0ba40 CK |
1399 | if (nodes) { |
1400 | addr = nodes->start << PAGE_SHIFT; | |
1401 | max_entries = (nodes->size - pfn) * | |
1402 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1403 | } else { | |
1404 | addr = 0; | |
1405 | max_entries = S64_MAX; | |
1406 | } | |
a14faa65 | 1407 | |
63e0ba40 | 1408 | if (pages_addr) { |
9fc8fc70 CK |
1409 | uint64_t count; |
1410 | ||
457e0fee | 1411 | max_entries = min(max_entries, 16ull * 1024ull); |
9fc8fc70 CK |
1412 | for (count = 1; count < max_entries; ++count) { |
1413 | uint64_t idx = pfn + count; | |
1414 | ||
1415 | if (pages_addr[idx] != | |
1416 | (pages_addr[idx - 1] + PAGE_SIZE)) | |
1417 | break; | |
1418 | } | |
1419 | ||
1420 | if (count < min_linear_pages) { | |
1421 | addr = pfn << PAGE_SHIFT; | |
1422 | dma_addr = pages_addr; | |
1423 | } else { | |
1424 | addr = pages_addr[pfn]; | |
1425 | max_entries = count; | |
1426 | } | |
1427 | ||
63e0ba40 CK |
1428 | } else if (flags & AMDGPU_PTE_VALID) { |
1429 | addr += adev->vm_manager.vram_base_offset; | |
9fc8fc70 | 1430 | addr += pfn << PAGE_SHIFT; |
63e0ba40 | 1431 | } |
63e0ba40 | 1432 | |
a9f87f64 | 1433 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
9fc8fc70 | 1434 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, |
a14faa65 CK |
1435 | start, last, flags, addr, |
1436 | fence); | |
1437 | if (r) | |
1438 | return r; | |
1439 | ||
63e0ba40 CK |
1440 | pfn += last - start + 1; |
1441 | if (nodes && nodes->size == pfn) { | |
1442 | pfn = 0; | |
1443 | ++nodes; | |
1444 | } | |
a14faa65 | 1445 | start = last + 1; |
63e0ba40 | 1446 | |
a9f87f64 | 1447 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1448 | |
1449 | return 0; | |
1450 | } | |
1451 | ||
d38ceaf9 AD |
1452 | /** |
1453 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1454 | * | |
1455 | * @adev: amdgpu_device pointer | |
1456 | * @bo_va: requested BO and VM object | |
99e124f4 | 1457 | * @clear: if true clear the entries |
d38ceaf9 AD |
1458 | * |
1459 | * Fill in the page table entries for @bo_va. | |
1460 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1461 | */ |
1462 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1463 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1464 | bool clear) |
d38ceaf9 | 1465 | { |
ec681545 CK |
1466 | struct amdgpu_bo *bo = bo_va->base.bo; |
1467 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1468 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1469 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 1470 | struct ttm_mem_reg *mem; |
63e0ba40 | 1471 | struct drm_mm_node *nodes; |
4e55eb38 | 1472 | struct dma_fence *exclusive, **last_update; |
457e0fee | 1473 | uint64_t flags; |
d38ceaf9 AD |
1474 | int r; |
1475 | ||
ec681545 | 1476 | if (clear || !bo_va->base.bo) { |
99e124f4 | 1477 | mem = NULL; |
63e0ba40 | 1478 | nodes = NULL; |
99e124f4 CK |
1479 | exclusive = NULL; |
1480 | } else { | |
8358dcee CK |
1481 | struct ttm_dma_tt *ttm; |
1482 | ||
ec681545 | 1483 | mem = &bo_va->base.bo->tbo.mem; |
63e0ba40 CK |
1484 | nodes = mem->mm_node; |
1485 | if (mem->mem_type == TTM_PL_TT) { | |
ec681545 CK |
1486 | ttm = container_of(bo_va->base.bo->tbo.ttm, |
1487 | struct ttm_dma_tt, ttm); | |
8358dcee | 1488 | pages_addr = ttm->dma_address; |
9ab21462 | 1489 | } |
ec681545 | 1490 | exclusive = reservation_object_get_excl(bo->tbo.resv); |
d38ceaf9 AD |
1491 | } |
1492 | ||
457e0fee | 1493 | if (bo) |
ec681545 | 1494 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
457e0fee | 1495 | else |
a5f6b5b1 | 1496 | flags = 0x0; |
d38ceaf9 | 1497 | |
4e55eb38 CK |
1498 | if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) |
1499 | last_update = &vm->last_update; | |
1500 | else | |
1501 | last_update = &bo_va->last_pt_update; | |
1502 | ||
3d7d4d3a CK |
1503 | if (!clear && bo_va->base.moved) { |
1504 | bo_va->base.moved = false; | |
7fc11959 | 1505 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1506 | |
cb7b6ec2 CK |
1507 | } else if (bo_va->cleared != clear) { |
1508 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1509 | } |
7fc11959 CK |
1510 | |
1511 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
457e0fee | 1512 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
63e0ba40 | 1513 | mapping, flags, nodes, |
4e55eb38 | 1514 | last_update); |
d38ceaf9 AD |
1515 | if (r) |
1516 | return r; | |
1517 | } | |
1518 | ||
cb7b6ec2 CK |
1519 | if (vm->use_cpu_for_update) { |
1520 | /* Flush HDP */ | |
1521 | mb(); | |
69882565 | 1522 | amdgpu_asic_flush_hdp(adev, NULL); |
d6c10f6b CK |
1523 | } |
1524 | ||
d38ceaf9 | 1525 | spin_lock(&vm->status_lock); |
ec681545 | 1526 | list_del_init(&bo_va->base.vm_status); |
d38ceaf9 AD |
1527 | spin_unlock(&vm->status_lock); |
1528 | ||
cb7b6ec2 CK |
1529 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1530 | bo_va->cleared = clear; | |
1531 | ||
1532 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1533 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1534 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1535 | } |
1536 | ||
d38ceaf9 AD |
1537 | return 0; |
1538 | } | |
1539 | ||
284710fa CK |
1540 | /** |
1541 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1542 | */ | |
1543 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1544 | { | |
1545 | unsigned long flags; | |
1546 | bool enable; | |
1547 | ||
1548 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1549 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
132f34e4 | 1550 | adev->gmc.gmc_funcs->set_prt(adev, enable); |
284710fa CK |
1551 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); |
1552 | } | |
1553 | ||
451bc8eb | 1554 | /** |
4388fc2a | 1555 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1556 | */ |
1557 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1558 | { | |
132f34e4 | 1559 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1560 | return; |
1561 | ||
451bc8eb CK |
1562 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1563 | amdgpu_vm_update_prt_state(adev); | |
1564 | } | |
1565 | ||
0b15f2fc CK |
1566 | /** |
1567 | * amdgpu_vm_prt_put - drop a PRT user | |
1568 | */ | |
1569 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1570 | { | |
451bc8eb | 1571 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1572 | amdgpu_vm_update_prt_state(adev); |
1573 | } | |
1574 | ||
284710fa | 1575 | /** |
451bc8eb | 1576 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1577 | */ |
1578 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1579 | { | |
1580 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1581 | ||
0b15f2fc | 1582 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1583 | kfree(cb); |
1584 | } | |
1585 | ||
451bc8eb CK |
1586 | /** |
1587 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1588 | */ | |
1589 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1590 | struct dma_fence *fence) | |
1591 | { | |
4388fc2a | 1592 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1593 | |
132f34e4 | 1594 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1595 | return; |
1596 | ||
1597 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1598 | if (!cb) { |
1599 | /* Last resort when we are OOM */ | |
1600 | if (fence) | |
1601 | dma_fence_wait(fence, false); | |
1602 | ||
486a68f5 | 1603 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1604 | } else { |
1605 | cb->adev = adev; | |
1606 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1607 | amdgpu_vm_prt_cb)) | |
1608 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1609 | } | |
1610 | } | |
1611 | ||
284710fa CK |
1612 | /** |
1613 | * amdgpu_vm_free_mapping - free a mapping | |
1614 | * | |
1615 | * @adev: amdgpu_device pointer | |
1616 | * @vm: requested vm | |
1617 | * @mapping: mapping to be freed | |
1618 | * @fence: fence of the unmap operation | |
1619 | * | |
1620 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1621 | */ | |
1622 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1623 | struct amdgpu_vm *vm, | |
1624 | struct amdgpu_bo_va_mapping *mapping, | |
1625 | struct dma_fence *fence) | |
1626 | { | |
451bc8eb CK |
1627 | if (mapping->flags & AMDGPU_PTE_PRT) |
1628 | amdgpu_vm_add_prt_cb(adev, fence); | |
1629 | kfree(mapping); | |
1630 | } | |
284710fa | 1631 | |
451bc8eb CK |
1632 | /** |
1633 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1634 | * | |
1635 | * @adev: amdgpu_device pointer | |
1636 | * @vm: requested vm | |
1637 | * | |
1638 | * Register a cleanup callback to disable PRT support after VM dies. | |
1639 | */ | |
1640 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1641 | { | |
3f3333f8 | 1642 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
451bc8eb CK |
1643 | struct dma_fence *excl, **shared; |
1644 | unsigned i, shared_count; | |
1645 | int r; | |
0b15f2fc | 1646 | |
451bc8eb CK |
1647 | r = reservation_object_get_fences_rcu(resv, &excl, |
1648 | &shared_count, &shared); | |
1649 | if (r) { | |
1650 | /* Not enough memory to grab the fence list, as last resort | |
1651 | * block for all the fences to complete. | |
1652 | */ | |
1653 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1654 | MAX_SCHEDULE_TIMEOUT); | |
1655 | return; | |
284710fa | 1656 | } |
451bc8eb CK |
1657 | |
1658 | /* Add a callback for each fence in the reservation object */ | |
1659 | amdgpu_vm_prt_get(adev); | |
1660 | amdgpu_vm_add_prt_cb(adev, excl); | |
1661 | ||
1662 | for (i = 0; i < shared_count; ++i) { | |
1663 | amdgpu_vm_prt_get(adev); | |
1664 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1665 | } | |
1666 | ||
1667 | kfree(shared); | |
284710fa CK |
1668 | } |
1669 | ||
d38ceaf9 AD |
1670 | /** |
1671 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1672 | * | |
1673 | * @adev: amdgpu_device pointer | |
1674 | * @vm: requested vm | |
f3467818 NH |
1675 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1676 | * or if an error occurred) | |
d38ceaf9 AD |
1677 | * |
1678 | * Make sure all freed BOs are cleared in the PT. | |
1679 | * Returns 0 for success. | |
1680 | * | |
1681 | * PTs have to be reserved and mutex must be locked! | |
1682 | */ | |
1683 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1684 | struct amdgpu_vm *vm, |
1685 | struct dma_fence **fence) | |
d38ceaf9 AD |
1686 | { |
1687 | struct amdgpu_bo_va_mapping *mapping; | |
4584312d | 1688 | uint64_t init_pte_value = 0; |
f3467818 | 1689 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1690 | int r; |
1691 | ||
1692 | while (!list_empty(&vm->freed)) { | |
1693 | mapping = list_first_entry(&vm->freed, | |
1694 | struct amdgpu_bo_va_mapping, list); | |
1695 | list_del(&mapping->list); | |
e17841b9 | 1696 | |
4584312d | 1697 | if (vm->pte_support_ats && mapping->start < AMDGPU_VA_HOLE_START) |
6d16dac8 | 1698 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec | 1699 | |
570144c6 | 1700 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, |
fc6aa33d | 1701 | mapping->start, mapping->last, |
51ac7eec | 1702 | init_pte_value, 0, &f); |
f3467818 | 1703 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1704 | if (r) { |
f3467818 | 1705 | dma_fence_put(f); |
d38ceaf9 | 1706 | return r; |
284710fa | 1707 | } |
f3467818 | 1708 | } |
d38ceaf9 | 1709 | |
f3467818 NH |
1710 | if (fence && f) { |
1711 | dma_fence_put(*fence); | |
1712 | *fence = f; | |
1713 | } else { | |
1714 | dma_fence_put(f); | |
d38ceaf9 | 1715 | } |
f3467818 | 1716 | |
d38ceaf9 AD |
1717 | return 0; |
1718 | ||
1719 | } | |
1720 | ||
1721 | /** | |
73fb16e7 | 1722 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
1723 | * |
1724 | * @adev: amdgpu_device pointer | |
1725 | * @vm: requested vm | |
73fb16e7 | 1726 | * @sync: sync object to add fences to |
d38ceaf9 | 1727 | * |
73fb16e7 | 1728 | * Make sure all BOs which are moved are updated in the PTs. |
d38ceaf9 AD |
1729 | * Returns 0 for success. |
1730 | * | |
73fb16e7 | 1731 | * PTs have to be reserved! |
d38ceaf9 | 1732 | */ |
73fb16e7 | 1733 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 1734 | struct amdgpu_vm *vm) |
d38ceaf9 | 1735 | { |
73fb16e7 | 1736 | bool clear; |
91e1a520 | 1737 | int r = 0; |
d38ceaf9 AD |
1738 | |
1739 | spin_lock(&vm->status_lock); | |
27c7b9ae | 1740 | while (!list_empty(&vm->moved)) { |
4e55eb38 | 1741 | struct amdgpu_bo_va *bo_va; |
ec363e0d | 1742 | struct reservation_object *resv; |
4e55eb38 | 1743 | |
27c7b9ae | 1744 | bo_va = list_first_entry(&vm->moved, |
ec681545 | 1745 | struct amdgpu_bo_va, base.vm_status); |
d38ceaf9 | 1746 | spin_unlock(&vm->status_lock); |
32b41ac2 | 1747 | |
ec363e0d CK |
1748 | resv = bo_va->base.bo->tbo.resv; |
1749 | ||
73fb16e7 | 1750 | /* Per VM BOs never need to bo cleared in the page tables */ |
ec363e0d CK |
1751 | if (resv == vm->root.base.bo->tbo.resv) |
1752 | clear = false; | |
1753 | /* Try to reserve the BO to avoid clearing its ptes */ | |
9b8cad20 | 1754 | else if (!amdgpu_vm_debug && reservation_object_trylock(resv)) |
ec363e0d CK |
1755 | clear = false; |
1756 | /* Somebody else is using the BO right now */ | |
1757 | else | |
1758 | clear = true; | |
73fb16e7 CK |
1759 | |
1760 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
d38ceaf9 AD |
1761 | if (r) |
1762 | return r; | |
1763 | ||
ec363e0d CK |
1764 | if (!clear && resv != vm->root.base.bo->tbo.resv) |
1765 | reservation_object_unlock(resv); | |
1766 | ||
d38ceaf9 AD |
1767 | spin_lock(&vm->status_lock); |
1768 | } | |
1769 | spin_unlock(&vm->status_lock); | |
1770 | ||
91e1a520 | 1771 | return r; |
d38ceaf9 AD |
1772 | } |
1773 | ||
1774 | /** | |
1775 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1776 | * | |
1777 | * @adev: amdgpu_device pointer | |
1778 | * @vm: requested vm | |
1779 | * @bo: amdgpu buffer object | |
1780 | * | |
8843dbbb | 1781 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1782 | * Add @bo to the list of bos associated with the vm |
1783 | * Returns newly added bo_va or NULL for failure | |
1784 | * | |
1785 | * Object has to be reserved! | |
1786 | */ | |
1787 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1788 | struct amdgpu_vm *vm, | |
1789 | struct amdgpu_bo *bo) | |
1790 | { | |
1791 | struct amdgpu_bo_va *bo_va; | |
1792 | ||
1793 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1794 | if (bo_va == NULL) { | |
1795 | return NULL; | |
1796 | } | |
ec681545 CK |
1797 | bo_va->base.vm = vm; |
1798 | bo_va->base.bo = bo; | |
1799 | INIT_LIST_HEAD(&bo_va->base.bo_list); | |
1800 | INIT_LIST_HEAD(&bo_va->base.vm_status); | |
1801 | ||
d38ceaf9 | 1802 | bo_va->ref_count = 1; |
7fc11959 CK |
1803 | INIT_LIST_HEAD(&bo_va->valids); |
1804 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 1805 | |
727ffdf2 CK |
1806 | if (!bo) |
1807 | return bo_va; | |
1808 | ||
1809 | list_add_tail(&bo_va->base.bo_list, &bo->va); | |
1810 | ||
1811 | if (bo->tbo.resv != vm->root.base.bo->tbo.resv) | |
1812 | return bo_va; | |
1813 | ||
1814 | if (bo->preferred_domains & | |
1815 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)) | |
1816 | return bo_va; | |
1817 | ||
1818 | /* | |
1819 | * We checked all the prerequisites, but it looks like this per VM BO | |
1820 | * is currently evicted. add the BO to the evicted list to make sure it | |
1821 | * is validated on next VM use to avoid fault. | |
1822 | * */ | |
1823 | spin_lock(&vm->status_lock); | |
1824 | list_move_tail(&bo_va->base.vm_status, &vm->evicted); | |
1825 | spin_unlock(&vm->status_lock); | |
d38ceaf9 AD |
1826 | |
1827 | return bo_va; | |
1828 | } | |
1829 | ||
73fb16e7 CK |
1830 | |
1831 | /** | |
1832 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
1833 | * | |
1834 | * @adev: amdgpu_device pointer | |
1835 | * @bo_va: bo_va to store the address | |
1836 | * @mapping: the mapping to insert | |
1837 | * | |
1838 | * Insert a new mapping into all structures. | |
1839 | */ | |
1840 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
1841 | struct amdgpu_bo_va *bo_va, | |
1842 | struct amdgpu_bo_va_mapping *mapping) | |
1843 | { | |
1844 | struct amdgpu_vm *vm = bo_va->base.vm; | |
1845 | struct amdgpu_bo *bo = bo_va->base.bo; | |
1846 | ||
aebc5e6f | 1847 | mapping->bo_va = bo_va; |
73fb16e7 CK |
1848 | list_add(&mapping->list, &bo_va->invalids); |
1849 | amdgpu_vm_it_insert(mapping, &vm->va); | |
1850 | ||
1851 | if (mapping->flags & AMDGPU_PTE_PRT) | |
1852 | amdgpu_vm_prt_get(adev); | |
1853 | ||
1854 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { | |
1855 | spin_lock(&vm->status_lock); | |
481c2e94 CK |
1856 | if (list_empty(&bo_va->base.vm_status)) |
1857 | list_add(&bo_va->base.vm_status, &vm->moved); | |
73fb16e7 CK |
1858 | spin_unlock(&vm->status_lock); |
1859 | } | |
1860 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
1861 | } | |
1862 | ||
d38ceaf9 AD |
1863 | /** |
1864 | * amdgpu_vm_bo_map - map bo inside a vm | |
1865 | * | |
1866 | * @adev: amdgpu_device pointer | |
1867 | * @bo_va: bo_va to store the address | |
1868 | * @saddr: where to map the BO | |
1869 | * @offset: requested offset in the BO | |
1870 | * @flags: attributes of pages (read/write/valid/etc.) | |
1871 | * | |
1872 | * Add a mapping of the BO at the specefied addr into the VM. | |
1873 | * Returns 0 for success, error for failure. | |
1874 | * | |
49b02b18 | 1875 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1876 | */ |
1877 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1878 | struct amdgpu_bo_va *bo_va, | |
1879 | uint64_t saddr, uint64_t offset, | |
268c3001 | 1880 | uint64_t size, uint64_t flags) |
d38ceaf9 | 1881 | { |
a9f87f64 | 1882 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
1883 | struct amdgpu_bo *bo = bo_va->base.bo; |
1884 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1885 | uint64_t eaddr; |
d38ceaf9 | 1886 | |
0be52de9 CK |
1887 | /* validate the parameters */ |
1888 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1889 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1890 | return -EINVAL; |
0be52de9 | 1891 | |
d38ceaf9 | 1892 | /* make sure object fit at this offset */ |
005ae95e | 1893 | eaddr = saddr + size - 1; |
a5f6b5b1 | 1894 | if (saddr >= eaddr || |
ec681545 | 1895 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 1896 | return -EINVAL; |
d38ceaf9 | 1897 | |
d38ceaf9 AD |
1898 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1899 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1900 | ||
a9f87f64 CK |
1901 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
1902 | if (tmp) { | |
d38ceaf9 AD |
1903 | /* bo and tmp overlap, invalid addr */ |
1904 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 1905 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 1906 | tmp->start, tmp->last + 1); |
663e4577 | 1907 | return -EINVAL; |
d38ceaf9 AD |
1908 | } |
1909 | ||
1910 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
1911 | if (!mapping) |
1912 | return -ENOMEM; | |
d38ceaf9 | 1913 | |
a9f87f64 CK |
1914 | mapping->start = saddr; |
1915 | mapping->last = eaddr; | |
d38ceaf9 AD |
1916 | mapping->offset = offset; |
1917 | mapping->flags = flags; | |
1918 | ||
73fb16e7 | 1919 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
1920 | |
1921 | return 0; | |
1922 | } | |
1923 | ||
1924 | /** | |
1925 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
1926 | * | |
1927 | * @adev: amdgpu_device pointer | |
1928 | * @bo_va: bo_va to store the address | |
1929 | * @saddr: where to map the BO | |
1930 | * @offset: requested offset in the BO | |
1931 | * @flags: attributes of pages (read/write/valid/etc.) | |
1932 | * | |
1933 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
1934 | * mappings as we do so. | |
1935 | * Returns 0 for success, error for failure. | |
1936 | * | |
1937 | * Object has to be reserved and unreserved outside! | |
1938 | */ | |
1939 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
1940 | struct amdgpu_bo_va *bo_va, | |
1941 | uint64_t saddr, uint64_t offset, | |
1942 | uint64_t size, uint64_t flags) | |
1943 | { | |
1944 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 1945 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
1946 | uint64_t eaddr; |
1947 | int r; | |
1948 | ||
1949 | /* validate the parameters */ | |
1950 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
1951 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
1952 | return -EINVAL; | |
1953 | ||
1954 | /* make sure object fit at this offset */ | |
1955 | eaddr = saddr + size - 1; | |
1956 | if (saddr >= eaddr || | |
ec681545 | 1957 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
1958 | return -EINVAL; |
1959 | ||
1960 | /* Allocate all the needed memory */ | |
1961 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1962 | if (!mapping) | |
1963 | return -ENOMEM; | |
1964 | ||
ec681545 | 1965 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
1966 | if (r) { |
1967 | kfree(mapping); | |
1968 | return r; | |
1969 | } | |
1970 | ||
1971 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
1972 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1973 | ||
a9f87f64 CK |
1974 | mapping->start = saddr; |
1975 | mapping->last = eaddr; | |
80f95c57 CK |
1976 | mapping->offset = offset; |
1977 | mapping->flags = flags; | |
1978 | ||
73fb16e7 | 1979 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 1980 | |
d38ceaf9 | 1981 | return 0; |
d38ceaf9 AD |
1982 | } |
1983 | ||
1984 | /** | |
1985 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1986 | * | |
1987 | * @adev: amdgpu_device pointer | |
1988 | * @bo_va: bo_va to remove the address from | |
1989 | * @saddr: where to the BO is mapped | |
1990 | * | |
1991 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1992 | * Returns 0 for success, error for failure. | |
1993 | * | |
49b02b18 | 1994 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1995 | */ |
1996 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1997 | struct amdgpu_bo_va *bo_va, | |
1998 | uint64_t saddr) | |
1999 | { | |
2000 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2001 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2002 | bool valid = true; |
d38ceaf9 | 2003 | |
6c7fc503 | 2004 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2005 | |
7fc11959 | 2006 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2007 | if (mapping->start == saddr) |
d38ceaf9 AD |
2008 | break; |
2009 | } | |
2010 | ||
7fc11959 CK |
2011 | if (&mapping->list == &bo_va->valids) { |
2012 | valid = false; | |
2013 | ||
2014 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2015 | if (mapping->start == saddr) |
7fc11959 CK |
2016 | break; |
2017 | } | |
2018 | ||
32b41ac2 | 2019 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2020 | return -ENOENT; |
d38ceaf9 | 2021 | } |
32b41ac2 | 2022 | |
d38ceaf9 | 2023 | list_del(&mapping->list); |
a9f87f64 | 2024 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2025 | mapping->bo_va = NULL; |
93e3e438 | 2026 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2027 | |
e17841b9 | 2028 | if (valid) |
d38ceaf9 | 2029 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2030 | else |
284710fa CK |
2031 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2032 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2033 | |
2034 | return 0; | |
2035 | } | |
2036 | ||
dc54d3d1 CK |
2037 | /** |
2038 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2039 | * | |
2040 | * @adev: amdgpu_device pointer | |
2041 | * @vm: VM structure to use | |
2042 | * @saddr: start of the range | |
2043 | * @size: size of the range | |
2044 | * | |
2045 | * Remove all mappings in a range, split them as appropriate. | |
2046 | * Returns 0 for success, error for failure. | |
2047 | */ | |
2048 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2049 | struct amdgpu_vm *vm, | |
2050 | uint64_t saddr, uint64_t size) | |
2051 | { | |
2052 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2053 | LIST_HEAD(removed); |
2054 | uint64_t eaddr; | |
2055 | ||
2056 | eaddr = saddr + size - 1; | |
2057 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2058 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2059 | ||
2060 | /* Allocate all the needed memory */ | |
2061 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2062 | if (!before) | |
2063 | return -ENOMEM; | |
27f6d610 | 2064 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2065 | |
2066 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2067 | if (!after) { | |
2068 | kfree(before); | |
2069 | return -ENOMEM; | |
2070 | } | |
27f6d610 | 2071 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2072 | |
2073 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2074 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2075 | while (tmp) { | |
dc54d3d1 | 2076 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2077 | if (tmp->start < saddr) { |
2078 | before->start = tmp->start; | |
2079 | before->last = saddr - 1; | |
dc54d3d1 CK |
2080 | before->offset = tmp->offset; |
2081 | before->flags = tmp->flags; | |
2082 | list_add(&before->list, &tmp->list); | |
2083 | } | |
2084 | ||
2085 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2086 | if (tmp->last > eaddr) { |
2087 | after->start = eaddr + 1; | |
2088 | after->last = tmp->last; | |
dc54d3d1 | 2089 | after->offset = tmp->offset; |
a9f87f64 | 2090 | after->offset += after->start - tmp->start; |
dc54d3d1 CK |
2091 | after->flags = tmp->flags; |
2092 | list_add(&after->list, &tmp->list); | |
2093 | } | |
2094 | ||
2095 | list_del(&tmp->list); | |
2096 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2097 | |
2098 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2099 | } |
2100 | ||
2101 | /* And free them up */ | |
2102 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2103 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2104 | list_del(&tmp->list); |
2105 | ||
a9f87f64 CK |
2106 | if (tmp->start < saddr) |
2107 | tmp->start = saddr; | |
2108 | if (tmp->last > eaddr) | |
2109 | tmp->last = eaddr; | |
dc54d3d1 | 2110 | |
aebc5e6f | 2111 | tmp->bo_va = NULL; |
dc54d3d1 CK |
2112 | list_add(&tmp->list, &vm->freed); |
2113 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2114 | } | |
2115 | ||
27f6d610 JZ |
2116 | /* Insert partial mapping before the range */ |
2117 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2118 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2119 | if (before->flags & AMDGPU_PTE_PRT) |
2120 | amdgpu_vm_prt_get(adev); | |
2121 | } else { | |
2122 | kfree(before); | |
2123 | } | |
2124 | ||
2125 | /* Insert partial mapping after the range */ | |
27f6d610 | 2126 | if (!list_empty(&after->list)) { |
a9f87f64 | 2127 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2128 | if (after->flags & AMDGPU_PTE_PRT) |
2129 | amdgpu_vm_prt_get(adev); | |
2130 | } else { | |
2131 | kfree(after); | |
2132 | } | |
2133 | ||
2134 | return 0; | |
2135 | } | |
2136 | ||
aebc5e6f CK |
2137 | /** |
2138 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2139 | * | |
2140 | * @vm: the requested VM | |
2141 | * | |
2142 | * Find a mapping by it's address. | |
2143 | */ | |
2144 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2145 | uint64_t addr) | |
2146 | { | |
2147 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2148 | } | |
2149 | ||
d38ceaf9 AD |
2150 | /** |
2151 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2152 | * | |
2153 | * @adev: amdgpu_device pointer | |
2154 | * @bo_va: requested bo_va | |
2155 | * | |
8843dbbb | 2156 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2157 | * |
2158 | * Object have to be reserved! | |
2159 | */ | |
2160 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2161 | struct amdgpu_bo_va *bo_va) | |
2162 | { | |
2163 | struct amdgpu_bo_va_mapping *mapping, *next; | |
ec681545 | 2164 | struct amdgpu_vm *vm = bo_va->base.vm; |
d38ceaf9 | 2165 | |
ec681545 | 2166 | list_del(&bo_va->base.bo_list); |
d38ceaf9 | 2167 | |
d38ceaf9 | 2168 | spin_lock(&vm->status_lock); |
ec681545 | 2169 | list_del(&bo_va->base.vm_status); |
d38ceaf9 AD |
2170 | spin_unlock(&vm->status_lock); |
2171 | ||
7fc11959 | 2172 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2173 | list_del(&mapping->list); |
a9f87f64 | 2174 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2175 | mapping->bo_va = NULL; |
93e3e438 | 2176 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2177 | list_add(&mapping->list, &vm->freed); |
2178 | } | |
2179 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2180 | list_del(&mapping->list); | |
a9f87f64 | 2181 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2182 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2183 | bo_va->last_pt_update); | |
d38ceaf9 | 2184 | } |
32b41ac2 | 2185 | |
f54d1867 | 2186 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2187 | kfree(bo_va); |
d38ceaf9 AD |
2188 | } |
2189 | ||
2190 | /** | |
2191 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2192 | * | |
2193 | * @adev: amdgpu_device pointer | |
2194 | * @vm: requested vm | |
2195 | * @bo: amdgpu buffer object | |
2196 | * | |
8843dbbb | 2197 | * Mark @bo as invalid. |
d38ceaf9 AD |
2198 | */ |
2199 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2200 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2201 | { |
ec681545 CK |
2202 | struct amdgpu_vm_bo_base *bo_base; |
2203 | ||
2204 | list_for_each_entry(bo_base, &bo->va, bo_list) { | |
3f3333f8 CK |
2205 | struct amdgpu_vm *vm = bo_base->vm; |
2206 | ||
3d7d4d3a | 2207 | bo_base->moved = true; |
3f3333f8 CK |
2208 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
2209 | spin_lock(&bo_base->vm->status_lock); | |
73fb16e7 CK |
2210 | if (bo->tbo.type == ttm_bo_type_kernel) |
2211 | list_move(&bo_base->vm_status, &vm->evicted); | |
2212 | else | |
2213 | list_move_tail(&bo_base->vm_status, | |
2214 | &vm->evicted); | |
3f3333f8 CK |
2215 | spin_unlock(&bo_base->vm->status_lock); |
2216 | continue; | |
2217 | } | |
2218 | ||
ea09729c CK |
2219 | if (bo->tbo.type == ttm_bo_type_kernel) { |
2220 | spin_lock(&bo_base->vm->status_lock); | |
2221 | if (list_empty(&bo_base->vm_status)) | |
2222 | list_add(&bo_base->vm_status, &vm->relocated); | |
2223 | spin_unlock(&bo_base->vm->status_lock); | |
3f3333f8 | 2224 | continue; |
ea09729c | 2225 | } |
3f3333f8 | 2226 | |
ec681545 CK |
2227 | spin_lock(&bo_base->vm->status_lock); |
2228 | if (list_empty(&bo_base->vm_status)) | |
481c2e94 | 2229 | list_add(&bo_base->vm_status, &vm->moved); |
ec681545 | 2230 | spin_unlock(&bo_base->vm->status_lock); |
d38ceaf9 AD |
2231 | } |
2232 | } | |
2233 | ||
bab4fee7 JZ |
2234 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2235 | { | |
2236 | /* Total bits covered by PD + PTs */ | |
2237 | unsigned bits = ilog2(vm_size) + 18; | |
2238 | ||
2239 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2240 | Above that split equal between PD and PTs */ | |
2241 | if (vm_size <= 8) | |
2242 | return (bits - 9); | |
2243 | else | |
2244 | return ((bits + 3) / 2); | |
2245 | } | |
2246 | ||
d07f14be RH |
2247 | /** |
2248 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2249 | * |
2250 | * @adev: amdgpu_device pointer | |
2251 | * @vm_size: the default vm size if it's set auto | |
2252 | */ | |
fdd5faaa | 2253 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, |
f3368128 CK |
2254 | uint32_t fragment_size_default, unsigned max_level, |
2255 | unsigned max_bits) | |
bab4fee7 | 2256 | { |
36539dce CK |
2257 | uint64_t tmp; |
2258 | ||
2259 | /* adjust vm size first */ | |
f3368128 CK |
2260 | if (amdgpu_vm_size != -1) { |
2261 | unsigned max_size = 1 << (max_bits - 30); | |
2262 | ||
fdd5faaa | 2263 | vm_size = amdgpu_vm_size; |
f3368128 CK |
2264 | if (vm_size > max_size) { |
2265 | dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", | |
2266 | amdgpu_vm_size, max_size); | |
2267 | vm_size = max_size; | |
2268 | } | |
2269 | } | |
fdd5faaa CK |
2270 | |
2271 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
36539dce CK |
2272 | |
2273 | tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); | |
97489129 CK |
2274 | if (amdgpu_vm_block_size != -1) |
2275 | tmp >>= amdgpu_vm_block_size - 9; | |
36539dce CK |
2276 | tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; |
2277 | adev->vm_manager.num_level = min(max_level, (unsigned)tmp); | |
196f7489 CZ |
2278 | switch (adev->vm_manager.num_level) { |
2279 | case 3: | |
2280 | adev->vm_manager.root_level = AMDGPU_VM_PDB2; | |
2281 | break; | |
2282 | case 2: | |
2283 | adev->vm_manager.root_level = AMDGPU_VM_PDB1; | |
2284 | break; | |
2285 | case 1: | |
2286 | adev->vm_manager.root_level = AMDGPU_VM_PDB0; | |
2287 | break; | |
2288 | default: | |
2289 | dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n"); | |
2290 | } | |
b38f41eb | 2291 | /* block size depends on vm size and hw setup*/ |
97489129 | 2292 | if (amdgpu_vm_block_size != -1) |
bab4fee7 | 2293 | adev->vm_manager.block_size = |
97489129 CK |
2294 | min((unsigned)amdgpu_vm_block_size, max_bits |
2295 | - AMDGPU_GPU_PAGE_SHIFT | |
2296 | - 9 * adev->vm_manager.num_level); | |
2297 | else if (adev->vm_manager.num_level > 1) | |
2298 | adev->vm_manager.block_size = 9; | |
bab4fee7 | 2299 | else |
97489129 | 2300 | adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); |
bab4fee7 | 2301 | |
b38f41eb CK |
2302 | if (amdgpu_vm_fragment_size == -1) |
2303 | adev->vm_manager.fragment_size = fragment_size_default; | |
2304 | else | |
2305 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
d07f14be | 2306 | |
36539dce CK |
2307 | DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", |
2308 | vm_size, adev->vm_manager.num_level + 1, | |
2309 | adev->vm_manager.block_size, | |
fdd5faaa | 2310 | adev->vm_manager.fragment_size); |
bab4fee7 JZ |
2311 | } |
2312 | ||
d38ceaf9 AD |
2313 | /** |
2314 | * amdgpu_vm_init - initialize a vm instance | |
2315 | * | |
2316 | * @adev: amdgpu_device pointer | |
2317 | * @vm: requested vm | |
9a4b7d4c | 2318 | * @vm_context: Indicates if it GFX or Compute context |
d38ceaf9 | 2319 | * |
8843dbbb | 2320 | * Init @vm fields. |
d38ceaf9 | 2321 | */ |
9a4b7d4c | 2322 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 2323 | int vm_context, unsigned int pasid) |
d38ceaf9 AD |
2324 | { |
2325 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
36b32a68 | 2326 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2327 | unsigned ring_instance; |
2328 | struct amdgpu_ring *ring; | |
1b1f42d8 | 2329 | struct drm_sched_rq *rq; |
d3aab672 | 2330 | unsigned long size; |
13307f7e | 2331 | uint64_t flags; |
36bbf3bf | 2332 | int r, i; |
d38ceaf9 | 2333 | |
f808c13f | 2334 | vm->va = RB_ROOT_CACHED; |
36bbf3bf CZ |
2335 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2336 | vm->reserved_vmid[i] = NULL; | |
d38ceaf9 | 2337 | spin_lock_init(&vm->status_lock); |
3f3333f8 | 2338 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2339 | INIT_LIST_HEAD(&vm->relocated); |
27c7b9ae | 2340 | INIT_LIST_HEAD(&vm->moved); |
d38ceaf9 | 2341 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2342 | |
2bd9ccfa | 2343 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2344 | |
2345 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2346 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2347 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
1b1f42d8 LS |
2348 | rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL]; |
2349 | r = drm_sched_entity_init(&ring->sched, &vm->entity, | |
b3eebe3d | 2350 | rq, amdgpu_sched_jobs, NULL); |
2bd9ccfa | 2351 | if (r) |
f566ceb1 | 2352 | return r; |
2bd9ccfa | 2353 | |
51ac7eec YZ |
2354 | vm->pte_support_ats = false; |
2355 | ||
2356 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2357 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2358 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec | 2359 | |
13307f7e | 2360 | if (adev->asic_type == CHIP_RAVEN) |
51ac7eec | 2361 | vm->pte_support_ats = true; |
13307f7e | 2362 | } else { |
9a4b7d4c HK |
2363 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2364 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
13307f7e | 2365 | } |
9a4b7d4c HK |
2366 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2367 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
2368 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), | |
2369 | "CPU update of VM recommended only for large BAR system\n"); | |
d5884513 | 2370 | vm->last_update = NULL; |
05906dec | 2371 | |
13307f7e | 2372 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; |
3c824172 HK |
2373 | if (vm->use_cpu_for_update) |
2374 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
2375 | else | |
2376 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
2377 | AMDGPU_GEM_CREATE_SHADOW); | |
2378 | ||
d3aab672 CK |
2379 | size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level); |
2380 | r = amdgpu_bo_create(adev, size, align, true, AMDGPU_GEM_DOMAIN_VRAM, | |
8febe617 | 2381 | flags, NULL, NULL, &vm->root.base.bo); |
d38ceaf9 | 2382 | if (r) |
2bd9ccfa CK |
2383 | goto error_free_sched_entity; |
2384 | ||
d3aab672 CK |
2385 | r = amdgpu_bo_reserve(vm->root.base.bo, true); |
2386 | if (r) | |
2387 | goto error_free_root; | |
2388 | ||
13307f7e | 2389 | r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, |
4584312d CK |
2390 | adev->vm_manager.root_level, |
2391 | vm->pte_support_ats); | |
13307f7e CK |
2392 | if (r) |
2393 | goto error_unreserve; | |
2394 | ||
3f3333f8 CK |
2395 | vm->root.base.vm = vm; |
2396 | list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va); | |
d3aab672 CK |
2397 | list_add_tail(&vm->root.base.vm_status, &vm->evicted); |
2398 | amdgpu_bo_unreserve(vm->root.base.bo); | |
d38ceaf9 | 2399 | |
02208441 FK |
2400 | if (pasid) { |
2401 | unsigned long flags; | |
2402 | ||
2403 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2404 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2405 | GFP_ATOMIC); | |
2406 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2407 | if (r < 0) | |
2408 | goto error_free_root; | |
2409 | ||
2410 | vm->pasid = pasid; | |
0a096fb6 CK |
2411 | } |
2412 | ||
a2f14820 | 2413 | INIT_KFIFO(vm->faults); |
c98171cc | 2414 | vm->fault_credit = 16; |
d38ceaf9 AD |
2415 | |
2416 | return 0; | |
2bd9ccfa | 2417 | |
13307f7e CK |
2418 | error_unreserve: |
2419 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2420 | ||
67003a15 | 2421 | error_free_root: |
3f3333f8 CK |
2422 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2423 | amdgpu_bo_unref(&vm->root.base.bo); | |
2424 | vm->root.base.bo = NULL; | |
2bd9ccfa CK |
2425 | |
2426 | error_free_sched_entity: | |
1b1f42d8 | 2427 | drm_sched_entity_fini(&ring->sched, &vm->entity); |
2bd9ccfa CK |
2428 | |
2429 | return r; | |
d38ceaf9 AD |
2430 | } |
2431 | ||
f566ceb1 CK |
2432 | /** |
2433 | * amdgpu_vm_free_levels - free PD/PT levels | |
2434 | * | |
8f19cd78 CK |
2435 | * @adev: amdgpu device structure |
2436 | * @parent: PD/PT starting level to free | |
2437 | * @level: level of parent structure | |
f566ceb1 CK |
2438 | * |
2439 | * Free the page directory or page table level and all sub levels. | |
2440 | */ | |
8f19cd78 CK |
2441 | static void amdgpu_vm_free_levels(struct amdgpu_device *adev, |
2442 | struct amdgpu_vm_pt *parent, | |
2443 | unsigned level) | |
f566ceb1 | 2444 | { |
8f19cd78 | 2445 | unsigned i, num_entries = amdgpu_vm_num_entries(adev, level); |
f566ceb1 | 2446 | |
8f19cd78 CK |
2447 | if (parent->base.bo) { |
2448 | list_del(&parent->base.bo_list); | |
2449 | list_del(&parent->base.vm_status); | |
2450 | amdgpu_bo_unref(&parent->base.bo->shadow); | |
2451 | amdgpu_bo_unref(&parent->base.bo); | |
f566ceb1 CK |
2452 | } |
2453 | ||
8f19cd78 CK |
2454 | if (parent->entries) |
2455 | for (i = 0; i < num_entries; i++) | |
2456 | amdgpu_vm_free_levels(adev, &parent->entries[i], | |
2457 | level + 1); | |
f566ceb1 | 2458 | |
8f19cd78 | 2459 | kvfree(parent->entries); |
f566ceb1 CK |
2460 | } |
2461 | ||
d38ceaf9 AD |
2462 | /** |
2463 | * amdgpu_vm_fini - tear down a vm instance | |
2464 | * | |
2465 | * @adev: amdgpu_device pointer | |
2466 | * @vm: requested vm | |
2467 | * | |
8843dbbb | 2468 | * Tear down @vm. |
d38ceaf9 AD |
2469 | * Unbind the VM and remove all bos from the vm bo list |
2470 | */ | |
2471 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2472 | { | |
2473 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
132f34e4 | 2474 | bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt; |
2642cf11 | 2475 | struct amdgpu_bo *root; |
a2f14820 | 2476 | u64 fault; |
2642cf11 | 2477 | int i, r; |
d38ceaf9 | 2478 | |
a2f14820 FK |
2479 | /* Clear pending page faults from IH when the VM is destroyed */ |
2480 | while (kfifo_get(&vm->faults, &fault)) | |
2481 | amdgpu_ih_clear_fault(adev, fault); | |
2482 | ||
02208441 FK |
2483 | if (vm->pasid) { |
2484 | unsigned long flags; | |
2485 | ||
2486 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2487 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2488 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2489 | } | |
2490 | ||
1b1f42d8 | 2491 | drm_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 2492 | |
f808c13f | 2493 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
d38ceaf9 AD |
2494 | dev_err(adev->dev, "still active bo inside vm\n"); |
2495 | } | |
f808c13f DB |
2496 | rbtree_postorder_for_each_entry_safe(mapping, tmp, |
2497 | &vm->va.rb_root, rb) { | |
d38ceaf9 | 2498 | list_del(&mapping->list); |
a9f87f64 | 2499 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2500 | kfree(mapping); |
2501 | } | |
2502 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2503 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2504 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2505 | prt_fini_needed = false; |
451bc8eb | 2506 | } |
284710fa | 2507 | |
d38ceaf9 | 2508 | list_del(&mapping->list); |
451bc8eb | 2509 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2510 | } |
2511 | ||
2642cf11 CK |
2512 | root = amdgpu_bo_ref(vm->root.base.bo); |
2513 | r = amdgpu_bo_reserve(root, true); | |
2514 | if (r) { | |
2515 | dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); | |
2516 | } else { | |
196f7489 CZ |
2517 | amdgpu_vm_free_levels(adev, &vm->root, |
2518 | adev->vm_manager.root_level); | |
2642cf11 CK |
2519 | amdgpu_bo_unreserve(root); |
2520 | } | |
2521 | amdgpu_bo_unref(&root); | |
d5884513 | 2522 | dma_fence_put(vm->last_update); |
1e9ef26f | 2523 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
620f774f | 2524 | amdgpu_vmid_free_reserved(adev, vm, i); |
d38ceaf9 | 2525 | } |
ea89f8c9 | 2526 | |
c98171cc FK |
2527 | /** |
2528 | * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID | |
2529 | * | |
2530 | * @adev: amdgpu_device pointer | |
2531 | * @pasid: PASID do identify the VM | |
2532 | * | |
2533 | * This function is expected to be called in interrupt context. Returns | |
2534 | * true if there was fault credit, false otherwise | |
2535 | */ | |
2536 | bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, | |
2537 | unsigned int pasid) | |
2538 | { | |
2539 | struct amdgpu_vm *vm; | |
2540 | ||
2541 | spin_lock(&adev->vm_manager.pasid_lock); | |
2542 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
d958939a | 2543 | if (!vm) { |
c98171cc | 2544 | /* VM not found, can't track fault credit */ |
d958939a | 2545 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc | 2546 | return true; |
d958939a | 2547 | } |
c98171cc FK |
2548 | |
2549 | /* No lock needed. only accessed by IRQ handler */ | |
d958939a | 2550 | if (!vm->fault_credit) { |
c98171cc | 2551 | /* Too many faults in this VM */ |
d958939a | 2552 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc | 2553 | return false; |
d958939a | 2554 | } |
c98171cc FK |
2555 | |
2556 | vm->fault_credit--; | |
d958939a | 2557 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc FK |
2558 | return true; |
2559 | } | |
2560 | ||
a9a78b32 CK |
2561 | /** |
2562 | * amdgpu_vm_manager_init - init the VM manager | |
2563 | * | |
2564 | * @adev: amdgpu_device pointer | |
2565 | * | |
2566 | * Initialize the VM manager structures | |
2567 | */ | |
2568 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2569 | { | |
620f774f | 2570 | unsigned i; |
a9a78b32 | 2571 | |
620f774f | 2572 | amdgpu_vmid_mgr_init(adev); |
2d55e45a | 2573 | |
f54d1867 CW |
2574 | adev->vm_manager.fence_context = |
2575 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2576 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2577 | adev->vm_manager.seqno[i] = 0; | |
2578 | ||
2d55e45a | 2579 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
284710fa | 2580 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2581 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
2582 | |
2583 | /* If not overridden by the user, by default, only in large BAR systems | |
2584 | * Compute VM tables will be updated by CPU | |
2585 | */ | |
2586 | #ifdef CONFIG_X86_64 | |
2587 | if (amdgpu_vm_update_mode == -1) { | |
2588 | if (amdgpu_vm_is_large_bar(adev)) | |
2589 | adev->vm_manager.vm_update_mode = | |
2590 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
2591 | else | |
2592 | adev->vm_manager.vm_update_mode = 0; | |
2593 | } else | |
2594 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
2595 | #else | |
2596 | adev->vm_manager.vm_update_mode = 0; | |
2597 | #endif | |
2598 | ||
02208441 FK |
2599 | idr_init(&adev->vm_manager.pasid_idr); |
2600 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
a9a78b32 CK |
2601 | } |
2602 | ||
ea89f8c9 CK |
2603 | /** |
2604 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2605 | * | |
2606 | * @adev: amdgpu_device pointer | |
2607 | * | |
2608 | * Cleanup the VM manager and free resources. | |
2609 | */ | |
2610 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2611 | { | |
02208441 FK |
2612 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); |
2613 | idr_destroy(&adev->vm_manager.pasid_idr); | |
2614 | ||
620f774f | 2615 | amdgpu_vmid_mgr_fini(adev); |
ea89f8c9 | 2616 | } |
cfbcacf4 CZ |
2617 | |
2618 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
2619 | { | |
2620 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
2621 | struct amdgpu_device *adev = dev->dev_private; |
2622 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
2623 | int r; | |
cfbcacf4 CZ |
2624 | |
2625 | switch (args->in.op) { | |
2626 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f | 2627 | /* current, we only have requirement to reserve vmid from gfxhub */ |
620f774f | 2628 | r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
1e9ef26f CZ |
2629 | if (r) |
2630 | return r; | |
2631 | break; | |
cfbcacf4 | 2632 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
620f774f | 2633 | amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
2634 | break; |
2635 | default: | |
2636 | return -EINVAL; | |
2637 | } | |
2638 | ||
2639 | return 0; | |
2640 | } |