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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
1fbb2e92 | 28 | #include <linux/fence-array.h> |
d38ceaf9 AD |
29 | #include <drm/drmP.h> |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu.h" | |
32 | #include "amdgpu_trace.h" | |
33 | ||
34 | /* | |
35 | * GPUVM | |
36 | * GPUVM is similar to the legacy gart on older asics, however | |
37 | * rather than there being a single global gart table | |
38 | * for the entire GPU, there are multiple VM page tables active | |
39 | * at any given time. The VM page tables can contain a mix | |
40 | * vram pages and system memory pages and system memory pages | |
41 | * can be mapped as snooped (cached system pages) or unsnooped | |
42 | * (uncached system pages). | |
43 | * Each VM has an ID associated with it and there is a page table | |
44 | * associated with each VMID. When execting a command buffer, | |
45 | * the kernel tells the the ring what VMID to use for that command | |
46 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
47 | * The userspace drivers maintain their own address space and the kernel | |
48 | * sets up their pages tables accordingly when they submit their | |
49 | * command buffers and a VMID is assigned. | |
50 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
51 | * SI supports 16. | |
52 | */ | |
53 | ||
4ff37a83 CK |
54 | /* Special value that no flush is necessary */ |
55 | #define AMDGPU_VM_NO_FLUSH (~0ll) | |
56 | ||
f4833c4f HK |
57 | /* Local structure. Encapsulate some VM table update parameters to reduce |
58 | * the number of function parameters | |
59 | */ | |
60 | struct amdgpu_vm_update_params { | |
61 | /* address where to copy page table entries from */ | |
62 | uint64_t src; | |
63 | /* DMA addresses to use for mapping */ | |
64 | dma_addr_t *pages_addr; | |
65 | /* indirect buffer to fill with commands */ | |
66 | struct amdgpu_ib *ib; | |
67 | }; | |
68 | ||
d38ceaf9 AD |
69 | /** |
70 | * amdgpu_vm_num_pde - return the number of page directory entries | |
71 | * | |
72 | * @adev: amdgpu_device pointer | |
73 | * | |
8843dbbb | 74 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
75 | */ |
76 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
77 | { | |
78 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
79 | } | |
80 | ||
81 | /** | |
82 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
83 | * | |
84 | * @adev: amdgpu_device pointer | |
85 | * | |
8843dbbb | 86 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
87 | */ |
88 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
89 | { | |
90 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
91 | } | |
92 | ||
93 | /** | |
56467ebf | 94 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
95 | * |
96 | * @vm: vm providing the BOs | |
3c0eea6c | 97 | * @validated: head of validation list |
56467ebf | 98 | * @entry: entry to add |
d38ceaf9 AD |
99 | * |
100 | * Add the page directory to the list of BOs to | |
56467ebf | 101 | * validate for command submission. |
d38ceaf9 | 102 | */ |
56467ebf CK |
103 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
104 | struct list_head *validated, | |
105 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 106 | { |
56467ebf | 107 | entry->robj = vm->page_directory; |
56467ebf CK |
108 | entry->priority = 0; |
109 | entry->tv.bo = &vm->page_directory->tbo; | |
110 | entry->tv.shared = true; | |
2f568dbd | 111 | entry->user_pages = NULL; |
56467ebf CK |
112 | list_add(&entry->tv.head, validated); |
113 | } | |
d38ceaf9 | 114 | |
56467ebf | 115 | /** |
ee1782c3 | 116 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf | 117 | * |
5a712a87 | 118 | * @adev: amdgpu device pointer |
56467ebf | 119 | * @vm: vm providing the BOs |
3c0eea6c | 120 | * @duplicates: head of duplicates list |
d38ceaf9 | 121 | * |
ee1782c3 CK |
122 | * Add the page directory to the BO duplicates list |
123 | * for command submission. | |
d38ceaf9 | 124 | */ |
5a712a87 CK |
125 | void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
126 | struct list_head *duplicates) | |
d38ceaf9 | 127 | { |
5a712a87 | 128 | uint64_t num_evictions; |
ee1782c3 | 129 | unsigned i; |
d38ceaf9 | 130 | |
5a712a87 CK |
131 | /* We only need to validate the page tables |
132 | * if they aren't already valid. | |
133 | */ | |
134 | num_evictions = atomic64_read(&adev->num_evictions); | |
135 | if (num_evictions == vm->last_eviction_counter) | |
136 | return; | |
137 | ||
d38ceaf9 | 138 | /* add the vm page table to the list */ |
ee1782c3 CK |
139 | for (i = 0; i <= vm->max_pde_used; ++i) { |
140 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
141 | ||
142 | if (!entry->robj) | |
d38ceaf9 AD |
143 | continue; |
144 | ||
ee1782c3 | 145 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 146 | } |
eceb8a15 CK |
147 | |
148 | } | |
149 | ||
150 | /** | |
151 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
152 | * | |
153 | * @adev: amdgpu device instance | |
154 | * @vm: vm providing the BOs | |
155 | * | |
156 | * Move the PT BOs to the tail of the LRU. | |
157 | */ | |
158 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
159 | struct amdgpu_vm *vm) | |
160 | { | |
161 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
162 | unsigned i; | |
163 | ||
164 | spin_lock(&glob->lru_lock); | |
165 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
166 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
167 | ||
168 | if (!entry->robj) | |
169 | continue; | |
170 | ||
171 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
172 | } | |
173 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
174 | } |
175 | ||
176 | /** | |
177 | * amdgpu_vm_grab_id - allocate the next free VMID | |
178 | * | |
d38ceaf9 | 179 | * @vm: vm to allocate id for |
7f8a5290 CK |
180 | * @ring: ring we want to submit job to |
181 | * @sync: sync object where we add dependencies | |
94dd0a4a | 182 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 183 | * |
7f8a5290 | 184 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 185 | */ |
7f8a5290 | 186 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 CK |
187 | struct amdgpu_sync *sync, struct fence *fence, |
188 | unsigned *vm_id, uint64_t *vm_pd_addr) | |
d38ceaf9 | 189 | { |
d38ceaf9 | 190 | struct amdgpu_device *adev = ring->adev; |
4ff37a83 | 191 | struct fence *updates = sync->last_vm_update; |
8d76001e | 192 | struct amdgpu_vm_id *id, *idle; |
1fbb2e92 CK |
193 | struct fence **fences; |
194 | unsigned i; | |
195 | int r = 0; | |
196 | ||
197 | fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids, | |
198 | GFP_KERNEL); | |
199 | if (!fences) | |
200 | return -ENOMEM; | |
d38ceaf9 | 201 | |
94dd0a4a CK |
202 | mutex_lock(&adev->vm_manager.lock); |
203 | ||
36fd7c5c | 204 | /* Check if we have an idle VMID */ |
1fbb2e92 | 205 | i = 0; |
8d76001e | 206 | list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) { |
1fbb2e92 CK |
207 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
208 | if (!fences[i]) | |
36fd7c5c | 209 | break; |
1fbb2e92 | 210 | ++i; |
36fd7c5c CK |
211 | } |
212 | ||
1fbb2e92 | 213 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
8d76001e | 214 | if (&idle->list == &adev->vm_manager.ids_lru) { |
1fbb2e92 CK |
215 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
216 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
217 | struct fence_array *array; | |
218 | unsigned j; | |
219 | ||
220 | for (j = 0; j < i; ++j) | |
221 | fence_get(fences[j]); | |
222 | ||
223 | array = fence_array_create(i, fences, fence_context, | |
224 | seqno, true); | |
225 | if (!array) { | |
226 | for (j = 0; j < i; ++j) | |
227 | fence_put(fences[j]); | |
228 | kfree(fences); | |
229 | r = -ENOMEM; | |
230 | goto error; | |
231 | } | |
232 | ||
233 | ||
234 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
235 | fence_put(&array->base); | |
236 | if (r) | |
237 | goto error; | |
238 | ||
239 | mutex_unlock(&adev->vm_manager.lock); | |
240 | return 0; | |
241 | ||
242 | } | |
243 | kfree(fences); | |
244 | ||
245 | /* Check if we can use a VMID already assigned to this VM */ | |
246 | i = ring->idx; | |
247 | do { | |
248 | struct fence *flushed; | |
3dab83be | 249 | bool same_ring = ring->idx == i; |
1fbb2e92 CK |
250 | |
251 | id = vm->ids[i++]; | |
252 | if (i == AMDGPU_MAX_RINGS) | |
253 | i = 0; | |
8d76001e | 254 | |
1fbb2e92 CK |
255 | /* Check all the prerequisites to using this VMID */ |
256 | if (!id) | |
257 | continue; | |
6adb0513 CZ |
258 | if (id->current_gpu_reset_count != atomic_read(&adev->gpu_reset_counter)) |
259 | continue; | |
1fbb2e92 CK |
260 | |
261 | if (atomic64_read(&id->owner) != vm->client_id) | |
262 | continue; | |
263 | ||
281d144d | 264 | if (*vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
265 | continue; |
266 | ||
3dab83be | 267 | if (!same_ring && |
1fbb2e92 CK |
268 | (!id->last_flush || !fence_is_signaled(id->last_flush))) |
269 | continue; | |
270 | ||
271 | flushed = id->flushed_updates; | |
272 | if (updates && | |
273 | (!flushed || fence_is_later(updates, flushed))) | |
274 | continue; | |
275 | ||
3dab83be CK |
276 | /* Good we can use this VMID. Remember this submission as |
277 | * user of the VMID. | |
278 | */ | |
1fbb2e92 CK |
279 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
280 | if (r) | |
281 | goto error; | |
8d76001e | 282 | |
6adb0513 | 283 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
1fbb2e92 CK |
284 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
285 | vm->ids[ring->idx] = id; | |
8d76001e | 286 | |
1fbb2e92 CK |
287 | *vm_id = id - adev->vm_manager.ids; |
288 | *vm_pd_addr = AMDGPU_VM_NO_FLUSH; | |
289 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); | |
8d76001e | 290 | |
1fbb2e92 CK |
291 | mutex_unlock(&adev->vm_manager.lock); |
292 | return 0; | |
8d76001e | 293 | |
1fbb2e92 | 294 | } while (i != ring->idx); |
8d76001e | 295 | |
1fbb2e92 CK |
296 | /* Still no ID to use? Then use the idle one found earlier */ |
297 | id = idle; | |
8e9fbeb5 | 298 | |
1fbb2e92 CK |
299 | /* Remember this submission as user of the VMID */ |
300 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
301 | if (r) |
302 | goto error; | |
94dd0a4a | 303 | |
832a902f CK |
304 | fence_put(id->first); |
305 | id->first = fence_get(fence); | |
94dd0a4a | 306 | |
41d9eb2c CK |
307 | fence_put(id->last_flush); |
308 | id->last_flush = NULL; | |
309 | ||
832a902f CK |
310 | fence_put(id->flushed_updates); |
311 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 312 | |
281d144d | 313 | id->pd_gpu_addr = *vm_pd_addr; |
4ff37a83 | 314 | |
b46b8a87 | 315 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
832a902f | 316 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
0ea54b9b | 317 | atomic64_set(&id->owner, vm->client_id); |
832a902f | 318 | vm->ids[ring->idx] = id; |
d38ceaf9 | 319 | |
832a902f | 320 | *vm_id = id - adev->vm_manager.ids; |
832a902f CK |
321 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); |
322 | ||
323 | error: | |
94dd0a4a | 324 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 325 | return r; |
d38ceaf9 AD |
326 | } |
327 | ||
93dcc37d AD |
328 | static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) |
329 | { | |
330 | struct amdgpu_device *adev = ring->adev; | |
331 | const struct amdgpu_ip_block_version *ip_block; | |
332 | ||
333 | if (ring->type != AMDGPU_RING_TYPE_COMPUTE) | |
334 | /* only compute rings */ | |
335 | return false; | |
336 | ||
337 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
338 | if (!ip_block) | |
339 | return false; | |
340 | ||
341 | if (ip_block->major <= 7) { | |
342 | /* gfx7 has no workaround */ | |
343 | return true; | |
344 | } else if (ip_block->major == 8) { | |
345 | if (adev->gfx.mec_fw_version >= 673) | |
346 | /* gfx8 is fixed in MEC firmware 673 */ | |
347 | return false; | |
348 | else | |
349 | return true; | |
350 | } | |
351 | return false; | |
352 | } | |
353 | ||
d38ceaf9 AD |
354 | /** |
355 | * amdgpu_vm_flush - hardware flush the vm | |
356 | * | |
357 | * @ring: ring to use for flush | |
cffadc83 | 358 | * @vm_id: vmid number to use |
4ff37a83 | 359 | * @pd_addr: address of the page directory |
d38ceaf9 | 360 | * |
4ff37a83 | 361 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 362 | */ |
41d9eb2c CK |
363 | int amdgpu_vm_flush(struct amdgpu_ring *ring, |
364 | unsigned vm_id, uint64_t pd_addr, | |
365 | uint32_t gds_base, uint32_t gds_size, | |
366 | uint32_t gws_base, uint32_t gws_size, | |
367 | uint32_t oa_base, uint32_t oa_size) | |
d38ceaf9 | 368 | { |
971fe9a9 | 369 | struct amdgpu_device *adev = ring->adev; |
bcb1ba35 | 370 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
d564a06e | 371 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
bcb1ba35 CK |
372 | id->gds_base != gds_base || |
373 | id->gds_size != gds_size || | |
374 | id->gws_base != gws_base || | |
375 | id->gws_size != gws_size || | |
376 | id->oa_base != oa_base || | |
377 | id->oa_size != oa_size); | |
41d9eb2c | 378 | int r; |
d564a06e CK |
379 | |
380 | if (ring->funcs->emit_pipeline_sync && ( | |
fe707664 | 381 | pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed || |
93dcc37d | 382 | amdgpu_vm_ring_has_compute_vm_bug(ring))) |
d564a06e | 383 | amdgpu_ring_emit_pipeline_sync(ring); |
971fe9a9 | 384 | |
c5637837 ML |
385 | if (ring->funcs->emit_vm_flush && |
386 | pd_addr != AMDGPU_VM_NO_FLUSH) { | |
41d9eb2c CK |
387 | struct fence *fence; |
388 | ||
cffadc83 CK |
389 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); |
390 | amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); | |
41d9eb2c | 391 | |
3dab83be CK |
392 | r = amdgpu_fence_emit(ring, &fence); |
393 | if (r) | |
394 | return r; | |
395 | ||
41d9eb2c | 396 | mutex_lock(&adev->vm_manager.lock); |
3dab83be CK |
397 | fence_put(id->last_flush); |
398 | id->last_flush = fence; | |
41d9eb2c | 399 | mutex_unlock(&adev->vm_manager.lock); |
d38ceaf9 | 400 | } |
cffadc83 | 401 | |
d564a06e | 402 | if (gds_switch_needed) { |
bcb1ba35 CK |
403 | id->gds_base = gds_base; |
404 | id->gds_size = gds_size; | |
405 | id->gws_base = gws_base; | |
406 | id->gws_size = gws_size; | |
407 | id->oa_base = oa_base; | |
408 | id->oa_size = oa_size; | |
cffadc83 CK |
409 | amdgpu_ring_emit_gds_switch(ring, vm_id, |
410 | gds_base, gds_size, | |
411 | gws_base, gws_size, | |
412 | oa_base, oa_size); | |
971fe9a9 | 413 | } |
41d9eb2c CK |
414 | |
415 | return 0; | |
971fe9a9 CK |
416 | } |
417 | ||
418 | /** | |
419 | * amdgpu_vm_reset_id - reset VMID to zero | |
420 | * | |
421 | * @adev: amdgpu device structure | |
422 | * @vm_id: vmid number to use | |
423 | * | |
424 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
425 | */ | |
426 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
427 | { | |
bcb1ba35 CK |
428 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
429 | ||
430 | id->gds_base = 0; | |
431 | id->gds_size = 0; | |
432 | id->gws_base = 0; | |
433 | id->gws_size = 0; | |
434 | id->oa_base = 0; | |
435 | id->oa_size = 0; | |
d38ceaf9 AD |
436 | } |
437 | ||
d38ceaf9 AD |
438 | /** |
439 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
440 | * | |
441 | * @vm: requested vm | |
442 | * @bo: requested buffer object | |
443 | * | |
8843dbbb | 444 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
445 | * Search inside the @bos vm list for the requested vm |
446 | * Returns the found bo_va or NULL if none is found | |
447 | * | |
448 | * Object has to be reserved! | |
449 | */ | |
450 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
451 | struct amdgpu_bo *bo) | |
452 | { | |
453 | struct amdgpu_bo_va *bo_va; | |
454 | ||
455 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
456 | if (bo_va->vm == vm) { | |
457 | return bo_va; | |
458 | } | |
459 | } | |
460 | return NULL; | |
461 | } | |
462 | ||
463 | /** | |
464 | * amdgpu_vm_update_pages - helper to call the right asic function | |
465 | * | |
466 | * @adev: amdgpu_device pointer | |
f4833c4f | 467 | * @vm_update_params: see amdgpu_vm_update_params definition |
d38ceaf9 AD |
468 | * @pe: addr of the page entry |
469 | * @addr: dst addr to write into pe | |
470 | * @count: number of page entries to update | |
471 | * @incr: increase next addr by incr bytes | |
472 | * @flags: hw access flags | |
d38ceaf9 AD |
473 | * |
474 | * Traces the parameters and calls the right asic functions | |
475 | * to setup the page table using the DMA. | |
476 | */ | |
477 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
f4833c4f HK |
478 | struct amdgpu_vm_update_params |
479 | *vm_update_params, | |
d38ceaf9 AD |
480 | uint64_t pe, uint64_t addr, |
481 | unsigned count, uint32_t incr, | |
9ab21462 | 482 | uint32_t flags) |
d38ceaf9 AD |
483 | { |
484 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
485 | ||
f4833c4f HK |
486 | if (vm_update_params->src) { |
487 | amdgpu_vm_copy_pte(adev, vm_update_params->ib, | |
488 | pe, (vm_update_params->src + (addr >> 12) * 8), count); | |
d38ceaf9 | 489 | |
f4833c4f HK |
490 | } else if (vm_update_params->pages_addr) { |
491 | amdgpu_vm_write_pte(adev, vm_update_params->ib, | |
492 | vm_update_params->pages_addr, | |
493 | pe, addr, count, incr, flags); | |
b07c9d2a CK |
494 | |
495 | } else if (count < 3) { | |
f4833c4f | 496 | amdgpu_vm_write_pte(adev, vm_update_params->ib, NULL, pe, addr, |
b07c9d2a | 497 | count, incr, flags); |
d38ceaf9 AD |
498 | |
499 | } else { | |
f4833c4f | 500 | amdgpu_vm_set_pte_pde(adev, vm_update_params->ib, pe, addr, |
d38ceaf9 AD |
501 | count, incr, flags); |
502 | } | |
503 | } | |
504 | ||
505 | /** | |
506 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
507 | * | |
508 | * @adev: amdgpu_device pointer | |
509 | * @bo: bo to clear | |
ef9f0a83 CZ |
510 | * |
511 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
512 | */ |
513 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 514 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
515 | struct amdgpu_bo *bo) |
516 | { | |
2d55e45a | 517 | struct amdgpu_ring *ring; |
4af9f07c | 518 | struct fence *fence = NULL; |
d71518b5 | 519 | struct amdgpu_job *job; |
f4833c4f | 520 | struct amdgpu_vm_update_params vm_update_params; |
d38ceaf9 AD |
521 | unsigned entries; |
522 | uint64_t addr; | |
523 | int r; | |
524 | ||
f4833c4f | 525 | memset(&vm_update_params, 0, sizeof(vm_update_params)); |
2d55e45a CK |
526 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
527 | ||
ca952613 | 528 | r = reservation_object_reserve_shared(bo->tbo.resv); |
529 | if (r) | |
530 | return r; | |
531 | ||
d38ceaf9 AD |
532 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
533 | if (r) | |
ef9f0a83 | 534 | goto error; |
d38ceaf9 AD |
535 | |
536 | addr = amdgpu_bo_gpu_offset(bo); | |
537 | entries = amdgpu_bo_size(bo) / 8; | |
538 | ||
d71518b5 CK |
539 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
540 | if (r) | |
ef9f0a83 | 541 | goto error; |
d38ceaf9 | 542 | |
f4833c4f HK |
543 | vm_update_params.ib = &job->ibs[0]; |
544 | amdgpu_vm_update_pages(adev, &vm_update_params, addr, 0, entries, | |
d71518b5 CK |
545 | 0, 0); |
546 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); | |
547 | ||
548 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
549 | r = amdgpu_job_submit(job, ring, &vm->entity, |
550 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
551 | if (r) |
552 | goto error_free; | |
553 | ||
d71518b5 | 554 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 555 | fence_put(fence); |
cadf97b1 | 556 | return 0; |
ef9f0a83 | 557 | |
d38ceaf9 | 558 | error_free: |
d71518b5 | 559 | amdgpu_job_free(job); |
d38ceaf9 | 560 | |
ef9f0a83 | 561 | error: |
d38ceaf9 AD |
562 | return r; |
563 | } | |
564 | ||
565 | /** | |
b07c9d2a | 566 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 567 | * |
b07c9d2a | 568 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
569 | * @addr: the unmapped addr |
570 | * | |
571 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 572 | * to and return the pointer for the page table entry. |
d38ceaf9 | 573 | */ |
b07c9d2a | 574 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
575 | { |
576 | uint64_t result; | |
577 | ||
b07c9d2a CK |
578 | if (pages_addr) { |
579 | /* page table offset */ | |
580 | result = pages_addr[addr >> PAGE_SHIFT]; | |
581 | ||
582 | /* in case cpu page size != gpu page size*/ | |
583 | result |= addr & (~PAGE_MASK); | |
584 | ||
585 | } else { | |
586 | /* No mapping required */ | |
587 | result = addr; | |
588 | } | |
d38ceaf9 | 589 | |
b07c9d2a | 590 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
591 | |
592 | return result; | |
593 | } | |
594 | ||
595 | /** | |
596 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
597 | * | |
598 | * @adev: amdgpu_device pointer | |
599 | * @vm: requested vm | |
600 | * @start: start of GPU address range | |
601 | * @end: end of GPU address range | |
602 | * | |
603 | * Allocates new page tables if necessary | |
8843dbbb | 604 | * and updates the page directory. |
d38ceaf9 | 605 | * Returns 0 for success, error for failure. |
d38ceaf9 AD |
606 | */ |
607 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
608 | struct amdgpu_vm *vm) | |
609 | { | |
2d55e45a | 610 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
611 | struct amdgpu_bo *pd = vm->page_directory; |
612 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
613 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
614 | uint64_t last_pde = ~0, last_pt = ~0; | |
615 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 616 | struct amdgpu_job *job; |
f4833c4f | 617 | struct amdgpu_vm_update_params vm_update_params; |
4af9f07c | 618 | struct fence *fence = NULL; |
d5fc5e82 | 619 | |
d38ceaf9 AD |
620 | int r; |
621 | ||
f4833c4f | 622 | memset(&vm_update_params, 0, sizeof(vm_update_params)); |
2d55e45a CK |
623 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
624 | ||
d38ceaf9 AD |
625 | /* padding, etc. */ |
626 | ndw = 64; | |
627 | ||
628 | /* assume the worst case */ | |
629 | ndw += vm->max_pde_used * 6; | |
630 | ||
d71518b5 CK |
631 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
632 | if (r) | |
d38ceaf9 | 633 | return r; |
d71518b5 | 634 | |
f4833c4f | 635 | vm_update_params.ib = &job->ibs[0]; |
d38ceaf9 AD |
636 | |
637 | /* walk over the address space and update the page directory */ | |
638 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 639 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
640 | uint64_t pde, pt; |
641 | ||
642 | if (bo == NULL) | |
643 | continue; | |
644 | ||
645 | pt = amdgpu_bo_gpu_offset(bo); | |
646 | if (vm->page_tables[pt_idx].addr == pt) | |
647 | continue; | |
648 | vm->page_tables[pt_idx].addr = pt; | |
649 | ||
650 | pde = pd_addr + pt_idx * 8; | |
651 | if (((last_pde + 8 * count) != pde) || | |
652 | ((last_pt + incr * count) != pt)) { | |
653 | ||
654 | if (count) { | |
f4833c4f | 655 | amdgpu_vm_update_pages(adev, &vm_update_params, |
9ab21462 CK |
656 | last_pde, last_pt, |
657 | count, incr, | |
658 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
659 | } |
660 | ||
661 | count = 1; | |
662 | last_pde = pde; | |
663 | last_pt = pt; | |
664 | } else { | |
665 | ++count; | |
666 | } | |
667 | } | |
668 | ||
669 | if (count) | |
f4833c4f HK |
670 | amdgpu_vm_update_pages(adev, &vm_update_params, |
671 | last_pde, last_pt, | |
672 | count, incr, AMDGPU_PTE_VALID); | |
d38ceaf9 | 673 | |
f4833c4f HK |
674 | if (vm_update_params.ib->length_dw != 0) { |
675 | amdgpu_ring_pad_ib(ring, vm_update_params.ib); | |
e86f9cee CK |
676 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
677 | AMDGPU_FENCE_OWNER_VM); | |
f4833c4f | 678 | WARN_ON(vm_update_params.ib->length_dw > ndw); |
2bd9ccfa CK |
679 | r = amdgpu_job_submit(job, ring, &vm->entity, |
680 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
681 | if (r) |
682 | goto error_free; | |
05906dec | 683 | |
4af9f07c | 684 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
685 | fence_put(vm->page_directory_fence); |
686 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 687 | fence_put(fence); |
d5fc5e82 | 688 | |
d71518b5 CK |
689 | } else { |
690 | amdgpu_job_free(job); | |
d5fc5e82 | 691 | } |
d38ceaf9 AD |
692 | |
693 | return 0; | |
d5fc5e82 CZ |
694 | |
695 | error_free: | |
d71518b5 | 696 | amdgpu_job_free(job); |
4af9f07c | 697 | return r; |
d38ceaf9 AD |
698 | } |
699 | ||
700 | /** | |
701 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
702 | * | |
703 | * @adev: amdgpu_device pointer | |
f4833c4f | 704 | * @vm_update_params: see amdgpu_vm_update_params definition |
d38ceaf9 AD |
705 | * @pe_start: first PTE to handle |
706 | * @pe_end: last PTE to handle | |
707 | * @addr: addr those PTEs should point to | |
708 | * @flags: hw mapping flags | |
d38ceaf9 AD |
709 | */ |
710 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
f4833c4f HK |
711 | struct amdgpu_vm_update_params |
712 | *vm_update_params, | |
d38ceaf9 | 713 | uint64_t pe_start, uint64_t pe_end, |
9ab21462 | 714 | uint64_t addr, uint32_t flags) |
d38ceaf9 AD |
715 | { |
716 | /** | |
717 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
718 | * field in the PTE. When this field is set to a non-zero value, page | |
719 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
720 | * flags are considered valid for all PTEs within the fragment range | |
721 | * and corresponding mappings are assumed to be physically contiguous. | |
722 | * | |
723 | * The L1 TLB can store a single PTE for the whole fragment, | |
724 | * significantly increasing the space available for translation | |
725 | * caching. This leads to large improvements in throughput when the | |
726 | * TLB is under pressure. | |
727 | * | |
728 | * The L2 TLB distributes small and large fragments into two | |
729 | * asymmetric partitions. The large fragment cache is significantly | |
730 | * larger. Thus, we try to use large fragments wherever possible. | |
731 | * Userspace can support this by aligning virtual base address and | |
732 | * allocation size to the fragment size. | |
733 | */ | |
734 | ||
735 | /* SI and newer are optimized for 64KB */ | |
736 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
737 | uint64_t frag_align = 0x80; | |
738 | ||
739 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
740 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
741 | ||
742 | unsigned count; | |
743 | ||
31f6c1fe CK |
744 | /* Abort early if there isn't anything to do */ |
745 | if (pe_start == pe_end) | |
746 | return; | |
747 | ||
d38ceaf9 | 748 | /* system pages are non continuously */ |
f4833c4f HK |
749 | if (vm_update_params->src || vm_update_params->pages_addr || |
750 | !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) { | |
d38ceaf9 AD |
751 | |
752 | count = (pe_end - pe_start) / 8; | |
f4833c4f | 753 | amdgpu_vm_update_pages(adev, vm_update_params, pe_start, |
9ab21462 CK |
754 | addr, count, AMDGPU_GPU_PAGE_SIZE, |
755 | flags); | |
d38ceaf9 AD |
756 | return; |
757 | } | |
758 | ||
759 | /* handle the 4K area at the beginning */ | |
760 | if (pe_start != frag_start) { | |
761 | count = (frag_start - pe_start) / 8; | |
f4833c4f | 762 | amdgpu_vm_update_pages(adev, vm_update_params, pe_start, addr, |
9ab21462 | 763 | count, AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
764 | addr += AMDGPU_GPU_PAGE_SIZE * count; |
765 | } | |
766 | ||
767 | /* handle the area in the middle */ | |
768 | count = (frag_end - frag_start) / 8; | |
f4833c4f | 769 | amdgpu_vm_update_pages(adev, vm_update_params, frag_start, addr, count, |
9ab21462 | 770 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags); |
d38ceaf9 AD |
771 | |
772 | /* handle the 4K area at the end */ | |
773 | if (frag_end != pe_end) { | |
774 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
775 | count = (pe_end - frag_end) / 8; | |
f4833c4f | 776 | amdgpu_vm_update_pages(adev, vm_update_params, frag_end, addr, |
9ab21462 | 777 | count, AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
778 | } |
779 | } | |
780 | ||
781 | /** | |
782 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
783 | * | |
784 | * @adev: amdgpu_device pointer | |
f4833c4f | 785 | * @vm_update_params: see amdgpu_vm_update_params definition |
d38ceaf9 AD |
786 | * @vm: requested vm |
787 | * @start: start of GPU address range | |
788 | * @end: end of GPU address range | |
677131a1 | 789 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
790 | * @flags: mapping flags |
791 | * | |
8843dbbb | 792 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 793 | */ |
a1e08d3b | 794 | static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, |
f4833c4f HK |
795 | struct amdgpu_vm_update_params |
796 | *vm_update_params, | |
a1e08d3b | 797 | struct amdgpu_vm *vm, |
a1e08d3b CK |
798 | uint64_t start, uint64_t end, |
799 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 800 | { |
31f6c1fe CK |
801 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
802 | ||
21718497 | 803 | uint64_t cur_pe_start, cur_pe_end, cur_dst; |
677131a1 | 804 | uint64_t addr; /* next GPU address to be updated */ |
21718497 AX |
805 | uint64_t pt_idx; |
806 | struct amdgpu_bo *pt; | |
807 | unsigned nptes; /* next number of ptes to be updated */ | |
808 | uint64_t next_pe_start; | |
809 | ||
810 | /* initialize the variables */ | |
811 | addr = start; | |
812 | pt_idx = addr >> amdgpu_vm_block_size; | |
813 | pt = vm->page_tables[pt_idx].entry.robj; | |
814 | ||
815 | if ((addr & ~mask) == (end & ~mask)) | |
816 | nptes = end - addr; | |
817 | else | |
818 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
819 | ||
820 | cur_pe_start = amdgpu_bo_gpu_offset(pt); | |
821 | cur_pe_start += (addr & mask) * 8; | |
822 | cur_pe_end = cur_pe_start + 8 * nptes; | |
823 | cur_dst = dst; | |
824 | ||
825 | /* for next ptb*/ | |
826 | addr += nptes; | |
827 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
d38ceaf9 AD |
828 | |
829 | /* walk over the address space and update the page tables */ | |
21718497 AX |
830 | while (addr < end) { |
831 | pt_idx = addr >> amdgpu_vm_block_size; | |
832 | pt = vm->page_tables[pt_idx].entry.robj; | |
d38ceaf9 AD |
833 | |
834 | if ((addr & ~mask) == (end & ~mask)) | |
835 | nptes = end - addr; | |
836 | else | |
837 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
838 | ||
677131a1 AX |
839 | next_pe_start = amdgpu_bo_gpu_offset(pt); |
840 | next_pe_start += (addr & mask) * 8; | |
d38ceaf9 | 841 | |
3a6f8e0c AX |
842 | if (cur_pe_end == next_pe_start) { |
843 | /* The next ptb is consecutive to current ptb. | |
844 | * Don't call amdgpu_vm_frag_ptes now. | |
845 | * Will update two ptbs together in future. | |
846 | */ | |
847 | cur_pe_end += 8 * nptes; | |
848 | } else { | |
f4833c4f | 849 | amdgpu_vm_frag_ptes(adev, vm_update_params, |
677131a1 AX |
850 | cur_pe_start, cur_pe_end, |
851 | cur_dst, flags); | |
d38ceaf9 | 852 | |
677131a1 AX |
853 | cur_pe_start = next_pe_start; |
854 | cur_pe_end = next_pe_start + 8 * nptes; | |
855 | cur_dst = dst; | |
d38ceaf9 AD |
856 | } |
857 | ||
21718497 | 858 | /* for next ptb*/ |
d38ceaf9 AD |
859 | addr += nptes; |
860 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
861 | } | |
862 | ||
677131a1 AX |
863 | amdgpu_vm_frag_ptes(adev, vm_update_params, cur_pe_start, |
864 | cur_pe_end, cur_dst, flags); | |
d38ceaf9 AD |
865 | } |
866 | ||
d38ceaf9 AD |
867 | /** |
868 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
869 | * | |
870 | * @adev: amdgpu_device pointer | |
3cabaa54 | 871 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
872 | * @src: address where to copy page table entries from |
873 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 874 | * @vm: requested vm |
a14faa65 CK |
875 | * @start: start of mapped range |
876 | * @last: last mapped entry | |
877 | * @flags: flags for the entries | |
d38ceaf9 | 878 | * @addr: addr to set the area to |
d38ceaf9 AD |
879 | * @fence: optional resulting fence |
880 | * | |
a14faa65 | 881 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 882 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
883 | */ |
884 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
3cabaa54 | 885 | struct fence *exclusive, |
fa3ab3c7 CK |
886 | uint64_t src, |
887 | dma_addr_t *pages_addr, | |
d38ceaf9 | 888 | struct amdgpu_vm *vm, |
a14faa65 CK |
889 | uint64_t start, uint64_t last, |
890 | uint32_t flags, uint64_t addr, | |
891 | struct fence **fence) | |
d38ceaf9 | 892 | { |
2d55e45a | 893 | struct amdgpu_ring *ring; |
a1e08d3b | 894 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 895 | unsigned nptes, ncmds, ndw; |
d71518b5 | 896 | struct amdgpu_job *job; |
f4833c4f | 897 | struct amdgpu_vm_update_params vm_update_params; |
4af9f07c | 898 | struct fence *f = NULL; |
d38ceaf9 AD |
899 | int r; |
900 | ||
2d55e45a | 901 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
f4833c4f HK |
902 | memset(&vm_update_params, 0, sizeof(vm_update_params)); |
903 | vm_update_params.src = src; | |
904 | vm_update_params.pages_addr = pages_addr; | |
2d55e45a | 905 | |
a1e08d3b CK |
906 | /* sync to everything on unmapping */ |
907 | if (!(flags & AMDGPU_PTE_VALID)) | |
908 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
909 | ||
a14faa65 | 910 | nptes = last - start + 1; |
d38ceaf9 AD |
911 | |
912 | /* | |
913 | * reserve space for one command every (1 << BLOCK_SIZE) | |
914 | * entries or 2k dwords (whatever is smaller) | |
915 | */ | |
916 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
917 | ||
918 | /* padding, etc. */ | |
919 | ndw = 64; | |
920 | ||
f4833c4f | 921 | if (vm_update_params.src) { |
d38ceaf9 AD |
922 | /* only copy commands needed */ |
923 | ndw += ncmds * 7; | |
924 | ||
f4833c4f | 925 | } else if (vm_update_params.pages_addr) { |
d38ceaf9 AD |
926 | /* header for write data commands */ |
927 | ndw += ncmds * 4; | |
928 | ||
929 | /* body of write data command */ | |
930 | ndw += nptes * 2; | |
931 | ||
932 | } else { | |
933 | /* set page commands needed */ | |
934 | ndw += ncmds * 10; | |
935 | ||
936 | /* two extra commands for begin/end of fragment */ | |
937 | ndw += 2 * 10; | |
938 | } | |
939 | ||
d71518b5 CK |
940 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
941 | if (r) | |
d38ceaf9 | 942 | return r; |
d71518b5 | 943 | |
f4833c4f | 944 | vm_update_params.ib = &job->ibs[0]; |
d5fc5e82 | 945 | |
3cabaa54 CK |
946 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
947 | if (r) | |
948 | goto error_free; | |
949 | ||
e86f9cee | 950 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
951 | owner); |
952 | if (r) | |
953 | goto error_free; | |
d38ceaf9 | 954 | |
a1e08d3b CK |
955 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
956 | if (r) | |
957 | goto error_free; | |
958 | ||
f4833c4f | 959 | amdgpu_vm_update_ptes(adev, &vm_update_params, vm, start, |
fa3ab3c7 | 960 | last + 1, addr, flags); |
d38ceaf9 | 961 | |
f4833c4f HK |
962 | amdgpu_ring_pad_ib(ring, vm_update_params.ib); |
963 | WARN_ON(vm_update_params.ib->length_dw > ndw); | |
2bd9ccfa CK |
964 | r = amdgpu_job_submit(job, ring, &vm->entity, |
965 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
966 | if (r) |
967 | goto error_free; | |
d38ceaf9 | 968 | |
bf60efd3 | 969 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
970 | if (fence) { |
971 | fence_put(*fence); | |
972 | *fence = fence_get(f); | |
973 | } | |
281b4223 | 974 | fence_put(f); |
d38ceaf9 | 975 | return 0; |
d5fc5e82 CZ |
976 | |
977 | error_free: | |
d71518b5 | 978 | amdgpu_job_free(job); |
4af9f07c | 979 | return r; |
d38ceaf9 AD |
980 | } |
981 | ||
a14faa65 CK |
982 | /** |
983 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
984 | * | |
985 | * @adev: amdgpu_device pointer | |
3cabaa54 | 986 | * @exclusive: fence we need to sync to |
8358dcee CK |
987 | * @gtt_flags: flags as they are used for GTT |
988 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
989 | * @vm: requested vm |
990 | * @mapping: mapped range and flags to use for the update | |
991 | * @addr: addr to set the area to | |
8358dcee | 992 | * @flags: HW flags for the mapping |
a14faa65 CK |
993 | * @fence: optional resulting fence |
994 | * | |
995 | * Split the mapping into smaller chunks so that each update fits | |
996 | * into a SDMA IB. | |
997 | * Returns 0 for success, -EINVAL for failure. | |
998 | */ | |
999 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
3cabaa54 | 1000 | struct fence *exclusive, |
a14faa65 | 1001 | uint32_t gtt_flags, |
8358dcee | 1002 | dma_addr_t *pages_addr, |
a14faa65 CK |
1003 | struct amdgpu_vm *vm, |
1004 | struct amdgpu_bo_va_mapping *mapping, | |
fa3ab3c7 CK |
1005 | uint32_t flags, uint64_t addr, |
1006 | struct fence **fence) | |
a14faa65 CK |
1007 | { |
1008 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
1009 | ||
fa3ab3c7 | 1010 | uint64_t src = 0, start = mapping->it.start; |
a14faa65 CK |
1011 | int r; |
1012 | ||
1013 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1014 | * but in case of something, we filter the flags in first place | |
1015 | */ | |
1016 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1017 | flags &= ~AMDGPU_PTE_READABLE; | |
1018 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1019 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1020 | ||
1021 | trace_amdgpu_vm_bo_update(mapping); | |
1022 | ||
8358dcee | 1023 | if (pages_addr) { |
fa3ab3c7 CK |
1024 | if (flags == gtt_flags) |
1025 | src = adev->gart.table_addr + (addr >> 12) * 8; | |
fa3ab3c7 CK |
1026 | addr = 0; |
1027 | } | |
a14faa65 CK |
1028 | addr += mapping->offset; |
1029 | ||
8358dcee | 1030 | if (!pages_addr || src) |
3cabaa54 CK |
1031 | return amdgpu_vm_bo_update_mapping(adev, exclusive, |
1032 | src, pages_addr, vm, | |
a14faa65 CK |
1033 | start, mapping->it.last, |
1034 | flags, addr, fence); | |
1035 | ||
1036 | while (start != mapping->it.last + 1) { | |
1037 | uint64_t last; | |
1038 | ||
fb29b57c | 1039 | last = min((uint64_t)mapping->it.last, start + max_size - 1); |
3cabaa54 CK |
1040 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1041 | src, pages_addr, vm, | |
a14faa65 CK |
1042 | start, last, flags, addr, |
1043 | fence); | |
1044 | if (r) | |
1045 | return r; | |
1046 | ||
1047 | start = last + 1; | |
fb29b57c | 1048 | addr += max_size * AMDGPU_GPU_PAGE_SIZE; |
a14faa65 CK |
1049 | } |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | ||
d38ceaf9 AD |
1054 | /** |
1055 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1056 | * | |
1057 | * @adev: amdgpu_device pointer | |
1058 | * @bo_va: requested BO and VM object | |
1059 | * @mem: ttm mem | |
1060 | * | |
1061 | * Fill in the page table entries for @bo_va. | |
1062 | * Returns 0 for success, -EINVAL for failure. | |
1063 | * | |
1064 | * Object have to be reserved and mutex must be locked! | |
1065 | */ | |
1066 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1067 | struct amdgpu_bo_va *bo_va, | |
1068 | struct ttm_mem_reg *mem) | |
1069 | { | |
1070 | struct amdgpu_vm *vm = bo_va->vm; | |
1071 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1072 | dma_addr_t *pages_addr = NULL; |
fa3ab3c7 | 1073 | uint32_t gtt_flags, flags; |
3cabaa54 | 1074 | struct fence *exclusive; |
d38ceaf9 AD |
1075 | uint64_t addr; |
1076 | int r; | |
1077 | ||
1078 | if (mem) { | |
8358dcee CK |
1079 | struct ttm_dma_tt *ttm; |
1080 | ||
b7d698d7 | 1081 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
1082 | switch (mem->mem_type) { |
1083 | case TTM_PL_TT: | |
8358dcee CK |
1084 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1085 | ttm_dma_tt, ttm); | |
1086 | pages_addr = ttm->dma_address; | |
9ab21462 CK |
1087 | break; |
1088 | ||
1089 | case TTM_PL_VRAM: | |
d38ceaf9 | 1090 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
1091 | break; |
1092 | ||
1093 | default: | |
1094 | break; | |
1095 | } | |
3cabaa54 CK |
1096 | |
1097 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); | |
d38ceaf9 AD |
1098 | } else { |
1099 | addr = 0; | |
3cabaa54 | 1100 | exclusive = NULL; |
d38ceaf9 AD |
1101 | } |
1102 | ||
d38ceaf9 | 1103 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
fa3ab3c7 | 1104 | gtt_flags = (adev == bo_va->bo->adev) ? flags : 0; |
d38ceaf9 | 1105 | |
7fc11959 CK |
1106 | spin_lock(&vm->status_lock); |
1107 | if (!list_empty(&bo_va->vm_status)) | |
1108 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1109 | spin_unlock(&vm->status_lock); | |
1110 | ||
1111 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1112 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1113 | gtt_flags, pages_addr, vm, | |
8358dcee CK |
1114 | mapping, flags, addr, |
1115 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
1116 | if (r) |
1117 | return r; | |
1118 | } | |
1119 | ||
d6c10f6b CK |
1120 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1121 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1122 | trace_amdgpu_vm_bo_mapping(mapping); | |
1123 | ||
1124 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1125 | trace_amdgpu_vm_bo_mapping(mapping); | |
1126 | } | |
1127 | ||
d38ceaf9 | 1128 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1129 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1130 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
1131 | if (!mem) |
1132 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
1133 | spin_unlock(&vm->status_lock); |
1134 | ||
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | /** | |
1139 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1140 | * | |
1141 | * @adev: amdgpu_device pointer | |
1142 | * @vm: requested vm | |
1143 | * | |
1144 | * Make sure all freed BOs are cleared in the PT. | |
1145 | * Returns 0 for success. | |
1146 | * | |
1147 | * PTs have to be reserved and mutex must be locked! | |
1148 | */ | |
1149 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
1150 | struct amdgpu_vm *vm) | |
1151 | { | |
1152 | struct amdgpu_bo_va_mapping *mapping; | |
1153 | int r; | |
1154 | ||
1155 | while (!list_empty(&vm->freed)) { | |
1156 | mapping = list_first_entry(&vm->freed, | |
1157 | struct amdgpu_bo_va_mapping, list); | |
1158 | list_del(&mapping->list); | |
e17841b9 | 1159 | |
3cabaa54 | 1160 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping, |
fa3ab3c7 | 1161 | 0, 0, NULL); |
d38ceaf9 AD |
1162 | kfree(mapping); |
1163 | if (r) | |
1164 | return r; | |
1165 | ||
1166 | } | |
1167 | return 0; | |
1168 | ||
1169 | } | |
1170 | ||
1171 | /** | |
1172 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1173 | * | |
1174 | * @adev: amdgpu_device pointer | |
1175 | * @vm: requested vm | |
1176 | * | |
1177 | * Make sure all invalidated BOs are cleared in the PT. | |
1178 | * Returns 0 for success. | |
1179 | * | |
1180 | * PTs have to be reserved and mutex must be locked! | |
1181 | */ | |
1182 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1183 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1184 | { |
cfe2c978 | 1185 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1186 | int r = 0; |
d38ceaf9 AD |
1187 | |
1188 | spin_lock(&vm->status_lock); | |
1189 | while (!list_empty(&vm->invalidated)) { | |
1190 | bo_va = list_first_entry(&vm->invalidated, | |
1191 | struct amdgpu_bo_va, vm_status); | |
1192 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1193 | |
d38ceaf9 AD |
1194 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
1195 | if (r) | |
1196 | return r; | |
1197 | ||
1198 | spin_lock(&vm->status_lock); | |
1199 | } | |
1200 | spin_unlock(&vm->status_lock); | |
1201 | ||
cfe2c978 | 1202 | if (bo_va) |
bb1e38a4 | 1203 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1204 | |
1205 | return r; | |
d38ceaf9 AD |
1206 | } |
1207 | ||
1208 | /** | |
1209 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1210 | * | |
1211 | * @adev: amdgpu_device pointer | |
1212 | * @vm: requested vm | |
1213 | * @bo: amdgpu buffer object | |
1214 | * | |
8843dbbb | 1215 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1216 | * Add @bo to the list of bos associated with the vm |
1217 | * Returns newly added bo_va or NULL for failure | |
1218 | * | |
1219 | * Object has to be reserved! | |
1220 | */ | |
1221 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1222 | struct amdgpu_vm *vm, | |
1223 | struct amdgpu_bo *bo) | |
1224 | { | |
1225 | struct amdgpu_bo_va *bo_va; | |
1226 | ||
1227 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1228 | if (bo_va == NULL) { | |
1229 | return NULL; | |
1230 | } | |
1231 | bo_va->vm = vm; | |
1232 | bo_va->bo = bo; | |
d38ceaf9 AD |
1233 | bo_va->ref_count = 1; |
1234 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1235 | INIT_LIST_HEAD(&bo_va->valids); |
1236 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1237 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1238 | |
d38ceaf9 | 1239 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1240 | |
1241 | return bo_va; | |
1242 | } | |
1243 | ||
1244 | /** | |
1245 | * amdgpu_vm_bo_map - map bo inside a vm | |
1246 | * | |
1247 | * @adev: amdgpu_device pointer | |
1248 | * @bo_va: bo_va to store the address | |
1249 | * @saddr: where to map the BO | |
1250 | * @offset: requested offset in the BO | |
1251 | * @flags: attributes of pages (read/write/valid/etc.) | |
1252 | * | |
1253 | * Add a mapping of the BO at the specefied addr into the VM. | |
1254 | * Returns 0 for success, error for failure. | |
1255 | * | |
49b02b18 | 1256 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1257 | */ |
1258 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1259 | struct amdgpu_bo_va *bo_va, | |
1260 | uint64_t saddr, uint64_t offset, | |
1261 | uint64_t size, uint32_t flags) | |
1262 | { | |
1263 | struct amdgpu_bo_va_mapping *mapping; | |
1264 | struct amdgpu_vm *vm = bo_va->vm; | |
1265 | struct interval_tree_node *it; | |
1266 | unsigned last_pfn, pt_idx; | |
1267 | uint64_t eaddr; | |
1268 | int r; | |
1269 | ||
0be52de9 CK |
1270 | /* validate the parameters */ |
1271 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1272 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1273 | return -EINVAL; |
0be52de9 | 1274 | |
d38ceaf9 | 1275 | /* make sure object fit at this offset */ |
005ae95e | 1276 | eaddr = saddr + size - 1; |
49b02b18 | 1277 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1278 | return -EINVAL; |
d38ceaf9 AD |
1279 | |
1280 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1281 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1282 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1283 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1284 | return -EINVAL; |
1285 | } | |
1286 | ||
d38ceaf9 AD |
1287 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1288 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1289 | ||
005ae95e | 1290 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
d38ceaf9 AD |
1291 | if (it) { |
1292 | struct amdgpu_bo_va_mapping *tmp; | |
1293 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1294 | /* bo and tmp overlap, invalid addr */ | |
1295 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1296 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1297 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1298 | r = -EINVAL; |
f48b2659 | 1299 | goto error; |
d38ceaf9 AD |
1300 | } |
1301 | ||
1302 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1303 | if (!mapping) { | |
d38ceaf9 | 1304 | r = -ENOMEM; |
f48b2659 | 1305 | goto error; |
d38ceaf9 AD |
1306 | } |
1307 | ||
1308 | INIT_LIST_HEAD(&mapping->list); | |
1309 | mapping->it.start = saddr; | |
005ae95e | 1310 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1311 | mapping->offset = offset; |
1312 | mapping->flags = flags; | |
1313 | ||
7fc11959 | 1314 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 AD |
1315 | interval_tree_insert(&mapping->it, &vm->va); |
1316 | ||
1317 | /* Make sure the page tables are allocated */ | |
1318 | saddr >>= amdgpu_vm_block_size; | |
1319 | eaddr >>= amdgpu_vm_block_size; | |
1320 | ||
1321 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1322 | ||
1323 | if (eaddr > vm->max_pde_used) | |
1324 | vm->max_pde_used = eaddr; | |
1325 | ||
d38ceaf9 AD |
1326 | /* walk over the address space and allocate the page tables */ |
1327 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1328 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1329 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1330 | struct amdgpu_bo *pt; |
1331 | ||
ee1782c3 CK |
1332 | entry = &vm->page_tables[pt_idx].entry; |
1333 | if (entry->robj) | |
d38ceaf9 AD |
1334 | continue; |
1335 | ||
d38ceaf9 AD |
1336 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1337 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1338 | AMDGPU_GEM_DOMAIN_VRAM, |
1339 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 | 1340 | NULL, resv, &pt); |
49b02b18 | 1341 | if (r) |
d38ceaf9 | 1342 | goto error_free; |
49b02b18 | 1343 | |
82b9c55b CK |
1344 | /* Keep a reference to the page table to avoid freeing |
1345 | * them up in the wrong order. | |
1346 | */ | |
1347 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1348 | ||
2bd9ccfa | 1349 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 AD |
1350 | if (r) { |
1351 | amdgpu_bo_unref(&pt); | |
1352 | goto error_free; | |
1353 | } | |
1354 | ||
ee1782c3 | 1355 | entry->robj = pt; |
ee1782c3 CK |
1356 | entry->priority = 0; |
1357 | entry->tv.bo = &entry->robj->tbo; | |
1358 | entry->tv.shared = true; | |
2f568dbd | 1359 | entry->user_pages = NULL; |
d38ceaf9 | 1360 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1361 | } |
1362 | ||
d38ceaf9 AD |
1363 | return 0; |
1364 | ||
1365 | error_free: | |
d38ceaf9 AD |
1366 | list_del(&mapping->list); |
1367 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1368 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1369 | kfree(mapping); |
1370 | ||
f48b2659 | 1371 | error: |
d38ceaf9 AD |
1372 | return r; |
1373 | } | |
1374 | ||
1375 | /** | |
1376 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1377 | * | |
1378 | * @adev: amdgpu_device pointer | |
1379 | * @bo_va: bo_va to remove the address from | |
1380 | * @saddr: where to the BO is mapped | |
1381 | * | |
1382 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1383 | * Returns 0 for success, error for failure. | |
1384 | * | |
49b02b18 | 1385 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1386 | */ |
1387 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1388 | struct amdgpu_bo_va *bo_va, | |
1389 | uint64_t saddr) | |
1390 | { | |
1391 | struct amdgpu_bo_va_mapping *mapping; | |
1392 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1393 | bool valid = true; |
d38ceaf9 | 1394 | |
6c7fc503 | 1395 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1396 | |
7fc11959 | 1397 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1398 | if (mapping->it.start == saddr) |
1399 | break; | |
1400 | } | |
1401 | ||
7fc11959 CK |
1402 | if (&mapping->list == &bo_va->valids) { |
1403 | valid = false; | |
1404 | ||
1405 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1406 | if (mapping->it.start == saddr) | |
1407 | break; | |
1408 | } | |
1409 | ||
32b41ac2 | 1410 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1411 | return -ENOENT; |
d38ceaf9 | 1412 | } |
32b41ac2 | 1413 | |
d38ceaf9 AD |
1414 | list_del(&mapping->list); |
1415 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1416 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1417 | |
e17841b9 | 1418 | if (valid) |
d38ceaf9 | 1419 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1420 | else |
d38ceaf9 | 1421 | kfree(mapping); |
d38ceaf9 AD |
1422 | |
1423 | return 0; | |
1424 | } | |
1425 | ||
1426 | /** | |
1427 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1428 | * | |
1429 | * @adev: amdgpu_device pointer | |
1430 | * @bo_va: requested bo_va | |
1431 | * | |
8843dbbb | 1432 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1433 | * |
1434 | * Object have to be reserved! | |
1435 | */ | |
1436 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1437 | struct amdgpu_bo_va *bo_va) | |
1438 | { | |
1439 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1440 | struct amdgpu_vm *vm = bo_va->vm; | |
1441 | ||
1442 | list_del(&bo_va->bo_list); | |
1443 | ||
d38ceaf9 AD |
1444 | spin_lock(&vm->status_lock); |
1445 | list_del(&bo_va->vm_status); | |
1446 | spin_unlock(&vm->status_lock); | |
1447 | ||
7fc11959 | 1448 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1449 | list_del(&mapping->list); |
1450 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1451 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1452 | list_add(&mapping->list, &vm->freed); |
1453 | } | |
1454 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1455 | list_del(&mapping->list); | |
1456 | interval_tree_remove(&mapping->it, &vm->va); | |
1457 | kfree(mapping); | |
d38ceaf9 | 1458 | } |
32b41ac2 | 1459 | |
bb1e38a4 | 1460 | fence_put(bo_va->last_pt_update); |
d38ceaf9 | 1461 | kfree(bo_va); |
d38ceaf9 AD |
1462 | } |
1463 | ||
1464 | /** | |
1465 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1466 | * | |
1467 | * @adev: amdgpu_device pointer | |
1468 | * @vm: requested vm | |
1469 | * @bo: amdgpu buffer object | |
1470 | * | |
8843dbbb | 1471 | * Mark @bo as invalid. |
d38ceaf9 AD |
1472 | */ |
1473 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1474 | struct amdgpu_bo *bo) | |
1475 | { | |
1476 | struct amdgpu_bo_va *bo_va; | |
1477 | ||
1478 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1479 | spin_lock(&bo_va->vm->status_lock); |
1480 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1481 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1482 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1483 | } |
1484 | } | |
1485 | ||
1486 | /** | |
1487 | * amdgpu_vm_init - initialize a vm instance | |
1488 | * | |
1489 | * @adev: amdgpu_device pointer | |
1490 | * @vm: requested vm | |
1491 | * | |
8843dbbb | 1492 | * Init @vm fields. |
d38ceaf9 AD |
1493 | */ |
1494 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1495 | { | |
1496 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1497 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1498 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1499 | unsigned ring_instance; |
1500 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1501 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1502 | int i, r; |
1503 | ||
bcb1ba35 CK |
1504 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1505 | vm->ids[i] = NULL; | |
d38ceaf9 | 1506 | vm->va = RB_ROOT; |
031e2983 | 1507 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
d38ceaf9 AD |
1508 | spin_lock_init(&vm->status_lock); |
1509 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1510 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1511 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 1512 | |
d38ceaf9 AD |
1513 | pd_size = amdgpu_vm_directory_size(adev); |
1514 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1515 | ||
1516 | /* allocate page table array */ | |
9571e1d8 | 1517 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1518 | if (vm->page_tables == NULL) { |
1519 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1520 | return -ENOMEM; | |
1521 | } | |
1522 | ||
2bd9ccfa | 1523 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1524 | |
1525 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1526 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1527 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1528 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1529 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1530 | rq, amdgpu_sched_jobs); | |
1531 | if (r) | |
1532 | return r; | |
1533 | ||
05906dec BN |
1534 | vm->page_directory_fence = NULL; |
1535 | ||
d38ceaf9 | 1536 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1537 | AMDGPU_GEM_DOMAIN_VRAM, |
1538 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1539 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1540 | if (r) |
2bd9ccfa CK |
1541 | goto error_free_sched_entity; |
1542 | ||
ef9f0a83 | 1543 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1544 | if (r) |
1545 | goto error_free_page_directory; | |
1546 | ||
1547 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
ef9f0a83 | 1548 | amdgpu_bo_unreserve(vm->page_directory); |
2bd9ccfa CK |
1549 | if (r) |
1550 | goto error_free_page_directory; | |
5a712a87 | 1551 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
d38ceaf9 AD |
1552 | |
1553 | return 0; | |
2bd9ccfa CK |
1554 | |
1555 | error_free_page_directory: | |
1556 | amdgpu_bo_unref(&vm->page_directory); | |
1557 | vm->page_directory = NULL; | |
1558 | ||
1559 | error_free_sched_entity: | |
1560 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1561 | ||
1562 | return r; | |
d38ceaf9 AD |
1563 | } |
1564 | ||
1565 | /** | |
1566 | * amdgpu_vm_fini - tear down a vm instance | |
1567 | * | |
1568 | * @adev: amdgpu_device pointer | |
1569 | * @vm: requested vm | |
1570 | * | |
8843dbbb | 1571 | * Tear down @vm. |
d38ceaf9 AD |
1572 | * Unbind the VM and remove all bos from the vm bo list |
1573 | */ | |
1574 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1575 | { | |
1576 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1577 | int i; | |
1578 | ||
2d55e45a | 1579 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1580 | |
d38ceaf9 AD |
1581 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1582 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1583 | } | |
1584 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1585 | list_del(&mapping->list); | |
1586 | interval_tree_remove(&mapping->it, &vm->va); | |
1587 | kfree(mapping); | |
1588 | } | |
1589 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1590 | list_del(&mapping->list); | |
1591 | kfree(mapping); | |
1592 | } | |
1593 | ||
1594 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
ee1782c3 | 1595 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
9571e1d8 | 1596 | drm_free_large(vm->page_tables); |
d38ceaf9 AD |
1597 | |
1598 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1599 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1600 | } |
ea89f8c9 | 1601 | |
a9a78b32 CK |
1602 | /** |
1603 | * amdgpu_vm_manager_init - init the VM manager | |
1604 | * | |
1605 | * @adev: amdgpu_device pointer | |
1606 | * | |
1607 | * Initialize the VM manager structures | |
1608 | */ | |
1609 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1610 | { | |
1611 | unsigned i; | |
1612 | ||
1613 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1614 | ||
1615 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1616 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1617 | amdgpu_vm_reset_id(adev, i); | |
832a902f | 1618 | amdgpu_sync_create(&adev->vm_manager.ids[i].active); |
a9a78b32 CK |
1619 | list_add_tail(&adev->vm_manager.ids[i].list, |
1620 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1621 | } |
2d55e45a | 1622 | |
1fbb2e92 CK |
1623 | adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); |
1624 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | |
1625 | adev->vm_manager.seqno[i] = 0; | |
1626 | ||
2d55e45a | 1627 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 1628 | atomic64_set(&adev->vm_manager.client_counter, 0); |
a9a78b32 CK |
1629 | } |
1630 | ||
ea89f8c9 CK |
1631 | /** |
1632 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1633 | * | |
1634 | * @adev: amdgpu_device pointer | |
1635 | * | |
1636 | * Cleanup the VM manager and free resources. | |
1637 | */ | |
1638 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1639 | { | |
1640 | unsigned i; | |
1641 | ||
bcb1ba35 CK |
1642 | for (i = 0; i < AMDGPU_NUM_VM; ++i) { |
1643 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; | |
1644 | ||
832a902f CK |
1645 | fence_put(adev->vm_manager.ids[i].first); |
1646 | amdgpu_sync_free(&adev->vm_manager.ids[i].active); | |
bcb1ba35 CK |
1647 | fence_put(id->flushed_updates); |
1648 | } | |
ea89f8c9 | 1649 | } |