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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
d38ceaf9 AD |
30 | #include <drm/drmP.h> |
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
33 | #include "amdgpu_trace.h" | |
34 | ||
35 | /* | |
36 | * GPUVM | |
37 | * GPUVM is similar to the legacy gart on older asics, however | |
38 | * rather than there being a single global gart table | |
39 | * for the entire GPU, there are multiple VM page tables active | |
40 | * at any given time. The VM page tables can contain a mix | |
41 | * vram pages and system memory pages and system memory pages | |
42 | * can be mapped as snooped (cached system pages) or unsnooped | |
43 | * (uncached system pages). | |
44 | * Each VM has an ID associated with it and there is a page table | |
45 | * associated with each VMID. When execting a command buffer, | |
46 | * the kernel tells the the ring what VMID to use for that command | |
47 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
48 | * The userspace drivers maintain their own address space and the kernel | |
49 | * sets up their pages tables accordingly when they submit their | |
50 | * command buffers and a VMID is assigned. | |
51 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
52 | * SI supports 16. | |
53 | */ | |
54 | ||
a9f87f64 CK |
55 | #define START(node) ((node)->start) |
56 | #define LAST(node) ((node)->last) | |
57 | ||
58 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
59 | START, LAST, static, amdgpu_vm_it) | |
60 | ||
61 | #undef START | |
62 | #undef LAST | |
63 | ||
f4833c4f HK |
64 | /* Local structure. Encapsulate some VM table update parameters to reduce |
65 | * the number of function parameters | |
66 | */ | |
29efc4f5 | 67 | struct amdgpu_pte_update_params { |
27c5f36f CK |
68 | /* amdgpu device we do this update for */ |
69 | struct amdgpu_device *adev; | |
49ac8a24 CK |
70 | /* optional amdgpu_vm we do this update for */ |
71 | struct amdgpu_vm *vm; | |
f4833c4f HK |
72 | /* address where to copy page table entries from */ |
73 | uint64_t src; | |
f4833c4f HK |
74 | /* indirect buffer to fill with commands */ |
75 | struct amdgpu_ib *ib; | |
afef8b8f CK |
76 | /* Function which actually does the update */ |
77 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
78 | uint64_t addr, unsigned count, uint32_t incr, | |
6b777607 | 79 | uint64_t flags); |
b4d42511 HK |
80 | /* The next two are used during VM update by CPU |
81 | * DMA addresses to use for mapping | |
82 | * Kernel pointer of PD/PT BO that needs to be updated | |
83 | */ | |
84 | dma_addr_t *pages_addr; | |
85 | void *kptr; | |
f4833c4f HK |
86 | }; |
87 | ||
284710fa CK |
88 | /* Helper to disable partial resident texture feature from a fence callback */ |
89 | struct amdgpu_prt_cb { | |
90 | struct amdgpu_device *adev; | |
91 | struct dma_fence_cb cb; | |
92 | }; | |
93 | ||
d38ceaf9 | 94 | /** |
72a7ec5c | 95 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
96 | * |
97 | * @adev: amdgpu_device pointer | |
98 | * | |
72a7ec5c | 99 | * Calculate the number of entries in a page directory or page table. |
d38ceaf9 | 100 | */ |
72a7ec5c CK |
101 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
102 | unsigned level) | |
d38ceaf9 | 103 | { |
72a7ec5c CK |
104 | if (level == 0) |
105 | /* For the root directory */ | |
106 | return adev->vm_manager.max_pfn >> | |
36b32a68 ZJ |
107 | (adev->vm_manager.block_size * |
108 | adev->vm_manager.num_level); | |
72a7ec5c CK |
109 | else if (level == adev->vm_manager.num_level) |
110 | /* For the page tables on the leaves */ | |
36b32a68 | 111 | return AMDGPU_VM_PTE_COUNT(adev); |
72a7ec5c CK |
112 | else |
113 | /* Everything in between */ | |
36b32a68 | 114 | return 1 << adev->vm_manager.block_size; |
d38ceaf9 AD |
115 | } |
116 | ||
117 | /** | |
72a7ec5c | 118 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
119 | * |
120 | * @adev: amdgpu_device pointer | |
121 | * | |
72a7ec5c | 122 | * Calculate the size of the BO for a page directory or page table in bytes. |
d38ceaf9 | 123 | */ |
72a7ec5c | 124 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 125 | { |
72a7ec5c | 126 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
127 | } |
128 | ||
129 | /** | |
56467ebf | 130 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
131 | * |
132 | * @vm: vm providing the BOs | |
3c0eea6c | 133 | * @validated: head of validation list |
56467ebf | 134 | * @entry: entry to add |
d38ceaf9 AD |
135 | * |
136 | * Add the page directory to the list of BOs to | |
56467ebf | 137 | * validate for command submission. |
d38ceaf9 | 138 | */ |
56467ebf CK |
139 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
140 | struct list_head *validated, | |
141 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 142 | { |
67003a15 | 143 | entry->robj = vm->root.bo; |
56467ebf | 144 | entry->priority = 0; |
67003a15 | 145 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 146 | entry->tv.shared = true; |
2f568dbd | 147 | entry->user_pages = NULL; |
56467ebf CK |
148 | list_add(&entry->tv.head, validated); |
149 | } | |
d38ceaf9 | 150 | |
670fecc8 CK |
151 | /** |
152 | * amdgpu_vm_validate_layer - validate a single page table level | |
153 | * | |
154 | * @parent: parent page table level | |
155 | * @validate: callback to do the validation | |
156 | * @param: parameter for the validation callback | |
157 | * | |
158 | * Validate the page table BOs on command submission if neccessary. | |
159 | */ | |
160 | static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent, | |
161 | int (*validate)(void *, struct amdgpu_bo *), | |
162 | void *param) | |
163 | { | |
164 | unsigned i; | |
165 | int r; | |
166 | ||
167 | if (!parent->entries) | |
168 | return 0; | |
169 | ||
170 | for (i = 0; i <= parent->last_entry_used; ++i) { | |
171 | struct amdgpu_vm_pt *entry = &parent->entries[i]; | |
172 | ||
173 | if (!entry->bo) | |
174 | continue; | |
175 | ||
176 | r = validate(param, entry->bo); | |
177 | if (r) | |
178 | return r; | |
179 | ||
180 | /* | |
181 | * Recurse into the sub directory. This is harmless because we | |
182 | * have only a maximum of 5 layers. | |
183 | */ | |
184 | r = amdgpu_vm_validate_level(entry, validate, param); | |
185 | if (r) | |
186 | return r; | |
187 | } | |
188 | ||
189 | return r; | |
190 | } | |
191 | ||
56467ebf | 192 | /** |
f7da30d9 | 193 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
56467ebf | 194 | * |
5a712a87 | 195 | * @adev: amdgpu device pointer |
56467ebf | 196 | * @vm: vm providing the BOs |
f7da30d9 CK |
197 | * @validate: callback to do the validation |
198 | * @param: parameter for the validation callback | |
d38ceaf9 | 199 | * |
f7da30d9 | 200 | * Validate the page table BOs on command submission if neccessary. |
d38ceaf9 | 201 | */ |
f7da30d9 CK |
202 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
203 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
204 | void *param) | |
d38ceaf9 | 205 | { |
5a712a87 | 206 | uint64_t num_evictions; |
d38ceaf9 | 207 | |
5a712a87 CK |
208 | /* We only need to validate the page tables |
209 | * if they aren't already valid. | |
210 | */ | |
211 | num_evictions = atomic64_read(&adev->num_evictions); | |
212 | if (num_evictions == vm->last_eviction_counter) | |
f7da30d9 | 213 | return 0; |
5a712a87 | 214 | |
670fecc8 | 215 | return amdgpu_vm_validate_level(&vm->root, validate, param); |
eceb8a15 CK |
216 | } |
217 | ||
218 | /** | |
d711e139 | 219 | * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail |
eceb8a15 CK |
220 | * |
221 | * @adev: amdgpu device instance | |
222 | * @vm: vm providing the BOs | |
223 | * | |
224 | * Move the PT BOs to the tail of the LRU. | |
225 | */ | |
d711e139 | 226 | static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent) |
eceb8a15 | 227 | { |
eceb8a15 CK |
228 | unsigned i; |
229 | ||
d711e139 CK |
230 | if (!parent->entries) |
231 | return; | |
eceb8a15 | 232 | |
d711e139 CK |
233 | for (i = 0; i <= parent->last_entry_used; ++i) { |
234 | struct amdgpu_vm_pt *entry = &parent->entries[i]; | |
235 | ||
236 | if (!entry->bo) | |
eceb8a15 CK |
237 | continue; |
238 | ||
d711e139 CK |
239 | ttm_bo_move_to_lru_tail(&entry->bo->tbo); |
240 | amdgpu_vm_move_level_in_lru(entry); | |
eceb8a15 | 241 | } |
d711e139 CK |
242 | } |
243 | ||
244 | /** | |
245 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
246 | * | |
247 | * @adev: amdgpu device instance | |
248 | * @vm: vm providing the BOs | |
249 | * | |
250 | * Move the PT BOs to the tail of the LRU. | |
251 | */ | |
252 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
253 | struct amdgpu_vm *vm) | |
254 | { | |
255 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
256 | ||
257 | spin_lock(&glob->lru_lock); | |
258 | amdgpu_vm_move_level_in_lru(&vm->root); | |
eceb8a15 | 259 | spin_unlock(&glob->lru_lock); |
d38ceaf9 AD |
260 | } |
261 | ||
f566ceb1 CK |
262 | /** |
263 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels | |
264 | * | |
265 | * @adev: amdgpu_device pointer | |
266 | * @vm: requested vm | |
267 | * @saddr: start of the address range | |
268 | * @eaddr: end of the address range | |
269 | * | |
270 | * Make sure the page directories and page tables are allocated | |
271 | */ | |
272 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
273 | struct amdgpu_vm *vm, | |
274 | struct amdgpu_vm_pt *parent, | |
275 | uint64_t saddr, uint64_t eaddr, | |
276 | unsigned level) | |
277 | { | |
278 | unsigned shift = (adev->vm_manager.num_level - level) * | |
36b32a68 | 279 | adev->vm_manager.block_size; |
f566ceb1 CK |
280 | unsigned pt_idx, from, to; |
281 | int r; | |
3c824172 | 282 | u64 flags; |
f566ceb1 CK |
283 | |
284 | if (!parent->entries) { | |
285 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
286 | ||
2098105e MH |
287 | parent->entries = kvmalloc_array(num_entries, |
288 | sizeof(struct amdgpu_vm_pt), | |
289 | GFP_KERNEL | __GFP_ZERO); | |
f566ceb1 CK |
290 | if (!parent->entries) |
291 | return -ENOMEM; | |
292 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
293 | } | |
294 | ||
1866bac8 FK |
295 | from = saddr >> shift; |
296 | to = eaddr >> shift; | |
297 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
298 | to >= amdgpu_vm_num_entries(adev, level)) | |
299 | return -EINVAL; | |
f566ceb1 CK |
300 | |
301 | if (to > parent->last_entry_used) | |
302 | parent->last_entry_used = to; | |
303 | ||
304 | ++level; | |
1866bac8 FK |
305 | saddr = saddr & ((1 << shift) - 1); |
306 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 | 307 | |
3c824172 HK |
308 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
309 | AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
310 | if (vm->use_cpu_for_update) | |
311 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
312 | else | |
313 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
314 | AMDGPU_GEM_CREATE_SHADOW); | |
315 | ||
f566ceb1 CK |
316 | /* walk over the address space and allocate the page tables */ |
317 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
318 | struct reservation_object *resv = vm->root.bo->tbo.resv; | |
319 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
320 | struct amdgpu_bo *pt; | |
321 | ||
322 | if (!entry->bo) { | |
323 | r = amdgpu_bo_create(adev, | |
324 | amdgpu_vm_bo_size(adev, level), | |
325 | AMDGPU_GPU_PAGE_SIZE, true, | |
326 | AMDGPU_GEM_DOMAIN_VRAM, | |
3c824172 | 327 | flags, |
f566ceb1 CK |
328 | NULL, resv, &pt); |
329 | if (r) | |
330 | return r; | |
331 | ||
332 | /* Keep a reference to the root directory to avoid | |
333 | * freeing them up in the wrong order. | |
334 | */ | |
335 | pt->parent = amdgpu_bo_ref(vm->root.bo); | |
336 | ||
337 | entry->bo = pt; | |
338 | entry->addr = 0; | |
339 | } | |
340 | ||
341 | if (level < adev->vm_manager.num_level) { | |
1866bac8 FK |
342 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
343 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
344 | ((1 << shift) - 1); | |
345 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
346 | sub_eaddr, level); | |
f566ceb1 CK |
347 | if (r) |
348 | return r; | |
349 | } | |
350 | } | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
663e4577 CK |
355 | /** |
356 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
357 | * | |
358 | * @adev: amdgpu_device pointer | |
359 | * @vm: VM to allocate page tables for | |
360 | * @saddr: Start address which needs to be allocated | |
361 | * @size: Size from start address we need. | |
362 | * | |
363 | * Make sure the page tables are allocated. | |
364 | */ | |
365 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
366 | struct amdgpu_vm *vm, | |
367 | uint64_t saddr, uint64_t size) | |
368 | { | |
22770e5a | 369 | uint64_t last_pfn; |
663e4577 | 370 | uint64_t eaddr; |
663e4577 CK |
371 | |
372 | /* validate the parameters */ | |
373 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
374 | return -EINVAL; | |
375 | ||
376 | eaddr = saddr + size - 1; | |
377 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
378 | if (last_pfn >= adev->vm_manager.max_pfn) { | |
22770e5a | 379 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", |
663e4577 CK |
380 | last_pfn, adev->vm_manager.max_pfn); |
381 | return -EINVAL; | |
382 | } | |
383 | ||
384 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
385 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
386 | ||
f566ceb1 | 387 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); |
663e4577 CK |
388 | } |
389 | ||
641e9400 CK |
390 | /** |
391 | * amdgpu_vm_had_gpu_reset - check if reset occured since last use | |
392 | * | |
393 | * @adev: amdgpu_device pointer | |
394 | * @id: VMID structure | |
395 | * | |
396 | * Check if GPU reset occured since last use of the VMID. | |
397 | */ | |
398 | static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev, | |
399 | struct amdgpu_vm_id *id) | |
192b7dcb CZ |
400 | { |
401 | return id->current_gpu_reset_count != | |
641e9400 | 402 | atomic_read(&adev->gpu_reset_counter); |
192b7dcb CZ |
403 | } |
404 | ||
7a63eb23 CZ |
405 | static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub) |
406 | { | |
407 | return !!vm->reserved_vmid[vmhub]; | |
408 | } | |
409 | ||
410 | /* idr_mgr->lock must be held */ | |
411 | static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, | |
412 | struct amdgpu_ring *ring, | |
413 | struct amdgpu_sync *sync, | |
414 | struct dma_fence *fence, | |
415 | struct amdgpu_job *job) | |
416 | { | |
417 | struct amdgpu_device *adev = ring->adev; | |
418 | unsigned vmhub = ring->funcs->vmhub; | |
419 | uint64_t fence_context = adev->fence_context + ring->idx; | |
420 | struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub]; | |
421 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
422 | struct dma_fence *updates = sync->last_vm_update; | |
423 | int r = 0; | |
424 | struct dma_fence *flushed, *tmp; | |
425 | bool needs_flush = false; | |
426 | ||
427 | flushed = id->flushed_updates; | |
428 | if ((amdgpu_vm_had_gpu_reset(adev, id)) || | |
429 | (atomic64_read(&id->owner) != vm->client_id) || | |
430 | (job->vm_pd_addr != id->pd_gpu_addr) || | |
431 | (updates && (!flushed || updates->context != flushed->context || | |
432 | dma_fence_is_later(updates, flushed))) || | |
433 | (!id->last_flush || (id->last_flush->context != fence_context && | |
434 | !dma_fence_is_signaled(id->last_flush)))) { | |
435 | needs_flush = true; | |
436 | /* to prevent one context starved by another context */ | |
437 | id->pd_gpu_addr = 0; | |
438 | tmp = amdgpu_sync_peek_fence(&id->active, ring); | |
439 | if (tmp) { | |
440 | r = amdgpu_sync_fence(adev, sync, tmp); | |
441 | return r; | |
442 | } | |
443 | } | |
444 | ||
445 | /* Good we can use this VMID. Remember this submission as | |
446 | * user of the VMID. | |
447 | */ | |
448 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
449 | if (r) | |
450 | goto out; | |
451 | ||
452 | if (updates && (!flushed || updates->context != flushed->context || | |
453 | dma_fence_is_later(updates, flushed))) { | |
454 | dma_fence_put(id->flushed_updates); | |
455 | id->flushed_updates = dma_fence_get(updates); | |
456 | } | |
457 | id->pd_gpu_addr = job->vm_pd_addr; | |
7a63eb23 CZ |
458 | atomic64_set(&id->owner, vm->client_id); |
459 | job->vm_needs_flush = needs_flush; | |
460 | if (needs_flush) { | |
461 | dma_fence_put(id->last_flush); | |
462 | id->last_flush = NULL; | |
463 | } | |
464 | job->vm_id = id - id_mgr->ids; | |
465 | trace_amdgpu_vm_grab_id(vm, ring, job); | |
466 | out: | |
467 | return r; | |
468 | } | |
469 | ||
d38ceaf9 AD |
470 | /** |
471 | * amdgpu_vm_grab_id - allocate the next free VMID | |
472 | * | |
d38ceaf9 | 473 | * @vm: vm to allocate id for |
7f8a5290 CK |
474 | * @ring: ring we want to submit job to |
475 | * @sync: sync object where we add dependencies | |
94dd0a4a | 476 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 477 | * |
7f8a5290 | 478 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 479 | */ |
7f8a5290 | 480 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
f54d1867 | 481 | struct amdgpu_sync *sync, struct dma_fence *fence, |
fd53be30 | 482 | struct amdgpu_job *job) |
d38ceaf9 | 483 | { |
d38ceaf9 | 484 | struct amdgpu_device *adev = ring->adev; |
2e819849 | 485 | unsigned vmhub = ring->funcs->vmhub; |
7645670d | 486 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
090b767e | 487 | uint64_t fence_context = adev->fence_context + ring->idx; |
f54d1867 | 488 | struct dma_fence *updates = sync->last_vm_update; |
8d76001e | 489 | struct amdgpu_vm_id *id, *idle; |
f54d1867 | 490 | struct dma_fence **fences; |
1fbb2e92 CK |
491 | unsigned i; |
492 | int r = 0; | |
493 | ||
7a63eb23 CZ |
494 | mutex_lock(&id_mgr->lock); |
495 | if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) { | |
496 | r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job); | |
497 | mutex_unlock(&id_mgr->lock); | |
498 | return r; | |
499 | } | |
7645670d | 500 | fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); |
7a63eb23 CZ |
501 | if (!fences) { |
502 | mutex_unlock(&id_mgr->lock); | |
1fbb2e92 | 503 | return -ENOMEM; |
7a63eb23 | 504 | } |
36fd7c5c | 505 | /* Check if we have an idle VMID */ |
1fbb2e92 | 506 | i = 0; |
7645670d | 507 | list_for_each_entry(idle, &id_mgr->ids_lru, list) { |
1fbb2e92 CK |
508 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
509 | if (!fences[i]) | |
36fd7c5c | 510 | break; |
1fbb2e92 | 511 | ++i; |
36fd7c5c CK |
512 | } |
513 | ||
1fbb2e92 | 514 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
7645670d | 515 | if (&idle->list == &id_mgr->ids_lru) { |
1fbb2e92 CK |
516 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
517 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
f54d1867 | 518 | struct dma_fence_array *array; |
1fbb2e92 CK |
519 | unsigned j; |
520 | ||
521 | for (j = 0; j < i; ++j) | |
f54d1867 | 522 | dma_fence_get(fences[j]); |
1fbb2e92 | 523 | |
f54d1867 | 524 | array = dma_fence_array_create(i, fences, fence_context, |
1fbb2e92 CK |
525 | seqno, true); |
526 | if (!array) { | |
527 | for (j = 0; j < i; ++j) | |
f54d1867 | 528 | dma_fence_put(fences[j]); |
1fbb2e92 CK |
529 | kfree(fences); |
530 | r = -ENOMEM; | |
531 | goto error; | |
532 | } | |
533 | ||
534 | ||
535 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
f54d1867 | 536 | dma_fence_put(&array->base); |
1fbb2e92 CK |
537 | if (r) |
538 | goto error; | |
539 | ||
7645670d | 540 | mutex_unlock(&id_mgr->lock); |
1fbb2e92 CK |
541 | return 0; |
542 | ||
543 | } | |
544 | kfree(fences); | |
545 | ||
87c910d8 | 546 | job->vm_needs_flush = false; |
1fbb2e92 | 547 | /* Check if we can use a VMID already assigned to this VM */ |
7645670d | 548 | list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) { |
f54d1867 | 549 | struct dma_fence *flushed; |
87c910d8 | 550 | bool needs_flush = false; |
1fbb2e92 | 551 | |
1fbb2e92 | 552 | /* Check all the prerequisites to using this VMID */ |
641e9400 | 553 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
6adb0513 | 554 | continue; |
1fbb2e92 CK |
555 | |
556 | if (atomic64_read(&id->owner) != vm->client_id) | |
557 | continue; | |
558 | ||
fd53be30 | 559 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
560 | continue; |
561 | ||
87c910d8 CK |
562 | if (!id->last_flush || |
563 | (id->last_flush->context != fence_context && | |
564 | !dma_fence_is_signaled(id->last_flush))) | |
565 | needs_flush = true; | |
1fbb2e92 CK |
566 | |
567 | flushed = id->flushed_updates; | |
87c910d8 CK |
568 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) |
569 | needs_flush = true; | |
570 | ||
571 | /* Concurrent flushes are only possible starting with Vega10 */ | |
572 | if (adev->asic_type < CHIP_VEGA10 && needs_flush) | |
1fbb2e92 CK |
573 | continue; |
574 | ||
3dab83be CK |
575 | /* Good we can use this VMID. Remember this submission as |
576 | * user of the VMID. | |
577 | */ | |
1fbb2e92 CK |
578 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
579 | if (r) | |
580 | goto error; | |
8d76001e | 581 | |
87c910d8 CK |
582 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) { |
583 | dma_fence_put(id->flushed_updates); | |
584 | id->flushed_updates = dma_fence_get(updates); | |
585 | } | |
8d76001e | 586 | |
87c910d8 CK |
587 | if (needs_flush) |
588 | goto needs_flush; | |
589 | else | |
590 | goto no_flush_needed; | |
8d76001e | 591 | |
4f618e73 | 592 | }; |
8d76001e | 593 | |
1fbb2e92 CK |
594 | /* Still no ID to use? Then use the idle one found earlier */ |
595 | id = idle; | |
8e9fbeb5 | 596 | |
1fbb2e92 CK |
597 | /* Remember this submission as user of the VMID */ |
598 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
599 | if (r) |
600 | goto error; | |
94dd0a4a | 601 | |
87c910d8 | 602 | id->pd_gpu_addr = job->vm_pd_addr; |
f54d1867 CW |
603 | dma_fence_put(id->flushed_updates); |
604 | id->flushed_updates = dma_fence_get(updates); | |
0ea54b9b | 605 | atomic64_set(&id->owner, vm->client_id); |
d38ceaf9 | 606 | |
87c910d8 CK |
607 | needs_flush: |
608 | job->vm_needs_flush = true; | |
609 | dma_fence_put(id->last_flush); | |
610 | id->last_flush = NULL; | |
611 | ||
612 | no_flush_needed: | |
613 | list_move_tail(&id->list, &id_mgr->ids_lru); | |
614 | ||
7645670d | 615 | job->vm_id = id - id_mgr->ids; |
c5296d14 | 616 | trace_amdgpu_vm_grab_id(vm, ring, job); |
832a902f CK |
617 | |
618 | error: | |
7645670d | 619 | mutex_unlock(&id_mgr->lock); |
a9a78b32 | 620 | return r; |
d38ceaf9 AD |
621 | } |
622 | ||
1e9ef26f CZ |
623 | static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev, |
624 | struct amdgpu_vm *vm, | |
625 | unsigned vmhub) | |
626 | { | |
627 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
628 | ||
629 | mutex_lock(&id_mgr->lock); | |
630 | if (vm->reserved_vmid[vmhub]) { | |
631 | list_add(&vm->reserved_vmid[vmhub]->list, | |
632 | &id_mgr->ids_lru); | |
633 | vm->reserved_vmid[vmhub] = NULL; | |
c3505770 | 634 | atomic_dec(&id_mgr->reserved_vmid_num); |
1e9ef26f CZ |
635 | } |
636 | mutex_unlock(&id_mgr->lock); | |
637 | } | |
638 | ||
639 | static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev, | |
640 | struct amdgpu_vm *vm, | |
641 | unsigned vmhub) | |
642 | { | |
643 | struct amdgpu_vm_id_manager *id_mgr; | |
644 | struct amdgpu_vm_id *idle; | |
645 | int r = 0; | |
646 | ||
647 | id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
648 | mutex_lock(&id_mgr->lock); | |
649 | if (vm->reserved_vmid[vmhub]) | |
650 | goto unlock; | |
c3505770 CZ |
651 | if (atomic_inc_return(&id_mgr->reserved_vmid_num) > |
652 | AMDGPU_VM_MAX_RESERVED_VMID) { | |
653 | DRM_ERROR("Over limitation of reserved vmid\n"); | |
654 | atomic_dec(&id_mgr->reserved_vmid_num); | |
655 | r = -EINVAL; | |
656 | goto unlock; | |
657 | } | |
1e9ef26f CZ |
658 | /* Select the first entry VMID */ |
659 | idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list); | |
660 | list_del_init(&idle->list); | |
661 | vm->reserved_vmid[vmhub] = idle; | |
662 | mutex_unlock(&id_mgr->lock); | |
663 | ||
664 | return 0; | |
665 | unlock: | |
666 | mutex_unlock(&id_mgr->lock); | |
667 | return r; | |
668 | } | |
669 | ||
e59c0205 AX |
670 | /** |
671 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
672 | * | |
673 | * @adev: amdgpu_device pointer | |
674 | */ | |
675 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 676 | { |
a1255107 | 677 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
678 | bool has_compute_vm_bug; |
679 | struct amdgpu_ring *ring; | |
680 | int i; | |
93dcc37d | 681 | |
e59c0205 | 682 | has_compute_vm_bug = false; |
93dcc37d AD |
683 | |
684 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
e59c0205 AX |
685 | if (ip_block) { |
686 | /* Compute has a VM bug for GFX version < 7. | |
687 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
688 | if (ip_block->version->major <= 7) | |
689 | has_compute_vm_bug = true; | |
690 | else if (ip_block->version->major == 8) | |
691 | if (adev->gfx.mec_fw_version < 673) | |
692 | has_compute_vm_bug = true; | |
693 | } | |
93dcc37d | 694 | |
e59c0205 AX |
695 | for (i = 0; i < adev->num_rings; i++) { |
696 | ring = adev->rings[i]; | |
697 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
698 | /* only compute rings */ | |
699 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 700 | else |
e59c0205 | 701 | ring->has_compute_vm_bug = false; |
93dcc37d | 702 | } |
93dcc37d AD |
703 | } |
704 | ||
b9bf33d5 CZ |
705 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
706 | struct amdgpu_job *job) | |
e60f8db5 | 707 | { |
b9bf33d5 CZ |
708 | struct amdgpu_device *adev = ring->adev; |
709 | unsigned vmhub = ring->funcs->vmhub; | |
710 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
711 | struct amdgpu_vm_id *id; | |
712 | bool gds_switch_needed; | |
e59c0205 | 713 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 CZ |
714 | |
715 | if (job->vm_id == 0) | |
716 | return false; | |
717 | id = &id_mgr->ids[job->vm_id]; | |
718 | gds_switch_needed = ring->funcs->emit_gds_switch && ( | |
719 | id->gds_base != job->gds_base || | |
720 | id->gds_size != job->gds_size || | |
721 | id->gws_base != job->gws_base || | |
722 | id->gws_size != job->gws_size || | |
723 | id->oa_base != job->oa_base || | |
724 | id->oa_size != job->oa_size); | |
e60f8db5 | 725 | |
b9bf33d5 CZ |
726 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
727 | return true; | |
e60f8db5 | 728 | |
bb37b67d | 729 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
730 | } |
731 | ||
9a4b7d4c HK |
732 | static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) |
733 | { | |
734 | return (adev->mc.real_vram_size == adev->mc.visible_vram_size); | |
e60f8db5 AX |
735 | } |
736 | ||
d38ceaf9 AD |
737 | /** |
738 | * amdgpu_vm_flush - hardware flush the vm | |
739 | * | |
740 | * @ring: ring to use for flush | |
cffadc83 | 741 | * @vm_id: vmid number to use |
4ff37a83 | 742 | * @pd_addr: address of the page directory |
d38ceaf9 | 743 | * |
4ff37a83 | 744 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 745 | */ |
8fdf074f | 746 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 747 | { |
971fe9a9 | 748 | struct amdgpu_device *adev = ring->adev; |
7645670d CK |
749 | unsigned vmhub = ring->funcs->vmhub; |
750 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
751 | struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id]; | |
d564a06e | 752 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
753 | id->gds_base != job->gds_base || |
754 | id->gds_size != job->gds_size || | |
755 | id->gws_base != job->gws_base || | |
756 | id->gws_size != job->gws_size || | |
757 | id->oa_base != job->oa_base || | |
758 | id->oa_size != job->oa_size); | |
de37e68a | 759 | bool vm_flush_needed = job->vm_needs_flush; |
c0e51931 | 760 | unsigned patch_offset = 0; |
41d9eb2c | 761 | int r; |
d564a06e | 762 | |
f7d015b9 CK |
763 | if (amdgpu_vm_had_gpu_reset(adev, id)) { |
764 | gds_switch_needed = true; | |
765 | vm_flush_needed = true; | |
766 | } | |
971fe9a9 | 767 | |
8fdf074f | 768 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 769 | return 0; |
41d9eb2c | 770 | |
c0e51931 CK |
771 | if (ring->funcs->init_cond_exec) |
772 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 773 | |
8fdf074f ML |
774 | if (need_pipe_sync) |
775 | amdgpu_ring_emit_pipeline_sync(ring); | |
776 | ||
f7d015b9 | 777 | if (ring->funcs->emit_vm_flush && vm_flush_needed) { |
c0e51931 | 778 | struct dma_fence *fence; |
41d9eb2c | 779 | |
9a94f5a5 CK |
780 | trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr); |
781 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
e9d672b2 | 782 | |
c0e51931 CK |
783 | r = amdgpu_fence_emit(ring, &fence); |
784 | if (r) | |
785 | return r; | |
e9d672b2 | 786 | |
7645670d | 787 | mutex_lock(&id_mgr->lock); |
c0e51931 CK |
788 | dma_fence_put(id->last_flush); |
789 | id->last_flush = fence; | |
bea39672 | 790 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
7645670d | 791 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 792 | } |
e9d672b2 | 793 | |
7c4378f4 | 794 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
795 | id->gds_base = job->gds_base; |
796 | id->gds_size = job->gds_size; | |
797 | id->gws_base = job->gws_base; | |
798 | id->gws_size = job->gws_size; | |
799 | id->oa_base = job->oa_base; | |
800 | id->oa_size = job->oa_size; | |
801 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base, | |
802 | job->gds_size, job->gws_base, | |
803 | job->gws_size, job->oa_base, | |
804 | job->oa_size); | |
805 | } | |
806 | ||
807 | if (ring->funcs->patch_cond_exec) | |
808 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
809 | ||
810 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
811 | if (ring->funcs->emit_switch_buffer) { | |
812 | amdgpu_ring_emit_switch_buffer(ring); | |
813 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 814 | } |
41d9eb2c | 815 | return 0; |
971fe9a9 CK |
816 | } |
817 | ||
818 | /** | |
819 | * amdgpu_vm_reset_id - reset VMID to zero | |
820 | * | |
821 | * @adev: amdgpu device structure | |
822 | * @vm_id: vmid number to use | |
823 | * | |
824 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
825 | */ | |
7645670d CK |
826 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
827 | unsigned vmid) | |
971fe9a9 | 828 | { |
7645670d CK |
829 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
830 | struct amdgpu_vm_id *id = &id_mgr->ids[vmid]; | |
bcb1ba35 | 831 | |
b3c85a0f | 832 | atomic64_set(&id->owner, 0); |
bcb1ba35 CK |
833 | id->gds_base = 0; |
834 | id->gds_size = 0; | |
835 | id->gws_base = 0; | |
836 | id->gws_size = 0; | |
837 | id->oa_base = 0; | |
838 | id->oa_size = 0; | |
d38ceaf9 AD |
839 | } |
840 | ||
b3c85a0f CK |
841 | /** |
842 | * amdgpu_vm_reset_all_id - reset VMID to zero | |
843 | * | |
844 | * @adev: amdgpu device structure | |
845 | * | |
846 | * Reset VMID to force flush on next use | |
847 | */ | |
848 | void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev) | |
849 | { | |
850 | unsigned i, j; | |
851 | ||
852 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
853 | struct amdgpu_vm_id_manager *id_mgr = | |
854 | &adev->vm_manager.id_mgr[i]; | |
855 | ||
856 | for (j = 1; j < id_mgr->num_ids; ++j) | |
857 | amdgpu_vm_reset_id(adev, i, j); | |
858 | } | |
859 | } | |
860 | ||
d38ceaf9 AD |
861 | /** |
862 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
863 | * | |
864 | * @vm: requested vm | |
865 | * @bo: requested buffer object | |
866 | * | |
8843dbbb | 867 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
868 | * Search inside the @bos vm list for the requested vm |
869 | * Returns the found bo_va or NULL if none is found | |
870 | * | |
871 | * Object has to be reserved! | |
872 | */ | |
873 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
874 | struct amdgpu_bo *bo) | |
875 | { | |
876 | struct amdgpu_bo_va *bo_va; | |
877 | ||
878 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
879 | if (bo_va->vm == vm) { | |
880 | return bo_va; | |
881 | } | |
882 | } | |
883 | return NULL; | |
884 | } | |
885 | ||
886 | /** | |
afef8b8f | 887 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 888 | * |
29efc4f5 | 889 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
890 | * @pe: addr of the page entry |
891 | * @addr: dst addr to write into pe | |
892 | * @count: number of page entries to update | |
893 | * @incr: increase next addr by incr bytes | |
894 | * @flags: hw access flags | |
d38ceaf9 AD |
895 | * |
896 | * Traces the parameters and calls the right asic functions | |
897 | * to setup the page table using the DMA. | |
898 | */ | |
afef8b8f CK |
899 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
900 | uint64_t pe, uint64_t addr, | |
901 | unsigned count, uint32_t incr, | |
6b777607 | 902 | uint64_t flags) |
d38ceaf9 | 903 | { |
ec2f05f0 | 904 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 905 | |
afef8b8f | 906 | if (count < 3) { |
de9ea7bd CK |
907 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
908 | addr | flags, count, incr); | |
d38ceaf9 AD |
909 | |
910 | } else { | |
27c5f36f | 911 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
912 | count, incr, flags); |
913 | } | |
914 | } | |
915 | ||
afef8b8f CK |
916 | /** |
917 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
918 | * | |
919 | * @params: see amdgpu_pte_update_params definition | |
920 | * @pe: addr of the page entry | |
921 | * @addr: dst addr to write into pe | |
922 | * @count: number of page entries to update | |
923 | * @incr: increase next addr by incr bytes | |
924 | * @flags: hw access flags | |
925 | * | |
926 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
927 | */ | |
928 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
929 | uint64_t pe, uint64_t addr, | |
930 | unsigned count, uint32_t incr, | |
6b777607 | 931 | uint64_t flags) |
afef8b8f | 932 | { |
ec2f05f0 | 933 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 934 | |
ec2f05f0 CK |
935 | |
936 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
937 | ||
938 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
939 | } |
940 | ||
d38ceaf9 | 941 | /** |
b07c9d2a | 942 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 943 | * |
b07c9d2a | 944 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
945 | * @addr: the unmapped addr |
946 | * | |
947 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 948 | * to and return the pointer for the page table entry. |
d38ceaf9 | 949 | */ |
de9ea7bd | 950 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
951 | { |
952 | uint64_t result; | |
953 | ||
de9ea7bd CK |
954 | /* page table offset */ |
955 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 956 | |
de9ea7bd CK |
957 | /* in case cpu page size != gpu page size*/ |
958 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 959 | |
b07c9d2a | 960 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
961 | |
962 | return result; | |
963 | } | |
964 | ||
3c824172 HK |
965 | /** |
966 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU | |
967 | * | |
968 | * @params: see amdgpu_pte_update_params definition | |
969 | * @pe: kmap addr of the page entry | |
970 | * @addr: dst addr to write into pe | |
971 | * @count: number of page entries to update | |
972 | * @incr: increase next addr by incr bytes | |
973 | * @flags: hw access flags | |
974 | * | |
975 | * Write count number of PT/PD entries directly. | |
976 | */ | |
977 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, | |
978 | uint64_t pe, uint64_t addr, | |
979 | unsigned count, uint32_t incr, | |
980 | uint64_t flags) | |
981 | { | |
982 | unsigned int i; | |
b4d42511 | 983 | uint64_t value; |
3c824172 HK |
984 | |
985 | for (i = 0; i < count; i++) { | |
b4d42511 HK |
986 | value = params->pages_addr ? |
987 | amdgpu_vm_map_gart(params->pages_addr, addr) : | |
988 | addr; | |
a1924005 | 989 | amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe, |
b4d42511 | 990 | i, value, flags); |
3c824172 HK |
991 | addr += incr; |
992 | } | |
993 | ||
994 | /* Flush HDP */ | |
995 | mb(); | |
996 | amdgpu_gart_flush_gpu_tlb(params->adev, 0); | |
997 | } | |
998 | ||
999 | static int amdgpu_vm_bo_wait(struct amdgpu_device *adev, struct amdgpu_bo *bo) | |
1000 | { | |
1001 | struct amdgpu_sync sync; | |
1002 | int r; | |
1003 | ||
1004 | amdgpu_sync_create(&sync); | |
1005 | amdgpu_sync_resv(adev, &sync, bo->tbo.resv, AMDGPU_FENCE_OWNER_VM); | |
1006 | r = amdgpu_sync_wait(&sync, true); | |
1007 | amdgpu_sync_free(&sync); | |
1008 | ||
1009 | return r; | |
1010 | } | |
1011 | ||
f8991bab | 1012 | /* |
194d2161 | 1013 | * amdgpu_vm_update_level - update a single level in the hierarchy |
f8991bab CK |
1014 | * |
1015 | * @adev: amdgpu_device pointer | |
1016 | * @vm: requested vm | |
194d2161 | 1017 | * @parent: parent directory |
f8991bab | 1018 | * |
194d2161 | 1019 | * Makes sure all entries in @parent are up to date. |
f8991bab CK |
1020 | * Returns 0 for success, error for failure. |
1021 | */ | |
194d2161 CK |
1022 | static int amdgpu_vm_update_level(struct amdgpu_device *adev, |
1023 | struct amdgpu_vm *vm, | |
1024 | struct amdgpu_vm_pt *parent, | |
1025 | unsigned level) | |
d38ceaf9 | 1026 | { |
f8991bab | 1027 | struct amdgpu_bo *shadow; |
a1924005 HK |
1028 | struct amdgpu_ring *ring = NULL; |
1029 | uint64_t pd_addr, shadow_addr = 0; | |
194d2161 | 1030 | uint32_t incr = amdgpu_vm_bo_size(adev, level + 1); |
f8991bab | 1031 | uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; |
a1924005 | 1032 | unsigned count = 0, pt_idx, ndw = 0; |
d71518b5 | 1033 | struct amdgpu_job *job; |
29efc4f5 | 1034 | struct amdgpu_pte_update_params params; |
f54d1867 | 1035 | struct dma_fence *fence = NULL; |
d5fc5e82 | 1036 | |
d38ceaf9 AD |
1037 | int r; |
1038 | ||
194d2161 CK |
1039 | if (!parent->entries) |
1040 | return 0; | |
2d55e45a | 1041 | |
3c824172 HK |
1042 | memset(¶ms, 0, sizeof(params)); |
1043 | params.adev = adev; | |
1044 | shadow = parent->bo->shadow; | |
d38ceaf9 | 1045 | |
3c824172 HK |
1046 | WARN_ON(vm->use_cpu_for_update && shadow); |
1047 | if (vm->use_cpu_for_update && !shadow) { | |
1048 | r = amdgpu_bo_kmap(parent->bo, (void **)&pd_addr); | |
1049 | if (r) | |
1050 | return r; | |
1051 | r = amdgpu_vm_bo_wait(adev, parent->bo); | |
1052 | if (unlikely(r)) { | |
1053 | amdgpu_bo_kunmap(parent->bo); | |
1054 | return r; | |
1055 | } | |
1056 | params.func = amdgpu_vm_cpu_set_ptes; | |
1057 | } else { | |
1058 | if (shadow) { | |
1059 | r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); | |
1060 | if (r) | |
1061 | return r; | |
1062 | } | |
1063 | ring = container_of(vm->entity.sched, struct amdgpu_ring, | |
1064 | sched); | |
d38ceaf9 | 1065 | |
3c824172 HK |
1066 | /* padding, etc. */ |
1067 | ndw = 64; | |
194d2161 | 1068 | |
3c824172 HK |
1069 | /* assume the worst case */ |
1070 | ndw += parent->last_entry_used * 6; | |
1071 | ||
1072 | pd_addr = amdgpu_bo_gpu_offset(parent->bo); | |
1073 | ||
1074 | if (shadow) { | |
1075 | shadow_addr = amdgpu_bo_gpu_offset(shadow); | |
1076 | ndw *= 2; | |
1077 | } else { | |
1078 | shadow_addr = 0; | |
1079 | } | |
1080 | ||
1081 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
f8991bab CK |
1082 | if (r) |
1083 | return r; | |
f8991bab | 1084 | |
3c824172 HK |
1085 | params.ib = &job->ibs[0]; |
1086 | params.func = amdgpu_vm_do_set_ptes; | |
1087 | } | |
d71518b5 | 1088 | |
d38ceaf9 | 1089 | |
194d2161 CK |
1090 | /* walk over the address space and update the directory */ |
1091 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
1092 | struct amdgpu_bo *bo = parent->entries[pt_idx].bo; | |
d38ceaf9 AD |
1093 | uint64_t pde, pt; |
1094 | ||
1095 | if (bo == NULL) | |
1096 | continue; | |
1097 | ||
0fc8683e | 1098 | if (bo->shadow) { |
f8991bab | 1099 | struct amdgpu_bo *pt_shadow = bo->shadow; |
0fc8683e | 1100 | |
f8991bab CK |
1101 | r = amdgpu_ttm_bind(&pt_shadow->tbo, |
1102 | &pt_shadow->tbo.mem); | |
0fc8683e CK |
1103 | if (r) |
1104 | return r; | |
1105 | } | |
1106 | ||
d38ceaf9 | 1107 | pt = amdgpu_bo_gpu_offset(bo); |
53e2e91d | 1108 | pt = amdgpu_gart_get_vm_pde(adev, pt); |
194d2161 | 1109 | if (parent->entries[pt_idx].addr == pt) |
f8991bab CK |
1110 | continue; |
1111 | ||
194d2161 | 1112 | parent->entries[pt_idx].addr = pt; |
d38ceaf9 AD |
1113 | |
1114 | pde = pd_addr + pt_idx * 8; | |
1115 | if (((last_pde + 8 * count) != pde) || | |
96105e53 CK |
1116 | ((last_pt + incr * count) != pt) || |
1117 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
d38ceaf9 AD |
1118 | |
1119 | if (count) { | |
f8991bab | 1120 | if (shadow) |
3c824172 HK |
1121 | params.func(¶ms, |
1122 | last_shadow, | |
1123 | last_pt, count, | |
1124 | incr, | |
1125 | AMDGPU_PTE_VALID); | |
1126 | ||
1127 | params.func(¶ms, last_pde, | |
1128 | last_pt, count, incr, | |
1129 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
1130 | } |
1131 | ||
1132 | count = 1; | |
1133 | last_pde = pde; | |
f8991bab | 1134 | last_shadow = shadow_addr + pt_idx * 8; |
d38ceaf9 AD |
1135 | last_pt = pt; |
1136 | } else { | |
1137 | ++count; | |
1138 | } | |
1139 | } | |
1140 | ||
f8991bab | 1141 | if (count) { |
67003a15 | 1142 | if (vm->root.bo->shadow) |
3c824172 HK |
1143 | params.func(¶ms, last_shadow, last_pt, |
1144 | count, incr, AMDGPU_PTE_VALID); | |
f8991bab | 1145 | |
3c824172 HK |
1146 | params.func(¶ms, last_pde, last_pt, |
1147 | count, incr, AMDGPU_PTE_VALID); | |
f8991bab | 1148 | } |
d38ceaf9 | 1149 | |
3c824172 HK |
1150 | if (params.func == amdgpu_vm_cpu_set_ptes) |
1151 | amdgpu_bo_kunmap(parent->bo); | |
1152 | else if (params.ib->length_dw == 0) { | |
f8991bab | 1153 | amdgpu_job_free(job); |
194d2161 CK |
1154 | } else { |
1155 | amdgpu_ring_pad_ib(ring, params.ib); | |
1156 | amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv, | |
e86f9cee | 1157 | AMDGPU_FENCE_OWNER_VM); |
194d2161 CK |
1158 | if (shadow) |
1159 | amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv, | |
1160 | AMDGPU_FENCE_OWNER_VM); | |
05906dec | 1161 | |
194d2161 CK |
1162 | WARN_ON(params.ib->length_dw > ndw); |
1163 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
1164 | AMDGPU_FENCE_OWNER_VM, &fence); | |
1165 | if (r) | |
1166 | goto error_free; | |
1167 | ||
1168 | amdgpu_bo_fence(parent->bo, fence, true); | |
1169 | dma_fence_put(vm->last_dir_update); | |
1170 | vm->last_dir_update = dma_fence_get(fence); | |
1171 | dma_fence_put(fence); | |
1172 | } | |
1173 | /* | |
1174 | * Recurse into the subdirectories. This recursion is harmless because | |
1175 | * we only have a maximum of 5 layers. | |
1176 | */ | |
1177 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
1178 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
1179 | ||
1180 | if (!entry->bo) | |
1181 | continue; | |
d5fc5e82 | 1182 | |
194d2161 CK |
1183 | r = amdgpu_vm_update_level(adev, vm, entry, level + 1); |
1184 | if (r) | |
1185 | return r; | |
1186 | } | |
d38ceaf9 AD |
1187 | |
1188 | return 0; | |
d5fc5e82 CZ |
1189 | |
1190 | error_free: | |
d71518b5 | 1191 | amdgpu_job_free(job); |
4af9f07c | 1192 | return r; |
d38ceaf9 AD |
1193 | } |
1194 | ||
92456b93 CK |
1195 | /* |
1196 | * amdgpu_vm_invalidate_level - mark all PD levels as invalid | |
1197 | * | |
1198 | * @parent: parent PD | |
1199 | * | |
1200 | * Mark all PD level as invalid after an error. | |
1201 | */ | |
1202 | static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent) | |
1203 | { | |
1204 | unsigned pt_idx; | |
1205 | ||
1206 | /* | |
1207 | * Recurse into the subdirectories. This recursion is harmless because | |
1208 | * we only have a maximum of 5 layers. | |
1209 | */ | |
1210 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
1211 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
1212 | ||
1213 | if (!entry->bo) | |
1214 | continue; | |
1215 | ||
1216 | entry->addr = ~0ULL; | |
1217 | amdgpu_vm_invalidate_level(entry); | |
1218 | } | |
1219 | } | |
1220 | ||
194d2161 CK |
1221 | /* |
1222 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1223 | * | |
1224 | * @adev: amdgpu_device pointer | |
1225 | * @vm: requested vm | |
1226 | * | |
1227 | * Makes sure all directories are up to date. | |
1228 | * Returns 0 for success, error for failure. | |
1229 | */ | |
1230 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1231 | struct amdgpu_vm *vm) | |
1232 | { | |
92456b93 CK |
1233 | int r; |
1234 | ||
1235 | r = amdgpu_vm_update_level(adev, vm, &vm->root, 0); | |
1236 | if (r) | |
1237 | amdgpu_vm_invalidate_level(&vm->root); | |
1238 | ||
1239 | return r; | |
194d2161 CK |
1240 | } |
1241 | ||
4e2cb640 CK |
1242 | /** |
1243 | * amdgpu_vm_find_pt - find the page table for an address | |
1244 | * | |
1245 | * @p: see amdgpu_pte_update_params definition | |
1246 | * @addr: virtual address in question | |
1247 | * | |
1248 | * Find the page table BO for a virtual address, return NULL when none found. | |
1249 | */ | |
1250 | static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p, | |
1251 | uint64_t addr) | |
1252 | { | |
1253 | struct amdgpu_vm_pt *entry = &p->vm->root; | |
1254 | unsigned idx, level = p->adev->vm_manager.num_level; | |
1255 | ||
1256 | while (entry->entries) { | |
36b32a68 | 1257 | idx = addr >> (p->adev->vm_manager.block_size * level--); |
4e2cb640 CK |
1258 | idx %= amdgpu_bo_size(entry->bo) / 8; |
1259 | entry = &entry->entries[idx]; | |
1260 | } | |
1261 | ||
1262 | if (level) | |
1263 | return NULL; | |
1264 | ||
1265 | return entry->bo; | |
1266 | } | |
1267 | ||
d38ceaf9 AD |
1268 | /** |
1269 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1270 | * | |
29efc4f5 | 1271 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1272 | * @vm: requested vm |
1273 | * @start: start of GPU address range | |
1274 | * @end: end of GPU address range | |
677131a1 | 1275 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1276 | * @flags: mapping flags |
1277 | * | |
8843dbbb | 1278 | * Update the page tables in the range @start - @end. |
cc28c4ed | 1279 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 | 1280 | */ |
cc28c4ed | 1281 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1282 | uint64_t start, uint64_t end, |
6b777607 | 1283 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1284 | { |
36b32a68 ZJ |
1285 | struct amdgpu_device *adev = params->adev; |
1286 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1287 | |
301654a4 | 1288 | uint64_t addr, pe_start; |
21718497 | 1289 | struct amdgpu_bo *pt; |
301654a4 | 1290 | unsigned nptes; |
370f092f HK |
1291 | int r; |
1292 | bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes); | |
21718497 | 1293 | |
d38ceaf9 AD |
1294 | |
1295 | /* walk over the address space and update the page tables */ | |
301654a4 | 1296 | for (addr = start; addr < end; addr += nptes) { |
4e2cb640 | 1297 | pt = amdgpu_vm_get_pt(params, addr); |
1866bac8 FK |
1298 | if (!pt) { |
1299 | pr_err("PT not found, aborting update_ptes\n"); | |
cc28c4ed | 1300 | return -EINVAL; |
1866bac8 | 1301 | } |
4e2cb640 | 1302 | |
d38ceaf9 AD |
1303 | if ((addr & ~mask) == (end & ~mask)) |
1304 | nptes = end - addr; | |
1305 | else | |
36b32a68 | 1306 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1307 | |
370f092f HK |
1308 | if (use_cpu_update) { |
1309 | r = amdgpu_bo_kmap(pt, (void *)&pe_start); | |
1310 | if (r) | |
1311 | return r; | |
dd0792c1 CK |
1312 | |
1313 | WARN_ONCE(pt->shadow, | |
1314 | "CPU VM update doesn't support shadow pages"); | |
1315 | } else { | |
1316 | if (pt->shadow) { | |
1317 | pe_start = amdgpu_bo_gpu_offset(pt->shadow); | |
1318 | pe_start += (addr & mask) * 8; | |
1319 | params->func(params, pe_start, dst, nptes, | |
1320 | AMDGPU_GPU_PAGE_SIZE, flags); | |
1321 | } | |
370f092f | 1322 | pe_start = amdgpu_bo_gpu_offset(pt); |
dd0792c1 | 1323 | } |
d38ceaf9 | 1324 | |
301654a4 | 1325 | pe_start += (addr & mask) * 8; |
301654a4 CK |
1326 | params->func(params, pe_start, dst, nptes, |
1327 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 | 1328 | |
d38ceaf9 | 1329 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; |
370f092f HK |
1330 | |
1331 | if (use_cpu_update) | |
1332 | amdgpu_bo_kunmap(pt); | |
d38ceaf9 AD |
1333 | } |
1334 | ||
cc28c4ed | 1335 | return 0; |
92696dd5 CK |
1336 | } |
1337 | ||
1338 | /* | |
1339 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1340 | * | |
1341 | * @params: see amdgpu_pte_update_params definition | |
1342 | * @vm: requested vm | |
1343 | * @start: first PTE to handle | |
1344 | * @end: last PTE to handle | |
1345 | * @dst: addr those PTEs should point to | |
1346 | * @flags: hw mapping flags | |
cc28c4ed | 1347 | * Returns 0 for success, -EINVAL for failure. |
92696dd5 | 1348 | */ |
cc28c4ed | 1349 | static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, |
92696dd5 | 1350 | uint64_t start, uint64_t end, |
6b777607 | 1351 | uint64_t dst, uint64_t flags) |
92696dd5 | 1352 | { |
cc28c4ed HK |
1353 | int r; |
1354 | ||
92696dd5 CK |
1355 | /** |
1356 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1357 | * field in the PTE. When this field is set to a non-zero value, page | |
1358 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1359 | * flags are considered valid for all PTEs within the fragment range | |
1360 | * and corresponding mappings are assumed to be physically contiguous. | |
1361 | * | |
1362 | * The L1 TLB can store a single PTE for the whole fragment, | |
1363 | * significantly increasing the space available for translation | |
1364 | * caching. This leads to large improvements in throughput when the | |
1365 | * TLB is under pressure. | |
1366 | * | |
1367 | * The L2 TLB distributes small and large fragments into two | |
1368 | * asymmetric partitions. The large fragment cache is significantly | |
1369 | * larger. Thus, we try to use large fragments wherever possible. | |
1370 | * Userspace can support this by aligning virtual base address and | |
1371 | * allocation size to the fragment size. | |
1372 | */ | |
1373 | ||
8036617e CK |
1374 | /* SI and newer are optimized for 64KB */ |
1375 | uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG); | |
1376 | uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG; | |
92696dd5 CK |
1377 | |
1378 | uint64_t frag_start = ALIGN(start, frag_align); | |
1379 | uint64_t frag_end = end & ~(frag_align - 1); | |
1380 | ||
1381 | /* system pages are non continuously */ | |
b7fc2cbd | 1382 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
cc28c4ed HK |
1383 | (frag_start >= frag_end)) |
1384 | return amdgpu_vm_update_ptes(params, start, end, dst, flags); | |
92696dd5 CK |
1385 | |
1386 | /* handle the 4K area at the beginning */ | |
1387 | if (start != frag_start) { | |
cc28c4ed HK |
1388 | r = amdgpu_vm_update_ptes(params, start, frag_start, |
1389 | dst, flags); | |
1390 | if (r) | |
1391 | return r; | |
92696dd5 CK |
1392 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; |
1393 | } | |
1394 | ||
1395 | /* handle the area in the middle */ | |
cc28c4ed HK |
1396 | r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, |
1397 | flags | frag_flags); | |
1398 | if (r) | |
1399 | return r; | |
92696dd5 CK |
1400 | |
1401 | /* handle the 4K area at the end */ | |
1402 | if (frag_end != end) { | |
1403 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
cc28c4ed | 1404 | r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); |
92696dd5 | 1405 | } |
cc28c4ed | 1406 | return r; |
d38ceaf9 AD |
1407 | } |
1408 | ||
d38ceaf9 AD |
1409 | /** |
1410 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1411 | * | |
1412 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1413 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
1414 | * @src: address where to copy page table entries from |
1415 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 1416 | * @vm: requested vm |
a14faa65 CK |
1417 | * @start: start of mapped range |
1418 | * @last: last mapped entry | |
1419 | * @flags: flags for the entries | |
d38ceaf9 | 1420 | * @addr: addr to set the area to |
d38ceaf9 AD |
1421 | * @fence: optional resulting fence |
1422 | * | |
a14faa65 | 1423 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 1424 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
1425 | */ |
1426 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1427 | struct dma_fence *exclusive, |
fa3ab3c7 CK |
1428 | uint64_t src, |
1429 | dma_addr_t *pages_addr, | |
d38ceaf9 | 1430 | struct amdgpu_vm *vm, |
a14faa65 | 1431 | uint64_t start, uint64_t last, |
6b777607 | 1432 | uint64_t flags, uint64_t addr, |
f54d1867 | 1433 | struct dma_fence **fence) |
d38ceaf9 | 1434 | { |
2d55e45a | 1435 | struct amdgpu_ring *ring; |
a1e08d3b | 1436 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1437 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1438 | struct amdgpu_job *job; |
29efc4f5 | 1439 | struct amdgpu_pte_update_params params; |
f54d1867 | 1440 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1441 | int r; |
1442 | ||
afef8b8f CK |
1443 | memset(¶ms, 0, sizeof(params)); |
1444 | params.adev = adev; | |
49ac8a24 | 1445 | params.vm = vm; |
afef8b8f CK |
1446 | params.src = src; |
1447 | ||
b4d42511 HK |
1448 | if (vm->use_cpu_for_update) { |
1449 | /* params.src is used as flag to indicate system Memory */ | |
1450 | if (pages_addr) | |
1451 | params.src = ~0; | |
1452 | ||
1453 | /* Wait for PT BOs to be free. PTs share the same resv. object | |
1454 | * as the root PD BO | |
1455 | */ | |
1456 | r = amdgpu_vm_bo_wait(adev, vm->root.bo); | |
1457 | if (unlikely(r)) | |
1458 | return r; | |
1459 | ||
1460 | params.func = amdgpu_vm_cpu_set_ptes; | |
1461 | params.pages_addr = pages_addr; | |
b4d42511 HK |
1462 | return amdgpu_vm_frag_ptes(¶ms, start, last + 1, |
1463 | addr, flags); | |
1464 | } | |
1465 | ||
2d55e45a | 1466 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 1467 | |
a1e08d3b CK |
1468 | /* sync to everything on unmapping */ |
1469 | if (!(flags & AMDGPU_PTE_VALID)) | |
1470 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1471 | ||
a14faa65 | 1472 | nptes = last - start + 1; |
d38ceaf9 AD |
1473 | |
1474 | /* | |
1475 | * reserve space for one command every (1 << BLOCK_SIZE) | |
1476 | * entries or 2k dwords (whatever is smaller) | |
1477 | */ | |
36b32a68 | 1478 | ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1; |
d38ceaf9 AD |
1479 | |
1480 | /* padding, etc. */ | |
1481 | ndw = 64; | |
1482 | ||
b0456f93 | 1483 | if (src) { |
d38ceaf9 AD |
1484 | /* only copy commands needed */ |
1485 | ndw += ncmds * 7; | |
1486 | ||
afef8b8f CK |
1487 | params.func = amdgpu_vm_do_copy_ptes; |
1488 | ||
b0456f93 CK |
1489 | } else if (pages_addr) { |
1490 | /* copy commands needed */ | |
1491 | ndw += ncmds * 7; | |
d38ceaf9 | 1492 | |
b0456f93 | 1493 | /* and also PTEs */ |
d38ceaf9 AD |
1494 | ndw += nptes * 2; |
1495 | ||
afef8b8f CK |
1496 | params.func = amdgpu_vm_do_copy_ptes; |
1497 | ||
d38ceaf9 AD |
1498 | } else { |
1499 | /* set page commands needed */ | |
1500 | ndw += ncmds * 10; | |
1501 | ||
1502 | /* two extra commands for begin/end of fragment */ | |
1503 | ndw += 2 * 10; | |
afef8b8f CK |
1504 | |
1505 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1506 | } |
1507 | ||
d71518b5 CK |
1508 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1509 | if (r) | |
d38ceaf9 | 1510 | return r; |
d71518b5 | 1511 | |
29efc4f5 | 1512 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1513 | |
b0456f93 CK |
1514 | if (!src && pages_addr) { |
1515 | uint64_t *pte; | |
1516 | unsigned i; | |
1517 | ||
1518 | /* Put the PTEs at the end of the IB. */ | |
1519 | i = ndw - nptes * 2; | |
1520 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1521 | params.src = job->ibs->gpu_addr + i * 4; | |
1522 | ||
1523 | for (i = 0; i < nptes; ++i) { | |
1524 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1525 | AMDGPU_GPU_PAGE_SIZE); | |
1526 | pte[i] |= flags; | |
1527 | } | |
d7a4ac66 | 1528 | addr = 0; |
b0456f93 CK |
1529 | } |
1530 | ||
3cabaa54 CK |
1531 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
1532 | if (r) | |
1533 | goto error_free; | |
1534 | ||
67003a15 | 1535 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv, |
a1e08d3b CK |
1536 | owner); |
1537 | if (r) | |
1538 | goto error_free; | |
d38ceaf9 | 1539 | |
67003a15 | 1540 | r = reservation_object_reserve_shared(vm->root.bo->tbo.resv); |
a1e08d3b CK |
1541 | if (r) |
1542 | goto error_free; | |
1543 | ||
cc28c4ed HK |
1544 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
1545 | if (r) | |
1546 | goto error_free; | |
d38ceaf9 | 1547 | |
29efc4f5 CK |
1548 | amdgpu_ring_pad_ib(ring, params.ib); |
1549 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1550 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1551 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1552 | if (r) |
1553 | goto error_free; | |
d38ceaf9 | 1554 | |
67003a15 | 1555 | amdgpu_bo_fence(vm->root.bo, f, true); |
284710fa CK |
1556 | dma_fence_put(*fence); |
1557 | *fence = f; | |
d38ceaf9 | 1558 | return 0; |
d5fc5e82 CZ |
1559 | |
1560 | error_free: | |
d71518b5 | 1561 | amdgpu_job_free(job); |
4af9f07c | 1562 | return r; |
d38ceaf9 AD |
1563 | } |
1564 | ||
a14faa65 CK |
1565 | /** |
1566 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1567 | * | |
1568 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1569 | * @exclusive: fence we need to sync to |
8358dcee CK |
1570 | * @gtt_flags: flags as they are used for GTT |
1571 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
1572 | * @vm: requested vm |
1573 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1574 | * @flags: HW flags for the mapping |
63e0ba40 | 1575 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1576 | * @fence: optional resulting fence |
1577 | * | |
1578 | * Split the mapping into smaller chunks so that each update fits | |
1579 | * into a SDMA IB. | |
1580 | * Returns 0 for success, -EINVAL for failure. | |
1581 | */ | |
1582 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1583 | struct dma_fence *exclusive, |
6b777607 | 1584 | uint64_t gtt_flags, |
8358dcee | 1585 | dma_addr_t *pages_addr, |
a14faa65 CK |
1586 | struct amdgpu_vm *vm, |
1587 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1588 | uint64_t flags, |
63e0ba40 | 1589 | struct drm_mm_node *nodes, |
f54d1867 | 1590 | struct dma_fence **fence) |
a14faa65 | 1591 | { |
a9f87f64 | 1592 | uint64_t pfn, src = 0, start = mapping->start; |
a14faa65 CK |
1593 | int r; |
1594 | ||
1595 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1596 | * but in case of something, we filter the flags in first place | |
1597 | */ | |
1598 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1599 | flags &= ~AMDGPU_PTE_READABLE; | |
1600 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1601 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1602 | ||
15b31c59 AX |
1603 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1604 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1605 | ||
b0fd18b0 AX |
1606 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1607 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1608 | ||
d0766e98 ZJ |
1609 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1610 | (adev->asic_type >= CHIP_VEGA10)) { | |
1611 | flags |= AMDGPU_PTE_PRT; | |
1612 | flags &= ~AMDGPU_PTE_VALID; | |
1613 | } | |
1614 | ||
a14faa65 CK |
1615 | trace_amdgpu_vm_bo_update(mapping); |
1616 | ||
63e0ba40 CK |
1617 | pfn = mapping->offset >> PAGE_SHIFT; |
1618 | if (nodes) { | |
1619 | while (pfn >= nodes->size) { | |
1620 | pfn -= nodes->size; | |
1621 | ++nodes; | |
1622 | } | |
fa3ab3c7 | 1623 | } |
a14faa65 | 1624 | |
63e0ba40 CK |
1625 | do { |
1626 | uint64_t max_entries; | |
1627 | uint64_t addr, last; | |
a14faa65 | 1628 | |
63e0ba40 CK |
1629 | if (nodes) { |
1630 | addr = nodes->start << PAGE_SHIFT; | |
1631 | max_entries = (nodes->size - pfn) * | |
1632 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1633 | } else { | |
1634 | addr = 0; | |
1635 | max_entries = S64_MAX; | |
1636 | } | |
a14faa65 | 1637 | |
63e0ba40 CK |
1638 | if (pages_addr) { |
1639 | if (flags == gtt_flags) | |
1640 | src = adev->gart.table_addr + | |
1641 | (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8; | |
1642 | else | |
1643 | max_entries = min(max_entries, 16ull * 1024ull); | |
1644 | addr = 0; | |
1645 | } else if (flags & AMDGPU_PTE_VALID) { | |
1646 | addr += adev->vm_manager.vram_base_offset; | |
1647 | } | |
1648 | addr += pfn << PAGE_SHIFT; | |
1649 | ||
a9f87f64 | 1650 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
3cabaa54 CK |
1651 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1652 | src, pages_addr, vm, | |
a14faa65 CK |
1653 | start, last, flags, addr, |
1654 | fence); | |
1655 | if (r) | |
1656 | return r; | |
1657 | ||
63e0ba40 CK |
1658 | pfn += last - start + 1; |
1659 | if (nodes && nodes->size == pfn) { | |
1660 | pfn = 0; | |
1661 | ++nodes; | |
1662 | } | |
a14faa65 | 1663 | start = last + 1; |
63e0ba40 | 1664 | |
a9f87f64 | 1665 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1666 | |
1667 | return 0; | |
1668 | } | |
1669 | ||
d38ceaf9 AD |
1670 | /** |
1671 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1672 | * | |
1673 | * @adev: amdgpu_device pointer | |
1674 | * @bo_va: requested BO and VM object | |
99e124f4 | 1675 | * @clear: if true clear the entries |
d38ceaf9 AD |
1676 | * |
1677 | * Fill in the page table entries for @bo_va. | |
1678 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1679 | */ |
1680 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1681 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1682 | bool clear) |
d38ceaf9 AD |
1683 | { |
1684 | struct amdgpu_vm *vm = bo_va->vm; | |
1685 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1686 | dma_addr_t *pages_addr = NULL; |
6b777607 | 1687 | uint64_t gtt_flags, flags; |
99e124f4 | 1688 | struct ttm_mem_reg *mem; |
63e0ba40 | 1689 | struct drm_mm_node *nodes; |
f54d1867 | 1690 | struct dma_fence *exclusive; |
d38ceaf9 AD |
1691 | int r; |
1692 | ||
a5f6b5b1 | 1693 | if (clear || !bo_va->bo) { |
99e124f4 | 1694 | mem = NULL; |
63e0ba40 | 1695 | nodes = NULL; |
99e124f4 CK |
1696 | exclusive = NULL; |
1697 | } else { | |
8358dcee CK |
1698 | struct ttm_dma_tt *ttm; |
1699 | ||
99e124f4 | 1700 | mem = &bo_va->bo->tbo.mem; |
63e0ba40 CK |
1701 | nodes = mem->mm_node; |
1702 | if (mem->mem_type == TTM_PL_TT) { | |
8358dcee CK |
1703 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1704 | ttm_dma_tt, ttm); | |
1705 | pages_addr = ttm->dma_address; | |
9ab21462 | 1706 | } |
3cabaa54 | 1707 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); |
d38ceaf9 AD |
1708 | } |
1709 | ||
a5f6b5b1 CK |
1710 | if (bo_va->bo) { |
1711 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); | |
1712 | gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && | |
1713 | adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? | |
1714 | flags : 0; | |
1715 | } else { | |
1716 | flags = 0x0; | |
1717 | gtt_flags = ~0x0; | |
1718 | } | |
d38ceaf9 | 1719 | |
7fc11959 CK |
1720 | spin_lock(&vm->status_lock); |
1721 | if (!list_empty(&bo_va->vm_status)) | |
1722 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1723 | spin_unlock(&vm->status_lock); | |
1724 | ||
1725 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1726 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1727 | gtt_flags, pages_addr, vm, | |
63e0ba40 | 1728 | mapping, flags, nodes, |
8358dcee | 1729 | &bo_va->last_pt_update); |
d38ceaf9 AD |
1730 | if (r) |
1731 | return r; | |
1732 | } | |
1733 | ||
d6c10f6b CK |
1734 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1735 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1736 | trace_amdgpu_vm_bo_mapping(mapping); | |
1737 | ||
1738 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1739 | trace_amdgpu_vm_bo_mapping(mapping); | |
1740 | } | |
1741 | ||
d38ceaf9 | 1742 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1743 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1744 | list_del_init(&bo_va->vm_status); |
99e124f4 | 1745 | if (clear) |
7fc11959 | 1746 | list_add(&bo_va->vm_status, &vm->cleared); |
d38ceaf9 AD |
1747 | spin_unlock(&vm->status_lock); |
1748 | ||
1749 | return 0; | |
1750 | } | |
1751 | ||
284710fa CK |
1752 | /** |
1753 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1754 | */ | |
1755 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1756 | { | |
1757 | unsigned long flags; | |
1758 | bool enable; | |
1759 | ||
1760 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1761 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
284710fa CK |
1762 | adev->gart.gart_funcs->set_prt(adev, enable); |
1763 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
1764 | } | |
1765 | ||
451bc8eb | 1766 | /** |
4388fc2a | 1767 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1768 | */ |
1769 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1770 | { | |
4388fc2a CK |
1771 | if (!adev->gart.gart_funcs->set_prt) |
1772 | return; | |
1773 | ||
451bc8eb CK |
1774 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1775 | amdgpu_vm_update_prt_state(adev); | |
1776 | } | |
1777 | ||
0b15f2fc CK |
1778 | /** |
1779 | * amdgpu_vm_prt_put - drop a PRT user | |
1780 | */ | |
1781 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1782 | { | |
451bc8eb | 1783 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1784 | amdgpu_vm_update_prt_state(adev); |
1785 | } | |
1786 | ||
284710fa | 1787 | /** |
451bc8eb | 1788 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1789 | */ |
1790 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1791 | { | |
1792 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1793 | ||
0b15f2fc | 1794 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1795 | kfree(cb); |
1796 | } | |
1797 | ||
451bc8eb CK |
1798 | /** |
1799 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1800 | */ | |
1801 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1802 | struct dma_fence *fence) | |
1803 | { | |
4388fc2a | 1804 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1805 | |
4388fc2a CK |
1806 | if (!adev->gart.gart_funcs->set_prt) |
1807 | return; | |
1808 | ||
1809 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1810 | if (!cb) { |
1811 | /* Last resort when we are OOM */ | |
1812 | if (fence) | |
1813 | dma_fence_wait(fence, false); | |
1814 | ||
486a68f5 | 1815 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1816 | } else { |
1817 | cb->adev = adev; | |
1818 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1819 | amdgpu_vm_prt_cb)) | |
1820 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1821 | } | |
1822 | } | |
1823 | ||
284710fa CK |
1824 | /** |
1825 | * amdgpu_vm_free_mapping - free a mapping | |
1826 | * | |
1827 | * @adev: amdgpu_device pointer | |
1828 | * @vm: requested vm | |
1829 | * @mapping: mapping to be freed | |
1830 | * @fence: fence of the unmap operation | |
1831 | * | |
1832 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1833 | */ | |
1834 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1835 | struct amdgpu_vm *vm, | |
1836 | struct amdgpu_bo_va_mapping *mapping, | |
1837 | struct dma_fence *fence) | |
1838 | { | |
451bc8eb CK |
1839 | if (mapping->flags & AMDGPU_PTE_PRT) |
1840 | amdgpu_vm_add_prt_cb(adev, fence); | |
1841 | kfree(mapping); | |
1842 | } | |
284710fa | 1843 | |
451bc8eb CK |
1844 | /** |
1845 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1846 | * | |
1847 | * @adev: amdgpu_device pointer | |
1848 | * @vm: requested vm | |
1849 | * | |
1850 | * Register a cleanup callback to disable PRT support after VM dies. | |
1851 | */ | |
1852 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1853 | { | |
67003a15 | 1854 | struct reservation_object *resv = vm->root.bo->tbo.resv; |
451bc8eb CK |
1855 | struct dma_fence *excl, **shared; |
1856 | unsigned i, shared_count; | |
1857 | int r; | |
0b15f2fc | 1858 | |
451bc8eb CK |
1859 | r = reservation_object_get_fences_rcu(resv, &excl, |
1860 | &shared_count, &shared); | |
1861 | if (r) { | |
1862 | /* Not enough memory to grab the fence list, as last resort | |
1863 | * block for all the fences to complete. | |
1864 | */ | |
1865 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1866 | MAX_SCHEDULE_TIMEOUT); | |
1867 | return; | |
284710fa | 1868 | } |
451bc8eb CK |
1869 | |
1870 | /* Add a callback for each fence in the reservation object */ | |
1871 | amdgpu_vm_prt_get(adev); | |
1872 | amdgpu_vm_add_prt_cb(adev, excl); | |
1873 | ||
1874 | for (i = 0; i < shared_count; ++i) { | |
1875 | amdgpu_vm_prt_get(adev); | |
1876 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1877 | } | |
1878 | ||
1879 | kfree(shared); | |
284710fa CK |
1880 | } |
1881 | ||
d38ceaf9 AD |
1882 | /** |
1883 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1884 | * | |
1885 | * @adev: amdgpu_device pointer | |
1886 | * @vm: requested vm | |
f3467818 NH |
1887 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1888 | * or if an error occurred) | |
d38ceaf9 AD |
1889 | * |
1890 | * Make sure all freed BOs are cleared in the PT. | |
1891 | * Returns 0 for success. | |
1892 | * | |
1893 | * PTs have to be reserved and mutex must be locked! | |
1894 | */ | |
1895 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1896 | struct amdgpu_vm *vm, |
1897 | struct dma_fence **fence) | |
d38ceaf9 AD |
1898 | { |
1899 | struct amdgpu_bo_va_mapping *mapping; | |
f3467818 | 1900 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1901 | int r; |
1902 | ||
1903 | while (!list_empty(&vm->freed)) { | |
1904 | mapping = list_first_entry(&vm->freed, | |
1905 | struct amdgpu_bo_va_mapping, list); | |
1906 | list_del(&mapping->list); | |
e17841b9 | 1907 | |
fc6aa33d CK |
1908 | r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm, |
1909 | mapping->start, mapping->last, | |
1910 | 0, 0, &f); | |
f3467818 | 1911 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1912 | if (r) { |
f3467818 | 1913 | dma_fence_put(f); |
d38ceaf9 | 1914 | return r; |
284710fa | 1915 | } |
f3467818 | 1916 | } |
d38ceaf9 | 1917 | |
f3467818 NH |
1918 | if (fence && f) { |
1919 | dma_fence_put(*fence); | |
1920 | *fence = f; | |
1921 | } else { | |
1922 | dma_fence_put(f); | |
d38ceaf9 | 1923 | } |
f3467818 | 1924 | |
d38ceaf9 AD |
1925 | return 0; |
1926 | ||
1927 | } | |
1928 | ||
1929 | /** | |
1930 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1931 | * | |
1932 | * @adev: amdgpu_device pointer | |
1933 | * @vm: requested vm | |
1934 | * | |
1935 | * Make sure all invalidated BOs are cleared in the PT. | |
1936 | * Returns 0 for success. | |
1937 | * | |
1938 | * PTs have to be reserved and mutex must be locked! | |
1939 | */ | |
1940 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1941 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1942 | { |
cfe2c978 | 1943 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1944 | int r = 0; |
d38ceaf9 AD |
1945 | |
1946 | spin_lock(&vm->status_lock); | |
1947 | while (!list_empty(&vm->invalidated)) { | |
1948 | bo_va = list_first_entry(&vm->invalidated, | |
1949 | struct amdgpu_bo_va, vm_status); | |
1950 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1951 | |
99e124f4 | 1952 | r = amdgpu_vm_bo_update(adev, bo_va, true); |
d38ceaf9 AD |
1953 | if (r) |
1954 | return r; | |
1955 | ||
1956 | spin_lock(&vm->status_lock); | |
1957 | } | |
1958 | spin_unlock(&vm->status_lock); | |
1959 | ||
cfe2c978 | 1960 | if (bo_va) |
bb1e38a4 | 1961 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1962 | |
1963 | return r; | |
d38ceaf9 AD |
1964 | } |
1965 | ||
1966 | /** | |
1967 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1968 | * | |
1969 | * @adev: amdgpu_device pointer | |
1970 | * @vm: requested vm | |
1971 | * @bo: amdgpu buffer object | |
1972 | * | |
8843dbbb | 1973 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1974 | * Add @bo to the list of bos associated with the vm |
1975 | * Returns newly added bo_va or NULL for failure | |
1976 | * | |
1977 | * Object has to be reserved! | |
1978 | */ | |
1979 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1980 | struct amdgpu_vm *vm, | |
1981 | struct amdgpu_bo *bo) | |
1982 | { | |
1983 | struct amdgpu_bo_va *bo_va; | |
1984 | ||
1985 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1986 | if (bo_va == NULL) { | |
1987 | return NULL; | |
1988 | } | |
1989 | bo_va->vm = vm; | |
1990 | bo_va->bo = bo; | |
d38ceaf9 AD |
1991 | bo_va->ref_count = 1; |
1992 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1993 | INIT_LIST_HEAD(&bo_va->valids); |
1994 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1995 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1996 | |
a5f6b5b1 CK |
1997 | if (bo) |
1998 | list_add_tail(&bo_va->bo_list, &bo->va); | |
d38ceaf9 AD |
1999 | |
2000 | return bo_va; | |
2001 | } | |
2002 | ||
2003 | /** | |
2004 | * amdgpu_vm_bo_map - map bo inside a vm | |
2005 | * | |
2006 | * @adev: amdgpu_device pointer | |
2007 | * @bo_va: bo_va to store the address | |
2008 | * @saddr: where to map the BO | |
2009 | * @offset: requested offset in the BO | |
2010 | * @flags: attributes of pages (read/write/valid/etc.) | |
2011 | * | |
2012 | * Add a mapping of the BO at the specefied addr into the VM. | |
2013 | * Returns 0 for success, error for failure. | |
2014 | * | |
49b02b18 | 2015 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2016 | */ |
2017 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2018 | struct amdgpu_bo_va *bo_va, | |
2019 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2020 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2021 | { |
a9f87f64 | 2022 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
d38ceaf9 | 2023 | struct amdgpu_vm *vm = bo_va->vm; |
d38ceaf9 | 2024 | uint64_t eaddr; |
d38ceaf9 | 2025 | |
0be52de9 CK |
2026 | /* validate the parameters */ |
2027 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2028 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2029 | return -EINVAL; |
0be52de9 | 2030 | |
d38ceaf9 | 2031 | /* make sure object fit at this offset */ |
005ae95e | 2032 | eaddr = saddr + size - 1; |
a5f6b5b1 CK |
2033 | if (saddr >= eaddr || |
2034 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
d38ceaf9 | 2035 | return -EINVAL; |
d38ceaf9 | 2036 | |
d38ceaf9 AD |
2037 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2038 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2039 | ||
a9f87f64 CK |
2040 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2041 | if (tmp) { | |
d38ceaf9 AD |
2042 | /* bo and tmp overlap, invalid addr */ |
2043 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
a9f87f64 CK |
2044 | "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr, |
2045 | tmp->start, tmp->last + 1); | |
663e4577 | 2046 | return -EINVAL; |
d38ceaf9 AD |
2047 | } |
2048 | ||
2049 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2050 | if (!mapping) |
2051 | return -ENOMEM; | |
d38ceaf9 AD |
2052 | |
2053 | INIT_LIST_HEAD(&mapping->list); | |
a9f87f64 CK |
2054 | mapping->start = saddr; |
2055 | mapping->last = eaddr; | |
d38ceaf9 AD |
2056 | mapping->offset = offset; |
2057 | mapping->flags = flags; | |
2058 | ||
7fc11959 | 2059 | list_add(&mapping->list, &bo_va->invalids); |
a9f87f64 | 2060 | amdgpu_vm_it_insert(mapping, &vm->va); |
80f95c57 CK |
2061 | |
2062 | if (flags & AMDGPU_PTE_PRT) | |
2063 | amdgpu_vm_prt_get(adev); | |
2064 | ||
2065 | return 0; | |
2066 | } | |
2067 | ||
2068 | /** | |
2069 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2070 | * | |
2071 | * @adev: amdgpu_device pointer | |
2072 | * @bo_va: bo_va to store the address | |
2073 | * @saddr: where to map the BO | |
2074 | * @offset: requested offset in the BO | |
2075 | * @flags: attributes of pages (read/write/valid/etc.) | |
2076 | * | |
2077 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2078 | * mappings as we do so. | |
2079 | * Returns 0 for success, error for failure. | |
2080 | * | |
2081 | * Object has to be reserved and unreserved outside! | |
2082 | */ | |
2083 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2084 | struct amdgpu_bo_va *bo_va, | |
2085 | uint64_t saddr, uint64_t offset, | |
2086 | uint64_t size, uint64_t flags) | |
2087 | { | |
2088 | struct amdgpu_bo_va_mapping *mapping; | |
2089 | struct amdgpu_vm *vm = bo_va->vm; | |
2090 | uint64_t eaddr; | |
2091 | int r; | |
2092 | ||
2093 | /* validate the parameters */ | |
2094 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2095 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2096 | return -EINVAL; | |
2097 | ||
2098 | /* make sure object fit at this offset */ | |
2099 | eaddr = saddr + size - 1; | |
2100 | if (saddr >= eaddr || | |
2101 | (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) | |
2102 | return -EINVAL; | |
2103 | ||
2104 | /* Allocate all the needed memory */ | |
2105 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2106 | if (!mapping) | |
2107 | return -ENOMEM; | |
2108 | ||
2109 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size); | |
2110 | if (r) { | |
2111 | kfree(mapping); | |
2112 | return r; | |
2113 | } | |
2114 | ||
2115 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2116 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2117 | ||
a9f87f64 CK |
2118 | mapping->start = saddr; |
2119 | mapping->last = eaddr; | |
80f95c57 CK |
2120 | mapping->offset = offset; |
2121 | mapping->flags = flags; | |
2122 | ||
2123 | list_add(&mapping->list, &bo_va->invalids); | |
a9f87f64 | 2124 | amdgpu_vm_it_insert(mapping, &vm->va); |
d38ceaf9 | 2125 | |
4388fc2a CK |
2126 | if (flags & AMDGPU_PTE_PRT) |
2127 | amdgpu_vm_prt_get(adev); | |
2128 | ||
d38ceaf9 | 2129 | return 0; |
d38ceaf9 AD |
2130 | } |
2131 | ||
2132 | /** | |
2133 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2134 | * | |
2135 | * @adev: amdgpu_device pointer | |
2136 | * @bo_va: bo_va to remove the address from | |
2137 | * @saddr: where to the BO is mapped | |
2138 | * | |
2139 | * Remove a mapping of the BO at the specefied addr from the VM. | |
2140 | * Returns 0 for success, error for failure. | |
2141 | * | |
49b02b18 | 2142 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2143 | */ |
2144 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2145 | struct amdgpu_bo_va *bo_va, | |
2146 | uint64_t saddr) | |
2147 | { | |
2148 | struct amdgpu_bo_va_mapping *mapping; | |
2149 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 2150 | bool valid = true; |
d38ceaf9 | 2151 | |
6c7fc503 | 2152 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2153 | |
7fc11959 | 2154 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2155 | if (mapping->start == saddr) |
d38ceaf9 AD |
2156 | break; |
2157 | } | |
2158 | ||
7fc11959 CK |
2159 | if (&mapping->list == &bo_va->valids) { |
2160 | valid = false; | |
2161 | ||
2162 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2163 | if (mapping->start == saddr) |
7fc11959 CK |
2164 | break; |
2165 | } | |
2166 | ||
32b41ac2 | 2167 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2168 | return -ENOENT; |
d38ceaf9 | 2169 | } |
32b41ac2 | 2170 | |
d38ceaf9 | 2171 | list_del(&mapping->list); |
a9f87f64 | 2172 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2173 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2174 | |
e17841b9 | 2175 | if (valid) |
d38ceaf9 | 2176 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2177 | else |
284710fa CK |
2178 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2179 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2180 | |
2181 | return 0; | |
2182 | } | |
2183 | ||
dc54d3d1 CK |
2184 | /** |
2185 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2186 | * | |
2187 | * @adev: amdgpu_device pointer | |
2188 | * @vm: VM structure to use | |
2189 | * @saddr: start of the range | |
2190 | * @size: size of the range | |
2191 | * | |
2192 | * Remove all mappings in a range, split them as appropriate. | |
2193 | * Returns 0 for success, error for failure. | |
2194 | */ | |
2195 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2196 | struct amdgpu_vm *vm, | |
2197 | uint64_t saddr, uint64_t size) | |
2198 | { | |
2199 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2200 | LIST_HEAD(removed); |
2201 | uint64_t eaddr; | |
2202 | ||
2203 | eaddr = saddr + size - 1; | |
2204 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2205 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2206 | ||
2207 | /* Allocate all the needed memory */ | |
2208 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2209 | if (!before) | |
2210 | return -ENOMEM; | |
27f6d610 | 2211 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2212 | |
2213 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2214 | if (!after) { | |
2215 | kfree(before); | |
2216 | return -ENOMEM; | |
2217 | } | |
27f6d610 | 2218 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2219 | |
2220 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2221 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2222 | while (tmp) { | |
dc54d3d1 | 2223 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2224 | if (tmp->start < saddr) { |
2225 | before->start = tmp->start; | |
2226 | before->last = saddr - 1; | |
dc54d3d1 CK |
2227 | before->offset = tmp->offset; |
2228 | before->flags = tmp->flags; | |
2229 | list_add(&before->list, &tmp->list); | |
2230 | } | |
2231 | ||
2232 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2233 | if (tmp->last > eaddr) { |
2234 | after->start = eaddr + 1; | |
2235 | after->last = tmp->last; | |
dc54d3d1 | 2236 | after->offset = tmp->offset; |
a9f87f64 | 2237 | after->offset += after->start - tmp->start; |
dc54d3d1 CK |
2238 | after->flags = tmp->flags; |
2239 | list_add(&after->list, &tmp->list); | |
2240 | } | |
2241 | ||
2242 | list_del(&tmp->list); | |
2243 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2244 | |
2245 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2246 | } |
2247 | ||
2248 | /* And free them up */ | |
2249 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2250 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2251 | list_del(&tmp->list); |
2252 | ||
a9f87f64 CK |
2253 | if (tmp->start < saddr) |
2254 | tmp->start = saddr; | |
2255 | if (tmp->last > eaddr) | |
2256 | tmp->last = eaddr; | |
dc54d3d1 CK |
2257 | |
2258 | list_add(&tmp->list, &vm->freed); | |
2259 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2260 | } | |
2261 | ||
27f6d610 JZ |
2262 | /* Insert partial mapping before the range */ |
2263 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2264 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2265 | if (before->flags & AMDGPU_PTE_PRT) |
2266 | amdgpu_vm_prt_get(adev); | |
2267 | } else { | |
2268 | kfree(before); | |
2269 | } | |
2270 | ||
2271 | /* Insert partial mapping after the range */ | |
27f6d610 | 2272 | if (!list_empty(&after->list)) { |
a9f87f64 | 2273 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2274 | if (after->flags & AMDGPU_PTE_PRT) |
2275 | amdgpu_vm_prt_get(adev); | |
2276 | } else { | |
2277 | kfree(after); | |
2278 | } | |
2279 | ||
2280 | return 0; | |
2281 | } | |
2282 | ||
d38ceaf9 AD |
2283 | /** |
2284 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2285 | * | |
2286 | * @adev: amdgpu_device pointer | |
2287 | * @bo_va: requested bo_va | |
2288 | * | |
8843dbbb | 2289 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2290 | * |
2291 | * Object have to be reserved! | |
2292 | */ | |
2293 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2294 | struct amdgpu_bo_va *bo_va) | |
2295 | { | |
2296 | struct amdgpu_bo_va_mapping *mapping, *next; | |
2297 | struct amdgpu_vm *vm = bo_va->vm; | |
2298 | ||
2299 | list_del(&bo_va->bo_list); | |
2300 | ||
d38ceaf9 AD |
2301 | spin_lock(&vm->status_lock); |
2302 | list_del(&bo_va->vm_status); | |
2303 | spin_unlock(&vm->status_lock); | |
2304 | ||
7fc11959 | 2305 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2306 | list_del(&mapping->list); |
a9f87f64 | 2307 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2308 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2309 | list_add(&mapping->list, &vm->freed); |
2310 | } | |
2311 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2312 | list_del(&mapping->list); | |
a9f87f64 | 2313 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2314 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2315 | bo_va->last_pt_update); | |
d38ceaf9 | 2316 | } |
32b41ac2 | 2317 | |
f54d1867 | 2318 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2319 | kfree(bo_va); |
d38ceaf9 AD |
2320 | } |
2321 | ||
2322 | /** | |
2323 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2324 | * | |
2325 | * @adev: amdgpu_device pointer | |
2326 | * @vm: requested vm | |
2327 | * @bo: amdgpu buffer object | |
2328 | * | |
8843dbbb | 2329 | * Mark @bo as invalid. |
d38ceaf9 AD |
2330 | */ |
2331 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
2332 | struct amdgpu_bo *bo) | |
2333 | { | |
2334 | struct amdgpu_bo_va *bo_va; | |
2335 | ||
2336 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
2337 | spin_lock(&bo_va->vm->status_lock); |
2338 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 2339 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 2340 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
2341 | } |
2342 | } | |
2343 | ||
bab4fee7 JZ |
2344 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2345 | { | |
2346 | /* Total bits covered by PD + PTs */ | |
2347 | unsigned bits = ilog2(vm_size) + 18; | |
2348 | ||
2349 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2350 | Above that split equal between PD and PTs */ | |
2351 | if (vm_size <= 8) | |
2352 | return (bits - 9); | |
2353 | else | |
2354 | return ((bits + 3) / 2); | |
2355 | } | |
2356 | ||
2357 | /** | |
2358 | * amdgpu_vm_adjust_size - adjust vm size and block size | |
2359 | * | |
2360 | * @adev: amdgpu_device pointer | |
2361 | * @vm_size: the default vm size if it's set auto | |
2362 | */ | |
2363 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) | |
2364 | { | |
2365 | /* adjust vm size firstly */ | |
2366 | if (amdgpu_vm_size == -1) | |
2367 | adev->vm_manager.vm_size = vm_size; | |
2368 | else | |
2369 | adev->vm_manager.vm_size = amdgpu_vm_size; | |
2370 | ||
2371 | /* block size depends on vm size */ | |
2372 | if (amdgpu_vm_block_size == -1) | |
2373 | adev->vm_manager.block_size = | |
2374 | amdgpu_vm_get_block_size(adev->vm_manager.vm_size); | |
2375 | else | |
2376 | adev->vm_manager.block_size = amdgpu_vm_block_size; | |
2377 | ||
2378 | DRM_INFO("vm size is %llu GB, block size is %u-bit\n", | |
2379 | adev->vm_manager.vm_size, adev->vm_manager.block_size); | |
2380 | } | |
2381 | ||
d38ceaf9 AD |
2382 | /** |
2383 | * amdgpu_vm_init - initialize a vm instance | |
2384 | * | |
2385 | * @adev: amdgpu_device pointer | |
2386 | * @vm: requested vm | |
9a4b7d4c | 2387 | * @vm_context: Indicates if it GFX or Compute context |
d38ceaf9 | 2388 | * |
8843dbbb | 2389 | * Init @vm fields. |
d38ceaf9 | 2390 | */ |
9a4b7d4c HK |
2391 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
2392 | int vm_context) | |
d38ceaf9 AD |
2393 | { |
2394 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
36b32a68 | 2395 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2396 | unsigned ring_instance; |
2397 | struct amdgpu_ring *ring; | |
2bd9ccfa | 2398 | struct amd_sched_rq *rq; |
36bbf3bf | 2399 | int r, i; |
3c824172 | 2400 | u64 flags; |
d38ceaf9 | 2401 | |
d38ceaf9 | 2402 | vm->va = RB_ROOT; |
031e2983 | 2403 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
36bbf3bf CZ |
2404 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2405 | vm->reserved_vmid[i] = NULL; | |
d38ceaf9 AD |
2406 | spin_lock_init(&vm->status_lock); |
2407 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 2408 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 2409 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2410 | |
2bd9ccfa | 2411 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2412 | |
2413 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2414 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2415 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
2416 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
2417 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
2418 | rq, amdgpu_sched_jobs); | |
2419 | if (r) | |
f566ceb1 | 2420 | return r; |
2bd9ccfa | 2421 | |
9a4b7d4c HK |
2422 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) |
2423 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
2424 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
2425 | else | |
2426 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
2427 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
2428 | DRM_DEBUG_DRIVER("VM update mode is %s\n", | |
2429 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
2430 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), | |
2431 | "CPU update of VM recommended only for large BAR system\n"); | |
a24960f3 | 2432 | vm->last_dir_update = NULL; |
05906dec | 2433 | |
3c824172 HK |
2434 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
2435 | AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
2436 | if (vm->use_cpu_for_update) | |
2437 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
2438 | else | |
2439 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
2440 | AMDGPU_GEM_CREATE_SHADOW); | |
2441 | ||
f566ceb1 | 2442 | r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, |
857d913d | 2443 | AMDGPU_GEM_DOMAIN_VRAM, |
3c824172 | 2444 | flags, |
67003a15 | 2445 | NULL, NULL, &vm->root.bo); |
d38ceaf9 | 2446 | if (r) |
2bd9ccfa CK |
2447 | goto error_free_sched_entity; |
2448 | ||
67003a15 | 2449 | r = amdgpu_bo_reserve(vm->root.bo, false); |
2bd9ccfa | 2450 | if (r) |
67003a15 | 2451 | goto error_free_root; |
2bd9ccfa | 2452 | |
5a712a87 | 2453 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
67003a15 | 2454 | amdgpu_bo_unreserve(vm->root.bo); |
d38ceaf9 AD |
2455 | |
2456 | return 0; | |
2bd9ccfa | 2457 | |
67003a15 CK |
2458 | error_free_root: |
2459 | amdgpu_bo_unref(&vm->root.bo->shadow); | |
2460 | amdgpu_bo_unref(&vm->root.bo); | |
2461 | vm->root.bo = NULL; | |
2bd9ccfa CK |
2462 | |
2463 | error_free_sched_entity: | |
2464 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
2465 | ||
2466 | return r; | |
d38ceaf9 AD |
2467 | } |
2468 | ||
f566ceb1 CK |
2469 | /** |
2470 | * amdgpu_vm_free_levels - free PD/PT levels | |
2471 | * | |
2472 | * @level: PD/PT starting level to free | |
2473 | * | |
2474 | * Free the page directory or page table level and all sub levels. | |
2475 | */ | |
2476 | static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) | |
2477 | { | |
2478 | unsigned i; | |
2479 | ||
2480 | if (level->bo) { | |
2481 | amdgpu_bo_unref(&level->bo->shadow); | |
2482 | amdgpu_bo_unref(&level->bo); | |
2483 | } | |
2484 | ||
2485 | if (level->entries) | |
2486 | for (i = 0; i <= level->last_entry_used; i++) | |
2487 | amdgpu_vm_free_levels(&level->entries[i]); | |
2488 | ||
2098105e | 2489 | kvfree(level->entries); |
f566ceb1 CK |
2490 | } |
2491 | ||
d38ceaf9 AD |
2492 | /** |
2493 | * amdgpu_vm_fini - tear down a vm instance | |
2494 | * | |
2495 | * @adev: amdgpu_device pointer | |
2496 | * @vm: requested vm | |
2497 | * | |
8843dbbb | 2498 | * Tear down @vm. |
d38ceaf9 AD |
2499 | * Unbind the VM and remove all bos from the vm bo list |
2500 | */ | |
2501 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2502 | { | |
2503 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
4388fc2a | 2504 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
36bbf3bf | 2505 | int i; |
d38ceaf9 | 2506 | |
2d55e45a | 2507 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 2508 | |
d38ceaf9 AD |
2509 | if (!RB_EMPTY_ROOT(&vm->va)) { |
2510 | dev_err(adev->dev, "still active bo inside vm\n"); | |
2511 | } | |
a9f87f64 | 2512 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) { |
d38ceaf9 | 2513 | list_del(&mapping->list); |
a9f87f64 | 2514 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2515 | kfree(mapping); |
2516 | } | |
2517 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2518 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2519 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2520 | prt_fini_needed = false; |
451bc8eb | 2521 | } |
284710fa | 2522 | |
d38ceaf9 | 2523 | list_del(&mapping->list); |
451bc8eb | 2524 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2525 | } |
2526 | ||
f566ceb1 | 2527 | amdgpu_vm_free_levels(&vm->root); |
a24960f3 | 2528 | dma_fence_put(vm->last_dir_update); |
1e9ef26f CZ |
2529 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2530 | amdgpu_vm_free_reserved_vmid(adev, vm, i); | |
d38ceaf9 | 2531 | } |
ea89f8c9 | 2532 | |
a9a78b32 CK |
2533 | /** |
2534 | * amdgpu_vm_manager_init - init the VM manager | |
2535 | * | |
2536 | * @adev: amdgpu_device pointer | |
2537 | * | |
2538 | * Initialize the VM manager structures | |
2539 | */ | |
2540 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2541 | { | |
7645670d CK |
2542 | unsigned i, j; |
2543 | ||
2544 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
2545 | struct amdgpu_vm_id_manager *id_mgr = | |
2546 | &adev->vm_manager.id_mgr[i]; | |
a9a78b32 | 2547 | |
7645670d CK |
2548 | mutex_init(&id_mgr->lock); |
2549 | INIT_LIST_HEAD(&id_mgr->ids_lru); | |
c3505770 | 2550 | atomic_set(&id_mgr->reserved_vmid_num, 0); |
a9a78b32 | 2551 | |
7645670d CK |
2552 | /* skip over VMID 0, since it is the system VM */ |
2553 | for (j = 1; j < id_mgr->num_ids; ++j) { | |
2554 | amdgpu_vm_reset_id(adev, i, j); | |
2555 | amdgpu_sync_create(&id_mgr->ids[i].active); | |
2556 | list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); | |
2557 | } | |
971fe9a9 | 2558 | } |
2d55e45a | 2559 | |
f54d1867 CW |
2560 | adev->vm_manager.fence_context = |
2561 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2562 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2563 | adev->vm_manager.seqno[i] = 0; | |
2564 | ||
2d55e45a | 2565 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 2566 | atomic64_set(&adev->vm_manager.client_counter, 0); |
284710fa | 2567 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2568 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
2569 | |
2570 | /* If not overridden by the user, by default, only in large BAR systems | |
2571 | * Compute VM tables will be updated by CPU | |
2572 | */ | |
2573 | #ifdef CONFIG_X86_64 | |
2574 | if (amdgpu_vm_update_mode == -1) { | |
2575 | if (amdgpu_vm_is_large_bar(adev)) | |
2576 | adev->vm_manager.vm_update_mode = | |
2577 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
2578 | else | |
2579 | adev->vm_manager.vm_update_mode = 0; | |
2580 | } else | |
2581 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
2582 | #else | |
2583 | adev->vm_manager.vm_update_mode = 0; | |
2584 | #endif | |
2585 | ||
a9a78b32 CK |
2586 | } |
2587 | ||
ea89f8c9 CK |
2588 | /** |
2589 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2590 | * | |
2591 | * @adev: amdgpu_device pointer | |
2592 | * | |
2593 | * Cleanup the VM manager and free resources. | |
2594 | */ | |
2595 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2596 | { | |
7645670d | 2597 | unsigned i, j; |
ea89f8c9 | 2598 | |
7645670d CK |
2599 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
2600 | struct amdgpu_vm_id_manager *id_mgr = | |
2601 | &adev->vm_manager.id_mgr[i]; | |
bcb1ba35 | 2602 | |
7645670d CK |
2603 | mutex_destroy(&id_mgr->lock); |
2604 | for (j = 0; j < AMDGPU_NUM_VM; ++j) { | |
2605 | struct amdgpu_vm_id *id = &id_mgr->ids[j]; | |
2606 | ||
2607 | amdgpu_sync_free(&id->active); | |
2608 | dma_fence_put(id->flushed_updates); | |
2609 | dma_fence_put(id->last_flush); | |
2610 | } | |
bcb1ba35 | 2611 | } |
ea89f8c9 | 2612 | } |
cfbcacf4 CZ |
2613 | |
2614 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
2615 | { | |
2616 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
2617 | struct amdgpu_device *adev = dev->dev_private; |
2618 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
2619 | int r; | |
cfbcacf4 CZ |
2620 | |
2621 | switch (args->in.op) { | |
2622 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f CZ |
2623 | /* current, we only have requirement to reserve vmid from gfxhub */ |
2624 | r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm, | |
2625 | AMDGPU_GFXHUB); | |
2626 | if (r) | |
2627 | return r; | |
2628 | break; | |
cfbcacf4 | 2629 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
1e9ef26f | 2630 | amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
2631 | break; |
2632 | default: | |
2633 | return -EINVAL; | |
2634 | } | |
2635 | ||
2636 | return 0; | |
2637 | } |