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a2e73f56 AD |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
47b757fb | 24 | |
a2e73f56 | 25 | #include <linux/firmware.h> |
47b757fb SR |
26 | #include <linux/module.h> |
27 | ||
a2e73f56 AD |
28 | #include "amdgpu.h" |
29 | #include "amdgpu_ucode.h" | |
30 | #include "amdgpu_trace.h" | |
31 | #include "cikd.h" | |
32 | #include "cik.h" | |
33 | ||
34 | #include "bif/bif_4_1_d.h" | |
35 | #include "bif/bif_4_1_sh_mask.h" | |
36 | ||
37 | #include "gca/gfx_7_2_d.h" | |
74a5d165 JX |
38 | #include "gca/gfx_7_2_enum.h" |
39 | #include "gca/gfx_7_2_sh_mask.h" | |
a2e73f56 AD |
40 | |
41 | #include "gmc/gmc_7_1_d.h" | |
42 | #include "gmc/gmc_7_1_sh_mask.h" | |
43 | ||
44 | #include "oss/oss_2_0_d.h" | |
45 | #include "oss/oss_2_0_sh_mask.h" | |
46 | ||
47 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = | |
48 | { | |
49 | SDMA0_REGISTER_OFFSET, | |
50 | SDMA1_REGISTER_OFFSET | |
51 | }; | |
52 | ||
53 | static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); | |
54 | static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); | |
55 | static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); | |
56 | static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); | |
10ea9434 | 57 | static int cik_sdma_soft_reset(void *handle); |
a2e73f56 | 58 | |
ce206464 AD |
59 | MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin"); |
60 | MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin"); | |
61 | MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin"); | |
62 | MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin"); | |
63 | MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin"); | |
64 | MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin"); | |
65 | MODULE_FIRMWARE("amdgpu/kabini_sdma.bin"); | |
66 | MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin"); | |
67 | MODULE_FIRMWARE("amdgpu/mullins_sdma.bin"); | |
68 | MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin"); | |
a2e73f56 AD |
69 | |
70 | u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); | |
71 | ||
d1ff53b7 ML |
72 | |
73 | static void cik_sdma_free_microcode(struct amdgpu_device *adev) | |
74 | { | |
75 | int i; | |
76 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
77 | release_firmware(adev->sdma.instance[i].fw); | |
78 | adev->sdma.instance[i].fw = NULL; | |
79 | } | |
80 | } | |
81 | ||
a2e73f56 AD |
82 | /* |
83 | * sDMA - System DMA | |
84 | * Starting with CIK, the GPU has new asynchronous | |
85 | * DMA engines. These engines are used for compute | |
86 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | |
87 | * and each one supports 1 ring buffer used for gfx | |
88 | * and 2 queues used for compute. | |
89 | * | |
90 | * The programming model is very similar to the CP | |
91 | * (ring buffer, IBs, etc.), but sDMA has it's own | |
92 | * packet format that is different from the PM4 format | |
93 | * used by the CP. sDMA supports copying data, writing | |
94 | * embedded data, solid fills, and a number of other | |
95 | * things. It also has support for tiling/detiling of | |
96 | * buffers. | |
97 | */ | |
98 | ||
99 | /** | |
100 | * cik_sdma_init_microcode - load ucode images from disk | |
101 | * | |
102 | * @adev: amdgpu_device pointer | |
103 | * | |
104 | * Use the firmware interface to load the ucode images into | |
105 | * the driver (not loaded into hw). | |
106 | * Returns 0 on success, error on failure. | |
107 | */ | |
108 | static int cik_sdma_init_microcode(struct amdgpu_device *adev) | |
109 | { | |
110 | const char *chip_name; | |
111 | char fw_name[30]; | |
c113ea1c | 112 | int err = 0, i; |
a2e73f56 AD |
113 | |
114 | DRM_DEBUG("\n"); | |
115 | ||
116 | switch (adev->asic_type) { | |
117 | case CHIP_BONAIRE: | |
118 | chip_name = "bonaire"; | |
119 | break; | |
120 | case CHIP_HAWAII: | |
121 | chip_name = "hawaii"; | |
122 | break; | |
123 | case CHIP_KAVERI: | |
124 | chip_name = "kaveri"; | |
125 | break; | |
126 | case CHIP_KABINI: | |
127 | chip_name = "kabini"; | |
128 | break; | |
129 | case CHIP_MULLINS: | |
130 | chip_name = "mullins"; | |
131 | break; | |
132 | default: BUG(); | |
133 | } | |
134 | ||
c113ea1c | 135 | for (i = 0; i < adev->sdma.num_instances; i++) { |
a2e73f56 | 136 | if (i == 0) |
ce206464 | 137 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); |
a2e73f56 | 138 | else |
ce206464 | 139 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); |
c113ea1c | 140 | err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); |
a2e73f56 AD |
141 | if (err) |
142 | goto out; | |
c113ea1c | 143 | err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); |
a2e73f56 AD |
144 | } |
145 | out: | |
146 | if (err) { | |
7ca85295 | 147 | pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name); |
c113ea1c AD |
148 | for (i = 0; i < adev->sdma.num_instances; i++) { |
149 | release_firmware(adev->sdma.instance[i].fw); | |
150 | adev->sdma.instance[i].fw = NULL; | |
a2e73f56 AD |
151 | } |
152 | } | |
153 | return err; | |
154 | } | |
155 | ||
156 | /** | |
157 | * cik_sdma_ring_get_rptr - get the current read pointer | |
158 | * | |
159 | * @ring: amdgpu ring pointer | |
160 | * | |
161 | * Get the current rptr from the hardware (CIK+). | |
162 | */ | |
536fbf94 | 163 | static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) |
a2e73f56 AD |
164 | { |
165 | u32 rptr; | |
166 | ||
167 | rptr = ring->adev->wb.wb[ring->rptr_offs]; | |
168 | ||
169 | return (rptr & 0x3fffc) >> 2; | |
170 | } | |
171 | ||
172 | /** | |
173 | * cik_sdma_ring_get_wptr - get the current write pointer | |
174 | * | |
175 | * @ring: amdgpu ring pointer | |
176 | * | |
177 | * Get the current wptr from the hardware (CIK+). | |
178 | */ | |
536fbf94 | 179 | static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) |
a2e73f56 AD |
180 | { |
181 | struct amdgpu_device *adev = ring->adev; | |
a2e73f56 | 182 | |
1cf0abb6 | 183 | return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; |
a2e73f56 AD |
184 | } |
185 | ||
186 | /** | |
187 | * cik_sdma_ring_set_wptr - commit the write pointer | |
188 | * | |
189 | * @ring: amdgpu ring pointer | |
190 | * | |
191 | * Write the wptr back to the hardware (CIK+). | |
192 | */ | |
193 | static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) | |
194 | { | |
195 | struct amdgpu_device *adev = ring->adev; | |
a2e73f56 | 196 | |
1cf0abb6 | 197 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], |
536fbf94 | 198 | (lower_32_bits(ring->wptr) << 2) & 0x3fffc); |
a2e73f56 AD |
199 | } |
200 | ||
ac01db3d JZ |
201 | static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
202 | { | |
ccf191f8 | 203 | struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); |
ac01db3d JZ |
204 | int i; |
205 | ||
206 | for (i = 0; i < count; i++) | |
207 | if (sdma && sdma->burst_nop && (i == 0)) | |
79887142 | 208 | amdgpu_ring_write(ring, ring->funcs->nop | |
ac01db3d JZ |
209 | SDMA_NOP_COUNT(count - 1)); |
210 | else | |
79887142 | 211 | amdgpu_ring_write(ring, ring->funcs->nop); |
ac01db3d JZ |
212 | } |
213 | ||
a2e73f56 AD |
214 | /** |
215 | * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine | |
216 | * | |
217 | * @ring: amdgpu ring pointer | |
218 | * @ib: IB object to schedule | |
219 | * | |
220 | * Schedule an IB in the DMA ring (CIK). | |
221 | */ | |
222 | static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, | |
34955e03 | 223 | struct amdgpu_job *job, |
d88bf583 | 224 | struct amdgpu_ib *ib, |
c4c905ec | 225 | uint32_t flags) |
a2e73f56 | 226 | { |
34955e03 | 227 | unsigned vmid = AMDGPU_JOB_GET_VMID(job); |
c4f46f22 | 228 | u32 extra_bits = vmid & 0xf; |
a2e73f56 | 229 | |
a2e73f56 | 230 | /* IB packet must end on a 8 DW boundary */ |
536fbf94 | 231 | cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8); |
ac01db3d | 232 | |
a2e73f56 AD |
233 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); |
234 | amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ | |
235 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); | |
236 | amdgpu_ring_write(ring, ib->length_dw); | |
237 | ||
238 | } | |
239 | ||
240 | /** | |
d2edb07b | 241 | * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
a2e73f56 AD |
242 | * |
243 | * @ring: amdgpu ring pointer | |
244 | * | |
245 | * Emit an hdp flush packet on the requested DMA ring. | |
246 | */ | |
d2edb07b | 247 | static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
a2e73f56 AD |
248 | { |
249 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | | |
250 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ | |
251 | u32 ref_and_mask; | |
252 | ||
1cf0abb6 | 253 | if (ring->me == 0) |
a2e73f56 AD |
254 | ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; |
255 | else | |
256 | ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; | |
257 | ||
258 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
259 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); | |
260 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); | |
261 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ | |
262 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ | |
263 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
264 | } | |
265 | ||
266 | /** | |
267 | * cik_sdma_ring_emit_fence - emit a fence on the DMA ring | |
268 | * | |
269 | * @ring: amdgpu ring pointer | |
270 | * @fence: amdgpu fence object | |
271 | * | |
272 | * Add a DMA fence packet to the ring to write | |
273 | * the fence seq number and DMA trap packet to generate | |
274 | * an interrupt if needed (CIK). | |
275 | */ | |
276 | static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
890ee23f | 277 | unsigned flags) |
a2e73f56 | 278 | { |
890ee23f | 279 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
a2e73f56 AD |
280 | /* write the fence */ |
281 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); | |
282 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
283 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
284 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
285 | ||
286 | /* optionally write high bits as well */ | |
287 | if (write64bit) { | |
288 | addr += 4; | |
289 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); | |
290 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
291 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
292 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
293 | } | |
294 | ||
295 | /* generate an interrupt */ | |
296 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); | |
297 | } | |
298 | ||
a2e73f56 AD |
299 | /** |
300 | * cik_sdma_gfx_stop - stop the gfx async dma engines | |
301 | * | |
302 | * @adev: amdgpu_device pointer | |
303 | * | |
304 | * Stop the gfx async dma ring buffers (CIK). | |
305 | */ | |
306 | static void cik_sdma_gfx_stop(struct amdgpu_device *adev) | |
307 | { | |
c113ea1c AD |
308 | struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; |
309 | struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; | |
a2e73f56 AD |
310 | u32 rb_cntl; |
311 | int i; | |
312 | ||
313 | if ((adev->mman.buffer_funcs_ring == sdma0) || | |
314 | (adev->mman.buffer_funcs_ring == sdma1)) | |
57adc4ce | 315 | amdgpu_ttm_set_buffer_funcs_status(adev, false); |
a2e73f56 | 316 | |
c113ea1c | 317 | for (i = 0; i < adev->sdma.num_instances; i++) { |
a2e73f56 AD |
318 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); |
319 | rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; | |
320 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
321 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); | |
322 | } | |
c66ed765 AG |
323 | sdma0->sched.ready = false; |
324 | sdma1->sched.ready = false; | |
a2e73f56 AD |
325 | } |
326 | ||
327 | /** | |
328 | * cik_sdma_rlc_stop - stop the compute async dma engines | |
329 | * | |
330 | * @adev: amdgpu_device pointer | |
331 | * | |
332 | * Stop the compute async dma queues (CIK). | |
333 | */ | |
334 | static void cik_sdma_rlc_stop(struct amdgpu_device *adev) | |
335 | { | |
336 | /* XXX todo */ | |
337 | } | |
338 | ||
763dbbfa FK |
339 | /** |
340 | * cik_ctx_switch_enable - stop the async dma engines context switch | |
341 | * | |
342 | * @adev: amdgpu_device pointer | |
343 | * @enable: enable/disable the DMA MEs context switch. | |
344 | * | |
345 | * Halt or unhalt the async dma engines context switch (VI). | |
346 | */ | |
347 | static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable) | |
348 | { | |
a667386c | 349 | u32 f32_cntl, phase_quantum = 0; |
763dbbfa FK |
350 | int i; |
351 | ||
a667386c FK |
352 | if (amdgpu_sdma_phase_quantum) { |
353 | unsigned value = amdgpu_sdma_phase_quantum; | |
354 | unsigned unit = 0; | |
355 | ||
356 | while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> | |
357 | SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { | |
358 | value = (value + 1) >> 1; | |
359 | unit++; | |
360 | } | |
361 | if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> | |
362 | SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { | |
363 | value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> | |
364 | SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); | |
365 | unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> | |
366 | SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); | |
367 | WARN_ONCE(1, | |
368 | "clamping sdma_phase_quantum to %uK clock cycles\n", | |
369 | value << unit); | |
370 | } | |
371 | phase_quantum = | |
372 | value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | | |
373 | unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; | |
374 | } | |
375 | ||
763dbbfa FK |
376 | for (i = 0; i < adev->sdma.num_instances; i++) { |
377 | f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); | |
378 | if (enable) { | |
379 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, | |
380 | AUTO_CTXSW_ENABLE, 1); | |
a667386c FK |
381 | if (amdgpu_sdma_phase_quantum) { |
382 | WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], | |
383 | phase_quantum); | |
384 | WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], | |
385 | phase_quantum); | |
386 | } | |
763dbbfa FK |
387 | } else { |
388 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, | |
389 | AUTO_CTXSW_ENABLE, 0); | |
390 | } | |
391 | ||
392 | WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); | |
393 | } | |
394 | } | |
395 | ||
a2e73f56 AD |
396 | /** |
397 | * cik_sdma_enable - stop the async dma engines | |
398 | * | |
399 | * @adev: amdgpu_device pointer | |
400 | * @enable: enable/disable the DMA MEs. | |
401 | * | |
402 | * Halt or unhalt the async dma engines (CIK). | |
403 | */ | |
404 | static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) | |
405 | { | |
406 | u32 me_cntl; | |
407 | int i; | |
408 | ||
004e29cc | 409 | if (!enable) { |
a2e73f56 AD |
410 | cik_sdma_gfx_stop(adev); |
411 | cik_sdma_rlc_stop(adev); | |
412 | } | |
413 | ||
c113ea1c | 414 | for (i = 0; i < adev->sdma.num_instances; i++) { |
a2e73f56 AD |
415 | me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); |
416 | if (enable) | |
417 | me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; | |
418 | else | |
419 | me_cntl |= SDMA0_F32_CNTL__HALT_MASK; | |
420 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); | |
421 | } | |
422 | } | |
423 | ||
424 | /** | |
425 | * cik_sdma_gfx_resume - setup and start the async dma engines | |
426 | * | |
427 | * @adev: amdgpu_device pointer | |
428 | * | |
429 | * Set up the gfx DMA ring buffers and enable them (CIK). | |
430 | * Returns 0 for success, error for failure. | |
431 | */ | |
432 | static int cik_sdma_gfx_resume(struct amdgpu_device *adev) | |
433 | { | |
434 | struct amdgpu_ring *ring; | |
435 | u32 rb_cntl, ib_cntl; | |
436 | u32 rb_bufsz; | |
437 | u32 wb_offset; | |
438 | int i, j, r; | |
439 | ||
c113ea1c AD |
440 | for (i = 0; i < adev->sdma.num_instances; i++) { |
441 | ring = &adev->sdma.instance[i].ring; | |
a2e73f56 AD |
442 | wb_offset = (ring->rptr_offs * 4); |
443 | ||
444 | mutex_lock(&adev->srbm_mutex); | |
445 | for (j = 0; j < 16; j++) { | |
446 | cik_srbm_select(adev, 0, 0, 0, j); | |
447 | /* SDMA GFX */ | |
448 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); | |
449 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); | |
450 | /* XXX SDMA RLC - todo */ | |
451 | } | |
452 | cik_srbm_select(adev, 0, 0, 0, 0); | |
453 | mutex_unlock(&adev->srbm_mutex); | |
454 | ||
2b3a765d AD |
455 | WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], |
456 | adev->gfx.config.gb_addr_config & 0x70); | |
457 | ||
a2e73f56 AD |
458 | WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); |
459 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); | |
460 | ||
461 | /* Set ring buffer size in dwords */ | |
462 | rb_bufsz = order_base_2(ring->ring_size / 4); | |
463 | rb_cntl = rb_bufsz << 1; | |
464 | #ifdef __BIG_ENDIAN | |
454fc95e AD |
465 | rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | |
466 | SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; | |
a2e73f56 AD |
467 | #endif |
468 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
469 | ||
470 | /* Initialize the ring buffer's read and write pointers */ | |
471 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); | |
472 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); | |
d72f7c06 ML |
473 | WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); |
474 | WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); | |
a2e73f56 AD |
475 | |
476 | /* set the wb address whether it's enabled or not */ | |
477 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], | |
478 | upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); | |
479 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], | |
480 | ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); | |
481 | ||
482 | rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; | |
483 | ||
484 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); | |
485 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); | |
486 | ||
487 | ring->wptr = 0; | |
536fbf94 | 488 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); |
a2e73f56 AD |
489 | |
490 | /* enable DMA RB */ | |
491 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], | |
492 | rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); | |
493 | ||
494 | ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; | |
495 | #ifdef __BIG_ENDIAN | |
496 | ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; | |
497 | #endif | |
498 | /* enable DMA IBs */ | |
499 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
500 | ||
c66ed765 | 501 | ring->sched.ready = true; |
505dfe76 ML |
502 | } |
503 | ||
504 | cik_sdma_enable(adev, true); | |
a2e73f56 | 505 | |
505dfe76 ML |
506 | for (i = 0; i < adev->sdma.num_instances; i++) { |
507 | ring = &adev->sdma.instance[i].ring; | |
c66ed765 AG |
508 | r = amdgpu_ring_test_helper(ring); |
509 | if (r) | |
a2e73f56 | 510 | return r; |
a2e73f56 AD |
511 | |
512 | if (adev->mman.buffer_funcs_ring == ring) | |
57adc4ce | 513 | amdgpu_ttm_set_buffer_funcs_status(adev, true); |
a2e73f56 AD |
514 | } |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
519 | /** | |
520 | * cik_sdma_rlc_resume - setup and start the async dma engines | |
521 | * | |
522 | * @adev: amdgpu_device pointer | |
523 | * | |
524 | * Set up the compute DMA queues and enable them (CIK). | |
525 | * Returns 0 for success, error for failure. | |
526 | */ | |
527 | static int cik_sdma_rlc_resume(struct amdgpu_device *adev) | |
528 | { | |
529 | /* XXX todo */ | |
530 | return 0; | |
531 | } | |
532 | ||
533 | /** | |
534 | * cik_sdma_load_microcode - load the sDMA ME ucode | |
535 | * | |
536 | * @adev: amdgpu_device pointer | |
537 | * | |
538 | * Loads the sDMA0/1 ucode. | |
539 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
540 | */ | |
541 | static int cik_sdma_load_microcode(struct amdgpu_device *adev) | |
542 | { | |
543 | const struct sdma_firmware_header_v1_0 *hdr; | |
544 | const __le32 *fw_data; | |
545 | u32 fw_size; | |
546 | int i, j; | |
547 | ||
a2e73f56 AD |
548 | /* halt the MEs */ |
549 | cik_sdma_enable(adev, false); | |
550 | ||
c113ea1c AD |
551 | for (i = 0; i < adev->sdma.num_instances; i++) { |
552 | if (!adev->sdma.instance[i].fw) | |
553 | return -EINVAL; | |
554 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; | |
a2e73f56 AD |
555 | amdgpu_ucode_print_sdma_hdr(&hdr->header); |
556 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
c113ea1c AD |
557 | adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); |
558 | adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
559 | if (adev->sdma.instance[i].feature_version >= 20) | |
560 | adev->sdma.instance[i].burst_nop = true; | |
a2e73f56 | 561 | fw_data = (const __le32 *) |
c113ea1c | 562 | (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
a2e73f56 AD |
563 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); |
564 | for (j = 0; j < fw_size; j++) | |
565 | WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); | |
c113ea1c | 566 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); |
a2e73f56 AD |
567 | } |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
572 | /** | |
573 | * cik_sdma_start - setup and start the async dma engines | |
574 | * | |
575 | * @adev: amdgpu_device pointer | |
576 | * | |
577 | * Set up the DMA engines and enable them (CIK). | |
578 | * Returns 0 for success, error for failure. | |
579 | */ | |
580 | static int cik_sdma_start(struct amdgpu_device *adev) | |
581 | { | |
582 | int r; | |
583 | ||
584 | r = cik_sdma_load_microcode(adev); | |
585 | if (r) | |
586 | return r; | |
587 | ||
505dfe76 ML |
588 | /* halt the engine before programing */ |
589 | cik_sdma_enable(adev, false); | |
763dbbfa FK |
590 | /* enable sdma ring preemption */ |
591 | cik_ctx_switch_enable(adev, true); | |
a2e73f56 AD |
592 | |
593 | /* start the gfx rings and rlc compute queues */ | |
594 | r = cik_sdma_gfx_resume(adev); | |
595 | if (r) | |
596 | return r; | |
597 | r = cik_sdma_rlc_resume(adev); | |
598 | if (r) | |
599 | return r; | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | /** | |
605 | * cik_sdma_ring_test_ring - simple async dma engine test | |
606 | * | |
607 | * @ring: amdgpu_ring structure holding ring information | |
608 | * | |
609 | * Test the DMA engine by writing using it to write an | |
610 | * value to memory. (CIK). | |
611 | * Returns 0 for success, error for failure. | |
612 | */ | |
613 | static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) | |
614 | { | |
615 | struct amdgpu_device *adev = ring->adev; | |
616 | unsigned i; | |
617 | unsigned index; | |
618 | int r; | |
619 | u32 tmp; | |
620 | u64 gpu_addr; | |
621 | ||
131b4b36 | 622 | r = amdgpu_device_wb_get(adev, &index); |
dc9eeff8 | 623 | if (r) |
a2e73f56 | 624 | return r; |
a2e73f56 AD |
625 | |
626 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
627 | tmp = 0xCAFEDEAD; | |
628 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
629 | ||
a27de35c | 630 | r = amdgpu_ring_alloc(ring, 5); |
dc9eeff8 CK |
631 | if (r) |
632 | goto error_free_wb; | |
633 | ||
a2e73f56 AD |
634 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); |
635 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); | |
636 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); | |
637 | amdgpu_ring_write(ring, 1); /* number of DWs to follow */ | |
638 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
a27de35c | 639 | amdgpu_ring_commit(ring); |
a2e73f56 AD |
640 | |
641 | for (i = 0; i < adev->usec_timeout; i++) { | |
642 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
643 | if (tmp == 0xDEADBEEF) | |
644 | break; | |
c366be54 | 645 | udelay(1); |
a2e73f56 AD |
646 | } |
647 | ||
dc9eeff8 CK |
648 | if (i >= adev->usec_timeout) |
649 | r = -ETIMEDOUT; | |
a2e73f56 | 650 | |
dc9eeff8 CK |
651 | error_free_wb: |
652 | amdgpu_device_wb_free(adev, index); | |
a2e73f56 AD |
653 | return r; |
654 | } | |
655 | ||
656 | /** | |
657 | * cik_sdma_ring_test_ib - test an IB on the DMA engine | |
658 | * | |
659 | * @ring: amdgpu_ring structure holding ring information | |
660 | * | |
661 | * Test a simple IB in the DMA ring (CIK). | |
662 | * Returns 0 on success, error on failure. | |
663 | */ | |
bbec97aa | 664 | static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
a2e73f56 AD |
665 | { |
666 | struct amdgpu_device *adev = ring->adev; | |
667 | struct amdgpu_ib ib; | |
f54d1867 | 668 | struct dma_fence *f = NULL; |
a2e73f56 | 669 | unsigned index; |
a2e73f56 AD |
670 | u32 tmp = 0; |
671 | u64 gpu_addr; | |
bbec97aa | 672 | long r; |
a2e73f56 | 673 | |
131b4b36 | 674 | r = amdgpu_device_wb_get(adev, &index); |
98079389 | 675 | if (r) |
a2e73f56 | 676 | return r; |
a2e73f56 AD |
677 | |
678 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
679 | tmp = 0xCAFEDEAD; | |
680 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
b203dd95 | 681 | memset(&ib, 0, sizeof(ib)); |
b07c60c0 | 682 | r = amdgpu_ib_get(adev, NULL, 256, &ib); |
98079389 | 683 | if (r) |
0011fdaa | 684 | goto err0; |
a2e73f56 | 685 | |
6d44565d CK |
686 | ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, |
687 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
a2e73f56 AD |
688 | ib.ptr[1] = lower_32_bits(gpu_addr); |
689 | ib.ptr[2] = upper_32_bits(gpu_addr); | |
690 | ib.ptr[3] = 1; | |
691 | ib.ptr[4] = 0xDEADBEEF; | |
692 | ib.length_dw = 5; | |
50ddc75e | 693 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); |
0011fdaa CZ |
694 | if (r) |
695 | goto err1; | |
a2e73f56 | 696 | |
f54d1867 | 697 | r = dma_fence_wait_timeout(f, false, timeout); |
bbec97aa | 698 | if (r == 0) { |
bbec97aa CK |
699 | r = -ETIMEDOUT; |
700 | goto err1; | |
701 | } else if (r < 0) { | |
0011fdaa | 702 | goto err1; |
a2e73f56 | 703 | } |
6d44565d | 704 | tmp = le32_to_cpu(adev->wb.wb[index]); |
98079389 | 705 | if (tmp == 0xDEADBEEF) |
bbec97aa | 706 | r = 0; |
98079389 | 707 | else |
a2e73f56 | 708 | r = -EINVAL; |
0011fdaa CZ |
709 | |
710 | err1: | |
cc55c45d | 711 | amdgpu_ib_free(adev, &ib, NULL); |
f54d1867 | 712 | dma_fence_put(f); |
0011fdaa | 713 | err0: |
131b4b36 | 714 | amdgpu_device_wb_free(adev, index); |
a2e73f56 AD |
715 | return r; |
716 | } | |
717 | ||
718 | /** | |
719 | * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART | |
720 | * | |
721 | * @ib: indirect buffer to fill with commands | |
722 | * @pe: addr of the page entry | |
723 | * @src: src addr to copy from | |
724 | * @count: number of page entries to update | |
725 | * | |
726 | * Update PTEs by copying them from the GART using sDMA (CIK). | |
727 | */ | |
728 | static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, | |
729 | uint64_t pe, uint64_t src, | |
730 | unsigned count) | |
731 | { | |
96105e53 CK |
732 | unsigned bytes = count * 8; |
733 | ||
734 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, | |
735 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
736 | ib->ptr[ib->length_dw++] = bytes; | |
737 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
738 | ib->ptr[ib->length_dw++] = lower_32_bits(src); | |
739 | ib->ptr[ib->length_dw++] = upper_32_bits(src); | |
740 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
741 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
a2e73f56 AD |
742 | } |
743 | ||
744 | /** | |
745 | * cik_sdma_vm_write_pages - update PTEs by writing them manually | |
746 | * | |
747 | * @ib: indirect buffer to fill with commands | |
748 | * @pe: addr of the page entry | |
de9ea7bd | 749 | * @value: dst addr to write into pe |
a2e73f56 AD |
750 | * @count: number of page entries to update |
751 | * @incr: increase next addr by incr bytes | |
a2e73f56 AD |
752 | * |
753 | * Update PTEs by writing them manually using sDMA (CIK). | |
754 | */ | |
de9ea7bd CK |
755 | static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, |
756 | uint64_t value, unsigned count, | |
757 | uint32_t incr) | |
a2e73f56 | 758 | { |
de9ea7bd CK |
759 | unsigned ndw = count * 2; |
760 | ||
761 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, | |
762 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
763 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
764 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
765 | ib->ptr[ib->length_dw++] = ndw; | |
766 | for (; ndw > 0; ndw -= 2) { | |
767 | ib->ptr[ib->length_dw++] = lower_32_bits(value); | |
768 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
769 | value += incr; | |
a2e73f56 AD |
770 | } |
771 | } | |
772 | ||
773 | /** | |
774 | * cik_sdma_vm_set_pages - update the page tables using sDMA | |
775 | * | |
776 | * @ib: indirect buffer to fill with commands | |
777 | * @pe: addr of the page entry | |
778 | * @addr: dst addr to write into pe | |
779 | * @count: number of page entries to update | |
780 | * @incr: increase next addr by incr bytes | |
781 | * @flags: access flags | |
782 | * | |
783 | * Update the page tables using sDMA (CIK). | |
784 | */ | |
96105e53 | 785 | static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, |
a2e73f56 | 786 | uint64_t addr, unsigned count, |
6b777607 | 787 | uint32_t incr, uint64_t flags) |
a2e73f56 | 788 | { |
96105e53 CK |
789 | /* for physically contiguous pages (vram) */ |
790 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); | |
791 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ | |
792 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
b9be700e JZ |
793 | ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ |
794 | ib->ptr[ib->length_dw++] = upper_32_bits(flags); | |
96105e53 CK |
795 | ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ |
796 | ib->ptr[ib->length_dw++] = upper_32_bits(addr); | |
797 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
798 | ib->ptr[ib->length_dw++] = 0; | |
799 | ib->ptr[ib->length_dw++] = count; /* number of entries */ | |
a2e73f56 AD |
800 | } |
801 | ||
802 | /** | |
803 | * cik_sdma_vm_pad_ib - pad the IB to the required number of dw | |
804 | * | |
805 | * @ib: indirect buffer to fill with padding | |
806 | * | |
807 | */ | |
9e5d5309 | 808 | static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) |
a2e73f56 | 809 | { |
ccf191f8 | 810 | struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); |
ac01db3d JZ |
811 | u32 pad_count; |
812 | int i; | |
813 | ||
814 | pad_count = (8 - (ib->length_dw & 0x7)) % 8; | |
815 | for (i = 0; i < pad_count; i++) | |
816 | if (sdma && sdma->burst_nop && (i == 0)) | |
817 | ib->ptr[ib->length_dw++] = | |
818 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | | |
819 | SDMA_NOP_COUNT(pad_count - 1); | |
820 | else | |
821 | ib->ptr[ib->length_dw++] = | |
822 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); | |
a2e73f56 AD |
823 | } |
824 | ||
825 | /** | |
00b7c4ff | 826 | * cik_sdma_ring_emit_pipeline_sync - sync the pipeline |
a2e73f56 AD |
827 | * |
828 | * @ring: amdgpu_ring pointer | |
a2e73f56 | 829 | * |
00b7c4ff | 830 | * Make sure all previous operations are completed (CIK). |
a2e73f56 | 831 | */ |
00b7c4ff | 832 | static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |
a2e73f56 | 833 | { |
5c55db83 CZ |
834 | uint32_t seq = ring->fence_drv.sync_seq; |
835 | uint64_t addr = ring->fence_drv.gpu_addr; | |
836 | ||
837 | /* wait for idle */ | |
838 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, | |
839 | SDMA_POLL_REG_MEM_EXTRA_OP(0) | | |
840 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */ | |
841 | SDMA_POLL_REG_MEM_EXTRA_M)); | |
842 | amdgpu_ring_write(ring, addr & 0xfffffffc); | |
843 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); | |
844 | amdgpu_ring_write(ring, seq); /* reference */ | |
4a8e06f7 | 845 | amdgpu_ring_write(ring, 0xffffffff); /* mask */ |
5c55db83 | 846 | amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */ |
00b7c4ff | 847 | } |
5c55db83 | 848 | |
a2e73f56 AD |
849 | /** |
850 | * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA | |
851 | * | |
852 | * @ring: amdgpu_ring pointer | |
853 | * @vm: amdgpu_vm pointer | |
854 | * | |
855 | * Update the page table base and flush the VM TLB | |
856 | * using sDMA (CIK). | |
857 | */ | |
858 | static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
c633c00b | 859 | unsigned vmid, uint64_t pd_addr) |
a2e73f56 AD |
860 | { |
861 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | | |
862 | SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ | |
863 | ||
c633c00b | 864 | amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); |
a2e73f56 AD |
865 | |
866 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
867 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); | |
868 | amdgpu_ring_write(ring, 0); | |
869 | amdgpu_ring_write(ring, 0); /* reference */ | |
870 | amdgpu_ring_write(ring, 0); /* mask */ | |
871 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
872 | } | |
873 | ||
a37e69db CK |
874 | static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring, |
875 | uint32_t reg, uint32_t val) | |
876 | { | |
877 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
878 | amdgpu_ring_write(ring, reg); | |
879 | amdgpu_ring_write(ring, val); | |
880 | } | |
881 | ||
a2e73f56 AD |
882 | static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, |
883 | bool enable) | |
884 | { | |
885 | u32 orig, data; | |
886 | ||
e3b04bc7 | 887 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { |
a2e73f56 AD |
888 | WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); |
889 | WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); | |
890 | } else { | |
891 | orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); | |
892 | data |= 0xff000000; | |
893 | if (data != orig) | |
894 | WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); | |
895 | ||
896 | orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); | |
897 | data |= 0xff000000; | |
898 | if (data != orig) | |
899 | WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); | |
900 | } | |
901 | } | |
902 | ||
903 | static void cik_enable_sdma_mgls(struct amdgpu_device *adev, | |
904 | bool enable) | |
905 | { | |
906 | u32 orig, data; | |
907 | ||
e3b04bc7 | 908 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { |
a2e73f56 AD |
909 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); |
910 | data |= 0x100; | |
911 | if (orig != data) | |
912 | WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); | |
913 | ||
914 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); | |
915 | data |= 0x100; | |
916 | if (orig != data) | |
917 | WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); | |
918 | } else { | |
919 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); | |
920 | data &= ~0x100; | |
921 | if (orig != data) | |
922 | WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); | |
923 | ||
924 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); | |
925 | data &= ~0x100; | |
926 | if (orig != data) | |
927 | WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); | |
928 | } | |
929 | } | |
930 | ||
5fc3aeeb | 931 | static int cik_sdma_early_init(void *handle) |
a2e73f56 | 932 | { |
5fc3aeeb | 933 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
934 | ||
c113ea1c AD |
935 | adev->sdma.num_instances = SDMA_MAX_INSTANCE; |
936 | ||
a2e73f56 AD |
937 | cik_sdma_set_ring_funcs(adev); |
938 | cik_sdma_set_irq_funcs(adev); | |
939 | cik_sdma_set_buffer_funcs(adev); | |
940 | cik_sdma_set_vm_pte_funcs(adev); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
5fc3aeeb | 945 | static int cik_sdma_sw_init(void *handle) |
a2e73f56 AD |
946 | { |
947 | struct amdgpu_ring *ring; | |
5fc3aeeb | 948 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c113ea1c | 949 | int r, i; |
a2e73f56 AD |
950 | |
951 | r = cik_sdma_init_microcode(adev); | |
952 | if (r) { | |
953 | DRM_ERROR("Failed to load sdma firmware!\n"); | |
954 | return r; | |
955 | } | |
956 | ||
957 | /* SDMA trap event */ | |
1ffdeca6 | 958 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224, |
d766e6a3 | 959 | &adev->sdma.trap_irq); |
a2e73f56 AD |
960 | if (r) |
961 | return r; | |
962 | ||
963 | /* SDMA Privileged inst */ | |
1ffdeca6 | 964 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, |
d766e6a3 | 965 | &adev->sdma.illegal_inst_irq); |
a2e73f56 AD |
966 | if (r) |
967 | return r; | |
968 | ||
969 | /* SDMA Privileged inst */ | |
1ffdeca6 | 970 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247, |
d766e6a3 | 971 | &adev->sdma.illegal_inst_irq); |
a2e73f56 AD |
972 | if (r) |
973 | return r; | |
974 | ||
c113ea1c AD |
975 | for (i = 0; i < adev->sdma.num_instances; i++) { |
976 | ring = &adev->sdma.instance[i].ring; | |
977 | ring->ring_obj = NULL; | |
978 | sprintf(ring->name, "sdma%d", i); | |
b38d99c4 | 979 | r = amdgpu_ring_init(adev, ring, 1024, |
c113ea1c AD |
980 | &adev->sdma.trap_irq, |
981 | (i == 0) ? | |
af67772d ED |
982 | AMDGPU_SDMA_IRQ_INSTANCE0 : |
983 | AMDGPU_SDMA_IRQ_INSTANCE1); | |
c113ea1c AD |
984 | if (r) |
985 | return r; | |
986 | } | |
a2e73f56 AD |
987 | |
988 | return r; | |
989 | } | |
990 | ||
5fc3aeeb | 991 | static int cik_sdma_sw_fini(void *handle) |
a2e73f56 | 992 | { |
5fc3aeeb | 993 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c113ea1c | 994 | int i; |
5fc3aeeb | 995 | |
c113ea1c AD |
996 | for (i = 0; i < adev->sdma.num_instances; i++) |
997 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); | |
a2e73f56 | 998 | |
d1ff53b7 | 999 | cik_sdma_free_microcode(adev); |
a2e73f56 AD |
1000 | return 0; |
1001 | } | |
1002 | ||
5fc3aeeb | 1003 | static int cik_sdma_hw_init(void *handle) |
a2e73f56 AD |
1004 | { |
1005 | int r; | |
5fc3aeeb | 1006 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1007 | |
1008 | r = cik_sdma_start(adev); | |
1009 | if (r) | |
1010 | return r; | |
1011 | ||
1012 | return r; | |
1013 | } | |
1014 | ||
5fc3aeeb | 1015 | static int cik_sdma_hw_fini(void *handle) |
a2e73f56 | 1016 | { |
5fc3aeeb | 1017 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1018 | ||
763dbbfa | 1019 | cik_ctx_switch_enable(adev, false); |
a2e73f56 AD |
1020 | cik_sdma_enable(adev, false); |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
5fc3aeeb | 1025 | static int cik_sdma_suspend(void *handle) |
a2e73f56 | 1026 | { |
5fc3aeeb | 1027 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1028 | |
1029 | return cik_sdma_hw_fini(adev); | |
1030 | } | |
1031 | ||
5fc3aeeb | 1032 | static int cik_sdma_resume(void *handle) |
a2e73f56 | 1033 | { |
5fc3aeeb | 1034 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 | 1035 | |
10ea9434 | 1036 | cik_sdma_soft_reset(handle); |
1037 | ||
a2e73f56 AD |
1038 | return cik_sdma_hw_init(adev); |
1039 | } | |
1040 | ||
5fc3aeeb | 1041 | static bool cik_sdma_is_idle(void *handle) |
a2e73f56 | 1042 | { |
5fc3aeeb | 1043 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1044 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1045 | ||
1046 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1047 | SRBM_STATUS2__SDMA1_BUSY_MASK)) | |
1048 | return false; | |
1049 | ||
1050 | return true; | |
1051 | } | |
1052 | ||
5fc3aeeb | 1053 | static int cik_sdma_wait_for_idle(void *handle) |
a2e73f56 AD |
1054 | { |
1055 | unsigned i; | |
1056 | u32 tmp; | |
5fc3aeeb | 1057 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1058 | |
1059 | for (i = 0; i < adev->usec_timeout; i++) { | |
1060 | tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1061 | SRBM_STATUS2__SDMA1_BUSY_MASK); | |
1062 | ||
1063 | if (!tmp) | |
1064 | return 0; | |
1065 | udelay(1); | |
1066 | } | |
1067 | return -ETIMEDOUT; | |
1068 | } | |
1069 | ||
5fc3aeeb | 1070 | static int cik_sdma_soft_reset(void *handle) |
a2e73f56 AD |
1071 | { |
1072 | u32 srbm_soft_reset = 0; | |
5fc3aeeb | 1073 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1074 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1075 | ||
1076 | if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { | |
1077 | /* sdma0 */ | |
1078 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); | |
1079 | tmp |= SDMA0_F32_CNTL__HALT_MASK; | |
1080 | WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); | |
1081 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; | |
1082 | } | |
1083 | if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { | |
1084 | /* sdma1 */ | |
1085 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); | |
1086 | tmp |= SDMA0_F32_CNTL__HALT_MASK; | |
1087 | WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); | |
1088 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; | |
1089 | } | |
1090 | ||
1091 | if (srbm_soft_reset) { | |
a2e73f56 AD |
1092 | tmp = RREG32(mmSRBM_SOFT_RESET); |
1093 | tmp |= srbm_soft_reset; | |
1094 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1095 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1096 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1097 | ||
1098 | udelay(50); | |
1099 | ||
1100 | tmp &= ~srbm_soft_reset; | |
1101 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1102 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1103 | ||
1104 | /* Wait a little for things to settle down */ | |
1105 | udelay(50); | |
a2e73f56 AD |
1106 | } |
1107 | ||
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, | |
1112 | struct amdgpu_irq_src *src, | |
1113 | unsigned type, | |
1114 | enum amdgpu_interrupt_state state) | |
1115 | { | |
1116 | u32 sdma_cntl; | |
1117 | ||
1118 | switch (type) { | |
af67772d | 1119 | case AMDGPU_SDMA_IRQ_INSTANCE0: |
a2e73f56 AD |
1120 | switch (state) { |
1121 | case AMDGPU_IRQ_STATE_DISABLE: | |
1122 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1123 | sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1124 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1125 | break; | |
1126 | case AMDGPU_IRQ_STATE_ENABLE: | |
1127 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1128 | sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1129 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1130 | break; | |
1131 | default: | |
1132 | break; | |
1133 | } | |
1134 | break; | |
af67772d | 1135 | case AMDGPU_SDMA_IRQ_INSTANCE1: |
a2e73f56 AD |
1136 | switch (state) { |
1137 | case AMDGPU_IRQ_STATE_DISABLE: | |
1138 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1139 | sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1140 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1141 | break; | |
1142 | case AMDGPU_IRQ_STATE_ENABLE: | |
1143 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1144 | sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1145 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1146 | break; | |
1147 | default: | |
1148 | break; | |
1149 | } | |
1150 | break; | |
1151 | default: | |
1152 | break; | |
1153 | } | |
1154 | return 0; | |
1155 | } | |
1156 | ||
1157 | static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, | |
1158 | struct amdgpu_irq_src *source, | |
1159 | struct amdgpu_iv_entry *entry) | |
1160 | { | |
1161 | u8 instance_id, queue_id; | |
1162 | ||
1163 | instance_id = (entry->ring_id & 0x3) >> 0; | |
1164 | queue_id = (entry->ring_id & 0xc) >> 2; | |
1165 | DRM_DEBUG("IH: SDMA trap\n"); | |
1166 | switch (instance_id) { | |
1167 | case 0: | |
1168 | switch (queue_id) { | |
1169 | case 0: | |
c113ea1c | 1170 | amdgpu_fence_process(&adev->sdma.instance[0].ring); |
a2e73f56 AD |
1171 | break; |
1172 | case 1: | |
1173 | /* XXX compute */ | |
1174 | break; | |
1175 | case 2: | |
1176 | /* XXX compute */ | |
1177 | break; | |
1178 | } | |
1179 | break; | |
1180 | case 1: | |
1181 | switch (queue_id) { | |
1182 | case 0: | |
c113ea1c | 1183 | amdgpu_fence_process(&adev->sdma.instance[1].ring); |
a2e73f56 AD |
1184 | break; |
1185 | case 1: | |
1186 | /* XXX compute */ | |
1187 | break; | |
1188 | case 2: | |
1189 | /* XXX compute */ | |
1190 | break; | |
1191 | } | |
1192 | break; | |
1193 | } | |
1194 | ||
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, | |
1199 | struct amdgpu_irq_src *source, | |
1200 | struct amdgpu_iv_entry *entry) | |
1201 | { | |
898c2cb5 CK |
1202 | u8 instance_id; |
1203 | ||
a2e73f56 | 1204 | DRM_ERROR("Illegal instruction in SDMA command stream\n"); |
898c2cb5 CK |
1205 | instance_id = (entry->ring_id & 0x3) >> 0; |
1206 | drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); | |
a2e73f56 AD |
1207 | return 0; |
1208 | } | |
1209 | ||
5fc3aeeb | 1210 | static int cik_sdma_set_clockgating_state(void *handle, |
1211 | enum amd_clockgating_state state) | |
a2e73f56 AD |
1212 | { |
1213 | bool gate = false; | |
5fc3aeeb | 1214 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 | 1215 | |
5fc3aeeb | 1216 | if (state == AMD_CG_STATE_GATE) |
a2e73f56 AD |
1217 | gate = true; |
1218 | ||
1219 | cik_enable_sdma_mgcg(adev, gate); | |
1220 | cik_enable_sdma_mgls(adev, gate); | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
5fc3aeeb | 1225 | static int cik_sdma_set_powergating_state(void *handle, |
1226 | enum amd_powergating_state state) | |
a2e73f56 AD |
1227 | { |
1228 | return 0; | |
1229 | } | |
1230 | ||
a1255107 | 1231 | static const struct amd_ip_funcs cik_sdma_ip_funcs = { |
88a907d6 | 1232 | .name = "cik_sdma", |
a2e73f56 AD |
1233 | .early_init = cik_sdma_early_init, |
1234 | .late_init = NULL, | |
1235 | .sw_init = cik_sdma_sw_init, | |
1236 | .sw_fini = cik_sdma_sw_fini, | |
1237 | .hw_init = cik_sdma_hw_init, | |
1238 | .hw_fini = cik_sdma_hw_fini, | |
1239 | .suspend = cik_sdma_suspend, | |
1240 | .resume = cik_sdma_resume, | |
1241 | .is_idle = cik_sdma_is_idle, | |
1242 | .wait_for_idle = cik_sdma_wait_for_idle, | |
1243 | .soft_reset = cik_sdma_soft_reset, | |
a2e73f56 AD |
1244 | .set_clockgating_state = cik_sdma_set_clockgating_state, |
1245 | .set_powergating_state = cik_sdma_set_powergating_state, | |
1246 | }; | |
1247 | ||
a2e73f56 | 1248 | static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { |
21cd942e | 1249 | .type = AMDGPU_RING_TYPE_SDMA, |
79887142 CK |
1250 | .align_mask = 0xf, |
1251 | .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), | |
536fbf94 | 1252 | .support_64bit_ptrs = false, |
a2e73f56 AD |
1253 | .get_rptr = cik_sdma_ring_get_rptr, |
1254 | .get_wptr = cik_sdma_ring_get_wptr, | |
1255 | .set_wptr = cik_sdma_ring_set_wptr, | |
e12f3d7a CK |
1256 | .emit_frame_size = |
1257 | 6 + /* cik_sdma_ring_emit_hdp_flush */ | |
2ee150cd | 1258 | 3 + /* hdp invalidate */ |
e12f3d7a | 1259 | 6 + /* cik_sdma_ring_emit_pipeline_sync */ |
d9a701cc | 1260 | CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */ |
e12f3d7a CK |
1261 | 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ |
1262 | .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */ | |
a2e73f56 AD |
1263 | .emit_ib = cik_sdma_ring_emit_ib, |
1264 | .emit_fence = cik_sdma_ring_emit_fence, | |
00b7c4ff | 1265 | .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, |
a2e73f56 | 1266 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, |
d2edb07b | 1267 | .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, |
a2e73f56 AD |
1268 | .test_ring = cik_sdma_ring_test_ring, |
1269 | .test_ib = cik_sdma_ring_test_ib, | |
ac01db3d | 1270 | .insert_nop = cik_sdma_ring_insert_nop, |
9e5d5309 | 1271 | .pad_ib = cik_sdma_ring_pad_ib, |
a37e69db | 1272 | .emit_wreg = cik_sdma_ring_emit_wreg, |
a2e73f56 AD |
1273 | }; |
1274 | ||
1275 | static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) | |
1276 | { | |
c113ea1c AD |
1277 | int i; |
1278 | ||
1cf0abb6 | 1279 | for (i = 0; i < adev->sdma.num_instances; i++) { |
c113ea1c | 1280 | adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; |
1cf0abb6 AD |
1281 | adev->sdma.instance[i].ring.me = i; |
1282 | } | |
a2e73f56 AD |
1283 | } |
1284 | ||
1285 | static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { | |
1286 | .set = cik_sdma_set_trap_irq_state, | |
1287 | .process = cik_sdma_process_trap_irq, | |
1288 | }; | |
1289 | ||
1290 | static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { | |
1291 | .process = cik_sdma_process_illegal_inst_irq, | |
1292 | }; | |
1293 | ||
1294 | static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) | |
1295 | { | |
c113ea1c AD |
1296 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; |
1297 | adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; | |
1298 | adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; | |
a2e73f56 AD |
1299 | } |
1300 | ||
1301 | /** | |
1302 | * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine | |
1303 | * | |
1304 | * @ring: amdgpu_ring structure holding ring information | |
1305 | * @src_offset: src GPU address | |
1306 | * @dst_offset: dst GPU address | |
1307 | * @byte_count: number of bytes to xfer | |
1308 | * | |
1309 | * Copy GPU buffers using the DMA engine (CIK). | |
1310 | * Used by the amdgpu ttm implementation to move pages if | |
1311 | * registered as the asic copy callback. | |
1312 | */ | |
c7ae72c0 | 1313 | static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, |
a2e73f56 AD |
1314 | uint64_t src_offset, |
1315 | uint64_t dst_offset, | |
1316 | uint32_t byte_count) | |
1317 | { | |
c7ae72c0 CZ |
1318 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); |
1319 | ib->ptr[ib->length_dw++] = byte_count; | |
1320 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
1321 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); | |
1322 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); | |
1323 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1324 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
a2e73f56 AD |
1325 | } |
1326 | ||
1327 | /** | |
1328 | * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine | |
1329 | * | |
1330 | * @ring: amdgpu_ring structure holding ring information | |
1331 | * @src_data: value to write to buffer | |
1332 | * @dst_offset: dst GPU address | |
1333 | * @byte_count: number of bytes to xfer | |
1334 | * | |
1335 | * Fill GPU buffers using the DMA engine (CIK). | |
1336 | */ | |
6e7a3840 | 1337 | static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, |
a2e73f56 AD |
1338 | uint32_t src_data, |
1339 | uint64_t dst_offset, | |
1340 | uint32_t byte_count) | |
1341 | { | |
6e7a3840 CZ |
1342 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); |
1343 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1344 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
1345 | ib->ptr[ib->length_dw++] = src_data; | |
1346 | ib->ptr[ib->length_dw++] = byte_count; | |
a2e73f56 AD |
1347 | } |
1348 | ||
1349 | static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { | |
1350 | .copy_max_bytes = 0x1fffff, | |
1351 | .copy_num_dw = 7, | |
1352 | .emit_copy_buffer = cik_sdma_emit_copy_buffer, | |
1353 | ||
1354 | .fill_max_bytes = 0x1fffff, | |
1355 | .fill_num_dw = 5, | |
1356 | .emit_fill_buffer = cik_sdma_emit_fill_buffer, | |
1357 | }; | |
1358 | ||
1359 | static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) | |
1360 | { | |
f54b30d7 CK |
1361 | adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; |
1362 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; | |
a2e73f56 AD |
1363 | } |
1364 | ||
1365 | static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { | |
e6d92197 | 1366 | .copy_pte_num_dw = 7, |
a2e73f56 | 1367 | .copy_pte = cik_sdma_vm_copy_pte, |
e6d92197 | 1368 | |
a2e73f56 AD |
1369 | .write_pte = cik_sdma_vm_write_pte, |
1370 | .set_pte_pde = cik_sdma_vm_set_pte_pde, | |
a2e73f56 AD |
1371 | }; |
1372 | ||
1373 | static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) | |
1374 | { | |
3798e9a6 | 1375 | struct drm_gpu_scheduler *sched; |
2d55e45a CK |
1376 | unsigned i; |
1377 | ||
f54b30d7 CK |
1378 | adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; |
1379 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
1380 | sched = &adev->sdma.instance[i].ring.sched; | |
1381 | adev->vm_manager.vm_pte_rqs[i] = | |
1382 | &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; | |
a2e73f56 | 1383 | } |
f54b30d7 | 1384 | adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; |
a2e73f56 | 1385 | } |
a1255107 AD |
1386 | |
1387 | const struct amdgpu_ip_block_version cik_sdma_ip_block = | |
1388 | { | |
1389 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
1390 | .major = 2, | |
1391 | .minor = 0, | |
1392 | .rev = 0, | |
1393 | .funcs = &cik_sdma_ip_funcs, | |
1394 | }; |