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a2e73f56 AD |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_ucode.h" | |
28 | #include "amdgpu_trace.h" | |
29 | #include "cikd.h" | |
30 | #include "cik.h" | |
31 | ||
32 | #include "bif/bif_4_1_d.h" | |
33 | #include "bif/bif_4_1_sh_mask.h" | |
34 | ||
35 | #include "gca/gfx_7_2_d.h" | |
74a5d165 JX |
36 | #include "gca/gfx_7_2_enum.h" |
37 | #include "gca/gfx_7_2_sh_mask.h" | |
a2e73f56 AD |
38 | |
39 | #include "gmc/gmc_7_1_d.h" | |
40 | #include "gmc/gmc_7_1_sh_mask.h" | |
41 | ||
42 | #include "oss/oss_2_0_d.h" | |
43 | #include "oss/oss_2_0_sh_mask.h" | |
44 | ||
45 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = | |
46 | { | |
47 | SDMA0_REGISTER_OFFSET, | |
48 | SDMA1_REGISTER_OFFSET | |
49 | }; | |
50 | ||
51 | static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); | |
52 | static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); | |
53 | static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); | |
54 | static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); | |
10ea9434 | 55 | static int cik_sdma_soft_reset(void *handle); |
a2e73f56 AD |
56 | |
57 | MODULE_FIRMWARE("radeon/bonaire_sdma.bin"); | |
58 | MODULE_FIRMWARE("radeon/bonaire_sdma1.bin"); | |
59 | MODULE_FIRMWARE("radeon/hawaii_sdma.bin"); | |
60 | MODULE_FIRMWARE("radeon/hawaii_sdma1.bin"); | |
61 | MODULE_FIRMWARE("radeon/kaveri_sdma.bin"); | |
62 | MODULE_FIRMWARE("radeon/kaveri_sdma1.bin"); | |
63 | MODULE_FIRMWARE("radeon/kabini_sdma.bin"); | |
64 | MODULE_FIRMWARE("radeon/kabini_sdma1.bin"); | |
65 | MODULE_FIRMWARE("radeon/mullins_sdma.bin"); | |
66 | MODULE_FIRMWARE("radeon/mullins_sdma1.bin"); | |
67 | ||
68 | u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); | |
69 | ||
d1ff53b7 ML |
70 | |
71 | static void cik_sdma_free_microcode(struct amdgpu_device *adev) | |
72 | { | |
73 | int i; | |
74 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
75 | release_firmware(adev->sdma.instance[i].fw); | |
76 | adev->sdma.instance[i].fw = NULL; | |
77 | } | |
78 | } | |
79 | ||
a2e73f56 AD |
80 | /* |
81 | * sDMA - System DMA | |
82 | * Starting with CIK, the GPU has new asynchronous | |
83 | * DMA engines. These engines are used for compute | |
84 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | |
85 | * and each one supports 1 ring buffer used for gfx | |
86 | * and 2 queues used for compute. | |
87 | * | |
88 | * The programming model is very similar to the CP | |
89 | * (ring buffer, IBs, etc.), but sDMA has it's own | |
90 | * packet format that is different from the PM4 format | |
91 | * used by the CP. sDMA supports copying data, writing | |
92 | * embedded data, solid fills, and a number of other | |
93 | * things. It also has support for tiling/detiling of | |
94 | * buffers. | |
95 | */ | |
96 | ||
97 | /** | |
98 | * cik_sdma_init_microcode - load ucode images from disk | |
99 | * | |
100 | * @adev: amdgpu_device pointer | |
101 | * | |
102 | * Use the firmware interface to load the ucode images into | |
103 | * the driver (not loaded into hw). | |
104 | * Returns 0 on success, error on failure. | |
105 | */ | |
106 | static int cik_sdma_init_microcode(struct amdgpu_device *adev) | |
107 | { | |
108 | const char *chip_name; | |
109 | char fw_name[30]; | |
c113ea1c | 110 | int err = 0, i; |
a2e73f56 AD |
111 | |
112 | DRM_DEBUG("\n"); | |
113 | ||
114 | switch (adev->asic_type) { | |
115 | case CHIP_BONAIRE: | |
116 | chip_name = "bonaire"; | |
117 | break; | |
118 | case CHIP_HAWAII: | |
119 | chip_name = "hawaii"; | |
120 | break; | |
121 | case CHIP_KAVERI: | |
122 | chip_name = "kaveri"; | |
123 | break; | |
124 | case CHIP_KABINI: | |
125 | chip_name = "kabini"; | |
126 | break; | |
127 | case CHIP_MULLINS: | |
128 | chip_name = "mullins"; | |
129 | break; | |
130 | default: BUG(); | |
131 | } | |
132 | ||
c113ea1c | 133 | for (i = 0; i < adev->sdma.num_instances; i++) { |
a2e73f56 AD |
134 | if (i == 0) |
135 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); | |
136 | else | |
137 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); | |
c113ea1c | 138 | err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); |
a2e73f56 AD |
139 | if (err) |
140 | goto out; | |
c113ea1c | 141 | err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); |
a2e73f56 AD |
142 | } |
143 | out: | |
144 | if (err) { | |
145 | printk(KERN_ERR | |
146 | "cik_sdma: Failed to load firmware \"%s\"\n", | |
147 | fw_name); | |
c113ea1c AD |
148 | for (i = 0; i < adev->sdma.num_instances; i++) { |
149 | release_firmware(adev->sdma.instance[i].fw); | |
150 | adev->sdma.instance[i].fw = NULL; | |
a2e73f56 AD |
151 | } |
152 | } | |
153 | return err; | |
154 | } | |
155 | ||
156 | /** | |
157 | * cik_sdma_ring_get_rptr - get the current read pointer | |
158 | * | |
159 | * @ring: amdgpu ring pointer | |
160 | * | |
161 | * Get the current rptr from the hardware (CIK+). | |
162 | */ | |
163 | static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) | |
164 | { | |
165 | u32 rptr; | |
166 | ||
167 | rptr = ring->adev->wb.wb[ring->rptr_offs]; | |
168 | ||
169 | return (rptr & 0x3fffc) >> 2; | |
170 | } | |
171 | ||
172 | /** | |
173 | * cik_sdma_ring_get_wptr - get the current write pointer | |
174 | * | |
175 | * @ring: amdgpu ring pointer | |
176 | * | |
177 | * Get the current wptr from the hardware (CIK+). | |
178 | */ | |
179 | static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) | |
180 | { | |
181 | struct amdgpu_device *adev = ring->adev; | |
c113ea1c | 182 | u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; |
a2e73f56 AD |
183 | |
184 | return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; | |
185 | } | |
186 | ||
187 | /** | |
188 | * cik_sdma_ring_set_wptr - commit the write pointer | |
189 | * | |
190 | * @ring: amdgpu ring pointer | |
191 | * | |
192 | * Write the wptr back to the hardware (CIK+). | |
193 | */ | |
194 | static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) | |
195 | { | |
196 | struct amdgpu_device *adev = ring->adev; | |
c113ea1c | 197 | u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; |
a2e73f56 AD |
198 | |
199 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); | |
200 | } | |
201 | ||
ac01db3d JZ |
202 | static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
203 | { | |
c113ea1c | 204 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
205 | int i; |
206 | ||
207 | for (i = 0; i < count; i++) | |
208 | if (sdma && sdma->burst_nop && (i == 0)) | |
209 | amdgpu_ring_write(ring, ring->nop | | |
210 | SDMA_NOP_COUNT(count - 1)); | |
211 | else | |
212 | amdgpu_ring_write(ring, ring->nop); | |
213 | } | |
214 | ||
a2e73f56 AD |
215 | /** |
216 | * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine | |
217 | * | |
218 | * @ring: amdgpu ring pointer | |
219 | * @ib: IB object to schedule | |
220 | * | |
221 | * Schedule an IB in the DMA ring (CIK). | |
222 | */ | |
223 | static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, | |
d88bf583 CK |
224 | struct amdgpu_ib *ib, |
225 | unsigned vm_id, bool ctx_switch) | |
a2e73f56 | 226 | { |
d88bf583 | 227 | u32 extra_bits = vm_id & 0xf; |
a2e73f56 | 228 | |
a2e73f56 | 229 | /* IB packet must end on a 8 DW boundary */ |
ac01db3d JZ |
230 | cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8); |
231 | ||
a2e73f56 AD |
232 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); |
233 | amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ | |
234 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); | |
235 | amdgpu_ring_write(ring, ib->length_dw); | |
236 | ||
237 | } | |
238 | ||
239 | /** | |
d2edb07b | 240 | * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
a2e73f56 AD |
241 | * |
242 | * @ring: amdgpu ring pointer | |
243 | * | |
244 | * Emit an hdp flush packet on the requested DMA ring. | |
245 | */ | |
d2edb07b | 246 | static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
a2e73f56 AD |
247 | { |
248 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | | |
249 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ | |
250 | u32 ref_and_mask; | |
251 | ||
c113ea1c | 252 | if (ring == &ring->adev->sdma.instance[0].ring) |
a2e73f56 AD |
253 | ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; |
254 | else | |
255 | ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; | |
256 | ||
257 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
258 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); | |
259 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); | |
260 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ | |
261 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ | |
262 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
263 | } | |
264 | ||
498dd97d CZ |
265 | static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) |
266 | { | |
267 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
268 | amdgpu_ring_write(ring, mmHDP_DEBUG0); | |
269 | amdgpu_ring_write(ring, 1); | |
270 | } | |
271 | ||
a2e73f56 AD |
272 | /** |
273 | * cik_sdma_ring_emit_fence - emit a fence on the DMA ring | |
274 | * | |
275 | * @ring: amdgpu ring pointer | |
276 | * @fence: amdgpu fence object | |
277 | * | |
278 | * Add a DMA fence packet to the ring to write | |
279 | * the fence seq number and DMA trap packet to generate | |
280 | * an interrupt if needed (CIK). | |
281 | */ | |
282 | static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
890ee23f | 283 | unsigned flags) |
a2e73f56 | 284 | { |
890ee23f | 285 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
a2e73f56 AD |
286 | /* write the fence */ |
287 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); | |
288 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
289 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
290 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
291 | ||
292 | /* optionally write high bits as well */ | |
293 | if (write64bit) { | |
294 | addr += 4; | |
295 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); | |
296 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
297 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
298 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
299 | } | |
300 | ||
301 | /* generate an interrupt */ | |
302 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); | |
303 | } | |
304 | ||
a2e73f56 AD |
305 | /** |
306 | * cik_sdma_gfx_stop - stop the gfx async dma engines | |
307 | * | |
308 | * @adev: amdgpu_device pointer | |
309 | * | |
310 | * Stop the gfx async dma ring buffers (CIK). | |
311 | */ | |
312 | static void cik_sdma_gfx_stop(struct amdgpu_device *adev) | |
313 | { | |
c113ea1c AD |
314 | struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; |
315 | struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; | |
a2e73f56 AD |
316 | u32 rb_cntl; |
317 | int i; | |
318 | ||
319 | if ((adev->mman.buffer_funcs_ring == sdma0) || | |
320 | (adev->mman.buffer_funcs_ring == sdma1)) | |
321 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); | |
322 | ||
c113ea1c | 323 | for (i = 0; i < adev->sdma.num_instances; i++) { |
a2e73f56 AD |
324 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); |
325 | rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; | |
326 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
327 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); | |
328 | } | |
329 | sdma0->ready = false; | |
330 | sdma1->ready = false; | |
331 | } | |
332 | ||
333 | /** | |
334 | * cik_sdma_rlc_stop - stop the compute async dma engines | |
335 | * | |
336 | * @adev: amdgpu_device pointer | |
337 | * | |
338 | * Stop the compute async dma queues (CIK). | |
339 | */ | |
340 | static void cik_sdma_rlc_stop(struct amdgpu_device *adev) | |
341 | { | |
342 | /* XXX todo */ | |
343 | } | |
344 | ||
345 | /** | |
346 | * cik_sdma_enable - stop the async dma engines | |
347 | * | |
348 | * @adev: amdgpu_device pointer | |
349 | * @enable: enable/disable the DMA MEs. | |
350 | * | |
351 | * Halt or unhalt the async dma engines (CIK). | |
352 | */ | |
353 | static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) | |
354 | { | |
355 | u32 me_cntl; | |
356 | int i; | |
357 | ||
004e29cc | 358 | if (!enable) { |
a2e73f56 AD |
359 | cik_sdma_gfx_stop(adev); |
360 | cik_sdma_rlc_stop(adev); | |
361 | } | |
362 | ||
c113ea1c | 363 | for (i = 0; i < adev->sdma.num_instances; i++) { |
a2e73f56 AD |
364 | me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); |
365 | if (enable) | |
366 | me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; | |
367 | else | |
368 | me_cntl |= SDMA0_F32_CNTL__HALT_MASK; | |
369 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); | |
370 | } | |
371 | } | |
372 | ||
373 | /** | |
374 | * cik_sdma_gfx_resume - setup and start the async dma engines | |
375 | * | |
376 | * @adev: amdgpu_device pointer | |
377 | * | |
378 | * Set up the gfx DMA ring buffers and enable them (CIK). | |
379 | * Returns 0 for success, error for failure. | |
380 | */ | |
381 | static int cik_sdma_gfx_resume(struct amdgpu_device *adev) | |
382 | { | |
383 | struct amdgpu_ring *ring; | |
384 | u32 rb_cntl, ib_cntl; | |
385 | u32 rb_bufsz; | |
386 | u32 wb_offset; | |
387 | int i, j, r; | |
388 | ||
c113ea1c AD |
389 | for (i = 0; i < adev->sdma.num_instances; i++) { |
390 | ring = &adev->sdma.instance[i].ring; | |
a2e73f56 AD |
391 | wb_offset = (ring->rptr_offs * 4); |
392 | ||
393 | mutex_lock(&adev->srbm_mutex); | |
394 | for (j = 0; j < 16; j++) { | |
395 | cik_srbm_select(adev, 0, 0, 0, j); | |
396 | /* SDMA GFX */ | |
397 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); | |
398 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); | |
399 | /* XXX SDMA RLC - todo */ | |
400 | } | |
401 | cik_srbm_select(adev, 0, 0, 0, 0); | |
402 | mutex_unlock(&adev->srbm_mutex); | |
403 | ||
2b3a765d AD |
404 | WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], |
405 | adev->gfx.config.gb_addr_config & 0x70); | |
406 | ||
a2e73f56 AD |
407 | WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); |
408 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); | |
409 | ||
410 | /* Set ring buffer size in dwords */ | |
411 | rb_bufsz = order_base_2(ring->ring_size / 4); | |
412 | rb_cntl = rb_bufsz << 1; | |
413 | #ifdef __BIG_ENDIAN | |
454fc95e AD |
414 | rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | |
415 | SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; | |
a2e73f56 AD |
416 | #endif |
417 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
418 | ||
419 | /* Initialize the ring buffer's read and write pointers */ | |
420 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); | |
421 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); | |
d72f7c06 ML |
422 | WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); |
423 | WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); | |
a2e73f56 AD |
424 | |
425 | /* set the wb address whether it's enabled or not */ | |
426 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], | |
427 | upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); | |
428 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], | |
429 | ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); | |
430 | ||
431 | rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; | |
432 | ||
433 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); | |
434 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); | |
435 | ||
436 | ring->wptr = 0; | |
437 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); | |
438 | ||
439 | /* enable DMA RB */ | |
440 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], | |
441 | rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); | |
442 | ||
443 | ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; | |
444 | #ifdef __BIG_ENDIAN | |
445 | ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; | |
446 | #endif | |
447 | /* enable DMA IBs */ | |
448 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
449 | ||
450 | ring->ready = true; | |
505dfe76 ML |
451 | } |
452 | ||
453 | cik_sdma_enable(adev, true); | |
a2e73f56 | 454 | |
505dfe76 ML |
455 | for (i = 0; i < adev->sdma.num_instances; i++) { |
456 | ring = &adev->sdma.instance[i].ring; | |
a2e73f56 AD |
457 | r = amdgpu_ring_test_ring(ring); |
458 | if (r) { | |
459 | ring->ready = false; | |
460 | return r; | |
461 | } | |
462 | ||
463 | if (adev->mman.buffer_funcs_ring == ring) | |
464 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); | |
465 | } | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
470 | /** | |
471 | * cik_sdma_rlc_resume - setup and start the async dma engines | |
472 | * | |
473 | * @adev: amdgpu_device pointer | |
474 | * | |
475 | * Set up the compute DMA queues and enable them (CIK). | |
476 | * Returns 0 for success, error for failure. | |
477 | */ | |
478 | static int cik_sdma_rlc_resume(struct amdgpu_device *adev) | |
479 | { | |
480 | /* XXX todo */ | |
481 | return 0; | |
482 | } | |
483 | ||
484 | /** | |
485 | * cik_sdma_load_microcode - load the sDMA ME ucode | |
486 | * | |
487 | * @adev: amdgpu_device pointer | |
488 | * | |
489 | * Loads the sDMA0/1 ucode. | |
490 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
491 | */ | |
492 | static int cik_sdma_load_microcode(struct amdgpu_device *adev) | |
493 | { | |
494 | const struct sdma_firmware_header_v1_0 *hdr; | |
495 | const __le32 *fw_data; | |
496 | u32 fw_size; | |
497 | int i, j; | |
498 | ||
a2e73f56 AD |
499 | /* halt the MEs */ |
500 | cik_sdma_enable(adev, false); | |
501 | ||
c113ea1c AD |
502 | for (i = 0; i < adev->sdma.num_instances; i++) { |
503 | if (!adev->sdma.instance[i].fw) | |
504 | return -EINVAL; | |
505 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; | |
a2e73f56 AD |
506 | amdgpu_ucode_print_sdma_hdr(&hdr->header); |
507 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
c113ea1c AD |
508 | adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); |
509 | adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
510 | if (adev->sdma.instance[i].feature_version >= 20) | |
511 | adev->sdma.instance[i].burst_nop = true; | |
a2e73f56 | 512 | fw_data = (const __le32 *) |
c113ea1c | 513 | (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
a2e73f56 AD |
514 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); |
515 | for (j = 0; j < fw_size; j++) | |
516 | WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); | |
c113ea1c | 517 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); |
a2e73f56 AD |
518 | } |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
523 | /** | |
524 | * cik_sdma_start - setup and start the async dma engines | |
525 | * | |
526 | * @adev: amdgpu_device pointer | |
527 | * | |
528 | * Set up the DMA engines and enable them (CIK). | |
529 | * Returns 0 for success, error for failure. | |
530 | */ | |
531 | static int cik_sdma_start(struct amdgpu_device *adev) | |
532 | { | |
533 | int r; | |
534 | ||
535 | r = cik_sdma_load_microcode(adev); | |
536 | if (r) | |
537 | return r; | |
538 | ||
505dfe76 ML |
539 | /* halt the engine before programing */ |
540 | cik_sdma_enable(adev, false); | |
a2e73f56 AD |
541 | |
542 | /* start the gfx rings and rlc compute queues */ | |
543 | r = cik_sdma_gfx_resume(adev); | |
544 | if (r) | |
545 | return r; | |
546 | r = cik_sdma_rlc_resume(adev); | |
547 | if (r) | |
548 | return r; | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
553 | /** | |
554 | * cik_sdma_ring_test_ring - simple async dma engine test | |
555 | * | |
556 | * @ring: amdgpu_ring structure holding ring information | |
557 | * | |
558 | * Test the DMA engine by writing using it to write an | |
559 | * value to memory. (CIK). | |
560 | * Returns 0 for success, error for failure. | |
561 | */ | |
562 | static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) | |
563 | { | |
564 | struct amdgpu_device *adev = ring->adev; | |
565 | unsigned i; | |
566 | unsigned index; | |
567 | int r; | |
568 | u32 tmp; | |
569 | u64 gpu_addr; | |
570 | ||
571 | r = amdgpu_wb_get(adev, &index); | |
572 | if (r) { | |
573 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
574 | return r; | |
575 | } | |
576 | ||
577 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
578 | tmp = 0xCAFEDEAD; | |
579 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
580 | ||
a27de35c | 581 | r = amdgpu_ring_alloc(ring, 5); |
a2e73f56 AD |
582 | if (r) { |
583 | DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); | |
584 | amdgpu_wb_free(adev, index); | |
585 | return r; | |
586 | } | |
587 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); | |
588 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); | |
589 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); | |
590 | amdgpu_ring_write(ring, 1); /* number of DWs to follow */ | |
591 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
a27de35c | 592 | amdgpu_ring_commit(ring); |
a2e73f56 AD |
593 | |
594 | for (i = 0; i < adev->usec_timeout; i++) { | |
595 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
596 | if (tmp == 0xDEADBEEF) | |
597 | break; | |
598 | DRM_UDELAY(1); | |
599 | } | |
600 | ||
601 | if (i < adev->usec_timeout) { | |
602 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); | |
603 | } else { | |
604 | DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", | |
605 | ring->idx, tmp); | |
606 | r = -EINVAL; | |
607 | } | |
608 | amdgpu_wb_free(adev, index); | |
609 | ||
610 | return r; | |
611 | } | |
612 | ||
613 | /** | |
614 | * cik_sdma_ring_test_ib - test an IB on the DMA engine | |
615 | * | |
616 | * @ring: amdgpu_ring structure holding ring information | |
617 | * | |
618 | * Test a simple IB in the DMA ring (CIK). | |
619 | * Returns 0 on success, error on failure. | |
620 | */ | |
bbec97aa | 621 | static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
a2e73f56 AD |
622 | { |
623 | struct amdgpu_device *adev = ring->adev; | |
624 | struct amdgpu_ib ib; | |
f54d1867 | 625 | struct dma_fence *f = NULL; |
a2e73f56 | 626 | unsigned index; |
a2e73f56 AD |
627 | u32 tmp = 0; |
628 | u64 gpu_addr; | |
bbec97aa | 629 | long r; |
a2e73f56 AD |
630 | |
631 | r = amdgpu_wb_get(adev, &index); | |
632 | if (r) { | |
bbec97aa | 633 | dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); |
a2e73f56 AD |
634 | return r; |
635 | } | |
636 | ||
637 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
638 | tmp = 0xCAFEDEAD; | |
639 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
b203dd95 | 640 | memset(&ib, 0, sizeof(ib)); |
b07c60c0 | 641 | r = amdgpu_ib_get(adev, NULL, 256, &ib); |
a2e73f56 | 642 | if (r) { |
bbec97aa | 643 | DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); |
0011fdaa | 644 | goto err0; |
a2e73f56 AD |
645 | } |
646 | ||
6d44565d CK |
647 | ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, |
648 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
a2e73f56 AD |
649 | ib.ptr[1] = lower_32_bits(gpu_addr); |
650 | ib.ptr[2] = upper_32_bits(gpu_addr); | |
651 | ib.ptr[3] = 1; | |
652 | ib.ptr[4] = 0xDEADBEEF; | |
653 | ib.length_dw = 5; | |
c5637837 | 654 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); |
0011fdaa CZ |
655 | if (r) |
656 | goto err1; | |
a2e73f56 | 657 | |
f54d1867 | 658 | r = dma_fence_wait_timeout(f, false, timeout); |
bbec97aa CK |
659 | if (r == 0) { |
660 | DRM_ERROR("amdgpu: IB test timed out\n"); | |
661 | r = -ETIMEDOUT; | |
662 | goto err1; | |
663 | } else if (r < 0) { | |
664 | DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); | |
0011fdaa | 665 | goto err1; |
a2e73f56 | 666 | } |
6d44565d CK |
667 | tmp = le32_to_cpu(adev->wb.wb[index]); |
668 | if (tmp == 0xDEADBEEF) { | |
669 | DRM_INFO("ib test on ring %d succeeded\n", ring->idx); | |
bbec97aa | 670 | r = 0; |
a2e73f56 AD |
671 | } else { |
672 | DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); | |
673 | r = -EINVAL; | |
674 | } | |
0011fdaa CZ |
675 | |
676 | err1: | |
cc55c45d | 677 | amdgpu_ib_free(adev, &ib, NULL); |
f54d1867 | 678 | dma_fence_put(f); |
0011fdaa | 679 | err0: |
a2e73f56 AD |
680 | amdgpu_wb_free(adev, index); |
681 | return r; | |
682 | } | |
683 | ||
684 | /** | |
685 | * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART | |
686 | * | |
687 | * @ib: indirect buffer to fill with commands | |
688 | * @pe: addr of the page entry | |
689 | * @src: src addr to copy from | |
690 | * @count: number of page entries to update | |
691 | * | |
692 | * Update PTEs by copying them from the GART using sDMA (CIK). | |
693 | */ | |
694 | static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, | |
695 | uint64_t pe, uint64_t src, | |
696 | unsigned count) | |
697 | { | |
96105e53 CK |
698 | unsigned bytes = count * 8; |
699 | ||
700 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, | |
701 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
702 | ib->ptr[ib->length_dw++] = bytes; | |
703 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
704 | ib->ptr[ib->length_dw++] = lower_32_bits(src); | |
705 | ib->ptr[ib->length_dw++] = upper_32_bits(src); | |
706 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
707 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
a2e73f56 AD |
708 | } |
709 | ||
710 | /** | |
711 | * cik_sdma_vm_write_pages - update PTEs by writing them manually | |
712 | * | |
713 | * @ib: indirect buffer to fill with commands | |
714 | * @pe: addr of the page entry | |
de9ea7bd | 715 | * @value: dst addr to write into pe |
a2e73f56 AD |
716 | * @count: number of page entries to update |
717 | * @incr: increase next addr by incr bytes | |
a2e73f56 AD |
718 | * |
719 | * Update PTEs by writing them manually using sDMA (CIK). | |
720 | */ | |
de9ea7bd CK |
721 | static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, |
722 | uint64_t value, unsigned count, | |
723 | uint32_t incr) | |
a2e73f56 | 724 | { |
de9ea7bd CK |
725 | unsigned ndw = count * 2; |
726 | ||
727 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, | |
728 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); | |
729 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
730 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
731 | ib->ptr[ib->length_dw++] = ndw; | |
732 | for (; ndw > 0; ndw -= 2) { | |
733 | ib->ptr[ib->length_dw++] = lower_32_bits(value); | |
734 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
735 | value += incr; | |
a2e73f56 AD |
736 | } |
737 | } | |
738 | ||
739 | /** | |
740 | * cik_sdma_vm_set_pages - update the page tables using sDMA | |
741 | * | |
742 | * @ib: indirect buffer to fill with commands | |
743 | * @pe: addr of the page entry | |
744 | * @addr: dst addr to write into pe | |
745 | * @count: number of page entries to update | |
746 | * @incr: increase next addr by incr bytes | |
747 | * @flags: access flags | |
748 | * | |
749 | * Update the page tables using sDMA (CIK). | |
750 | */ | |
96105e53 | 751 | static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, |
a2e73f56 AD |
752 | uint64_t addr, unsigned count, |
753 | uint32_t incr, uint32_t flags) | |
754 | { | |
96105e53 CK |
755 | /* for physically contiguous pages (vram) */ |
756 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); | |
757 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ | |
758 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
759 | ib->ptr[ib->length_dw++] = flags; /* mask */ | |
760 | ib->ptr[ib->length_dw++] = 0; | |
761 | ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ | |
762 | ib->ptr[ib->length_dw++] = upper_32_bits(addr); | |
763 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
764 | ib->ptr[ib->length_dw++] = 0; | |
765 | ib->ptr[ib->length_dw++] = count; /* number of entries */ | |
a2e73f56 AD |
766 | } |
767 | ||
768 | /** | |
769 | * cik_sdma_vm_pad_ib - pad the IB to the required number of dw | |
770 | * | |
771 | * @ib: indirect buffer to fill with padding | |
772 | * | |
773 | */ | |
9e5d5309 | 774 | static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) |
a2e73f56 | 775 | { |
9e5d5309 | 776 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
777 | u32 pad_count; |
778 | int i; | |
779 | ||
780 | pad_count = (8 - (ib->length_dw & 0x7)) % 8; | |
781 | for (i = 0; i < pad_count; i++) | |
782 | if (sdma && sdma->burst_nop && (i == 0)) | |
783 | ib->ptr[ib->length_dw++] = | |
784 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | | |
785 | SDMA_NOP_COUNT(pad_count - 1); | |
786 | else | |
787 | ib->ptr[ib->length_dw++] = | |
788 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); | |
a2e73f56 AD |
789 | } |
790 | ||
791 | /** | |
00b7c4ff | 792 | * cik_sdma_ring_emit_pipeline_sync - sync the pipeline |
a2e73f56 AD |
793 | * |
794 | * @ring: amdgpu_ring pointer | |
a2e73f56 | 795 | * |
00b7c4ff | 796 | * Make sure all previous operations are completed (CIK). |
a2e73f56 | 797 | */ |
00b7c4ff | 798 | static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |
a2e73f56 | 799 | { |
5c55db83 CZ |
800 | uint32_t seq = ring->fence_drv.sync_seq; |
801 | uint64_t addr = ring->fence_drv.gpu_addr; | |
802 | ||
803 | /* wait for idle */ | |
804 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, | |
805 | SDMA_POLL_REG_MEM_EXTRA_OP(0) | | |
806 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */ | |
807 | SDMA_POLL_REG_MEM_EXTRA_M)); | |
808 | amdgpu_ring_write(ring, addr & 0xfffffffc); | |
809 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); | |
810 | amdgpu_ring_write(ring, seq); /* reference */ | |
811 | amdgpu_ring_write(ring, 0xfffffff); /* mask */ | |
812 | amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */ | |
00b7c4ff | 813 | } |
5c55db83 | 814 | |
a2e73f56 AD |
815 | /** |
816 | * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA | |
817 | * | |
818 | * @ring: amdgpu_ring pointer | |
819 | * @vm: amdgpu_vm pointer | |
820 | * | |
821 | * Update the page table base and flush the VM TLB | |
822 | * using sDMA (CIK). | |
823 | */ | |
824 | static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
825 | unsigned vm_id, uint64_t pd_addr) | |
826 | { | |
827 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | | |
828 | SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ | |
829 | ||
830 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
831 | if (vm_id < 8) { | |
832 | amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); | |
833 | } else { | |
834 | amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); | |
835 | } | |
836 | amdgpu_ring_write(ring, pd_addr >> 12); | |
837 | ||
a2e73f56 AD |
838 | /* flush TLB */ |
839 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | |
840 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); | |
841 | amdgpu_ring_write(ring, 1 << vm_id); | |
842 | ||
843 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); | |
844 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); | |
845 | amdgpu_ring_write(ring, 0); | |
846 | amdgpu_ring_write(ring, 0); /* reference */ | |
847 | amdgpu_ring_write(ring, 0); /* mask */ | |
848 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ | |
849 | } | |
850 | ||
77b52a5b AD |
851 | static unsigned cik_sdma_ring_get_emit_ib_size(struct amdgpu_ring *ring) |
852 | { | |
853 | return | |
854 | 7 + 4; /* cik_sdma_ring_emit_ib */ | |
855 | } | |
856 | ||
857 | static unsigned cik_sdma_ring_get_dma_frame_size(struct amdgpu_ring *ring) | |
858 | { | |
859 | return | |
860 | 6 + /* cik_sdma_ring_emit_hdp_flush */ | |
861 | 3 + /* cik_sdma_ring_emit_hdp_invalidate */ | |
862 | 6 + /* cik_sdma_ring_emit_pipeline_sync */ | |
863 | 12 + /* cik_sdma_ring_emit_vm_flush */ | |
864 | 9 + 9 + 9; /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ | |
865 | } | |
866 | ||
a2e73f56 AD |
867 | static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, |
868 | bool enable) | |
869 | { | |
870 | u32 orig, data; | |
871 | ||
e3b04bc7 | 872 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { |
a2e73f56 AD |
873 | WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); |
874 | WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); | |
875 | } else { | |
876 | orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); | |
877 | data |= 0xff000000; | |
878 | if (data != orig) | |
879 | WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); | |
880 | ||
881 | orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); | |
882 | data |= 0xff000000; | |
883 | if (data != orig) | |
884 | WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); | |
885 | } | |
886 | } | |
887 | ||
888 | static void cik_enable_sdma_mgls(struct amdgpu_device *adev, | |
889 | bool enable) | |
890 | { | |
891 | u32 orig, data; | |
892 | ||
e3b04bc7 | 893 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { |
a2e73f56 AD |
894 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); |
895 | data |= 0x100; | |
896 | if (orig != data) | |
897 | WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); | |
898 | ||
899 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); | |
900 | data |= 0x100; | |
901 | if (orig != data) | |
902 | WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); | |
903 | } else { | |
904 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); | |
905 | data &= ~0x100; | |
906 | if (orig != data) | |
907 | WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); | |
908 | ||
909 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); | |
910 | data &= ~0x100; | |
911 | if (orig != data) | |
912 | WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); | |
913 | } | |
914 | } | |
915 | ||
5fc3aeeb | 916 | static int cik_sdma_early_init(void *handle) |
a2e73f56 | 917 | { |
5fc3aeeb | 918 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
919 | ||
c113ea1c AD |
920 | adev->sdma.num_instances = SDMA_MAX_INSTANCE; |
921 | ||
a2e73f56 AD |
922 | cik_sdma_set_ring_funcs(adev); |
923 | cik_sdma_set_irq_funcs(adev); | |
924 | cik_sdma_set_buffer_funcs(adev); | |
925 | cik_sdma_set_vm_pte_funcs(adev); | |
926 | ||
927 | return 0; | |
928 | } | |
929 | ||
5fc3aeeb | 930 | static int cik_sdma_sw_init(void *handle) |
a2e73f56 AD |
931 | { |
932 | struct amdgpu_ring *ring; | |
5fc3aeeb | 933 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c113ea1c | 934 | int r, i; |
a2e73f56 AD |
935 | |
936 | r = cik_sdma_init_microcode(adev); | |
937 | if (r) { | |
938 | DRM_ERROR("Failed to load sdma firmware!\n"); | |
939 | return r; | |
940 | } | |
941 | ||
942 | /* SDMA trap event */ | |
c113ea1c | 943 | r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); |
a2e73f56 AD |
944 | if (r) |
945 | return r; | |
946 | ||
947 | /* SDMA Privileged inst */ | |
c113ea1c | 948 | r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); |
a2e73f56 AD |
949 | if (r) |
950 | return r; | |
951 | ||
952 | /* SDMA Privileged inst */ | |
c113ea1c | 953 | r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); |
a2e73f56 AD |
954 | if (r) |
955 | return r; | |
956 | ||
c113ea1c AD |
957 | for (i = 0; i < adev->sdma.num_instances; i++) { |
958 | ring = &adev->sdma.instance[i].ring; | |
959 | ring->ring_obj = NULL; | |
960 | sprintf(ring->name, "sdma%d", i); | |
b38d99c4 | 961 | r = amdgpu_ring_init(adev, ring, 1024, |
c113ea1c AD |
962 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, |
963 | &adev->sdma.trap_irq, | |
964 | (i == 0) ? | |
965 | AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, | |
966 | AMDGPU_RING_TYPE_SDMA); | |
967 | if (r) | |
968 | return r; | |
969 | } | |
a2e73f56 AD |
970 | |
971 | return r; | |
972 | } | |
973 | ||
5fc3aeeb | 974 | static int cik_sdma_sw_fini(void *handle) |
a2e73f56 | 975 | { |
5fc3aeeb | 976 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c113ea1c | 977 | int i; |
5fc3aeeb | 978 | |
c113ea1c AD |
979 | for (i = 0; i < adev->sdma.num_instances; i++) |
980 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); | |
a2e73f56 | 981 | |
d1ff53b7 | 982 | cik_sdma_free_microcode(adev); |
a2e73f56 AD |
983 | return 0; |
984 | } | |
985 | ||
5fc3aeeb | 986 | static int cik_sdma_hw_init(void *handle) |
a2e73f56 AD |
987 | { |
988 | int r; | |
5fc3aeeb | 989 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
990 | |
991 | r = cik_sdma_start(adev); | |
992 | if (r) | |
993 | return r; | |
994 | ||
995 | return r; | |
996 | } | |
997 | ||
5fc3aeeb | 998 | static int cik_sdma_hw_fini(void *handle) |
a2e73f56 | 999 | { |
5fc3aeeb | 1000 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1001 | ||
a2e73f56 AD |
1002 | cik_sdma_enable(adev, false); |
1003 | ||
1004 | return 0; | |
1005 | } | |
1006 | ||
5fc3aeeb | 1007 | static int cik_sdma_suspend(void *handle) |
a2e73f56 | 1008 | { |
5fc3aeeb | 1009 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1010 | |
1011 | return cik_sdma_hw_fini(adev); | |
1012 | } | |
1013 | ||
5fc3aeeb | 1014 | static int cik_sdma_resume(void *handle) |
a2e73f56 | 1015 | { |
5fc3aeeb | 1016 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 | 1017 | |
10ea9434 | 1018 | cik_sdma_soft_reset(handle); |
1019 | ||
a2e73f56 AD |
1020 | return cik_sdma_hw_init(adev); |
1021 | } | |
1022 | ||
5fc3aeeb | 1023 | static bool cik_sdma_is_idle(void *handle) |
a2e73f56 | 1024 | { |
5fc3aeeb | 1025 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1026 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1027 | ||
1028 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1029 | SRBM_STATUS2__SDMA1_BUSY_MASK)) | |
1030 | return false; | |
1031 | ||
1032 | return true; | |
1033 | } | |
1034 | ||
5fc3aeeb | 1035 | static int cik_sdma_wait_for_idle(void *handle) |
a2e73f56 AD |
1036 | { |
1037 | unsigned i; | |
1038 | u32 tmp; | |
5fc3aeeb | 1039 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1040 | |
1041 | for (i = 0; i < adev->usec_timeout; i++) { | |
1042 | tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1043 | SRBM_STATUS2__SDMA1_BUSY_MASK); | |
1044 | ||
1045 | if (!tmp) | |
1046 | return 0; | |
1047 | udelay(1); | |
1048 | } | |
1049 | return -ETIMEDOUT; | |
1050 | } | |
1051 | ||
5fc3aeeb | 1052 | static int cik_sdma_soft_reset(void *handle) |
a2e73f56 AD |
1053 | { |
1054 | u32 srbm_soft_reset = 0; | |
5fc3aeeb | 1055 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
1056 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1057 | ||
1058 | if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { | |
1059 | /* sdma0 */ | |
1060 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); | |
1061 | tmp |= SDMA0_F32_CNTL__HALT_MASK; | |
1062 | WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); | |
1063 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; | |
1064 | } | |
1065 | if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { | |
1066 | /* sdma1 */ | |
1067 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); | |
1068 | tmp |= SDMA0_F32_CNTL__HALT_MASK; | |
1069 | WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); | |
1070 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; | |
1071 | } | |
1072 | ||
1073 | if (srbm_soft_reset) { | |
a2e73f56 AD |
1074 | tmp = RREG32(mmSRBM_SOFT_RESET); |
1075 | tmp |= srbm_soft_reset; | |
1076 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1077 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1078 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1079 | ||
1080 | udelay(50); | |
1081 | ||
1082 | tmp &= ~srbm_soft_reset; | |
1083 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1084 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1085 | ||
1086 | /* Wait a little for things to settle down */ | |
1087 | udelay(50); | |
a2e73f56 AD |
1088 | } |
1089 | ||
1090 | return 0; | |
1091 | } | |
1092 | ||
1093 | static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, | |
1094 | struct amdgpu_irq_src *src, | |
1095 | unsigned type, | |
1096 | enum amdgpu_interrupt_state state) | |
1097 | { | |
1098 | u32 sdma_cntl; | |
1099 | ||
1100 | switch (type) { | |
1101 | case AMDGPU_SDMA_IRQ_TRAP0: | |
1102 | switch (state) { | |
1103 | case AMDGPU_IRQ_STATE_DISABLE: | |
1104 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1105 | sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1106 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1107 | break; | |
1108 | case AMDGPU_IRQ_STATE_ENABLE: | |
1109 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1110 | sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1111 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1112 | break; | |
1113 | default: | |
1114 | break; | |
1115 | } | |
1116 | break; | |
1117 | case AMDGPU_SDMA_IRQ_TRAP1: | |
1118 | switch (state) { | |
1119 | case AMDGPU_IRQ_STATE_DISABLE: | |
1120 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1121 | sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1122 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1123 | break; | |
1124 | case AMDGPU_IRQ_STATE_ENABLE: | |
1125 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1126 | sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; | |
1127 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1128 | break; | |
1129 | default: | |
1130 | break; | |
1131 | } | |
1132 | break; | |
1133 | default: | |
1134 | break; | |
1135 | } | |
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, | |
1140 | struct amdgpu_irq_src *source, | |
1141 | struct amdgpu_iv_entry *entry) | |
1142 | { | |
1143 | u8 instance_id, queue_id; | |
1144 | ||
1145 | instance_id = (entry->ring_id & 0x3) >> 0; | |
1146 | queue_id = (entry->ring_id & 0xc) >> 2; | |
1147 | DRM_DEBUG("IH: SDMA trap\n"); | |
1148 | switch (instance_id) { | |
1149 | case 0: | |
1150 | switch (queue_id) { | |
1151 | case 0: | |
c113ea1c | 1152 | amdgpu_fence_process(&adev->sdma.instance[0].ring); |
a2e73f56 AD |
1153 | break; |
1154 | case 1: | |
1155 | /* XXX compute */ | |
1156 | break; | |
1157 | case 2: | |
1158 | /* XXX compute */ | |
1159 | break; | |
1160 | } | |
1161 | break; | |
1162 | case 1: | |
1163 | switch (queue_id) { | |
1164 | case 0: | |
c113ea1c | 1165 | amdgpu_fence_process(&adev->sdma.instance[1].ring); |
a2e73f56 AD |
1166 | break; |
1167 | case 1: | |
1168 | /* XXX compute */ | |
1169 | break; | |
1170 | case 2: | |
1171 | /* XXX compute */ | |
1172 | break; | |
1173 | } | |
1174 | break; | |
1175 | } | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
1180 | static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, | |
1181 | struct amdgpu_irq_src *source, | |
1182 | struct amdgpu_iv_entry *entry) | |
1183 | { | |
1184 | DRM_ERROR("Illegal instruction in SDMA command stream\n"); | |
1185 | schedule_work(&adev->reset_work); | |
1186 | return 0; | |
1187 | } | |
1188 | ||
5fc3aeeb | 1189 | static int cik_sdma_set_clockgating_state(void *handle, |
1190 | enum amd_clockgating_state state) | |
a2e73f56 AD |
1191 | { |
1192 | bool gate = false; | |
5fc3aeeb | 1193 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 | 1194 | |
5fc3aeeb | 1195 | if (state == AMD_CG_STATE_GATE) |
a2e73f56 AD |
1196 | gate = true; |
1197 | ||
1198 | cik_enable_sdma_mgcg(adev, gate); | |
1199 | cik_enable_sdma_mgls(adev, gate); | |
1200 | ||
1201 | return 0; | |
1202 | } | |
1203 | ||
5fc3aeeb | 1204 | static int cik_sdma_set_powergating_state(void *handle, |
1205 | enum amd_powergating_state state) | |
a2e73f56 AD |
1206 | { |
1207 | return 0; | |
1208 | } | |
1209 | ||
5fc3aeeb | 1210 | const struct amd_ip_funcs cik_sdma_ip_funcs = { |
88a907d6 | 1211 | .name = "cik_sdma", |
a2e73f56 AD |
1212 | .early_init = cik_sdma_early_init, |
1213 | .late_init = NULL, | |
1214 | .sw_init = cik_sdma_sw_init, | |
1215 | .sw_fini = cik_sdma_sw_fini, | |
1216 | .hw_init = cik_sdma_hw_init, | |
1217 | .hw_fini = cik_sdma_hw_fini, | |
1218 | .suspend = cik_sdma_suspend, | |
1219 | .resume = cik_sdma_resume, | |
1220 | .is_idle = cik_sdma_is_idle, | |
1221 | .wait_for_idle = cik_sdma_wait_for_idle, | |
1222 | .soft_reset = cik_sdma_soft_reset, | |
a2e73f56 AD |
1223 | .set_clockgating_state = cik_sdma_set_clockgating_state, |
1224 | .set_powergating_state = cik_sdma_set_powergating_state, | |
1225 | }; | |
1226 | ||
a2e73f56 AD |
1227 | static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { |
1228 | .get_rptr = cik_sdma_ring_get_rptr, | |
1229 | .get_wptr = cik_sdma_ring_get_wptr, | |
1230 | .set_wptr = cik_sdma_ring_set_wptr, | |
1231 | .parse_cs = NULL, | |
1232 | .emit_ib = cik_sdma_ring_emit_ib, | |
1233 | .emit_fence = cik_sdma_ring_emit_fence, | |
00b7c4ff | 1234 | .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, |
a2e73f56 | 1235 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, |
d2edb07b | 1236 | .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, |
498dd97d | 1237 | .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate, |
a2e73f56 AD |
1238 | .test_ring = cik_sdma_ring_test_ring, |
1239 | .test_ib = cik_sdma_ring_test_ib, | |
ac01db3d | 1240 | .insert_nop = cik_sdma_ring_insert_nop, |
9e5d5309 | 1241 | .pad_ib = cik_sdma_ring_pad_ib, |
77b52a5b AD |
1242 | .get_emit_ib_size = cik_sdma_ring_get_emit_ib_size, |
1243 | .get_dma_frame_size = cik_sdma_ring_get_dma_frame_size, | |
a2e73f56 AD |
1244 | }; |
1245 | ||
1246 | static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) | |
1247 | { | |
c113ea1c AD |
1248 | int i; |
1249 | ||
1250 | for (i = 0; i < adev->sdma.num_instances; i++) | |
1251 | adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; | |
a2e73f56 AD |
1252 | } |
1253 | ||
1254 | static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { | |
1255 | .set = cik_sdma_set_trap_irq_state, | |
1256 | .process = cik_sdma_process_trap_irq, | |
1257 | }; | |
1258 | ||
1259 | static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { | |
1260 | .process = cik_sdma_process_illegal_inst_irq, | |
1261 | }; | |
1262 | ||
1263 | static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) | |
1264 | { | |
c113ea1c AD |
1265 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; |
1266 | adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; | |
1267 | adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; | |
a2e73f56 AD |
1268 | } |
1269 | ||
1270 | /** | |
1271 | * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine | |
1272 | * | |
1273 | * @ring: amdgpu_ring structure holding ring information | |
1274 | * @src_offset: src GPU address | |
1275 | * @dst_offset: dst GPU address | |
1276 | * @byte_count: number of bytes to xfer | |
1277 | * | |
1278 | * Copy GPU buffers using the DMA engine (CIK). | |
1279 | * Used by the amdgpu ttm implementation to move pages if | |
1280 | * registered as the asic copy callback. | |
1281 | */ | |
c7ae72c0 | 1282 | static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, |
a2e73f56 AD |
1283 | uint64_t src_offset, |
1284 | uint64_t dst_offset, | |
1285 | uint32_t byte_count) | |
1286 | { | |
c7ae72c0 CZ |
1287 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); |
1288 | ib->ptr[ib->length_dw++] = byte_count; | |
1289 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
1290 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); | |
1291 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); | |
1292 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1293 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
a2e73f56 AD |
1294 | } |
1295 | ||
1296 | /** | |
1297 | * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine | |
1298 | * | |
1299 | * @ring: amdgpu_ring structure holding ring information | |
1300 | * @src_data: value to write to buffer | |
1301 | * @dst_offset: dst GPU address | |
1302 | * @byte_count: number of bytes to xfer | |
1303 | * | |
1304 | * Fill GPU buffers using the DMA engine (CIK). | |
1305 | */ | |
6e7a3840 | 1306 | static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, |
a2e73f56 AD |
1307 | uint32_t src_data, |
1308 | uint64_t dst_offset, | |
1309 | uint32_t byte_count) | |
1310 | { | |
6e7a3840 CZ |
1311 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); |
1312 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1313 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
1314 | ib->ptr[ib->length_dw++] = src_data; | |
1315 | ib->ptr[ib->length_dw++] = byte_count; | |
a2e73f56 AD |
1316 | } |
1317 | ||
1318 | static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { | |
1319 | .copy_max_bytes = 0x1fffff, | |
1320 | .copy_num_dw = 7, | |
1321 | .emit_copy_buffer = cik_sdma_emit_copy_buffer, | |
1322 | ||
1323 | .fill_max_bytes = 0x1fffff, | |
1324 | .fill_num_dw = 5, | |
1325 | .emit_fill_buffer = cik_sdma_emit_fill_buffer, | |
1326 | }; | |
1327 | ||
1328 | static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) | |
1329 | { | |
1330 | if (adev->mman.buffer_funcs == NULL) { | |
1331 | adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; | |
c113ea1c | 1332 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; |
a2e73f56 AD |
1333 | } |
1334 | } | |
1335 | ||
1336 | static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { | |
1337 | .copy_pte = cik_sdma_vm_copy_pte, | |
1338 | .write_pte = cik_sdma_vm_write_pte, | |
1339 | .set_pte_pde = cik_sdma_vm_set_pte_pde, | |
a2e73f56 AD |
1340 | }; |
1341 | ||
1342 | static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) | |
1343 | { | |
2d55e45a CK |
1344 | unsigned i; |
1345 | ||
a2e73f56 AD |
1346 | if (adev->vm_manager.vm_pte_funcs == NULL) { |
1347 | adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; | |
2d55e45a CK |
1348 | for (i = 0; i < adev->sdma.num_instances; i++) |
1349 | adev->vm_manager.vm_pte_rings[i] = | |
1350 | &adev->sdma.instance[i].ring; | |
1351 | ||
1352 | adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; | |
a2e73f56 AD |
1353 | } |
1354 | } |