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drm/amdgpu/cz: store the forced dpm level
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / cz_dpm.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/seq_file.h>
26#include "drmP.h"
27#include "amdgpu.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_atombios.h"
30#include "vid.h"
31#include "vi_dpm.h"
32#include "amdgpu_dpm.h"
33#include "cz_dpm.h"
34#include "cz_ppsmc.h"
35#include "atom.h"
36
37#include "smu/smu_8_0_d.h"
38#include "smu/smu_8_0_sh_mask.h"
39#include "gca/gfx_8_0_d.h"
40#include "gca/gfx_8_0_sh_mask.h"
41#include "gmc/gmc_8_1_d.h"
42#include "bif/bif_5_1_d.h"
43#include "gfx_v8_0.h"
44
564ea790 45static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
b7a07769 46static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
564ea790 47
aaa36a97
AD		 48static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps)
49{
50 struct cz_ps *ps = rps->ps_priv;
51
52 return ps;
53}
54
55static struct cz_power_info *cz_get_pi(struct amdgpu_device *adev)
56{
57 struct cz_power_info *pi = adev->pm.dpm.priv;
58
59 return pi;
60}
61
62static uint16_t cz_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
63 uint16_t voltage)
64{
65 uint16_t tmp = 6200 - voltage * 25;
66
67 return tmp;
68}
69
70static void cz_construct_max_power_limits_table(struct amdgpu_device *adev,
71 struct amdgpu_clock_and_voltage_limits *table)
72{
73 struct cz_power_info *pi = cz_get_pi(adev);
74 struct amdgpu_clock_voltage_dependency_table *dep_table =
75 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
76
77 if (dep_table->count > 0) {
78 table->sclk = dep_table->entries[dep_table->count - 1].clk;
79 table->vddc = cz_convert_8bit_index_to_voltage(adev,
80 dep_table->entries[dep_table->count - 1].v);
81 }
82
83 table->mclk = pi->sys_info.nbp_memory_clock[0];
84
85}
86
87union igp_info {
88 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
89 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
90 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
91 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
92};
93
94static int cz_parse_sys_info_table(struct amdgpu_device *adev)
95{
96 struct cz_power_info *pi = cz_get_pi(adev);
97 struct amdgpu_mode_info *mode_info = &adev->mode_info;
98 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
99 union igp_info *igp_info;
100 u8 frev, crev;
101 u16 data_offset;
102 int i = 0;
103
104 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
105 &frev, &crev, &data_offset)) {
106 igp_info = (union igp_info *)(mode_info->atom_context->bios +
107 data_offset);
108
109 if (crev != 9) {
110 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
111 return -EINVAL;
112 }
113 pi->sys_info.bootup_sclk =
114 le32_to_cpu(igp_info->info_9.ulBootUpEngineClock);
115 pi->sys_info.bootup_uma_clk =
116 le32_to_cpu(igp_info->info_9.ulBootUpUMAClock);
117 pi->sys_info.dentist_vco_freq =
118 le32_to_cpu(igp_info->info_9.ulDentistVCOFreq);
119 pi->sys_info.bootup_nb_voltage_index =
120 le16_to_cpu(igp_info->info_9.usBootUpNBVoltage);
121
122 if (igp_info->info_9.ucHtcTmpLmt == 0)
123 pi->sys_info.htc_tmp_lmt = 203;
124 else
125 pi->sys_info.htc_tmp_lmt = igp_info->info_9.ucHtcTmpLmt;
126
127 if (igp_info->info_9.ucHtcHystLmt == 0)
128 pi->sys_info.htc_hyst_lmt = 5;
129 else
130 pi->sys_info.htc_hyst_lmt = igp_info->info_9.ucHtcHystLmt;
131
132 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
133 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
134 return -EINVAL;
135 }
136
137 if (le32_to_cpu(igp_info->info_9.ulSystemConfig) & (1 << 3) &&
138 pi->enable_nb_ps_policy)
139 pi->sys_info.nb_dpm_enable = true;
140 else
141 pi->sys_info.nb_dpm_enable = false;
142
143 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
144 if (i < CZ_NUM_NBPMEMORY_CLOCK)
145 pi->sys_info.nbp_memory_clock[i] =
146 le32_to_cpu(igp_info->info_9.ulNbpStateMemclkFreq[i]);
147 pi->sys_info.nbp_n_clock[i] =
148 le32_to_cpu(igp_info->info_9.ulNbpStateNClkFreq[i]);
149 }
150
151 for (i = 0; i < CZ_MAX_DISPLAY_CLOCK_LEVEL; i++)
152 pi->sys_info.display_clock[i] =
153 le32_to_cpu(igp_info->info_9.sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
154
155 for (i = 0; i < CZ_NUM_NBPSTATES; i++)
156 pi->sys_info.nbp_voltage_index[i] =
157 le32_to_cpu(igp_info->info_9.usNBPStateVoltage[i]);
158
159 if (le32_to_cpu(igp_info->info_9.ulGPUCapInfo) &
160 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
161 pi->caps_enable_dfs_bypass = true;
162
163 pi->sys_info.uma_channel_number =
164 igp_info->info_9.ucUMAChannelNumber;
165
166 cz_construct_max_power_limits_table(adev,
167 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
168 }
169
170 return 0;
171}
172
173static void cz_patch_voltage_values(struct amdgpu_device *adev)
174{
175 int i;
176 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
177 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
178 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
179 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
180 struct amdgpu_clock_voltage_dependency_table *acp_table =
181 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
182
183 if (uvd_table->count) {
184 for (i = 0; i < uvd_table->count; i++)
185 uvd_table->entries[i].v =
186 cz_convert_8bit_index_to_voltage(adev,
187 uvd_table->entries[i].v);
188 }
189
190 if (vce_table->count) {
191 for (i = 0; i < vce_table->count; i++)
192 vce_table->entries[i].v =
193 cz_convert_8bit_index_to_voltage(adev,
194 vce_table->entries[i].v);
195 }
196
197 if (acp_table->count) {
198 for (i = 0; i < acp_table->count; i++)
199 acp_table->entries[i].v =
200 cz_convert_8bit_index_to_voltage(adev,
201 acp_table->entries[i].v);
202 }
203
204}
205
206static void cz_construct_boot_state(struct amdgpu_device *adev)
207{
208 struct cz_power_info *pi = cz_get_pi(adev);
209
210 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
211 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
212 pi->boot_pl.ds_divider_index = 0;
213 pi->boot_pl.ss_divider_index = 0;
214 pi->boot_pl.allow_gnb_slow = 1;
215 pi->boot_pl.force_nbp_state = 0;
216 pi->boot_pl.display_wm = 0;
217 pi->boot_pl.vce_wm = 0;
218
219}
220
221static void cz_patch_boot_state(struct amdgpu_device *adev,
222 struct cz_ps *ps)
223{
224 struct cz_power_info *pi = cz_get_pi(adev);
225
226 ps->num_levels = 1;
227 ps->levels[0] = pi->boot_pl;
228}
229
230union pplib_clock_info {
231 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
232 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
233 struct _ATOM_PPLIB_CZ_CLOCK_INFO carrizo;
234};
235
236static void cz_parse_pplib_clock_info(struct amdgpu_device *adev,
237 struct amdgpu_ps *rps, int index,
238 union pplib_clock_info *clock_info)
239{
240 struct cz_power_info *pi = cz_get_pi(adev);
241 struct cz_ps *ps = cz_get_ps(rps);
242 struct cz_pl *pl = &ps->levels[index];
243 struct amdgpu_clock_voltage_dependency_table *table =
244 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
245
246 pl->sclk = table->entries[clock_info->carrizo.index].clk;
247 pl->vddc_index = table->entries[clock_info->carrizo.index].v;
248
249 ps->num_levels = index + 1;
250
251 if (pi->caps_sclk_ds) {
252 pl->ds_divider_index = 5;
253 pl->ss_divider_index = 5;
254 }
255
256}
257
258static void cz_parse_pplib_non_clock_info(struct amdgpu_device *adev,
259 struct amdgpu_ps *rps,
260 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
261 u8 table_rev)
262{
263 struct cz_ps *ps = cz_get_ps(rps);
264
265 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
266 rps->class = le16_to_cpu(non_clock_info->usClassification);
267 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
268
269 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
270 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
271 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
272 } else {
273 rps->vclk = 0;
274 rps->dclk = 0;
275 }
276
277 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
278 adev->pm.dpm.boot_ps = rps;
279 cz_patch_boot_state(adev, ps);
280 }
281 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
282 adev->pm.dpm.uvd_ps = rps;
283
284}
285
286union power_info {
287 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
288 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
289 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
290 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
291 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
292};
293
294union pplib_power_state {
295 struct _ATOM_PPLIB_STATE v1;
296 struct _ATOM_PPLIB_STATE_V2 v2;
297};
298
299static int cz_parse_power_table(struct amdgpu_device *adev)
300{
301 struct amdgpu_mode_info *mode_info = &adev->mode_info;
302 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
303 union pplib_power_state *power_state;
304 int i, j, k, non_clock_array_index, clock_array_index;
305 union pplib_clock_info *clock_info;
306 struct _StateArray *state_array;
307 struct _ClockInfoArray *clock_info_array;
308 struct _NonClockInfoArray *non_clock_info_array;
309 union power_info *power_info;
310 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
311 u16 data_offset;
312 u8 frev, crev;
313 u8 *power_state_offset;
314 struct cz_ps *ps;
315
316 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
317 &frev, &crev, &data_offset))
318 return -EINVAL;
319 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
320
321 state_array = (struct _StateArray *)
322 (mode_info->atom_context->bios + data_offset +
323 le16_to_cpu(power_info->pplib.usStateArrayOffset));
324 clock_info_array = (struct _ClockInfoArray *)
325 (mode_info->atom_context->bios + data_offset +
326 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
327 non_clock_info_array = (struct _NonClockInfoArray *)
328 (mode_info->atom_context->bios + data_offset +
329 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
330
331 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
332 state_array->ucNumEntries, GFP_KERNEL);
333
334 if (!adev->pm.dpm.ps)
335 return -ENOMEM;
336
337 power_state_offset = (u8 *)state_array->states;
338 adev->pm.dpm.platform_caps =
339 le32_to_cpu(power_info->pplib.ulPlatformCaps);
340 adev->pm.dpm.backbias_response_time =
341 le16_to_cpu(power_info->pplib.usBackbiasTime);
342 adev->pm.dpm.voltage_response_time =
343 le16_to_cpu(power_info->pplib.usVoltageTime);
344
345 for (i = 0; i < state_array->ucNumEntries; i++) {
346 power_state = (union pplib_power_state *)power_state_offset;
347 non_clock_array_index = power_state->v2.nonClockInfoIndex;
348 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
349 &non_clock_info_array->nonClockInfo[non_clock_array_index];
350
351 ps = kzalloc(sizeof(struct cz_ps), GFP_KERNEL);
352 if (ps == NULL) {
353 kfree(adev->pm.dpm.ps);
354 return -ENOMEM;
355 }
356
357 adev->pm.dpm.ps[i].ps_priv = ps;
358 k = 0;
359 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
360 clock_array_index = power_state->v2.clockInfoIndex[j];
361 if (clock_array_index >= clock_info_array->ucNumEntries)
362 continue;
363 if (k >= CZ_MAX_HARDWARE_POWERLEVELS)
364 break;
365 clock_info = (union pplib_clock_info *)
366 &clock_info_array->clockInfo[clock_array_index *
367 clock_info_array->ucEntrySize];
368 cz_parse_pplib_clock_info(adev, &adev->pm.dpm.ps[i],
369 k, clock_info);
370 k++;
371 }
372 cz_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
373 non_clock_info,
374 non_clock_info_array->ucEntrySize);
375 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
376 }
377 adev->pm.dpm.num_ps = state_array->ucNumEntries;
378
379 return 0;
380}
381
382static int cz_process_firmware_header(struct amdgpu_device *adev)
383{
384 struct cz_power_info *pi = cz_get_pi(adev);
385 u32 tmp;
386 int ret;
387
388 ret = cz_read_smc_sram_dword(adev, SMU8_FIRMWARE_HEADER_LOCATION +
389 offsetof(struct SMU8_Firmware_Header,
390 DpmTable),
391 &tmp, pi->sram_end);
392
393 if (ret == 0)
394 pi->dpm_table_start = tmp;
395
396 return ret;
397}
398
399static int cz_dpm_init(struct amdgpu_device *adev)
400{
401 struct cz_power_info *pi;
402 int ret, i;
403
404 pi = kzalloc(sizeof(struct cz_power_info), GFP_KERNEL);
405 if (NULL == pi)
406 return -ENOMEM;
407
408 adev->pm.dpm.priv = pi;
409
410 ret = amdgpu_get_platform_caps(adev);
411 if (ret)
412 return ret;
413
414 ret = amdgpu_parse_extended_power_table(adev);
415 if (ret)
416 return ret;
417
418 pi->sram_end = SMC_RAM_END;
419
420 /* set up DPM defaults */
421 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
422 pi->active_target[i] = CZ_AT_DFLT;
423
424 pi->mgcg_cgtt_local0 = 0x0;
425 pi->mgcg_cgtt_local1 = 0x0;
426 pi->clock_slow_down_step = 25000;
427 pi->skip_clock_slow_down = 1;
9dcabece 428 pi->enable_nb_ps_policy = 0;
aaa36a97
AD		 429 pi->caps_power_containment = true;
430 pi->caps_cac = true;
431 pi->didt_enabled = false;
432 if (pi->didt_enabled) {
433 pi->caps_sq_ramping = true;
434 pi->caps_db_ramping = true;
435 pi->caps_td_ramping = true;
436 pi->caps_tcp_ramping = true;
437 }
438 pi->caps_sclk_ds = true;
439 pi->voting_clients = 0x00c00033;
440 pi->auto_thermal_throttling_enabled = true;
441 pi->bapm_enabled = false;
442 pi->disable_nb_ps3_in_battery = false;
443 pi->voltage_drop_threshold = 0;
444 pi->caps_sclk_throttle_low_notification = false;
445 pi->gfx_pg_threshold = 500;
446 pi->caps_fps = true;
447 /* uvd */
448 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false;
449 pi->caps_uvd_dpm = true;
450 /* vce */
451 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false;
452 pi->caps_vce_dpm = true;
453 /* acp */
454 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false;
455 pi->caps_acp_dpm = true;
456
457 pi->caps_stable_power_state = false;
458 pi->nb_dpm_enabled_by_driver = true;
459 pi->nb_dpm_enabled = false;
460 pi->caps_voltage_island = false;
461 /* flags which indicate need to upload pptable */
462 pi->need_pptable_upload = true;
463
464 ret = cz_parse_sys_info_table(adev);
465 if (ret)
466 return ret;
467
468 cz_patch_voltage_values(adev);
469 cz_construct_boot_state(adev);
470
471 ret = cz_parse_power_table(adev);
472 if (ret)
473 return ret;
474
475 ret = cz_process_firmware_header(adev);
476 if (ret)
477 return ret;
478
479 pi->dpm_enabled = true;
564ea790 480 pi->uvd_dynamic_pg = false;
aaa36a97
AD		 481
482 return 0;
483}
484
485static void cz_dpm_fini(struct amdgpu_device *adev)
486{
487 int i;
488
489 for (i = 0; i < adev->pm.dpm.num_ps; i++)
490 kfree(adev->pm.dpm.ps[i].ps_priv);
491
492 kfree(adev->pm.dpm.ps);
493 kfree(adev->pm.dpm.priv);
494 amdgpu_free_extended_power_table(adev);
495}
496
497static void
498cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
499 struct seq_file *m)
500{
501 struct amdgpu_clock_voltage_dependency_table *table =
502 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
503 u32 current_index =
504 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
505 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
506 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
507 u32 sclk, tmp;
508 u16 vddc;
509
510 if (current_index >= NUM_SCLK_LEVELS) {
511 seq_printf(m, "invalid dpm profile %d\n", current_index);
512 } else {
513 sclk = table->entries[current_index].clk;
514 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
515 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
516 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
517 vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
518 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
519 current_index, sclk, vddc);
520 }
521}
522
523static void cz_dpm_print_power_state(struct amdgpu_device *adev,
524 struct amdgpu_ps *rps)
525{
526 int i;
527 struct cz_ps *ps = cz_get_ps(rps);
528
529 amdgpu_dpm_print_class_info(rps->class, rps->class2);
530 amdgpu_dpm_print_cap_info(rps->caps);
531
532 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
533 for (i = 0; i < ps->num_levels; i++) {
534 struct cz_pl *pl = &ps->levels[i];
535
536 DRM_INFO("\t\tpower level %d sclk: %u vddc: %u\n",
537 i, pl->sclk,
538 cz_convert_8bit_index_to_voltage(adev, pl->vddc_index));
539 }
540
541 amdgpu_dpm_print_ps_status(adev, rps);
542}
543
544static void cz_dpm_set_funcs(struct amdgpu_device *adev);
545
5fc3aeeb 546static int cz_dpm_early_init(void *handle)
aaa36a97 547{
5fc3aeeb 548 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
549
aaa36a97
AD		 550 cz_dpm_set_funcs(adev);
551
552 return 0;
553}
554
564ea790 555
5fc3aeeb 556static int cz_dpm_late_init(void *handle)
564ea790 557{
5fc3aeeb 558 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
559
6d8db6ce
SJ		 560 if (amdgpu_dpm) {
561 /* powerdown unused blocks for now */
562 cz_dpm_powergate_uvd(adev, true);
563 cz_dpm_powergate_vce(adev, true);
564 }
564ea790
SJ		 565
566 return 0;
567}
568
5fc3aeeb 569static int cz_dpm_sw_init(void *handle)
aaa36a97 570{
5fc3aeeb 571 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 572 int ret = 0;
573 /* fix me to add thermal support TODO */
574
575 /* default to balanced state */
576 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
577 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
578 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
579 adev->pm.default_sclk = adev->clock.default_sclk;
580 adev->pm.default_mclk = adev->clock.default_mclk;
581 adev->pm.current_sclk = adev->clock.default_sclk;
582 adev->pm.current_mclk = adev->clock.default_mclk;
583 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
584
585 if (amdgpu_dpm == 0)
586 return 0;
587
588 mutex_lock(&adev->pm.mutex);
589 ret = cz_dpm_init(adev);
590 if (ret)
591 goto dpm_init_failed;
592
593 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
594 if (amdgpu_dpm == 1)
595 amdgpu_pm_print_power_states(adev);
596
597 ret = amdgpu_pm_sysfs_init(adev);
598 if (ret)
599 goto dpm_init_failed;
600
601 mutex_unlock(&adev->pm.mutex);
602 DRM_INFO("amdgpu: dpm initialized\n");
603
604 return 0;
605
606dpm_init_failed:
607 cz_dpm_fini(adev);
608 mutex_unlock(&adev->pm.mutex);
609 DRM_ERROR("amdgpu: dpm initialization failed\n");
610
611 return ret;
612}
613
5fc3aeeb 614static int cz_dpm_sw_fini(void *handle)
aaa36a97 615{
5fc3aeeb 616 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
617
aaa36a97
AD		 618 mutex_lock(&adev->pm.mutex);
619 amdgpu_pm_sysfs_fini(adev);
620 cz_dpm_fini(adev);
621 mutex_unlock(&adev->pm.mutex);
622
623 return 0;
624}
625
626static void cz_reset_ap_mask(struct amdgpu_device *adev)
627{
628 struct cz_power_info *pi = cz_get_pi(adev);
629
630 pi->active_process_mask = 0;
631
632}
633
634static int cz_dpm_download_pptable_from_smu(struct amdgpu_device *adev,
635 void **table)
636{
637 int ret = 0;
638
639 ret = cz_smu_download_pptable(adev, table);
640
641 return ret;
642}
643
644static int cz_dpm_upload_pptable_to_smu(struct amdgpu_device *adev)
645{
646 struct cz_power_info *pi = cz_get_pi(adev);
647 struct SMU8_Fusion_ClkTable *clock_table;
648 struct atom_clock_dividers dividers;
649 void *table = NULL;
650 uint8_t i = 0;
651 int ret = 0;
652
653 struct amdgpu_clock_voltage_dependency_table *vddc_table =
654 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
655 struct amdgpu_clock_voltage_dependency_table *vddgfx_table =
656 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk;
657 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
658 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
659 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
660 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
661 struct amdgpu_clock_voltage_dependency_table *acp_table =
662 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
663
664 if (!pi->need_pptable_upload)
665 return 0;
666
667 ret = cz_dpm_download_pptable_from_smu(adev, &table);
668 if (ret) {
669 DRM_ERROR("amdgpu: Failed to get power play table from SMU!\n");
670 return -EINVAL;
671 }
672
673 clock_table = (struct SMU8_Fusion_ClkTable *)table;
674 /* patch clock table */
675 if (vddc_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
676 vddgfx_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
677 uvd_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
678 vce_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
679 acp_table->count > CZ_MAX_HARDWARE_POWERLEVELS) {
680 DRM_ERROR("amdgpu: Invalid Clock Voltage Dependency Table!\n");
681 return -EINVAL;
682 }
683
684 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
685
686 /* vddc sclk */
687 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
688 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
689 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
690 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
691 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
692 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
693 false, &dividers);
694 if (ret)
695 return ret;
696 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
697 (uint8_t)dividers.post_divider;
698
699 /* vddgfx sclk */
700 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
701 (i < vddgfx_table->count) ? (uint8_t)vddgfx_table->entries[i].v : 0;
702
703 /* acp breakdown */
704 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
705 (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
706 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
707 (i < acp_table->count) ? acp_table->entries[i].clk : 0;
708 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
709 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
710 false, &dividers);
711 if (ret)
712 return ret;
713 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
714 (uint8_t)dividers.post_divider;
715
716 /* uvd breakdown */
717 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
718 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
719 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
720 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
721 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
722 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
723 false, &dividers);
724 if (ret)
725 return ret;
726 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
727 (uint8_t)dividers.post_divider;
728
729 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
730 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
731 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
732 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
733 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
734 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
735 false, &dividers);
736 if (ret)
737 return ret;
738 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
739 (uint8_t)dividers.post_divider;
740
741 /* vce breakdown */
742 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
743 (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
744 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
745 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
746 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
747 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
748 false, &dividers);
749 if (ret)
750 return ret;
751 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
752 (uint8_t)dividers.post_divider;
753 }
754
755 /* its time to upload to SMU */
756 ret = cz_smu_upload_pptable(adev);
757 if (ret) {
758 DRM_ERROR("amdgpu: Failed to put power play table to SMU!\n");
759 return ret;
760 }
761
762 return 0;
763}
764
765static void cz_init_sclk_limit(struct amdgpu_device *adev)
766{
767 struct cz_power_info *pi = cz_get_pi(adev);
768 struct amdgpu_clock_voltage_dependency_table *table =
769 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
770 uint32_t clock = 0, level;
771
772 if (!table || !table->count) {
773 DRM_ERROR("Invalid Voltage Dependency table.\n");
774 return;
775 }
776
777 pi->sclk_dpm.soft_min_clk = 0;
778 pi->sclk_dpm.hard_min_clk = 0;
779 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
780 level = cz_get_argument(adev);
781 if (level < table->count)
782 clock = table->entries[level].clk;
783 else {
784 DRM_ERROR("Invalid SLCK Voltage Dependency table entry.\n");
785 clock = table->entries[table->count - 1].clk;
786 }
787
788 pi->sclk_dpm.soft_max_clk = clock;
789 pi->sclk_dpm.hard_max_clk = clock;
790
791}
792
793static void cz_init_uvd_limit(struct amdgpu_device *adev)
794{
795 struct cz_power_info *pi = cz_get_pi(adev);
796 struct amdgpu_uvd_clock_voltage_dependency_table *table =
797 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
798 uint32_t clock = 0, level;
799
800 if (!table || !table->count) {
801 DRM_ERROR("Invalid Voltage Dependency table.\n");
802 return;
803 }
804
805 pi->uvd_dpm.soft_min_clk = 0;
806 pi->uvd_dpm.hard_min_clk = 0;
807 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel);
808 level = cz_get_argument(adev);
809 if (level < table->count)
810 clock = table->entries[level].vclk;
811 else {
812 DRM_ERROR("Invalid UVD Voltage Dependency table entry.\n");
813 clock = table->entries[table->count - 1].vclk;
814 }
815
816 pi->uvd_dpm.soft_max_clk = clock;
817 pi->uvd_dpm.hard_max_clk = clock;
818
819}
820
821static void cz_init_vce_limit(struct amdgpu_device *adev)
822{
823 struct cz_power_info *pi = cz_get_pi(adev);
824 struct amdgpu_vce_clock_voltage_dependency_table *table =
825 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
826 uint32_t clock = 0, level;
827
828 if (!table || !table->count) {
829 DRM_ERROR("Invalid Voltage Dependency table.\n");
830 return;
831 }
832
b7a07769
SJ		 833 pi->vce_dpm.soft_min_clk = table->entries[0].ecclk;
834 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
aaa36a97
AD		 835 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
836 level = cz_get_argument(adev);
837 if (level < table->count)
b7a07769 838 clock = table->entries[level].ecclk;
aaa36a97
AD		 839 else {
840 /* future BIOS would fix this error */
841 DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n");
b7a07769 842 clock = table->entries[table->count - 1].ecclk;
aaa36a97
AD		 843 }
844
845 pi->vce_dpm.soft_max_clk = clock;
846 pi->vce_dpm.hard_max_clk = clock;
847
848}
849
850static void cz_init_acp_limit(struct amdgpu_device *adev)
851{
852 struct cz_power_info *pi = cz_get_pi(adev);
853 struct amdgpu_clock_voltage_dependency_table *table =
854 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
855 uint32_t clock = 0, level;
856
857 if (!table || !table->count) {
858 DRM_ERROR("Invalid Voltage Dependency table.\n");
859 return;
860 }
861
862 pi->acp_dpm.soft_min_clk = 0;
863 pi->acp_dpm.hard_min_clk = 0;
864 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxAclkLevel);
865 level = cz_get_argument(adev);
866 if (level < table->count)
867 clock = table->entries[level].clk;
868 else {
869 DRM_ERROR("Invalid ACP Voltage Dependency table entry.\n");
870 clock = table->entries[table->count - 1].clk;
871 }
872
873 pi->acp_dpm.soft_max_clk = clock;
874 pi->acp_dpm.hard_max_clk = clock;
875
876}
877
878static void cz_init_pg_state(struct amdgpu_device *adev)
879{
880 struct cz_power_info *pi = cz_get_pi(adev);
881
882 pi->uvd_power_gated = false;
883 pi->vce_power_gated = false;
884 pi->acp_power_gated = false;
885
886}
887
888static void cz_init_sclk_threshold(struct amdgpu_device *adev)
889{
890 struct cz_power_info *pi = cz_get_pi(adev);
891
892 pi->low_sclk_interrupt_threshold = 0;
893
894}
895
896static void cz_dpm_setup_asic(struct amdgpu_device *adev)
897{
898 cz_reset_ap_mask(adev);
899 cz_dpm_upload_pptable_to_smu(adev);
900 cz_init_sclk_limit(adev);
901 cz_init_uvd_limit(adev);
902 cz_init_vce_limit(adev);
903 cz_init_acp_limit(adev);
904 cz_init_pg_state(adev);
905 cz_init_sclk_threshold(adev);
906
907}
908
909static bool cz_check_smu_feature(struct amdgpu_device *adev,
910 uint32_t feature)
911{
912 uint32_t smu_feature = 0;
913 int ret;
914
915 ret = cz_send_msg_to_smc_with_parameter(adev,
916 PPSMC_MSG_GetFeatureStatus, 0);
917 if (ret) {
918 DRM_ERROR("Failed to get SMU features from SMC.\n");
919 return false;
920 } else {
921 smu_feature = cz_get_argument(adev);
922 if (feature & smu_feature)
923 return true;
924 }
925
926 return false;
927}
928
929static bool cz_check_for_dpm_enabled(struct amdgpu_device *adev)
930{
931 if (cz_check_smu_feature(adev,
932 SMU_EnabledFeatureScoreboard_SclkDpmOn))
933 return true;
934
935 return false;
936}
937
938static void cz_program_voting_clients(struct amdgpu_device *adev)
939{
940 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
941}
942
943static void cz_clear_voting_clients(struct amdgpu_device *adev)
944{
945 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
946}
947
948static int cz_start_dpm(struct amdgpu_device *adev)
949{
950 int ret = 0;
951
952 if (amdgpu_dpm) {
953 ret = cz_send_msg_to_smc_with_parameter(adev,
954 PPSMC_MSG_EnableAllSmuFeatures, SCLK_DPM_MASK);
955 if (ret) {
956 DRM_ERROR("SMU feature: SCLK_DPM enable failed\n");
957 return -EINVAL;
958 }
959 }
960
961 return 0;
962}
963
964static int cz_stop_dpm(struct amdgpu_device *adev)
965{
966 int ret = 0;
967
968 if (amdgpu_dpm && adev->pm.dpm_enabled) {
969 ret = cz_send_msg_to_smc_with_parameter(adev,
970 PPSMC_MSG_DisableAllSmuFeatures, SCLK_DPM_MASK);
971 if (ret) {
972 DRM_ERROR("SMU feature: SCLK_DPM disable failed\n");
973 return -EINVAL;
974 }
975 }
976
977 return 0;
978}
979
980static uint32_t cz_get_sclk_level(struct amdgpu_device *adev,
981 uint32_t clock, uint16_t msg)
982{
983 int i = 0;
984 struct amdgpu_clock_voltage_dependency_table *table =
985 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
986
987 switch (msg) {
988 case PPSMC_MSG_SetSclkSoftMin:
989 case PPSMC_MSG_SetSclkHardMin:
990 for (i = 0; i < table->count; i++)
991 if (clock <= table->entries[i].clk)
992 break;
993 if (i == table->count)
994 i = table->count - 1;
995 break;
996 case PPSMC_MSG_SetSclkSoftMax:
997 case PPSMC_MSG_SetSclkHardMax:
998 for (i = table->count - 1; i >= 0; i--)
999 if (clock >= table->entries[i].clk)
1000 break;
1001 if (i < 0)
1002 i = 0;
1003 break;
1004 default:
1005 break;
1006 }
1007
1008 return i;
1009}
1010
b7a07769
SJ		 1011static uint32_t cz_get_eclk_level(struct amdgpu_device *adev,
1012 uint32_t clock, uint16_t msg)
1013{
1014 int i = 0;
1015 struct amdgpu_vce_clock_voltage_dependency_table *table =
1016 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1017
1018 if (table->count == 0)
1019 return 0;
1020
1021 switch (msg) {
1022 case PPSMC_MSG_SetEclkSoftMin:
1023 case PPSMC_MSG_SetEclkHardMin:
1024 for (i = 0; i < table->count-1; i++)
1025 if (clock <= table->entries[i].ecclk)
1026 break;
1027 break;
1028 case PPSMC_MSG_SetEclkSoftMax:
1029 case PPSMC_MSG_SetEclkHardMax:
1030 for (i = table->count - 1; i > 0; i--)
1031 if (clock >= table->entries[i].ecclk)
1032 break;
1033 break;
1034 default:
1035 break;
1036 }
1037
1038 return i;
1039}
1040
aaa36a97
AD		 1041static int cz_program_bootup_state(struct amdgpu_device *adev)
1042{
1043 struct cz_power_info *pi = cz_get_pi(adev);
1044 uint32_t soft_min_clk = 0;
1045 uint32_t soft_max_clk = 0;
1046 int ret = 0;
1047
1048 pi->sclk_dpm.soft_min_clk = pi->sys_info.bootup_sclk;
1049 pi->sclk_dpm.soft_max_clk = pi->sys_info.bootup_sclk;
1050
1051 soft_min_clk = cz_get_sclk_level(adev,
1052 pi->sclk_dpm.soft_min_clk,
1053 PPSMC_MSG_SetSclkSoftMin);
1054 soft_max_clk = cz_get_sclk_level(adev,
1055 pi->sclk_dpm.soft_max_clk,
1056 PPSMC_MSG_SetSclkSoftMax);
1057
1058 ret = cz_send_msg_to_smc_with_parameter(adev,
1059 PPSMC_MSG_SetSclkSoftMin, soft_min_clk);
1060 if (ret)
1061 return -EINVAL;
1062
1063 ret = cz_send_msg_to_smc_with_parameter(adev,
1064 PPSMC_MSG_SetSclkSoftMax, soft_max_clk);
1065 if (ret)
1066 return -EINVAL;
1067
1068 return 0;
1069}
1070
1071/* TODO */
1072static int cz_disable_cgpg(struct amdgpu_device *adev)
1073{
1074 return 0;
1075}
1076
1077/* TODO */
1078static int cz_enable_cgpg(struct amdgpu_device *adev)
1079{
1080 return 0;
1081}
1082
1083/* TODO */
1084static int cz_program_pt_config_registers(struct amdgpu_device *adev)
1085{
1086 return 0;
1087}
1088
1089static void cz_do_enable_didt(struct amdgpu_device *adev, bool enable)
1090{
1091 struct cz_power_info *pi = cz_get_pi(adev);
1092 uint32_t reg = 0;
1093
1094 if (pi->caps_sq_ramping) {
1095 reg = RREG32_DIDT(ixDIDT_SQ_CTRL0);
1096 if (enable)
1097 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1098 else
1099 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1100 WREG32_DIDT(ixDIDT_SQ_CTRL0, reg);
1101 }
1102 if (pi->caps_db_ramping) {
1103 reg = RREG32_DIDT(ixDIDT_DB_CTRL0);
1104 if (enable)
1105 reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 1);
1106 else
1107 reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 0);
1108 WREG32_DIDT(ixDIDT_DB_CTRL0, reg);
1109 }
1110 if (pi->caps_td_ramping) {
1111 reg = RREG32_DIDT(ixDIDT_TD_CTRL0);
1112 if (enable)
1113 reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 1);
1114 else
1115 reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 0);
1116 WREG32_DIDT(ixDIDT_TD_CTRL0, reg);
1117 }
1118 if (pi->caps_tcp_ramping) {
1119 reg = RREG32_DIDT(ixDIDT_TCP_CTRL0);
1120 if (enable)
1121 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1122 else
1123 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1124 WREG32_DIDT(ixDIDT_TCP_CTRL0, reg);
1125 }
1126
1127}
1128
1129static int cz_enable_didt(struct amdgpu_device *adev, bool enable)
1130{
1131 struct cz_power_info *pi = cz_get_pi(adev);
1132 int ret;
1133
1134 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
1135 pi->caps_td_ramping || pi->caps_tcp_ramping) {
1136 if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) {
1137 ret = cz_disable_cgpg(adev);
1138 if (ret) {
1139 DRM_ERROR("Pre Di/Dt disable cg/pg failed\n");
1140 return -EINVAL;
1141 }
1142 adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE;
1143 }
1144
1145 ret = cz_program_pt_config_registers(adev);
1146 if (ret) {
1147 DRM_ERROR("Di/Dt config failed\n");
1148 return -EINVAL;
1149 }
1150 cz_do_enable_didt(adev, enable);
1151
1152 if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) {
1153 ret = cz_enable_cgpg(adev);
1154 if (ret) {
1155 DRM_ERROR("Post Di/Dt enable cg/pg failed\n");
1156 return -EINVAL;
1157 }
1158 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1159 }
1160 }
1161
1162 return 0;
1163}
1164
1165/* TODO */
1166static void cz_reset_acp_boot_level(struct amdgpu_device *adev)
1167{
1168}
1169
1170static void cz_update_current_ps(struct amdgpu_device *adev,
1171 struct amdgpu_ps *rps)
1172{
1173 struct cz_power_info *pi = cz_get_pi(adev);
1174 struct cz_ps *ps = cz_get_ps(rps);
1175
1176 pi->current_ps = *ps;
1177 pi->current_rps = *rps;
1178 pi->current_rps.ps_priv = ps;
1179
1180}
1181
1182static void cz_update_requested_ps(struct amdgpu_device *adev,
1183 struct amdgpu_ps *rps)
1184{
1185 struct cz_power_info *pi = cz_get_pi(adev);
1186 struct cz_ps *ps = cz_get_ps(rps);
1187
1188 pi->requested_ps = *ps;
1189 pi->requested_rps = *rps;
1190 pi->requested_rps.ps_priv = ps;
1191
1192}
1193
1194/* PP arbiter support needed TODO */
1195static void cz_apply_state_adjust_rules(struct amdgpu_device *adev,
1196 struct amdgpu_ps *new_rps,
1197 struct amdgpu_ps *old_rps)
1198{
1199 struct cz_ps *ps = cz_get_ps(new_rps);
1200 struct cz_power_info *pi = cz_get_pi(adev);
1201 struct amdgpu_clock_and_voltage_limits *limits =
1202 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1203 /* 10kHz memory clock */
1204 uint32_t mclk = 0;
1205
1206 ps->force_high = false;
1207 ps->need_dfs_bypass = true;
1208 pi->video_start = new_rps->dclk || new_rps->vclk ||
1209 new_rps->evclk || new_rps->ecclk;
1210
1211 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
1212 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
1213 pi->battery_state = true;
1214 else
1215 pi->battery_state = false;
1216
1217 if (pi->caps_stable_power_state)
1218 mclk = limits->mclk;
1219
1220 if (mclk > pi->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK - 1])
1221 ps->force_high = true;
1222
1223}
1224
1225static int cz_dpm_enable(struct amdgpu_device *adev)
1226{
1227 int ret = 0;
1228
1229 /* renable will hang up SMU, so check first */
1230 if (cz_check_for_dpm_enabled(adev))
1231 return -EINVAL;
1232
1233 cz_program_voting_clients(adev);
1234
1235 ret = cz_start_dpm(adev);
1236 if (ret) {
1237 DRM_ERROR("Carrizo DPM enable failed\n");
1238 return -EINVAL;
1239 }
1240
1241 ret = cz_program_bootup_state(adev);
1242 if (ret) {
1243 DRM_ERROR("Carrizo bootup state program failed\n");
1244 return -EINVAL;
1245 }
1246
1247 ret = cz_enable_didt(adev, true);
1248 if (ret) {
1249 DRM_ERROR("Carrizo enable di/dt failed\n");
1250 return -EINVAL;
1251 }
1252
1253 cz_reset_acp_boot_level(adev);
1254
1255 cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1256
1257 return 0;
1258}
1259
5fc3aeeb 1260static int cz_dpm_hw_init(void *handle)
aaa36a97 1261{
5fc3aeeb 1262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
46651cc5 1263 int ret = 0;
aaa36a97
AD		 1264
1265 mutex_lock(&adev->pm.mutex);
1266
05188312
AD		 1267 /* smu init only needs to be called at startup, not resume.
1268 * It should be in sw_init, but requires the fw info gathered
1269 * in sw_init from other IP modules.
1270 */
aaa36a97
AD		 1271 ret = cz_smu_init(adev);
1272 if (ret) {
1273 DRM_ERROR("amdgpu: smc initialization failed\n");
1274 mutex_unlock(&adev->pm.mutex);
1275 return ret;
1276 }
1277
1278 /* do the actual fw loading */
1279 ret = cz_smu_start(adev);
1280 if (ret) {
1281 DRM_ERROR("amdgpu: smc start failed\n");
1282 mutex_unlock(&adev->pm.mutex);
1283 return ret;
1284 }
1285
46651cc5
SJ		 1286 if (!amdgpu_dpm) {
1287 adev->pm.dpm_enabled = false;
1288 mutex_unlock(&adev->pm.mutex);
1289 return ret;
1290 }
1291
aaa36a97
AD		 1292 /* cz dpm setup asic */
1293 cz_dpm_setup_asic(adev);
1294
1295 /* cz dpm enable */
1296 ret = cz_dpm_enable(adev);
1297 if (ret)
1298 adev->pm.dpm_enabled = false;
1299 else
1300 adev->pm.dpm_enabled = true;
1301
1302 mutex_unlock(&adev->pm.mutex);
1303
1304 return 0;
1305}
1306
1307static int cz_dpm_disable(struct amdgpu_device *adev)
1308{
1309 int ret = 0;
1310
1311 if (!cz_check_for_dpm_enabled(adev))
1312 return -EINVAL;
1313
1314 ret = cz_enable_didt(adev, false);
1315 if (ret) {
1316 DRM_ERROR("Carrizo disable di/dt failed\n");
1317 return -EINVAL;
1318 }
1319
564ea790
SJ		 1320 /* powerup blocks */
1321 cz_dpm_powergate_uvd(adev, false);
b7a07769 1322 cz_dpm_powergate_vce(adev, false);
564ea790 1323
aaa36a97
AD		 1324 cz_clear_voting_clients(adev);
1325 cz_stop_dpm(adev);
1326 cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1327
1328 return 0;
1329}
1330
5fc3aeeb 1331static int cz_dpm_hw_fini(void *handle)
aaa36a97
AD		 1332{
1333 int ret = 0;
5fc3aeeb 1334 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1335
1336 mutex_lock(&adev->pm.mutex);
1337
05188312
AD		 1338 /* smu fini only needs to be called at teardown, not suspend.
1339 * It should be in sw_fini, but we put it here for symmetry
1340 * with smu init.
1341 */
aaa36a97
AD		 1342 cz_smu_fini(adev);
1343
1344 if (adev->pm.dpm_enabled) {
1345 ret = cz_dpm_disable(adev);
aaa36a97
AD		 1346
1347 adev->pm.dpm.current_ps =
1348 adev->pm.dpm.requested_ps =
1349 adev->pm.dpm.boot_ps;
1350 }
1351
1352 adev->pm.dpm_enabled = false;
1353
1354 mutex_unlock(&adev->pm.mutex);
1355
10457457 1356 return ret;
aaa36a97
AD		 1357}
1358
5fc3aeeb 1359static int cz_dpm_suspend(void *handle)
aaa36a97
AD		 1360{
1361 int ret = 0;
5fc3aeeb 1362 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1363
1364 if (adev->pm.dpm_enabled) {
1365 mutex_lock(&adev->pm.mutex);
1366
1367 ret = cz_dpm_disable(adev);
aaa36a97
AD		 1368
1369 adev->pm.dpm.current_ps =
1370 adev->pm.dpm.requested_ps =
1371 adev->pm.dpm.boot_ps;
1372
1373 mutex_unlock(&adev->pm.mutex);
1374 }
1375
10457457 1376 return ret;
aaa36a97
AD		 1377}
1378
5fc3aeeb 1379static int cz_dpm_resume(void *handle)
aaa36a97
AD		 1380{
1381 int ret = 0;
5fc3aeeb 1382 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1383
1384 mutex_lock(&adev->pm.mutex);
aaa36a97
AD		 1385
1386 /* do the actual fw loading */
1387 ret = cz_smu_start(adev);
1388 if (ret) {
1389 DRM_ERROR("amdgpu: smc start failed\n");
1390 mutex_unlock(&adev->pm.mutex);
1391 return ret;
1392 }
1393
46651cc5
SJ		 1394 if (!amdgpu_dpm) {
1395 adev->pm.dpm_enabled = false;
1396 mutex_unlock(&adev->pm.mutex);
1397 return ret;
1398 }
1399
aaa36a97
AD		 1400 /* cz dpm setup asic */
1401 cz_dpm_setup_asic(adev);
1402
1403 /* cz dpm enable */
1404 ret = cz_dpm_enable(adev);
1405 if (ret)
1406 adev->pm.dpm_enabled = false;
1407 else
1408 adev->pm.dpm_enabled = true;
1409
1410 mutex_unlock(&adev->pm.mutex);
1411 /* upon resume, re-compute the clocks */
1412 if (adev->pm.dpm_enabled)
1413 amdgpu_pm_compute_clocks(adev);
1414
1415 return 0;
1416}
1417
5fc3aeeb 1418static int cz_dpm_set_clockgating_state(void *handle,
1419 enum amd_clockgating_state state)
aaa36a97
AD		 1420{
1421 return 0;
1422}
1423
5fc3aeeb 1424static int cz_dpm_set_powergating_state(void *handle,
1425 enum amd_powergating_state state)
aaa36a97
AD		 1426{
1427 return 0;
1428}
1429
1430/* borrowed from KV, need future unify */
1431static int cz_dpm_get_temperature(struct amdgpu_device *adev)
1432{
1433 int actual_temp = 0;
1434 uint32_t temp = RREG32_SMC(0xC0300E0C);
1435
1436 if (temp)
1437 actual_temp = 1000 * ((temp / 8) - 49);
1438
1439 return actual_temp;
1440}
1441
1442static int cz_dpm_pre_set_power_state(struct amdgpu_device *adev)
1443{
1444 struct cz_power_info *pi = cz_get_pi(adev);
1445 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1446 struct amdgpu_ps *new_ps = &requested_ps;
1447
1448 cz_update_requested_ps(adev, new_ps);
1449 cz_apply_state_adjust_rules(adev, &pi->requested_rps,
1450 &pi->current_rps);
1451
1452 return 0;
1453}
1454
1455static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev)
1456{
1457 struct cz_power_info *pi = cz_get_pi(adev);
1458 struct amdgpu_clock_and_voltage_limits *limits =
1459 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1460 uint32_t clock, stable_ps_clock = 0;
1461
1462 clock = pi->sclk_dpm.soft_min_clk;
1463
1464 if (pi->caps_stable_power_state) {
1465 stable_ps_clock = limits->sclk * 75 / 100;
1466 if (clock < stable_ps_clock)
1467 clock = stable_ps_clock;
1468 }
1469
1470 if (clock != pi->sclk_dpm.soft_min_clk) {
1471 pi->sclk_dpm.soft_min_clk = clock;
1472 cz_send_msg_to_smc_with_parameter(adev,
1473 PPSMC_MSG_SetSclkSoftMin,
1474 cz_get_sclk_level(adev, clock,
1475 PPSMC_MSG_SetSclkSoftMin));
1476 }
1477
1478 if (pi->caps_stable_power_state &&
1479 pi->sclk_dpm.soft_max_clk != clock) {
1480 pi->sclk_dpm.soft_max_clk = clock;
1481 cz_send_msg_to_smc_with_parameter(adev,
1482 PPSMC_MSG_SetSclkSoftMax,
1483 cz_get_sclk_level(adev, clock,
1484 PPSMC_MSG_SetSclkSoftMax));
1485 } else {
1486 cz_send_msg_to_smc_with_parameter(adev,
1487 PPSMC_MSG_SetSclkSoftMax,
1488 cz_get_sclk_level(adev,
1489 pi->sclk_dpm.soft_max_clk,
1490 PPSMC_MSG_SetSclkSoftMax));
1491 }
1492
1493 return 0;
1494}
1495
1496static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
1497{
1498 int ret = 0;
1499 struct cz_power_info *pi = cz_get_pi(adev);
1500
1501 if (pi->caps_sclk_ds) {
1502 cz_send_msg_to_smc_with_parameter(adev,
1503 PPSMC_MSG_SetMinDeepSleepSclk,
1504 CZ_MIN_DEEP_SLEEP_SCLK);
1505 }
1506
1507 return ret;
1508}
1509
1510/* ?? without dal support, is this still needed in setpowerstate list*/
1511static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev)
1512{
1513 int ret = 0;
1514 struct cz_power_info *pi = cz_get_pi(adev);
1515
1516 cz_send_msg_to_smc_with_parameter(adev,
1517 PPSMC_MSG_SetWatermarkFrequency,
1518 pi->sclk_dpm.soft_max_clk);
1519
1520 return ret;
1521}
1522
1523static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev)
1524{
1525 int ret = 0;
1526 struct cz_power_info *pi = cz_get_pi(adev);
1527
1528 /* also depend on dal NBPStateDisableRequired */
1529 if (pi->nb_dpm_enabled_by_driver && !pi->nb_dpm_enabled) {
1530 ret = cz_send_msg_to_smc_with_parameter(adev,
1531 PPSMC_MSG_EnableAllSmuFeatures,
1532 NB_DPM_MASK);
1533 if (ret) {
1534 DRM_ERROR("amdgpu: nb dpm enable failed\n");
1535 return ret;
1536 }
1537 pi->nb_dpm_enabled = true;
1538 }
1539
1540 return ret;
1541}
1542
1543static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev,
1544 bool enable)
1545{
1546 if (enable)
1547 cz_send_msg_to_smc(adev, PPSMC_MSG_EnableLowMemoryPstate);
1548 else
1549 cz_send_msg_to_smc(adev, PPSMC_MSG_DisableLowMemoryPstate);
1550
1551}
1552
1553static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
1554{
1555 int ret = 0;
1556 struct cz_power_info *pi = cz_get_pi(adev);
1557 struct cz_ps *ps = &pi->requested_ps;
1558
1559 if (pi->sys_info.nb_dpm_enable) {
1560 if (ps->force_high)
1561 cz_dpm_nbdpm_lm_pstate_enable(adev, true);
1562 else
1563 cz_dpm_nbdpm_lm_pstate_enable(adev, false);
1564 }
1565
1566 return ret;
1567}
1568
1569/* with dpm enabled */
1570static int cz_dpm_set_power_state(struct amdgpu_device *adev)
1571{
1572 int ret = 0;
1573
1574 cz_dpm_update_sclk_limit(adev);
1575 cz_dpm_set_deep_sleep_sclk_threshold(adev);
1576 cz_dpm_set_watermark_threshold(adev);
1577 cz_dpm_enable_nbdpm(adev);
1578 cz_dpm_update_low_memory_pstate(adev);
1579
1580 return ret;
1581}
1582
1583static void cz_dpm_post_set_power_state(struct amdgpu_device *adev)
1584{
1585 struct cz_power_info *pi = cz_get_pi(adev);
1586 struct amdgpu_ps *ps = &pi->requested_rps;
1587
1588 cz_update_current_ps(adev, ps);
1589
1590}
1591
1592static int cz_dpm_force_highest(struct amdgpu_device *adev)
1593{
1594 struct cz_power_info *pi = cz_get_pi(adev);
1595 int ret = 0;
1596
1597 if (pi->sclk_dpm.soft_min_clk != pi->sclk_dpm.soft_max_clk) {
1598 pi->sclk_dpm.soft_min_clk =
1599 pi->sclk_dpm.soft_max_clk;
1600 ret = cz_send_msg_to_smc_with_parameter(adev,
1601 PPSMC_MSG_SetSclkSoftMin,
1602 cz_get_sclk_level(adev,
1603 pi->sclk_dpm.soft_min_clk,
1604 PPSMC_MSG_SetSclkSoftMin));
1605 if (ret)
1606 return ret;
1607 }
1608
1609 return ret;
1610}
1611
1612static int cz_dpm_force_lowest(struct amdgpu_device *adev)
1613{
1614 struct cz_power_info *pi = cz_get_pi(adev);
1615 int ret = 0;
1616
1617 if (pi->sclk_dpm.soft_max_clk != pi->sclk_dpm.soft_min_clk) {
1618 pi->sclk_dpm.soft_max_clk = pi->sclk_dpm.soft_min_clk;
1619 ret = cz_send_msg_to_smc_with_parameter(adev,
1620 PPSMC_MSG_SetSclkSoftMax,
1621 cz_get_sclk_level(adev,
1622 pi->sclk_dpm.soft_max_clk,
1623 PPSMC_MSG_SetSclkSoftMax));
1624 if (ret)
1625 return ret;
1626 }
1627
1628 return ret;
1629}
1630
1631static uint32_t cz_dpm_get_max_sclk_level(struct amdgpu_device *adev)
1632{
1633 struct cz_power_info *pi = cz_get_pi(adev);
1634
1635 if (!pi->max_sclk_level) {
1636 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
1637 pi->max_sclk_level = cz_get_argument(adev) + 1;
1638 }
1639
1640 if (pi->max_sclk_level > CZ_MAX_HARDWARE_POWERLEVELS) {
1641 DRM_ERROR("Invalid max sclk level!\n");
1642 return -EINVAL;
1643 }
1644
1645 return pi->max_sclk_level;
1646}
1647
1648static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
1649{
1650 struct cz_power_info *pi = cz_get_pi(adev);
1651 struct amdgpu_clock_voltage_dependency_table *dep_table =
1652 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1653 uint32_t level = 0;
1654 int ret = 0;
1655
1656 pi->sclk_dpm.soft_min_clk = dep_table->entries[0].clk;
1657 level = cz_dpm_get_max_sclk_level(adev) - 1;
1658 if (level < dep_table->count)
1659 pi->sclk_dpm.soft_max_clk = dep_table->entries[level].clk;
1660 else
1661 pi->sclk_dpm.soft_max_clk =
1662 dep_table->entries[dep_table->count - 1].clk;
1663
1664 /* get min/max sclk soft value
1665 * notify SMU to execute */
1666 ret = cz_send_msg_to_smc_with_parameter(adev,
1667 PPSMC_MSG_SetSclkSoftMin,
1668 cz_get_sclk_level(adev,
1669 pi->sclk_dpm.soft_min_clk,
1670 PPSMC_MSG_SetSclkSoftMin));
1671 if (ret)
1672 return ret;
1673
1674 ret = cz_send_msg_to_smc_with_parameter(adev,
1675 PPSMC_MSG_SetSclkSoftMax,
1676 cz_get_sclk_level(adev,
1677 pi->sclk_dpm.soft_max_clk,
1678 PPSMC_MSG_SetSclkSoftMax));
1679 if (ret)
1680 return ret;
1681
1682 DRM_INFO("DPM unforce state min=%d, max=%d.\n",
1683 pi->sclk_dpm.soft_min_clk,
1684 pi->sclk_dpm.soft_max_clk);
1685
1686 return 0;
1687}
1688
1689static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
85cfe096 1690 enum amdgpu_dpm_forced_level level)
aaa36a97
AD		 1691{
1692 int ret = 0;
1693
1694 switch (level) {
1695 case AMDGPU_DPM_FORCED_LEVEL_HIGH:
85cfe096
AD		 1696 ret = cz_dpm_unforce_dpm_levels(adev);
1697 if (ret)
1698 return ret;
aaa36a97
AD		 1699 ret = cz_dpm_force_highest(adev);
1700 if (ret)
1701 return ret;
1702 break;
1703 case AMDGPU_DPM_FORCED_LEVEL_LOW:
85cfe096
AD		 1704 ret = cz_dpm_unforce_dpm_levels(adev);
1705 if (ret)
1706 return ret;
aaa36a97
AD		 1707 ret = cz_dpm_force_lowest(adev);
1708 if (ret)
1709 return ret;
1710 break;
1711 case AMDGPU_DPM_FORCED_LEVEL_AUTO:
1712 ret = cz_dpm_unforce_dpm_levels(adev);
1713 if (ret)
1714 return ret;
1715 break;
1716 default:
1717 break;
1718 }
1719
58829aa6
AD		 1720 adev->pm.dpm.forced_level = level;
1721
aaa36a97
AD		 1722 return ret;
1723}
1724
1725/* fix me, display configuration change lists here
1726 * mostly dal related*/
1727static void cz_dpm_display_configuration_changed(struct amdgpu_device *adev)
1728{
1729}
1730
1731static uint32_t cz_dpm_get_sclk(struct amdgpu_device *adev, bool low)
1732{
1733 struct cz_power_info *pi = cz_get_pi(adev);
1734 struct cz_ps *requested_state = cz_get_ps(&pi->requested_rps);
1735
1736 if (low)
1737 return requested_state->levels[0].sclk;
1738 else
1739 return requested_state->levels[requested_state->num_levels - 1].sclk;
1740
1741}
1742
1743static uint32_t cz_dpm_get_mclk(struct amdgpu_device *adev, bool low)
1744{
1745 struct cz_power_info *pi = cz_get_pi(adev);
1746
1747 return pi->sys_info.bootup_uma_clk;
1748}
1749
564ea790
SJ		 1750static int cz_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1751{
1752 struct cz_power_info *pi = cz_get_pi(adev);
1753 int ret = 0;
1754
1755 if (enable && pi->caps_uvd_dpm ) {
1756 pi->dpm_flags |= DPMFlags_UVD_Enabled;
1757 DRM_DEBUG("UVD DPM Enabled.\n");
1758
1759 ret = cz_send_msg_to_smc_with_parameter(adev,
1760 PPSMC_MSG_EnableAllSmuFeatures, UVD_DPM_MASK);
1761 } else {
1762 pi->dpm_flags &= ~DPMFlags_UVD_Enabled;
1763 DRM_DEBUG("UVD DPM Stopped\n");
1764
1765 ret = cz_send_msg_to_smc_with_parameter(adev,
1766 PPSMC_MSG_DisableAllSmuFeatures, UVD_DPM_MASK);
1767 }
1768
1769 return ret;
1770}
1771
1772static int cz_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1773{
1774 return cz_enable_uvd_dpm(adev, !gate);
1775}
1776
1777
1778static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1779{
1780 struct cz_power_info *pi = cz_get_pi(adev);
1781 int ret;
1782
1783 if (pi->uvd_power_gated == gate)
1784 return;
1785
1786 pi->uvd_power_gated = gate;
1787
1788 if (gate) {
1789 if (pi->caps_uvd_pg) {
1790 /* disable clockgating so we can properly shut down the block */
5fc3aeeb 1791 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1792 AMD_CG_STATE_UNGATE);
564ea790 1793 /* shutdown the UVD block */
5fc3aeeb 1794 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1795 AMD_PG_STATE_GATE);
564ea790
SJ		 1796 /* XXX: check for errors */
1797 }
1798 cz_update_uvd_dpm(adev, gate);
1799 if (pi->caps_uvd_pg)
1800 /* power off the UVD block */
1801 cz_send_msg_to_smc(adev, PPSMC_MSG_UVDPowerOFF);
1802 } else {
1803 if (pi->caps_uvd_pg) {
1804 /* power on the UVD block */
1805 if (pi->uvd_dynamic_pg)
1806 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 1);
1807 else
1808 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0);
1809 /* re-init the UVD block */
5fc3aeeb 1810 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1811 AMD_PG_STATE_UNGATE);
564ea790 1812 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
5fc3aeeb 1813 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1814 AMD_CG_STATE_GATE);
564ea790
SJ		 1815 /* XXX: check for errors */
1816 }
1817 cz_update_uvd_dpm(adev, gate);
1818 }
1819}
1820
b7a07769
SJ		 1821static int cz_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1822{
1823 struct cz_power_info *pi = cz_get_pi(adev);
1824 int ret = 0;
1825
1826 if (enable && pi->caps_vce_dpm) {
1827 pi->dpm_flags |= DPMFlags_VCE_Enabled;
1828 DRM_DEBUG("VCE DPM Enabled.\n");
1829
1830 ret = cz_send_msg_to_smc_with_parameter(adev,
1831 PPSMC_MSG_EnableAllSmuFeatures, VCE_DPM_MASK);
1832
1833 } else {
1834 pi->dpm_flags &= ~DPMFlags_VCE_Enabled;
1835 DRM_DEBUG("VCE DPM Stopped\n");
1836
1837 ret = cz_send_msg_to_smc_with_parameter(adev,
1838 PPSMC_MSG_DisableAllSmuFeatures, VCE_DPM_MASK);
1839 }
1840
1841 return ret;
1842}
1843
1844static int cz_update_vce_dpm(struct amdgpu_device *adev)
1845{
1846 struct cz_power_info *pi = cz_get_pi(adev);
1847 struct amdgpu_vce_clock_voltage_dependency_table *table =
1848 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1849
1850 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1851 if (pi->caps_stable_power_state) {
1852 pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk;
1853
1854 } else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */
1855 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
1856 }
1857
1858 cz_send_msg_to_smc_with_parameter(adev,
1859 PPSMC_MSG_SetEclkHardMin,
1860 cz_get_eclk_level(adev,
1861 pi->vce_dpm.hard_min_clk,
1862 PPSMC_MSG_SetEclkHardMin));
1863 return 0;
1864}
1865
1866static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1867{
1868 struct cz_power_info *pi = cz_get_pi(adev);
1869
1870 if (pi->caps_vce_pg) {
1871 if (pi->vce_power_gated != gate) {
1872 if (gate) {
1873 /* disable clockgating so we can properly shut down the block */
1874 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1875 AMD_CG_STATE_UNGATE);
1876 /* shutdown the VCE block */
1877 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1878 AMD_PG_STATE_GATE);
1879
1880 cz_enable_vce_dpm(adev, false);
1881 /* TODO: to figure out why vce can't be poweroff. */
1882 /* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */
1883 pi->vce_power_gated = true;
1884 } else {
1885 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
1886 pi->vce_power_gated = false;
1887
1888 /* re-init the VCE block */
1889 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1890 AMD_PG_STATE_UNGATE);
1891 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1892 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1893 AMD_CG_STATE_GATE);
1894
1895 cz_update_vce_dpm(adev);
1896 cz_enable_vce_dpm(adev, true);
1897 }
1898 } else {
1899 if (! pi->vce_power_gated) {
1900 cz_update_vce_dpm(adev);
1901 }
1902 }
1903 } else { /*pi->caps_vce_pg*/
1904 cz_update_vce_dpm(adev);
1905 cz_enable_vce_dpm(adev, true);
1906 }
1907
1908 return;
1909}
1910
5fc3aeeb 1911const struct amd_ip_funcs cz_dpm_ip_funcs = {
aaa36a97 1912 .early_init = cz_dpm_early_init,
564ea790 1913 .late_init = cz_dpm_late_init,
aaa36a97
AD		 1914 .sw_init = cz_dpm_sw_init,
1915 .sw_fini = cz_dpm_sw_fini,
1916 .hw_init = cz_dpm_hw_init,
1917 .hw_fini = cz_dpm_hw_fini,
1918 .suspend = cz_dpm_suspend,
1919 .resume = cz_dpm_resume,
1920 .is_idle = NULL,
1921 .wait_for_idle = NULL,
1922 .soft_reset = NULL,
1923 .print_status = NULL,
1924 .set_clockgating_state = cz_dpm_set_clockgating_state,
1925 .set_powergating_state = cz_dpm_set_powergating_state,
1926};
1927
1928static const struct amdgpu_dpm_funcs cz_dpm_funcs = {
1929 .get_temperature = cz_dpm_get_temperature,
1930 .pre_set_power_state = cz_dpm_pre_set_power_state,
1931 .set_power_state = cz_dpm_set_power_state,
1932 .post_set_power_state = cz_dpm_post_set_power_state,
1933 .display_configuration_changed = cz_dpm_display_configuration_changed,
1934 .get_sclk = cz_dpm_get_sclk,
1935 .get_mclk = cz_dpm_get_mclk,
1936 .print_power_state = cz_dpm_print_power_state,
1937 .debugfs_print_current_performance_level =
1938 cz_dpm_debugfs_print_current_performance_level,
1939 .force_performance_level = cz_dpm_force_dpm_level,
1940 .vblank_too_short = NULL,
564ea790 1941 .powergate_uvd = cz_dpm_powergate_uvd,
b7a07769 1942 .powergate_vce = cz_dpm_powergate_vce,
aaa36a97
AD		 1943};
1944
1945static void cz_dpm_set_funcs(struct amdgpu_device *adev)
1946{
1947 if (NULL == adev->pm.funcs)
1948 adev->pm.funcs = &cz_dpm_funcs;
1949}
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