[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / cz_ih.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "drmP.h"
#include "amdgpu.h"
#include "amdgpu_ih.h"
#include "vid.h"

#include "oss/oss_3_0_1_d.h"
#include "oss/oss_3_0_1_sh_mask.h"

#include "bif/bif_5_1_d.h"
#include "bif/bif_5_1_sh_mask.h"

/*
 * Interrupts
 * Starting with r6xx, interrupts are handled via a ring buffer.
 * Ring buffers are areas of GPU accessible memory that the GPU
 * writes interrupt vectors into and the host reads vectors out of.
 * There is a rptr (read pointer) that determines where the
 * host is currently reading, and a wptr (write pointer)
 * which determines where the GPU has written.  When the
 * pointers are equal, the ring is idle.  When the GPU
 * writes vectors to the ring buffer, it increments the
 * wptr.  When there is an interrupt, the host then starts
 * fetching commands and processing them until the pointers are
 * equal again at which point it updates the rptr.
 */

static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev);

/**
 * cz_ih_enable_interrupts - Enable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Enable the interrupt ring buffer (VI).
 */
static void cz_ih_enable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_cntl = RREG32(mmIH_CNTL);
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
	WREG32(mmIH_CNTL, ih_cntl);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	adev->irq.ih.enabled = true;
}

/**
 * cz_ih_disable_interrupts - Disable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Disable the interrupt ring buffer (VI).
 */
static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	u32 ih_cntl = RREG32(mmIH_CNTL);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	WREG32(mmIH_CNTL, ih_cntl);
	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);
	adev->irq.ih.enabled = false;
	adev->irq.ih.rptr = 0;
}

/**
 * cz_ih_irq_init - init and enable the interrupt ring
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate a ring buffer for the interrupt controller,
 * enable the RLC, disable interrupts, enable the IH
 * ring buffer and enable it (VI).
 * Called at device load and reume.
 * Returns 0 for success, errors for failure.
 */
static int cz_ih_irq_init(struct amdgpu_device *adev)
{
	int rb_bufsz;
	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
	u64 wptr_off;

	/* disable irqs */
	cz_ih_disable_interrupts(adev);

	/* setup interrupt control */
	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	 */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);

	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

	/* set the writeback address whether it's enabled or not */
	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

	WREG32(mmIH_RB_CNTL, ih_rb_cntl);

	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);

	/* Default settings for IH_CNTL (disabled at first) */
	ih_cntl = RREG32(mmIH_CNTL);
	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);

	if (adev->irq.msi_enabled)
		ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
	WREG32(mmIH_CNTL, ih_cntl);

	pci_set_master(adev->pdev);

	/* enable interrupts */
	cz_ih_enable_interrupts(adev);

	return 0;
}

/**
 * cz_ih_irq_disable - disable interrupts
 *
 * @adev: amdgpu_device pointer
 *
 * Disable interrupts on the hw (VI).
 */
static void cz_ih_irq_disable(struct amdgpu_device *adev)
{
	cz_ih_disable_interrupts(adev);

	/* Wait and acknowledge irq */
	mdelay(1);
}

/**
 * cz_ih_get_wptr - get the IH ring buffer wptr
 *
 * @adev: amdgpu_device pointer
 *
 * Get the IH ring buffer wptr from either the register
 * or the writeback memory buffer (VI).  Also check for
 * ring buffer overflow and deal with it.
 * Used by cz_irq_process(VI).
 * Returns the value of the wptr.
 */
static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
{
	u32 wptr, tmp;

	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);

	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
		/* When a ring buffer overflow happen start parsing interrupt
		 * from the last not overwritten vector (wptr + 16). Hopefully
		 * this should allow us to catchup.
		 */
		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
		tmp = RREG32(mmIH_RB_CNTL);
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
		WREG32(mmIH_RB_CNTL, tmp);
	}
	return (wptr & adev->irq.ih.ptr_mask);
}

/**
 * cz_ih_decode_iv - decode an interrupt vector
 *
 * @adev: amdgpu_device pointer
 *
 * Decodes the interrupt vector at the current rptr
 * position and also advance the position.
 */
static void cz_ih_decode_iv(struct amdgpu_device *adev,
				 struct amdgpu_iv_entry *entry)
{
	/* wptr/rptr are in bytes! */
	u32 ring_index = adev->irq.ih.rptr >> 2;
	uint32_t dw[4];

	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);

	entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
	entry->src_id = dw[0] & 0xff;
	entry->src_data[0] = dw[1] & 0xfffffff;
	entry->ring_id = dw[2] & 0xff;
	entry->vm_id = (dw[2] >> 8) & 0xff;
	entry->pas_id = (dw[2] >> 16) & 0xffff;

	/* wptr/rptr are in bytes! */
	adev->irq.ih.rptr += 16;
}

/**
 * cz_ih_set_rptr - set the IH ring buffer rptr
 *
 * @adev: amdgpu_device pointer
 *
 * Set the IH ring buffer rptr.
 */
static void cz_ih_set_rptr(struct amdgpu_device *adev)
{
	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
}

static int cz_ih_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int ret;

	ret = amdgpu_irq_add_domain(adev);
	if (ret)
		return ret;

	cz_ih_set_interrupt_funcs(adev);

	return 0;
}

static int cz_ih_sw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
	if (r)
		return r;

	r = amdgpu_irq_init(adev);

	return r;
}

static int cz_ih_sw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	amdgpu_irq_fini(adev);
	amdgpu_ih_ring_fini(adev);
	amdgpu_irq_remove_domain(adev);

	return 0;
}

static int cz_ih_hw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = cz_ih_irq_init(adev);
	if (r)
		return r;

	return 0;
}

static int cz_ih_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	cz_ih_irq_disable(adev);

	return 0;
}

static int cz_ih_suspend(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return cz_ih_hw_fini(adev);
}

static int cz_ih_resume(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return cz_ih_hw_init(adev);
}

static bool cz_ih_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
		return false;

	return true;
}

static int cz_ih_wait_for_idle(void *handle)
{
	unsigned i;
	u32 tmp;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	for (i = 0; i < adev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(mmSRBM_STATUS);
		if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
			return 0;
		udelay(1);
	}
	return -ETIMEDOUT;
}

static int cz_ih_soft_reset(void *handle)
{
	u32 srbm_soft_reset = 0;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
						SOFT_RESET_IH, 1);

	if (srbm_soft_reset) {
		tmp = RREG32(mmSRBM_SOFT_RESET);
		tmp |= srbm_soft_reset;
		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		udelay(50);

		tmp &= ~srbm_soft_reset;
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		/* Wait a little for things to settle down */
		udelay(50);
	}

	return 0;
}

static int cz_ih_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	// TODO
	return 0;
}

static int cz_ih_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	// TODO
	return 0;
}

static const struct amd_ip_funcs cz_ih_ip_funcs = {
	.name = "cz_ih",
	.early_init = cz_ih_early_init,
	.late_init = NULL,
	.sw_init = cz_ih_sw_init,
	.sw_fini = cz_ih_sw_fini,
	.hw_init = cz_ih_hw_init,
	.hw_fini = cz_ih_hw_fini,
	.suspend = cz_ih_suspend,
	.resume = cz_ih_resume,
	.is_idle = cz_ih_is_idle,
	.wait_for_idle = cz_ih_wait_for_idle,
	.soft_reset = cz_ih_soft_reset,
	.set_clockgating_state = cz_ih_set_clockgating_state,
	.set_powergating_state = cz_ih_set_powergating_state,
};

static const struct amdgpu_ih_funcs cz_ih_funcs = {
	.get_wptr = cz_ih_get_wptr,
	.decode_iv = cz_ih_decode_iv,
	.set_rptr = cz_ih_set_rptr
};

static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
	if (adev->irq.ih_funcs == NULL)
		adev->irq.ih_funcs = &cz_ih_funcs;
}

const struct amdgpu_ip_block_version cz_ih_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_IH,
	.major = 3,
	.minor = 0,
	.rev = 0,
	.funcs = &cz_ih_ip_funcs,
};
Commit	Line	Data
aaa36a97 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "drmP.h"
	24	#include "amdgpu.h"
	25	#include "amdgpu_ih.h"
	26	#include "vid.h"
	27
	28	#include "oss/oss_3_0_1_d.h"
	29	#include "oss/oss_3_0_1_sh_mask.h"
	30
	31	#include "bif/bif_5_1_d.h"
	32	#include "bif/bif_5_1_sh_mask.h"
	33
	34	/*
	35	* Interrupts
	36	* Starting with r6xx, interrupts are handled via a ring buffer.
	37	* Ring buffers are areas of GPU accessible memory that the GPU
	38	* writes interrupt vectors into and the host reads vectors out of.
	39	* There is a rptr (read pointer) that determines where the
	40	* host is currently reading, and a wptr (write pointer)
	41	* which determines where the GPU has written. When the
	42	* pointers are equal, the ring is idle. When the GPU
	43	* writes vectors to the ring buffer, it increments the
	44	* wptr. When there is an interrupt, the host then starts
	45	* fetching commands and processing them until the pointers are
	46	* equal again at which point it updates the rptr.
	47	*/
	48
	49	static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev);
	50
	51	/**
	52	* cz_ih_enable_interrupts - Enable the interrupt ring buffer
	53	*
	54	* @adev: amdgpu_device pointer
	55	*
	56	* Enable the interrupt ring buffer (VI).
	57	*/
	58	static void cz_ih_enable_interrupts(struct amdgpu_device *adev)
	59	{
	60	u32 ih_cntl = RREG32(mmIH_CNTL);
	61	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	62
	63	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
	64	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
65	WREG32(mmIH_CNTL, ih_cntl);
66	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
67	adev->irq.ih.enabled = true;
68	}
69
70	/**
71	* cz_ih_disable_interrupts - Disable the interrupt ring buffer
72	*
73	* @adev: amdgpu_device pointer
74	*
75	* Disable the interrupt ring buffer (VI).
76	*/
77	static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
78	{
79	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
80	u32 ih_cntl = RREG32(mmIH_CNTL);
81
82	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
83	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
84	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
85	WREG32(mmIH_CNTL, ih_cntl);
86	/* set rptr, wptr to 0 */
87	WREG32(mmIH_RB_RPTR, 0);
88	WREG32(mmIH_RB_WPTR, 0);
89	adev->irq.ih.enabled = false;
90	adev->irq.ih.rptr = 0;
91	}
92
93	/**
94	* cz_ih_irq_init - init and enable the interrupt ring
95	*
96	* @adev: amdgpu_device pointer
97	*
98	* Allocate a ring buffer for the interrupt controller,
99	* enable the RLC, disable interrupts, enable the IH
100	* ring buffer and enable it (VI).
101	* Called at device load and reume.
102	* Returns 0 for success, errors for failure.
103	*/
104	static int cz_ih_irq_init(struct amdgpu_device *adev)
105	{
aaa36a97 AD	106	int rb_bufsz;
	107	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
	108	u64 wptr_off;
	109
	110	/* disable irqs */
	111	cz_ih_disable_interrupts(adev);
	112
	113	/* setup interrupt control */
	114	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
	115	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	116	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	117	* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	118	*/
	119	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	120	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	121	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	122	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
	123
	124	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
	125	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
	126
	127	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
	128	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
	129	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	130	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
	131
	132	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
	133	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
	134
	135	/* set the writeback address whether it's enabled or not */
	136	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
	137	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
	138	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
	139
	140	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	141
	142	/* set rptr, wptr to 0 */
	143	WREG32(mmIH_RB_RPTR, 0);
	144	WREG32(mmIH_RB_WPTR, 0);
	145
	146	/* Default settings for IH_CNTL (disabled at first) */
	147	ih_cntl = RREG32(mmIH_CNTL);
	148	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
	149
	150	if (adev->irq.msi_enabled)
	151	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
	152	WREG32(mmIH_CNTL, ih_cntl);
	153
	154	pci_set_master(adev->pdev);
	155
	156	/* enable interrupts */
	157	cz_ih_enable_interrupts(adev);
	158
0e2b854e	159	return 0;
aaa36a97 AD	160	}
	161
	162	/**
	163	* cz_ih_irq_disable - disable interrupts
	164	*
	165	* @adev: amdgpu_device pointer
	166	*
	167	* Disable interrupts on the hw (VI).
	168	*/
	169	static void cz_ih_irq_disable(struct amdgpu_device *adev)
	170	{
	171	cz_ih_disable_interrupts(adev);
	172
	173	/* Wait and acknowledge irq */
	174	mdelay(1);
	175	}
	176
	177	/**
	178	* cz_ih_get_wptr - get the IH ring buffer wptr
	179	*
	180	* @adev: amdgpu_device pointer
	181	*
	182	* Get the IH ring buffer wptr from either the register
	183	* or the writeback memory buffer (VI). Also check for
	184	* ring buffer overflow and deal with it.
	185	* Used by cz_irq_process(VI).
	186	* Returns the value of the wptr.
	187	*/
	188	static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
	189	{
	190	u32 wptr, tmp;
	191
	192	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
	193
	194	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
	195	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
	196	/* When a ring buffer overflow happen start parsing interrupt
	197	* from the last not overwritten vector (wptr + 16). Hopefully
	198	* this should allow us to catchup.
	199	*/
	200	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
	201	wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
	202	adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
	203	tmp = RREG32(mmIH_RB_CNTL);
	204	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	205	WREG32(mmIH_RB_CNTL, tmp);
	206	}
	207	return (wptr & adev->irq.ih.ptr_mask);
	208	}
	209
	210	/**
	211	* cz_ih_decode_iv - decode an interrupt vector
	212	*
	213	* @adev: amdgpu_device pointer
	214	*
	215	* Decodes the interrupt vector at the current rptr
	216	* position and also advance the position.
	217	*/
	218	static void cz_ih_decode_iv(struct amdgpu_device *adev,
	219	struct amdgpu_iv_entry *entry)
	220	{
	221	/* wptr/rptr are in bytes! */
	222	u32 ring_index = adev->irq.ih.rptr >> 2;
	223	uint32_t dw[4];
edf600da	224
aaa36a97 AD	225	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
	226	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
	227	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
	228	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
	229
d766e6a3	230	entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
aaa36a97	231	entry->src_id = dw[0] & 0xff;
7ccf5aa8	232	entry->src_data[0] = dw[1] & 0xfffffff;
aaa36a97 AD	233	entry->ring_id = dw[2] & 0xff;
	234	entry->vm_id = (dw[2] >> 8) & 0xff;
	235	entry->pas_id = (dw[2] >> 16) & 0xffff;
	236
	237	/* wptr/rptr are in bytes! */
	238	adev->irq.ih.rptr += 16;
	239	}
	240
	241	/**
	242	* cz_ih_set_rptr - set the IH ring buffer rptr
	243	*
	244	* @adev: amdgpu_device pointer
	245	*
	246	* Set the IH ring buffer rptr.
	247	*/
	248	static void cz_ih_set_rptr(struct amdgpu_device *adev)
	249	{
	250	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
	251	}
	252
5fc3aeeb	253	static int cz_ih_early_init(void *handle)
aaa36a97	254	{
5fc3aeeb	255	struct amdgpu_device adev = (struct amdgpu_device )handle;
5f232365 AD	256	int ret;
	257
	258	ret = amdgpu_irq_add_domain(adev);
	259	if (ret)
	260	return ret;
5fc3aeeb	261
aaa36a97	262	cz_ih_set_interrupt_funcs(adev);
5f232365	263
aaa36a97 AD	264	return 0;
	265	}
	266
5fc3aeeb	267	static int cz_ih_sw_init(void *handle)
aaa36a97 AD	268	{
aaa36a97 AD	269	int r;
5fc3aeeb	270	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	271
	272	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
	273	if (r)
	274	return r;
	275
	276	r = amdgpu_irq_init(adev);
	277
	278	return r;
	279	}
	280
5fc3aeeb	281	static int cz_ih_sw_fini(void *handle)
aaa36a97	282	{
5fc3aeeb	283	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	284
aaa36a97 AD	285	amdgpu_irq_fini(adev);
aaa36a97 AD	286	amdgpu_ih_ring_fini(adev);
5f232365	287	amdgpu_irq_remove_domain(adev);
aaa36a97 AD	288
	289	return 0;
	290	}
	291
5fc3aeeb	292	static int cz_ih_hw_init(void *handle)
aaa36a97 AD	293	{
aaa36a97 AD	294	int r;
5fc3aeeb	295	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	296
	297	r = cz_ih_irq_init(adev);
	298	if (r)
	299	return r;
	300
	301	return 0;
	302	}
	303
5fc3aeeb	304	static int cz_ih_hw_fini(void *handle)
aaa36a97	305	{
5fc3aeeb	306	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	307
aaa36a97 AD	308	cz_ih_irq_disable(adev);
	309
	310	return 0;
	311	}
	312
5fc3aeeb	313	static int cz_ih_suspend(void *handle)
aaa36a97	314	{
5fc3aeeb	315	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	316
aaa36a97 AD	317	return cz_ih_hw_fini(adev);
	318	}
	319
5fc3aeeb	320	static int cz_ih_resume(void *handle)
aaa36a97	321	{
5fc3aeeb	322	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	323
aaa36a97 AD	324	return cz_ih_hw_init(adev);
	325	}
	326
5fc3aeeb	327	static bool cz_ih_is_idle(void *handle)
aaa36a97	328	{
5fc3aeeb	329	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	330	u32 tmp = RREG32(mmSRBM_STATUS);
	331
	332	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	333	return false;
	334
	335	return true;
	336	}
	337
5fc3aeeb	338	static int cz_ih_wait_for_idle(void *handle)
aaa36a97 AD	339	{
	340	unsigned i;
	341	u32 tmp;
5fc3aeeb	342	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	343
	344	for (i = 0; i < adev->usec_timeout; i++) {
	345	/* read MC_STATUS */
	346	tmp = RREG32(mmSRBM_STATUS);
	347	if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	348	return 0;
	349	udelay(1);
	350	}
	351	return -ETIMEDOUT;
	352	}
	353
5fc3aeeb	354	static int cz_ih_soft_reset(void *handle)
aaa36a97 AD	355	{
aaa36a97 AD	356	u32 srbm_soft_reset = 0;
5fc3aeeb	357	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	358	u32 tmp = RREG32(mmSRBM_STATUS);
	359
	360	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
	361	srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
	362	SOFT_RESET_IH, 1);
	363
	364	if (srbm_soft_reset) {
aaa36a97 AD	365	tmp = RREG32(mmSRBM_SOFT_RESET);
	366	tmp \|= srbm_soft_reset;
	367	dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
	368	WREG32(mmSRBM_SOFT_RESET, tmp);
	369	tmp = RREG32(mmSRBM_SOFT_RESET);
	370
	371	udelay(50);
	372
	373	tmp &= ~srbm_soft_reset;
	374	WREG32(mmSRBM_SOFT_RESET, tmp);
	375	tmp = RREG32(mmSRBM_SOFT_RESET);
	376
	377	/* Wait a little for things to settle down */
	378	udelay(50);
aaa36a97 AD	379	}
	380
	381	return 0;
	382	}
	383
5fc3aeeb	384	static int cz_ih_set_clockgating_state(void *handle,
5fc3aeeb	385	enum amd_clockgating_state state)
aaa36a97 AD	386	{
	387	// TODO
	388	return 0;
	389	}
	390
5fc3aeeb	391	static int cz_ih_set_powergating_state(void *handle,
5fc3aeeb	392	enum amd_powergating_state state)
aaa36a97 AD	393	{
	394	// TODO
	395	return 0;
	396	}
	397
a1255107	398	static const struct amd_ip_funcs cz_ih_ip_funcs = {
88a907d6	399	.name = "cz_ih",
aaa36a97 AD	400	.early_init = cz_ih_early_init,
	401	.late_init = NULL,
	402	.sw_init = cz_ih_sw_init,
	403	.sw_fini = cz_ih_sw_fini,
	404	.hw_init = cz_ih_hw_init,
	405	.hw_fini = cz_ih_hw_fini,
	406	.suspend = cz_ih_suspend,
	407	.resume = cz_ih_resume,
	408	.is_idle = cz_ih_is_idle,
	409	.wait_for_idle = cz_ih_wait_for_idle,
	410	.soft_reset = cz_ih_soft_reset,
aaa36a97 AD	411	.set_clockgating_state = cz_ih_set_clockgating_state,
	412	.set_powergating_state = cz_ih_set_powergating_state,
	413	};
	414
	415	static const struct amdgpu_ih_funcs cz_ih_funcs = {
	416	.get_wptr = cz_ih_get_wptr,
	417	.decode_iv = cz_ih_decode_iv,
	418	.set_rptr = cz_ih_set_rptr
	419	};
	420
	421	static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
	422	{
	423	if (adev->irq.ih_funcs == NULL)
	424	adev->irq.ih_funcs = &cz_ih_funcs;
	425	}
	426
a1255107 AD	427	const struct amdgpu_ip_block_version cz_ih_ip_block =
	428	{
	429	.type = AMD_IP_BLOCK_TYPE_IH,
	430	.major = 3,
	431	.minor = 0,
	432	.rev = 0,
	433	.funcs = &cz_ih_ip_funcs,
	434	};