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Merge tag 'trace-v4.10-rc2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rosted...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / dce_v11_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
356aee30 34#include "dce_v11_0.h"
aaa36a97
AD		 35
36#include "dce/dce_11_0_d.h"
37#include "dce/dce_11_0_sh_mask.h"
38#include "dce/dce_11_0_enum.h"
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41#include "gmc/gmc_8_1_d.h"
42#include "gmc/gmc_8_1_sh_mask.h"
43
44static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
45static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
46
47static const u32 crtc_offsets[] =
48{
49 CRTC0_REGISTER_OFFSET,
50 CRTC1_REGISTER_OFFSET,
51 CRTC2_REGISTER_OFFSET,
52 CRTC3_REGISTER_OFFSET,
53 CRTC4_REGISTER_OFFSET,
54 CRTC5_REGISTER_OFFSET,
55 CRTC6_REGISTER_OFFSET
56};
57
58static const u32 hpd_offsets[] =
59{
60 HPD0_REGISTER_OFFSET,
61 HPD1_REGISTER_OFFSET,
62 HPD2_REGISTER_OFFSET,
63 HPD3_REGISTER_OFFSET,
64 HPD4_REGISTER_OFFSET,
65 HPD5_REGISTER_OFFSET
66};
67
68static const uint32_t dig_offsets[] = {
69 DIG0_REGISTER_OFFSET,
70 DIG1_REGISTER_OFFSET,
71 DIG2_REGISTER_OFFSET,
72 DIG3_REGISTER_OFFSET,
73 DIG4_REGISTER_OFFSET,
74 DIG5_REGISTER_OFFSET,
75 DIG6_REGISTER_OFFSET,
76 DIG7_REGISTER_OFFSET,
77 DIG8_REGISTER_OFFSET
78};
79
80static const struct {
81 uint32_t reg;
82 uint32_t vblank;
83 uint32_t vline;
84 uint32_t hpd;
85
86} interrupt_status_offsets[] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91}, {
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96}, {
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101}, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106}, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111}, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
116} };
117
118static const u32 cz_golden_settings_a11[] =
119{
120 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
121 mmFBC_MISC, 0x1f311fff, 0x14300000,
122};
123
5732a94f
AD		 124static const u32 cz_mgcg_cgcg_init[] =
125{
126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
128};
129
fa2f9bef
SL		 130static const u32 stoney_golden_settings_a11[] =
131{
132 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
133 mmFBC_MISC, 0x1f311fff, 0x14302000,
134};
135
2cc0c0b5 136static const u32 polaris11_golden_settings_a11[] =
60909285
FC		 137{
138 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
139 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
140 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
b9934878 141 mmFBC_MISC, 0x9f313fff, 0x14302008,
60909285
FC		 142 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
143};
144
2cc0c0b5 145static const u32 polaris10_golden_settings_a11[] =
60909285
FC		 146{
147 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
148 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
d4ab989f 149 mmFBC_MISC, 0x9f313fff, 0x14302008,
60909285
FC		 150 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
151};
fa2f9bef 152
aaa36a97
AD		 153static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
154{
155 switch (adev->asic_type) {
156 case CHIP_CARRIZO:
5732a94f
AD		 157 amdgpu_program_register_sequence(adev,
158 cz_mgcg_cgcg_init,
159 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
aaa36a97
AD		 160 amdgpu_program_register_sequence(adev,
161 cz_golden_settings_a11,
162 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
163 break;
fa2f9bef
SL		 164 case CHIP_STONEY:
165 amdgpu_program_register_sequence(adev,
166 stoney_golden_settings_a11,
167 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
168 break;
2cc0c0b5 169 case CHIP_POLARIS11:
c4642a47 170 case CHIP_POLARIS12:
60909285 171 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 172 polaris11_golden_settings_a11,
173 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
60909285 174 break;
2cc0c0b5 175 case CHIP_POLARIS10:
60909285 176 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 177 polaris10_golden_settings_a11,
178 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
60909285 179 break;
aaa36a97
AD		 180 default:
181 break;
182 }
183}
184
185static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
186 u32 block_offset, u32 reg)
187{
188 unsigned long flags;
189 u32 r;
190
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
195
196 return r;
197}
198
199static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
200 u32 block_offset, u32 reg, u32 v)
201{
202 unsigned long flags;
203
204 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
205 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
206 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
207 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
208}
209
210static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
211{
212 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
213 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
214 return true;
215 else
216 return false;
217}
218
219static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
220{
221 u32 pos1, pos2;
222
223 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
224 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
225
226 if (pos1 != pos2)
227 return true;
228 else
229 return false;
230}
231
232/**
233 * dce_v11_0_vblank_wait - vblank wait asic callback.
234 *
235 * @adev: amdgpu_device pointer
236 * @crtc: crtc to wait for vblank on
237 *
238 * Wait for vblank on the requested crtc (evergreen+).
239 */
240static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
241{
9e4e1ae8 242 unsigned i = 100;
aaa36a97 243
15c3277f 244 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
aaa36a97
AD		 245 return;
246
247 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
248 return;
249
250 /* depending on when we hit vblank, we may be close to active; if so,
251 * wait for another frame.
252 */
253 while (dce_v11_0_is_in_vblank(adev, crtc)) {
9e4e1ae8
TSD		 254 if (i++ == 100) {
255 i = 0;
aaa36a97
AD		 256 if (!dce_v11_0_is_counter_moving(adev, crtc))
257 break;
258 }
259 }
260
261 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
9e4e1ae8
TSD		 262 if (i++ == 100) {
263 i = 0;
aaa36a97
AD		 264 if (!dce_v11_0_is_counter_moving(adev, crtc))
265 break;
266 }
267 }
268}
269
270static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
271{
15c3277f 272 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
aaa36a97
AD		 273 return 0;
274 else
275 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
276}
277
f6c7aba4
MD		 278static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
279{
280 unsigned i;
281
282 /* Enable pflip interrupts */
283 for (i = 0; i < adev->mode_info.num_crtc; i++)
284 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
285}
286
287static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
288{
289 unsigned i;
290
291 /* Disable pflip interrupts */
292 for (i = 0; i < adev->mode_info.num_crtc; i++)
293 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
294}
295
aaa36a97
AD		 296/**
297 * dce_v11_0_page_flip - pageflip callback.
298 *
299 * @adev: amdgpu_device pointer
300 * @crtc_id: crtc to cleanup pageflip on
301 * @crtc_base: new address of the crtc (GPU MC address)
302 *
ce055fe3
AD		 303 * Triggers the actual pageflip by updating the primary
304 * surface base address.
aaa36a97
AD		 305 */
306static void dce_v11_0_page_flip(struct amdgpu_device *adev,
cb9e59d7 307 int crtc_id, u64 crtc_base, bool async)
aaa36a97
AD		 308{
309 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
cb9e59d7 310 u32 tmp;
aaa36a97 311
7359ee63 312 /* flip immediate for async, default is vsync */
cb9e59d7
AD		 313 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
314 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
7359ee63 315 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
cb9e59d7 316 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
aaa36a97 317 /* update the scanout addresses */
aaa36a97
AD		 318 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
319 upper_32_bits(crtc_base));
ce055fe3 320 /* writing to the low address triggers the update */
aaa36a97
AD		 321 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
322 lower_32_bits(crtc_base));
ce055fe3
AD		 323 /* post the write */
324 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
aaa36a97
AD		 325}
326
327static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
328 u32 *vbl, u32 *position)
329{
330 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
331 return -EINVAL;
332
333 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
334 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
335
336 return 0;
337}
338
339/**
340 * dce_v11_0_hpd_sense - hpd sense callback.
341 *
342 * @adev: amdgpu_device pointer
343 * @hpd: hpd (hotplug detect) pin
344 *
345 * Checks if a digital monitor is connected (evergreen+).
346 * Returns true if connected, false if not connected.
347 */
348static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
349 enum amdgpu_hpd_id hpd)
350{
aaa36a97
AD		 351 bool connected = false;
352
d2486d25 353 if (hpd >= adev->mode_info.num_hpd)
aaa36a97 354 return connected;
aaa36a97 355
d2486d25 356 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
aaa36a97
AD		 357 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
358 connected = true;
359
360 return connected;
361}
362
363/**
364 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
365 *
366 * @adev: amdgpu_device pointer
367 * @hpd: hpd (hotplug detect) pin
368 *
369 * Set the polarity of the hpd pin (evergreen+).
370 */
371static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
372 enum amdgpu_hpd_id hpd)
373{
374 u32 tmp;
375 bool connected = dce_v11_0_hpd_sense(adev, hpd);
aaa36a97 376
d2486d25 377 if (hpd >= adev->mode_info.num_hpd)
aaa36a97 378 return;
aaa36a97 379
d2486d25 380 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
aaa36a97
AD		 381 if (connected)
382 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
383 else
384 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
d2486d25 385 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
aaa36a97
AD		 386}
387
388/**
389 * dce_v11_0_hpd_init - hpd setup callback.
390 *
391 * @adev: amdgpu_device pointer
392 *
393 * Setup the hpd pins used by the card (evergreen+).
394 * Enable the pin, set the polarity, and enable the hpd interrupts.
395 */
396static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
397{
398 struct drm_device *dev = adev->ddev;
399 struct drm_connector *connector;
400 u32 tmp;
aaa36a97
AD		 401
402 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
403 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
404
d2486d25 405 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
aaa36a97 406 continue;
aaa36a97 407
3a9d993e
AD		 408 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
409 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
410 /* don't try to enable hpd on eDP or LVDS avoid breaking the
411 * aux dp channel on imac and help (but not completely fix)
412 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
413 * also avoid interrupt storms during dpms.
414 */
d2486d25 415 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
3a9d993e 416 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
d2486d25 417 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
3a9d993e
AD		 418 continue;
419 }
420
d2486d25 421 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
aaa36a97 422 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
d2486d25 423 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
aaa36a97 424
d2486d25 425 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
aaa36a97
AD		 426 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
427 DC_HPD_CONNECT_INT_DELAY,
428 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
429 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
430 DC_HPD_DISCONNECT_INT_DELAY,
431 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
d2486d25 432 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
aaa36a97
AD		 433
434 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
435 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
436 }
437}
438
439/**
440 * dce_v11_0_hpd_fini - hpd tear down callback.
441 *
442 * @adev: amdgpu_device pointer
443 *
444 * Tear down the hpd pins used by the card (evergreen+).
445 * Disable the hpd interrupts.
446 */
447static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
448{
449 struct drm_device *dev = adev->ddev;
450 struct drm_connector *connector;
451 u32 tmp;
aaa36a97
AD		 452
453 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
454 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
455
d2486d25 456 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
aaa36a97 457 continue;
aaa36a97 458
d2486d25 459 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
aaa36a97 460 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
d2486d25 461 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
aaa36a97
AD		 462
463 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
464 }
465}
466
467static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
468{
469 return mmDC_GPIO_HPD_A;
470}
471
472static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
473{
474 u32 crtc_hung = 0;
475 u32 crtc_status[6];
476 u32 i, j, tmp;
477
478 for (i = 0; i < adev->mode_info.num_crtc; i++) {
479 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
480 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
481 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
482 crtc_hung |= (1 << i);
483 }
484 }
485
486 for (j = 0; j < 10; j++) {
487 for (i = 0; i < adev->mode_info.num_crtc; i++) {
488 if (crtc_hung & (1 << i)) {
489 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
490 if (tmp != crtc_status[i])
491 crtc_hung &= ~(1 << i);
492 }
493 }
494 if (crtc_hung == 0)
495 return false;
496 udelay(100);
497 }
498
499 return true;
500}
501
502static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
503 struct amdgpu_mode_mc_save *save)
504{
505 u32 crtc_enabled, tmp;
506 int i;
507
508 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
509 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
510
511 /* disable VGA render */
512 tmp = RREG32(mmVGA_RENDER_CONTROL);
513 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
514 WREG32(mmVGA_RENDER_CONTROL, tmp);
515
516 /* blank the display controllers */
517 for (i = 0; i < adev->mode_info.num_crtc; i++) {
518 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
519 CRTC_CONTROL, CRTC_MASTER_EN);
520 if (crtc_enabled) {
01c02a8b 521#if 1
aaa36a97
AD		 522 save->crtc_enabled[i] = true;
523 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
524 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
01c02a8b
VP		 525 /*it is correct only for RGB ; black is 0*/
526 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
aaa36a97
AD		 527 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
528 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
aaa36a97
AD		 529 }
530#else
531 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
532 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
533 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
534 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
535 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
536 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
537 save->crtc_enabled[i] = false;
538 /* ***** */
539#endif
540 } else {
541 save->crtc_enabled[i] = false;
542 }
543 }
544}
545
546static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
547 struct amdgpu_mode_mc_save *save)
548{
01c02a8b
VP		 549 u32 tmp;
550 int i;
aaa36a97
AD		 551
552 /* update crtc base addresses */
553 for (i = 0; i < adev->mode_info.num_crtc; i++) {
554 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
555 upper_32_bits(adev->mc.vram_start));
aaa36a97
AD		 556 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
557 (u32)adev->mc.vram_start);
aaa36a97
AD		 558
559 if (save->crtc_enabled[i]) {
aaa36a97
AD		 560 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
561 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
aaa36a97 562 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
aaa36a97
AD		 563 }
564 }
565
566 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
567 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
568
569 /* Unlock vga access */
570 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
571 mdelay(1);
572 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
573}
574
575static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
576 bool render)
577{
578 u32 tmp;
579
580 /* Lockout access through VGA aperture*/
581 tmp = RREG32(mmVGA_HDP_CONTROL);
582 if (render)
583 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
584 else
585 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
586 WREG32(mmVGA_HDP_CONTROL, tmp);
587
588 /* disable VGA render */
589 tmp = RREG32(mmVGA_RENDER_CONTROL);
590 if (render)
591 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
592 else
593 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
594 WREG32(mmVGA_RENDER_CONTROL, tmp);
595}
596
83c9b025
ED		 597static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
598{
599 int num_crtc = 0;
600
601 switch (adev->asic_type) {
602 case CHIP_CARRIZO:
603 num_crtc = 3;
604 break;
605 case CHIP_STONEY:
606 num_crtc = 2;
607 break;
608 case CHIP_POLARIS10:
609 num_crtc = 6;
610 break;
611 case CHIP_POLARIS11:
c4642a47 612 case CHIP_POLARIS12:
83c9b025
ED		 613 num_crtc = 5;
614 break;
615 default:
616 num_crtc = 0;
617 }
618 return num_crtc;
619}
620
621void dce_v11_0_disable_dce(struct amdgpu_device *adev)
622{
623 /*Disable VGA render and enabled crtc, if has DCE engine*/
624 if (amdgpu_atombios_has_dce_engine_info(adev)) {
625 u32 tmp;
626 int crtc_enabled, i;
627
628 dce_v11_0_set_vga_render_state(adev, false);
629
630 /*Disable crtc*/
631 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
632 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
633 CRTC_CONTROL, CRTC_MASTER_EN);
634 if (crtc_enabled) {
635 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
636 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
637 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
638 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
639 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
640 }
641 }
642 }
643}
644
aaa36a97
AD		 645static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
646{
647 struct drm_device *dev = encoder->dev;
648 struct amdgpu_device *adev = dev->dev_private;
649 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
650 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
651 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
652 int bpc = 0;
653 u32 tmp = 0;
654 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
655
656 if (connector) {
657 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
658 bpc = amdgpu_connector_get_monitor_bpc(connector);
659 dither = amdgpu_connector->dither;
660 }
661
662 /* LVDS/eDP FMT is set up by atom */
663 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
664 return;
665
666 /* not needed for analog */
667 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
668 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
669 return;
670
671 if (bpc == 0)
672 return;
673
674 switch (bpc) {
675 case 6:
676 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
677 /* XXX sort out optimal dither settings */
678 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
679 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
680 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
681 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
682 } else {
683 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
684 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
685 }
686 break;
687 case 8:
688 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
689 /* XXX sort out optimal dither settings */
690 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
691 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
692 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
693 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
694 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
695 } else {
696 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
697 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
698 }
699 break;
700 case 10:
701 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
702 /* XXX sort out optimal dither settings */
703 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
704 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
705 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
706 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
707 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
708 } else {
709 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
710 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
711 }
712 break;
713 default:
714 /* not needed */
715 break;
716 }
717
718 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
719}
720
721
722/* display watermark setup */
723/**
724 * dce_v11_0_line_buffer_adjust - Set up the line buffer
725 *
726 * @adev: amdgpu_device pointer
727 * @amdgpu_crtc: the selected display controller
728 * @mode: the current display mode on the selected display
729 * controller
730 *
731 * Setup up the line buffer allocation for
732 * the selected display controller (CIK).
733 * Returns the line buffer size in pixels.
734 */
735static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
736 struct amdgpu_crtc *amdgpu_crtc,
737 struct drm_display_mode *mode)
738{
739 u32 tmp, buffer_alloc, i, mem_cfg;
740 u32 pipe_offset = amdgpu_crtc->crtc_id;
741 /*
742 * Line Buffer Setup
743 * There are 6 line buffers, one for each display controllers.
744 * There are 3 partitions per LB. Select the number of partitions
745 * to enable based on the display width. For display widths larger
746 * than 4096, you need use to use 2 display controllers and combine
747 * them using the stereo blender.
748 */
749 if (amdgpu_crtc->base.enabled && mode) {
750 if (mode->crtc_hdisplay < 1920) {
751 mem_cfg = 1;
752 buffer_alloc = 2;
753 } else if (mode->crtc_hdisplay < 2560) {
754 mem_cfg = 2;
755 buffer_alloc = 2;
756 } else if (mode->crtc_hdisplay < 4096) {
757 mem_cfg = 0;
2f7d10b3 758 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
aaa36a97
AD		 759 } else {
760 DRM_DEBUG_KMS("Mode too big for LB!\n");
761 mem_cfg = 0;
2f7d10b3 762 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
aaa36a97
AD		 763 }
764 } else {
765 mem_cfg = 1;
766 buffer_alloc = 0;
767 }
768
769 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
770 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
771 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
772
773 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
774 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
775 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
776
777 for (i = 0; i < adev->usec_timeout; i++) {
778 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
779 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
780 break;
781 udelay(1);
782 }
783
784 if (amdgpu_crtc->base.enabled && mode) {
785 switch (mem_cfg) {
786 case 0:
787 default:
788 return 4096 * 2;
789 case 1:
790 return 1920 * 2;
791 case 2:
792 return 2560 * 2;
793 }
794 }
795
796 /* controller not enabled, so no lb used */
797 return 0;
798}
799
800/**
801 * cik_get_number_of_dram_channels - get the number of dram channels
802 *
803 * @adev: amdgpu_device pointer
804 *
805 * Look up the number of video ram channels (CIK).
806 * Used for display watermark bandwidth calculations
807 * Returns the number of dram channels
808 */
809static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
810{
811 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
812
813 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
814 case 0:
815 default:
816 return 1;
817 case 1:
818 return 2;
819 case 2:
820 return 4;
821 case 3:
822 return 8;
823 case 4:
824 return 3;
825 case 5:
826 return 6;
827 case 6:
828 return 10;
829 case 7:
830 return 12;
831 case 8:
832 return 16;
833 }
834}
835
836struct dce10_wm_params {
837 u32 dram_channels; /* number of dram channels */
838 u32 yclk; /* bandwidth per dram data pin in kHz */
839 u32 sclk; /* engine clock in kHz */
840 u32 disp_clk; /* display clock in kHz */
841 u32 src_width; /* viewport width */
842 u32 active_time; /* active display time in ns */
843 u32 blank_time; /* blank time in ns */
844 bool interlaced; /* mode is interlaced */
845 fixed20_12 vsc; /* vertical scale ratio */
846 u32 num_heads; /* number of active crtcs */
847 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
848 u32 lb_size; /* line buffer allocated to pipe */
849 u32 vtaps; /* vertical scaler taps */
850};
851
852/**
853 * dce_v11_0_dram_bandwidth - get the dram bandwidth
854 *
855 * @wm: watermark calculation data
856 *
857 * Calculate the raw dram bandwidth (CIK).
858 * Used for display watermark bandwidth calculations
859 * Returns the dram bandwidth in MBytes/s
860 */
861static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
862{
863 /* Calculate raw DRAM Bandwidth */
864 fixed20_12 dram_efficiency; /* 0.7 */
865 fixed20_12 yclk, dram_channels, bandwidth;
866 fixed20_12 a;
867
868 a.full = dfixed_const(1000);
869 yclk.full = dfixed_const(wm->yclk);
870 yclk.full = dfixed_div(yclk, a);
871 dram_channels.full = dfixed_const(wm->dram_channels * 4);
872 a.full = dfixed_const(10);
873 dram_efficiency.full = dfixed_const(7);
874 dram_efficiency.full = dfixed_div(dram_efficiency, a);
875 bandwidth.full = dfixed_mul(dram_channels, yclk);
876 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
877
878 return dfixed_trunc(bandwidth);
879}
880
881/**
882 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
883 *
884 * @wm: watermark calculation data
885 *
886 * Calculate the dram bandwidth used for display (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the dram bandwidth for display in MBytes/s
889 */
890static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
891{
892 /* Calculate DRAM Bandwidth and the part allocated to display. */
893 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
894 fixed20_12 yclk, dram_channels, bandwidth;
895 fixed20_12 a;
896
897 a.full = dfixed_const(1000);
898 yclk.full = dfixed_const(wm->yclk);
899 yclk.full = dfixed_div(yclk, a);
900 dram_channels.full = dfixed_const(wm->dram_channels * 4);
901 a.full = dfixed_const(10);
902 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
903 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
904 bandwidth.full = dfixed_mul(dram_channels, yclk);
905 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
906
907 return dfixed_trunc(bandwidth);
908}
909
910/**
911 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
912 *
913 * @wm: watermark calculation data
914 *
915 * Calculate the data return bandwidth used for display (CIK).
916 * Used for display watermark bandwidth calculations
917 * Returns the data return bandwidth in MBytes/s
918 */
919static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
920{
921 /* Calculate the display Data return Bandwidth */
922 fixed20_12 return_efficiency; /* 0.8 */
923 fixed20_12 sclk, bandwidth;
924 fixed20_12 a;
925
926 a.full = dfixed_const(1000);
927 sclk.full = dfixed_const(wm->sclk);
928 sclk.full = dfixed_div(sclk, a);
929 a.full = dfixed_const(10);
930 return_efficiency.full = dfixed_const(8);
931 return_efficiency.full = dfixed_div(return_efficiency, a);
932 a.full = dfixed_const(32);
933 bandwidth.full = dfixed_mul(a, sclk);
934 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
935
936 return dfixed_trunc(bandwidth);
937}
938
939/**
940 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
941 *
942 * @wm: watermark calculation data
943 *
944 * Calculate the dmif bandwidth used for display (CIK).
945 * Used for display watermark bandwidth calculations
946 * Returns the dmif bandwidth in MBytes/s
947 */
948static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
949{
950 /* Calculate the DMIF Request Bandwidth */
951 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
952 fixed20_12 disp_clk, bandwidth;
953 fixed20_12 a, b;
954
955 a.full = dfixed_const(1000);
956 disp_clk.full = dfixed_const(wm->disp_clk);
957 disp_clk.full = dfixed_div(disp_clk, a);
958 a.full = dfixed_const(32);
959 b.full = dfixed_mul(a, disp_clk);
960
961 a.full = dfixed_const(10);
962 disp_clk_request_efficiency.full = dfixed_const(8);
963 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
964
965 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
966
967 return dfixed_trunc(bandwidth);
968}
969
970/**
971 * dce_v11_0_available_bandwidth - get the min available bandwidth
972 *
973 * @wm: watermark calculation data
974 *
975 * Calculate the min available bandwidth used for display (CIK).
976 * Used for display watermark bandwidth calculations
977 * Returns the min available bandwidth in MBytes/s
978 */
979static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
980{
981 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
982 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
983 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
984 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
985
986 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
987}
988
989/**
990 * dce_v11_0_average_bandwidth - get the average available bandwidth
991 *
992 * @wm: watermark calculation data
993 *
994 * Calculate the average available bandwidth used for display (CIK).
995 * Used for display watermark bandwidth calculations
996 * Returns the average available bandwidth in MBytes/s
997 */
998static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
999{
1000 /* Calculate the display mode Average Bandwidth
1001 * DisplayMode should contain the source and destination dimensions,
1002 * timing, etc.
1003 */
1004 fixed20_12 bpp;
1005 fixed20_12 line_time;
1006 fixed20_12 src_width;
1007 fixed20_12 bandwidth;
1008 fixed20_12 a;
1009
1010 a.full = dfixed_const(1000);
1011 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1012 line_time.full = dfixed_div(line_time, a);
1013 bpp.full = dfixed_const(wm->bytes_per_pixel);
1014 src_width.full = dfixed_const(wm->src_width);
1015 bandwidth.full = dfixed_mul(src_width, bpp);
1016 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1017 bandwidth.full = dfixed_div(bandwidth, line_time);
1018
1019 return dfixed_trunc(bandwidth);
1020}
1021
1022/**
1023 * dce_v11_0_latency_watermark - get the latency watermark
1024 *
1025 * @wm: watermark calculation data
1026 *
1027 * Calculate the latency watermark (CIK).
1028 * Used for display watermark bandwidth calculations
1029 * Returns the latency watermark in ns
1030 */
1031static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1032{
1033 /* First calculate the latency in ns */
1034 u32 mc_latency = 2000; /* 2000 ns. */
1035 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1036 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1037 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1038 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1039 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1040 (wm->num_heads * cursor_line_pair_return_time);
1041 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1042 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1043 u32 tmp, dmif_size = 12288;
1044 fixed20_12 a, b, c;
1045
1046 if (wm->num_heads == 0)
1047 return 0;
1048
1049 a.full = dfixed_const(2);
1050 b.full = dfixed_const(1);
1051 if ((wm->vsc.full > a.full) ||
1052 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1053 (wm->vtaps >= 5) ||
1054 ((wm->vsc.full >= a.full) && wm->interlaced))
1055 max_src_lines_per_dst_line = 4;
1056 else
1057 max_src_lines_per_dst_line = 2;
1058
1059 a.full = dfixed_const(available_bandwidth);
1060 b.full = dfixed_const(wm->num_heads);
1061 a.full = dfixed_div(a, b);
1062
1063 b.full = dfixed_const(mc_latency + 512);
1064 c.full = dfixed_const(wm->disp_clk);
1065 b.full = dfixed_div(b, c);
1066
1067 c.full = dfixed_const(dmif_size);
1068 b.full = dfixed_div(c, b);
1069
1070 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1071
1072 b.full = dfixed_const(1000);
1073 c.full = dfixed_const(wm->disp_clk);
1074 b.full = dfixed_div(c, b);
1075 c.full = dfixed_const(wm->bytes_per_pixel);
1076 b.full = dfixed_mul(b, c);
1077
1078 lb_fill_bw = min(tmp, dfixed_trunc(b));
1079
1080 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1081 b.full = dfixed_const(1000);
1082 c.full = dfixed_const(lb_fill_bw);
1083 b.full = dfixed_div(c, b);
1084 a.full = dfixed_div(a, b);
1085 line_fill_time = dfixed_trunc(a);
1086
1087 if (line_fill_time < wm->active_time)
1088 return latency;
1089 else
1090 return latency + (line_fill_time - wm->active_time);
1091
1092}
1093
1094/**
1095 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1096 * average and available dram bandwidth
1097 *
1098 * @wm: watermark calculation data
1099 *
1100 * Check if the display average bandwidth fits in the display
1101 * dram bandwidth (CIK).
1102 * Used for display watermark bandwidth calculations
1103 * Returns true if the display fits, false if not.
1104 */
1105static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1106{
1107 if (dce_v11_0_average_bandwidth(wm) <=
1108 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1109 return true;
1110 else
1111 return false;
1112}
1113
1114/**
1115 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1116 * average and available bandwidth
1117 *
1118 * @wm: watermark calculation data
1119 *
1120 * Check if the display average bandwidth fits in the display
1121 * available bandwidth (CIK).
1122 * Used for display watermark bandwidth calculations
1123 * Returns true if the display fits, false if not.
1124 */
1125static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1126{
1127 if (dce_v11_0_average_bandwidth(wm) <=
1128 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1129 return true;
1130 else
1131 return false;
1132}
1133
1134/**
1135 * dce_v11_0_check_latency_hiding - check latency hiding
1136 *
1137 * @wm: watermark calculation data
1138 *
1139 * Check latency hiding (CIK).
1140 * Used for display watermark bandwidth calculations
1141 * Returns true if the display fits, false if not.
1142 */
1143static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1144{
1145 u32 lb_partitions = wm->lb_size / wm->src_width;
1146 u32 line_time = wm->active_time + wm->blank_time;
1147 u32 latency_tolerant_lines;
1148 u32 latency_hiding;
1149 fixed20_12 a;
1150
1151 a.full = dfixed_const(1);
1152 if (wm->vsc.full > a.full)
1153 latency_tolerant_lines = 1;
1154 else {
1155 if (lb_partitions <= (wm->vtaps + 1))
1156 latency_tolerant_lines = 1;
1157 else
1158 latency_tolerant_lines = 2;
1159 }
1160
1161 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1162
1163 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1164 return true;
1165 else
1166 return false;
1167}
1168
1169/**
1170 * dce_v11_0_program_watermarks - program display watermarks
1171 *
1172 * @adev: amdgpu_device pointer
1173 * @amdgpu_crtc: the selected display controller
1174 * @lb_size: line buffer size
1175 * @num_heads: number of display controllers in use
1176 *
1177 * Calculate and program the display watermarks for the
1178 * selected display controller (CIK).
1179 */
1180static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1181 struct amdgpu_crtc *amdgpu_crtc,
1182 u32 lb_size, u32 num_heads)
1183{
1184 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1185 struct dce10_wm_params wm_low, wm_high;
1186 u32 pixel_period;
1187 u32 line_time = 0;
1188 u32 latency_watermark_a = 0, latency_watermark_b = 0;
8e36f9d3 1189 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
aaa36a97
AD		 1190
1191 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1192 pixel_period = 1000000 / (u32)mode->clock;
1193 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1194
1195 /* watermark for high clocks */
1196 if (adev->pm.dpm_enabled) {
1197 wm_high.yclk =
1198 amdgpu_dpm_get_mclk(adev, false) * 10;
1199 wm_high.sclk =
1200 amdgpu_dpm_get_sclk(adev, false) * 10;
1201 } else {
1202 wm_high.yclk = adev->pm.current_mclk * 10;
1203 wm_high.sclk = adev->pm.current_sclk * 10;
1204 }
1205
1206 wm_high.disp_clk = mode->clock;
1207 wm_high.src_width = mode->crtc_hdisplay;
1208 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1209 wm_high.blank_time = line_time - wm_high.active_time;
1210 wm_high.interlaced = false;
1211 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1212 wm_high.interlaced = true;
1213 wm_high.vsc = amdgpu_crtc->vsc;
1214 wm_high.vtaps = 1;
1215 if (amdgpu_crtc->rmx_type != RMX_OFF)
1216 wm_high.vtaps = 2;
1217 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1218 wm_high.lb_size = lb_size;
1219 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1220 wm_high.num_heads = num_heads;
1221
1222 /* set for high clocks */
1223 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1224
1225 /* possibly force display priority to high */
1226 /* should really do this at mode validation time... */
1227 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1228 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1229 !dce_v11_0_check_latency_hiding(&wm_high) ||
1230 (adev->mode_info.disp_priority == 2)) {
1231 DRM_DEBUG_KMS("force priority to high\n");
1232 }
1233
1234 /* watermark for low clocks */
1235 if (adev->pm.dpm_enabled) {
1236 wm_low.yclk =
1237 amdgpu_dpm_get_mclk(adev, true) * 10;
1238 wm_low.sclk =
1239 amdgpu_dpm_get_sclk(adev, true) * 10;
1240 } else {
1241 wm_low.yclk = adev->pm.current_mclk * 10;
1242 wm_low.sclk = adev->pm.current_sclk * 10;
1243 }
1244
1245 wm_low.disp_clk = mode->clock;
1246 wm_low.src_width = mode->crtc_hdisplay;
1247 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1248 wm_low.blank_time = line_time - wm_low.active_time;
1249 wm_low.interlaced = false;
1250 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1251 wm_low.interlaced = true;
1252 wm_low.vsc = amdgpu_crtc->vsc;
1253 wm_low.vtaps = 1;
1254 if (amdgpu_crtc->rmx_type != RMX_OFF)
1255 wm_low.vtaps = 2;
1256 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1257 wm_low.lb_size = lb_size;
1258 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1259 wm_low.num_heads = num_heads;
1260
1261 /* set for low clocks */
1262 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1263
1264 /* possibly force display priority to high */
1265 /* should really do this at mode validation time... */
1266 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1267 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1268 !dce_v11_0_check_latency_hiding(&wm_low) ||
1269 (adev->mode_info.disp_priority == 2)) {
1270 DRM_DEBUG_KMS("force priority to high\n");
1271 }
8e36f9d3 1272 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
aaa36a97
AD		 1273 }
1274
1275 /* select wm A */
1276 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1277 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1278 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1279 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1280 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1281 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1282 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1283 /* select wm B */
1284 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1285 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1286 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
99a09238 1287 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
aaa36a97
AD		 1288 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1289 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1290 /* restore original selection */
1291 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1292
1293 /* save values for DPM */
1294 amdgpu_crtc->line_time = line_time;
1295 amdgpu_crtc->wm_high = latency_watermark_a;
1296 amdgpu_crtc->wm_low = latency_watermark_b;
8e36f9d3
AD		 1297 /* Save number of lines the linebuffer leads before the scanout */
1298 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
aaa36a97
AD		 1299}
1300
1301/**
1302 * dce_v11_0_bandwidth_update - program display watermarks
1303 *
1304 * @adev: amdgpu_device pointer
1305 *
1306 * Calculate and program the display watermarks and line
1307 * buffer allocation (CIK).
1308 */
1309static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1310{
1311 struct drm_display_mode *mode = NULL;
1312 u32 num_heads = 0, lb_size;
1313 int i;
1314
1315 amdgpu_update_display_priority(adev);
1316
1317 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1318 if (adev->mode_info.crtcs[i]->base.enabled)
1319 num_heads++;
1320 }
1321 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1322 mode = &adev->mode_info.crtcs[i]->base.mode;
1323 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1324 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1325 lb_size, num_heads);
1326 }
1327}
1328
1329static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1330{
1331 int i;
1332 u32 offset, tmp;
1333
1334 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1335 offset = adev->mode_info.audio.pin[i].offset;
1336 tmp = RREG32_AUDIO_ENDPT(offset,
1337 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1338 if (((tmp &
1339 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1340 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1341 adev->mode_info.audio.pin[i].connected = false;
1342 else
1343 adev->mode_info.audio.pin[i].connected = true;
1344 }
1345}
1346
1347static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1348{
1349 int i;
1350
1351 dce_v11_0_audio_get_connected_pins(adev);
1352
1353 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1354 if (adev->mode_info.audio.pin[i].connected)
1355 return &adev->mode_info.audio.pin[i];
1356 }
1357 DRM_ERROR("No connected audio pins found!\n");
1358 return NULL;
1359}
1360
1361static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1362{
1363 struct amdgpu_device *adev = encoder->dev->dev_private;
1364 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1365 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1366 u32 tmp;
1367
1368 if (!dig || !dig->afmt || !dig->afmt->pin)
1369 return;
1370
1371 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1372 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1373 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1374}
1375
1376static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1377 struct drm_display_mode *mode)
1378{
1379 struct amdgpu_device *adev = encoder->dev->dev_private;
1380 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1381 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1382 struct drm_connector *connector;
1383 struct amdgpu_connector *amdgpu_connector = NULL;
1384 u32 tmp;
1385 int interlace = 0;
1386
1387 if (!dig || !dig->afmt || !dig->afmt->pin)
1388 return;
1389
1390 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1391 if (connector->encoder == encoder) {
1392 amdgpu_connector = to_amdgpu_connector(connector);
1393 break;
1394 }
1395 }
1396
1397 if (!amdgpu_connector) {
1398 DRM_ERROR("Couldn't find encoder's connector\n");
1399 return;
1400 }
1401
1402 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1403 interlace = 1;
1404 if (connector->latency_present[interlace]) {
1405 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1406 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1407 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1408 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1409 } else {
1410 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1411 VIDEO_LIPSYNC, 0);
1412 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1413 AUDIO_LIPSYNC, 0);
1414 }
1415 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1416 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1417}
1418
1419static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1420{
1421 struct amdgpu_device *adev = encoder->dev->dev_private;
1422 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1423 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1424 struct drm_connector *connector;
1425 struct amdgpu_connector *amdgpu_connector = NULL;
1426 u32 tmp;
1427 u8 *sadb = NULL;
1428 int sad_count;
1429
1430 if (!dig || !dig->afmt || !dig->afmt->pin)
1431 return;
1432
1433 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1434 if (connector->encoder == encoder) {
1435 amdgpu_connector = to_amdgpu_connector(connector);
1436 break;
1437 }
1438 }
1439
1440 if (!amdgpu_connector) {
1441 DRM_ERROR("Couldn't find encoder's connector\n");
1442 return;
1443 }
1444
1445 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1446 if (sad_count < 0) {
1447 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1448 sad_count = 0;
1449 }
1450
1451 /* program the speaker allocation */
1452 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1453 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1454 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1455 DP_CONNECTION, 0);
1456 /* set HDMI mode */
1457 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1458 HDMI_CONNECTION, 1);
1459 if (sad_count)
1460 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1461 SPEAKER_ALLOCATION, sadb[0]);
1462 else
1463 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1464 SPEAKER_ALLOCATION, 5); /* stereo */
1465 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1466 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1467
1468 kfree(sadb);
1469}
1470
1471static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1472{
1473 struct amdgpu_device *adev = encoder->dev->dev_private;
1474 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1475 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1476 struct drm_connector *connector;
1477 struct amdgpu_connector *amdgpu_connector = NULL;
1478 struct cea_sad *sads;
1479 int i, sad_count;
1480
1481 static const u16 eld_reg_to_type[][2] = {
1482 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1483 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1484 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1485 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1486 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1487 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1488 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1489 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1490 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1491 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1492 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1493 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1494 };
1495
1496 if (!dig || !dig->afmt || !dig->afmt->pin)
1497 return;
1498
1499 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1500 if (connector->encoder == encoder) {
1501 amdgpu_connector = to_amdgpu_connector(connector);
1502 break;
1503 }
1504 }
1505
1506 if (!amdgpu_connector) {
1507 DRM_ERROR("Couldn't find encoder's connector\n");
1508 return;
1509 }
1510
1511 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1512 if (sad_count <= 0) {
1513 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1514 return;
1515 }
1516 BUG_ON(!sads);
1517
1518 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1519 u32 tmp = 0;
1520 u8 stereo_freqs = 0;
1521 int max_channels = -1;
1522 int j;
1523
1524 for (j = 0; j < sad_count; j++) {
1525 struct cea_sad *sad = &sads[j];
1526
1527 if (sad->format == eld_reg_to_type[i][1]) {
1528 if (sad->channels > max_channels) {
1529 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1530 MAX_CHANNELS, sad->channels);
1531 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1532 DESCRIPTOR_BYTE_2, sad->byte2);
1533 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1534 SUPPORTED_FREQUENCIES, sad->freq);
1535 max_channels = sad->channels;
1536 }
1537
1538 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1539 stereo_freqs |= sad->freq;
1540 else
1541 break;
1542 }
1543 }
1544
1545 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1546 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1547 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1548 }
1549
1550 kfree(sads);
1551}
1552
1553static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1554 struct amdgpu_audio_pin *pin,
1555 bool enable)
1556{
1557 if (!pin)
1558 return;
1559
1560 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1561 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1562}
1563
1564static const u32 pin_offsets[] =
1565{
1566 AUD0_REGISTER_OFFSET,
1567 AUD1_REGISTER_OFFSET,
1568 AUD2_REGISTER_OFFSET,
1569 AUD3_REGISTER_OFFSET,
1570 AUD4_REGISTER_OFFSET,
1571 AUD5_REGISTER_OFFSET,
1572 AUD6_REGISTER_OFFSET,
67b1fcc9 1573 AUD7_REGISTER_OFFSET,
aaa36a97
AD		 1574};
1575
1576static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1577{
1578 int i;
1579
1580 if (!amdgpu_audio)
1581 return 0;
1582
1583 adev->mode_info.audio.enabled = true;
1584
d525eb8d
AD		 1585 switch (adev->asic_type) {
1586 case CHIP_CARRIZO:
1587 case CHIP_STONEY:
1588 adev->mode_info.audio.num_pins = 7;
1589 break;
2cc0c0b5 1590 case CHIP_POLARIS10:
d525eb8d
AD		 1591 adev->mode_info.audio.num_pins = 8;
1592 break;
2cc0c0b5 1593 case CHIP_POLARIS11:
c4642a47 1594 case CHIP_POLARIS12:
d525eb8d
AD		 1595 adev->mode_info.audio.num_pins = 6;
1596 break;
1597 default:
1598 return -EINVAL;
1599 }
aaa36a97
AD		 1600
1601 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1602 adev->mode_info.audio.pin[i].channels = -1;
1603 adev->mode_info.audio.pin[i].rate = -1;
1604 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1605 adev->mode_info.audio.pin[i].status_bits = 0;
1606 adev->mode_info.audio.pin[i].category_code = 0;
1607 adev->mode_info.audio.pin[i].connected = false;
1608 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1609 adev->mode_info.audio.pin[i].id = i;
1610 /* disable audio. it will be set up later */
1611 /* XXX remove once we switch to ip funcs */
1612 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1613 }
1614
1615 return 0;
1616}
1617
1618static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1619{
1620 int i;
1621
29f646df
TSD		 1622 if (!amdgpu_audio)
1623 return;
1624
aaa36a97
AD		 1625 if (!adev->mode_info.audio.enabled)
1626 return;
1627
1628 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1629 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1630
1631 adev->mode_info.audio.enabled = false;
1632}
1633
1634/*
1635 * update the N and CTS parameters for a given pixel clock rate
1636 */
1637static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1638{
1639 struct drm_device *dev = encoder->dev;
1640 struct amdgpu_device *adev = dev->dev_private;
1641 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1642 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1643 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1644 u32 tmp;
1645
1646 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1647 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1648 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1649 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1650 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1651 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1652
1653 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1654 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1655 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1656 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1657 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1658 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1659
1660 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1661 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1662 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1663 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1664 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1665 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1666
1667}
1668
1669/*
1670 * build a HDMI Video Info Frame
1671 */
1672static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1673 void *buffer, size_t size)
1674{
1675 struct drm_device *dev = encoder->dev;
1676 struct amdgpu_device *adev = dev->dev_private;
1677 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1678 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1679 uint8_t *frame = buffer + 3;
1680 uint8_t *header = buffer;
1681
1682 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1683 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1684 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1685 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1686 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1687 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1688 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1689 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1690}
1691
1692static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1693{
1694 struct drm_device *dev = encoder->dev;
1695 struct amdgpu_device *adev = dev->dev_private;
1696 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1697 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1698 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1699 u32 dto_phase = 24 * 1000;
1700 u32 dto_modulo = clock;
1701 u32 tmp;
1702
1703 if (!dig || !dig->afmt)
1704 return;
1705
1706 /* XXX two dtos; generally use dto0 for hdmi */
1707 /* Express [24MHz / target pixel clock] as an exact rational
1708 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1709 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1710 */
1711 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1712 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1713 amdgpu_crtc->crtc_id);
1714 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1715 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1716 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1717}
1718
1719/*
1720 * update the info frames with the data from the current display mode
1721 */
1722static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1723 struct drm_display_mode *mode)
1724{
1725 struct drm_device *dev = encoder->dev;
1726 struct amdgpu_device *adev = dev->dev_private;
1727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1728 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1729 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1730 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1731 struct hdmi_avi_infoframe frame;
1732 ssize_t err;
1733 u32 tmp;
1734 int bpc = 8;
1735
1736 if (!dig || !dig->afmt)
1737 return;
1738
1739 /* Silent, r600_hdmi_enable will raise WARN for us */
1740 if (!dig->afmt->enabled)
1741 return;
1742
1743 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1744 if (encoder->crtc) {
1745 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1746 bpc = amdgpu_crtc->bpc;
1747 }
1748
1749 /* disable audio prior to setting up hw */
1750 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1751 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1752
1753 dce_v11_0_audio_set_dto(encoder, mode->clock);
1754
1755 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1756 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1757 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1758
1759 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1760
1761 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1762 switch (bpc) {
1763 case 0:
1764 case 6:
1765 case 8:
1766 case 16:
1767 default:
1768 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1769 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1770 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1771 connector->name, bpc);
1772 break;
1773 case 10:
1774 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1775 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1776 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1777 connector->name);
1778 break;
1779 case 12:
1780 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1781 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1782 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1783 connector->name);
1784 break;
1785 }
1786 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1787
1788 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1789 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1790 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1791 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1792 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1793
1794 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1795 /* enable audio info frames (frames won't be set until audio is enabled) */
1796 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1797 /* required for audio info values to be updated */
1798 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1799 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1800
1801 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1802 /* required for audio info values to be updated */
1803 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1804 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1805
1806 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1807 /* anything other than 0 */
1808 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1809 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1810
1811 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1812
1813 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1814 /* set the default audio delay */
1815 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1816 /* should be suffient for all audio modes and small enough for all hblanks */
1817 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1818 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1819
1820 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1821 /* allow 60958 channel status fields to be updated */
1822 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1823 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1824
1825 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1826 if (bpc > 8)
1827 /* clear SW CTS value */
1828 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1829 else
1830 /* select SW CTS value */
1831 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1832 /* allow hw to sent ACR packets when required */
1833 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1834 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1835
1836 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1837
1838 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1839 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1840 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1841
1842 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1843 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1844 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1845
1846 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1847 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1848 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1849 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1850 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1851 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1852 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1853 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1854
1855 dce_v11_0_audio_write_speaker_allocation(encoder);
1856
1857 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1858 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1859
1860 dce_v11_0_afmt_audio_select_pin(encoder);
1861 dce_v11_0_audio_write_sad_regs(encoder);
1862 dce_v11_0_audio_write_latency_fields(encoder, mode);
1863
1864 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1865 if (err < 0) {
1866 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1867 return;
1868 }
1869
1870 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1871 if (err < 0) {
1872 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1873 return;
1874 }
1875
1876 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1877
1878 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1879 /* enable AVI info frames */
1880 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1881 /* required for audio info values to be updated */
1882 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1883 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1884
1885 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1886 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1887 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1888
1889 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1890 /* send audio packets */
1891 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1892 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1893
1894 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1895 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1896 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1897 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1898
1899 /* enable audio after to setting up hw */
1900 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1901}
1902
1903static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1904{
1905 struct drm_device *dev = encoder->dev;
1906 struct amdgpu_device *adev = dev->dev_private;
1907 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1908 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1909
1910 if (!dig || !dig->afmt)
1911 return;
1912
1913 /* Silent, r600_hdmi_enable will raise WARN for us */
1914 if (enable && dig->afmt->enabled)
1915 return;
1916 if (!enable && !dig->afmt->enabled)
1917 return;
1918
1919 if (!enable && dig->afmt->pin) {
1920 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1921 dig->afmt->pin = NULL;
1922 }
1923
1924 dig->afmt->enabled = enable;
1925
1926 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1927 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1928}
1929
041ab0a4 1930static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
aaa36a97
AD		 1931{
1932 int i;
1933
1934 for (i = 0; i < adev->mode_info.num_dig; i++)
1935 adev->mode_info.afmt[i] = NULL;
1936
1937 /* DCE11 has audio blocks tied to DIG encoders */
1938 for (i = 0; i < adev->mode_info.num_dig; i++) {
1939 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1940 if (adev->mode_info.afmt[i]) {
1941 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1942 adev->mode_info.afmt[i]->id = i;
041ab0a4
TSD		 1943 } else {
1944 int j;
1945 for (j = 0; j < i; j++) {
1946 kfree(adev->mode_info.afmt[j]);
1947 adev->mode_info.afmt[j] = NULL;
1948 }
1949 return -ENOMEM;
aaa36a97
AD		 1950 }
1951 }
041ab0a4 1952 return 0;
aaa36a97
AD		 1953}
1954
1955static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1956{
1957 int i;
1958
1959 for (i = 0; i < adev->mode_info.num_dig; i++) {
1960 kfree(adev->mode_info.afmt[i]);
1961 adev->mode_info.afmt[i] = NULL;
1962 }
1963}
1964
1965static const u32 vga_control_regs[6] =
1966{
1967 mmD1VGA_CONTROL,
1968 mmD2VGA_CONTROL,
1969 mmD3VGA_CONTROL,
1970 mmD4VGA_CONTROL,
1971 mmD5VGA_CONTROL,
1972 mmD6VGA_CONTROL,
1973};
1974
1975static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1976{
1977 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1978 struct drm_device *dev = crtc->dev;
1979 struct amdgpu_device *adev = dev->dev_private;
1980 u32 vga_control;
1981
1982 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1983 if (enable)
1984 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1985 else
1986 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1987}
1988
1989static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1990{
1991 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1992 struct drm_device *dev = crtc->dev;
1993 struct amdgpu_device *adev = dev->dev_private;
1994
1995 if (enable)
1996 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1997 else
1998 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1999}
2000
aaa36a97
AD		 2001static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2002 struct drm_framebuffer *fb,
2003 int x, int y, int atomic)
2004{
2005 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2006 struct drm_device *dev = crtc->dev;
2007 struct amdgpu_device *adev = dev->dev_private;
2008 struct amdgpu_framebuffer *amdgpu_fb;
2009 struct drm_framebuffer *target_fb;
2010 struct drm_gem_object *obj;
765e7fbf 2011 struct amdgpu_bo *abo;
aaa36a97
AD		 2012 uint64_t fb_location, tiling_flags;
2013 uint32_t fb_format, fb_pitch_pixels;
aaa36a97 2014 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
fbd76d59 2015 u32 pipe_config;
aaa36a97
AD		 2016 u32 tmp, viewport_w, viewport_h;
2017 int r;
2018 bool bypass_lut = false;
b3c11ac2 2019 struct drm_format_name_buf format_name;
aaa36a97
AD		 2020
2021 /* no fb bound */
2022 if (!atomic && !crtc->primary->fb) {
2023 DRM_DEBUG_KMS("No FB bound\n");
2024 return 0;
2025 }
2026
2027 if (atomic) {
2028 amdgpu_fb = to_amdgpu_framebuffer(fb);
2029 target_fb = fb;
e484f8d4 2030 } else {
aaa36a97
AD		 2031 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2032 target_fb = crtc->primary->fb;
2033 }
2034
2035 /* If atomic, assume fb object is pinned & idle & fenced and
2036 * just update base pointers
2037 */
2038 obj = amdgpu_fb->obj;
765e7fbf
CK		 2039 abo = gem_to_amdgpu_bo(obj);
2040 r = amdgpu_bo_reserve(abo, false);
aaa36a97
AD		 2041 if (unlikely(r != 0))
2042 return r;
2043
e484f8d4 2044 if (atomic) {
765e7fbf 2045 fb_location = amdgpu_bo_gpu_offset(abo);
e484f8d4 2046 } else {
765e7fbf 2047 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
aaa36a97 2048 if (unlikely(r != 0)) {
765e7fbf 2049 amdgpu_bo_unreserve(abo);
aaa36a97
AD		 2050 return -EINVAL;
2051 }
2052 }
2053
765e7fbf
CK		 2054 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2055 amdgpu_bo_unreserve(abo);
aaa36a97 2056
fbd76d59
MO		 2057 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2058
aaa36a97
AD		 2059 switch (target_fb->pixel_format) {
2060 case DRM_FORMAT_C8:
2061 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2062 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2063 break;
2064 case DRM_FORMAT_XRGB4444:
2065 case DRM_FORMAT_ARGB4444:
2066 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2067 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2068#ifdef __BIG_ENDIAN
2069 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2070 ENDIAN_8IN16);
2071#endif
2072 break;
2073 case DRM_FORMAT_XRGB1555:
2074 case DRM_FORMAT_ARGB1555:
2075 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2076 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2077#ifdef __BIG_ENDIAN
2078 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2079 ENDIAN_8IN16);
2080#endif
2081 break;
2082 case DRM_FORMAT_BGRX5551:
2083 case DRM_FORMAT_BGRA5551:
2084 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2085 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2086#ifdef __BIG_ENDIAN
2087 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2088 ENDIAN_8IN16);
2089#endif
2090 break;
2091 case DRM_FORMAT_RGB565:
2092 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2093 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2094#ifdef __BIG_ENDIAN
2095 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2096 ENDIAN_8IN16);
2097#endif
2098 break;
2099 case DRM_FORMAT_XRGB8888:
2100 case DRM_FORMAT_ARGB8888:
2101 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2102 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2103#ifdef __BIG_ENDIAN
2104 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2105 ENDIAN_8IN32);
2106#endif
2107 break;
2108 case DRM_FORMAT_XRGB2101010:
2109 case DRM_FORMAT_ARGB2101010:
2110 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2111 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2112#ifdef __BIG_ENDIAN
2113 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2114 ENDIAN_8IN32);
2115#endif
2116 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2117 bypass_lut = true;
2118 break;
2119 case DRM_FORMAT_BGRX1010102:
2120 case DRM_FORMAT_BGRA1010102:
2121 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2122 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2123#ifdef __BIG_ENDIAN
2124 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2125 ENDIAN_8IN32);
2126#endif
2127 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2128 bypass_lut = true;
2129 break;
2130 default:
b3c11ac2
EE		 2131 DRM_ERROR("Unsupported screen format %s\n",
2132 drm_get_format_name(target_fb->pixel_format, &format_name));
aaa36a97
AD		 2133 return -EINVAL;
2134 }
2135
fbd76d59
MO		 2136 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2137 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
aaa36a97 2138
fbd76d59
MO		 2139 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2140 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2141 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2142 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2143 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
aaa36a97 2144
aaa36a97
AD		 2145 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2146 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2147 ARRAY_2D_TILED_THIN1);
2148 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2149 tile_split);
2150 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2151 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2152 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2153 mtaspect);
2154 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2155 ADDR_SURF_MICRO_TILING_DISPLAY);
fbd76d59 2156 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
aaa36a97
AD		 2157 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2158 ARRAY_1D_TILED_THIN1);
2159 }
2160
aaa36a97
AD		 2161 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2162 pipe_config);
2163
2164 dce_v11_0_vga_enable(crtc, false);
2165
cb9e59d7
AD		 2166 /* Make sure surface address is updated at vertical blank rather than
2167 * horizontal blank
2168 */
2169 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2170 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2171 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2172 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2173
aaa36a97
AD		 2174 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2175 upper_32_bits(fb_location));
2176 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2177 upper_32_bits(fb_location));
2178 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2179 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2180 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2181 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2182 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2183 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2184
2185 /*
2186 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2187 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2188 * retain the full precision throughout the pipeline.
2189 */
2190 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2191 if (bypass_lut)
2192 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2193 else
2194 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2195 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2196
2197 if (bypass_lut)
2198 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2199
2200 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2201 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2202 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2203 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2204 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2205 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2206
2207 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2208 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2209
2210 dce_v11_0_grph_enable(crtc, true);
2211
2212 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2213 target_fb->height);
2214
2215 x &= ~3;
2216 y &= ~1;
2217 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2218 (x << 16) | y);
2219 viewport_w = crtc->mode.hdisplay;
2220 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2221 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2222 (viewport_w << 16) | viewport_h);
2223
3fd4b751
MD		 2224 /* set pageflip to happen anywhere in vblank interval */
2225 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
aaa36a97
AD		 2226
2227 if (!atomic && fb && fb != crtc->primary->fb) {
2228 amdgpu_fb = to_amdgpu_framebuffer(fb);
765e7fbf
CK		 2229 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2230 r = amdgpu_bo_reserve(abo, false);
aaa36a97
AD		 2231 if (unlikely(r != 0))
2232 return r;
765e7fbf
CK		 2233 amdgpu_bo_unpin(abo);
2234 amdgpu_bo_unreserve(abo);
aaa36a97
AD		 2235 }
2236
2237 /* Bytes per pixel may have changed */
2238 dce_v11_0_bandwidth_update(adev);
2239
2240 return 0;
2241}
2242
2243static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2244 struct drm_display_mode *mode)
2245{
2246 struct drm_device *dev = crtc->dev;
2247 struct amdgpu_device *adev = dev->dev_private;
2248 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2249 u32 tmp;
2250
2251 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2252 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2253 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2254 else
2255 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2256 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2257}
2258
2259static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2260{
2261 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2262 struct drm_device *dev = crtc->dev;
2263 struct amdgpu_device *adev = dev->dev_private;
2264 int i;
2265 u32 tmp;
2266
2267 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2268
2269 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2270 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2271 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2272
2273 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2274 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2275 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2276
2277 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2278 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2279 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2280
2281 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2282
2283 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2284 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2285 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2286
2287 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2288 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2289 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2290
2291 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2292 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2293
2294 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2295 for (i = 0; i < 256; i++) {
2296 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2297 (amdgpu_crtc->lut_r[i] << 20) |
2298 (amdgpu_crtc->lut_g[i] << 10) |
2299 (amdgpu_crtc->lut_b[i] << 0));
2300 }
2301
2302 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2303 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2304 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2305 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2306 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2307
2308 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2309 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2310 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2311
2312 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2313 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2314 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2315
2316 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2317 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2318 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2319
2320 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2321 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2322 /* XXX this only needs to be programmed once per crtc at startup,
2323 * not sure where the best place for it is
2324 */
2325 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2326 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2327 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2328}
2329
2330static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2331{
2332 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2333 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2334
2335 switch (amdgpu_encoder->encoder_id) {
2336 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2337 if (dig->linkb)
2338 return 1;
2339 else
2340 return 0;
2341 break;
2342 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2343 if (dig->linkb)
2344 return 3;
2345 else
2346 return 2;
2347 break;
2348 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2349 if (dig->linkb)
2350 return 5;
2351 else
2352 return 4;
2353 break;
2354 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2355 return 6;
2356 break;
2357 default:
2358 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2359 return 0;
2360 }
2361}
2362
2363/**
2364 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2365 *
2366 * @crtc: drm crtc
2367 *
2368 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2369 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2370 * monitors a dedicated PPLL must be used. If a particular board has
2371 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2372 * as there is no need to program the PLL itself. If we are not able to
2373 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2374 * avoid messing up an existing monitor.
2375 *
2376 * Asic specific PLL information
2377 *
2378 * DCE 10.x
2379 * Tonga
2380 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2381 * CI
2382 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2383 *
2384 */
2385static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2386{
2387 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2388 struct drm_device *dev = crtc->dev;
2389 struct amdgpu_device *adev = dev->dev_private;
2390 u32 pll_in_use;
2391 int pll;
2392
2cc0c0b5 2393 if ((adev->asic_type == CHIP_POLARIS10) ||
c4642a47
JZ		 2394 (adev->asic_type == CHIP_POLARIS11) ||
2395 (adev->asic_type == CHIP_POLARIS12)) {
927a81c9
AD		 2396 struct amdgpu_encoder *amdgpu_encoder =
2397 to_amdgpu_encoder(amdgpu_crtc->encoder);
2398 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2399
2400 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2401 return ATOM_DP_DTO;
927a81c9
AD		 2402
2403 switch (amdgpu_encoder->encoder_id) {
2404 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2405 if (dig->linkb)
2406 return ATOM_COMBOPHY_PLL1;
2407 else
2408 return ATOM_COMBOPHY_PLL0;
2409 break;
2410 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2411 if (dig->linkb)
2412 return ATOM_COMBOPHY_PLL3;
2413 else
2414 return ATOM_COMBOPHY_PLL2;
2415 break;
2416 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2417 if (dig->linkb)
2418 return ATOM_COMBOPHY_PLL5;
2419 else
2420 return ATOM_COMBOPHY_PLL4;
2421 break;
2422 default:
2423 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2424 return ATOM_PPLL_INVALID;
2425 }
2426 }
2427
aaa36a97
AD		 2428 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2429 if (adev->clock.dp_extclk)
2430 /* skip PPLL programming if using ext clock */
2431 return ATOM_PPLL_INVALID;
2432 else {
2433 /* use the same PPLL for all DP monitors */
2434 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2435 if (pll != ATOM_PPLL_INVALID)
2436 return pll;
2437 }
2438 } else {
2439 /* use the same PPLL for all monitors with the same clock */
2440 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2441 if (pll != ATOM_PPLL_INVALID)
2442 return pll;
2443 }
2444
2445 /* XXX need to determine what plls are available on each DCE11 part */
2446 pll_in_use = amdgpu_pll_get_use_mask(crtc);
fa2f9bef 2447 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
aaa36a97
AD		 2448 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2449 return ATOM_PPLL1;
2450 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2451 return ATOM_PPLL0;
2452 DRM_ERROR("unable to allocate a PPLL\n");
2453 return ATOM_PPLL_INVALID;
2454 } else {
2455 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2456 return ATOM_PPLL2;
2457 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2458 return ATOM_PPLL1;
2459 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2460 return ATOM_PPLL0;
2461 DRM_ERROR("unable to allocate a PPLL\n");
2462 return ATOM_PPLL_INVALID;
2463 }
2464 return ATOM_PPLL_INVALID;
2465}
2466
2467static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2468{
2469 struct amdgpu_device *adev = crtc->dev->dev_private;
2470 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2471 uint32_t cur_lock;
2472
2473 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2474 if (lock)
2475 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2476 else
2477 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2478 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2479}
2480
2481static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2482{
2483 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2484 struct amdgpu_device *adev = crtc->dev->dev_private;
2485 u32 tmp;
2486
2487 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2488 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2489 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2490}
2491
2492static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2493{
2494 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2495 struct amdgpu_device *adev = crtc->dev->dev_private;
2496 u32 tmp;
2497
ec9353dc
AD		 2498 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2499 upper_32_bits(amdgpu_crtc->cursor_addr));
2500 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2501 lower_32_bits(amdgpu_crtc->cursor_addr));
2502
aaa36a97
AD		 2503 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2504 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2505 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2506 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2507}
2508
d8ee89c6
AD		 2509static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2510 int x, int y)
aaa36a97
AD		 2511{
2512 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2513 struct amdgpu_device *adev = crtc->dev->dev_private;
2514 int xorigin = 0, yorigin = 0;
2515
8e57ec61
MD		 2516 amdgpu_crtc->cursor_x = x;
2517 amdgpu_crtc->cursor_y = y;
2518
aaa36a97
AD		 2519 /* avivo cursor are offset into the total surface */
2520 x += crtc->x;
2521 y += crtc->y;
2522 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2523
2524 if (x < 0) {
2525 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2526 x = 0;
2527 }
2528 if (y < 0) {
2529 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2530 y = 0;
2531 }
2532
aaa36a97
AD		 2533 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2534 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
69bcc0b7
MD		 2535 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2536 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
d8ee89c6 2537
aaa36a97
AD		 2538 return 0;
2539}
2540
d8ee89c6
AD		 2541static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2542 int x, int y)
2543{
2544 int ret;
2545
2546 dce_v11_0_lock_cursor(crtc, true);
2547 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2548 dce_v11_0_lock_cursor(crtc, false);
2549
2550 return ret;
2551}
2552
2553static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2554 struct drm_file *file_priv,
2555 uint32_t handle,
2556 uint32_t width,
2557 uint32_t height,
2558 int32_t hot_x,
2559 int32_t hot_y)
aaa36a97
AD		 2560{
2561 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2562 struct drm_gem_object *obj;
232cc652 2563 struct amdgpu_bo *aobj;
aaa36a97
AD		 2564 int ret;
2565
2566 if (!handle) {
2567 /* turn off cursor */
2568 dce_v11_0_hide_cursor(crtc);
2569 obj = NULL;
2570 goto unpin;
2571 }
2572
2573 if ((width > amdgpu_crtc->max_cursor_width) ||
2574 (height > amdgpu_crtc->max_cursor_height)) {
2575 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2576 return -EINVAL;
2577 }
2578
a8ad0bd8 2579 obj = drm_gem_object_lookup(file_priv, handle);
aaa36a97
AD		 2580 if (!obj) {
2581 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2582 return -ENOENT;
2583 }
2584
232cc652
AD		 2585 aobj = gem_to_amdgpu_bo(obj);
2586 ret = amdgpu_bo_reserve(aobj, false);
2587 if (ret != 0) {
2588 drm_gem_object_unreference_unlocked(obj);
2589 return ret;
2590 }
2591
2592 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2593 amdgpu_bo_unreserve(aobj);
2594 if (ret) {
2595 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2596 drm_gem_object_unreference_unlocked(obj);
2597 return ret;
2598 }
aaa36a97 2599
aaa36a97 2600 dce_v11_0_lock_cursor(crtc, true);
1996ea09 2601
69bcc0b7
MD		 2602 if (width != amdgpu_crtc->cursor_width ||
2603 height != amdgpu_crtc->cursor_height ||
2604 hot_x != amdgpu_crtc->cursor_hot_x ||
1996ea09
AD		 2605 hot_y != amdgpu_crtc->cursor_hot_y) {
2606 int x, y;
2607
2608 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2609 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2610
2611 dce_v11_0_cursor_move_locked(crtc, x, y);
2612
7c83d7ab
MD		 2613 amdgpu_crtc->cursor_width = width;
2614 amdgpu_crtc->cursor_height = height;
69bcc0b7
MD		 2615 amdgpu_crtc->cursor_hot_x = hot_x;
2616 amdgpu_crtc->cursor_hot_y = hot_y;
7c83d7ab
MD		 2617 }
2618
aaa36a97
AD		 2619 dce_v11_0_show_cursor(crtc);
2620 dce_v11_0_lock_cursor(crtc, false);
2621
2622unpin:
2623 if (amdgpu_crtc->cursor_bo) {
8ddef5a5
AD		 2624 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2625 ret = amdgpu_bo_reserve(aobj, false);
aaa36a97 2626 if (likely(ret == 0)) {
8ddef5a5
AD		 2627 amdgpu_bo_unpin(aobj);
2628 amdgpu_bo_unreserve(aobj);
aaa36a97
AD		 2629 }
2630 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2631 }
2632
2633 amdgpu_crtc->cursor_bo = obj;
2634 return 0;
8ddef5a5 2635}
aaa36a97 2636
8ddef5a5
AD		 2637static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2638{
2639 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
8ddef5a5
AD		 2640
2641 if (amdgpu_crtc->cursor_bo) {
2642 dce_v11_0_lock_cursor(crtc, true);
2643
2644 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2645 amdgpu_crtc->cursor_y);
2646
232cc652 2647 dce_v11_0_show_cursor(crtc);
8ddef5a5
AD		 2648
2649 dce_v11_0_lock_cursor(crtc, false);
2650 }
aaa36a97
AD		 2651}
2652
7ea77283
ML		 2653static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2654 u16 *blue, uint32_t size)
aaa36a97
AD		 2655{
2656 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7ea77283 2657 int i;
aaa36a97
AD		 2658
2659 /* userspace palettes are always correct as is */
7ea77283 2660 for (i = 0; i < size; i++) {
aaa36a97
AD		 2661 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2662 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2663 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2664 }
2665 dce_v11_0_crtc_load_lut(crtc);
7ea77283
ML		 2666
2667 return 0;
aaa36a97
AD		 2668}
2669
2670static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2671{
2672 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2673
2674 drm_crtc_cleanup(crtc);
aaa36a97
AD		 2675 kfree(amdgpu_crtc);
2676}
2677
2678static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
d8ee89c6 2679 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
aaa36a97
AD		 2680 .cursor_move = dce_v11_0_crtc_cursor_move,
2681 .gamma_set = dce_v11_0_crtc_gamma_set,
2682 .set_config = amdgpu_crtc_set_config,
2683 .destroy = dce_v11_0_crtc_destroy,
325cbba1 2684 .page_flip_target = amdgpu_crtc_page_flip_target,
aaa36a97
AD		 2685};
2686
2687static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2688{
2689 struct drm_device *dev = crtc->dev;
2690 struct amdgpu_device *adev = dev->dev_private;
2691 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
d84b272a 2692 unsigned type;
aaa36a97
AD		 2693
2694 switch (mode) {
2695 case DRM_MODE_DPMS_ON:
2696 amdgpu_crtc->enabled = true;
2697 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2698 dce_v11_0_vga_enable(crtc, true);
2699 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2700 dce_v11_0_vga_enable(crtc, false);
f6c7aba4 2701 /* Make sure VBLANK and PFLIP interrupts are still enabled */
d84b272a
MD		 2702 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2703 amdgpu_irq_update(adev, &adev->crtc_irq, type);
f6c7aba4 2704 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
9a7841e9 2705 drm_crtc_vblank_on(crtc);
aaa36a97
AD		 2706 dce_v11_0_crtc_load_lut(crtc);
2707 break;
2708 case DRM_MODE_DPMS_STANDBY:
2709 case DRM_MODE_DPMS_SUSPEND:
2710 case DRM_MODE_DPMS_OFF:
9a7841e9 2711 drm_crtc_vblank_off(crtc);
aaa36a97
AD		 2712 if (amdgpu_crtc->enabled) {
2713 dce_v11_0_vga_enable(crtc, true);
2714 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2715 dce_v11_0_vga_enable(crtc, false);
2716 }
2717 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2718 amdgpu_crtc->enabled = false;
2719 break;
2720 }
2721 /* adjust pm to dpms */
2722 amdgpu_pm_compute_clocks(adev);
2723}
2724
2725static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2726{
2727 /* disable crtc pair power gating before programming */
2728 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2729 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2730 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2731}
2732
2733static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2734{
2735 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2736 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2737}
2738
2739static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2740{
2741 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2742 struct drm_device *dev = crtc->dev;
2743 struct amdgpu_device *adev = dev->dev_private;
2744 struct amdgpu_atom_ss ss;
2745 int i;
2746
2747 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2748 if (crtc->primary->fb) {
2749 int r;
2750 struct amdgpu_framebuffer *amdgpu_fb;
765e7fbf 2751 struct amdgpu_bo *abo;
aaa36a97
AD		 2752
2753 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
765e7fbf
CK		 2754 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2755 r = amdgpu_bo_reserve(abo, false);
aaa36a97 2756 if (unlikely(r))
765e7fbf 2757 DRM_ERROR("failed to reserve abo before unpin\n");
aaa36a97 2758 else {
765e7fbf
CK		 2759 amdgpu_bo_unpin(abo);
2760 amdgpu_bo_unreserve(abo);
aaa36a97
AD		 2761 }
2762 }
2763 /* disable the GRPH */
2764 dce_v11_0_grph_enable(crtc, false);
2765
2766 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2767
2768 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2769 if (adev->mode_info.crtcs[i] &&
2770 adev->mode_info.crtcs[i]->enabled &&
2771 i != amdgpu_crtc->crtc_id &&
2772 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2773 /* one other crtc is using this pll don't turn
2774 * off the pll
2775 */
2776 goto done;
2777 }
2778 }
2779
2780 switch (amdgpu_crtc->pll_id) {
2781 case ATOM_PPLL0:
2782 case ATOM_PPLL1:
2783 case ATOM_PPLL2:
2784 /* disable the ppll */
2785 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
22f0c5bd
AD		 2786 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2787 break;
2788 case ATOM_COMBOPHY_PLL0:
2789 case ATOM_COMBOPHY_PLL1:
2790 case ATOM_COMBOPHY_PLL2:
2791 case ATOM_COMBOPHY_PLL3:
2792 case ATOM_COMBOPHY_PLL4:
2793 case ATOM_COMBOPHY_PLL5:
2794 /* disable the ppll */
2795 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2796 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
aaa36a97
AD		 2797 break;
2798 default:
2799 break;
2800 }
2801done:
2802 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2803 amdgpu_crtc->adjusted_clock = 0;
2804 amdgpu_crtc->encoder = NULL;
2805 amdgpu_crtc->connector = NULL;
2806}
2807
2808static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2809 struct drm_display_mode *mode,
2810 struct drm_display_mode *adjusted_mode,
2811 int x, int y, struct drm_framebuffer *old_fb)
2812{
2813 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
22f0c5bd
AD		 2814 struct drm_device *dev = crtc->dev;
2815 struct amdgpu_device *adev = dev->dev_private;
aaa36a97
AD		 2816
2817 if (!amdgpu_crtc->adjusted_clock)
2818 return -EINVAL;
2819
2cc0c0b5 2820 if ((adev->asic_type == CHIP_POLARIS10) ||
c4642a47
JZ		 2821 (adev->asic_type == CHIP_POLARIS11) ||
2822 (adev->asic_type == CHIP_POLARIS12)) {
22f0c5bd
AD		 2823 struct amdgpu_encoder *amdgpu_encoder =
2824 to_amdgpu_encoder(amdgpu_crtc->encoder);
2825 int encoder_mode =
2826 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2827
2828 /* SetPixelClock calculates the plls and ss values now */
2829 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2830 amdgpu_crtc->pll_id,
2831 encoder_mode, amdgpu_encoder->encoder_id,
2832 adjusted_mode->clock, 0, 0, 0, 0,
2833 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2834 } else {
2835 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2836 }
aaa36a97
AD		 2837 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2838 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2839 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2840 amdgpu_atombios_crtc_scaler_setup(crtc);
8ddef5a5 2841 dce_v11_0_cursor_reset(crtc);
aaa36a97
AD		 2842 /* update the hw version fpr dpm */
2843 amdgpu_crtc->hw_mode = *adjusted_mode;
2844
2845 return 0;
2846}
2847
2848static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2849 const struct drm_display_mode *mode,
2850 struct drm_display_mode *adjusted_mode)
2851{
2852 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2853 struct drm_device *dev = crtc->dev;
2854 struct drm_encoder *encoder;
2855
2856 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2857 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2858 if (encoder->crtc == crtc) {
2859 amdgpu_crtc->encoder = encoder;
2860 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2861 break;
2862 }
2863 }
2864 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2865 amdgpu_crtc->encoder = NULL;
2866 amdgpu_crtc->connector = NULL;
2867 return false;
2868 }
2869 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2870 return false;
2871 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2872 return false;
2873 /* pick pll */
2874 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2875 /* if we can't get a PPLL for a non-DP encoder, fail */
2876 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2877 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2878 return false;
2879
2880 return true;
2881}
2882
2883static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2884 struct drm_framebuffer *old_fb)
2885{
2886 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2887}
2888
2889static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2890 struct drm_framebuffer *fb,
2891 int x, int y, enum mode_set_atomic state)
2892{
2893 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2894}
2895
2896static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2897 .dpms = dce_v11_0_crtc_dpms,
2898 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2899 .mode_set = dce_v11_0_crtc_mode_set,
2900 .mode_set_base = dce_v11_0_crtc_set_base,
2901 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2902 .prepare = dce_v11_0_crtc_prepare,
2903 .commit = dce_v11_0_crtc_commit,
2904 .load_lut = dce_v11_0_crtc_load_lut,
2905 .disable = dce_v11_0_crtc_disable,
2906};
2907
2908static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2909{
2910 struct amdgpu_crtc *amdgpu_crtc;
2911 int i;
2912
2913 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2914 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2915 if (amdgpu_crtc == NULL)
2916 return -ENOMEM;
2917
2918 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2919
2920 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2921 amdgpu_crtc->crtc_id = index;
aaa36a97
AD		 2922 adev->mode_info.crtcs[index] = amdgpu_crtc;
2923
2924 amdgpu_crtc->max_cursor_width = 128;
2925 amdgpu_crtc->max_cursor_height = 128;
2926 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2927 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2928
2929 for (i = 0; i < 256; i++) {
2930 amdgpu_crtc->lut_r[i] = i << 2;
2931 amdgpu_crtc->lut_g[i] = i << 2;
2932 amdgpu_crtc->lut_b[i] = i << 2;
2933 }
2934
2935 switch (amdgpu_crtc->crtc_id) {
2936 case 0:
2937 default:
2938 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2939 break;
2940 case 1:
2941 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2942 break;
2943 case 2:
2944 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2945 break;
2946 case 3:
2947 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2948 break;
2949 case 4:
2950 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2951 break;
2952 case 5:
2953 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2954 break;
2955 }
2956
2957 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2958 amdgpu_crtc->adjusted_clock = 0;
2959 amdgpu_crtc->encoder = NULL;
2960 amdgpu_crtc->connector = NULL;
2961 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2962
2963 return 0;
2964}
2965
5fc3aeeb 2966static int dce_v11_0_early_init(void *handle)
aaa36a97 2967{
5fc3aeeb 2968 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2969
aaa36a97
AD		 2970 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2971 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2972
2973 dce_v11_0_set_display_funcs(adev);
2974 dce_v11_0_set_irq_funcs(adev);
2975
83c9b025
ED		 2976 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2977
aaa36a97
AD		 2978 switch (adev->asic_type) {
2979 case CHIP_CARRIZO:
aaa36a97
AD		 2980 adev->mode_info.num_hpd = 6;
2981 adev->mode_info.num_dig = 9;
2982 break;
fa2f9bef 2983 case CHIP_STONEY:
fa2f9bef
SL		 2984 adev->mode_info.num_hpd = 6;
2985 adev->mode_info.num_dig = 9;
2986 break;
2cc0c0b5 2987 case CHIP_POLARIS10:
d525eb8d
AD		 2988 adev->mode_info.num_hpd = 6;
2989 adev->mode_info.num_dig = 6;
2990 break;
2cc0c0b5 2991 case CHIP_POLARIS11:
c4642a47 2992 case CHIP_POLARIS12:
d525eb8d
AD		 2993 adev->mode_info.num_hpd = 5;
2994 adev->mode_info.num_dig = 5;
2995 break;
aaa36a97
AD		 2996 default:
2997 /* FIXME: not supported yet */
2998 return -EINVAL;
2999 }
3000
3001 return 0;
3002}
3003
5fc3aeeb 3004static int dce_v11_0_sw_init(void *handle)
aaa36a97
AD		 3005{
3006 int r, i;
5fc3aeeb 3007 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3008
3009 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3010 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3011 if (r)
bcc71beb 3012 return r;
aaa36a97
AD		 3013 }
3014
3015 for (i = 8; i < 20; i += 2) {
3016 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3017 if (r)
3018 return r;
3019 }
3020
3021 /* HPD hotplug */
3022 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3023 if (r)
bcc71beb 3024 return r;
aaa36a97 3025
aaa36a97
AD		 3026 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3027
cb9e59d7
AD		 3028 adev->ddev->mode_config.async_page_flip = true;
3029
aaa36a97
AD		 3030 adev->ddev->mode_config.max_width = 16384;
3031 adev->ddev->mode_config.max_height = 16384;
3032
3033 adev->ddev->mode_config.preferred_depth = 24;
3034 adev->ddev->mode_config.prefer_shadow = 1;
3035
3036 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3037
3038 r = amdgpu_modeset_create_props(adev);
3039 if (r)
3040 return r;
3041
3042 adev->ddev->mode_config.max_width = 16384;
3043 adev->ddev->mode_config.max_height = 16384;
3044
c437b9d6 3045
aaa36a97
AD		 3046 /* allocate crtcs */
3047 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3048 r = dce_v11_0_crtc_init(adev, i);
3049 if (r)
3050 return r;
3051 }
3052
3053 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3054 amdgpu_print_display_setup(adev->ddev);
3055 else
3056 return -EINVAL;
3057
3058 /* setup afmt */
041ab0a4
TSD		 3059 r = dce_v11_0_afmt_init(adev);
3060 if (r)
3061 return r;
aaa36a97
AD		 3062
3063 r = dce_v11_0_audio_init(adev);
3064 if (r)
3065 return r;
3066
3067 drm_kms_helper_poll_init(adev->ddev);
3068
c437b9d6
TSD		 3069 adev->mode_info.mode_config_initialized = true;
3070 return 0;
aaa36a97
AD		 3071}
3072
5fc3aeeb 3073static int dce_v11_0_sw_fini(void *handle)
aaa36a97 3074{
5fc3aeeb 3075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3076
aaa36a97
AD		 3077 kfree(adev->mode_info.bios_hardcoded_edid);
3078
3079 drm_kms_helper_poll_fini(adev->ddev);
3080
3081 dce_v11_0_audio_fini(adev);
3082
3083 dce_v11_0_afmt_fini(adev);
3084
140c94da 3085 drm_mode_config_cleanup(adev->ddev);
aaa36a97
AD		 3086 adev->mode_info.mode_config_initialized = false;
3087
3088 return 0;
3089}
3090
5fc3aeeb 3091static int dce_v11_0_hw_init(void *handle)
aaa36a97
AD		 3092{
3093 int i;
5fc3aeeb 3094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3095
3096 dce_v11_0_init_golden_registers(adev);
3097
3098 /* init dig PHYs, disp eng pll */
f9fff064 3099 amdgpu_atombios_crtc_powergate_init(adev);
aaa36a97 3100 amdgpu_atombios_encoder_init_dig(adev);
2cc0c0b5 3101 if ((adev->asic_type == CHIP_POLARIS10) ||
c4642a47
JZ		 3102 (adev->asic_type == CHIP_POLARIS11) ||
3103 (adev->asic_type == CHIP_POLARIS12)) {
b18e6ad7
AD		 3104 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3105 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3106 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3107 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3108 } else {
3109 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3110 }
aaa36a97
AD		 3111
3112 /* initialize hpd */
3113 dce_v11_0_hpd_init(adev);
3114
3115 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3116 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3117 }
3118
f6c7aba4
MD		 3119 dce_v11_0_pageflip_interrupt_init(adev);
3120
aaa36a97
AD		 3121 return 0;
3122}
3123
5fc3aeeb 3124static int dce_v11_0_hw_fini(void *handle)
aaa36a97
AD		 3125{
3126 int i;
5fc3aeeb 3127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3128
3129 dce_v11_0_hpd_fini(adev);
3130
3131 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3132 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3133 }
3134
f6c7aba4
MD		 3135 dce_v11_0_pageflip_interrupt_fini(adev);
3136
aaa36a97
AD		 3137 return 0;
3138}
3139
5fc3aeeb 3140static int dce_v11_0_suspend(void *handle)
aaa36a97 3141{
f9fff064 3142 return dce_v11_0_hw_fini(handle);
aaa36a97
AD		 3143}
3144
5fc3aeeb 3145static int dce_v11_0_resume(void *handle)
aaa36a97 3146{
5fc3aeeb 3147 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
f9fff064 3148 int ret;
aaa36a97 3149
f9fff064 3150 ret = dce_v11_0_hw_init(handle);
aaa36a97 3151
aaa36a97
AD		 3152 /* turn on the BL */
3153 if (adev->mode_info.bl_encoder) {
3154 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3155 adev->mode_info.bl_encoder);
3156 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3157 bl_level);
3158 }
3159
f9fff064 3160 return ret;
aaa36a97
AD		 3161}
3162
5fc3aeeb 3163static bool dce_v11_0_is_idle(void *handle)
aaa36a97 3164{
aaa36a97
AD		 3165 return true;
3166}
3167
5fc3aeeb 3168static int dce_v11_0_wait_for_idle(void *handle)
aaa36a97 3169{
aaa36a97
AD		 3170 return 0;
3171}
3172
5fc3aeeb 3173static int dce_v11_0_soft_reset(void *handle)
aaa36a97
AD		 3174{
3175 u32 srbm_soft_reset = 0, tmp;
5fc3aeeb 3176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3177
3178 if (dce_v11_0_is_display_hung(adev))
3179 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3180
3181 if (srbm_soft_reset) {
aaa36a97
AD		 3182 tmp = RREG32(mmSRBM_SOFT_RESET);
3183 tmp |= srbm_soft_reset;
3184 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3185 WREG32(mmSRBM_SOFT_RESET, tmp);
3186 tmp = RREG32(mmSRBM_SOFT_RESET);
3187
3188 udelay(50);
3189
3190 tmp &= ~srbm_soft_reset;
3191 WREG32(mmSRBM_SOFT_RESET, tmp);
3192 tmp = RREG32(mmSRBM_SOFT_RESET);
3193
3194 /* Wait a little for things to settle down */
3195 udelay(50);
aaa36a97
AD		 3196 }
3197 return 0;
3198}
3199
3200static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3201 int crtc,
3202 enum amdgpu_interrupt_state state)
3203{
3204 u32 lb_interrupt_mask;
3205
3206 if (crtc >= adev->mode_info.num_crtc) {
3207 DRM_DEBUG("invalid crtc %d\n", crtc);
3208 return;
3209 }
3210
3211 switch (state) {
3212 case AMDGPU_IRQ_STATE_DISABLE:
3213 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3214 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3215 VBLANK_INTERRUPT_MASK, 0);
3216 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3217 break;
3218 case AMDGPU_IRQ_STATE_ENABLE:
3219 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3220 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3221 VBLANK_INTERRUPT_MASK, 1);
3222 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3223 break;
3224 default:
3225 break;
3226 }
3227}
3228
3229static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3230 int crtc,
3231 enum amdgpu_interrupt_state state)
3232{
3233 u32 lb_interrupt_mask;
3234
3235 if (crtc >= adev->mode_info.num_crtc) {
3236 DRM_DEBUG("invalid crtc %d\n", crtc);
3237 return;
3238 }
3239
3240 switch (state) {
3241 case AMDGPU_IRQ_STATE_DISABLE:
3242 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3243 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3244 VLINE_INTERRUPT_MASK, 0);
3245 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3246 break;
3247 case AMDGPU_IRQ_STATE_ENABLE:
3248 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3249 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3250 VLINE_INTERRUPT_MASK, 1);
3251 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3252 break;
3253 default:
3254 break;
3255 }
3256}
3257
3258static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3259 struct amdgpu_irq_src *source,
3260 unsigned hpd,
3261 enum amdgpu_interrupt_state state)
3262{
3263 u32 tmp;
3264
3265 if (hpd >= adev->mode_info.num_hpd) {
3266 DRM_DEBUG("invalid hdp %d\n", hpd);
3267 return 0;
3268 }
3269
3270 switch (state) {
3271 case AMDGPU_IRQ_STATE_DISABLE:
3272 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3273 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3274 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3275 break;
3276 case AMDGPU_IRQ_STATE_ENABLE:
3277 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3278 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3279 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3280 break;
3281 default:
3282 break;
3283 }
3284
3285 return 0;
3286}
3287
3288static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3289 struct amdgpu_irq_src *source,
3290 unsigned type,
3291 enum amdgpu_interrupt_state state)
3292{
3293 switch (type) {
3294 case AMDGPU_CRTC_IRQ_VBLANK1:
3295 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3296 break;
3297 case AMDGPU_CRTC_IRQ_VBLANK2:
3298 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3299 break;
3300 case AMDGPU_CRTC_IRQ_VBLANK3:
3301 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3302 break;
3303 case AMDGPU_CRTC_IRQ_VBLANK4:
3304 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3305 break;
3306 case AMDGPU_CRTC_IRQ_VBLANK5:
3307 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3308 break;
3309 case AMDGPU_CRTC_IRQ_VBLANK6:
3310 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3311 break;
3312 case AMDGPU_CRTC_IRQ_VLINE1:
3313 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3314 break;
3315 case AMDGPU_CRTC_IRQ_VLINE2:
3316 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3317 break;
3318 case AMDGPU_CRTC_IRQ_VLINE3:
3319 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3320 break;
3321 case AMDGPU_CRTC_IRQ_VLINE4:
3322 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3323 break;
3324 case AMDGPU_CRTC_IRQ_VLINE5:
3325 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3326 break;
3327 case AMDGPU_CRTC_IRQ_VLINE6:
3328 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3329 break;
3330 default:
3331 break;
3332 }
3333 return 0;
3334}
3335
3336static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3337 struct amdgpu_irq_src *src,
3338 unsigned type,
3339 enum amdgpu_interrupt_state state)
3340{
7dfac896
AD		 3341 u32 reg;
3342
3343 if (type >= adev->mode_info.num_crtc) {
3344 DRM_ERROR("invalid pageflip crtc %d\n", type);
3345 return -EINVAL;
aaa36a97
AD		 3346 }
3347
7dfac896 3348 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
aaa36a97 3349 if (state == AMDGPU_IRQ_STATE_DISABLE)
7dfac896
AD		 3350 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3351 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
aaa36a97 3352 else
7dfac896
AD		 3353 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3354 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
aaa36a97
AD		 3355
3356 return 0;
3357}
3358
3359static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3360 struct amdgpu_irq_src *source,
3361 struct amdgpu_iv_entry *entry)
3362{
aaa36a97
AD		 3363 unsigned long flags;
3364 unsigned crtc_id;
3365 struct amdgpu_crtc *amdgpu_crtc;
3366 struct amdgpu_flip_work *works;
3367
3368 crtc_id = (entry->src_id - 8) >> 1;
3369 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3370
7dfac896
AD		 3371 if (crtc_id >= adev->mode_info.num_crtc) {
3372 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3373 return -EINVAL;
aaa36a97
AD		 3374 }
3375
7dfac896
AD		 3376 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3377 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3378 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3379 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
aaa36a97
AD		 3380
3381 /* IRQ could occur when in initial stage */
3382 if(amdgpu_crtc == NULL)
3383 return 0;
3384
3385 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3386 works = amdgpu_crtc->pflip_works;
3387 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3388 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3389 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3390 amdgpu_crtc->pflip_status,
3391 AMDGPU_FLIP_SUBMITTED);
3392 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3393 return 0;
3394 }
3395
3396 /* page flip completed. clean up */
3397 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3398 amdgpu_crtc->pflip_works = NULL;
3399
3400 /* wakeup usersapce */
3401 if(works->event)
56286769 3402 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
aaa36a97
AD		 3403
3404 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3405
60629c4d 3406 drm_crtc_vblank_put(&amdgpu_crtc->base);
87d58c11 3407 schedule_work(&works->unpin_work);
aaa36a97
AD		 3408
3409 return 0;
3410}
3411
3412static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3413 int hpd)
3414{
3415 u32 tmp;
3416
3417 if (hpd >= adev->mode_info.num_hpd) {
3418 DRM_DEBUG("invalid hdp %d\n", hpd);
3419 return;
3420 }
3421
3422 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3423 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3424 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3425}
3426
3427static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3428 int crtc)
3429{
3430 u32 tmp;
3431
15c3277f 3432 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
aaa36a97
AD		 3433 DRM_DEBUG("invalid crtc %d\n", crtc);
3434 return;
3435 }
3436
3437 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3438 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3439 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3440}
3441
3442static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3443 int crtc)
3444{
3445 u32 tmp;
3446
15c3277f 3447 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
aaa36a97
AD		 3448 DRM_DEBUG("invalid crtc %d\n", crtc);
3449 return;
3450 }
3451
3452 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3453 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3454 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3455}
3456
3457static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3458 struct amdgpu_irq_src *source,
3459 struct amdgpu_iv_entry *entry)
3460{
3461 unsigned crtc = entry->src_id - 1;
3462 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3463 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3464
3465 switch (entry->src_data) {
3466 case 0: /* vblank */
bd833144 3467 if (disp_int & interrupt_status_offsets[crtc].vblank)
aaa36a97 3468 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
bd833144
MK		 3469 else
3470 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3471
3472 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3473 drm_handle_vblank(adev->ddev, crtc);
aaa36a97 3474 }
bd833144
MK		 3475 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3476
aaa36a97
AD		 3477 break;
3478 case 1: /* vline */
bd833144 3479 if (disp_int & interrupt_status_offsets[crtc].vline)
aaa36a97 3480 dce_v11_0_crtc_vline_int_ack(adev, crtc);
bd833144
MK		 3481 else
3482 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3483
3484 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3485
aaa36a97
AD		 3486 break;
3487 default:
3488 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3489 break;
3490 }
3491
3492 return 0;
3493}
3494
3495static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3496 struct amdgpu_irq_src *source,
3497 struct amdgpu_iv_entry *entry)
3498{
3499 uint32_t disp_int, mask;
3500 unsigned hpd;
3501
3502 if (entry->src_data >= adev->mode_info.num_hpd) {
3503 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3504 return 0;
3505 }
3506
3507 hpd = entry->src_data;
3508 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3509 mask = interrupt_status_offsets[hpd].hpd;
3510
3511 if (disp_int & mask) {
3512 dce_v11_0_hpd_int_ack(adev, hpd);
3513 schedule_work(&adev->hotplug_work);
3514 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3515 }
3516
3517 return 0;
3518}
3519
5fc3aeeb 3520static int dce_v11_0_set_clockgating_state(void *handle,
3521 enum amd_clockgating_state state)
aaa36a97
AD		 3522{
3523 return 0;
3524}
3525
5fc3aeeb 3526static int dce_v11_0_set_powergating_state(void *handle,
3527 enum amd_powergating_state state)
aaa36a97
AD		 3528{
3529 return 0;
3530}
3531
a1255107 3532static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
88a907d6 3533 .name = "dce_v11_0",
aaa36a97
AD		 3534 .early_init = dce_v11_0_early_init,
3535 .late_init = NULL,
3536 .sw_init = dce_v11_0_sw_init,
3537 .sw_fini = dce_v11_0_sw_fini,
3538 .hw_init = dce_v11_0_hw_init,
3539 .hw_fini = dce_v11_0_hw_fini,
3540 .suspend = dce_v11_0_suspend,
3541 .resume = dce_v11_0_resume,
3542 .is_idle = dce_v11_0_is_idle,
3543 .wait_for_idle = dce_v11_0_wait_for_idle,
3544 .soft_reset = dce_v11_0_soft_reset,
aaa36a97
AD		 3545 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3546 .set_powergating_state = dce_v11_0_set_powergating_state,
3547};
3548
3549static void
3550dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3551 struct drm_display_mode *mode,
3552 struct drm_display_mode *adjusted_mode)
3553{
3554 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3555
3556 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3557
3558 /* need to call this here rather than in prepare() since we need some crtc info */
3559 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3560
3561 /* set scaler clears this on some chips */
3562 dce_v11_0_set_interleave(encoder->crtc, mode);
3563
3564 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3565 dce_v11_0_afmt_enable(encoder, true);
3566 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3567 }
3568}
3569
3570static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3571{
3572 struct amdgpu_device *adev = encoder->dev->dev_private;
3573 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3574 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3575
3576 if ((amdgpu_encoder->active_device &
3577 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3578 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3579 ENCODER_OBJECT_ID_NONE)) {
3580 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3581 if (dig) {
3582 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3583 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3584 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3585 }
3586 }
3587
3588 amdgpu_atombios_scratch_regs_lock(adev, true);
3589
3590 if (connector) {
3591 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3592
3593 /* select the clock/data port if it uses a router */
3594 if (amdgpu_connector->router.cd_valid)
3595 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3596
3597 /* turn eDP panel on for mode set */
3598 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3599 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3600 ATOM_TRANSMITTER_ACTION_POWER_ON);
3601 }
3602
3603 /* this is needed for the pll/ss setup to work correctly in some cases */
3604 amdgpu_atombios_encoder_set_crtc_source(encoder);
3605 /* set up the FMT blocks */
3606 dce_v11_0_program_fmt(encoder);
3607}
3608
3609static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3610{
3611 struct drm_device *dev = encoder->dev;
3612 struct amdgpu_device *adev = dev->dev_private;
3613
3614 /* need to call this here as we need the crtc set up */
3615 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3616 amdgpu_atombios_scratch_regs_lock(adev, false);
3617}
3618
3619static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3620{
3621 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3622 struct amdgpu_encoder_atom_dig *dig;
3623
3624 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3625
3626 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3627 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3628 dce_v11_0_afmt_enable(encoder, false);
3629 dig = amdgpu_encoder->enc_priv;
3630 dig->dig_encoder = -1;
3631 }
3632 amdgpu_encoder->active_device = 0;
3633}
3634
3635/* these are handled by the primary encoders */
3636static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3637{
3638
3639}
3640
3641static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3642{
3643
3644}
3645
3646static void
3647dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3648 struct drm_display_mode *mode,
3649 struct drm_display_mode *adjusted_mode)
3650{
3651
3652}
3653
3654static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3655{
3656
3657}
3658
3659static void
3660dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3661{
3662
3663}
3664
aaa36a97
AD		 3665static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3666 .dpms = dce_v11_0_ext_dpms,
aaa36a97
AD		 3667 .prepare = dce_v11_0_ext_prepare,
3668 .mode_set = dce_v11_0_ext_mode_set,
3669 .commit = dce_v11_0_ext_commit,
3670 .disable = dce_v11_0_ext_disable,
3671 /* no detect for TMDS/LVDS yet */
3672};
3673
3674static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3675 .dpms = amdgpu_atombios_encoder_dpms,
3676 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3677 .prepare = dce_v11_0_encoder_prepare,
3678 .mode_set = dce_v11_0_encoder_mode_set,
3679 .commit = dce_v11_0_encoder_commit,
3680 .disable = dce_v11_0_encoder_disable,
3681 .detect = amdgpu_atombios_encoder_dig_detect,
3682};
3683
3684static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3685 .dpms = amdgpu_atombios_encoder_dpms,
3686 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3687 .prepare = dce_v11_0_encoder_prepare,
3688 .mode_set = dce_v11_0_encoder_mode_set,
3689 .commit = dce_v11_0_encoder_commit,
3690 .detect = amdgpu_atombios_encoder_dac_detect,
3691};
3692
3693static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3694{
3695 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3696 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3697 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3698 kfree(amdgpu_encoder->enc_priv);
3699 drm_encoder_cleanup(encoder);
3700 kfree(amdgpu_encoder);
3701}
3702
3703static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3704 .destroy = dce_v11_0_encoder_destroy,
3705};
3706
3707static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3708 uint32_t encoder_enum,
3709 uint32_t supported_device,
3710 u16 caps)
3711{
3712 struct drm_device *dev = adev->ddev;
3713 struct drm_encoder *encoder;
3714 struct amdgpu_encoder *amdgpu_encoder;
3715
3716 /* see if we already added it */
3717 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3718 amdgpu_encoder = to_amdgpu_encoder(encoder);
3719 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3720 amdgpu_encoder->devices |= supported_device;
3721 return;
3722 }
3723
3724 }
3725
3726 /* add a new one */
3727 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3728 if (!amdgpu_encoder)
3729 return;
3730
3731 encoder = &amdgpu_encoder->base;
3732 switch (adev->mode_info.num_crtc) {
3733 case 1:
3734 encoder->possible_crtcs = 0x1;
3735 break;
3736 case 2:
3737 default:
3738 encoder->possible_crtcs = 0x3;
3739 break;
3740 case 4:
3741 encoder->possible_crtcs = 0xf;
3742 break;
3743 case 6:
3744 encoder->possible_crtcs = 0x3f;
3745 break;
3746 }
3747
3748 amdgpu_encoder->enc_priv = NULL;
3749
3750 amdgpu_encoder->encoder_enum = encoder_enum;
3751 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3752 amdgpu_encoder->devices = supported_device;
3753 amdgpu_encoder->rmx_type = RMX_OFF;
3754 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3755 amdgpu_encoder->is_ext_encoder = false;
3756 amdgpu_encoder->caps = caps;
3757
3758 switch (amdgpu_encoder->encoder_id) {
3759 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3760 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3761 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3762 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3763 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3764 break;
3765 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3766 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3767 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3768 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3769 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3770 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3771 amdgpu_encoder->rmx_type = RMX_FULL;
3772 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3773 DRM_MODE_ENCODER_LVDS, NULL);
aaa36a97
AD		 3774 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3775 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3776 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3777 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3778 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3779 } else {
3780 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3781 DRM_MODE_ENCODER_TMDS, NULL);
aaa36a97
AD		 3782 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3783 }
3784 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3785 break;
3786 case ENCODER_OBJECT_ID_SI170B:
3787 case ENCODER_OBJECT_ID_CH7303:
3788 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3789 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3790 case ENCODER_OBJECT_ID_TITFP513:
3791 case ENCODER_OBJECT_ID_VT1623:
3792 case ENCODER_OBJECT_ID_HDMI_SI1930:
3793 case ENCODER_OBJECT_ID_TRAVIS:
3794 case ENCODER_OBJECT_ID_NUTMEG:
3795 /* these are handled by the primary encoders */
3796 amdgpu_encoder->is_ext_encoder = true;
3797 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3798 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3799 DRM_MODE_ENCODER_LVDS, NULL);
aaa36a97
AD		 3800 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3801 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3802 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3803 else
3804 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3805 DRM_MODE_ENCODER_TMDS, NULL);
aaa36a97
AD		 3806 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3807 break;
3808 }
3809}
3810
3811static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3812 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3813 .bandwidth_update = &dce_v11_0_bandwidth_update,
3814 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3815 .vblank_wait = &dce_v11_0_vblank_wait,
aaa36a97
AD		 3816 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3817 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3818 .hpd_sense = &dce_v11_0_hpd_sense,
3819 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3820 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3821 .page_flip = &dce_v11_0_page_flip,
3822 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3823 .add_encoder = &dce_v11_0_encoder_add,
3824 .add_connector = &amdgpu_connector_add,
3825 .stop_mc_access = &dce_v11_0_stop_mc_access,
3826 .resume_mc_access = &dce_v11_0_resume_mc_access,
3827};
3828
3829static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3830{
3831 if (adev->mode_info.funcs == NULL)
3832 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3833}
3834
3835static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3836 .set = dce_v11_0_set_crtc_irq_state,
3837 .process = dce_v11_0_crtc_irq,
3838};
3839
3840static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3841 .set = dce_v11_0_set_pageflip_irq_state,
3842 .process = dce_v11_0_pageflip_irq,
3843};
3844
3845static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3846 .set = dce_v11_0_set_hpd_irq_state,
3847 .process = dce_v11_0_hpd_irq,
3848};
3849
3850static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3851{
3852 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3853 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3854
3855 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3856 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3857
3858 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3859 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3860}
a1255107
AD		 3861
3862const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3863{
3864 .type = AMD_IP_BLOCK_TYPE_DCE,
3865 .major = 11,
3866 .minor = 0,
3867 .rev = 0,
3868 .funcs = &dce_v11_0_ip_funcs,
3869};
3870
3871const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3872{
3873 .type = AMD_IP_BLOCK_TYPE_DCE,
3874 .major = 11,
3875 .minor = 2,
3876 .rev = 0,
3877 .funcs = &dce_v11_0_ip_funcs,
3878};
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