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drm: Add missing mutex_destroy in drm_dev_init/release
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / dce_v6_0.c
CommitLineData
e2cdf640
KW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "atom.h"
28#include "amdgpu_atombios.h"
29#include "atombios_crtc.h"
30#include "atombios_encoders.h"
31#include "amdgpu_pll.h"
32#include "amdgpu_connectors.h"
33#include "si/si_reg.h"
34#include "si/sid.h"
35
36static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
37static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
38
39static const u32 crtc_offsets[6] =
40{
41 SI_CRTC0_REGISTER_OFFSET,
42 SI_CRTC1_REGISTER_OFFSET,
43 SI_CRTC2_REGISTER_OFFSET,
44 SI_CRTC3_REGISTER_OFFSET,
45 SI_CRTC4_REGISTER_OFFSET,
46 SI_CRTC5_REGISTER_OFFSET
47};
48
34386043
AD		 49static const u32 hpd_offsets[] =
50{
51 DC_HPD1_INT_STATUS - DC_HPD1_INT_STATUS,
52 DC_HPD2_INT_STATUS - DC_HPD1_INT_STATUS,
53 DC_HPD3_INT_STATUS - DC_HPD1_INT_STATUS,
54 DC_HPD4_INT_STATUS - DC_HPD1_INT_STATUS,
55 DC_HPD5_INT_STATUS - DC_HPD1_INT_STATUS,
56 DC_HPD6_INT_STATUS - DC_HPD1_INT_STATUS,
57};
58
e2cdf640
KW		 59static const uint32_t dig_offsets[] = {
60 SI_CRTC0_REGISTER_OFFSET,
61 SI_CRTC1_REGISTER_OFFSET,
62 SI_CRTC2_REGISTER_OFFSET,
63 SI_CRTC3_REGISTER_OFFSET,
64 SI_CRTC4_REGISTER_OFFSET,
65 SI_CRTC5_REGISTER_OFFSET,
66 (0x13830 - 0x7030) >> 2,
67};
68
69static const struct {
70 uint32_t reg;
71 uint32_t vblank;
72 uint32_t vline;
73 uint32_t hpd;
74
75} interrupt_status_offsets[6] = { {
76 .reg = DISP_INTERRUPT_STATUS,
77 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
78 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
80}, {
81 .reg = DISP_INTERRUPT_STATUS_CONTINUE,
82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
83 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
85}, {
86 .reg = DISP_INTERRUPT_STATUS_CONTINUE2,
87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
90}, {
91 .reg = DISP_INTERRUPT_STATUS_CONTINUE3,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
95}, {
96 .reg = DISP_INTERRUPT_STATUS_CONTINUE4,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
100}, {
101 .reg = DISP_INTERRUPT_STATUS_CONTINUE5,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
105} };
106
e2cdf640
KW		 107static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
108 u32 block_offset, u32 reg)
109{
110 DRM_INFO("xxxx: dce_v6_0_audio_endpt_rreg ----no impl!!!!\n");
111 return 0;
112}
113
114static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
115 u32 block_offset, u32 reg, u32 v)
116{
117 DRM_INFO("xxxx: dce_v6_0_audio_endpt_wreg ----no impl!!!!\n");
118}
119
120static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
121{
122 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
123 return true;
124 else
125 return false;
126}
127
128static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
129{
130 u32 pos1, pos2;
131
132 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
133 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
134
135 if (pos1 != pos2)
136 return true;
137 else
138 return false;
139}
140
141/**
142 * dce_v6_0_wait_for_vblank - vblank wait asic callback.
143 *
144 * @crtc: crtc to wait for vblank on
145 *
146 * Wait for vblank on the requested crtc (evergreen+).
147 */
148static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
149{
e37e4f05 150 unsigned i = 100;
e2cdf640
KW		 151
152 if (crtc >= adev->mode_info.num_crtc)
153 return;
154
155 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
156 return;
157
158 /* depending on when we hit vblank, we may be close to active; if so,
159 * wait for another frame.
160 */
161 while (dce_v6_0_is_in_vblank(adev, crtc)) {
e37e4f05
TSD		 162 if (i++ == 100) {
163 i = 0;
e2cdf640
KW		 164 if (!dce_v6_0_is_counter_moving(adev, crtc))
165 break;
166 }
167 }
168
169 while (!dce_v6_0_is_in_vblank(adev, crtc)) {
e37e4f05
TSD		 170 if (i++ == 100) {
171 i = 0;
e2cdf640
KW		 172 if (!dce_v6_0_is_counter_moving(adev, crtc))
173 break;
174 }
175 }
176}
177
178static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
179{
180 if (crtc >= adev->mode_info.num_crtc)
181 return 0;
182 else
183 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
184}
185
186static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
187{
188 unsigned i;
189
190 /* Enable pflip interrupts */
02124a03 191 for (i = 0; i < adev->mode_info.num_crtc; i++)
e2cdf640
KW		 192 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
193}
194
195static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
196{
197 unsigned i;
198
199 /* Disable pflip interrupts */
02124a03 200 for (i = 0; i < adev->mode_info.num_crtc; i++)
e2cdf640
KW		 201 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
202}
203
204/**
205 * dce_v6_0_page_flip - pageflip callback.
206 *
207 * @adev: amdgpu_device pointer
208 * @crtc_id: crtc to cleanup pageflip on
209 * @crtc_base: new address of the crtc (GPU MC address)
210 *
211 * Does the actual pageflip (evergreen+).
212 * During vblank we take the crtc lock and wait for the update_pending
213 * bit to go high, when it does, we release the lock, and allow the
214 * double buffered update to take place.
215 * Returns the current update pending status.
216 */
217static void dce_v6_0_page_flip(struct amdgpu_device *adev,
218 int crtc_id, u64 crtc_base, bool async)
219{
220 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
221
222 /* flip at hsync for async, default is vsync */
223 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
224 EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
225 /* update the scanout addresses */
226 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
227 upper_32_bits(crtc_base));
228 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
229 (u32)crtc_base);
230
231 /* post the write */
232 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
233}
234
235static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
236 u32 *vbl, u32 *position)
237{
238 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
239 return -EINVAL;
240 *vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + crtc_offsets[crtc]);
241 *position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
242
243 return 0;
244
245}
246
247/**
248 * dce_v6_0_hpd_sense - hpd sense callback.
249 *
250 * @adev: amdgpu_device pointer
251 * @hpd: hpd (hotplug detect) pin
252 *
253 * Checks if a digital monitor is connected (evergreen+).
254 * Returns true if connected, false if not connected.
255 */
256static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
257 enum amdgpu_hpd_id hpd)
258{
259 bool connected = false;
260
34386043
AD		 261 if (hpd >= adev->mode_info.num_hpd)
262 return connected;
263
264 if (RREG32(DC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPDx_SENSE)
265 connected = true;
e2cdf640
KW		 266
267 return connected;
268}
269
270/**
271 * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
272 *
273 * @adev: amdgpu_device pointer
274 * @hpd: hpd (hotplug detect) pin
275 *
276 * Set the polarity of the hpd pin (evergreen+).
277 */
278static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
279 enum amdgpu_hpd_id hpd)
280{
281 u32 tmp;
282 bool connected = dce_v6_0_hpd_sense(adev, hpd);
283
34386043
AD		 284 if (hpd >= adev->mode_info.num_hpd)
285 return;
286
287 tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
288 if (connected)
289 tmp &= ~DC_HPDx_INT_POLARITY;
290 else
291 tmp |= DC_HPDx_INT_POLARITY;
292 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
e2cdf640
KW		 293}
294
295/**
296 * dce_v6_0_hpd_init - hpd setup callback.
297 *
298 * @adev: amdgpu_device pointer
299 *
300 * Setup the hpd pins used by the card (evergreen+).
301 * Enable the pin, set the polarity, and enable the hpd interrupts.
302 */
303static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
304{
305 struct drm_device *dev = adev->ddev;
306 struct drm_connector *connector;
079ea190 307 u32 tmp;
e2cdf640
KW		 308
309 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
310 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
311
34386043
AD		 312 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
313 continue;
314
079ea190
AD		 315 tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
316 tmp |= DC_HPDx_EN;
34386043 317 WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
2744b647
AD		 318
319 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
320 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
321 /* don't try to enable hpd on eDP or LVDS avoid breaking the
322 * aux dp channel on imac and help (but not completely fix)
323 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
324 * also avoid interrupt storms during dpms.
325 */
34386043
AD		 326 tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
327 tmp &= ~DC_HPDx_INT_EN;
328 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
2744b647
AD		 329 continue;
330 }
331
e2cdf640
KW		 332 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
333 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
334 }
335
336}
337
338/**
339 * dce_v6_0_hpd_fini - hpd tear down callback.
340 *
341 * @adev: amdgpu_device pointer
342 *
343 * Tear down the hpd pins used by the card (evergreen+).
344 * Disable the hpd interrupts.
345 */
346static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
347{
348 struct drm_device *dev = adev->ddev;
349 struct drm_connector *connector;
079ea190 350 u32 tmp;
e2cdf640
KW		 351
352 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
353 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
354
34386043
AD		 355 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
356 continue;
357
079ea190
AD		 358 tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
359 tmp &= ~DC_HPDx_EN;
34386043
AD		 360 WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
361
e2cdf640
KW		 362 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
363 }
364}
365
366static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
367{
368 return SI_DC_GPIO_HPD_A;
369}
370
371static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev)
372{
373 DRM_INFO("xxxx: dce_v6_0_is_display_hung ----no imp!!!!!\n");
374
375 return true;
376}
377
378static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
379{
380 if (crtc >= adev->mode_info.num_crtc)
381 return 0;
382 else
383 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
384}
385
386static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
387 struct amdgpu_mode_mc_save *save)
388{
389 u32 crtc_enabled, tmp, frame_count;
390 int i, j;
391
392 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
393 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
394
395 /* disable VGA render */
396 WREG32(VGA_RENDER_CONTROL, 0);
397
398 /* blank the display controllers */
399 for (i = 0; i < adev->mode_info.num_crtc; i++) {
400 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
401 if (crtc_enabled) {
402 save->crtc_enabled[i] = true;
403 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
404
405 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
406 dce_v6_0_vblank_wait(adev, i);
407 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
408 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
409 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
410 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
411 }
412 /* wait for the next frame */
413 frame_count = evergreen_get_vblank_counter(adev, i);
414 for (j = 0; j < adev->usec_timeout; j++) {
415 if (evergreen_get_vblank_counter(adev, i) != frame_count)
416 break;
417 udelay(1);
418 }
419
420 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
421 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
422 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
423 tmp &= ~EVERGREEN_CRTC_MASTER_EN;
424 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
425 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
426 save->crtc_enabled[i] = false;
427 /* ***** */
428 } else {
429 save->crtc_enabled[i] = false;
430 }
431 }
432}
433
434static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
435 struct amdgpu_mode_mc_save *save)
436{
437 u32 tmp;
438 int i, j;
439
440 /* update crtc base addresses */
441 for (i = 0; i < adev->mode_info.num_crtc; i++) {
442 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
443 upper_32_bits(adev->mc.vram_start));
444 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
445 upper_32_bits(adev->mc.vram_start));
446 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
447 (u32)adev->mc.vram_start);
448 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
449 (u32)adev->mc.vram_start);
450 }
451
452 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
453 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
454
455 /* unlock regs and wait for update */
456 for (i = 0; i < adev->mode_info.num_crtc; i++) {
457 if (save->crtc_enabled[i]) {
458 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
459 if ((tmp & 0x7) != 3) {
460 tmp &= ~0x7;
461 tmp |= 0x3;
462 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
463 }
464 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
465 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
466 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
467 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
468 }
469 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
470 if (tmp & 1) {
471 tmp &= ~1;
472 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
473 }
474 for (j = 0; j < adev->usec_timeout; j++) {
475 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
476 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
477 break;
478 udelay(1);
479 }
480 }
481 }
482
483 /* Unlock vga access */
484 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
485 mdelay(1);
486 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
487
488}
489
490static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
491 bool render)
492{
1d160f43 493 if (!render)
e2cdf640
KW		 494 WREG32(R_000300_VGA_RENDER_CONTROL,
495 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
496
497}
498
1d160f43
AD		 499static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
500{
501 int num_crtc = 0;
502
503 switch (adev->asic_type) {
504 case CHIP_TAHITI:
505 case CHIP_PITCAIRN:
506 case CHIP_VERDE:
507 num_crtc = 6;
508 break;
509 case CHIP_OLAND:
510 num_crtc = 2;
511 break;
512 default:
513 num_crtc = 0;
514 }
515 return num_crtc;
516}
517
518void dce_v6_0_disable_dce(struct amdgpu_device *adev)
519{
520 /*Disable VGA render and enabled crtc, if has DCE engine*/
521 if (amdgpu_atombios_has_dce_engine_info(adev)) {
522 u32 tmp;
523 int crtc_enabled, i;
524
525 dce_v6_0_set_vga_render_state(adev, false);
526
527 /*Disable crtc*/
528 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
529 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) &
530 EVERGREEN_CRTC_MASTER_EN;
531 if (crtc_enabled) {
532 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
533 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
534 tmp &= ~EVERGREEN_CRTC_MASTER_EN;
535 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
536 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
537 }
538 }
539 }
540}
541
e2cdf640
KW		 542static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
543{
544
545 struct drm_device *dev = encoder->dev;
546 struct amdgpu_device *adev = dev->dev_private;
547 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
548 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
549 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
550 int bpc = 0;
551 u32 tmp = 0;
552 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
553
554 if (connector) {
555 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
556 bpc = amdgpu_connector_get_monitor_bpc(connector);
557 dither = amdgpu_connector->dither;
558 }
559
560 /* LVDS FMT is set up by atom */
561 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
562 return;
563
564 if (bpc == 0)
565 return;
566
567
568 switch (bpc) {
569 case 6:
570 if (dither == AMDGPU_FMT_DITHER_ENABLE)
571 /* XXX sort out optimal dither settings */
572 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
573 FMT_SPATIAL_DITHER_EN);
574 else
575 tmp |= FMT_TRUNCATE_EN;
576 break;
577 case 8:
578 if (dither == AMDGPU_FMT_DITHER_ENABLE)
579 /* XXX sort out optimal dither settings */
580 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
581 FMT_RGB_RANDOM_ENABLE |
582 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
583 else
584 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
585 break;
586 case 10:
587 default:
588 /* not needed */
589 break;
590 }
591
592 WREG32(FMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
593}
594
595/**
596 * cik_get_number_of_dram_channels - get the number of dram channels
597 *
598 * @adev: amdgpu_device pointer
599 *
600 * Look up the number of video ram channels (CIK).
601 * Used for display watermark bandwidth calculations
602 * Returns the number of dram channels
603 */
604static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
605{
606 u32 tmp = RREG32(MC_SHARED_CHMAP);
607
608 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
609 case 0:
610 default:
611 return 1;
612 case 1:
613 return 2;
614 case 2:
615 return 4;
616 case 3:
617 return 8;
618 case 4:
619 return 3;
620 case 5:
621 return 6;
622 case 6:
623 return 10;
624 case 7:
625 return 12;
626 case 8:
627 return 16;
628 }
629}
630
631struct dce6_wm_params {
632 u32 dram_channels; /* number of dram channels */
633 u32 yclk; /* bandwidth per dram data pin in kHz */
634 u32 sclk; /* engine clock in kHz */
635 u32 disp_clk; /* display clock in kHz */
636 u32 src_width; /* viewport width */
637 u32 active_time; /* active display time in ns */
638 u32 blank_time; /* blank time in ns */
639 bool interlaced; /* mode is interlaced */
640 fixed20_12 vsc; /* vertical scale ratio */
641 u32 num_heads; /* number of active crtcs */
642 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
643 u32 lb_size; /* line buffer allocated to pipe */
644 u32 vtaps; /* vertical scaler taps */
645};
646
647/**
648 * dce_v6_0_dram_bandwidth - get the dram bandwidth
649 *
650 * @wm: watermark calculation data
651 *
652 * Calculate the raw dram bandwidth (CIK).
653 * Used for display watermark bandwidth calculations
654 * Returns the dram bandwidth in MBytes/s
655 */
656static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
657{
658 /* Calculate raw DRAM Bandwidth */
659 fixed20_12 dram_efficiency; /* 0.7 */
660 fixed20_12 yclk, dram_channels, bandwidth;
661 fixed20_12 a;
662
663 a.full = dfixed_const(1000);
664 yclk.full = dfixed_const(wm->yclk);
665 yclk.full = dfixed_div(yclk, a);
666 dram_channels.full = dfixed_const(wm->dram_channels * 4);
667 a.full = dfixed_const(10);
668 dram_efficiency.full = dfixed_const(7);
669 dram_efficiency.full = dfixed_div(dram_efficiency, a);
670 bandwidth.full = dfixed_mul(dram_channels, yclk);
671 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
672
673 return dfixed_trunc(bandwidth);
674}
675
676/**
677 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
678 *
679 * @wm: watermark calculation data
680 *
681 * Calculate the dram bandwidth used for display (CIK).
682 * Used for display watermark bandwidth calculations
683 * Returns the dram bandwidth for display in MBytes/s
684 */
685static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
686{
687 /* Calculate DRAM Bandwidth and the part allocated to display. */
688 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
689 fixed20_12 yclk, dram_channels, bandwidth;
690 fixed20_12 a;
691
692 a.full = dfixed_const(1000);
693 yclk.full = dfixed_const(wm->yclk);
694 yclk.full = dfixed_div(yclk, a);
695 dram_channels.full = dfixed_const(wm->dram_channels * 4);
696 a.full = dfixed_const(10);
697 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
698 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
699 bandwidth.full = dfixed_mul(dram_channels, yclk);
700 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
701
702 return dfixed_trunc(bandwidth);
703}
704
705/**
706 * dce_v6_0_data_return_bandwidth - get the data return bandwidth
707 *
708 * @wm: watermark calculation data
709 *
710 * Calculate the data return bandwidth used for display (CIK).
711 * Used for display watermark bandwidth calculations
712 * Returns the data return bandwidth in MBytes/s
713 */
714static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
715{
716 /* Calculate the display Data return Bandwidth */
717 fixed20_12 return_efficiency; /* 0.8 */
718 fixed20_12 sclk, bandwidth;
719 fixed20_12 a;
720
721 a.full = dfixed_const(1000);
722 sclk.full = dfixed_const(wm->sclk);
723 sclk.full = dfixed_div(sclk, a);
724 a.full = dfixed_const(10);
725 return_efficiency.full = dfixed_const(8);
726 return_efficiency.full = dfixed_div(return_efficiency, a);
727 a.full = dfixed_const(32);
728 bandwidth.full = dfixed_mul(a, sclk);
729 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
730
731 return dfixed_trunc(bandwidth);
732}
733
734/**
735 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
736 *
737 * @wm: watermark calculation data
738 *
739 * Calculate the dmif bandwidth used for display (CIK).
740 * Used for display watermark bandwidth calculations
741 * Returns the dmif bandwidth in MBytes/s
742 */
743static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
744{
745 /* Calculate the DMIF Request Bandwidth */
746 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
747 fixed20_12 disp_clk, bandwidth;
748 fixed20_12 a, b;
749
750 a.full = dfixed_const(1000);
751 disp_clk.full = dfixed_const(wm->disp_clk);
752 disp_clk.full = dfixed_div(disp_clk, a);
753 a.full = dfixed_const(32);
754 b.full = dfixed_mul(a, disp_clk);
755
756 a.full = dfixed_const(10);
757 disp_clk_request_efficiency.full = dfixed_const(8);
758 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
759
760 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
761
762 return dfixed_trunc(bandwidth);
763}
764
765/**
766 * dce_v6_0_available_bandwidth - get the min available bandwidth
767 *
768 * @wm: watermark calculation data
769 *
770 * Calculate the min available bandwidth used for display (CIK).
771 * Used for display watermark bandwidth calculations
772 * Returns the min available bandwidth in MBytes/s
773 */
774static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
775{
776 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
777 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
778 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
779 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
780
781 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
782}
783
784/**
785 * dce_v6_0_average_bandwidth - get the average available bandwidth
786 *
787 * @wm: watermark calculation data
788 *
789 * Calculate the average available bandwidth used for display (CIK).
790 * Used for display watermark bandwidth calculations
791 * Returns the average available bandwidth in MBytes/s
792 */
793static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
794{
795 /* Calculate the display mode Average Bandwidth
796 * DisplayMode should contain the source and destination dimensions,
797 * timing, etc.
798 */
799 fixed20_12 bpp;
800 fixed20_12 line_time;
801 fixed20_12 src_width;
802 fixed20_12 bandwidth;
803 fixed20_12 a;
804
805 a.full = dfixed_const(1000);
806 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
807 line_time.full = dfixed_div(line_time, a);
808 bpp.full = dfixed_const(wm->bytes_per_pixel);
809 src_width.full = dfixed_const(wm->src_width);
810 bandwidth.full = dfixed_mul(src_width, bpp);
811 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
812 bandwidth.full = dfixed_div(bandwidth, line_time);
813
814 return dfixed_trunc(bandwidth);
815}
816
817/**
818 * dce_v6_0_latency_watermark - get the latency watermark
819 *
820 * @wm: watermark calculation data
821 *
822 * Calculate the latency watermark (CIK).
823 * Used for display watermark bandwidth calculations
824 * Returns the latency watermark in ns
825 */
826static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
827{
828 /* First calculate the latency in ns */
829 u32 mc_latency = 2000; /* 2000 ns. */
830 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);
831 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
832 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
833 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
834 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
835 (wm->num_heads * cursor_line_pair_return_time);
836 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
837 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
838 u32 tmp, dmif_size = 12288;
839 fixed20_12 a, b, c;
840
841 if (wm->num_heads == 0)
842 return 0;
843
844 a.full = dfixed_const(2);
845 b.full = dfixed_const(1);
846 if ((wm->vsc.full > a.full) ||
847 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
848 (wm->vtaps >= 5) ||
849 ((wm->vsc.full >= a.full) && wm->interlaced))
850 max_src_lines_per_dst_line = 4;
851 else
852 max_src_lines_per_dst_line = 2;
853
854 a.full = dfixed_const(available_bandwidth);
855 b.full = dfixed_const(wm->num_heads);
856 a.full = dfixed_div(a, b);
857
858 b.full = dfixed_const(mc_latency + 512);
859 c.full = dfixed_const(wm->disp_clk);
860 b.full = dfixed_div(b, c);
861
862 c.full = dfixed_const(dmif_size);
863 b.full = dfixed_div(c, b);
864
865 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
866
867 b.full = dfixed_const(1000);
868 c.full = dfixed_const(wm->disp_clk);
869 b.full = dfixed_div(c, b);
870 c.full = dfixed_const(wm->bytes_per_pixel);
871 b.full = dfixed_mul(b, c);
872
873 lb_fill_bw = min(tmp, dfixed_trunc(b));
874
875 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
876 b.full = dfixed_const(1000);
877 c.full = dfixed_const(lb_fill_bw);
878 b.full = dfixed_div(c, b);
879 a.full = dfixed_div(a, b);
880 line_fill_time = dfixed_trunc(a);
881
882 if (line_fill_time < wm->active_time)
883 return latency;
884 else
885 return latency + (line_fill_time - wm->active_time);
886
887}
888
889/**
890 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
891 * average and available dram bandwidth
892 *
893 * @wm: watermark calculation data
894 *
895 * Check if the display average bandwidth fits in the display
896 * dram bandwidth (CIK).
897 * Used for display watermark bandwidth calculations
898 * Returns true if the display fits, false if not.
899 */
900static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
901{
902 if (dce_v6_0_average_bandwidth(wm) <=
903 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
904 return true;
905 else
906 return false;
907}
908
909/**
910 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
911 * average and available bandwidth
912 *
913 * @wm: watermark calculation data
914 *
915 * Check if the display average bandwidth fits in the display
916 * available bandwidth (CIK).
917 * Used for display watermark bandwidth calculations
918 * Returns true if the display fits, false if not.
919 */
920static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
921{
922 if (dce_v6_0_average_bandwidth(wm) <=
923 (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
924 return true;
925 else
926 return false;
927}
928
929/**
930 * dce_v6_0_check_latency_hiding - check latency hiding
931 *
932 * @wm: watermark calculation data
933 *
934 * Check latency hiding (CIK).
935 * Used for display watermark bandwidth calculations
936 * Returns true if the display fits, false if not.
937 */
938static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
939{
940 u32 lb_partitions = wm->lb_size / wm->src_width;
941 u32 line_time = wm->active_time + wm->blank_time;
942 u32 latency_tolerant_lines;
943 u32 latency_hiding;
944 fixed20_12 a;
945
946 a.full = dfixed_const(1);
947 if (wm->vsc.full > a.full)
948 latency_tolerant_lines = 1;
949 else {
950 if (lb_partitions <= (wm->vtaps + 1))
951 latency_tolerant_lines = 1;
952 else
953 latency_tolerant_lines = 2;
954 }
955
956 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
957
958 if (dce_v6_0_latency_watermark(wm) <= latency_hiding)
959 return true;
960 else
961 return false;
962}
963
964/**
965 * dce_v6_0_program_watermarks - program display watermarks
966 *
967 * @adev: amdgpu_device pointer
968 * @amdgpu_crtc: the selected display controller
969 * @lb_size: line buffer size
970 * @num_heads: number of display controllers in use
971 *
972 * Calculate and program the display watermarks for the
973 * selected display controller (CIK).
974 */
975static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
976 struct amdgpu_crtc *amdgpu_crtc,
977 u32 lb_size, u32 num_heads)
978{
979 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
980 struct dce6_wm_params wm_low, wm_high;
981 u32 dram_channels;
982 u32 pixel_period;
983 u32 line_time = 0;
984 u32 latency_watermark_a = 0, latency_watermark_b = 0;
985 u32 priority_a_mark = 0, priority_b_mark = 0;
986 u32 priority_a_cnt = PRIORITY_OFF;
987 u32 priority_b_cnt = PRIORITY_OFF;
988 u32 tmp, arb_control3;
989 fixed20_12 a, b, c;
990
991 if (amdgpu_crtc->base.enabled && num_heads && mode) {
992 pixel_period = 1000000 / (u32)mode->clock;
993 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
994 priority_a_cnt = 0;
995 priority_b_cnt = 0;
996
997 dram_channels = si_get_number_of_dram_channels(adev);
998
999 /* watermark for high clocks */
1000 if (adev->pm.dpm_enabled) {
1001 wm_high.yclk =
1002 amdgpu_dpm_get_mclk(adev, false) * 10;
1003 wm_high.sclk =
1004 amdgpu_dpm_get_sclk(adev, false) * 10;
1005 } else {
1006 wm_high.yclk = adev->pm.current_mclk * 10;
1007 wm_high.sclk = adev->pm.current_sclk * 10;
1008 }
1009
1010 wm_high.disp_clk = mode->clock;
1011 wm_high.src_width = mode->crtc_hdisplay;
1012 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1013 wm_high.blank_time = line_time - wm_high.active_time;
1014 wm_high.interlaced = false;
1015 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1016 wm_high.interlaced = true;
1017 wm_high.vsc = amdgpu_crtc->vsc;
1018 wm_high.vtaps = 1;
1019 if (amdgpu_crtc->rmx_type != RMX_OFF)
1020 wm_high.vtaps = 2;
1021 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1022 wm_high.lb_size = lb_size;
1023 wm_high.dram_channels = dram_channels;
1024 wm_high.num_heads = num_heads;
1025
1026 if (adev->pm.dpm_enabled) {
1027 /* watermark for low clocks */
1028 wm_low.yclk =
1029 amdgpu_dpm_get_mclk(adev, true) * 10;
1030 wm_low.sclk =
1031 amdgpu_dpm_get_sclk(adev, true) * 10;
1032 } else {
1033 wm_low.yclk = adev->pm.current_mclk * 10;
1034 wm_low.sclk = adev->pm.current_sclk * 10;
1035 }
1036
1037 wm_low.disp_clk = mode->clock;
1038 wm_low.src_width = mode->crtc_hdisplay;
1039 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1040 wm_low.blank_time = line_time - wm_low.active_time;
1041 wm_low.interlaced = false;
1042 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1043 wm_low.interlaced = true;
1044 wm_low.vsc = amdgpu_crtc->vsc;
1045 wm_low.vtaps = 1;
1046 if (amdgpu_crtc->rmx_type != RMX_OFF)
1047 wm_low.vtaps = 2;
1048 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1049 wm_low.lb_size = lb_size;
1050 wm_low.dram_channels = dram_channels;
1051 wm_low.num_heads = num_heads;
1052
1053 /* set for high clocks */
1054 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535);
1055 /* set for low clocks */
1056 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535);
1057
1058 /* possibly force display priority to high */
1059 /* should really do this at mode validation time... */
1060 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1061 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1062 !dce_v6_0_check_latency_hiding(&wm_high) ||
1063 (adev->mode_info.disp_priority == 2)) {
1064 DRM_DEBUG_KMS("force priority to high\n");
1065 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1066 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1067 }
1068 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1069 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1070 !dce_v6_0_check_latency_hiding(&wm_low) ||
1071 (adev->mode_info.disp_priority == 2)) {
1072 DRM_DEBUG_KMS("force priority to high\n");
1073 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1074 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1075 }
1076
1077 a.full = dfixed_const(1000);
1078 b.full = dfixed_const(mode->clock);
1079 b.full = dfixed_div(b, a);
1080 c.full = dfixed_const(latency_watermark_a);
1081 c.full = dfixed_mul(c, b);
1082 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
1083 c.full = dfixed_div(c, a);
1084 a.full = dfixed_const(16);
1085 c.full = dfixed_div(c, a);
1086 priority_a_mark = dfixed_trunc(c);
1087 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1088
1089 a.full = dfixed_const(1000);
1090 b.full = dfixed_const(mode->clock);
1091 b.full = dfixed_div(b, a);
1092 c.full = dfixed_const(latency_watermark_b);
1093 c.full = dfixed_mul(c, b);
1094 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
1095 c.full = dfixed_div(c, a);
1096 a.full = dfixed_const(16);
1097 c.full = dfixed_div(c, a);
1098 priority_b_mark = dfixed_trunc(c);
1099 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1100 }
1101
1102 /* select wm A */
1103 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1104 tmp = arb_control3;
1105 tmp &= ~LATENCY_WATERMARK_MASK(3);
1106 tmp |= LATENCY_WATERMARK_MASK(1);
1107 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1108 WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset,
1109 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1110 LATENCY_HIGH_WATERMARK(line_time)));
1111 /* select wm B */
1112 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1113 tmp &= ~LATENCY_WATERMARK_MASK(3);
1114 tmp |= LATENCY_WATERMARK_MASK(2);
1115 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1116 WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset,
1117 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1118 LATENCY_HIGH_WATERMARK(line_time)));
1119 /* restore original selection */
1120 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
1121
1122 /* write the priority marks */
1123 WREG32(PRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
1124 WREG32(PRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
1125
1126 /* save values for DPM */
1127 amdgpu_crtc->line_time = line_time;
1128 amdgpu_crtc->wm_high = latency_watermark_a;
1129}
1130
1131/* watermark setup */
1132static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
1133 struct amdgpu_crtc *amdgpu_crtc,
1134 struct drm_display_mode *mode,
1135 struct drm_display_mode *other_mode)
1136{
1137 u32 tmp, buffer_alloc, i;
1138 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
1139 /*
1140 * Line Buffer Setup
1141 * There are 3 line buffers, each one shared by 2 display controllers.
1142 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1143 * the display controllers. The paritioning is done via one of four
1144 * preset allocations specified in bits 21:20:
1145 * 0 - half lb
1146 * 2 - whole lb, other crtc must be disabled
1147 */
1148 /* this can get tricky if we have two large displays on a paired group
1149 * of crtcs. Ideally for multiple large displays we'd assign them to
1150 * non-linked crtcs for maximum line buffer allocation.
1151 */
1152 if (amdgpu_crtc->base.enabled && mode) {
1153 if (other_mode) {
1154 tmp = 0; /* 1/2 */
1155 buffer_alloc = 1;
1156 } else {
1157 tmp = 2; /* whole */
1158 buffer_alloc = 2;
1159 }
1160 } else {
1161 tmp = 0;
1162 buffer_alloc = 0;
1163 }
1164
1165 WREG32(DC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1166 DC_LB_MEMORY_CONFIG(tmp));
1167
1168 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1169 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
1170 for (i = 0; i < adev->usec_timeout; i++) {
1171 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1172 DMIF_BUFFERS_ALLOCATED_COMPLETED)
1173 break;
1174 udelay(1);
1175 }
1176
1177 if (amdgpu_crtc->base.enabled && mode) {
1178 switch (tmp) {
1179 case 0:
1180 default:
1181 return 4096 * 2;
1182 case 2:
1183 return 8192 * 2;
1184 }
1185 }
1186
1187 /* controller not enabled, so no lb used */
1188 return 0;
1189}
1190
1191
1192/**
1193 *
1194 * dce_v6_0_bandwidth_update - program display watermarks
1195 *
1196 * @adev: amdgpu_device pointer
1197 *
1198 * Calculate and program the display watermarks and line
1199 * buffer allocation (CIK).
1200 */
1201static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
1202{
1203 struct drm_display_mode *mode0 = NULL;
1204 struct drm_display_mode *mode1 = NULL;
1205 u32 num_heads = 0, lb_size;
1206 int i;
1207
1208 if (!adev->mode_info.mode_config_initialized)
1209 return;
1210
1211 amdgpu_update_display_priority(adev);
1212
1213 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1214 if (adev->mode_info.crtcs[i]->base.enabled)
1215 num_heads++;
1216 }
1217 for (i = 0; i < adev->mode_info.num_crtc; i += 2) {
1218 mode0 = &adev->mode_info.crtcs[i]->base.mode;
1219 mode1 = &adev->mode_info.crtcs[i+1]->base.mode;
1220 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
1221 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads);
1222 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0);
1223 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads);
1224 }
1225}
1226/*
1227static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
1228{
1229 int i;
1230 u32 offset, tmp;
1231
1232 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1233 offset = adev->mode_info.audio.pin[i].offset;
1234 tmp = RREG32_AUDIO_ENDPT(offset,
1235 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1236 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
1237 adev->mode_info.audio.pin[i].connected = false;
1238 else
1239 adev->mode_info.audio.pin[i].connected = true;
1240 }
1241
1242}
1243
1244static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev)
1245{
1246 int i;
1247
1248 dce_v6_0_audio_get_connected_pins(adev);
1249
1250 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1251 if (adev->mode_info.audio.pin[i].connected)
1252 return &adev->mode_info.audio.pin[i];
1253 }
1254 DRM_ERROR("No connected audio pins found!\n");
1255 return NULL;
1256}
1257
1258static void dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1259{
1260 struct amdgpu_device *adev = encoder->dev->dev_private;
1261 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1262 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1263 u32 offset;
1264
1265 if (!dig || !dig->afmt || !dig->afmt->pin)
1266 return;
1267
1268 offset = dig->afmt->offset;
1269
1270 WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
1271 AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
1272
1273}
1274
1275static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
1276 struct drm_display_mode *mode)
1277{
1278 DRM_INFO("xxxx: dce_v6_0_audio_write_latency_fields---no imp!!!!!\n");
1279}
1280
1281static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1282{
1283 DRM_INFO("xxxx: dce_v6_0_audio_write_speaker_allocation---no imp!!!!!\n");
1284}
1285
1286static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
1287{
1288 DRM_INFO("xxxx: dce_v6_0_audio_write_sad_regs---no imp!!!!!\n");
1289
1290}
1291*/
1292static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
1293 struct amdgpu_audio_pin *pin,
1294 bool enable)
1295{
1296 DRM_INFO("xxxx: dce_v6_0_audio_enable---no imp!!!!!\n");
1297}
1298
1299static const u32 pin_offsets[7] =
1300{
1301 (0x1780 - 0x1780),
1302 (0x1786 - 0x1780),
1303 (0x178c - 0x1780),
1304 (0x1792 - 0x1780),
1305 (0x1798 - 0x1780),
1306 (0x179d - 0x1780),
1307 (0x17a4 - 0x1780),
1308};
1309
1310static int dce_v6_0_audio_init(struct amdgpu_device *adev)
1311{
1312 return 0;
1313}
1314
1315static void dce_v6_0_audio_fini(struct amdgpu_device *adev)
1316{
1317
1318}
1319
1320/*
1321static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1322{
1323 DRM_INFO("xxxx: dce_v6_0_afmt_update_ACR---no imp!!!!!\n");
1324}
1325*/
1326/*
1327 * build a HDMI Video Info Frame
1328 */
1329/*
1330static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1331 void *buffer, size_t size)
1332{
1333 DRM_INFO("xxxx: dce_v6_0_afmt_update_avi_infoframe---no imp!!!!!\n");
1334}
1335
1336static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1337{
1338 DRM_INFO("xxxx: dce_v6_0_audio_set_dto---no imp!!!!!\n");
1339}
1340*/
1341/*
1342 * update the info frames with the data from the current display mode
1343 */
1344static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
1345 struct drm_display_mode *mode)
1346{
1347 DRM_INFO("xxxx: dce_v6_0_afmt_setmode ----no impl !!!!!!!!\n");
1348}
1349
1350static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1351{
1352 struct drm_device *dev = encoder->dev;
1353 struct amdgpu_device *adev = dev->dev_private;
1354 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1355 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1356
1357 if (!dig || !dig->afmt)
1358 return;
1359
1360 /* Silent, r600_hdmi_enable will raise WARN for us */
1361 if (enable && dig->afmt->enabled)
1362 return;
1363 if (!enable && !dig->afmt->enabled)
1364 return;
1365
1366 if (!enable && dig->afmt->pin) {
1367 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1368 dig->afmt->pin = NULL;
1369 }
1370
1371 dig->afmt->enabled = enable;
1372
1373 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1374 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1375}
1376
beb86f29 1377static int dce_v6_0_afmt_init(struct amdgpu_device *adev)
e2cdf640 1378{
beb86f29 1379 int i, j;
e2cdf640
KW		 1380
1381 for (i = 0; i < adev->mode_info.num_dig; i++)
1382 adev->mode_info.afmt[i] = NULL;
1383
beb86f29 1384 /* DCE6 has audio blocks tied to DIG encoders */
e2cdf640
KW		 1385 for (i = 0; i < adev->mode_info.num_dig; i++) {
1386 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1387 if (adev->mode_info.afmt[i]) {
1388 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1389 adev->mode_info.afmt[i]->id = i;
beb86f29
TSD		 1390 } else {
1391 for (j = 0; j < i; j++) {
1392 kfree(adev->mode_info.afmt[j]);
1393 adev->mode_info.afmt[j] = NULL;
1394 }
1395 DRM_ERROR("Out of memory allocating afmt table\n");
1396 return -ENOMEM;
e2cdf640
KW		 1397 }
1398 }
beb86f29 1399 return 0;
e2cdf640
KW		 1400}
1401
1402static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1403{
1404 int i;
1405
1406 for (i = 0; i < adev->mode_info.num_dig; i++) {
1407 kfree(adev->mode_info.afmt[i]);
1408 adev->mode_info.afmt[i] = NULL;
1409 }
1410}
1411
1412static const u32 vga_control_regs[6] =
1413{
1414 AVIVO_D1VGA_CONTROL,
1415 AVIVO_D2VGA_CONTROL,
1416 EVERGREEN_D3VGA_CONTROL,
1417 EVERGREEN_D4VGA_CONTROL,
1418 EVERGREEN_D5VGA_CONTROL,
1419 EVERGREEN_D6VGA_CONTROL,
1420};
1421
1422static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
1423{
1424 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1425 struct drm_device *dev = crtc->dev;
1426 struct amdgpu_device *adev = dev->dev_private;
1427 u32 vga_control;
1428
1429 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
3d5f4d47 1430 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
e2cdf640
KW		 1431}
1432
1433static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1434{
1435 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1436 struct drm_device *dev = crtc->dev;
1437 struct amdgpu_device *adev = dev->dev_private;
1438
3d5f4d47 1439 WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
e2cdf640
KW		 1440}
1441
1442static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1443 struct drm_framebuffer *fb,
1444 int x, int y, int atomic)
1445{
1446 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1447 struct drm_device *dev = crtc->dev;
1448 struct amdgpu_device *adev = dev->dev_private;
1449 struct amdgpu_framebuffer *amdgpu_fb;
1450 struct drm_framebuffer *target_fb;
1451 struct drm_gem_object *obj;
765e7fbf 1452 struct amdgpu_bo *abo;
e2cdf640
KW		 1453 uint64_t fb_location, tiling_flags;
1454 uint32_t fb_format, fb_pitch_pixels, pipe_config;
1455 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1456 u32 viewport_w, viewport_h;
1457 int r;
1458 bool bypass_lut = false;
1459
1460 /* no fb bound */
1461 if (!atomic && !crtc->primary->fb) {
1462 DRM_DEBUG_KMS("No FB bound\n");
1463 return 0;
1464 }
1465
1466 if (atomic) {
1467 amdgpu_fb = to_amdgpu_framebuffer(fb);
1468 target_fb = fb;
3d5f4d47 1469 } else {
e2cdf640
KW		 1470 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1471 target_fb = crtc->primary->fb;
1472 }
1473
1474 /* If atomic, assume fb object is pinned & idle & fenced and
1475 * just update base pointers
1476 */
1477 obj = amdgpu_fb->obj;
765e7fbf
CK		 1478 abo = gem_to_amdgpu_bo(obj);
1479 r = amdgpu_bo_reserve(abo, false);
e2cdf640
KW		 1480 if (unlikely(r != 0))
1481 return r;
1482
3d5f4d47 1483 if (atomic) {
765e7fbf 1484 fb_location = amdgpu_bo_gpu_offset(abo);
3d5f4d47 1485 } else {
765e7fbf 1486 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
e2cdf640 1487 if (unlikely(r != 0)) {
765e7fbf 1488 amdgpu_bo_unreserve(abo);
e2cdf640
KW		 1489 return -EINVAL;
1490 }
1491 }
1492
765e7fbf
CK		 1493 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1494 amdgpu_bo_unreserve(abo);
e2cdf640
KW		 1495
1496 switch (target_fb->pixel_format) {
1497 case DRM_FORMAT_C8:
1498 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1499 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1500 break;
1501 case DRM_FORMAT_XRGB4444:
1502 case DRM_FORMAT_ARGB4444:
1503 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1504 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1505#ifdef __BIG_ENDIAN
1506 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1507#endif
1508 break;
1509 case DRM_FORMAT_XRGB1555:
1510 case DRM_FORMAT_ARGB1555:
1511 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1512 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1513#ifdef __BIG_ENDIAN
1514 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1515#endif
1516 break;
1517 case DRM_FORMAT_BGRX5551:
1518 case DRM_FORMAT_BGRA5551:
1519 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1520 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1521#ifdef __BIG_ENDIAN
1522 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1523#endif
1524 break;
1525 case DRM_FORMAT_RGB565:
1526 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1527 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1528#ifdef __BIG_ENDIAN
1529 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1530#endif
1531 break;
1532 case DRM_FORMAT_XRGB8888:
1533 case DRM_FORMAT_ARGB8888:
1534 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1535 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1536#ifdef __BIG_ENDIAN
1537 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1538#endif
1539 break;
1540 case DRM_FORMAT_XRGB2101010:
1541 case DRM_FORMAT_ARGB2101010:
1542 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1543 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1544#ifdef __BIG_ENDIAN
1545 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1546#endif
1547 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1548 bypass_lut = true;
1549 break;
1550 case DRM_FORMAT_BGRX1010102:
1551 case DRM_FORMAT_BGRA1010102:
1552 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1553 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1554#ifdef __BIG_ENDIAN
1555 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1556#endif
1557 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1558 bypass_lut = true;
1559 break;
1560 default:
1561 DRM_ERROR("Unsupported screen format %s\n",
1562 drm_get_format_name(target_fb->pixel_format));
1563 return -EINVAL;
1564 }
1565
1566 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1567 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1568
1569 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1570 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1571 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1572 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1573 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1574
1575 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1576 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1577 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1578 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1579 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1580 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
3d5f4d47 1581 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
e2cdf640 1582 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
3d5f4d47 1583 }
e2cdf640
KW		 1584
1585 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1586 fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
1587
1588 dce_v6_0_vga_enable(crtc, false);
1589
1590 /* Make sure surface address is updated at vertical blank rather than
1591 * horizontal blank
1592 */
1593 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1594
1595 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1596 upper_32_bits(fb_location));
1597 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1598 upper_32_bits(fb_location));
1599 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1600 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1601 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1602 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1603 WREG32(EVERGREEN_GRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1604 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + amdgpu_crtc->crtc_offset, fb_swap);
1605
1606 /*
1607 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1608 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1609 * retain the full precision throughout the pipeline.
1610 */
1611 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1612 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1613 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1614
1615 if (bypass_lut)
1616 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1617
1618 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1619 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1620 WREG32(EVERGREEN_GRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1621 WREG32(EVERGREEN_GRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1622 WREG32(EVERGREEN_GRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1623 WREG32(EVERGREEN_GRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1624
1625 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1626 WREG32(EVERGREEN_GRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1627
1628 dce_v6_0_grph_enable(crtc, true);
1629
1630 WREG32(EVERGREEN_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1631 target_fb->height);
1632 x &= ~3;
1633 y &= ~1;
1634 WREG32(EVERGREEN_VIEWPORT_START + amdgpu_crtc->crtc_offset,
1635 (x << 16) | y);
1636 viewport_w = crtc->mode.hdisplay;
1637 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1638
1639 WREG32(EVERGREEN_VIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1640 (viewport_w << 16) | viewport_h);
1641
1642 /* set pageflip to happen anywhere in vblank interval */
1643 WREG32(EVERGREEN_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1644
1645 if (!atomic && fb && fb != crtc->primary->fb) {
1646 amdgpu_fb = to_amdgpu_framebuffer(fb);
765e7fbf
CK		 1647 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1648 r = amdgpu_bo_reserve(abo, false);
e2cdf640
KW		 1649 if (unlikely(r != 0))
1650 return r;
765e7fbf
CK		 1651 amdgpu_bo_unpin(abo);
1652 amdgpu_bo_unreserve(abo);
e2cdf640
KW		 1653 }
1654
1655 /* Bytes per pixel may have changed */
1656 dce_v6_0_bandwidth_update(adev);
1657
1658 return 0;
1659
1660}
1661
1662static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
1663 struct drm_display_mode *mode)
1664{
1665 struct drm_device *dev = crtc->dev;
1666 struct amdgpu_device *adev = dev->dev_private;
1667 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1668
1669 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1670 WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset,
1671 EVERGREEN_INTERLEAVE_EN);
1672 else
1673 WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
1674}
1675
1676static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
1677{
1678
1679 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1680 struct drm_device *dev = crtc->dev;
1681 struct amdgpu_device *adev = dev->dev_private;
1682 int i;
1683
1684 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
1685
1686 WREG32(NI_INPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1687 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
1688 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
1689 WREG32(NI_PRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
1690 NI_GRPH_PRESCALE_BYPASS);
1691 WREG32(NI_PRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
1692 NI_OVL_PRESCALE_BYPASS);
1693 WREG32(NI_INPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1694 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
1695 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
1696
1697
1698
1699 WREG32(EVERGREEN_DC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
1700
1701 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
1702 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
1703 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
1704
1705 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
1706 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
1707 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
1708
1709 WREG32(EVERGREEN_DC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
1710 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
1711
1712 WREG32(EVERGREEN_DC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
1713 for (i = 0; i < 256; i++) {
1714 WREG32(EVERGREEN_DC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
1715 (amdgpu_crtc->lut_r[i] << 20) |
1716 (amdgpu_crtc->lut_g[i] << 10) |
1717 (amdgpu_crtc->lut_b[i] << 0));
1718 }
1719
1720 WREG32(NI_DEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1721 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
1722 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
1723 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
1724 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
1725 WREG32(NI_GAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
1726 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
1727 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
1728 WREG32(NI_REGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1729 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
1730 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
1731 WREG32(NI_OUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1732 (NI_OUTPUT_CSC_GRPH_MODE(0) |
1733 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
1734 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
1735 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
1736
1737
1738}
1739
1740static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
1741{
1742 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1743 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1744
1745 switch (amdgpu_encoder->encoder_id) {
1746 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3d5f4d47 1747 return dig->linkb ? 1 : 0;
e2cdf640 1748 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3d5f4d47 1749 return dig->linkb ? 3 : 2;
e2cdf640 1750 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3d5f4d47 1751 return dig->linkb ? 5 : 4;
e2cdf640
KW		 1752 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1753 return 6;
e2cdf640
KW		 1754 default:
1755 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
1756 return 0;
1757 }
1758}
1759
1760/**
1761 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
1762 *
1763 * @crtc: drm crtc
1764 *
1765 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1766 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1767 * monitors a dedicated PPLL must be used. If a particular board has
1768 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1769 * as there is no need to program the PLL itself. If we are not able to
1770 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1771 * avoid messing up an existing monitor.
1772 *
1773 *
1774 */
1775static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)
1776{
1777 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1778 struct drm_device *dev = crtc->dev;
1779 struct amdgpu_device *adev = dev->dev_private;
1780 u32 pll_in_use;
1781 int pll;
1782
1783 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
1784 if (adev->clock.dp_extclk)
1785 /* skip PPLL programming if using ext clock */
1786 return ATOM_PPLL_INVALID;
1787 else
1788 return ATOM_PPLL0;
1789 } else {
1790 /* use the same PPLL for all monitors with the same clock */
1791 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
1792 if (pll != ATOM_PPLL_INVALID)
1793 return pll;
1794 }
1795
1796 /* PPLL1, and PPLL2 */
1797 pll_in_use = amdgpu_pll_get_use_mask(crtc);
1798 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1799 return ATOM_PPLL2;
1800 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1801 return ATOM_PPLL1;
1802 DRM_ERROR("unable to allocate a PPLL\n");
1803 return ATOM_PPLL_INVALID;
1804}
1805
1806static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
1807{
1808 struct amdgpu_device *adev = crtc->dev->dev_private;
1809 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1810 uint32_t cur_lock;
1811
1812 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset);
1813 if (lock)
1814 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
1815 else
1816 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
1817 WREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
1818}
1819
1820static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
1821{
1822 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1823 struct amdgpu_device *adev = crtc->dev->dev_private;
1824
1825 WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset,
1826 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
1827 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
1828
1829
1830}
1831
1832static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
1833{
1834 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1835 struct amdgpu_device *adev = crtc->dev->dev_private;
1836
1837 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1838 upper_32_bits(amdgpu_crtc->cursor_addr));
1839 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1840 lower_32_bits(amdgpu_crtc->cursor_addr));
1841
1842 WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset,
1843 EVERGREEN_CURSOR_EN |
1844 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
1845 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
1846
1847}
1848
1849static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
1850 int x, int y)
1851{
1852 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1853 struct amdgpu_device *adev = crtc->dev->dev_private;
1854 int xorigin = 0, yorigin = 0;
1855
1856 int w = amdgpu_crtc->cursor_width;
1857
1858 /* avivo cursor are offset into the total surface */
1859 x += crtc->x;
1860 y += crtc->y;
1861 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
1862
1863 if (x < 0) {
1864 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
1865 x = 0;
1866 }
1867 if (y < 0) {
1868 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
1869 y = 0;
1870 }
1871
1872 WREG32(EVERGREEN_CUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
1873 WREG32(EVERGREEN_CUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
1874 WREG32(EVERGREEN_CUR_SIZE + amdgpu_crtc->crtc_offset,
1875 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
1876
1877 amdgpu_crtc->cursor_x = x;
1878 amdgpu_crtc->cursor_y = y;
1879 return 0;
1880}
1881
1882static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc,
1883 int x, int y)
1884{
1885 int ret;
1886
1887 dce_v6_0_lock_cursor(crtc, true);
1888 ret = dce_v6_0_cursor_move_locked(crtc, x, y);
1889 dce_v6_0_lock_cursor(crtc, false);
1890
1891 return ret;
1892}
1893
1894static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
1895 struct drm_file *file_priv,
1896 uint32_t handle,
1897 uint32_t width,
1898 uint32_t height,
1899 int32_t hot_x,
1900 int32_t hot_y)
1901{
1902 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1903 struct drm_gem_object *obj;
1904 struct amdgpu_bo *aobj;
1905 int ret;
1906
1907 if (!handle) {
1908 /* turn off cursor */
1909 dce_v6_0_hide_cursor(crtc);
1910 obj = NULL;
1911 goto unpin;
1912 }
1913
1914 if ((width > amdgpu_crtc->max_cursor_width) ||
1915 (height > amdgpu_crtc->max_cursor_height)) {
1916 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
1917 return -EINVAL;
1918 }
1919
1920 obj = drm_gem_object_lookup(file_priv, handle);
1921 if (!obj) {
1922 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
1923 return -ENOENT;
1924 }
1925
1926 aobj = gem_to_amdgpu_bo(obj);
1927 ret = amdgpu_bo_reserve(aobj, false);
1928 if (ret != 0) {
1929 drm_gem_object_unreference_unlocked(obj);
1930 return ret;
1931 }
1932
1933 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
1934 amdgpu_bo_unreserve(aobj);
1935 if (ret) {
1936 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
1937 drm_gem_object_unreference_unlocked(obj);
1938 return ret;
1939 }
1940
1941 amdgpu_crtc->cursor_width = width;
1942 amdgpu_crtc->cursor_height = height;
1943
1944 dce_v6_0_lock_cursor(crtc, true);
1945
1946 if (hot_x != amdgpu_crtc->cursor_hot_x ||
1947 hot_y != amdgpu_crtc->cursor_hot_y) {
1948 int x, y;
1949
1950 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
1951 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
1952
1953 dce_v6_0_cursor_move_locked(crtc, x, y);
1954
1955 amdgpu_crtc->cursor_hot_x = hot_x;
1956 amdgpu_crtc->cursor_hot_y = hot_y;
1957 }
1958
1959 dce_v6_0_show_cursor(crtc);
1960 dce_v6_0_lock_cursor(crtc, false);
1961
1962unpin:
1963 if (amdgpu_crtc->cursor_bo) {
1964 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1965 ret = amdgpu_bo_reserve(aobj, false);
1966 if (likely(ret == 0)) {
1967 amdgpu_bo_unpin(aobj);
1968 amdgpu_bo_unreserve(aobj);
1969 }
1970 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
1971 }
1972
1973 amdgpu_crtc->cursor_bo = obj;
1974 return 0;
1975}
1976
1977static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
1978{
1979 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1980
1981 if (amdgpu_crtc->cursor_bo) {
1982 dce_v6_0_lock_cursor(crtc, true);
1983
1984 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
1985 amdgpu_crtc->cursor_y);
1986
1987 dce_v6_0_show_cursor(crtc);
e2cdf640
KW		 1988 dce_v6_0_lock_cursor(crtc, false);
1989 }
1990}
1991
1992static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1993 u16 *blue, uint32_t size)
1994{
1995 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1996 int i;
1997
1998 /* userspace palettes are always correct as is */
1999 for (i = 0; i < size; i++) {
2000 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2001 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2002 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2003 }
2004 dce_v6_0_crtc_load_lut(crtc);
2005
2006 return 0;
2007}
2008
2009static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc)
2010{
2011 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2012
2013 drm_crtc_cleanup(crtc);
2014 kfree(amdgpu_crtc);
2015}
2016
2017static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = {
2018 .cursor_set2 = dce_v6_0_crtc_cursor_set2,
2019 .cursor_move = dce_v6_0_crtc_cursor_move,
2020 .gamma_set = dce_v6_0_crtc_gamma_set,
2021 .set_config = amdgpu_crtc_set_config,
2022 .destroy = dce_v6_0_crtc_destroy,
2023 .page_flip_target = amdgpu_crtc_page_flip_target,
2024};
2025
2026static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2027{
2028 struct drm_device *dev = crtc->dev;
2029 struct amdgpu_device *adev = dev->dev_private;
2030 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2031 unsigned type;
2032
2033 switch (mode) {
2034 case DRM_MODE_DPMS_ON:
2035 amdgpu_crtc->enabled = true;
2036 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2037 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2038 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2039 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2040 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2041 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2042 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2043 dce_v6_0_crtc_load_lut(crtc);
2044 break;
2045 case DRM_MODE_DPMS_STANDBY:
2046 case DRM_MODE_DPMS_SUSPEND:
2047 case DRM_MODE_DPMS_OFF:
2048 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2049 if (amdgpu_crtc->enabled)
2050 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2051 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2052 amdgpu_crtc->enabled = false;
2053 break;
2054 }
2055 /* adjust pm to dpms */
2056 amdgpu_pm_compute_clocks(adev);
2057}
2058
2059static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc)
2060{
2061 /* disable crtc pair power gating before programming */
2062 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2063 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2064 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2065}
2066
2067static void dce_v6_0_crtc_commit(struct drm_crtc *crtc)
2068{
2069 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2070 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2071}
2072
2073static void dce_v6_0_crtc_disable(struct drm_crtc *crtc)
2074{
2075
2076 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2077 struct drm_device *dev = crtc->dev;
2078 struct amdgpu_device *adev = dev->dev_private;
2079 struct amdgpu_atom_ss ss;
2080 int i;
2081
2082 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2083 if (crtc->primary->fb) {
2084 int r;
2085 struct amdgpu_framebuffer *amdgpu_fb;
765e7fbf 2086 struct amdgpu_bo *abo;
e2cdf640
KW		 2087
2088 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
765e7fbf
CK		 2089 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2090 r = amdgpu_bo_reserve(abo, false);
e2cdf640 2091 if (unlikely(r))
765e7fbf 2092 DRM_ERROR("failed to reserve abo before unpin\n");
e2cdf640 2093 else {
765e7fbf
CK		 2094 amdgpu_bo_unpin(abo);
2095 amdgpu_bo_unreserve(abo);
e2cdf640
KW		 2096 }
2097 }
2098 /* disable the GRPH */
2099 dce_v6_0_grph_enable(crtc, false);
2100
2101 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2102
2103 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2104 if (adev->mode_info.crtcs[i] &&
2105 adev->mode_info.crtcs[i]->enabled &&
2106 i != amdgpu_crtc->crtc_id &&
2107 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2108 /* one other crtc is using this pll don't turn
2109 * off the pll
2110 */
2111 goto done;
2112 }
2113 }
2114
2115 switch (amdgpu_crtc->pll_id) {
2116 case ATOM_PPLL1:
2117 case ATOM_PPLL2:
2118 /* disable the ppll */
2119 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2120 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2121 break;
2122 default:
2123 break;
2124 }
2125done:
2126 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2127 amdgpu_crtc->adjusted_clock = 0;
2128 amdgpu_crtc->encoder = NULL;
2129 amdgpu_crtc->connector = NULL;
2130}
2131
2132static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc,
2133 struct drm_display_mode *mode,
2134 struct drm_display_mode *adjusted_mode,
2135 int x, int y, struct drm_framebuffer *old_fb)
2136{
2137 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2138
2139 if (!amdgpu_crtc->adjusted_clock)
2140 return -EINVAL;
2141
2142 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2143 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2144 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2145 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2146 amdgpu_atombios_crtc_scaler_setup(crtc);
2147 dce_v6_0_cursor_reset(crtc);
2148 /* update the hw version fpr dpm */
2149 amdgpu_crtc->hw_mode = *adjusted_mode;
2150
2151 return 0;
2152}
2153
2154static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
2155 const struct drm_display_mode *mode,
2156 struct drm_display_mode *adjusted_mode)
2157{
2158
2159 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2160 struct drm_device *dev = crtc->dev;
2161 struct drm_encoder *encoder;
2162
2163 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2164 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2165 if (encoder->crtc == crtc) {
2166 amdgpu_crtc->encoder = encoder;
2167 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2168 break;
2169 }
2170 }
2171 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2172 amdgpu_crtc->encoder = NULL;
2173 amdgpu_crtc->connector = NULL;
2174 return false;
2175 }
2176 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2177 return false;
2178 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2179 return false;
2180 /* pick pll */
2181 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);
2182 /* if we can't get a PPLL for a non-DP encoder, fail */
2183 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2184 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2185 return false;
2186
2187 return true;
2188}
2189
2190static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2191 struct drm_framebuffer *old_fb)
2192{
2193 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2194}
2195
2196static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2197 struct drm_framebuffer *fb,
2198 int x, int y, enum mode_set_atomic state)
2199{
2200 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
2201}
2202
2203static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
2204 .dpms = dce_v6_0_crtc_dpms,
2205 .mode_fixup = dce_v6_0_crtc_mode_fixup,
2206 .mode_set = dce_v6_0_crtc_mode_set,
2207 .mode_set_base = dce_v6_0_crtc_set_base,
2208 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
2209 .prepare = dce_v6_0_crtc_prepare,
2210 .commit = dce_v6_0_crtc_commit,
2211 .load_lut = dce_v6_0_crtc_load_lut,
2212 .disable = dce_v6_0_crtc_disable,
2213};
2214
2215static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)
2216{
2217 struct amdgpu_crtc *amdgpu_crtc;
2218 int i;
2219
2220 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2221 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2222 if (amdgpu_crtc == NULL)
2223 return -ENOMEM;
2224
2225 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
2226
2227 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2228 amdgpu_crtc->crtc_id = index;
2229 adev->mode_info.crtcs[index] = amdgpu_crtc;
2230
2231 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;
2232 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;
2233 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2234 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2235
2236 for (i = 0; i < 256; i++) {
2237 amdgpu_crtc->lut_r[i] = i << 2;
2238 amdgpu_crtc->lut_g[i] = i << 2;
2239 amdgpu_crtc->lut_b[i] = i << 2;
2240 }
2241
2242 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2243
2244 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2245 amdgpu_crtc->adjusted_clock = 0;
2246 amdgpu_crtc->encoder = NULL;
2247 amdgpu_crtc->connector = NULL;
2248 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);
2249
2250 return 0;
2251}
2252
2253static int dce_v6_0_early_init(void *handle)
2254{
2255 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2256
2257 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg;
2258 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
2259
2260 dce_v6_0_set_display_funcs(adev);
2261 dce_v6_0_set_irq_funcs(adev);
2262
1d160f43
AD		 2263 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
2264
e2cdf640
KW		 2265 switch (adev->asic_type) {
2266 case CHIP_TAHITI:
2267 case CHIP_PITCAIRN:
2268 case CHIP_VERDE:
e2cdf640
KW		 2269 adev->mode_info.num_hpd = 6;
2270 adev->mode_info.num_dig = 6;
2271 break;
2272 case CHIP_OLAND:
e2cdf640
KW		 2273 adev->mode_info.num_hpd = 2;
2274 adev->mode_info.num_dig = 2;
2275 break;
2276 default:
e2cdf640
KW		 2277 return -EINVAL;
2278 }
2279
2280 return 0;
2281}
2282
2283static int dce_v6_0_sw_init(void *handle)
2284{
2285 int r, i;
2286 bool ret;
2287 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2288
2289 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2290 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2291 if (r)
2292 return r;
2293 }
2294
2295 for (i = 8; i < 20; i += 2) {
2296 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2297 if (r)
2298 return r;
2299 }
2300
2301 /* HPD hotplug */
2302 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2303 if (r)
2304 return r;
2305
2306 adev->mode_info.mode_config_initialized = true;
2307
2308 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
e2cdf640 2309 adev->ddev->mode_config.async_page_flip = true;
e2cdf640
KW		 2310 adev->ddev->mode_config.max_width = 16384;
2311 adev->ddev->mode_config.max_height = 16384;
e2cdf640
KW		 2312 adev->ddev->mode_config.preferred_depth = 24;
2313 adev->ddev->mode_config.prefer_shadow = 1;
e2cdf640
KW		 2314 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2315
2316 r = amdgpu_modeset_create_props(adev);
2317 if (r)
2318 return r;
2319
2320 adev->ddev->mode_config.max_width = 16384;
2321 adev->ddev->mode_config.max_height = 16384;
2322
2323 /* allocate crtcs */
2324 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2325 r = dce_v6_0_crtc_init(adev, i);
2326 if (r)
2327 return r;
2328 }
2329
2330 ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
2331 if (ret)
2332 amdgpu_print_display_setup(adev->ddev);
2333 else
2334 return -EINVAL;
2335
2336 /* setup afmt */
beb86f29
TSD		 2337 r = dce_v6_0_afmt_init(adev);
2338 if (r)
2339 return r;
e2cdf640
KW		 2340
2341 r = dce_v6_0_audio_init(adev);
2342 if (r)
2343 return r;
2344
2345 drm_kms_helper_poll_init(adev->ddev);
2346
2347 return r;
2348}
2349
2350static int dce_v6_0_sw_fini(void *handle)
2351{
2352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2353
2354 kfree(adev->mode_info.bios_hardcoded_edid);
2355
2356 drm_kms_helper_poll_fini(adev->ddev);
2357
2358 dce_v6_0_audio_fini(adev);
e2cdf640
KW		 2359 dce_v6_0_afmt_fini(adev);
2360
2361 drm_mode_config_cleanup(adev->ddev);
2362 adev->mode_info.mode_config_initialized = false;
2363
2364 return 0;
2365}
2366
2367static int dce_v6_0_hw_init(void *handle)
2368{
2369 int i;
2370 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2371
2372 /* init dig PHYs, disp eng pll */
2373 amdgpu_atombios_encoder_init_dig(adev);
2374 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2375
2376 /* initialize hpd */
2377 dce_v6_0_hpd_init(adev);
2378
2379 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2380 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2381 }
2382
2383 dce_v6_0_pageflip_interrupt_init(adev);
2384
2385 return 0;
2386}
2387
2388static int dce_v6_0_hw_fini(void *handle)
2389{
2390 int i;
2391 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2392
2393 dce_v6_0_hpd_fini(adev);
2394
2395 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2396 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2397 }
2398
2399 dce_v6_0_pageflip_interrupt_fini(adev);
2400
2401 return 0;
2402}
2403
2404static int dce_v6_0_suspend(void *handle)
2405{
e2cdf640
KW		 2406 return dce_v6_0_hw_fini(handle);
2407}
2408
2409static int dce_v6_0_resume(void *handle)
2410{
2411 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2412 int ret;
2413
2414 ret = dce_v6_0_hw_init(handle);
2415
e2cdf640
KW		 2416 /* turn on the BL */
2417 if (adev->mode_info.bl_encoder) {
2418 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2419 adev->mode_info.bl_encoder);
2420 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2421 bl_level);
2422 }
2423
2424 return ret;
2425}
2426
2427static bool dce_v6_0_is_idle(void *handle)
2428{
2429 return true;
2430}
2431
2432static int dce_v6_0_wait_for_idle(void *handle)
2433{
2434 return 0;
2435}
2436
2437static int dce_v6_0_soft_reset(void *handle)
2438{
2439 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
2440 return 0;
2441}
2442
2443static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2444 int crtc,
2445 enum amdgpu_interrupt_state state)
2446{
2447 u32 reg_block, interrupt_mask;
2448
2449 if (crtc >= adev->mode_info.num_crtc) {
2450 DRM_DEBUG("invalid crtc %d\n", crtc);
2451 return;
2452 }
2453
2454 switch (crtc) {
2455 case 0:
2456 reg_block = SI_CRTC0_REGISTER_OFFSET;
2457 break;
2458 case 1:
2459 reg_block = SI_CRTC1_REGISTER_OFFSET;
2460 break;
2461 case 2:
2462 reg_block = SI_CRTC2_REGISTER_OFFSET;
2463 break;
2464 case 3:
2465 reg_block = SI_CRTC3_REGISTER_OFFSET;
2466 break;
2467 case 4:
2468 reg_block = SI_CRTC4_REGISTER_OFFSET;
2469 break;
2470 case 5:
2471 reg_block = SI_CRTC5_REGISTER_OFFSET;
2472 break;
2473 default:
2474 DRM_DEBUG("invalid crtc %d\n", crtc);
2475 return;
2476 }
2477
2478 switch (state) {
2479 case AMDGPU_IRQ_STATE_DISABLE:
2480 interrupt_mask = RREG32(INT_MASK + reg_block);
2481 interrupt_mask &= ~VBLANK_INT_MASK;
2482 WREG32(INT_MASK + reg_block, interrupt_mask);
2483 break;
2484 case AMDGPU_IRQ_STATE_ENABLE:
2485 interrupt_mask = RREG32(INT_MASK + reg_block);
2486 interrupt_mask |= VBLANK_INT_MASK;
2487 WREG32(INT_MASK + reg_block, interrupt_mask);
2488 break;
2489 default:
2490 break;
2491 }
2492}
2493
2494static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2495 int crtc,
2496 enum amdgpu_interrupt_state state)
2497{
2498
2499}
2500
2501static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2502 struct amdgpu_irq_src *src,
2503 unsigned type,
2504 enum amdgpu_interrupt_state state)
2505{
34386043 2506 u32 dc_hpd_int_cntl;
e2cdf640 2507
34386043 2508 if (type >= adev->mode_info.num_hpd) {
e2cdf640
KW		 2509 DRM_DEBUG("invalid hdp %d\n", type);
2510 return 0;
2511 }
2512
2513 switch (state) {
2514 case AMDGPU_IRQ_STATE_DISABLE:
34386043 2515 dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]);
46c9cc11 2516 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
34386043 2517 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
e2cdf640
KW		 2518 break;
2519 case AMDGPU_IRQ_STATE_ENABLE:
34386043 2520 dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]);
46c9cc11 2521 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
34386043 2522 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
e2cdf640
KW		 2523 break;
2524 default:
2525 break;
2526 }
2527
2528 return 0;
2529}
2530
2531static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2532 struct amdgpu_irq_src *src,
2533 unsigned type,
2534 enum amdgpu_interrupt_state state)
2535{
2536 switch (type) {
2537 case AMDGPU_CRTC_IRQ_VBLANK1:
2538 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2539 break;
2540 case AMDGPU_CRTC_IRQ_VBLANK2:
2541 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state);
2542 break;
2543 case AMDGPU_CRTC_IRQ_VBLANK3:
2544 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state);
2545 break;
2546 case AMDGPU_CRTC_IRQ_VBLANK4:
2547 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state);
2548 break;
2549 case AMDGPU_CRTC_IRQ_VBLANK5:
2550 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state);
2551 break;
2552 case AMDGPU_CRTC_IRQ_VBLANK6:
2553 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state);
2554 break;
2555 case AMDGPU_CRTC_IRQ_VLINE1:
2556 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state);
2557 break;
2558 case AMDGPU_CRTC_IRQ_VLINE2:
2559 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state);
2560 break;
2561 case AMDGPU_CRTC_IRQ_VLINE3:
2562 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state);
2563 break;
2564 case AMDGPU_CRTC_IRQ_VLINE4:
2565 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state);
2566 break;
2567 case AMDGPU_CRTC_IRQ_VLINE5:
2568 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state);
2569 break;
2570 case AMDGPU_CRTC_IRQ_VLINE6:
2571 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state);
2572 break;
2573 default:
2574 break;
2575 }
2576 return 0;
2577}
2578
2579static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2580 struct amdgpu_irq_src *source,
2581 struct amdgpu_iv_entry *entry)
2582{
2583 unsigned crtc = entry->src_id - 1;
2584 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
2585 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
2586
2587 switch (entry->src_data) {
2588 case 0: /* vblank */
2589 if (disp_int & interrupt_status_offsets[crtc].vblank)
2590 WREG32(VBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
2591 else
2592 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2593
2594 if (amdgpu_irq_enabled(adev, source, irq_type)) {
2595 drm_handle_vblank(adev->ddev, crtc);
2596 }
2597 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
2598 break;
2599 case 1: /* vline */
2600 if (disp_int & interrupt_status_offsets[crtc].vline)
2601 WREG32(VLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
2602 else
2603 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2604
2605 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
2606 break;
2607 default:
2608 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
2609 break;
2610 }
2611
2612 return 0;
2613}
2614
2615static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
2616 struct amdgpu_irq_src *src,
2617 unsigned type,
2618 enum amdgpu_interrupt_state state)
2619{
2620 u32 reg;
2621
2622 if (type >= adev->mode_info.num_crtc) {
2623 DRM_ERROR("invalid pageflip crtc %d\n", type);
2624 return -EINVAL;
2625 }
2626
2627 reg = RREG32(GRPH_INT_CONTROL + crtc_offsets[type]);
2628 if (state == AMDGPU_IRQ_STATE_DISABLE)
2629 WREG32(GRPH_INT_CONTROL + crtc_offsets[type],
2630 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2631 else
2632 WREG32(GRPH_INT_CONTROL + crtc_offsets[type],
2633 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2634
2635 return 0;
2636}
2637
2638static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
2639 struct amdgpu_irq_src *source,
2640 struct amdgpu_iv_entry *entry)
2641{
2642 unsigned long flags;
2643 unsigned crtc_id;
2644 struct amdgpu_crtc *amdgpu_crtc;
2645 struct amdgpu_flip_work *works;
2646
2647 crtc_id = (entry->src_id - 8) >> 1;
2648 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
2649
2650 if (crtc_id >= adev->mode_info.num_crtc) {
2651 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
2652 return -EINVAL;
2653 }
2654
2655 if (RREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id]) &
2656 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
2657 WREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id],
2658 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
2659
2660 /* IRQ could occur when in initial stage */
2661 if (amdgpu_crtc == NULL)
2662 return 0;
2663
2664 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2665 works = amdgpu_crtc->pflip_works;
2666 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
2667 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
2668 "AMDGPU_FLIP_SUBMITTED(%d)\n",
2669 amdgpu_crtc->pflip_status,
2670 AMDGPU_FLIP_SUBMITTED);
2671 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2672 return 0;
2673 }
2674
2675 /* page flip completed. clean up */
2676 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
2677 amdgpu_crtc->pflip_works = NULL;
2678
2679 /* wakeup usersapce */
2680 if (works->event)
2681 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
2682
2683 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2684
2685 drm_crtc_vblank_put(&amdgpu_crtc->base);
2686 schedule_work(&works->unpin_work);
2687
2688 return 0;
2689}
2690
2691static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
2692 struct amdgpu_irq_src *source,
2693 struct amdgpu_iv_entry *entry)
2694{
34386043 2695 uint32_t disp_int, mask, tmp;
e2cdf640
KW		 2696 unsigned hpd;
2697
664a08bb 2698 if (entry->src_data >= adev->mode_info.num_hpd) {
e2cdf640
KW		 2699 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
2700 return 0;
2701 }
2702
2703 hpd = entry->src_data;
2704 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
2705 mask = interrupt_status_offsets[hpd].hpd;
e2cdf640
KW		 2706
2707 if (disp_int & mask) {
34386043 2708 tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
e2cdf640 2709 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
34386043 2710 WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
e2cdf640
KW		 2711 schedule_work(&adev->hotplug_work);
2712 DRM_INFO("IH: HPD%d\n", hpd + 1);
2713 }
2714
2715 return 0;
2716
2717}
2718
2719static int dce_v6_0_set_clockgating_state(void *handle,
2720 enum amd_clockgating_state state)
2721{
2722 return 0;
2723}
2724
2725static int dce_v6_0_set_powergating_state(void *handle,
2726 enum amd_powergating_state state)
2727{
2728 return 0;
2729}
2730
a1255107 2731static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
e2cdf640
KW		 2732 .name = "dce_v6_0",
2733 .early_init = dce_v6_0_early_init,
2734 .late_init = NULL,
2735 .sw_init = dce_v6_0_sw_init,
2736 .sw_fini = dce_v6_0_sw_fini,
2737 .hw_init = dce_v6_0_hw_init,
2738 .hw_fini = dce_v6_0_hw_fini,
2739 .suspend = dce_v6_0_suspend,
2740 .resume = dce_v6_0_resume,
2741 .is_idle = dce_v6_0_is_idle,
2742 .wait_for_idle = dce_v6_0_wait_for_idle,
2743 .soft_reset = dce_v6_0_soft_reset,
2744 .set_clockgating_state = dce_v6_0_set_clockgating_state,
2745 .set_powergating_state = dce_v6_0_set_powergating_state,
2746};
2747
2748static void
2749dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
2750 struct drm_display_mode *mode,
2751 struct drm_display_mode *adjusted_mode)
2752{
2753
2754 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2755
2756 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
2757
2758 /* need to call this here rather than in prepare() since we need some crtc info */
2759 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2760
2761 /* set scaler clears this on some chips */
2762 dce_v6_0_set_interleave(encoder->crtc, mode);
2763
2764 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2765 dce_v6_0_afmt_enable(encoder, true);
2766 dce_v6_0_afmt_setmode(encoder, adjusted_mode);
2767 }
2768}
2769
2770static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)
2771{
2772
2773 struct amdgpu_device *adev = encoder->dev->dev_private;
2774 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2775 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
2776
2777 if ((amdgpu_encoder->active_device &
2778 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2779 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
2780 ENCODER_OBJECT_ID_NONE)) {
2781 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2782 if (dig) {
2783 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder);
2784 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
2785 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
2786 }
2787 }
2788
2789 amdgpu_atombios_scratch_regs_lock(adev, true);
2790
2791 if (connector) {
2792 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
2793
2794 /* select the clock/data port if it uses a router */
2795 if (amdgpu_connector->router.cd_valid)
2796 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
2797
2798 /* turn eDP panel on for mode set */
2799 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2800 amdgpu_atombios_encoder_set_edp_panel_power(connector,
2801 ATOM_TRANSMITTER_ACTION_POWER_ON);
2802 }
2803
2804 /* this is needed for the pll/ss setup to work correctly in some cases */
2805 amdgpu_atombios_encoder_set_crtc_source(encoder);
2806 /* set up the FMT blocks */
2807 dce_v6_0_program_fmt(encoder);
2808}
2809
2810static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)
2811{
2812
2813 struct drm_device *dev = encoder->dev;
2814 struct amdgpu_device *adev = dev->dev_private;
2815
2816 /* need to call this here as we need the crtc set up */
2817 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2818 amdgpu_atombios_scratch_regs_lock(adev, false);
2819}
2820
2821static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)
2822{
2823
2824 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2825 struct amdgpu_encoder_atom_dig *dig;
2826
2827 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2828
2829 if (amdgpu_atombios_encoder_is_digital(encoder)) {
2830 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2831 dce_v6_0_afmt_enable(encoder, false);
2832 dig = amdgpu_encoder->enc_priv;
2833 dig->dig_encoder = -1;
2834 }
2835 amdgpu_encoder->active_device = 0;
2836}
2837
2838/* these are handled by the primary encoders */
2839static void dce_v6_0_ext_prepare(struct drm_encoder *encoder)
2840{
2841
2842}
2843
2844static void dce_v6_0_ext_commit(struct drm_encoder *encoder)
2845{
2846
2847}
2848
2849static void
2850dce_v6_0_ext_mode_set(struct drm_encoder *encoder,
2851 struct drm_display_mode *mode,
2852 struct drm_display_mode *adjusted_mode)
2853{
2854
2855}
2856
2857static void dce_v6_0_ext_disable(struct drm_encoder *encoder)
2858{
2859
2860}
2861
2862static void
2863dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)
2864{
2865
2866}
2867
2868static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder,
2869 const struct drm_display_mode *mode,
2870 struct drm_display_mode *adjusted_mode)
2871{
2872 return true;
2873}
2874
2875static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = {
2876 .dpms = dce_v6_0_ext_dpms,
2877 .mode_fixup = dce_v6_0_ext_mode_fixup,
2878 .prepare = dce_v6_0_ext_prepare,
2879 .mode_set = dce_v6_0_ext_mode_set,
2880 .commit = dce_v6_0_ext_commit,
2881 .disable = dce_v6_0_ext_disable,
2882 /* no detect for TMDS/LVDS yet */
2883};
2884
2885static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = {
2886 .dpms = amdgpu_atombios_encoder_dpms,
2887 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
2888 .prepare = dce_v6_0_encoder_prepare,
2889 .mode_set = dce_v6_0_encoder_mode_set,
2890 .commit = dce_v6_0_encoder_commit,
2891 .disable = dce_v6_0_encoder_disable,
2892 .detect = amdgpu_atombios_encoder_dig_detect,
2893};
2894
2895static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = {
2896 .dpms = amdgpu_atombios_encoder_dpms,
2897 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
2898 .prepare = dce_v6_0_encoder_prepare,
2899 .mode_set = dce_v6_0_encoder_mode_set,
2900 .commit = dce_v6_0_encoder_commit,
2901 .detect = amdgpu_atombios_encoder_dac_detect,
2902};
2903
2904static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder)
2905{
2906 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2907 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2908 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
2909 kfree(amdgpu_encoder->enc_priv);
2910 drm_encoder_cleanup(encoder);
2911 kfree(amdgpu_encoder);
2912}
2913
2914static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = {
2915 .destroy = dce_v6_0_encoder_destroy,
2916};
2917
2918static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
2919 uint32_t encoder_enum,
2920 uint32_t supported_device,
2921 u16 caps)
2922{
2923 struct drm_device *dev = adev->ddev;
2924 struct drm_encoder *encoder;
2925 struct amdgpu_encoder *amdgpu_encoder;
2926
2927 /* see if we already added it */
2928 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2929 amdgpu_encoder = to_amdgpu_encoder(encoder);
2930 if (amdgpu_encoder->encoder_enum == encoder_enum) {
2931 amdgpu_encoder->devices |= supported_device;
2932 return;
2933 }
2934
2935 }
2936
2937 /* add a new one */
2938 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
2939 if (!amdgpu_encoder)
2940 return;
2941
2942 encoder = &amdgpu_encoder->base;
2943 switch (adev->mode_info.num_crtc) {
2944 case 1:
2945 encoder->possible_crtcs = 0x1;
2946 break;
2947 case 2:
2948 default:
2949 encoder->possible_crtcs = 0x3;
2950 break;
2951 case 4:
2952 encoder->possible_crtcs = 0xf;
2953 break;
2954 case 6:
2955 encoder->possible_crtcs = 0x3f;
2956 break;
2957 }
2958
2959 amdgpu_encoder->enc_priv = NULL;
e2cdf640
KW		 2960 amdgpu_encoder->encoder_enum = encoder_enum;
2961 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2962 amdgpu_encoder->devices = supported_device;
2963 amdgpu_encoder->rmx_type = RMX_OFF;
2964 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
2965 amdgpu_encoder->is_ext_encoder = false;
2966 amdgpu_encoder->caps = caps;
2967
2968 switch (amdgpu_encoder->encoder_id) {
2969 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2970 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2971 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2972 DRM_MODE_ENCODER_DAC, NULL);
2973 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs);
2974 break;
2975 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2976 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2977 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2978 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2979 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2980 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2981 amdgpu_encoder->rmx_type = RMX_FULL;
2982 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2983 DRM_MODE_ENCODER_LVDS, NULL);
2984 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
2985 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2986 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2987 DRM_MODE_ENCODER_DAC, NULL);
2988 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
2989 } else {
2990 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2991 DRM_MODE_ENCODER_TMDS, NULL);
2992 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
2993 }
2994 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs);
2995 break;
2996 case ENCODER_OBJECT_ID_SI170B:
2997 case ENCODER_OBJECT_ID_CH7303:
2998 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2999 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3000 case ENCODER_OBJECT_ID_TITFP513:
3001 case ENCODER_OBJECT_ID_VT1623:
3002 case ENCODER_OBJECT_ID_HDMI_SI1930:
3003 case ENCODER_OBJECT_ID_TRAVIS:
3004 case ENCODER_OBJECT_ID_NUTMEG:
3005 /* these are handled by the primary encoders */
3006 amdgpu_encoder->is_ext_encoder = true;
3007 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3008 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3009 DRM_MODE_ENCODER_LVDS, NULL);
3010 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3011 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3012 DRM_MODE_ENCODER_DAC, NULL);
3013 else
3014 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3015 DRM_MODE_ENCODER_TMDS, NULL);
3016 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs);
3017 break;
3018 }
3019}
3020
3021static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3022 .set_vga_render_state = &dce_v6_0_set_vga_render_state,
3023 .bandwidth_update = &dce_v6_0_bandwidth_update,
3024 .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3025 .vblank_wait = &dce_v6_0_vblank_wait,
3026 .is_display_hung = &dce_v6_0_is_display_hung,
3027 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3028 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3029 .hpd_sense = &dce_v6_0_hpd_sense,
3030 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity,
3031 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg,
3032 .page_flip = &dce_v6_0_page_flip,
3033 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos,
3034 .add_encoder = &dce_v6_0_encoder_add,
3035 .add_connector = &amdgpu_connector_add,
3036 .stop_mc_access = &dce_v6_0_stop_mc_access,
3037 .resume_mc_access = &dce_v6_0_resume_mc_access,
3038};
3039
3040static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
3041{
3042 if (adev->mode_info.funcs == NULL)
3043 adev->mode_info.funcs = &dce_v6_0_display_funcs;
3044}
3045
3046static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
3047 .set = dce_v6_0_set_crtc_interrupt_state,
3048 .process = dce_v6_0_crtc_irq,
3049};
3050
3051static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = {
3052 .set = dce_v6_0_set_pageflip_interrupt_state,
3053 .process = dce_v6_0_pageflip_irq,
3054};
3055
3056static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {
3057 .set = dce_v6_0_set_hpd_interrupt_state,
3058 .process = dce_v6_0_hpd_irq,
3059};
3060
3061static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3062{
3063 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3064 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
3065
3066 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3067 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
3068
3069 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3070 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
3071}
a1255107
AD		 3072
3073const struct amdgpu_ip_block_version dce_v6_0_ip_block =
3074{
3075 .type = AMD_IP_BLOCK_TYPE_DCE,
3076 .major = 6,
3077 .minor = 0,
3078 .rev = 0,
3079 .funcs = &dce_v6_0_ip_funcs,
3080};
3081
3082const struct amdgpu_ip_block_version dce_v6_4_ip_block =
3083{
3084 .type = AMD_IP_BLOCK_TYPE_DCE,
3085 .major = 6,
3086 .minor = 4,
3087 .rev = 0,
3088 .funcs = &dce_v6_0_ip_funcs,
3089};
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