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drm/amdgpu: Provide page_flip_target hook
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / dce_v8_0.c
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a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "cikd.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34
35#include "dce/dce_8_0_d.h"
36#include "dce/dce_8_0_sh_mask.h"
37
38#include "gca/gfx_7_2_enum.h"
39
40#include "gmc/gmc_7_1_d.h"
41#include "gmc/gmc_7_1_sh_mask.h"
42
43#include "oss/oss_2_0_d.h"
44#include "oss/oss_2_0_sh_mask.h"
45
46static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
47static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
48
49static const u32 crtc_offsets[6] =
50{
51 CRTC0_REGISTER_OFFSET,
52 CRTC1_REGISTER_OFFSET,
53 CRTC2_REGISTER_OFFSET,
54 CRTC3_REGISTER_OFFSET,
55 CRTC4_REGISTER_OFFSET,
56 CRTC5_REGISTER_OFFSET
57};
58
59static const uint32_t dig_offsets[] = {
60 CRTC0_REGISTER_OFFSET,
61 CRTC1_REGISTER_OFFSET,
62 CRTC2_REGISTER_OFFSET,
63 CRTC3_REGISTER_OFFSET,
64 CRTC4_REGISTER_OFFSET,
65 CRTC5_REGISTER_OFFSET,
66 (0x13830 - 0x7030) >> 2,
67};
68
69static const struct {
70 uint32_t reg;
71 uint32_t vblank;
72 uint32_t vline;
73 uint32_t hpd;
74
75} interrupt_status_offsets[6] = { {
76 .reg = mmDISP_INTERRUPT_STATUS,
77 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
78 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
80}, {
81 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
83 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
85}, {
86 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
90}, {
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
95}, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
100}, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
105} };
106
107static const uint32_t hpd_int_control_offsets[6] = {
108 mmDC_HPD1_INT_CONTROL,
109 mmDC_HPD2_INT_CONTROL,
110 mmDC_HPD3_INT_CONTROL,
111 mmDC_HPD4_INT_CONTROL,
112 mmDC_HPD5_INT_CONTROL,
113 mmDC_HPD6_INT_CONTROL,
114};
115
116static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
117 u32 block_offset, u32 reg)
118{
119 unsigned long flags;
120 u32 r;
121
122 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
124 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
125 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
126
127 return r;
128}
129
130static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
131 u32 block_offset, u32 reg, u32 v)
132{
133 unsigned long flags;
134
135 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
138 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
139}
140
141static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
142{
143 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
144 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
145 return true;
146 else
147 return false;
148}
149
150static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
151{
152 u32 pos1, pos2;
153
154 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
155 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
156
157 if (pos1 != pos2)
158 return true;
159 else
160 return false;
161}
162
163/**
164 * dce_v8_0_vblank_wait - vblank wait asic callback.
165 *
166 * @adev: amdgpu_device pointer
167 * @crtc: crtc to wait for vblank on
168 *
169 * Wait for vblank on the requested crtc (evergreen+).
170 */
171static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
172{
173 unsigned i = 0;
174
175 if (crtc >= adev->mode_info.num_crtc)
176 return;
177
178 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
179 return;
180
181 /* depending on when we hit vblank, we may be close to active; if so,
182 * wait for another frame.
183 */
184 while (dce_v8_0_is_in_vblank(adev, crtc)) {
185 if (i++ % 100 == 0) {
186 if (!dce_v8_0_is_counter_moving(adev, crtc))
187 break;
188 }
189 }
190
191 while (!dce_v8_0_is_in_vblank(adev, crtc)) {
192 if (i++ % 100 == 0) {
193 if (!dce_v8_0_is_counter_moving(adev, crtc))
194 break;
195 }
196 }
197}
198
199static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
200{
201 if (crtc >= adev->mode_info.num_crtc)
202 return 0;
203 else
204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
205}
206
f6c7aba4
MD		 207static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
208{
209 unsigned i;
210
211 /* Enable pflip interrupts */
212 for (i = 0; i < adev->mode_info.num_crtc; i++)
213 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
214}
215
216static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
217{
218 unsigned i;
219
220 /* Disable pflip interrupts */
221 for (i = 0; i < adev->mode_info.num_crtc; i++)
222 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
223}
224
a2e73f56
AD		 225/**
226 * dce_v8_0_page_flip - pageflip callback.
227 *
228 * @adev: amdgpu_device pointer
229 * @crtc_id: crtc to cleanup pageflip on
230 * @crtc_base: new address of the crtc (GPU MC address)
231 *
82326860
AD		 232 * Triggers the actual pageflip by updating the primary
233 * surface base address.
a2e73f56
AD		 234 */
235static void dce_v8_0_page_flip(struct amdgpu_device *adev,
cb9e59d7 236 int crtc_id, u64 crtc_base, bool async)
a2e73f56
AD		 237{
238 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
a2e73f56 239
cb9e59d7
AD		 240 /* flip at hsync for async, default is vsync */
241 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
242 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
82326860 243 /* update the primary scanout addresses */
a2e73f56
AD		 244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
245 upper_32_bits(crtc_base));
82326860 246 /* writing to the low address triggers the update */
a2e73f56 247 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
82326860
AD		 248 lower_32_bits(crtc_base));
249 /* post the write */
250 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
a2e73f56
AD		 251}
252
253static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
254 u32 *vbl, u32 *position)
255{
256 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
257 return -EINVAL;
258
259 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
260 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
261
262 return 0;
263}
264
265/**
266 * dce_v8_0_hpd_sense - hpd sense callback.
267 *
268 * @adev: amdgpu_device pointer
269 * @hpd: hpd (hotplug detect) pin
270 *
271 * Checks if a digital monitor is connected (evergreen+).
272 * Returns true if connected, false if not connected.
273 */
274static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
275 enum amdgpu_hpd_id hpd)
276{
277 bool connected = false;
278
279 switch (hpd) {
280 case AMDGPU_HPD_1:
281 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
282 connected = true;
283 break;
284 case AMDGPU_HPD_2:
285 if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK)
286 connected = true;
287 break;
288 case AMDGPU_HPD_3:
289 if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK)
290 connected = true;
291 break;
292 case AMDGPU_HPD_4:
293 if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK)
294 connected = true;
295 break;
296 case AMDGPU_HPD_5:
297 if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK)
298 connected = true;
299 break;
300 case AMDGPU_HPD_6:
301 if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK)
302 connected = true;
303 break;
304 default:
305 break;
306 }
307
308 return connected;
309}
310
311/**
312 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
313 *
314 * @adev: amdgpu_device pointer
315 * @hpd: hpd (hotplug detect) pin
316 *
317 * Set the polarity of the hpd pin (evergreen+).
318 */
319static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
320 enum amdgpu_hpd_id hpd)
321{
322 u32 tmp;
323 bool connected = dce_v8_0_hpd_sense(adev, hpd);
324
325 switch (hpd) {
326 case AMDGPU_HPD_1:
327 tmp = RREG32(mmDC_HPD1_INT_CONTROL);
328 if (connected)
329 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
330 else
331 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
332 WREG32(mmDC_HPD1_INT_CONTROL, tmp);
333 break;
334 case AMDGPU_HPD_2:
335 tmp = RREG32(mmDC_HPD2_INT_CONTROL);
336 if (connected)
337 tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
338 else
339 tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
340 WREG32(mmDC_HPD2_INT_CONTROL, tmp);
341 break;
342 case AMDGPU_HPD_3:
343 tmp = RREG32(mmDC_HPD3_INT_CONTROL);
344 if (connected)
345 tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
346 else
347 tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
348 WREG32(mmDC_HPD3_INT_CONTROL, tmp);
349 break;
350 case AMDGPU_HPD_4:
351 tmp = RREG32(mmDC_HPD4_INT_CONTROL);
352 if (connected)
353 tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
354 else
355 tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
356 WREG32(mmDC_HPD4_INT_CONTROL, tmp);
357 break;
358 case AMDGPU_HPD_5:
359 tmp = RREG32(mmDC_HPD5_INT_CONTROL);
360 if (connected)
361 tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
362 else
363 tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
364 WREG32(mmDC_HPD5_INT_CONTROL, tmp);
365 break;
366 case AMDGPU_HPD_6:
367 tmp = RREG32(mmDC_HPD6_INT_CONTROL);
368 if (connected)
369 tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
370 else
371 tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
372 WREG32(mmDC_HPD6_INT_CONTROL, tmp);
373 break;
374 default:
375 break;
376 }
377}
378
379/**
380 * dce_v8_0_hpd_init - hpd setup callback.
381 *
382 * @adev: amdgpu_device pointer
383 *
384 * Setup the hpd pins used by the card (evergreen+).
385 * Enable the pin, set the polarity, and enable the hpd interrupts.
386 */
387static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
388{
389 struct drm_device *dev = adev->ddev;
390 struct drm_connector *connector;
391 u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) |
392 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) |
393 DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
394
395 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
396 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
397
398 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
399 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
400 /* don't try to enable hpd on eDP or LVDS avoid breaking the
401 * aux dp channel on imac and help (but not completely fix)
402 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
403 * also avoid interrupt storms during dpms.
404 */
405 continue;
406 }
407 switch (amdgpu_connector->hpd.hpd) {
408 case AMDGPU_HPD_1:
409 WREG32(mmDC_HPD1_CONTROL, tmp);
410 break;
411 case AMDGPU_HPD_2:
412 WREG32(mmDC_HPD2_CONTROL, tmp);
413 break;
414 case AMDGPU_HPD_3:
415 WREG32(mmDC_HPD3_CONTROL, tmp);
416 break;
417 case AMDGPU_HPD_4:
418 WREG32(mmDC_HPD4_CONTROL, tmp);
419 break;
420 case AMDGPU_HPD_5:
421 WREG32(mmDC_HPD5_CONTROL, tmp);
422 break;
423 case AMDGPU_HPD_6:
424 WREG32(mmDC_HPD6_CONTROL, tmp);
425 break;
426 default:
427 break;
428 }
429 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
430 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
431 }
432}
433
434/**
435 * dce_v8_0_hpd_fini - hpd tear down callback.
436 *
437 * @adev: amdgpu_device pointer
438 *
439 * Tear down the hpd pins used by the card (evergreen+).
440 * Disable the hpd interrupts.
441 */
442static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
443{
444 struct drm_device *dev = adev->ddev;
445 struct drm_connector *connector;
446
447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
448 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
449
450 switch (amdgpu_connector->hpd.hpd) {
451 case AMDGPU_HPD_1:
452 WREG32(mmDC_HPD1_CONTROL, 0);
453 break;
454 case AMDGPU_HPD_2:
455 WREG32(mmDC_HPD2_CONTROL, 0);
456 break;
457 case AMDGPU_HPD_3:
458 WREG32(mmDC_HPD3_CONTROL, 0);
459 break;
460 case AMDGPU_HPD_4:
461 WREG32(mmDC_HPD4_CONTROL, 0);
462 break;
463 case AMDGPU_HPD_5:
464 WREG32(mmDC_HPD5_CONTROL, 0);
465 break;
466 case AMDGPU_HPD_6:
467 WREG32(mmDC_HPD6_CONTROL, 0);
468 break;
469 default:
470 break;
471 }
472 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
473 }
474}
475
476static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
477{
478 return mmDC_GPIO_HPD_A;
479}
480
481static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
482{
483 u32 crtc_hung = 0;
484 u32 crtc_status[6];
485 u32 i, j, tmp;
486
487 for (i = 0; i < adev->mode_info.num_crtc; i++) {
488 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
489 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
490 crtc_hung |= (1 << i);
491 }
492 }
493
494 for (j = 0; j < 10; j++) {
495 for (i = 0; i < adev->mode_info.num_crtc; i++) {
496 if (crtc_hung & (1 << i)) {
497 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
498 if (tmp != crtc_status[i])
499 crtc_hung &= ~(1 << i);
500 }
501 }
502 if (crtc_hung == 0)
503 return false;
504 udelay(100);
505 }
506
507 return true;
508}
509
510static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
511 struct amdgpu_mode_mc_save *save)
512{
513 u32 crtc_enabled, tmp;
514 int i;
515
516 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
517 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
518
519 /* disable VGA render */
520 tmp = RREG32(mmVGA_RENDER_CONTROL);
521 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
522 WREG32(mmVGA_RENDER_CONTROL, tmp);
523
524 /* blank the display controllers */
525 for (i = 0; i < adev->mode_info.num_crtc; i++) {
526 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
527 CRTC_CONTROL, CRTC_MASTER_EN);
528 if (crtc_enabled) {
5a3f25db 529#if 1
a2e73f56
AD		 530 save->crtc_enabled[i] = true;
531 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
532 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
5a3f25db
JZ		 533 /*it is correct only for RGB ; black is 0*/
534 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
a2e73f56
AD		 535 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
536 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
a2e73f56 537 }
5a3f25db 538 mdelay(20);
a2e73f56
AD		 539#else
540 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
541 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
542 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
543 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
544 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
545 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
546 save->crtc_enabled[i] = false;
547 /* ***** */
548#endif
549 } else {
550 save->crtc_enabled[i] = false;
551 }
552 }
553}
554
555static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
556 struct amdgpu_mode_mc_save *save)
557{
5a3f25db
JZ		 558 u32 tmp;
559 int i;
a2e73f56
AD		 560
561 /* update crtc base addresses */
562 for (i = 0; i < adev->mode_info.num_crtc; i++) {
563 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
564 upper_32_bits(adev->mc.vram_start));
a2e73f56
AD		 565 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
566 (u32)adev->mc.vram_start);
a2e73f56
AD		 567
568 if (save->crtc_enabled[i]) {
a2e73f56
AD		 569 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
570 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
a2e73f56 571 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
a2e73f56 572 }
5a3f25db 573 mdelay(20);
a2e73f56
AD		 574 }
575
576 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
577 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
578
579 /* Unlock vga access */
580 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
581 mdelay(1);
582 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
583}
584
585static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
586 bool render)
587{
588 u32 tmp;
589
590 /* Lockout access through VGA aperture*/
591 tmp = RREG32(mmVGA_HDP_CONTROL);
592 if (render)
593 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
594 else
595 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
596 WREG32(mmVGA_HDP_CONTROL, tmp);
597
598 /* disable VGA render */
599 tmp = RREG32(mmVGA_RENDER_CONTROL);
600 if (render)
601 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
602 else
603 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
604 WREG32(mmVGA_RENDER_CONTROL, tmp);
605}
606
83c9b025
ED		 607static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
608{
609 int num_crtc = 0;
610
611 switch (adev->asic_type) {
612 case CHIP_BONAIRE:
613 case CHIP_HAWAII:
614 num_crtc = 6;
615 break;
616 case CHIP_KAVERI:
617 num_crtc = 4;
618 break;
619 case CHIP_KABINI:
620 case CHIP_MULLINS:
621 num_crtc = 2;
622 break;
623 default:
624 num_crtc = 0;
625 }
626 return num_crtc;
627}
628
629void dce_v8_0_disable_dce(struct amdgpu_device *adev)
630{
631 /*Disable VGA render and enabled crtc, if has DCE engine*/
632 if (amdgpu_atombios_has_dce_engine_info(adev)) {
633 u32 tmp;
634 int crtc_enabled, i;
635
636 dce_v8_0_set_vga_render_state(adev, false);
637
638 /*Disable crtc*/
639 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
640 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
641 CRTC_CONTROL, CRTC_MASTER_EN);
642 if (crtc_enabled) {
643 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
644 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
645 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
646 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
647 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
648 }
649 }
650 }
651}
652
a2e73f56
AD		 653static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
654{
655 struct drm_device *dev = encoder->dev;
656 struct amdgpu_device *adev = dev->dev_private;
657 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
658 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
659 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
660 int bpc = 0;
661 u32 tmp = 0;
662 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
663
664 if (connector) {
665 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
666 bpc = amdgpu_connector_get_monitor_bpc(connector);
667 dither = amdgpu_connector->dither;
668 }
669
670 /* LVDS/eDP FMT is set up by atom */
671 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
672 return;
673
674 /* not needed for analog */
675 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
676 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
677 return;
678
679 if (bpc == 0)
680 return;
681
682 switch (bpc) {
683 case 6:
684 if (dither == AMDGPU_FMT_DITHER_ENABLE)
685 /* XXX sort out optimal dither settings */
686 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
687 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
688 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
689 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
690 else
691 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
692 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
693 break;
694 case 8:
695 if (dither == AMDGPU_FMT_DITHER_ENABLE)
696 /* XXX sort out optimal dither settings */
697 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
698 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
699 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
700 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
701 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
702 else
703 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
704 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
705 break;
706 case 10:
707 if (dither == AMDGPU_FMT_DITHER_ENABLE)
708 /* XXX sort out optimal dither settings */
709 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
710 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
711 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
712 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
713 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
714 else
715 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
716 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
717 break;
718 default:
719 /* not needed */
720 break;
721 }
722
723 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
724}
725
726
727/* display watermark setup */
728/**
729 * dce_v8_0_line_buffer_adjust - Set up the line buffer
730 *
731 * @adev: amdgpu_device pointer
732 * @amdgpu_crtc: the selected display controller
733 * @mode: the current display mode on the selected display
734 * controller
735 *
736 * Setup up the line buffer allocation for
737 * the selected display controller (CIK).
738 * Returns the line buffer size in pixels.
739 */
740static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
741 struct amdgpu_crtc *amdgpu_crtc,
742 struct drm_display_mode *mode)
743{
744 u32 tmp, buffer_alloc, i;
745 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
746 /*
747 * Line Buffer Setup
748 * There are 6 line buffers, one for each display controllers.
749 * There are 3 partitions per LB. Select the number of partitions
750 * to enable based on the display width. For display widths larger
751 * than 4096, you need use to use 2 display controllers and combine
752 * them using the stereo blender.
753 */
754 if (amdgpu_crtc->base.enabled && mode) {
755 if (mode->crtc_hdisplay < 1920) {
756 tmp = 1;
757 buffer_alloc = 2;
758 } else if (mode->crtc_hdisplay < 2560) {
759 tmp = 2;
760 buffer_alloc = 2;
761 } else if (mode->crtc_hdisplay < 4096) {
762 tmp = 0;
2f7d10b3 763 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
a2e73f56
AD		 764 } else {
765 DRM_DEBUG_KMS("Mode too big for LB!\n");
766 tmp = 0;
2f7d10b3 767 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
a2e73f56
AD		 768 }
769 } else {
770 tmp = 1;
771 buffer_alloc = 0;
772 }
773
774 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
775 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
776 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
777
778 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
779 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
780 for (i = 0; i < adev->usec_timeout; i++) {
781 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
782 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
783 break;
784 udelay(1);
785 }
786
787 if (amdgpu_crtc->base.enabled && mode) {
788 switch (tmp) {
789 case 0:
790 default:
791 return 4096 * 2;
792 case 1:
793 return 1920 * 2;
794 case 2:
795 return 2560 * 2;
796 }
797 }
798
799 /* controller not enabled, so no lb used */
800 return 0;
801}
802
803/**
804 * cik_get_number_of_dram_channels - get the number of dram channels
805 *
806 * @adev: amdgpu_device pointer
807 *
808 * Look up the number of video ram channels (CIK).
809 * Used for display watermark bandwidth calculations
810 * Returns the number of dram channels
811 */
812static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
813{
814 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
815
816 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
817 case 0:
818 default:
819 return 1;
820 case 1:
821 return 2;
822 case 2:
823 return 4;
824 case 3:
825 return 8;
826 case 4:
827 return 3;
828 case 5:
829 return 6;
830 case 6:
831 return 10;
832 case 7:
833 return 12;
834 case 8:
835 return 16;
836 }
837}
838
839struct dce8_wm_params {
840 u32 dram_channels; /* number of dram channels */
841 u32 yclk; /* bandwidth per dram data pin in kHz */
842 u32 sclk; /* engine clock in kHz */
843 u32 disp_clk; /* display clock in kHz */
844 u32 src_width; /* viewport width */
845 u32 active_time; /* active display time in ns */
846 u32 blank_time; /* blank time in ns */
847 bool interlaced; /* mode is interlaced */
848 fixed20_12 vsc; /* vertical scale ratio */
849 u32 num_heads; /* number of active crtcs */
850 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
851 u32 lb_size; /* line buffer allocated to pipe */
852 u32 vtaps; /* vertical scaler taps */
853};
854
855/**
856 * dce_v8_0_dram_bandwidth - get the dram bandwidth
857 *
858 * @wm: watermark calculation data
859 *
860 * Calculate the raw dram bandwidth (CIK).
861 * Used for display watermark bandwidth calculations
862 * Returns the dram bandwidth in MBytes/s
863 */
864static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
865{
866 /* Calculate raw DRAM Bandwidth */
867 fixed20_12 dram_efficiency; /* 0.7 */
868 fixed20_12 yclk, dram_channels, bandwidth;
869 fixed20_12 a;
870
871 a.full = dfixed_const(1000);
872 yclk.full = dfixed_const(wm->yclk);
873 yclk.full = dfixed_div(yclk, a);
874 dram_channels.full = dfixed_const(wm->dram_channels * 4);
875 a.full = dfixed_const(10);
876 dram_efficiency.full = dfixed_const(7);
877 dram_efficiency.full = dfixed_div(dram_efficiency, a);
878 bandwidth.full = dfixed_mul(dram_channels, yclk);
879 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
880
881 return dfixed_trunc(bandwidth);
882}
883
884/**
885 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
886 *
887 * @wm: watermark calculation data
888 *
889 * Calculate the dram bandwidth used for display (CIK).
890 * Used for display watermark bandwidth calculations
891 * Returns the dram bandwidth for display in MBytes/s
892 */
893static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
894{
895 /* Calculate DRAM Bandwidth and the part allocated to display. */
896 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
897 fixed20_12 yclk, dram_channels, bandwidth;
898 fixed20_12 a;
899
900 a.full = dfixed_const(1000);
901 yclk.full = dfixed_const(wm->yclk);
902 yclk.full = dfixed_div(yclk, a);
903 dram_channels.full = dfixed_const(wm->dram_channels * 4);
904 a.full = dfixed_const(10);
905 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
906 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
907 bandwidth.full = dfixed_mul(dram_channels, yclk);
908 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
909
910 return dfixed_trunc(bandwidth);
911}
912
913/**
914 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
915 *
916 * @wm: watermark calculation data
917 *
918 * Calculate the data return bandwidth used for display (CIK).
919 * Used for display watermark bandwidth calculations
920 * Returns the data return bandwidth in MBytes/s
921 */
922static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
923{
924 /* Calculate the display Data return Bandwidth */
925 fixed20_12 return_efficiency; /* 0.8 */
926 fixed20_12 sclk, bandwidth;
927 fixed20_12 a;
928
929 a.full = dfixed_const(1000);
930 sclk.full = dfixed_const(wm->sclk);
931 sclk.full = dfixed_div(sclk, a);
932 a.full = dfixed_const(10);
933 return_efficiency.full = dfixed_const(8);
934 return_efficiency.full = dfixed_div(return_efficiency, a);
935 a.full = dfixed_const(32);
936 bandwidth.full = dfixed_mul(a, sclk);
937 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
938
939 return dfixed_trunc(bandwidth);
940}
941
942/**
943 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
944 *
945 * @wm: watermark calculation data
946 *
947 * Calculate the dmif bandwidth used for display (CIK).
948 * Used for display watermark bandwidth calculations
949 * Returns the dmif bandwidth in MBytes/s
950 */
951static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
952{
953 /* Calculate the DMIF Request Bandwidth */
954 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
955 fixed20_12 disp_clk, bandwidth;
956 fixed20_12 a, b;
957
958 a.full = dfixed_const(1000);
959 disp_clk.full = dfixed_const(wm->disp_clk);
960 disp_clk.full = dfixed_div(disp_clk, a);
961 a.full = dfixed_const(32);
962 b.full = dfixed_mul(a, disp_clk);
963
964 a.full = dfixed_const(10);
965 disp_clk_request_efficiency.full = dfixed_const(8);
966 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
967
968 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
969
970 return dfixed_trunc(bandwidth);
971}
972
973/**
974 * dce_v8_0_available_bandwidth - get the min available bandwidth
975 *
976 * @wm: watermark calculation data
977 *
978 * Calculate the min available bandwidth used for display (CIK).
979 * Used for display watermark bandwidth calculations
980 * Returns the min available bandwidth in MBytes/s
981 */
982static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
983{
984 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
985 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
986 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
987 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
988
989 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
990}
991
992/**
993 * dce_v8_0_average_bandwidth - get the average available bandwidth
994 *
995 * @wm: watermark calculation data
996 *
997 * Calculate the average available bandwidth used for display (CIK).
998 * Used for display watermark bandwidth calculations
999 * Returns the average available bandwidth in MBytes/s
1000 */
1001static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
1002{
1003 /* Calculate the display mode Average Bandwidth
1004 * DisplayMode should contain the source and destination dimensions,
1005 * timing, etc.
1006 */
1007 fixed20_12 bpp;
1008 fixed20_12 line_time;
1009 fixed20_12 src_width;
1010 fixed20_12 bandwidth;
1011 fixed20_12 a;
1012
1013 a.full = dfixed_const(1000);
1014 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1015 line_time.full = dfixed_div(line_time, a);
1016 bpp.full = dfixed_const(wm->bytes_per_pixel);
1017 src_width.full = dfixed_const(wm->src_width);
1018 bandwidth.full = dfixed_mul(src_width, bpp);
1019 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1020 bandwidth.full = dfixed_div(bandwidth, line_time);
1021
1022 return dfixed_trunc(bandwidth);
1023}
1024
1025/**
1026 * dce_v8_0_latency_watermark - get the latency watermark
1027 *
1028 * @wm: watermark calculation data
1029 *
1030 * Calculate the latency watermark (CIK).
1031 * Used for display watermark bandwidth calculations
1032 * Returns the latency watermark in ns
1033 */
1034static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
1035{
1036 /* First calculate the latency in ns */
1037 u32 mc_latency = 2000; /* 2000 ns. */
1038 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
1039 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1040 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1041 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1042 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1043 (wm->num_heads * cursor_line_pair_return_time);
1044 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1045 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1046 u32 tmp, dmif_size = 12288;
1047 fixed20_12 a, b, c;
1048
1049 if (wm->num_heads == 0)
1050 return 0;
1051
1052 a.full = dfixed_const(2);
1053 b.full = dfixed_const(1);
1054 if ((wm->vsc.full > a.full) ||
1055 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1056 (wm->vtaps >= 5) ||
1057 ((wm->vsc.full >= a.full) && wm->interlaced))
1058 max_src_lines_per_dst_line = 4;
1059 else
1060 max_src_lines_per_dst_line = 2;
1061
1062 a.full = dfixed_const(available_bandwidth);
1063 b.full = dfixed_const(wm->num_heads);
1064 a.full = dfixed_div(a, b);
1065
1066 b.full = dfixed_const(mc_latency + 512);
1067 c.full = dfixed_const(wm->disp_clk);
1068 b.full = dfixed_div(b, c);
1069
1070 c.full = dfixed_const(dmif_size);
1071 b.full = dfixed_div(c, b);
1072
1073 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1074
1075 b.full = dfixed_const(1000);
1076 c.full = dfixed_const(wm->disp_clk);
1077 b.full = dfixed_div(c, b);
1078 c.full = dfixed_const(wm->bytes_per_pixel);
1079 b.full = dfixed_mul(b, c);
1080
1081 lb_fill_bw = min(tmp, dfixed_trunc(b));
1082
1083 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1084 b.full = dfixed_const(1000);
1085 c.full = dfixed_const(lb_fill_bw);
1086 b.full = dfixed_div(c, b);
1087 a.full = dfixed_div(a, b);
1088 line_fill_time = dfixed_trunc(a);
1089
1090 if (line_fill_time < wm->active_time)
1091 return latency;
1092 else
1093 return latency + (line_fill_time - wm->active_time);
1094
1095}
1096
1097/**
1098 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1099 * average and available dram bandwidth
1100 *
1101 * @wm: watermark calculation data
1102 *
1103 * Check if the display average bandwidth fits in the display
1104 * dram bandwidth (CIK).
1105 * Used for display watermark bandwidth calculations
1106 * Returns true if the display fits, false if not.
1107 */
1108static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1109{
1110 if (dce_v8_0_average_bandwidth(wm) <=
1111 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1112 return true;
1113 else
1114 return false;
1115}
1116
1117/**
1118 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1119 * average and available bandwidth
1120 *
1121 * @wm: watermark calculation data
1122 *
1123 * Check if the display average bandwidth fits in the display
1124 * available bandwidth (CIK).
1125 * Used for display watermark bandwidth calculations
1126 * Returns true if the display fits, false if not.
1127 */
1128static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1129{
1130 if (dce_v8_0_average_bandwidth(wm) <=
1131 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1132 return true;
1133 else
1134 return false;
1135}
1136
1137/**
1138 * dce_v8_0_check_latency_hiding - check latency hiding
1139 *
1140 * @wm: watermark calculation data
1141 *
1142 * Check latency hiding (CIK).
1143 * Used for display watermark bandwidth calculations
1144 * Returns true if the display fits, false if not.
1145 */
1146static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1147{
1148 u32 lb_partitions = wm->lb_size / wm->src_width;
1149 u32 line_time = wm->active_time + wm->blank_time;
1150 u32 latency_tolerant_lines;
1151 u32 latency_hiding;
1152 fixed20_12 a;
1153
1154 a.full = dfixed_const(1);
1155 if (wm->vsc.full > a.full)
1156 latency_tolerant_lines = 1;
1157 else {
1158 if (lb_partitions <= (wm->vtaps + 1))
1159 latency_tolerant_lines = 1;
1160 else
1161 latency_tolerant_lines = 2;
1162 }
1163
1164 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1165
1166 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1167 return true;
1168 else
1169 return false;
1170}
1171
1172/**
1173 * dce_v8_0_program_watermarks - program display watermarks
1174 *
1175 * @adev: amdgpu_device pointer
1176 * @amdgpu_crtc: the selected display controller
1177 * @lb_size: line buffer size
1178 * @num_heads: number of display controllers in use
1179 *
1180 * Calculate and program the display watermarks for the
1181 * selected display controller (CIK).
1182 */
1183static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1184 struct amdgpu_crtc *amdgpu_crtc,
1185 u32 lb_size, u32 num_heads)
1186{
1187 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1188 struct dce8_wm_params wm_low, wm_high;
1189 u32 pixel_period;
1190 u32 line_time = 0;
1191 u32 latency_watermark_a = 0, latency_watermark_b = 0;
8e36f9d3 1192 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
a2e73f56
AD		 1193
1194 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1195 pixel_period = 1000000 / (u32)mode->clock;
1196 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1197
1198 /* watermark for high clocks */
1199 if (adev->pm.dpm_enabled) {
1200 wm_high.yclk =
1201 amdgpu_dpm_get_mclk(adev, false) * 10;
1202 wm_high.sclk =
1203 amdgpu_dpm_get_sclk(adev, false) * 10;
1204 } else {
1205 wm_high.yclk = adev->pm.current_mclk * 10;
1206 wm_high.sclk = adev->pm.current_sclk * 10;
1207 }
1208
1209 wm_high.disp_clk = mode->clock;
1210 wm_high.src_width = mode->crtc_hdisplay;
1211 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1212 wm_high.blank_time = line_time - wm_high.active_time;
1213 wm_high.interlaced = false;
1214 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1215 wm_high.interlaced = true;
1216 wm_high.vsc = amdgpu_crtc->vsc;
1217 wm_high.vtaps = 1;
1218 if (amdgpu_crtc->rmx_type != RMX_OFF)
1219 wm_high.vtaps = 2;
1220 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1221 wm_high.lb_size = lb_size;
1222 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1223 wm_high.num_heads = num_heads;
1224
1225 /* set for high clocks */
1226 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1227
1228 /* possibly force display priority to high */
1229 /* should really do this at mode validation time... */
1230 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1231 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1232 !dce_v8_0_check_latency_hiding(&wm_high) ||
1233 (adev->mode_info.disp_priority == 2)) {
1234 DRM_DEBUG_KMS("force priority to high\n");
1235 }
1236
1237 /* watermark for low clocks */
1238 if (adev->pm.dpm_enabled) {
1239 wm_low.yclk =
1240 amdgpu_dpm_get_mclk(adev, true) * 10;
1241 wm_low.sclk =
1242 amdgpu_dpm_get_sclk(adev, true) * 10;
1243 } else {
1244 wm_low.yclk = adev->pm.current_mclk * 10;
1245 wm_low.sclk = adev->pm.current_sclk * 10;
1246 }
1247
1248 wm_low.disp_clk = mode->clock;
1249 wm_low.src_width = mode->crtc_hdisplay;
1250 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1251 wm_low.blank_time = line_time - wm_low.active_time;
1252 wm_low.interlaced = false;
1253 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1254 wm_low.interlaced = true;
1255 wm_low.vsc = amdgpu_crtc->vsc;
1256 wm_low.vtaps = 1;
1257 if (amdgpu_crtc->rmx_type != RMX_OFF)
1258 wm_low.vtaps = 2;
1259 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1260 wm_low.lb_size = lb_size;
1261 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1262 wm_low.num_heads = num_heads;
1263
1264 /* set for low clocks */
1265 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1266
1267 /* possibly force display priority to high */
1268 /* should really do this at mode validation time... */
1269 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1270 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1271 !dce_v8_0_check_latency_hiding(&wm_low) ||
1272 (adev->mode_info.disp_priority == 2)) {
1273 DRM_DEBUG_KMS("force priority to high\n");
1274 }
8e36f9d3 1275 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
a2e73f56
AD		 1276 }
1277
1278 /* select wm A */
1279 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1280 tmp = wm_mask;
1281 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1282 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1283 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1284 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1285 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1286 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1287 /* select wm B */
1288 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1289 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1290 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1291 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1292 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1293 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1294 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1295 /* restore original selection */
1296 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1297
1298 /* save values for DPM */
1299 amdgpu_crtc->line_time = line_time;
1300 amdgpu_crtc->wm_high = latency_watermark_a;
1301 amdgpu_crtc->wm_low = latency_watermark_b;
8e36f9d3
AD		 1302 /* Save number of lines the linebuffer leads before the scanout */
1303 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
a2e73f56
AD		 1304}
1305
1306/**
1307 * dce_v8_0_bandwidth_update - program display watermarks
1308 *
1309 * @adev: amdgpu_device pointer
1310 *
1311 * Calculate and program the display watermarks and line
1312 * buffer allocation (CIK).
1313 */
1314static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1315{
1316 struct drm_display_mode *mode = NULL;
1317 u32 num_heads = 0, lb_size;
1318 int i;
1319
1320 amdgpu_update_display_priority(adev);
1321
1322 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1323 if (adev->mode_info.crtcs[i]->base.enabled)
1324 num_heads++;
1325 }
1326 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1327 mode = &adev->mode_info.crtcs[i]->base.mode;
1328 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1329 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1330 lb_size, num_heads);
1331 }
1332}
1333
1334static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1335{
1336 int i;
1337 u32 offset, tmp;
1338
1339 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1340 offset = adev->mode_info.audio.pin[i].offset;
1341 tmp = RREG32_AUDIO_ENDPT(offset,
1342 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1343 if (((tmp &
1344 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1345 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1346 adev->mode_info.audio.pin[i].connected = false;
1347 else
1348 adev->mode_info.audio.pin[i].connected = true;
1349 }
1350}
1351
1352static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1353{
1354 int i;
1355
1356 dce_v8_0_audio_get_connected_pins(adev);
1357
1358 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1359 if (adev->mode_info.audio.pin[i].connected)
1360 return &adev->mode_info.audio.pin[i];
1361 }
1362 DRM_ERROR("No connected audio pins found!\n");
1363 return NULL;
1364}
1365
1366static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1367{
1368 struct amdgpu_device *adev = encoder->dev->dev_private;
1369 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1370 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1371 u32 offset;
1372
1373 if (!dig || !dig->afmt || !dig->afmt->pin)
1374 return;
1375
1376 offset = dig->afmt->offset;
1377
1378 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1379 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1380}
1381
1382static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1383 struct drm_display_mode *mode)
1384{
1385 struct amdgpu_device *adev = encoder->dev->dev_private;
1386 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1387 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1388 struct drm_connector *connector;
1389 struct amdgpu_connector *amdgpu_connector = NULL;
1390 u32 tmp = 0, offset;
1391
1392 if (!dig || !dig->afmt || !dig->afmt->pin)
1393 return;
1394
1395 offset = dig->afmt->pin->offset;
1396
1397 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1398 if (connector->encoder == encoder) {
1399 amdgpu_connector = to_amdgpu_connector(connector);
1400 break;
1401 }
1402 }
1403
1404 if (!amdgpu_connector) {
1405 DRM_ERROR("Couldn't find encoder's connector\n");
1406 return;
1407 }
1408
1409 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1410 if (connector->latency_present[1])
1411 tmp =
1412 (connector->video_latency[1] <<
1413 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1414 (connector->audio_latency[1] <<
1415 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1416 else
1417 tmp =
1418 (0 <<
1419 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1420 (0 <<
1421 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1422 } else {
1423 if (connector->latency_present[0])
1424 tmp =
1425 (connector->video_latency[0] <<
1426 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1427 (connector->audio_latency[0] <<
1428 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1429 else
1430 tmp =
1431 (0 <<
1432 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1433 (0 <<
1434 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1435
1436 }
1437 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1438}
1439
1440static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1441{
1442 struct amdgpu_device *adev = encoder->dev->dev_private;
1443 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1444 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1445 struct drm_connector *connector;
1446 struct amdgpu_connector *amdgpu_connector = NULL;
1447 u32 offset, tmp;
1448 u8 *sadb = NULL;
1449 int sad_count;
1450
1451 if (!dig || !dig->afmt || !dig->afmt->pin)
1452 return;
1453
1454 offset = dig->afmt->pin->offset;
1455
1456 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1457 if (connector->encoder == encoder) {
1458 amdgpu_connector = to_amdgpu_connector(connector);
1459 break;
1460 }
1461 }
1462
1463 if (!amdgpu_connector) {
1464 DRM_ERROR("Couldn't find encoder's connector\n");
1465 return;
1466 }
1467
1468 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1469 if (sad_count < 0) {
1470 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1471 sad_count = 0;
1472 }
1473
1474 /* program the speaker allocation */
1475 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1476 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1477 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1478 /* set HDMI mode */
1479 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1480 if (sad_count)
1481 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1482 else
1483 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1484 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1485
1486 kfree(sadb);
1487}
1488
1489static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1490{
1491 struct amdgpu_device *adev = encoder->dev->dev_private;
1492 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1493 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1494 u32 offset;
1495 struct drm_connector *connector;
1496 struct amdgpu_connector *amdgpu_connector = NULL;
1497 struct cea_sad *sads;
1498 int i, sad_count;
1499
1500 static const u16 eld_reg_to_type[][2] = {
1501 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1502 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1503 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1504 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1505 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1506 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1507 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1508 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1509 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1510 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1511 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1512 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1513 };
1514
1515 if (!dig || !dig->afmt || !dig->afmt->pin)
1516 return;
1517
1518 offset = dig->afmt->pin->offset;
1519
1520 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1521 if (connector->encoder == encoder) {
1522 amdgpu_connector = to_amdgpu_connector(connector);
1523 break;
1524 }
1525 }
1526
1527 if (!amdgpu_connector) {
1528 DRM_ERROR("Couldn't find encoder's connector\n");
1529 return;
1530 }
1531
1532 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1533 if (sad_count <= 0) {
1534 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1535 return;
1536 }
1537 BUG_ON(!sads);
1538
1539 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1540 u32 value = 0;
1541 u8 stereo_freqs = 0;
1542 int max_channels = -1;
1543 int j;
1544
1545 for (j = 0; j < sad_count; j++) {
1546 struct cea_sad *sad = &sads[j];
1547
1548 if (sad->format == eld_reg_to_type[i][1]) {
1549 if (sad->channels > max_channels) {
1550 value = (sad->channels <<
1551 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1552 (sad->byte2 <<
1553 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1554 (sad->freq <<
1555 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1556 max_channels = sad->channels;
1557 }
1558
1559 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1560 stereo_freqs |= sad->freq;
1561 else
1562 break;
1563 }
1564 }
1565
1566 value |= (stereo_freqs <<
1567 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1568
1569 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1570 }
1571
1572 kfree(sads);
1573}
1574
1575static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1576 struct amdgpu_audio_pin *pin,
1577 bool enable)
1578{
1579 if (!pin)
1580 return;
1581
1582 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1583 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1584}
1585
1586static const u32 pin_offsets[7] =
1587{
1588 (0x1780 - 0x1780),
1589 (0x1786 - 0x1780),
1590 (0x178c - 0x1780),
1591 (0x1792 - 0x1780),
1592 (0x1798 - 0x1780),
1593 (0x179d - 0x1780),
1594 (0x17a4 - 0x1780),
1595};
1596
1597static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1598{
1599 int i;
1600
1601 if (!amdgpu_audio)
1602 return 0;
1603
1604 adev->mode_info.audio.enabled = true;
1605
1606 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1607 adev->mode_info.audio.num_pins = 7;
1608 else if ((adev->asic_type == CHIP_KABINI) ||
1609 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1610 adev->mode_info.audio.num_pins = 3;
1611 else if ((adev->asic_type == CHIP_BONAIRE) ||
1612 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1613 adev->mode_info.audio.num_pins = 7;
1614 else
1615 adev->mode_info.audio.num_pins = 3;
1616
1617 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1618 adev->mode_info.audio.pin[i].channels = -1;
1619 adev->mode_info.audio.pin[i].rate = -1;
1620 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1621 adev->mode_info.audio.pin[i].status_bits = 0;
1622 adev->mode_info.audio.pin[i].category_code = 0;
1623 adev->mode_info.audio.pin[i].connected = false;
1624 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1625 adev->mode_info.audio.pin[i].id = i;
1626 /* disable audio. it will be set up later */
1627 /* XXX remove once we switch to ip funcs */
1628 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1629 }
1630
1631 return 0;
1632}
1633
1634static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1635{
1636 int i;
1637
84cffef1
TSD		 1638 if (!amdgpu_audio)
1639 return;
1640
a2e73f56
AD		 1641 if (!adev->mode_info.audio.enabled)
1642 return;
1643
1644 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1645 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1646
1647 adev->mode_info.audio.enabled = false;
1648}
1649
1650/*
1651 * update the N and CTS parameters for a given pixel clock rate
1652 */
1653static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1654{
1655 struct drm_device *dev = encoder->dev;
1656 struct amdgpu_device *adev = dev->dev_private;
1657 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1658 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1659 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1660 uint32_t offset = dig->afmt->offset;
1661
1662 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1663 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1664
1665 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1666 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1667
1668 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1669 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1670}
1671
1672/*
1673 * build a HDMI Video Info Frame
1674 */
1675static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1676 void *buffer, size_t size)
1677{
1678 struct drm_device *dev = encoder->dev;
1679 struct amdgpu_device *adev = dev->dev_private;
1680 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1681 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1682 uint32_t offset = dig->afmt->offset;
1683 uint8_t *frame = buffer + 3;
1684 uint8_t *header = buffer;
1685
1686 WREG32(mmAFMT_AVI_INFO0 + offset,
1687 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1688 WREG32(mmAFMT_AVI_INFO1 + offset,
1689 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1690 WREG32(mmAFMT_AVI_INFO2 + offset,
1691 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1692 WREG32(mmAFMT_AVI_INFO3 + offset,
1693 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1694}
1695
1696static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1697{
1698 struct drm_device *dev = encoder->dev;
1699 struct amdgpu_device *adev = dev->dev_private;
1700 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1701 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1702 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1703 u32 dto_phase = 24 * 1000;
1704 u32 dto_modulo = clock;
1705
1706 if (!dig || !dig->afmt)
1707 return;
1708
1709 /* XXX two dtos; generally use dto0 for hdmi */
1710 /* Express [24MHz / target pixel clock] as an exact rational
1711 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1712 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1713 */
1714 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1715 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1716 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1717}
1718
1719/*
1720 * update the info frames with the data from the current display mode
1721 */
1722static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1723 struct drm_display_mode *mode)
1724{
1725 struct drm_device *dev = encoder->dev;
1726 struct amdgpu_device *adev = dev->dev_private;
1727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1728 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1729 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1730 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1731 struct hdmi_avi_infoframe frame;
1732 uint32_t offset, val;
1733 ssize_t err;
1734 int bpc = 8;
1735
1736 if (!dig || !dig->afmt)
1737 return;
1738
1739 /* Silent, r600_hdmi_enable will raise WARN for us */
1740 if (!dig->afmt->enabled)
1741 return;
1742 offset = dig->afmt->offset;
1743
1744 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1745 if (encoder->crtc) {
1746 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1747 bpc = amdgpu_crtc->bpc;
1748 }
1749
1750 /* disable audio prior to setting up hw */
1751 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1752 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1753
1754 dce_v8_0_audio_set_dto(encoder, mode->clock);
1755
1756 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1757 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1758
1759 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1760
1761 val = RREG32(mmHDMI_CONTROL + offset);
1762 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1763 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1764
1765 switch (bpc) {
1766 case 0:
1767 case 6:
1768 case 8:
1769 case 16:
1770 default:
1771 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1772 connector->name, bpc);
1773 break;
1774 case 10:
1775 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1776 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1777 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1778 connector->name);
1779 break;
1780 case 12:
1781 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1782 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1783 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1784 connector->name);
1785 break;
1786 }
1787
1788 WREG32(mmHDMI_CONTROL + offset, val);
1789
1790 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1791 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1792 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1793 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1794
1795 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1796 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1797 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1798
1799 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1800 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1801
1802 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1803 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1804
1805 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1806
1807 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1808 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1809 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1810
1811 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1812 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1813
1814 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1815
1816 if (bpc > 8)
1817 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1818 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1819 else
1820 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1821 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1822 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1823
1824 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1825
1826 WREG32(mmAFMT_60958_0 + offset,
1827 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1828
1829 WREG32(mmAFMT_60958_1 + offset,
1830 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1831
1832 WREG32(mmAFMT_60958_2 + offset,
1833 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1834 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1835 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1836 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1837 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1838 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1839
1840 dce_v8_0_audio_write_speaker_allocation(encoder);
1841
1842
1843 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1844 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1845
1846 dce_v8_0_afmt_audio_select_pin(encoder);
1847 dce_v8_0_audio_write_sad_regs(encoder);
1848 dce_v8_0_audio_write_latency_fields(encoder, mode);
1849
1850 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1851 if (err < 0) {
1852 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1853 return;
1854 }
1855
1856 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1857 if (err < 0) {
1858 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1859 return;
1860 }
1861
1862 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1863
1864 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1865 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1866 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */
1867
1868 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1869 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1870 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1871
1872 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1873 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1874
1875 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
1876 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1877 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1878 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1879 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1880
1881 /* enable audio after to setting up hw */
1882 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1883}
1884
1885static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1886{
1887 struct drm_device *dev = encoder->dev;
1888 struct amdgpu_device *adev = dev->dev_private;
1889 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1890 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1891
1892 if (!dig || !dig->afmt)
1893 return;
1894
1895 /* Silent, r600_hdmi_enable will raise WARN for us */
1896 if (enable && dig->afmt->enabled)
1897 return;
1898 if (!enable && !dig->afmt->enabled)
1899 return;
1900
1901 if (!enable && dig->afmt->pin) {
1902 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1903 dig->afmt->pin = NULL;
1904 }
1905
1906 dig->afmt->enabled = enable;
1907
1908 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1909 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1910}
1911
ff923479 1912static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
a2e73f56
AD		 1913{
1914 int i;
1915
1916 for (i = 0; i < adev->mode_info.num_dig; i++)
1917 adev->mode_info.afmt[i] = NULL;
1918
1919 /* DCE8 has audio blocks tied to DIG encoders */
1920 for (i = 0; i < adev->mode_info.num_dig; i++) {
1921 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1922 if (adev->mode_info.afmt[i]) {
1923 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1924 adev->mode_info.afmt[i]->id = i;
ff923479
TSD		 1925 } else {
1926 int j;
1927 for (j = 0; j < i; j++) {
1928 kfree(adev->mode_info.afmt[j]);
1929 adev->mode_info.afmt[j] = NULL;
1930 }
1931 return -ENOMEM;
a2e73f56
AD		 1932 }
1933 }
ff923479 1934 return 0;
a2e73f56
AD		 1935}
1936
1937static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1938{
1939 int i;
1940
1941 for (i = 0; i < adev->mode_info.num_dig; i++) {
1942 kfree(adev->mode_info.afmt[i]);
1943 adev->mode_info.afmt[i] = NULL;
1944 }
1945}
1946
1947static const u32 vga_control_regs[6] =
1948{
1949 mmD1VGA_CONTROL,
1950 mmD2VGA_CONTROL,
1951 mmD3VGA_CONTROL,
1952 mmD4VGA_CONTROL,
1953 mmD5VGA_CONTROL,
1954 mmD6VGA_CONTROL,
1955};
1956
1957static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1958{
1959 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1960 struct drm_device *dev = crtc->dev;
1961 struct amdgpu_device *adev = dev->dev_private;
1962 u32 vga_control;
1963
1964 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1965 if (enable)
1966 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1967 else
1968 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1969}
1970
1971static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1972{
1973 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1974 struct drm_device *dev = crtc->dev;
1975 struct amdgpu_device *adev = dev->dev_private;
1976
1977 if (enable)
1978 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1979 else
1980 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1981}
1982
a2e73f56
AD		 1983static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1984 struct drm_framebuffer *fb,
1985 int x, int y, int atomic)
1986{
1987 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1988 struct drm_device *dev = crtc->dev;
1989 struct amdgpu_device *adev = dev->dev_private;
1990 struct amdgpu_framebuffer *amdgpu_fb;
1991 struct drm_framebuffer *target_fb;
1992 struct drm_gem_object *obj;
1993 struct amdgpu_bo *rbo;
1994 uint64_t fb_location, tiling_flags;
1995 uint32_t fb_format, fb_pitch_pixels;
a2e73f56 1996 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
fbd76d59 1997 u32 pipe_config;
cb9e59d7 1998 u32 viewport_w, viewport_h;
a2e73f56
AD		 1999 int r;
2000 bool bypass_lut = false;
2001
2002 /* no fb bound */
2003 if (!atomic && !crtc->primary->fb) {
2004 DRM_DEBUG_KMS("No FB bound\n");
2005 return 0;
2006 }
2007
2008 if (atomic) {
2009 amdgpu_fb = to_amdgpu_framebuffer(fb);
2010 target_fb = fb;
92821c26 2011 } else {
a2e73f56
AD		 2012 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2013 target_fb = crtc->primary->fb;
2014 }
2015
2016 /* If atomic, assume fb object is pinned & idle & fenced and
2017 * just update base pointers
2018 */
2019 obj = amdgpu_fb->obj;
2020 rbo = gem_to_amdgpu_bo(obj);
2021 r = amdgpu_bo_reserve(rbo, false);
2022 if (unlikely(r != 0))
2023 return r;
2024
92821c26 2025 if (atomic) {
a2e73f56 2026 fb_location = amdgpu_bo_gpu_offset(rbo);
92821c26 2027 } else {
a2e73f56
AD		 2028 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2029 if (unlikely(r != 0)) {
2030 amdgpu_bo_unreserve(rbo);
2031 return -EINVAL;
2032 }
2033 }
2034
2035 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2036 amdgpu_bo_unreserve(rbo);
2037
fbd76d59
MO		 2038 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2039
a2e73f56
AD		 2040 switch (target_fb->pixel_format) {
2041 case DRM_FORMAT_C8:
2042 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2043 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2044 break;
2045 case DRM_FORMAT_XRGB4444:
2046 case DRM_FORMAT_ARGB4444:
2047 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2048 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2049#ifdef __BIG_ENDIAN
2050 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2051#endif
2052 break;
2053 case DRM_FORMAT_XRGB1555:
2054 case DRM_FORMAT_ARGB1555:
2055 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2056 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2057#ifdef __BIG_ENDIAN
2058 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2059#endif
2060 break;
2061 case DRM_FORMAT_BGRX5551:
2062 case DRM_FORMAT_BGRA5551:
2063 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2064 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2065#ifdef __BIG_ENDIAN
2066 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2067#endif
2068 break;
2069 case DRM_FORMAT_RGB565:
2070 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2071 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2072#ifdef __BIG_ENDIAN
2073 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2074#endif
2075 break;
2076 case DRM_FORMAT_XRGB8888:
2077 case DRM_FORMAT_ARGB8888:
2078 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2079 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2080#ifdef __BIG_ENDIAN
2081 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2082#endif
2083 break;
2084 case DRM_FORMAT_XRGB2101010:
2085 case DRM_FORMAT_ARGB2101010:
2086 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2087 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2088#ifdef __BIG_ENDIAN
2089 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2090#endif
2091 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2092 bypass_lut = true;
2093 break;
2094 case DRM_FORMAT_BGRX1010102:
2095 case DRM_FORMAT_BGRA1010102:
2096 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2097 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2098#ifdef __BIG_ENDIAN
2099 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2100#endif
2101 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2102 bypass_lut = true;
2103 break;
2104 default:
2105 DRM_ERROR("Unsupported screen format %s\n",
2106 drm_get_format_name(target_fb->pixel_format));
2107 return -EINVAL;
2108 }
2109
fbd76d59
MO		 2110 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2111 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
a2e73f56 2112
fbd76d59
MO		 2113 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2114 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2115 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2116 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2117 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
a2e73f56 2118
a2e73f56
AD		 2119 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2120 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2121 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2122 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2123 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2124 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2125 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
fbd76d59 2126 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
a2e73f56
AD		 2127 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2128 }
2129
a2e73f56
AD		 2130 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2131
2132 dce_v8_0_vga_enable(crtc, false);
2133
cb9e59d7
AD		 2134 /* Make sure surface address is updated at vertical blank rather than
2135 * horizontal blank
2136 */
2137 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
2138
a2e73f56
AD		 2139 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2140 upper_32_bits(fb_location));
2141 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2142 upper_32_bits(fb_location));
2143 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2144 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2145 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2146 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2147 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2148 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2149
2150 /*
2151 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2152 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2153 * retain the full precision throughout the pipeline.
2154 */
2155 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2156 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2157 ~LUT_10BIT_BYPASS_EN);
2158
2159 if (bypass_lut)
2160 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2161
2162 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2163 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2164 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2165 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2166 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2167 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2168
2169 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2170 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2171
2172 dce_v8_0_grph_enable(crtc, true);
2173
2174 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2175 target_fb->height);
2176
2177 x &= ~3;
2178 y &= ~1;
2179 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2180 (x << 16) | y);
2181 viewport_w = crtc->mode.hdisplay;
2182 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2183 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2184 (viewport_w << 16) | viewport_h);
2185
a2e73f56
AD		 2186 /* set pageflip to happen only at start of vblank interval (front porch) */
2187 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2188
2189 if (!atomic && fb && fb != crtc->primary->fb) {
2190 amdgpu_fb = to_amdgpu_framebuffer(fb);
2191 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2192 r = amdgpu_bo_reserve(rbo, false);
2193 if (unlikely(r != 0))
2194 return r;
2195 amdgpu_bo_unpin(rbo);
2196 amdgpu_bo_unreserve(rbo);
2197 }
2198
2199 /* Bytes per pixel may have changed */
2200 dce_v8_0_bandwidth_update(adev);
2201
2202 return 0;
2203}
2204
2205static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2206 struct drm_display_mode *mode)
2207{
2208 struct drm_device *dev = crtc->dev;
2209 struct amdgpu_device *adev = dev->dev_private;
2210 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2211
2212 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2213 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2214 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2215 else
2216 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2217}
2218
2219static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2220{
2221 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2222 struct drm_device *dev = crtc->dev;
2223 struct amdgpu_device *adev = dev->dev_private;
2224 int i;
2225
2226 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2227
2228 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2229 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2230 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2231 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2232 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2233 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2234 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2235 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2236 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2237 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2238
2239 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2240
2241 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2242 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2243 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2244
2245 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2246 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2247 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2248
2249 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2250 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2251
2252 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2253 for (i = 0; i < 256; i++) {
2254 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2255 (amdgpu_crtc->lut_r[i] << 20) |
2256 (amdgpu_crtc->lut_g[i] << 10) |
2257 (amdgpu_crtc->lut_b[i] << 0));
2258 }
2259
2260 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2261 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2262 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2263 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2264 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2265 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2266 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2267 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2268 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2269 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2270 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2271 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2272 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2273 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2274 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2275 /* XXX this only needs to be programmed once per crtc at startup,
2276 * not sure where the best place for it is
2277 */
2278 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2279 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2280}
2281
2282static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2283{
2284 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2285 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2286
2287 switch (amdgpu_encoder->encoder_id) {
2288 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2289 if (dig->linkb)
2290 return 1;
2291 else
2292 return 0;
2293 break;
2294 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2295 if (dig->linkb)
2296 return 3;
2297 else
2298 return 2;
2299 break;
2300 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2301 if (dig->linkb)
2302 return 5;
2303 else
2304 return 4;
2305 break;
2306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2307 return 6;
2308 break;
2309 default:
2310 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2311 return 0;
2312 }
2313}
2314
2315/**
2316 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2317 *
2318 * @crtc: drm crtc
2319 *
2320 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2321 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2322 * monitors a dedicated PPLL must be used. If a particular board has
2323 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2324 * as there is no need to program the PLL itself. If we are not able to
2325 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2326 * avoid messing up an existing monitor.
2327 *
2328 * Asic specific PLL information
2329 *
2330 * DCE 8.x
2331 * KB/KV
2332 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2333 * CI
2334 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2335 *
2336 */
2337static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2338{
2339 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2340 struct drm_device *dev = crtc->dev;
2341 struct amdgpu_device *adev = dev->dev_private;
2342 u32 pll_in_use;
2343 int pll;
2344
2345 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2346 if (adev->clock.dp_extclk)
2347 /* skip PPLL programming if using ext clock */
2348 return ATOM_PPLL_INVALID;
2349 else {
2350 /* use the same PPLL for all DP monitors */
2351 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2352 if (pll != ATOM_PPLL_INVALID)
2353 return pll;
2354 }
2355 } else {
2356 /* use the same PPLL for all monitors with the same clock */
2357 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2358 if (pll != ATOM_PPLL_INVALID)
2359 return pll;
2360 }
2361 /* otherwise, pick one of the plls */
2362 if ((adev->asic_type == CHIP_KABINI) ||
2363 (adev->asic_type == CHIP_MULLINS)) {
2364 /* KB/ML has PPLL1 and PPLL2 */
2365 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2366 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2367 return ATOM_PPLL2;
2368 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2369 return ATOM_PPLL1;
2370 DRM_ERROR("unable to allocate a PPLL\n");
2371 return ATOM_PPLL_INVALID;
2372 } else {
2373 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2374 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2375 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2376 return ATOM_PPLL2;
2377 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2378 return ATOM_PPLL1;
2379 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2380 return ATOM_PPLL0;
2381 DRM_ERROR("unable to allocate a PPLL\n");
2382 return ATOM_PPLL_INVALID;
2383 }
2384 return ATOM_PPLL_INVALID;
2385}
2386
2387static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2388{
2389 struct amdgpu_device *adev = crtc->dev->dev_private;
2390 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2391 uint32_t cur_lock;
2392
2393 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2394 if (lock)
2395 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2396 else
2397 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2398 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2399}
2400
2401static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2402{
2403 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2404 struct amdgpu_device *adev = crtc->dev->dev_private;
2405
2406 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2407 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2408 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2409}
2410
2411static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2412{
2413 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2414 struct amdgpu_device *adev = crtc->dev->dev_private;
2415
a2df42da
AD		 2416 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2417 upper_32_bits(amdgpu_crtc->cursor_addr));
2418 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2419 lower_32_bits(amdgpu_crtc->cursor_addr));
2420
a2e73f56
AD		 2421 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2422 CUR_CONTROL__CURSOR_EN_MASK |
2423 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2424 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2425}
2426
77ed35b8
AD		 2427static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2428 int x, int y)
a2e73f56
AD		 2429{
2430 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2431 struct amdgpu_device *adev = crtc->dev->dev_private;
2432 int xorigin = 0, yorigin = 0;
2433
2434 /* avivo cursor are offset into the total surface */
2435 x += crtc->x;
2436 y += crtc->y;
2437 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2438
2439 if (x < 0) {
2440 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2441 x = 0;
2442 }
2443 if (y < 0) {
2444 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2445 y = 0;
2446 }
2447
a2e73f56
AD		 2448 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2449 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2450 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2451 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
77ed35b8
AD		 2452
2453 amdgpu_crtc->cursor_x = x;
2454 amdgpu_crtc->cursor_y = y;
a2e73f56
AD		 2455
2456 return 0;
2457}
2458
77ed35b8
AD		 2459static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2460 int x, int y)
2461{
2462 int ret;
2463
2464 dce_v8_0_lock_cursor(crtc, true);
2465 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2466 dce_v8_0_lock_cursor(crtc, false);
2467
2468 return ret;
2469}
2470
2471static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2472 struct drm_file *file_priv,
2473 uint32_t handle,
2474 uint32_t width,
2475 uint32_t height,
2476 int32_t hot_x,
2477 int32_t hot_y)
a2e73f56
AD		 2478{
2479 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2480 struct drm_gem_object *obj;
72b40067 2481 struct amdgpu_bo *aobj;
a2e73f56
AD		 2482 int ret;
2483
2484 if (!handle) {
2485 /* turn off cursor */
2486 dce_v8_0_hide_cursor(crtc);
2487 obj = NULL;
2488 goto unpin;
2489 }
2490
2491 if ((width > amdgpu_crtc->max_cursor_width) ||
2492 (height > amdgpu_crtc->max_cursor_height)) {
2493 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2494 return -EINVAL;
2495 }
2496
a8ad0bd8 2497 obj = drm_gem_object_lookup(file_priv, handle);
a2e73f56
AD		 2498 if (!obj) {
2499 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2500 return -ENOENT;
2501 }
2502
72b40067
AD		 2503 aobj = gem_to_amdgpu_bo(obj);
2504 ret = amdgpu_bo_reserve(aobj, false);
2505 if (ret != 0) {
2506 drm_gem_object_unreference_unlocked(obj);
2507 return ret;
2508 }
2509
2510 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2511 amdgpu_bo_unreserve(aobj);
2512 if (ret) {
2513 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2514 drm_gem_object_unreference_unlocked(obj);
2515 return ret;
2516 }
a2e73f56
AD		 2517
2518 amdgpu_crtc->cursor_width = width;
2519 amdgpu_crtc->cursor_height = height;
2520
2521 dce_v8_0_lock_cursor(crtc, true);
c4e0dfad
AD		 2522
2523 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2524 hot_y != amdgpu_crtc->cursor_hot_y) {
2525 int x, y;
2526
2527 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2528 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2529
2530 dce_v8_0_cursor_move_locked(crtc, x, y);
2531
2532 amdgpu_crtc->cursor_hot_x = hot_x;
2533 amdgpu_crtc->cursor_hot_y = hot_y;
2534 }
2535
a2e73f56
AD		 2536 dce_v8_0_show_cursor(crtc);
2537 dce_v8_0_lock_cursor(crtc, false);
2538
2539unpin:
2540 if (amdgpu_crtc->cursor_bo) {
fd70cf63
AD		 2541 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2542 ret = amdgpu_bo_reserve(aobj, false);
a2e73f56 2543 if (likely(ret == 0)) {
fd70cf63
AD		 2544 amdgpu_bo_unpin(aobj);
2545 amdgpu_bo_unreserve(aobj);
a2e73f56
AD		 2546 }
2547 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2548 }
2549
2550 amdgpu_crtc->cursor_bo = obj;
2551 return 0;
fd70cf63 2552}
a2e73f56 2553
fd70cf63
AD		 2554static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2555{
2556 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
fd70cf63
AD		 2557
2558 if (amdgpu_crtc->cursor_bo) {
2559 dce_v8_0_lock_cursor(crtc, true);
2560
2561 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2562 amdgpu_crtc->cursor_y);
2563
72b40067 2564 dce_v8_0_show_cursor(crtc);
fd70cf63
AD		 2565
2566 dce_v8_0_lock_cursor(crtc, false);
2567 }
a2e73f56
AD		 2568}
2569
7ea77283
ML		 2570static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2571 u16 *blue, uint32_t size)
a2e73f56
AD		 2572{
2573 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7ea77283 2574 int i;
a2e73f56
AD		 2575
2576 /* userspace palettes are always correct as is */
7ea77283 2577 for (i = 0; i < size; i++) {
a2e73f56
AD		 2578 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2579 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2580 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2581 }
2582 dce_v8_0_crtc_load_lut(crtc);
7ea77283
ML		 2583
2584 return 0;
a2e73f56
AD		 2585}
2586
2587static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2588{
2589 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2590
2591 drm_crtc_cleanup(crtc);
a2e73f56
AD		 2592 kfree(amdgpu_crtc);
2593}
2594
2595static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
77ed35b8 2596 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
a2e73f56
AD		 2597 .cursor_move = dce_v8_0_crtc_cursor_move,
2598 .gamma_set = dce_v8_0_crtc_gamma_set,
2599 .set_config = amdgpu_crtc_set_config,
2600 .destroy = dce_v8_0_crtc_destroy,
325cbba1 2601 .page_flip_target = amdgpu_crtc_page_flip_target,
a2e73f56
AD		 2602};
2603
2604static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2605{
2606 struct drm_device *dev = crtc->dev;
2607 struct amdgpu_device *adev = dev->dev_private;
2608 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1002d718 2609 unsigned type;
a2e73f56
AD		 2610
2611 switch (mode) {
2612 case DRM_MODE_DPMS_ON:
2613 amdgpu_crtc->enabled = true;
2614 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2615 dce_v8_0_vga_enable(crtc, true);
2616 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2617 dce_v8_0_vga_enable(crtc, false);
f6c7aba4 2618 /* Make sure VBLANK and PFLIP interrupts are still enabled */
1002d718
MD		 2619 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2620 amdgpu_irq_update(adev, &adev->crtc_irq, type);
f6c7aba4 2621 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
9a7841e9 2622 drm_crtc_vblank_on(crtc);
a2e73f56
AD		 2623 dce_v8_0_crtc_load_lut(crtc);
2624 break;
2625 case DRM_MODE_DPMS_STANDBY:
2626 case DRM_MODE_DPMS_SUSPEND:
2627 case DRM_MODE_DPMS_OFF:
9a7841e9 2628 drm_crtc_vblank_off(crtc);
a2e73f56
AD		 2629 if (amdgpu_crtc->enabled) {
2630 dce_v8_0_vga_enable(crtc, true);
2631 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2632 dce_v8_0_vga_enable(crtc, false);
2633 }
2634 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2635 amdgpu_crtc->enabled = false;
2636 break;
2637 }
2638 /* adjust pm to dpms */
2639 amdgpu_pm_compute_clocks(adev);
2640}
2641
2642static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2643{
2644 /* disable crtc pair power gating before programming */
2645 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2646 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2647 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2648}
2649
2650static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2651{
2652 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2653 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2654}
2655
2656static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2657{
2658 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2659 struct drm_device *dev = crtc->dev;
2660 struct amdgpu_device *adev = dev->dev_private;
2661 struct amdgpu_atom_ss ss;
2662 int i;
2663
2664 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2665 if (crtc->primary->fb) {
2666 int r;
2667 struct amdgpu_framebuffer *amdgpu_fb;
2668 struct amdgpu_bo *rbo;
2669
2670 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2671 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2672 r = amdgpu_bo_reserve(rbo, false);
2673 if (unlikely(r))
2674 DRM_ERROR("failed to reserve rbo before unpin\n");
2675 else {
2676 amdgpu_bo_unpin(rbo);
2677 amdgpu_bo_unreserve(rbo);
2678 }
2679 }
2680 /* disable the GRPH */
2681 dce_v8_0_grph_enable(crtc, false);
2682
2683 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2684
2685 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2686 if (adev->mode_info.crtcs[i] &&
2687 adev->mode_info.crtcs[i]->enabled &&
2688 i != amdgpu_crtc->crtc_id &&
2689 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2690 /* one other crtc is using this pll don't turn
2691 * off the pll
2692 */
2693 goto done;
2694 }
2695 }
2696
2697 switch (amdgpu_crtc->pll_id) {
2698 case ATOM_PPLL1:
2699 case ATOM_PPLL2:
2700 /* disable the ppll */
2701 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2702 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2703 break;
2704 case ATOM_PPLL0:
2705 /* disable the ppll */
2706 if ((adev->asic_type == CHIP_KAVERI) ||
2707 (adev->asic_type == CHIP_BONAIRE) ||
2708 (adev->asic_type == CHIP_HAWAII))
2709 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2710 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2711 break;
2712 default:
2713 break;
2714 }
2715done:
2716 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2717 amdgpu_crtc->adjusted_clock = 0;
2718 amdgpu_crtc->encoder = NULL;
2719 amdgpu_crtc->connector = NULL;
2720}
2721
2722static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2723 struct drm_display_mode *mode,
2724 struct drm_display_mode *adjusted_mode,
2725 int x, int y, struct drm_framebuffer *old_fb)
2726{
2727 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2728
2729 if (!amdgpu_crtc->adjusted_clock)
2730 return -EINVAL;
2731
2732 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2733 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2734 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2735 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2736 amdgpu_atombios_crtc_scaler_setup(crtc);
fd70cf63 2737 dce_v8_0_cursor_reset(crtc);
a2e73f56
AD		 2738 /* update the hw version fpr dpm */
2739 amdgpu_crtc->hw_mode = *adjusted_mode;
2740
2741 return 0;
2742}
2743
2744static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2745 const struct drm_display_mode *mode,
2746 struct drm_display_mode *adjusted_mode)
2747{
2748 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2749 struct drm_device *dev = crtc->dev;
2750 struct drm_encoder *encoder;
2751
2752 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2753 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2754 if (encoder->crtc == crtc) {
2755 amdgpu_crtc->encoder = encoder;
2756 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2757 break;
2758 }
2759 }
2760 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2761 amdgpu_crtc->encoder = NULL;
2762 amdgpu_crtc->connector = NULL;
2763 return false;
2764 }
2765 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2766 return false;
2767 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2768 return false;
2769 /* pick pll */
2770 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2771 /* if we can't get a PPLL for a non-DP encoder, fail */
2772 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2773 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2774 return false;
2775
2776 return true;
2777}
2778
2779static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2780 struct drm_framebuffer *old_fb)
2781{
2782 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2783}
2784
2785static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2786 struct drm_framebuffer *fb,
2787 int x, int y, enum mode_set_atomic state)
2788{
2789 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2790}
2791
2792static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2793 .dpms = dce_v8_0_crtc_dpms,
2794 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2795 .mode_set = dce_v8_0_crtc_mode_set,
2796 .mode_set_base = dce_v8_0_crtc_set_base,
2797 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2798 .prepare = dce_v8_0_crtc_prepare,
2799 .commit = dce_v8_0_crtc_commit,
2800 .load_lut = dce_v8_0_crtc_load_lut,
2801 .disable = dce_v8_0_crtc_disable,
2802};
2803
2804static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2805{
2806 struct amdgpu_crtc *amdgpu_crtc;
2807 int i;
2808
2809 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2810 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2811 if (amdgpu_crtc == NULL)
2812 return -ENOMEM;
2813
2814 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2815
2816 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2817 amdgpu_crtc->crtc_id = index;
a2e73f56
AD		 2818 adev->mode_info.crtcs[index] = amdgpu_crtc;
2819
2820 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2821 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2822 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2823 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2824
2825 for (i = 0; i < 256; i++) {
2826 amdgpu_crtc->lut_r[i] = i << 2;
2827 amdgpu_crtc->lut_g[i] = i << 2;
2828 amdgpu_crtc->lut_b[i] = i << 2;
2829 }
2830
2831 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2832
2833 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2834 amdgpu_crtc->adjusted_clock = 0;
2835 amdgpu_crtc->encoder = NULL;
2836 amdgpu_crtc->connector = NULL;
2837 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2838
2839 return 0;
2840}
2841
5fc3aeeb 2842static int dce_v8_0_early_init(void *handle)
a2e73f56 2843{
5fc3aeeb 2844 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2845
a2e73f56
AD		 2846 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2847 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2848
2849 dce_v8_0_set_display_funcs(adev);
2850 dce_v8_0_set_irq_funcs(adev);
2851
83c9b025
ED		 2852 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2853
a2e73f56
AD		 2854 switch (adev->asic_type) {
2855 case CHIP_BONAIRE:
2856 case CHIP_HAWAII:
a2e73f56
AD		 2857 adev->mode_info.num_hpd = 6;
2858 adev->mode_info.num_dig = 6;
2859 break;
2860 case CHIP_KAVERI:
a2e73f56
AD		 2861 adev->mode_info.num_hpd = 6;
2862 adev->mode_info.num_dig = 7;
2863 break;
2864 case CHIP_KABINI:
2865 case CHIP_MULLINS:
a2e73f56
AD		 2866 adev->mode_info.num_hpd = 6;
2867 adev->mode_info.num_dig = 6; /* ? */
2868 break;
2869 default:
2870 /* FIXME: not supported yet */
2871 return -EINVAL;
2872 }
2873
2874 return 0;
2875}
2876
5fc3aeeb 2877static int dce_v8_0_sw_init(void *handle)
a2e73f56
AD		 2878{
2879 int r, i;
5fc3aeeb 2880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2881
2882 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2883 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2884 if (r)
2885 return r;
2886 }
2887
2888 for (i = 8; i < 20; i += 2) {
2889 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2890 if (r)
2891 return r;
2892 }
2893
2894 /* HPD hotplug */
2895 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2896 if (r)
2897 return r;
2898
a2e73f56
AD		 2899 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2900
cb9e59d7
AD		 2901 adev->ddev->mode_config.async_page_flip = true;
2902
a2e73f56
AD		 2903 adev->ddev->mode_config.max_width = 16384;
2904 adev->ddev->mode_config.max_height = 16384;
2905
2906 adev->ddev->mode_config.preferred_depth = 24;
2907 adev->ddev->mode_config.prefer_shadow = 1;
2908
2909 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2910
2911 r = amdgpu_modeset_create_props(adev);
2912 if (r)
2913 return r;
2914
2915 adev->ddev->mode_config.max_width = 16384;
2916 adev->ddev->mode_config.max_height = 16384;
2917
2918 /* allocate crtcs */
2919 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2920 r = dce_v8_0_crtc_init(adev, i);
2921 if (r)
2922 return r;
2923 }
2924
2925 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2926 amdgpu_print_display_setup(adev->ddev);
2927 else
2928 return -EINVAL;
2929
2930 /* setup afmt */
ff923479
TSD		 2931 r = dce_v8_0_afmt_init(adev);
2932 if (r)
2933 return r;
a2e73f56
AD		 2934
2935 r = dce_v8_0_audio_init(adev);
2936 if (r)
2937 return r;
2938
2939 drm_kms_helper_poll_init(adev->ddev);
2940
74c1e842
TSD		 2941 adev->mode_info.mode_config_initialized = true;
2942 return 0;
a2e73f56
AD		 2943}
2944
5fc3aeeb 2945static int dce_v8_0_sw_fini(void *handle)
a2e73f56 2946{
5fc3aeeb 2947 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2948
a2e73f56
AD		 2949 kfree(adev->mode_info.bios_hardcoded_edid);
2950
2951 drm_kms_helper_poll_fini(adev->ddev);
2952
2953 dce_v8_0_audio_fini(adev);
2954
2955 dce_v8_0_afmt_fini(adev);
2956
2957 drm_mode_config_cleanup(adev->ddev);
2958 adev->mode_info.mode_config_initialized = false;
2959
2960 return 0;
2961}
2962
5fc3aeeb 2963static int dce_v8_0_hw_init(void *handle)
a2e73f56
AD		 2964{
2965 int i;
5fc3aeeb 2966 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2967
2968 /* init dig PHYs, disp eng pll */
2969 amdgpu_atombios_encoder_init_dig(adev);
2970 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2971
2972 /* initialize hpd */
2973 dce_v8_0_hpd_init(adev);
2974
2975 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2976 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2977 }
2978
f6c7aba4
MD		 2979 dce_v8_0_pageflip_interrupt_init(adev);
2980
a2e73f56
AD		 2981 return 0;
2982}
2983
5fc3aeeb 2984static int dce_v8_0_hw_fini(void *handle)
a2e73f56
AD		 2985{
2986 int i;
5fc3aeeb 2987 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2988
2989 dce_v8_0_hpd_fini(adev);
2990
2991 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2992 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2993 }
2994
f6c7aba4
MD		 2995 dce_v8_0_pageflip_interrupt_fini(adev);
2996
a2e73f56
AD		 2997 return 0;
2998}
2999
5fc3aeeb 3000static int dce_v8_0_suspend(void *handle)
a2e73f56 3001{
5fc3aeeb 3002 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 3003
a2e73f56
AD		 3004 amdgpu_atombios_scratch_regs_save(adev);
3005
f9fff064 3006 return dce_v8_0_hw_fini(handle);
a2e73f56
AD		 3007}
3008
5fc3aeeb 3009static int dce_v8_0_resume(void *handle)
a2e73f56 3010{
5fc3aeeb 3011 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
f9fff064
AD		 3012 int ret;
3013
3014 ret = dce_v8_0_hw_init(handle);
a2e73f56
AD		 3015
3016 amdgpu_atombios_scratch_regs_restore(adev);
3017
a2e73f56
AD		 3018 /* turn on the BL */
3019 if (adev->mode_info.bl_encoder) {
3020 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3021 adev->mode_info.bl_encoder);
3022 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3023 bl_level);
3024 }
3025
f9fff064 3026 return ret;
a2e73f56
AD		 3027}
3028
5fc3aeeb 3029static bool dce_v8_0_is_idle(void *handle)
a2e73f56 3030{
a2e73f56
AD		 3031 return true;
3032}
3033
5fc3aeeb 3034static int dce_v8_0_wait_for_idle(void *handle)
a2e73f56 3035{
a2e73f56
AD		 3036 return 0;
3037}
3038
5fc3aeeb 3039static int dce_v8_0_soft_reset(void *handle)
a2e73f56
AD		 3040{
3041 u32 srbm_soft_reset = 0, tmp;
5fc3aeeb 3042 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 3043
3044 if (dce_v8_0_is_display_hung(adev))
3045 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3046
3047 if (srbm_soft_reset) {
a2e73f56
AD		 3048 tmp = RREG32(mmSRBM_SOFT_RESET);
3049 tmp |= srbm_soft_reset;
3050 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3051 WREG32(mmSRBM_SOFT_RESET, tmp);
3052 tmp = RREG32(mmSRBM_SOFT_RESET);
3053
3054 udelay(50);
3055
3056 tmp &= ~srbm_soft_reset;
3057 WREG32(mmSRBM_SOFT_RESET, tmp);
3058 tmp = RREG32(mmSRBM_SOFT_RESET);
3059
3060 /* Wait a little for things to settle down */
3061 udelay(50);
a2e73f56
AD		 3062 }
3063 return 0;
3064}
3065
3066static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3067 int crtc,
3068 enum amdgpu_interrupt_state state)
3069{
3070 u32 reg_block, lb_interrupt_mask;
3071
3072 if (crtc >= adev->mode_info.num_crtc) {
3073 DRM_DEBUG("invalid crtc %d\n", crtc);
3074 return;
3075 }
3076
3077 switch (crtc) {
3078 case 0:
3079 reg_block = CRTC0_REGISTER_OFFSET;
3080 break;
3081 case 1:
3082 reg_block = CRTC1_REGISTER_OFFSET;
3083 break;
3084 case 2:
3085 reg_block = CRTC2_REGISTER_OFFSET;
3086 break;
3087 case 3:
3088 reg_block = CRTC3_REGISTER_OFFSET;
3089 break;
3090 case 4:
3091 reg_block = CRTC4_REGISTER_OFFSET;
3092 break;
3093 case 5:
3094 reg_block = CRTC5_REGISTER_OFFSET;
3095 break;
3096 default:
3097 DRM_DEBUG("invalid crtc %d\n", crtc);
3098 return;
3099 }
3100
3101 switch (state) {
3102 case AMDGPU_IRQ_STATE_DISABLE:
3103 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3104 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3105 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3106 break;
3107 case AMDGPU_IRQ_STATE_ENABLE:
3108 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3109 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3110 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3111 break;
3112 default:
3113 break;
3114 }
3115}
3116
3117static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3118 int crtc,
3119 enum amdgpu_interrupt_state state)
3120{
3121 u32 reg_block, lb_interrupt_mask;
3122
3123 if (crtc >= adev->mode_info.num_crtc) {
3124 DRM_DEBUG("invalid crtc %d\n", crtc);
3125 return;
3126 }
3127
3128 switch (crtc) {
3129 case 0:
3130 reg_block = CRTC0_REGISTER_OFFSET;
3131 break;
3132 case 1:
3133 reg_block = CRTC1_REGISTER_OFFSET;
3134 break;
3135 case 2:
3136 reg_block = CRTC2_REGISTER_OFFSET;
3137 break;
3138 case 3:
3139 reg_block = CRTC3_REGISTER_OFFSET;
3140 break;
3141 case 4:
3142 reg_block = CRTC4_REGISTER_OFFSET;
3143 break;
3144 case 5:
3145 reg_block = CRTC5_REGISTER_OFFSET;
3146 break;
3147 default:
3148 DRM_DEBUG("invalid crtc %d\n", crtc);
3149 return;
3150 }
3151
3152 switch (state) {
3153 case AMDGPU_IRQ_STATE_DISABLE:
3154 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3155 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3156 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3157 break;
3158 case AMDGPU_IRQ_STATE_ENABLE:
3159 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3160 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3161 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3162 break;
3163 default:
3164 break;
3165 }
3166}
3167
3168static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3169 struct amdgpu_irq_src *src,
3170 unsigned type,
3171 enum amdgpu_interrupt_state state)
3172{
3173 u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
3174
3175 switch (type) {
3176 case AMDGPU_HPD_1:
3177 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
3178 break;
3179 case AMDGPU_HPD_2:
3180 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
3181 break;
3182 case AMDGPU_HPD_3:
3183 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
3184 break;
3185 case AMDGPU_HPD_4:
3186 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
3187 break;
3188 case AMDGPU_HPD_5:
3189 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
3190 break;
3191 case AMDGPU_HPD_6:
3192 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
3193 break;
3194 default:
3195 DRM_DEBUG("invalid hdp %d\n", type);
3196 return 0;
3197 }
3198
3199 switch (state) {
3200 case AMDGPU_IRQ_STATE_DISABLE:
3201 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3202 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3203 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3204 break;
3205 case AMDGPU_IRQ_STATE_ENABLE:
3206 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3207 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3208 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3209 break;
3210 default:
3211 break;
3212 }
3213
3214 return 0;
3215}
3216
3217static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3218 struct amdgpu_irq_src *src,
3219 unsigned type,
3220 enum amdgpu_interrupt_state state)
3221{
3222 switch (type) {
3223 case AMDGPU_CRTC_IRQ_VBLANK1:
3224 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3225 break;
3226 case AMDGPU_CRTC_IRQ_VBLANK2:
3227 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3228 break;
3229 case AMDGPU_CRTC_IRQ_VBLANK3:
3230 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3231 break;
3232 case AMDGPU_CRTC_IRQ_VBLANK4:
3233 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3234 break;
3235 case AMDGPU_CRTC_IRQ_VBLANK5:
3236 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3237 break;
3238 case AMDGPU_CRTC_IRQ_VBLANK6:
3239 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3240 break;
3241 case AMDGPU_CRTC_IRQ_VLINE1:
3242 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3243 break;
3244 case AMDGPU_CRTC_IRQ_VLINE2:
3245 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3246 break;
3247 case AMDGPU_CRTC_IRQ_VLINE3:
3248 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3249 break;
3250 case AMDGPU_CRTC_IRQ_VLINE4:
3251 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3252 break;
3253 case AMDGPU_CRTC_IRQ_VLINE5:
3254 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3255 break;
3256 case AMDGPU_CRTC_IRQ_VLINE6:
3257 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3258 break;
3259 default:
3260 break;
3261 }
3262 return 0;
3263}
3264
3265static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3266 struct amdgpu_irq_src *source,
3267 struct amdgpu_iv_entry *entry)
3268{
3269 unsigned crtc = entry->src_id - 1;
3270 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3271 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3272
3273 switch (entry->src_data) {
3274 case 0: /* vblank */
bd833144 3275 if (disp_int & interrupt_status_offsets[crtc].vblank)
a2e73f56 3276 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
bd833144
MK		 3277 else
3278 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3279
3280 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3281 drm_handle_vblank(adev->ddev, crtc);
a2e73f56 3282 }
bd833144
MK		 3283 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3284
a2e73f56
AD		 3285 break;
3286 case 1: /* vline */
bd833144 3287 if (disp_int & interrupt_status_offsets[crtc].vline)
a2e73f56 3288 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
bd833144
MK		 3289 else
3290 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3291
3292 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3293
a2e73f56
AD		 3294 break;
3295 default:
3296 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3297 break;
3298 }
3299
3300 return 0;
3301}
3302
3303static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3304 struct amdgpu_irq_src *src,
3305 unsigned type,
3306 enum amdgpu_interrupt_state state)
3307{
7dfac896
AD		 3308 u32 reg;
3309
3310 if (type >= adev->mode_info.num_crtc) {
3311 DRM_ERROR("invalid pageflip crtc %d\n", type);
3312 return -EINVAL;
a2e73f56
AD		 3313 }
3314
7dfac896 3315 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
a2e73f56 3316 if (state == AMDGPU_IRQ_STATE_DISABLE)
7dfac896
AD		 3317 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3318 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
a2e73f56 3319 else
7dfac896
AD		 3320 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3321 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
a2e73f56
AD		 3322
3323 return 0;
3324}
3325
3326static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3327 struct amdgpu_irq_src *source,
3328 struct amdgpu_iv_entry *entry)
3329{
a2e73f56
AD		 3330 unsigned long flags;
3331 unsigned crtc_id;
3332 struct amdgpu_crtc *amdgpu_crtc;
3333 struct amdgpu_flip_work *works;
3334
3335 crtc_id = (entry->src_id - 8) >> 1;
3336 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3337
7dfac896
AD		 3338 if (crtc_id >= adev->mode_info.num_crtc) {
3339 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3340 return -EINVAL;
a2e73f56
AD		 3341 }
3342
7dfac896
AD		 3343 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3344 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3345 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3346 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
a2e73f56
AD		 3347
3348 /* IRQ could occur when in initial stage */
3349 if (amdgpu_crtc == NULL)
3350 return 0;
3351
3352 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3353 works = amdgpu_crtc->pflip_works;
3354 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3355 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3356 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3357 amdgpu_crtc->pflip_status,
3358 AMDGPU_FLIP_SUBMITTED);
3359 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3360 return 0;
3361 }
3362
3363 /* page flip completed. clean up */
3364 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3365 amdgpu_crtc->pflip_works = NULL;
3366
3367 /* wakeup usersapce */
3368 if (works->event)
56286769 3369 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
a2e73f56
AD		 3370
3371 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3372
60629c4d 3373 drm_crtc_vblank_put(&amdgpu_crtc->base);
87d58c11 3374 schedule_work(&works->unpin_work);
a2e73f56
AD		 3375
3376 return 0;
3377}
3378
3379static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3380 struct amdgpu_irq_src *source,
3381 struct amdgpu_iv_entry *entry)
3382{
3383 uint32_t disp_int, mask, int_control, tmp;
3384 unsigned hpd;
3385
e922cfb1 3386 if (entry->src_data >= adev->mode_info.num_hpd) {
a2e73f56
AD		 3387 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3388 return 0;
3389 }
3390
3391 hpd = entry->src_data;
3392 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3393 mask = interrupt_status_offsets[hpd].hpd;
3394 int_control = hpd_int_control_offsets[hpd];
3395
3396 if (disp_int & mask) {
3397 tmp = RREG32(int_control);
3398 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3399 WREG32(int_control, tmp);
3400 schedule_work(&adev->hotplug_work);
3401 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3402 }
3403
3404 return 0;
3405
3406}
3407
5fc3aeeb 3408static int dce_v8_0_set_clockgating_state(void *handle,
3409 enum amd_clockgating_state state)
a2e73f56
AD		 3410{
3411 return 0;
3412}
3413
5fc3aeeb 3414static int dce_v8_0_set_powergating_state(void *handle,
3415 enum amd_powergating_state state)
a2e73f56
AD		 3416{
3417 return 0;
3418}
3419
5fc3aeeb 3420const struct amd_ip_funcs dce_v8_0_ip_funcs = {
88a907d6 3421 .name = "dce_v8_0",
a2e73f56
AD		 3422 .early_init = dce_v8_0_early_init,
3423 .late_init = NULL,
3424 .sw_init = dce_v8_0_sw_init,
3425 .sw_fini = dce_v8_0_sw_fini,
3426 .hw_init = dce_v8_0_hw_init,
3427 .hw_fini = dce_v8_0_hw_fini,
3428 .suspend = dce_v8_0_suspend,
3429 .resume = dce_v8_0_resume,
3430 .is_idle = dce_v8_0_is_idle,
3431 .wait_for_idle = dce_v8_0_wait_for_idle,
3432 .soft_reset = dce_v8_0_soft_reset,
a2e73f56
AD		 3433 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3434 .set_powergating_state = dce_v8_0_set_powergating_state,
3435};
3436
3437static void
3438dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3439 struct drm_display_mode *mode,
3440 struct drm_display_mode *adjusted_mode)
3441{
3442 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3443
3444 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3445
3446 /* need to call this here rather than in prepare() since we need some crtc info */
3447 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3448
3449 /* set scaler clears this on some chips */
3450 dce_v8_0_set_interleave(encoder->crtc, mode);
3451
3452 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3453 dce_v8_0_afmt_enable(encoder, true);
3454 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3455 }
3456}
3457
3458static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3459{
3460 struct amdgpu_device *adev = encoder->dev->dev_private;
3461 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3462 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3463
3464 if ((amdgpu_encoder->active_device &
3465 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3466 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3467 ENCODER_OBJECT_ID_NONE)) {
3468 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3469 if (dig) {
3470 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3471 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3472 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3473 }
3474 }
3475
3476 amdgpu_atombios_scratch_regs_lock(adev, true);
3477
3478 if (connector) {
3479 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3480
3481 /* select the clock/data port if it uses a router */
3482 if (amdgpu_connector->router.cd_valid)
3483 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3484
3485 /* turn eDP panel on for mode set */
3486 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3487 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3488 ATOM_TRANSMITTER_ACTION_POWER_ON);
3489 }
3490
3491 /* this is needed for the pll/ss setup to work correctly in some cases */
3492 amdgpu_atombios_encoder_set_crtc_source(encoder);
3493 /* set up the FMT blocks */
3494 dce_v8_0_program_fmt(encoder);
3495}
3496
3497static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3498{
3499 struct drm_device *dev = encoder->dev;
3500 struct amdgpu_device *adev = dev->dev_private;
3501
3502 /* need to call this here as we need the crtc set up */
3503 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3504 amdgpu_atombios_scratch_regs_lock(adev, false);
3505}
3506
3507static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3508{
3509 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3510 struct amdgpu_encoder_atom_dig *dig;
3511
3512 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3513
3514 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3515 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3516 dce_v8_0_afmt_enable(encoder, false);
3517 dig = amdgpu_encoder->enc_priv;
3518 dig->dig_encoder = -1;
3519 }
3520 amdgpu_encoder->active_device = 0;
3521}
3522
3523/* these are handled by the primary encoders */
3524static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3525{
3526
3527}
3528
3529static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3530{
3531
3532}
3533
3534static void
3535dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3536 struct drm_display_mode *mode,
3537 struct drm_display_mode *adjusted_mode)
3538{
3539
3540}
3541
3542static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3543{
3544
3545}
3546
3547static void
3548dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3549{
3550
3551}
3552
a2e73f56
AD		 3553static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3554 .dpms = dce_v8_0_ext_dpms,
a2e73f56
AD		 3555 .prepare = dce_v8_0_ext_prepare,
3556 .mode_set = dce_v8_0_ext_mode_set,
3557 .commit = dce_v8_0_ext_commit,
3558 .disable = dce_v8_0_ext_disable,
3559 /* no detect for TMDS/LVDS yet */
3560};
3561
3562static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3563 .dpms = amdgpu_atombios_encoder_dpms,
3564 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3565 .prepare = dce_v8_0_encoder_prepare,
3566 .mode_set = dce_v8_0_encoder_mode_set,
3567 .commit = dce_v8_0_encoder_commit,
3568 .disable = dce_v8_0_encoder_disable,
3569 .detect = amdgpu_atombios_encoder_dig_detect,
3570};
3571
3572static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3573 .dpms = amdgpu_atombios_encoder_dpms,
3574 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3575 .prepare = dce_v8_0_encoder_prepare,
3576 .mode_set = dce_v8_0_encoder_mode_set,
3577 .commit = dce_v8_0_encoder_commit,
3578 .detect = amdgpu_atombios_encoder_dac_detect,
3579};
3580
3581static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3582{
3583 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3584 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3585 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3586 kfree(amdgpu_encoder->enc_priv);
3587 drm_encoder_cleanup(encoder);
3588 kfree(amdgpu_encoder);
3589}
3590
3591static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3592 .destroy = dce_v8_0_encoder_destroy,
3593};
3594
3595static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3596 uint32_t encoder_enum,
3597 uint32_t supported_device,
3598 u16 caps)
3599{
3600 struct drm_device *dev = adev->ddev;
3601 struct drm_encoder *encoder;
3602 struct amdgpu_encoder *amdgpu_encoder;
3603
3604 /* see if we already added it */
3605 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3606 amdgpu_encoder = to_amdgpu_encoder(encoder);
3607 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3608 amdgpu_encoder->devices |= supported_device;
3609 return;
3610 }
3611
3612 }
3613
3614 /* add a new one */
3615 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3616 if (!amdgpu_encoder)
3617 return;
3618
3619 encoder = &amdgpu_encoder->base;
3620 switch (adev->mode_info.num_crtc) {
3621 case 1:
3622 encoder->possible_crtcs = 0x1;
3623 break;
3624 case 2:
3625 default:
3626 encoder->possible_crtcs = 0x3;
3627 break;
3628 case 4:
3629 encoder->possible_crtcs = 0xf;
3630 break;
3631 case 6:
3632 encoder->possible_crtcs = 0x3f;
3633 break;
3634 }
3635
3636 amdgpu_encoder->enc_priv = NULL;
3637
3638 amdgpu_encoder->encoder_enum = encoder_enum;
3639 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3640 amdgpu_encoder->devices = supported_device;
3641 amdgpu_encoder->rmx_type = RMX_OFF;
3642 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3643 amdgpu_encoder->is_ext_encoder = false;
3644 amdgpu_encoder->caps = caps;
3645
3646 switch (amdgpu_encoder->encoder_id) {
3647 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3648 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3649 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3650 DRM_MODE_ENCODER_DAC, NULL);
a2e73f56
AD		 3651 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3652 break;
3653 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3654 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3655 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3656 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3657 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3658 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3659 amdgpu_encoder->rmx_type = RMX_FULL;
3660 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3661 DRM_MODE_ENCODER_LVDS, NULL);
a2e73f56
AD		 3662 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3663 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3664 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3665 DRM_MODE_ENCODER_DAC, NULL);
a2e73f56
AD		 3666 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3667 } else {
3668 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3669 DRM_MODE_ENCODER_TMDS, NULL);
a2e73f56
AD		 3670 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3671 }
3672 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3673 break;
3674 case ENCODER_OBJECT_ID_SI170B:
3675 case ENCODER_OBJECT_ID_CH7303:
3676 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3677 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3678 case ENCODER_OBJECT_ID_TITFP513:
3679 case ENCODER_OBJECT_ID_VT1623:
3680 case ENCODER_OBJECT_ID_HDMI_SI1930:
3681 case ENCODER_OBJECT_ID_TRAVIS:
3682 case ENCODER_OBJECT_ID_NUTMEG:
3683 /* these are handled by the primary encoders */
3684 amdgpu_encoder->is_ext_encoder = true;
3685 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3686 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3687 DRM_MODE_ENCODER_LVDS, NULL);
a2e73f56
AD		 3688 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3689 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3690 DRM_MODE_ENCODER_DAC, NULL);
a2e73f56
AD		 3691 else
3692 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3693 DRM_MODE_ENCODER_TMDS, NULL);
a2e73f56
AD		 3694 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3695 break;
3696 }
3697}
3698
3699static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3700 .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3701 .bandwidth_update = &dce_v8_0_bandwidth_update,
3702 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3703 .vblank_wait = &dce_v8_0_vblank_wait,
3704 .is_display_hung = &dce_v8_0_is_display_hung,
3705 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3706 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3707 .hpd_sense = &dce_v8_0_hpd_sense,
3708 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3709 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3710 .page_flip = &dce_v8_0_page_flip,
3711 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3712 .add_encoder = &dce_v8_0_encoder_add,
3713 .add_connector = &amdgpu_connector_add,
3714 .stop_mc_access = &dce_v8_0_stop_mc_access,
3715 .resume_mc_access = &dce_v8_0_resume_mc_access,
3716};
3717
3718static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3719{
3720 if (adev->mode_info.funcs == NULL)
3721 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3722}
3723
3724static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3725 .set = dce_v8_0_set_crtc_interrupt_state,
3726 .process = dce_v8_0_crtc_irq,
3727};
3728
3729static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3730 .set = dce_v8_0_set_pageflip_interrupt_state,
3731 .process = dce_v8_0_pageflip_irq,
3732};
3733
3734static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3735 .set = dce_v8_0_set_hpd_interrupt_state,
3736 .process = dce_v8_0_hpd_irq,
3737};
3738
3739static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3740{
3741 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3742 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3743
3744 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3745 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3746
3747 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3748 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3749}
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