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drm/amdgpu/dce10: simplify hpd code
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / dce_v8_0.c
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a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "cikd.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34
35#include "dce/dce_8_0_d.h"
36#include "dce/dce_8_0_sh_mask.h"
37
38#include "gca/gfx_7_2_enum.h"
39
40#include "gmc/gmc_7_1_d.h"
41#include "gmc/gmc_7_1_sh_mask.h"
42
43#include "oss/oss_2_0_d.h"
44#include "oss/oss_2_0_sh_mask.h"
45
46static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
47static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
48
49static const u32 crtc_offsets[6] =
50{
51 CRTC0_REGISTER_OFFSET,
52 CRTC1_REGISTER_OFFSET,
53 CRTC2_REGISTER_OFFSET,
54 CRTC3_REGISTER_OFFSET,
55 CRTC4_REGISTER_OFFSET,
56 CRTC5_REGISTER_OFFSET
57};
58
2285b91c
AD		 59static const u32 hpd_offsets[] =
60{
61 HPD0_REGISTER_OFFSET,
62 HPD1_REGISTER_OFFSET,
63 HPD2_REGISTER_OFFSET,
64 HPD3_REGISTER_OFFSET,
65 HPD4_REGISTER_OFFSET,
66 HPD5_REGISTER_OFFSET
67};
68
a2e73f56
AD		 69static const uint32_t dig_offsets[] = {
70 CRTC0_REGISTER_OFFSET,
71 CRTC1_REGISTER_OFFSET,
72 CRTC2_REGISTER_OFFSET,
73 CRTC3_REGISTER_OFFSET,
74 CRTC4_REGISTER_OFFSET,
75 CRTC5_REGISTER_OFFSET,
76 (0x13830 - 0x7030) >> 2,
77};
78
79static const struct {
80 uint32_t reg;
81 uint32_t vblank;
82 uint32_t vline;
83 uint32_t hpd;
84
85} interrupt_status_offsets[6] = { {
86 .reg = mmDISP_INTERRUPT_STATUS,
87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
90}, {
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
95}, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
100}, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
105}, {
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
110}, {
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
115} };
116
a2e73f56
AD		 117static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
118 u32 block_offset, u32 reg)
119{
120 unsigned long flags;
121 u32 r;
122
123 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
124 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
125 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
126 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
127
128 return r;
129}
130
131static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
132 u32 block_offset, u32 reg, u32 v)
133{
134 unsigned long flags;
135
136 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
138 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
139 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
140}
141
142static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
143{
144 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
145 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
146 return true;
147 else
148 return false;
149}
150
151static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
152{
153 u32 pos1, pos2;
154
155 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
156 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
157
158 if (pos1 != pos2)
159 return true;
160 else
161 return false;
162}
163
164/**
165 * dce_v8_0_vblank_wait - vblank wait asic callback.
166 *
167 * @adev: amdgpu_device pointer
168 * @crtc: crtc to wait for vblank on
169 *
170 * Wait for vblank on the requested crtc (evergreen+).
171 */
172static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
173{
e37e4f05 174 unsigned i = 100;
a2e73f56
AD		 175
176 if (crtc >= adev->mode_info.num_crtc)
177 return;
178
179 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
180 return;
181
182 /* depending on when we hit vblank, we may be close to active; if so,
183 * wait for another frame.
184 */
185 while (dce_v8_0_is_in_vblank(adev, crtc)) {
e37e4f05
TSD		 186 if (i++ == 100) {
187 i = 0;
a2e73f56
AD		 188 if (!dce_v8_0_is_counter_moving(adev, crtc))
189 break;
190 }
191 }
192
193 while (!dce_v8_0_is_in_vblank(adev, crtc)) {
e37e4f05
TSD		 194 if (i++ == 100) {
195 i = 0;
a2e73f56
AD		 196 if (!dce_v8_0_is_counter_moving(adev, crtc))
197 break;
198 }
199 }
200}
201
202static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
203{
204 if (crtc >= adev->mode_info.num_crtc)
205 return 0;
206 else
207 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
208}
209
f6c7aba4
MD		 210static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
211{
212 unsigned i;
213
214 /* Enable pflip interrupts */
215 for (i = 0; i < adev->mode_info.num_crtc; i++)
216 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
217}
218
219static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
220{
221 unsigned i;
222
223 /* Disable pflip interrupts */
224 for (i = 0; i < adev->mode_info.num_crtc; i++)
225 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
226}
227
a2e73f56
AD		 228/**
229 * dce_v8_0_page_flip - pageflip callback.
230 *
231 * @adev: amdgpu_device pointer
232 * @crtc_id: crtc to cleanup pageflip on
233 * @crtc_base: new address of the crtc (GPU MC address)
234 *
82326860
AD		 235 * Triggers the actual pageflip by updating the primary
236 * surface base address.
a2e73f56
AD		 237 */
238static void dce_v8_0_page_flip(struct amdgpu_device *adev,
cb9e59d7 239 int crtc_id, u64 crtc_base, bool async)
a2e73f56
AD		 240{
241 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
a2e73f56 242
cb9e59d7
AD		 243 /* flip at hsync for async, default is vsync */
244 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
245 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
82326860 246 /* update the primary scanout addresses */
a2e73f56
AD		 247 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
248 upper_32_bits(crtc_base));
82326860 249 /* writing to the low address triggers the update */
a2e73f56 250 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
82326860
AD		 251 lower_32_bits(crtc_base));
252 /* post the write */
253 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
a2e73f56
AD		 254}
255
256static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
257 u32 *vbl, u32 *position)
258{
259 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
260 return -EINVAL;
261
262 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
263 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
264
265 return 0;
266}
267
268/**
269 * dce_v8_0_hpd_sense - hpd sense callback.
270 *
271 * @adev: amdgpu_device pointer
272 * @hpd: hpd (hotplug detect) pin
273 *
274 * Checks if a digital monitor is connected (evergreen+).
275 * Returns true if connected, false if not connected.
276 */
277static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
278 enum amdgpu_hpd_id hpd)
279{
280 bool connected = false;
281
2285b91c
AD		 282 if (hpd >= adev->mode_info.num_hpd)
283 return connected;
284
285 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
286 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
287 connected = true;
a2e73f56
AD		 288
289 return connected;
290}
291
292/**
293 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
294 *
295 * @adev: amdgpu_device pointer
296 * @hpd: hpd (hotplug detect) pin
297 *
298 * Set the polarity of the hpd pin (evergreen+).
299 */
300static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
301 enum amdgpu_hpd_id hpd)
302{
303 u32 tmp;
304 bool connected = dce_v8_0_hpd_sense(adev, hpd);
305
2285b91c
AD		 306 if (hpd >= adev->mode_info.num_hpd)
307 return;
308
309 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
310 if (connected)
311 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
312 else
313 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
314 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
a2e73f56
AD		 315}
316
317/**
318 * dce_v8_0_hpd_init - hpd setup callback.
319 *
320 * @adev: amdgpu_device pointer
321 *
322 * Setup the hpd pins used by the card (evergreen+).
323 * Enable the pin, set the polarity, and enable the hpd interrupts.
324 */
325static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
326{
327 struct drm_device *dev = adev->ddev;
328 struct drm_connector *connector;
329 u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) |
330 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) |
331 DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
332
333 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
334 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
335
2285b91c
AD		 336 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
337 continue;
338
339 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
32408258
AD		 340
341 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
342 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
343 /* don't try to enable hpd on eDP or LVDS avoid breaking the
344 * aux dp channel on imac and help (but not completely fix)
345 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
346 * also avoid interrupt storms during dpms.
347 */
2285b91c
AD		 348 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
349 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
350 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
32408258
AD		 351 continue;
352 }
353
a2e73f56
AD		 354 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
355 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
356 }
357}
358
359/**
360 * dce_v8_0_hpd_fini - hpd tear down callback.
361 *
362 * @adev: amdgpu_device pointer
363 *
364 * Tear down the hpd pins used by the card (evergreen+).
365 * Disable the hpd interrupts.
366 */
367static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
368{
369 struct drm_device *dev = adev->ddev;
370 struct drm_connector *connector;
371
372 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
373 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
374
2285b91c
AD		 375 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
376 continue;
377
378 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
379
a2e73f56
AD		 380 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
381 }
382}
383
384static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
385{
386 return mmDC_GPIO_HPD_A;
387}
388
389static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
390{
391 u32 crtc_hung = 0;
392 u32 crtc_status[6];
393 u32 i, j, tmp;
394
395 for (i = 0; i < adev->mode_info.num_crtc; i++) {
396 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
397 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
398 crtc_hung |= (1 << i);
399 }
400 }
401
402 for (j = 0; j < 10; j++) {
403 for (i = 0; i < adev->mode_info.num_crtc; i++) {
404 if (crtc_hung & (1 << i)) {
405 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
406 if (tmp != crtc_status[i])
407 crtc_hung &= ~(1 << i);
408 }
409 }
410 if (crtc_hung == 0)
411 return false;
412 udelay(100);
413 }
414
415 return true;
416}
417
418static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
419 struct amdgpu_mode_mc_save *save)
420{
421 u32 crtc_enabled, tmp;
422 int i;
423
424 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
425 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
426
427 /* disable VGA render */
428 tmp = RREG32(mmVGA_RENDER_CONTROL);
429 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
430 WREG32(mmVGA_RENDER_CONTROL, tmp);
431
432 /* blank the display controllers */
433 for (i = 0; i < adev->mode_info.num_crtc; i++) {
434 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
435 CRTC_CONTROL, CRTC_MASTER_EN);
436 if (crtc_enabled) {
5a3f25db 437#if 1
a2e73f56
AD		 438 save->crtc_enabled[i] = true;
439 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
440 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
5a3f25db
JZ		 441 /*it is correct only for RGB ; black is 0*/
442 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
a2e73f56
AD		 443 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
444 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
a2e73f56 445 }
5a3f25db 446 mdelay(20);
a2e73f56
AD		 447#else
448 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
449 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
450 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
451 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
452 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
453 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
454 save->crtc_enabled[i] = false;
455 /* ***** */
456#endif
457 } else {
458 save->crtc_enabled[i] = false;
459 }
460 }
461}
462
463static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
464 struct amdgpu_mode_mc_save *save)
465{
5a3f25db
JZ		 466 u32 tmp;
467 int i;
a2e73f56
AD		 468
469 /* update crtc base addresses */
470 for (i = 0; i < adev->mode_info.num_crtc; i++) {
471 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
472 upper_32_bits(adev->mc.vram_start));
a2e73f56
AD		 473 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
474 (u32)adev->mc.vram_start);
a2e73f56
AD		 475
476 if (save->crtc_enabled[i]) {
a2e73f56
AD		 477 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
478 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
a2e73f56 479 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
a2e73f56 480 }
5a3f25db 481 mdelay(20);
a2e73f56
AD		 482 }
483
484 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
485 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
486
487 /* Unlock vga access */
488 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
489 mdelay(1);
490 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
491}
492
493static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
494 bool render)
495{
496 u32 tmp;
497
498 /* Lockout access through VGA aperture*/
499 tmp = RREG32(mmVGA_HDP_CONTROL);
500 if (render)
501 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
502 else
503 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
504 WREG32(mmVGA_HDP_CONTROL, tmp);
505
506 /* disable VGA render */
507 tmp = RREG32(mmVGA_RENDER_CONTROL);
508 if (render)
509 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
510 else
511 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
512 WREG32(mmVGA_RENDER_CONTROL, tmp);
513}
514
83c9b025
ED		 515static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
516{
517 int num_crtc = 0;
518
519 switch (adev->asic_type) {
520 case CHIP_BONAIRE:
521 case CHIP_HAWAII:
522 num_crtc = 6;
523 break;
524 case CHIP_KAVERI:
525 num_crtc = 4;
526 break;
527 case CHIP_KABINI:
528 case CHIP_MULLINS:
529 num_crtc = 2;
530 break;
531 default:
532 num_crtc = 0;
533 }
534 return num_crtc;
535}
536
537void dce_v8_0_disable_dce(struct amdgpu_device *adev)
538{
539 /*Disable VGA render and enabled crtc, if has DCE engine*/
540 if (amdgpu_atombios_has_dce_engine_info(adev)) {
541 u32 tmp;
542 int crtc_enabled, i;
543
544 dce_v8_0_set_vga_render_state(adev, false);
545
546 /*Disable crtc*/
547 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
548 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
549 CRTC_CONTROL, CRTC_MASTER_EN);
550 if (crtc_enabled) {
551 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
552 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
553 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
554 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
555 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
556 }
557 }
558 }
559}
560
a2e73f56
AD		 561static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
562{
563 struct drm_device *dev = encoder->dev;
564 struct amdgpu_device *adev = dev->dev_private;
565 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
566 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
567 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
568 int bpc = 0;
569 u32 tmp = 0;
570 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
571
572 if (connector) {
573 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
574 bpc = amdgpu_connector_get_monitor_bpc(connector);
575 dither = amdgpu_connector->dither;
576 }
577
578 /* LVDS/eDP FMT is set up by atom */
579 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
580 return;
581
582 /* not needed for analog */
583 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
584 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
585 return;
586
587 if (bpc == 0)
588 return;
589
590 switch (bpc) {
591 case 6:
592 if (dither == AMDGPU_FMT_DITHER_ENABLE)
593 /* XXX sort out optimal dither settings */
594 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
595 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
596 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
597 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
598 else
599 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
600 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
601 break;
602 case 8:
603 if (dither == AMDGPU_FMT_DITHER_ENABLE)
604 /* XXX sort out optimal dither settings */
605 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
606 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
607 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
608 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
609 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
610 else
611 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
612 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
613 break;
614 case 10:
615 if (dither == AMDGPU_FMT_DITHER_ENABLE)
616 /* XXX sort out optimal dither settings */
617 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
618 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
619 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
620 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
621 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
622 else
623 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
624 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
625 break;
626 default:
627 /* not needed */
628 break;
629 }
630
631 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
632}
633
634
635/* display watermark setup */
636/**
637 * dce_v8_0_line_buffer_adjust - Set up the line buffer
638 *
639 * @adev: amdgpu_device pointer
640 * @amdgpu_crtc: the selected display controller
641 * @mode: the current display mode on the selected display
642 * controller
643 *
644 * Setup up the line buffer allocation for
645 * the selected display controller (CIK).
646 * Returns the line buffer size in pixels.
647 */
648static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
649 struct amdgpu_crtc *amdgpu_crtc,
650 struct drm_display_mode *mode)
651{
652 u32 tmp, buffer_alloc, i;
653 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
654 /*
655 * Line Buffer Setup
656 * There are 6 line buffers, one for each display controllers.
657 * There are 3 partitions per LB. Select the number of partitions
658 * to enable based on the display width. For display widths larger
659 * than 4096, you need use to use 2 display controllers and combine
660 * them using the stereo blender.
661 */
662 if (amdgpu_crtc->base.enabled && mode) {
663 if (mode->crtc_hdisplay < 1920) {
664 tmp = 1;
665 buffer_alloc = 2;
666 } else if (mode->crtc_hdisplay < 2560) {
667 tmp = 2;
668 buffer_alloc = 2;
669 } else if (mode->crtc_hdisplay < 4096) {
670 tmp = 0;
2f7d10b3 671 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
a2e73f56
AD		 672 } else {
673 DRM_DEBUG_KMS("Mode too big for LB!\n");
674 tmp = 0;
2f7d10b3 675 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
a2e73f56
AD		 676 }
677 } else {
678 tmp = 1;
679 buffer_alloc = 0;
680 }
681
682 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
683 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
684 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
685
686 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
687 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
688 for (i = 0; i < adev->usec_timeout; i++) {
689 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
690 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
691 break;
692 udelay(1);
693 }
694
695 if (amdgpu_crtc->base.enabled && mode) {
696 switch (tmp) {
697 case 0:
698 default:
699 return 4096 * 2;
700 case 1:
701 return 1920 * 2;
702 case 2:
703 return 2560 * 2;
704 }
705 }
706
707 /* controller not enabled, so no lb used */
708 return 0;
709}
710
711/**
712 * cik_get_number_of_dram_channels - get the number of dram channels
713 *
714 * @adev: amdgpu_device pointer
715 *
716 * Look up the number of video ram channels (CIK).
717 * Used for display watermark bandwidth calculations
718 * Returns the number of dram channels
719 */
720static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
721{
722 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
723
724 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
725 case 0:
726 default:
727 return 1;
728 case 1:
729 return 2;
730 case 2:
731 return 4;
732 case 3:
733 return 8;
734 case 4:
735 return 3;
736 case 5:
737 return 6;
738 case 6:
739 return 10;
740 case 7:
741 return 12;
742 case 8:
743 return 16;
744 }
745}
746
747struct dce8_wm_params {
748 u32 dram_channels; /* number of dram channels */
749 u32 yclk; /* bandwidth per dram data pin in kHz */
750 u32 sclk; /* engine clock in kHz */
751 u32 disp_clk; /* display clock in kHz */
752 u32 src_width; /* viewport width */
753 u32 active_time; /* active display time in ns */
754 u32 blank_time; /* blank time in ns */
755 bool interlaced; /* mode is interlaced */
756 fixed20_12 vsc; /* vertical scale ratio */
757 u32 num_heads; /* number of active crtcs */
758 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
759 u32 lb_size; /* line buffer allocated to pipe */
760 u32 vtaps; /* vertical scaler taps */
761};
762
763/**
764 * dce_v8_0_dram_bandwidth - get the dram bandwidth
765 *
766 * @wm: watermark calculation data
767 *
768 * Calculate the raw dram bandwidth (CIK).
769 * Used for display watermark bandwidth calculations
770 * Returns the dram bandwidth in MBytes/s
771 */
772static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
773{
774 /* Calculate raw DRAM Bandwidth */
775 fixed20_12 dram_efficiency; /* 0.7 */
776 fixed20_12 yclk, dram_channels, bandwidth;
777 fixed20_12 a;
778
779 a.full = dfixed_const(1000);
780 yclk.full = dfixed_const(wm->yclk);
781 yclk.full = dfixed_div(yclk, a);
782 dram_channels.full = dfixed_const(wm->dram_channels * 4);
783 a.full = dfixed_const(10);
784 dram_efficiency.full = dfixed_const(7);
785 dram_efficiency.full = dfixed_div(dram_efficiency, a);
786 bandwidth.full = dfixed_mul(dram_channels, yclk);
787 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
788
789 return dfixed_trunc(bandwidth);
790}
791
792/**
793 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
794 *
795 * @wm: watermark calculation data
796 *
797 * Calculate the dram bandwidth used for display (CIK).
798 * Used for display watermark bandwidth calculations
799 * Returns the dram bandwidth for display in MBytes/s
800 */
801static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
802{
803 /* Calculate DRAM Bandwidth and the part allocated to display. */
804 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
805 fixed20_12 yclk, dram_channels, bandwidth;
806 fixed20_12 a;
807
808 a.full = dfixed_const(1000);
809 yclk.full = dfixed_const(wm->yclk);
810 yclk.full = dfixed_div(yclk, a);
811 dram_channels.full = dfixed_const(wm->dram_channels * 4);
812 a.full = dfixed_const(10);
813 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
814 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
815 bandwidth.full = dfixed_mul(dram_channels, yclk);
816 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
817
818 return dfixed_trunc(bandwidth);
819}
820
821/**
822 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
823 *
824 * @wm: watermark calculation data
825 *
826 * Calculate the data return bandwidth used for display (CIK).
827 * Used for display watermark bandwidth calculations
828 * Returns the data return bandwidth in MBytes/s
829 */
830static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
831{
832 /* Calculate the display Data return Bandwidth */
833 fixed20_12 return_efficiency; /* 0.8 */
834 fixed20_12 sclk, bandwidth;
835 fixed20_12 a;
836
837 a.full = dfixed_const(1000);
838 sclk.full = dfixed_const(wm->sclk);
839 sclk.full = dfixed_div(sclk, a);
840 a.full = dfixed_const(10);
841 return_efficiency.full = dfixed_const(8);
842 return_efficiency.full = dfixed_div(return_efficiency, a);
843 a.full = dfixed_const(32);
844 bandwidth.full = dfixed_mul(a, sclk);
845 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
846
847 return dfixed_trunc(bandwidth);
848}
849
850/**
851 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
852 *
853 * @wm: watermark calculation data
854 *
855 * Calculate the dmif bandwidth used for display (CIK).
856 * Used for display watermark bandwidth calculations
857 * Returns the dmif bandwidth in MBytes/s
858 */
859static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
860{
861 /* Calculate the DMIF Request Bandwidth */
862 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
863 fixed20_12 disp_clk, bandwidth;
864 fixed20_12 a, b;
865
866 a.full = dfixed_const(1000);
867 disp_clk.full = dfixed_const(wm->disp_clk);
868 disp_clk.full = dfixed_div(disp_clk, a);
869 a.full = dfixed_const(32);
870 b.full = dfixed_mul(a, disp_clk);
871
872 a.full = dfixed_const(10);
873 disp_clk_request_efficiency.full = dfixed_const(8);
874 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
875
876 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
877
878 return dfixed_trunc(bandwidth);
879}
880
881/**
882 * dce_v8_0_available_bandwidth - get the min available bandwidth
883 *
884 * @wm: watermark calculation data
885 *
886 * Calculate the min available bandwidth used for display (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the min available bandwidth in MBytes/s
889 */
890static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
891{
892 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
893 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
894 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
895 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
896
897 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
898}
899
900/**
901 * dce_v8_0_average_bandwidth - get the average available bandwidth
902 *
903 * @wm: watermark calculation data
904 *
905 * Calculate the average available bandwidth used for display (CIK).
906 * Used for display watermark bandwidth calculations
907 * Returns the average available bandwidth in MBytes/s
908 */
909static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
910{
911 /* Calculate the display mode Average Bandwidth
912 * DisplayMode should contain the source and destination dimensions,
913 * timing, etc.
914 */
915 fixed20_12 bpp;
916 fixed20_12 line_time;
917 fixed20_12 src_width;
918 fixed20_12 bandwidth;
919 fixed20_12 a;
920
921 a.full = dfixed_const(1000);
922 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
923 line_time.full = dfixed_div(line_time, a);
924 bpp.full = dfixed_const(wm->bytes_per_pixel);
925 src_width.full = dfixed_const(wm->src_width);
926 bandwidth.full = dfixed_mul(src_width, bpp);
927 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
928 bandwidth.full = dfixed_div(bandwidth, line_time);
929
930 return dfixed_trunc(bandwidth);
931}
932
933/**
934 * dce_v8_0_latency_watermark - get the latency watermark
935 *
936 * @wm: watermark calculation data
937 *
938 * Calculate the latency watermark (CIK).
939 * Used for display watermark bandwidth calculations
940 * Returns the latency watermark in ns
941 */
942static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
943{
944 /* First calculate the latency in ns */
945 u32 mc_latency = 2000; /* 2000 ns. */
946 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
947 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
948 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
949 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
950 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
951 (wm->num_heads * cursor_line_pair_return_time);
952 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
953 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
954 u32 tmp, dmif_size = 12288;
955 fixed20_12 a, b, c;
956
957 if (wm->num_heads == 0)
958 return 0;
959
960 a.full = dfixed_const(2);
961 b.full = dfixed_const(1);
962 if ((wm->vsc.full > a.full) ||
963 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
964 (wm->vtaps >= 5) ||
965 ((wm->vsc.full >= a.full) && wm->interlaced))
966 max_src_lines_per_dst_line = 4;
967 else
968 max_src_lines_per_dst_line = 2;
969
970 a.full = dfixed_const(available_bandwidth);
971 b.full = dfixed_const(wm->num_heads);
972 a.full = dfixed_div(a, b);
973
974 b.full = dfixed_const(mc_latency + 512);
975 c.full = dfixed_const(wm->disp_clk);
976 b.full = dfixed_div(b, c);
977
978 c.full = dfixed_const(dmif_size);
979 b.full = dfixed_div(c, b);
980
981 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
982
983 b.full = dfixed_const(1000);
984 c.full = dfixed_const(wm->disp_clk);
985 b.full = dfixed_div(c, b);
986 c.full = dfixed_const(wm->bytes_per_pixel);
987 b.full = dfixed_mul(b, c);
988
989 lb_fill_bw = min(tmp, dfixed_trunc(b));
990
991 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
992 b.full = dfixed_const(1000);
993 c.full = dfixed_const(lb_fill_bw);
994 b.full = dfixed_div(c, b);
995 a.full = dfixed_div(a, b);
996 line_fill_time = dfixed_trunc(a);
997
998 if (line_fill_time < wm->active_time)
999 return latency;
1000 else
1001 return latency + (line_fill_time - wm->active_time);
1002
1003}
1004
1005/**
1006 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1007 * average and available dram bandwidth
1008 *
1009 * @wm: watermark calculation data
1010 *
1011 * Check if the display average bandwidth fits in the display
1012 * dram bandwidth (CIK).
1013 * Used for display watermark bandwidth calculations
1014 * Returns true if the display fits, false if not.
1015 */
1016static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1017{
1018 if (dce_v8_0_average_bandwidth(wm) <=
1019 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1020 return true;
1021 else
1022 return false;
1023}
1024
1025/**
1026 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1027 * average and available bandwidth
1028 *
1029 * @wm: watermark calculation data
1030 *
1031 * Check if the display average bandwidth fits in the display
1032 * available bandwidth (CIK).
1033 * Used for display watermark bandwidth calculations
1034 * Returns true if the display fits, false if not.
1035 */
1036static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1037{
1038 if (dce_v8_0_average_bandwidth(wm) <=
1039 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1040 return true;
1041 else
1042 return false;
1043}
1044
1045/**
1046 * dce_v8_0_check_latency_hiding - check latency hiding
1047 *
1048 * @wm: watermark calculation data
1049 *
1050 * Check latency hiding (CIK).
1051 * Used for display watermark bandwidth calculations
1052 * Returns true if the display fits, false if not.
1053 */
1054static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1055{
1056 u32 lb_partitions = wm->lb_size / wm->src_width;
1057 u32 line_time = wm->active_time + wm->blank_time;
1058 u32 latency_tolerant_lines;
1059 u32 latency_hiding;
1060 fixed20_12 a;
1061
1062 a.full = dfixed_const(1);
1063 if (wm->vsc.full > a.full)
1064 latency_tolerant_lines = 1;
1065 else {
1066 if (lb_partitions <= (wm->vtaps + 1))
1067 latency_tolerant_lines = 1;
1068 else
1069 latency_tolerant_lines = 2;
1070 }
1071
1072 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1073
1074 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1075 return true;
1076 else
1077 return false;
1078}
1079
1080/**
1081 * dce_v8_0_program_watermarks - program display watermarks
1082 *
1083 * @adev: amdgpu_device pointer
1084 * @amdgpu_crtc: the selected display controller
1085 * @lb_size: line buffer size
1086 * @num_heads: number of display controllers in use
1087 *
1088 * Calculate and program the display watermarks for the
1089 * selected display controller (CIK).
1090 */
1091static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1092 struct amdgpu_crtc *amdgpu_crtc,
1093 u32 lb_size, u32 num_heads)
1094{
1095 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1096 struct dce8_wm_params wm_low, wm_high;
1097 u32 pixel_period;
1098 u32 line_time = 0;
1099 u32 latency_watermark_a = 0, latency_watermark_b = 0;
8e36f9d3 1100 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
a2e73f56
AD		 1101
1102 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1103 pixel_period = 1000000 / (u32)mode->clock;
1104 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1105
1106 /* watermark for high clocks */
1107 if (adev->pm.dpm_enabled) {
1108 wm_high.yclk =
1109 amdgpu_dpm_get_mclk(adev, false) * 10;
1110 wm_high.sclk =
1111 amdgpu_dpm_get_sclk(adev, false) * 10;
1112 } else {
1113 wm_high.yclk = adev->pm.current_mclk * 10;
1114 wm_high.sclk = adev->pm.current_sclk * 10;
1115 }
1116
1117 wm_high.disp_clk = mode->clock;
1118 wm_high.src_width = mode->crtc_hdisplay;
1119 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1120 wm_high.blank_time = line_time - wm_high.active_time;
1121 wm_high.interlaced = false;
1122 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1123 wm_high.interlaced = true;
1124 wm_high.vsc = amdgpu_crtc->vsc;
1125 wm_high.vtaps = 1;
1126 if (amdgpu_crtc->rmx_type != RMX_OFF)
1127 wm_high.vtaps = 2;
1128 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1129 wm_high.lb_size = lb_size;
1130 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1131 wm_high.num_heads = num_heads;
1132
1133 /* set for high clocks */
1134 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1135
1136 /* possibly force display priority to high */
1137 /* should really do this at mode validation time... */
1138 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1139 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1140 !dce_v8_0_check_latency_hiding(&wm_high) ||
1141 (adev->mode_info.disp_priority == 2)) {
1142 DRM_DEBUG_KMS("force priority to high\n");
1143 }
1144
1145 /* watermark for low clocks */
1146 if (adev->pm.dpm_enabled) {
1147 wm_low.yclk =
1148 amdgpu_dpm_get_mclk(adev, true) * 10;
1149 wm_low.sclk =
1150 amdgpu_dpm_get_sclk(adev, true) * 10;
1151 } else {
1152 wm_low.yclk = adev->pm.current_mclk * 10;
1153 wm_low.sclk = adev->pm.current_sclk * 10;
1154 }
1155
1156 wm_low.disp_clk = mode->clock;
1157 wm_low.src_width = mode->crtc_hdisplay;
1158 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1159 wm_low.blank_time = line_time - wm_low.active_time;
1160 wm_low.interlaced = false;
1161 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1162 wm_low.interlaced = true;
1163 wm_low.vsc = amdgpu_crtc->vsc;
1164 wm_low.vtaps = 1;
1165 if (amdgpu_crtc->rmx_type != RMX_OFF)
1166 wm_low.vtaps = 2;
1167 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1168 wm_low.lb_size = lb_size;
1169 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1170 wm_low.num_heads = num_heads;
1171
1172 /* set for low clocks */
1173 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1174
1175 /* possibly force display priority to high */
1176 /* should really do this at mode validation time... */
1177 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1178 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1179 !dce_v8_0_check_latency_hiding(&wm_low) ||
1180 (adev->mode_info.disp_priority == 2)) {
1181 DRM_DEBUG_KMS("force priority to high\n");
1182 }
8e36f9d3 1183 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
a2e73f56
AD		 1184 }
1185
1186 /* select wm A */
1187 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1188 tmp = wm_mask;
1189 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1190 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1191 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1192 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1193 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1194 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1195 /* select wm B */
1196 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1197 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1198 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1199 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1200 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1201 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1202 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1203 /* restore original selection */
1204 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1205
1206 /* save values for DPM */
1207 amdgpu_crtc->line_time = line_time;
1208 amdgpu_crtc->wm_high = latency_watermark_a;
1209 amdgpu_crtc->wm_low = latency_watermark_b;
8e36f9d3
AD		 1210 /* Save number of lines the linebuffer leads before the scanout */
1211 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
a2e73f56
AD		 1212}
1213
1214/**
1215 * dce_v8_0_bandwidth_update - program display watermarks
1216 *
1217 * @adev: amdgpu_device pointer
1218 *
1219 * Calculate and program the display watermarks and line
1220 * buffer allocation (CIK).
1221 */
1222static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1223{
1224 struct drm_display_mode *mode = NULL;
1225 u32 num_heads = 0, lb_size;
1226 int i;
1227
1228 amdgpu_update_display_priority(adev);
1229
1230 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1231 if (adev->mode_info.crtcs[i]->base.enabled)
1232 num_heads++;
1233 }
1234 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1235 mode = &adev->mode_info.crtcs[i]->base.mode;
1236 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1237 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1238 lb_size, num_heads);
1239 }
1240}
1241
1242static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1243{
1244 int i;
1245 u32 offset, tmp;
1246
1247 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1248 offset = adev->mode_info.audio.pin[i].offset;
1249 tmp = RREG32_AUDIO_ENDPT(offset,
1250 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1251 if (((tmp &
1252 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1253 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1254 adev->mode_info.audio.pin[i].connected = false;
1255 else
1256 adev->mode_info.audio.pin[i].connected = true;
1257 }
1258}
1259
1260static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1261{
1262 int i;
1263
1264 dce_v8_0_audio_get_connected_pins(adev);
1265
1266 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1267 if (adev->mode_info.audio.pin[i].connected)
1268 return &adev->mode_info.audio.pin[i];
1269 }
1270 DRM_ERROR("No connected audio pins found!\n");
1271 return NULL;
1272}
1273
1274static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1275{
1276 struct amdgpu_device *adev = encoder->dev->dev_private;
1277 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1278 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1279 u32 offset;
1280
1281 if (!dig || !dig->afmt || !dig->afmt->pin)
1282 return;
1283
1284 offset = dig->afmt->offset;
1285
1286 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1287 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1288}
1289
1290static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1291 struct drm_display_mode *mode)
1292{
1293 struct amdgpu_device *adev = encoder->dev->dev_private;
1294 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1295 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1296 struct drm_connector *connector;
1297 struct amdgpu_connector *amdgpu_connector = NULL;
1298 u32 tmp = 0, offset;
1299
1300 if (!dig || !dig->afmt || !dig->afmt->pin)
1301 return;
1302
1303 offset = dig->afmt->pin->offset;
1304
1305 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1306 if (connector->encoder == encoder) {
1307 amdgpu_connector = to_amdgpu_connector(connector);
1308 break;
1309 }
1310 }
1311
1312 if (!amdgpu_connector) {
1313 DRM_ERROR("Couldn't find encoder's connector\n");
1314 return;
1315 }
1316
1317 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1318 if (connector->latency_present[1])
1319 tmp =
1320 (connector->video_latency[1] <<
1321 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1322 (connector->audio_latency[1] <<
1323 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1324 else
1325 tmp =
1326 (0 <<
1327 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1328 (0 <<
1329 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1330 } else {
1331 if (connector->latency_present[0])
1332 tmp =
1333 (connector->video_latency[0] <<
1334 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1335 (connector->audio_latency[0] <<
1336 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1337 else
1338 tmp =
1339 (0 <<
1340 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1341 (0 <<
1342 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1343
1344 }
1345 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1346}
1347
1348static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1349{
1350 struct amdgpu_device *adev = encoder->dev->dev_private;
1351 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1352 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1353 struct drm_connector *connector;
1354 struct amdgpu_connector *amdgpu_connector = NULL;
1355 u32 offset, tmp;
1356 u8 *sadb = NULL;
1357 int sad_count;
1358
1359 if (!dig || !dig->afmt || !dig->afmt->pin)
1360 return;
1361
1362 offset = dig->afmt->pin->offset;
1363
1364 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1365 if (connector->encoder == encoder) {
1366 amdgpu_connector = to_amdgpu_connector(connector);
1367 break;
1368 }
1369 }
1370
1371 if (!amdgpu_connector) {
1372 DRM_ERROR("Couldn't find encoder's connector\n");
1373 return;
1374 }
1375
1376 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1377 if (sad_count < 0) {
1378 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1379 sad_count = 0;
1380 }
1381
1382 /* program the speaker allocation */
1383 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1384 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1385 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1386 /* set HDMI mode */
1387 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1388 if (sad_count)
1389 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1390 else
1391 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1392 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1393
1394 kfree(sadb);
1395}
1396
1397static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1398{
1399 struct amdgpu_device *adev = encoder->dev->dev_private;
1400 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1401 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1402 u32 offset;
1403 struct drm_connector *connector;
1404 struct amdgpu_connector *amdgpu_connector = NULL;
1405 struct cea_sad *sads;
1406 int i, sad_count;
1407
1408 static const u16 eld_reg_to_type[][2] = {
1409 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1410 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1411 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1412 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1413 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1414 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1415 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1416 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1417 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1418 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1419 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1420 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1421 };
1422
1423 if (!dig || !dig->afmt || !dig->afmt->pin)
1424 return;
1425
1426 offset = dig->afmt->pin->offset;
1427
1428 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1429 if (connector->encoder == encoder) {
1430 amdgpu_connector = to_amdgpu_connector(connector);
1431 break;
1432 }
1433 }
1434
1435 if (!amdgpu_connector) {
1436 DRM_ERROR("Couldn't find encoder's connector\n");
1437 return;
1438 }
1439
1440 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1441 if (sad_count <= 0) {
1442 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1443 return;
1444 }
1445 BUG_ON(!sads);
1446
1447 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1448 u32 value = 0;
1449 u8 stereo_freqs = 0;
1450 int max_channels = -1;
1451 int j;
1452
1453 for (j = 0; j < sad_count; j++) {
1454 struct cea_sad *sad = &sads[j];
1455
1456 if (sad->format == eld_reg_to_type[i][1]) {
1457 if (sad->channels > max_channels) {
5da25cd5
AD		 1458 value = (sad->channels <<
1459 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1460 (sad->byte2 <<
1461 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1462 (sad->freq <<
1463 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1464 max_channels = sad->channels;
a2e73f56
AD		 1465 }
1466
1467 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1468 stereo_freqs |= sad->freq;
1469 else
1470 break;
1471 }
1472 }
1473
1474 value |= (stereo_freqs <<
1475 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1476
1477 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1478 }
1479
1480 kfree(sads);
1481}
1482
1483static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1484 struct amdgpu_audio_pin *pin,
1485 bool enable)
1486{
1487 if (!pin)
1488 return;
1489
1490 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1491 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1492}
1493
1494static const u32 pin_offsets[7] =
1495{
1496 (0x1780 - 0x1780),
1497 (0x1786 - 0x1780),
1498 (0x178c - 0x1780),
1499 (0x1792 - 0x1780),
1500 (0x1798 - 0x1780),
1501 (0x179d - 0x1780),
1502 (0x17a4 - 0x1780),
1503};
1504
1505static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1506{
1507 int i;
1508
1509 if (!amdgpu_audio)
1510 return 0;
1511
1512 adev->mode_info.audio.enabled = true;
1513
1514 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1515 adev->mode_info.audio.num_pins = 7;
1516 else if ((adev->asic_type == CHIP_KABINI) ||
1517 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1518 adev->mode_info.audio.num_pins = 3;
1519 else if ((adev->asic_type == CHIP_BONAIRE) ||
1520 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1521 adev->mode_info.audio.num_pins = 7;
1522 else
1523 adev->mode_info.audio.num_pins = 3;
1524
1525 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1526 adev->mode_info.audio.pin[i].channels = -1;
1527 adev->mode_info.audio.pin[i].rate = -1;
1528 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1529 adev->mode_info.audio.pin[i].status_bits = 0;
1530 adev->mode_info.audio.pin[i].category_code = 0;
1531 adev->mode_info.audio.pin[i].connected = false;
1532 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1533 adev->mode_info.audio.pin[i].id = i;
1534 /* disable audio. it will be set up later */
1535 /* XXX remove once we switch to ip funcs */
1536 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1537 }
1538
1539 return 0;
1540}
1541
1542static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1543{
1544 int i;
1545
84cffef1
TSD		 1546 if (!amdgpu_audio)
1547 return;
1548
a2e73f56
AD		 1549 if (!adev->mode_info.audio.enabled)
1550 return;
1551
1552 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1553 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1554
1555 adev->mode_info.audio.enabled = false;
1556}
1557
1558/*
1559 * update the N and CTS parameters for a given pixel clock rate
1560 */
1561static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1562{
1563 struct drm_device *dev = encoder->dev;
1564 struct amdgpu_device *adev = dev->dev_private;
1565 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1566 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1567 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1568 uint32_t offset = dig->afmt->offset;
1569
75cd45a4 1570 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
a2e73f56
AD		 1571 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1572
1573 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1574 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1575
1576 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1577 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1578}
1579
1580/*
1581 * build a HDMI Video Info Frame
1582 */
1583static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1584 void *buffer, size_t size)
1585{
1586 struct drm_device *dev = encoder->dev;
1587 struct amdgpu_device *adev = dev->dev_private;
1588 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1589 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1590 uint32_t offset = dig->afmt->offset;
1591 uint8_t *frame = buffer + 3;
1592 uint8_t *header = buffer;
1593
1594 WREG32(mmAFMT_AVI_INFO0 + offset,
1595 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1596 WREG32(mmAFMT_AVI_INFO1 + offset,
1597 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1598 WREG32(mmAFMT_AVI_INFO2 + offset,
1599 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1600 WREG32(mmAFMT_AVI_INFO3 + offset,
1601 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1602}
1603
1604static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1605{
1606 struct drm_device *dev = encoder->dev;
1607 struct amdgpu_device *adev = dev->dev_private;
1608 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1609 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1610 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1611 u32 dto_phase = 24 * 1000;
1612 u32 dto_modulo = clock;
1613
1614 if (!dig || !dig->afmt)
1615 return;
1616
1617 /* XXX two dtos; generally use dto0 for hdmi */
1618 /* Express [24MHz / target pixel clock] as an exact rational
1619 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1620 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1621 */
1622 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1623 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1624 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1625}
1626
1627/*
1628 * update the info frames with the data from the current display mode
1629 */
1630static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1631 struct drm_display_mode *mode)
1632{
1633 struct drm_device *dev = encoder->dev;
1634 struct amdgpu_device *adev = dev->dev_private;
1635 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1636 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1637 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1638 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1639 struct hdmi_avi_infoframe frame;
1640 uint32_t offset, val;
1641 ssize_t err;
1642 int bpc = 8;
1643
1644 if (!dig || !dig->afmt)
1645 return;
1646
1647 /* Silent, r600_hdmi_enable will raise WARN for us */
1648 if (!dig->afmt->enabled)
1649 return;
dfaf2291 1650
a2e73f56
AD		 1651 offset = dig->afmt->offset;
1652
1653 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1654 if (encoder->crtc) {
1655 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1656 bpc = amdgpu_crtc->bpc;
1657 }
1658
1659 /* disable audio prior to setting up hw */
1660 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1661 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1662
1663 dce_v8_0_audio_set_dto(encoder, mode->clock);
1664
1665 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1666 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1667
1668 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1669
1670 val = RREG32(mmHDMI_CONTROL + offset);
1671 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1672 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1673
1674 switch (bpc) {
1675 case 0:
1676 case 6:
1677 case 8:
1678 case 16:
1679 default:
1680 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1681 connector->name, bpc);
1682 break;
1683 case 10:
1684 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1685 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1686 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1687 connector->name);
1688 break;
1689 case 12:
1690 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1691 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1692 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1693 connector->name);
1694 break;
1695 }
1696
1697 WREG32(mmHDMI_CONTROL + offset, val);
1698
1699 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1700 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1701 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1702 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1703
1704 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1705 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1706 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1707
1708 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1709 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1710
1711 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1712 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1713
1714 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1715
1716 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1717 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1718 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1719
1720 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1721 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1722
1723 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1724
1725 if (bpc > 8)
1726 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1727 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1728 else
1729 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1730 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1731 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1732
1733 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1734
1735 WREG32(mmAFMT_60958_0 + offset,
1736 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1737
1738 WREG32(mmAFMT_60958_1 + offset,
1739 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1740
1741 WREG32(mmAFMT_60958_2 + offset,
1742 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1743 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1744 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1745 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1746 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1747 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1748
1749 dce_v8_0_audio_write_speaker_allocation(encoder);
1750
1751
1752 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1753 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1754
1755 dce_v8_0_afmt_audio_select_pin(encoder);
1756 dce_v8_0_audio_write_sad_regs(encoder);
1757 dce_v8_0_audio_write_latency_fields(encoder, mode);
1758
1759 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1760 if (err < 0) {
1761 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1762 return;
1763 }
1764
1765 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1766 if (err < 0) {
1767 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1768 return;
1769 }
1770
1771 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1772
1773 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1774 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
dfaf2291 1775 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
a2e73f56
AD		 1776
1777 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1778 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1779 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1780
1781 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1782 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1783
a2e73f56
AD		 1784 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1785 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1786 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1787 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1788
dfaf2291 1789 /* enable audio after setting up hw */
a2e73f56
AD		 1790 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1791}
1792
1793static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1794{
1795 struct drm_device *dev = encoder->dev;
1796 struct amdgpu_device *adev = dev->dev_private;
1797 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1798 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1799
1800 if (!dig || !dig->afmt)
1801 return;
1802
1803 /* Silent, r600_hdmi_enable will raise WARN for us */
1804 if (enable && dig->afmt->enabled)
1805 return;
1806 if (!enable && !dig->afmt->enabled)
1807 return;
1808
1809 if (!enable && dig->afmt->pin) {
1810 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1811 dig->afmt->pin = NULL;
1812 }
1813
1814 dig->afmt->enabled = enable;
1815
1816 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1817 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1818}
1819
ff923479 1820static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
a2e73f56
AD		 1821{
1822 int i;
1823
1824 for (i = 0; i < adev->mode_info.num_dig; i++)
1825 adev->mode_info.afmt[i] = NULL;
1826
1827 /* DCE8 has audio blocks tied to DIG encoders */
1828 for (i = 0; i < adev->mode_info.num_dig; i++) {
1829 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1830 if (adev->mode_info.afmt[i]) {
1831 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1832 adev->mode_info.afmt[i]->id = i;
ff923479
TSD		 1833 } else {
1834 int j;
1835 for (j = 0; j < i; j++) {
1836 kfree(adev->mode_info.afmt[j]);
1837 adev->mode_info.afmt[j] = NULL;
1838 }
1839 return -ENOMEM;
a2e73f56
AD		 1840 }
1841 }
ff923479 1842 return 0;
a2e73f56
AD		 1843}
1844
1845static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1846{
1847 int i;
1848
1849 for (i = 0; i < adev->mode_info.num_dig; i++) {
1850 kfree(adev->mode_info.afmt[i]);
1851 adev->mode_info.afmt[i] = NULL;
1852 }
1853}
1854
1855static const u32 vga_control_regs[6] =
1856{
1857 mmD1VGA_CONTROL,
1858 mmD2VGA_CONTROL,
1859 mmD3VGA_CONTROL,
1860 mmD4VGA_CONTROL,
1861 mmD5VGA_CONTROL,
1862 mmD6VGA_CONTROL,
1863};
1864
1865static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1866{
1867 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1868 struct drm_device *dev = crtc->dev;
1869 struct amdgpu_device *adev = dev->dev_private;
1870 u32 vga_control;
1871
1872 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1873 if (enable)
1874 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1875 else
1876 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1877}
1878
1879static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1880{
1881 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1882 struct drm_device *dev = crtc->dev;
1883 struct amdgpu_device *adev = dev->dev_private;
1884
1885 if (enable)
1886 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1887 else
1888 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1889}
1890
a2e73f56
AD		 1891static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1892 struct drm_framebuffer *fb,
1893 int x, int y, int atomic)
1894{
1895 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1896 struct drm_device *dev = crtc->dev;
1897 struct amdgpu_device *adev = dev->dev_private;
1898 struct amdgpu_framebuffer *amdgpu_fb;
1899 struct drm_framebuffer *target_fb;
1900 struct drm_gem_object *obj;
765e7fbf 1901 struct amdgpu_bo *abo;
a2e73f56
AD		 1902 uint64_t fb_location, tiling_flags;
1903 uint32_t fb_format, fb_pitch_pixels;
a2e73f56 1904 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
fbd76d59 1905 u32 pipe_config;
cb9e59d7 1906 u32 viewport_w, viewport_h;
a2e73f56
AD		 1907 int r;
1908 bool bypass_lut = false;
d3828147 1909 char *format_name;
a2e73f56
AD		 1910
1911 /* no fb bound */
1912 if (!atomic && !crtc->primary->fb) {
1913 DRM_DEBUG_KMS("No FB bound\n");
1914 return 0;
1915 }
1916
1917 if (atomic) {
1918 amdgpu_fb = to_amdgpu_framebuffer(fb);
1919 target_fb = fb;
92821c26 1920 } else {
a2e73f56
AD		 1921 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1922 target_fb = crtc->primary->fb;
1923 }
1924
1925 /* If atomic, assume fb object is pinned & idle & fenced and
1926 * just update base pointers
1927 */
1928 obj = amdgpu_fb->obj;
765e7fbf
CK		 1929 abo = gem_to_amdgpu_bo(obj);
1930 r = amdgpu_bo_reserve(abo, false);
a2e73f56
AD		 1931 if (unlikely(r != 0))
1932 return r;
1933
92821c26 1934 if (atomic) {
765e7fbf 1935 fb_location = amdgpu_bo_gpu_offset(abo);
92821c26 1936 } else {
765e7fbf 1937 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
a2e73f56 1938 if (unlikely(r != 0)) {
765e7fbf 1939 amdgpu_bo_unreserve(abo);
a2e73f56
AD		 1940 return -EINVAL;
1941 }
1942 }
1943
765e7fbf
CK		 1944 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1945 amdgpu_bo_unreserve(abo);
a2e73f56 1946
fbd76d59
MO		 1947 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1948
a2e73f56
AD		 1949 switch (target_fb->pixel_format) {
1950 case DRM_FORMAT_C8:
1951 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1952 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1953 break;
1954 case DRM_FORMAT_XRGB4444:
1955 case DRM_FORMAT_ARGB4444:
1956 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
75cd45a4 1957 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
a2e73f56
AD		 1958#ifdef __BIG_ENDIAN
1959 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1960#endif
1961 break;
1962 case DRM_FORMAT_XRGB1555:
1963 case DRM_FORMAT_ARGB1555:
1964 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1965 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1966#ifdef __BIG_ENDIAN
1967 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1968#endif
1969 break;
1970 case DRM_FORMAT_BGRX5551:
1971 case DRM_FORMAT_BGRA5551:
1972 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1973 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1974#ifdef __BIG_ENDIAN
1975 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1976#endif
1977 break;
1978 case DRM_FORMAT_RGB565:
1979 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1980 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1981#ifdef __BIG_ENDIAN
1982 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1983#endif
1984 break;
1985 case DRM_FORMAT_XRGB8888:
1986 case DRM_FORMAT_ARGB8888:
1987 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1988 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1989#ifdef __BIG_ENDIAN
1990 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1991#endif
1992 break;
1993 case DRM_FORMAT_XRGB2101010:
1994 case DRM_FORMAT_ARGB2101010:
1995 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1996 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1997#ifdef __BIG_ENDIAN
1998 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1999#endif
2000 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2001 bypass_lut = true;
2002 break;
2003 case DRM_FORMAT_BGRX1010102:
2004 case DRM_FORMAT_BGRA1010102:
2005 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2006 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2007#ifdef __BIG_ENDIAN
2008 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2009#endif
2010 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2011 bypass_lut = true;
2012 break;
2013 default:
90844f00
EE		 2014 format_name = drm_get_format_name(target_fb->pixel_format);
2015 DRM_ERROR("Unsupported screen format %s\n", format_name);
2016 kfree(format_name);
a2e73f56
AD		 2017 return -EINVAL;
2018 }
2019
fbd76d59
MO		 2020 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2021 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
a2e73f56 2022
fbd76d59
MO		 2023 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2024 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2025 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2026 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2027 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
a2e73f56 2028
a2e73f56
AD		 2029 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2030 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2031 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2032 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2033 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2034 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2035 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
fbd76d59 2036 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
a2e73f56
AD		 2037 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2038 }
2039
a2e73f56
AD		 2040 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2041
2042 dce_v8_0_vga_enable(crtc, false);
2043
cb9e59d7
AD		 2044 /* Make sure surface address is updated at vertical blank rather than
2045 * horizontal blank
2046 */
2047 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
2048
a2e73f56
AD		 2049 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2050 upper_32_bits(fb_location));
2051 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2052 upper_32_bits(fb_location));
2053 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2054 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2055 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2056 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2057 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2058 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2059
2060 /*
2061 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2062 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2063 * retain the full precision throughout the pipeline.
2064 */
2065 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2066 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2067 ~LUT_10BIT_BYPASS_EN);
2068
2069 if (bypass_lut)
2070 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2071
2072 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2073 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2074 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2075 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2076 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2077 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2078
2079 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2080 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2081
2082 dce_v8_0_grph_enable(crtc, true);
2083
2084 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2085 target_fb->height);
2086
2087 x &= ~3;
2088 y &= ~1;
2089 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2090 (x << 16) | y);
2091 viewport_w = crtc->mode.hdisplay;
2092 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2093 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2094 (viewport_w << 16) | viewport_h);
2095
3fd4b751
MD		 2096 /* set pageflip to happen anywhere in vblank interval */
2097 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
a2e73f56
AD		 2098
2099 if (!atomic && fb && fb != crtc->primary->fb) {
2100 amdgpu_fb = to_amdgpu_framebuffer(fb);
765e7fbf
CK		 2101 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2102 r = amdgpu_bo_reserve(abo, false);
a2e73f56
AD		 2103 if (unlikely(r != 0))
2104 return r;
765e7fbf
CK		 2105 amdgpu_bo_unpin(abo);
2106 amdgpu_bo_unreserve(abo);
a2e73f56
AD		 2107 }
2108
2109 /* Bytes per pixel may have changed */
2110 dce_v8_0_bandwidth_update(adev);
2111
2112 return 0;
2113}
2114
2115static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2116 struct drm_display_mode *mode)
2117{
2118 struct drm_device *dev = crtc->dev;
2119 struct amdgpu_device *adev = dev->dev_private;
2120 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2121
2122 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2123 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2124 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2125 else
2126 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2127}
2128
2129static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2130{
2131 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2132 struct drm_device *dev = crtc->dev;
2133 struct amdgpu_device *adev = dev->dev_private;
2134 int i;
2135
2136 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2137
2138 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2139 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2140 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2141 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2142 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2143 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2144 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2145 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2146 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2147 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2148
2149 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2150
2151 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2152 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2153 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2154
2155 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2156 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2157 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2158
2159 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2160 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2161
2162 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2163 for (i = 0; i < 256; i++) {
2164 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2165 (amdgpu_crtc->lut_r[i] << 20) |
2166 (amdgpu_crtc->lut_g[i] << 10) |
2167 (amdgpu_crtc->lut_b[i] << 0));
2168 }
2169
2170 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2171 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2172 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2173 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2174 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2175 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2176 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2177 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2178 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2179 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2180 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2181 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2182 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2183 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2184 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2185 /* XXX this only needs to be programmed once per crtc at startup,
2186 * not sure where the best place for it is
2187 */
2188 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2189 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2190}
2191
2192static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2193{
2194 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2195 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2196
2197 switch (amdgpu_encoder->encoder_id) {
2198 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2199 if (dig->linkb)
2200 return 1;
2201 else
2202 return 0;
2203 break;
2204 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2205 if (dig->linkb)
2206 return 3;
2207 else
2208 return 2;
2209 break;
2210 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2211 if (dig->linkb)
2212 return 5;
2213 else
2214 return 4;
2215 break;
2216 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2217 return 6;
2218 break;
2219 default:
2220 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2221 return 0;
2222 }
2223}
2224
2225/**
2226 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2227 *
2228 * @crtc: drm crtc
2229 *
2230 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2231 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2232 * monitors a dedicated PPLL must be used. If a particular board has
2233 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2234 * as there is no need to program the PLL itself. If we are not able to
2235 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2236 * avoid messing up an existing monitor.
2237 *
2238 * Asic specific PLL information
2239 *
2240 * DCE 8.x
2241 * KB/KV
2242 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2243 * CI
2244 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2245 *
2246 */
2247static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2248{
2249 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2250 struct drm_device *dev = crtc->dev;
2251 struct amdgpu_device *adev = dev->dev_private;
2252 u32 pll_in_use;
2253 int pll;
2254
2255 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2256 if (adev->clock.dp_extclk)
2257 /* skip PPLL programming if using ext clock */
2258 return ATOM_PPLL_INVALID;
2259 else {
2260 /* use the same PPLL for all DP monitors */
2261 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2262 if (pll != ATOM_PPLL_INVALID)
2263 return pll;
2264 }
2265 } else {
2266 /* use the same PPLL for all monitors with the same clock */
2267 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2268 if (pll != ATOM_PPLL_INVALID)
2269 return pll;
2270 }
2271 /* otherwise, pick one of the plls */
2272 if ((adev->asic_type == CHIP_KABINI) ||
2273 (adev->asic_type == CHIP_MULLINS)) {
2274 /* KB/ML has PPLL1 and PPLL2 */
2275 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2276 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2277 return ATOM_PPLL2;
2278 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2279 return ATOM_PPLL1;
2280 DRM_ERROR("unable to allocate a PPLL\n");
2281 return ATOM_PPLL_INVALID;
2282 } else {
2283 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2284 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2285 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2286 return ATOM_PPLL2;
2287 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2288 return ATOM_PPLL1;
2289 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2290 return ATOM_PPLL0;
2291 DRM_ERROR("unable to allocate a PPLL\n");
2292 return ATOM_PPLL_INVALID;
2293 }
2294 return ATOM_PPLL_INVALID;
2295}
2296
2297static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2298{
2299 struct amdgpu_device *adev = crtc->dev->dev_private;
2300 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2301 uint32_t cur_lock;
2302
2303 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2304 if (lock)
2305 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2306 else
2307 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2308 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2309}
2310
2311static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2312{
2313 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2314 struct amdgpu_device *adev = crtc->dev->dev_private;
2315
2316 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2317 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2318 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2319}
2320
2321static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2322{
2323 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2324 struct amdgpu_device *adev = crtc->dev->dev_private;
2325
a2df42da
AD		 2326 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2327 upper_32_bits(amdgpu_crtc->cursor_addr));
2328 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2329 lower_32_bits(amdgpu_crtc->cursor_addr));
2330
a2e73f56
AD		 2331 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2332 CUR_CONTROL__CURSOR_EN_MASK |
2333 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2334 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2335}
2336
77ed35b8
AD		 2337static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2338 int x, int y)
a2e73f56
AD		 2339{
2340 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2341 struct amdgpu_device *adev = crtc->dev->dev_private;
2342 int xorigin = 0, yorigin = 0;
2343
2344 /* avivo cursor are offset into the total surface */
2345 x += crtc->x;
2346 y += crtc->y;
2347 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2348
2349 if (x < 0) {
2350 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2351 x = 0;
2352 }
2353 if (y < 0) {
2354 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2355 y = 0;
2356 }
2357
a2e73f56
AD		 2358 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2359 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2360 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2361 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
77ed35b8
AD		 2362
2363 amdgpu_crtc->cursor_x = x;
2364 amdgpu_crtc->cursor_y = y;
a2e73f56
AD		 2365
2366 return 0;
2367}
2368
77ed35b8
AD		 2369static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2370 int x, int y)
2371{
2372 int ret;
2373
2374 dce_v8_0_lock_cursor(crtc, true);
2375 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2376 dce_v8_0_lock_cursor(crtc, false);
2377
2378 return ret;
2379}
2380
2381static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2382 struct drm_file *file_priv,
2383 uint32_t handle,
2384 uint32_t width,
2385 uint32_t height,
2386 int32_t hot_x,
2387 int32_t hot_y)
a2e73f56
AD		 2388{
2389 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2390 struct drm_gem_object *obj;
72b40067 2391 struct amdgpu_bo *aobj;
a2e73f56
AD		 2392 int ret;
2393
2394 if (!handle) {
2395 /* turn off cursor */
2396 dce_v8_0_hide_cursor(crtc);
2397 obj = NULL;
2398 goto unpin;
2399 }
2400
2401 if ((width > amdgpu_crtc->max_cursor_width) ||
2402 (height > amdgpu_crtc->max_cursor_height)) {
2403 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2404 return -EINVAL;
2405 }
2406
a8ad0bd8 2407 obj = drm_gem_object_lookup(file_priv, handle);
a2e73f56
AD		 2408 if (!obj) {
2409 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2410 return -ENOENT;
2411 }
2412
72b40067
AD		 2413 aobj = gem_to_amdgpu_bo(obj);
2414 ret = amdgpu_bo_reserve(aobj, false);
2415 if (ret != 0) {
2416 drm_gem_object_unreference_unlocked(obj);
2417 return ret;
2418 }
2419
2420 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2421 amdgpu_bo_unreserve(aobj);
2422 if (ret) {
2423 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2424 drm_gem_object_unreference_unlocked(obj);
2425 return ret;
2426 }
a2e73f56
AD		 2427
2428 amdgpu_crtc->cursor_width = width;
2429 amdgpu_crtc->cursor_height = height;
2430
2431 dce_v8_0_lock_cursor(crtc, true);
c4e0dfad
AD		 2432
2433 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2434 hot_y != amdgpu_crtc->cursor_hot_y) {
2435 int x, y;
2436
2437 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2438 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2439
2440 dce_v8_0_cursor_move_locked(crtc, x, y);
2441
2442 amdgpu_crtc->cursor_hot_x = hot_x;
2443 amdgpu_crtc->cursor_hot_y = hot_y;
2444 }
2445
a2e73f56
AD		 2446 dce_v8_0_show_cursor(crtc);
2447 dce_v8_0_lock_cursor(crtc, false);
2448
2449unpin:
2450 if (amdgpu_crtc->cursor_bo) {
fd70cf63
AD		 2451 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2452 ret = amdgpu_bo_reserve(aobj, false);
a2e73f56 2453 if (likely(ret == 0)) {
fd70cf63
AD		 2454 amdgpu_bo_unpin(aobj);
2455 amdgpu_bo_unreserve(aobj);
a2e73f56
AD		 2456 }
2457 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2458 }
2459
2460 amdgpu_crtc->cursor_bo = obj;
2461 return 0;
fd70cf63 2462}
a2e73f56 2463
fd70cf63
AD		 2464static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2465{
2466 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
fd70cf63
AD		 2467
2468 if (amdgpu_crtc->cursor_bo) {
2469 dce_v8_0_lock_cursor(crtc, true);
2470
2471 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2472 amdgpu_crtc->cursor_y);
2473
72b40067 2474 dce_v8_0_show_cursor(crtc);
fd70cf63
AD		 2475
2476 dce_v8_0_lock_cursor(crtc, false);
2477 }
a2e73f56
AD		 2478}
2479
7ea77283
ML		 2480static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2481 u16 *blue, uint32_t size)
a2e73f56
AD		 2482{
2483 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7ea77283 2484 int i;
a2e73f56
AD		 2485
2486 /* userspace palettes are always correct as is */
7ea77283 2487 for (i = 0; i < size; i++) {
a2e73f56
AD		 2488 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2489 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2490 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2491 }
2492 dce_v8_0_crtc_load_lut(crtc);
7ea77283
ML		 2493
2494 return 0;
a2e73f56
AD		 2495}
2496
2497static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2498{
2499 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2500
2501 drm_crtc_cleanup(crtc);
a2e73f56
AD		 2502 kfree(amdgpu_crtc);
2503}
2504
2505static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
77ed35b8 2506 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
a2e73f56
AD		 2507 .cursor_move = dce_v8_0_crtc_cursor_move,
2508 .gamma_set = dce_v8_0_crtc_gamma_set,
2509 .set_config = amdgpu_crtc_set_config,
2510 .destroy = dce_v8_0_crtc_destroy,
325cbba1 2511 .page_flip_target = amdgpu_crtc_page_flip_target,
a2e73f56
AD		 2512};
2513
2514static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2515{
2516 struct drm_device *dev = crtc->dev;
2517 struct amdgpu_device *adev = dev->dev_private;
2518 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1002d718 2519 unsigned type;
a2e73f56
AD		 2520
2521 switch (mode) {
2522 case DRM_MODE_DPMS_ON:
2523 amdgpu_crtc->enabled = true;
2524 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2525 dce_v8_0_vga_enable(crtc, true);
2526 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2527 dce_v8_0_vga_enable(crtc, false);
f6c7aba4 2528 /* Make sure VBLANK and PFLIP interrupts are still enabled */
1002d718
MD		 2529 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2530 amdgpu_irq_update(adev, &adev->crtc_irq, type);
f6c7aba4 2531 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
9a7841e9 2532 drm_crtc_vblank_on(crtc);
a2e73f56
AD		 2533 dce_v8_0_crtc_load_lut(crtc);
2534 break;
2535 case DRM_MODE_DPMS_STANDBY:
2536 case DRM_MODE_DPMS_SUSPEND:
2537 case DRM_MODE_DPMS_OFF:
9a7841e9 2538 drm_crtc_vblank_off(crtc);
a2e73f56
AD		 2539 if (amdgpu_crtc->enabled) {
2540 dce_v8_0_vga_enable(crtc, true);
2541 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2542 dce_v8_0_vga_enable(crtc, false);
2543 }
2544 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2545 amdgpu_crtc->enabled = false;
2546 break;
2547 }
2548 /* adjust pm to dpms */
2549 amdgpu_pm_compute_clocks(adev);
2550}
2551
2552static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2553{
2554 /* disable crtc pair power gating before programming */
2555 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2556 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2557 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2558}
2559
2560static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2561{
2562 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2563 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2564}
2565
2566static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2567{
2568 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2569 struct drm_device *dev = crtc->dev;
2570 struct amdgpu_device *adev = dev->dev_private;
2571 struct amdgpu_atom_ss ss;
2572 int i;
2573
2574 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2575 if (crtc->primary->fb) {
2576 int r;
2577 struct amdgpu_framebuffer *amdgpu_fb;
765e7fbf 2578 struct amdgpu_bo *abo;
a2e73f56
AD		 2579
2580 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
765e7fbf
CK		 2581 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2582 r = amdgpu_bo_reserve(abo, false);
a2e73f56 2583 if (unlikely(r))
765e7fbf 2584 DRM_ERROR("failed to reserve abo before unpin\n");
a2e73f56 2585 else {
765e7fbf
CK		 2586 amdgpu_bo_unpin(abo);
2587 amdgpu_bo_unreserve(abo);
a2e73f56
AD		 2588 }
2589 }
2590 /* disable the GRPH */
2591 dce_v8_0_grph_enable(crtc, false);
2592
2593 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2594
2595 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2596 if (adev->mode_info.crtcs[i] &&
2597 adev->mode_info.crtcs[i]->enabled &&
2598 i != amdgpu_crtc->crtc_id &&
2599 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2600 /* one other crtc is using this pll don't turn
2601 * off the pll
2602 */
2603 goto done;
2604 }
2605 }
2606
2607 switch (amdgpu_crtc->pll_id) {
2608 case ATOM_PPLL1:
2609 case ATOM_PPLL2:
2610 /* disable the ppll */
2611 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
75cd45a4 2612 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
a2e73f56
AD		 2613 break;
2614 case ATOM_PPLL0:
2615 /* disable the ppll */
2616 if ((adev->asic_type == CHIP_KAVERI) ||
2617 (adev->asic_type == CHIP_BONAIRE) ||
2618 (adev->asic_type == CHIP_HAWAII))
2619 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2620 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2621 break;
2622 default:
2623 break;
2624 }
2625done:
2626 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2627 amdgpu_crtc->adjusted_clock = 0;
2628 amdgpu_crtc->encoder = NULL;
2629 amdgpu_crtc->connector = NULL;
2630}
2631
2632static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2633 struct drm_display_mode *mode,
2634 struct drm_display_mode *adjusted_mode,
2635 int x, int y, struct drm_framebuffer *old_fb)
2636{
2637 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2638
2639 if (!amdgpu_crtc->adjusted_clock)
2640 return -EINVAL;
2641
2642 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2643 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2644 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2645 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2646 amdgpu_atombios_crtc_scaler_setup(crtc);
fd70cf63 2647 dce_v8_0_cursor_reset(crtc);
a2e73f56
AD		 2648 /* update the hw version fpr dpm */
2649 amdgpu_crtc->hw_mode = *adjusted_mode;
2650
2651 return 0;
2652}
2653
2654static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2655 const struct drm_display_mode *mode,
2656 struct drm_display_mode *adjusted_mode)
2657{
2658 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2659 struct drm_device *dev = crtc->dev;
2660 struct drm_encoder *encoder;
2661
2662 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2663 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2664 if (encoder->crtc == crtc) {
2665 amdgpu_crtc->encoder = encoder;
2666 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2667 break;
2668 }
2669 }
2670 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2671 amdgpu_crtc->encoder = NULL;
2672 amdgpu_crtc->connector = NULL;
2673 return false;
2674 }
2675 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2676 return false;
2677 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2678 return false;
2679 /* pick pll */
2680 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2681 /* if we can't get a PPLL for a non-DP encoder, fail */
2682 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2683 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2684 return false;
2685
2686 return true;
2687}
2688
2689static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2690 struct drm_framebuffer *old_fb)
2691{
2692 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2693}
2694
2695static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2696 struct drm_framebuffer *fb,
2697 int x, int y, enum mode_set_atomic state)
2698{
2699 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2700}
2701
2702static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2703 .dpms = dce_v8_0_crtc_dpms,
2704 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2705 .mode_set = dce_v8_0_crtc_mode_set,
2706 .mode_set_base = dce_v8_0_crtc_set_base,
2707 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2708 .prepare = dce_v8_0_crtc_prepare,
2709 .commit = dce_v8_0_crtc_commit,
2710 .load_lut = dce_v8_0_crtc_load_lut,
2711 .disable = dce_v8_0_crtc_disable,
2712};
2713
2714static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2715{
2716 struct amdgpu_crtc *amdgpu_crtc;
2717 int i;
2718
2719 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2720 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2721 if (amdgpu_crtc == NULL)
2722 return -ENOMEM;
2723
2724 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2725
2726 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2727 amdgpu_crtc->crtc_id = index;
a2e73f56
AD		 2728 adev->mode_info.crtcs[index] = amdgpu_crtc;
2729
2730 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2731 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2732 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2733 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2734
2735 for (i = 0; i < 256; i++) {
2736 amdgpu_crtc->lut_r[i] = i << 2;
2737 amdgpu_crtc->lut_g[i] = i << 2;
2738 amdgpu_crtc->lut_b[i] = i << 2;
2739 }
2740
2741 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2742
2743 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2744 amdgpu_crtc->adjusted_clock = 0;
2745 amdgpu_crtc->encoder = NULL;
2746 amdgpu_crtc->connector = NULL;
2747 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2748
2749 return 0;
2750}
2751
5fc3aeeb 2752static int dce_v8_0_early_init(void *handle)
a2e73f56 2753{
5fc3aeeb 2754 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2755
a2e73f56
AD		 2756 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2757 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2758
2759 dce_v8_0_set_display_funcs(adev);
2760 dce_v8_0_set_irq_funcs(adev);
2761
83c9b025
ED		 2762 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2763
a2e73f56
AD		 2764 switch (adev->asic_type) {
2765 case CHIP_BONAIRE:
2766 case CHIP_HAWAII:
a2e73f56
AD		 2767 adev->mode_info.num_hpd = 6;
2768 adev->mode_info.num_dig = 6;
2769 break;
2770 case CHIP_KAVERI:
a2e73f56
AD		 2771 adev->mode_info.num_hpd = 6;
2772 adev->mode_info.num_dig = 7;
2773 break;
2774 case CHIP_KABINI:
2775 case CHIP_MULLINS:
a2e73f56
AD		 2776 adev->mode_info.num_hpd = 6;
2777 adev->mode_info.num_dig = 6; /* ? */
2778 break;
2779 default:
2780 /* FIXME: not supported yet */
2781 return -EINVAL;
2782 }
2783
2784 return 0;
2785}
2786
5fc3aeeb 2787static int dce_v8_0_sw_init(void *handle)
a2e73f56
AD		 2788{
2789 int r, i;
5fc3aeeb 2790 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2791
2792 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2793 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2794 if (r)
2795 return r;
2796 }
2797
2798 for (i = 8; i < 20; i += 2) {
2799 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2800 if (r)
2801 return r;
2802 }
2803
2804 /* HPD hotplug */
2805 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2806 if (r)
2807 return r;
2808
a2e73f56
AD		 2809 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2810
cb9e59d7
AD		 2811 adev->ddev->mode_config.async_page_flip = true;
2812
a2e73f56
AD		 2813 adev->ddev->mode_config.max_width = 16384;
2814 adev->ddev->mode_config.max_height = 16384;
2815
2816 adev->ddev->mode_config.preferred_depth = 24;
2817 adev->ddev->mode_config.prefer_shadow = 1;
2818
2819 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2820
2821 r = amdgpu_modeset_create_props(adev);
2822 if (r)
2823 return r;
2824
2825 adev->ddev->mode_config.max_width = 16384;
2826 adev->ddev->mode_config.max_height = 16384;
2827
2828 /* allocate crtcs */
2829 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2830 r = dce_v8_0_crtc_init(adev, i);
2831 if (r)
2832 return r;
2833 }
2834
2835 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2836 amdgpu_print_display_setup(adev->ddev);
2837 else
2838 return -EINVAL;
2839
2840 /* setup afmt */
ff923479
TSD		 2841 r = dce_v8_0_afmt_init(adev);
2842 if (r)
2843 return r;
a2e73f56
AD		 2844
2845 r = dce_v8_0_audio_init(adev);
2846 if (r)
2847 return r;
2848
2849 drm_kms_helper_poll_init(adev->ddev);
2850
74c1e842
TSD		 2851 adev->mode_info.mode_config_initialized = true;
2852 return 0;
a2e73f56
AD		 2853}
2854
5fc3aeeb 2855static int dce_v8_0_sw_fini(void *handle)
a2e73f56 2856{
5fc3aeeb 2857 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2858
a2e73f56
AD		 2859 kfree(adev->mode_info.bios_hardcoded_edid);
2860
2861 drm_kms_helper_poll_fini(adev->ddev);
2862
2863 dce_v8_0_audio_fini(adev);
2864
2865 dce_v8_0_afmt_fini(adev);
2866
2867 drm_mode_config_cleanup(adev->ddev);
2868 adev->mode_info.mode_config_initialized = false;
2869
2870 return 0;
2871}
2872
5fc3aeeb 2873static int dce_v8_0_hw_init(void *handle)
a2e73f56
AD		 2874{
2875 int i;
5fc3aeeb 2876 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2877
2878 /* init dig PHYs, disp eng pll */
2879 amdgpu_atombios_encoder_init_dig(adev);
2880 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2881
2882 /* initialize hpd */
2883 dce_v8_0_hpd_init(adev);
2884
2885 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2886 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2887 }
2888
f6c7aba4
MD		 2889 dce_v8_0_pageflip_interrupt_init(adev);
2890
a2e73f56
AD		 2891 return 0;
2892}
2893
5fc3aeeb 2894static int dce_v8_0_hw_fini(void *handle)
a2e73f56
AD		 2895{
2896 int i;
5fc3aeeb 2897 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2898
2899 dce_v8_0_hpd_fini(adev);
2900
2901 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2902 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2903 }
2904
f6c7aba4
MD		 2905 dce_v8_0_pageflip_interrupt_fini(adev);
2906
a2e73f56
AD		 2907 return 0;
2908}
2909
5fc3aeeb 2910static int dce_v8_0_suspend(void *handle)
a2e73f56 2911{
5fc3aeeb 2912 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 2913
a2e73f56
AD		 2914 amdgpu_atombios_scratch_regs_save(adev);
2915
f9fff064 2916 return dce_v8_0_hw_fini(handle);
a2e73f56
AD		 2917}
2918
5fc3aeeb 2919static int dce_v8_0_resume(void *handle)
a2e73f56 2920{
5fc3aeeb 2921 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
f9fff064
AD		 2922 int ret;
2923
2924 ret = dce_v8_0_hw_init(handle);
a2e73f56
AD		 2925
2926 amdgpu_atombios_scratch_regs_restore(adev);
2927
a2e73f56
AD		 2928 /* turn on the BL */
2929 if (adev->mode_info.bl_encoder) {
2930 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2931 adev->mode_info.bl_encoder);
2932 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2933 bl_level);
2934 }
2935
f9fff064 2936 return ret;
a2e73f56
AD		 2937}
2938
5fc3aeeb 2939static bool dce_v8_0_is_idle(void *handle)
a2e73f56 2940{
a2e73f56
AD		 2941 return true;
2942}
2943
5fc3aeeb 2944static int dce_v8_0_wait_for_idle(void *handle)
a2e73f56 2945{
a2e73f56
AD		 2946 return 0;
2947}
2948
5fc3aeeb 2949static int dce_v8_0_soft_reset(void *handle)
a2e73f56
AD		 2950{
2951 u32 srbm_soft_reset = 0, tmp;
5fc3aeeb 2952 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2953
2954 if (dce_v8_0_is_display_hung(adev))
2955 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2956
2957 if (srbm_soft_reset) {
a2e73f56
AD		 2958 tmp = RREG32(mmSRBM_SOFT_RESET);
2959 tmp |= srbm_soft_reset;
2960 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2961 WREG32(mmSRBM_SOFT_RESET, tmp);
2962 tmp = RREG32(mmSRBM_SOFT_RESET);
2963
2964 udelay(50);
2965
2966 tmp &= ~srbm_soft_reset;
2967 WREG32(mmSRBM_SOFT_RESET, tmp);
2968 tmp = RREG32(mmSRBM_SOFT_RESET);
2969
2970 /* Wait a little for things to settle down */
2971 udelay(50);
a2e73f56
AD		 2972 }
2973 return 0;
2974}
2975
2976static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2977 int crtc,
2978 enum amdgpu_interrupt_state state)
2979{
2980 u32 reg_block, lb_interrupt_mask;
2981
2982 if (crtc >= adev->mode_info.num_crtc) {
2983 DRM_DEBUG("invalid crtc %d\n", crtc);
2984 return;
2985 }
2986
2987 switch (crtc) {
2988 case 0:
2989 reg_block = CRTC0_REGISTER_OFFSET;
2990 break;
2991 case 1:
2992 reg_block = CRTC1_REGISTER_OFFSET;
2993 break;
2994 case 2:
2995 reg_block = CRTC2_REGISTER_OFFSET;
2996 break;
2997 case 3:
2998 reg_block = CRTC3_REGISTER_OFFSET;
2999 break;
3000 case 4:
3001 reg_block = CRTC4_REGISTER_OFFSET;
3002 break;
3003 case 5:
3004 reg_block = CRTC5_REGISTER_OFFSET;
3005 break;
3006 default:
3007 DRM_DEBUG("invalid crtc %d\n", crtc);
3008 return;
3009 }
3010
3011 switch (state) {
3012 case AMDGPU_IRQ_STATE_DISABLE:
3013 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3014 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3015 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3016 break;
3017 case AMDGPU_IRQ_STATE_ENABLE:
3018 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3019 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3020 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3021 break;
3022 default:
3023 break;
3024 }
3025}
3026
3027static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3028 int crtc,
3029 enum amdgpu_interrupt_state state)
3030{
3031 u32 reg_block, lb_interrupt_mask;
3032
3033 if (crtc >= adev->mode_info.num_crtc) {
3034 DRM_DEBUG("invalid crtc %d\n", crtc);
3035 return;
3036 }
3037
3038 switch (crtc) {
3039 case 0:
3040 reg_block = CRTC0_REGISTER_OFFSET;
3041 break;
3042 case 1:
3043 reg_block = CRTC1_REGISTER_OFFSET;
3044 break;
3045 case 2:
3046 reg_block = CRTC2_REGISTER_OFFSET;
3047 break;
3048 case 3:
3049 reg_block = CRTC3_REGISTER_OFFSET;
3050 break;
3051 case 4:
3052 reg_block = CRTC4_REGISTER_OFFSET;
3053 break;
3054 case 5:
3055 reg_block = CRTC5_REGISTER_OFFSET;
3056 break;
3057 default:
3058 DRM_DEBUG("invalid crtc %d\n", crtc);
3059 return;
3060 }
3061
3062 switch (state) {
3063 case AMDGPU_IRQ_STATE_DISABLE:
3064 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3065 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3066 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3067 break;
3068 case AMDGPU_IRQ_STATE_ENABLE:
3069 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3070 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3071 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3072 break;
3073 default:
3074 break;
3075 }
3076}
3077
3078static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3079 struct amdgpu_irq_src *src,
3080 unsigned type,
3081 enum amdgpu_interrupt_state state)
3082{
2285b91c 3083 u32 dc_hpd_int_cntl;
a2e73f56 3084
2285b91c 3085 if (type >= adev->mode_info.num_hpd) {
a2e73f56
AD		 3086 DRM_DEBUG("invalid hdp %d\n", type);
3087 return 0;
3088 }
3089
3090 switch (state) {
3091 case AMDGPU_IRQ_STATE_DISABLE:
2285b91c 3092 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
a2e73f56 3093 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2285b91c 3094 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
a2e73f56
AD		 3095 break;
3096 case AMDGPU_IRQ_STATE_ENABLE:
2285b91c 3097 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
a2e73f56 3098 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
2285b91c 3099 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
a2e73f56
AD		 3100 break;
3101 default:
3102 break;
3103 }
3104
3105 return 0;
3106}
3107
3108static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3109 struct amdgpu_irq_src *src,
3110 unsigned type,
3111 enum amdgpu_interrupt_state state)
3112{
3113 switch (type) {
3114 case AMDGPU_CRTC_IRQ_VBLANK1:
3115 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3116 break;
3117 case AMDGPU_CRTC_IRQ_VBLANK2:
3118 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3119 break;
3120 case AMDGPU_CRTC_IRQ_VBLANK3:
3121 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3122 break;
3123 case AMDGPU_CRTC_IRQ_VBLANK4:
3124 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3125 break;
3126 case AMDGPU_CRTC_IRQ_VBLANK5:
3127 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3128 break;
3129 case AMDGPU_CRTC_IRQ_VBLANK6:
3130 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3131 break;
3132 case AMDGPU_CRTC_IRQ_VLINE1:
3133 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3134 break;
3135 case AMDGPU_CRTC_IRQ_VLINE2:
3136 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3137 break;
3138 case AMDGPU_CRTC_IRQ_VLINE3:
3139 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3140 break;
3141 case AMDGPU_CRTC_IRQ_VLINE4:
3142 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3143 break;
3144 case AMDGPU_CRTC_IRQ_VLINE5:
3145 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3146 break;
3147 case AMDGPU_CRTC_IRQ_VLINE6:
3148 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3149 break;
3150 default:
3151 break;
3152 }
3153 return 0;
3154}
3155
3156static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3157 struct amdgpu_irq_src *source,
3158 struct amdgpu_iv_entry *entry)
3159{
3160 unsigned crtc = entry->src_id - 1;
3161 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3162 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3163
3164 switch (entry->src_data) {
3165 case 0: /* vblank */
bd833144 3166 if (disp_int & interrupt_status_offsets[crtc].vblank)
a2e73f56 3167 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
bd833144
MK		 3168 else
3169 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3170
3171 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3172 drm_handle_vblank(adev->ddev, crtc);
a2e73f56 3173 }
bd833144 3174 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
a2e73f56
AD		 3175 break;
3176 case 1: /* vline */
bd833144 3177 if (disp_int & interrupt_status_offsets[crtc].vline)
a2e73f56 3178 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
bd833144
MK		 3179 else
3180 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3181
3182 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
a2e73f56
AD		 3183 break;
3184 default:
3185 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3186 break;
3187 }
3188
3189 return 0;
3190}
3191
3192static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3193 struct amdgpu_irq_src *src,
3194 unsigned type,
3195 enum amdgpu_interrupt_state state)
3196{
7dfac896
AD		 3197 u32 reg;
3198
3199 if (type >= adev->mode_info.num_crtc) {
3200 DRM_ERROR("invalid pageflip crtc %d\n", type);
3201 return -EINVAL;
a2e73f56
AD		 3202 }
3203
7dfac896 3204 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
a2e73f56 3205 if (state == AMDGPU_IRQ_STATE_DISABLE)
7dfac896
AD		 3206 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3207 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
a2e73f56 3208 else
7dfac896
AD		 3209 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3210 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
a2e73f56
AD		 3211
3212 return 0;
3213}
3214
3215static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3216 struct amdgpu_irq_src *source,
3217 struct amdgpu_iv_entry *entry)
3218{
a2e73f56
AD		 3219 unsigned long flags;
3220 unsigned crtc_id;
3221 struct amdgpu_crtc *amdgpu_crtc;
3222 struct amdgpu_flip_work *works;
3223
3224 crtc_id = (entry->src_id - 8) >> 1;
3225 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3226
7dfac896
AD		 3227 if (crtc_id >= adev->mode_info.num_crtc) {
3228 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3229 return -EINVAL;
a2e73f56
AD		 3230 }
3231
7dfac896
AD		 3232 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3233 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3234 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3235 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
a2e73f56
AD		 3236
3237 /* IRQ could occur when in initial stage */
3238 if (amdgpu_crtc == NULL)
3239 return 0;
3240
3241 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3242 works = amdgpu_crtc->pflip_works;
3243 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3244 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3245 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3246 amdgpu_crtc->pflip_status,
3247 AMDGPU_FLIP_SUBMITTED);
3248 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3249 return 0;
3250 }
3251
3252 /* page flip completed. clean up */
3253 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3254 amdgpu_crtc->pflip_works = NULL;
3255
3256 /* wakeup usersapce */
3257 if (works->event)
56286769 3258 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
a2e73f56
AD		 3259
3260 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3261
60629c4d 3262 drm_crtc_vblank_put(&amdgpu_crtc->base);
87d58c11 3263 schedule_work(&works->unpin_work);
a2e73f56
AD		 3264
3265 return 0;
3266}
3267
3268static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3269 struct amdgpu_irq_src *source,
3270 struct amdgpu_iv_entry *entry)
3271{
2285b91c 3272 uint32_t disp_int, mask, tmp;
a2e73f56
AD		 3273 unsigned hpd;
3274
e922cfb1 3275 if (entry->src_data >= adev->mode_info.num_hpd) {
a2e73f56
AD		 3276 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3277 return 0;
3278 }
3279
3280 hpd = entry->src_data;
3281 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3282 mask = interrupt_status_offsets[hpd].hpd;
a2e73f56
AD		 3283
3284 if (disp_int & mask) {
2285b91c 3285 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
a2e73f56 3286 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
2285b91c 3287 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
a2e73f56
AD		 3288 schedule_work(&adev->hotplug_work);
3289 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3290 }
3291
3292 return 0;
3293
3294}
3295
5fc3aeeb 3296static int dce_v8_0_set_clockgating_state(void *handle,
3297 enum amd_clockgating_state state)
a2e73f56
AD		 3298{
3299 return 0;
3300}
3301
5fc3aeeb 3302static int dce_v8_0_set_powergating_state(void *handle,
3303 enum amd_powergating_state state)
a2e73f56
AD		 3304{
3305 return 0;
3306}
3307
5fc3aeeb 3308const struct amd_ip_funcs dce_v8_0_ip_funcs = {
88a907d6 3309 .name = "dce_v8_0",
a2e73f56
AD		 3310 .early_init = dce_v8_0_early_init,
3311 .late_init = NULL,
3312 .sw_init = dce_v8_0_sw_init,
3313 .sw_fini = dce_v8_0_sw_fini,
3314 .hw_init = dce_v8_0_hw_init,
3315 .hw_fini = dce_v8_0_hw_fini,
3316 .suspend = dce_v8_0_suspend,
3317 .resume = dce_v8_0_resume,
3318 .is_idle = dce_v8_0_is_idle,
3319 .wait_for_idle = dce_v8_0_wait_for_idle,
3320 .soft_reset = dce_v8_0_soft_reset,
a2e73f56
AD		 3321 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3322 .set_powergating_state = dce_v8_0_set_powergating_state,
3323};
3324
3325static void
3326dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3327 struct drm_display_mode *mode,
3328 struct drm_display_mode *adjusted_mode)
3329{
3330 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3331
3332 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3333
3334 /* need to call this here rather than in prepare() since we need some crtc info */
3335 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3336
3337 /* set scaler clears this on some chips */
3338 dce_v8_0_set_interleave(encoder->crtc, mode);
3339
3340 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3341 dce_v8_0_afmt_enable(encoder, true);
3342 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3343 }
3344}
3345
3346static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3347{
3348 struct amdgpu_device *adev = encoder->dev->dev_private;
3349 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3350 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3351
3352 if ((amdgpu_encoder->active_device &
3353 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3354 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3355 ENCODER_OBJECT_ID_NONE)) {
3356 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3357 if (dig) {
3358 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3359 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3360 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3361 }
3362 }
3363
3364 amdgpu_atombios_scratch_regs_lock(adev, true);
3365
3366 if (connector) {
3367 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3368
3369 /* select the clock/data port if it uses a router */
3370 if (amdgpu_connector->router.cd_valid)
3371 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3372
3373 /* turn eDP panel on for mode set */
3374 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3375 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3376 ATOM_TRANSMITTER_ACTION_POWER_ON);
3377 }
3378
3379 /* this is needed for the pll/ss setup to work correctly in some cases */
3380 amdgpu_atombios_encoder_set_crtc_source(encoder);
3381 /* set up the FMT blocks */
3382 dce_v8_0_program_fmt(encoder);
3383}
3384
3385static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3386{
3387 struct drm_device *dev = encoder->dev;
3388 struct amdgpu_device *adev = dev->dev_private;
3389
3390 /* need to call this here as we need the crtc set up */
3391 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3392 amdgpu_atombios_scratch_regs_lock(adev, false);
3393}
3394
3395static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3396{
3397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3398 struct amdgpu_encoder_atom_dig *dig;
3399
3400 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3401
3402 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3403 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3404 dce_v8_0_afmt_enable(encoder, false);
3405 dig = amdgpu_encoder->enc_priv;
3406 dig->dig_encoder = -1;
3407 }
3408 amdgpu_encoder->active_device = 0;
3409}
3410
3411/* these are handled by the primary encoders */
3412static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3413{
3414
3415}
3416
3417static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3418{
3419
3420}
3421
3422static void
3423dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3424 struct drm_display_mode *mode,
3425 struct drm_display_mode *adjusted_mode)
3426{
3427
3428}
3429
3430static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3431{
3432
3433}
3434
3435static void
3436dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3437{
3438
3439}
3440
a2e73f56
AD		 3441static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3442 .dpms = dce_v8_0_ext_dpms,
a2e73f56
AD		 3443 .prepare = dce_v8_0_ext_prepare,
3444 .mode_set = dce_v8_0_ext_mode_set,
3445 .commit = dce_v8_0_ext_commit,
3446 .disable = dce_v8_0_ext_disable,
3447 /* no detect for TMDS/LVDS yet */
3448};
3449
3450static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3451 .dpms = amdgpu_atombios_encoder_dpms,
3452 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3453 .prepare = dce_v8_0_encoder_prepare,
3454 .mode_set = dce_v8_0_encoder_mode_set,
3455 .commit = dce_v8_0_encoder_commit,
3456 .disable = dce_v8_0_encoder_disable,
3457 .detect = amdgpu_atombios_encoder_dig_detect,
3458};
3459
3460static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3461 .dpms = amdgpu_atombios_encoder_dpms,
3462 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3463 .prepare = dce_v8_0_encoder_prepare,
3464 .mode_set = dce_v8_0_encoder_mode_set,
3465 .commit = dce_v8_0_encoder_commit,
3466 .detect = amdgpu_atombios_encoder_dac_detect,
3467};
3468
3469static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3470{
3471 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3472 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3473 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3474 kfree(amdgpu_encoder->enc_priv);
3475 drm_encoder_cleanup(encoder);
3476 kfree(amdgpu_encoder);
3477}
3478
3479static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3480 .destroy = dce_v8_0_encoder_destroy,
3481};
3482
3483static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3484 uint32_t encoder_enum,
3485 uint32_t supported_device,
3486 u16 caps)
3487{
3488 struct drm_device *dev = adev->ddev;
3489 struct drm_encoder *encoder;
3490 struct amdgpu_encoder *amdgpu_encoder;
3491
3492 /* see if we already added it */
3493 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3494 amdgpu_encoder = to_amdgpu_encoder(encoder);
3495 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3496 amdgpu_encoder->devices |= supported_device;
3497 return;
3498 }
3499
3500 }
3501
3502 /* add a new one */
3503 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3504 if (!amdgpu_encoder)
3505 return;
3506
3507 encoder = &amdgpu_encoder->base;
3508 switch (adev->mode_info.num_crtc) {
3509 case 1:
3510 encoder->possible_crtcs = 0x1;
3511 break;
3512 case 2:
3513 default:
3514 encoder->possible_crtcs = 0x3;
3515 break;
3516 case 4:
3517 encoder->possible_crtcs = 0xf;
3518 break;
3519 case 6:
3520 encoder->possible_crtcs = 0x3f;
3521 break;
3522 }
3523
3524 amdgpu_encoder->enc_priv = NULL;
3525
3526 amdgpu_encoder->encoder_enum = encoder_enum;
3527 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3528 amdgpu_encoder->devices = supported_device;
3529 amdgpu_encoder->rmx_type = RMX_OFF;
3530 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3531 amdgpu_encoder->is_ext_encoder = false;
3532 amdgpu_encoder->caps = caps;
3533
3534 switch (amdgpu_encoder->encoder_id) {
3535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3536 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3537 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3538 DRM_MODE_ENCODER_DAC, NULL);
a2e73f56
AD		 3539 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3540 break;
3541 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3542 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3543 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3544 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3545 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3546 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3547 amdgpu_encoder->rmx_type = RMX_FULL;
3548 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3549 DRM_MODE_ENCODER_LVDS, NULL);
a2e73f56
AD		 3550 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3551 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3552 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3553 DRM_MODE_ENCODER_DAC, NULL);
a2e73f56
AD		 3554 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3555 } else {
3556 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3557 DRM_MODE_ENCODER_TMDS, NULL);
a2e73f56
AD		 3558 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3559 }
3560 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3561 break;
3562 case ENCODER_OBJECT_ID_SI170B:
3563 case ENCODER_OBJECT_ID_CH7303:
3564 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3565 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3566 case ENCODER_OBJECT_ID_TITFP513:
3567 case ENCODER_OBJECT_ID_VT1623:
3568 case ENCODER_OBJECT_ID_HDMI_SI1930:
3569 case ENCODER_OBJECT_ID_TRAVIS:
3570 case ENCODER_OBJECT_ID_NUTMEG:
3571 /* these are handled by the primary encoders */
3572 amdgpu_encoder->is_ext_encoder = true;
3573 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3574 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3575 DRM_MODE_ENCODER_LVDS, NULL);
a2e73f56
AD		 3576 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3577 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3578 DRM_MODE_ENCODER_DAC, NULL);
a2e73f56
AD		 3579 else
3580 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
13a3d91f 3581 DRM_MODE_ENCODER_TMDS, NULL);
a2e73f56
AD		 3582 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3583 break;
3584 }
3585}
3586
3587static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3588 .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3589 .bandwidth_update = &dce_v8_0_bandwidth_update,
3590 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3591 .vblank_wait = &dce_v8_0_vblank_wait,
3592 .is_display_hung = &dce_v8_0_is_display_hung,
3593 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3594 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3595 .hpd_sense = &dce_v8_0_hpd_sense,
3596 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3597 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3598 .page_flip = &dce_v8_0_page_flip,
3599 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3600 .add_encoder = &dce_v8_0_encoder_add,
3601 .add_connector = &amdgpu_connector_add,
3602 .stop_mc_access = &dce_v8_0_stop_mc_access,
3603 .resume_mc_access = &dce_v8_0_resume_mc_access,
3604};
3605
3606static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3607{
3608 if (adev->mode_info.funcs == NULL)
3609 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3610}
3611
3612static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3613 .set = dce_v8_0_set_crtc_interrupt_state,
3614 .process = dce_v8_0_crtc_irq,
3615};
3616
3617static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3618 .set = dce_v8_0_set_pageflip_interrupt_state,
3619 .process = dce_v8_0_pageflip_irq,
3620};
3621
3622static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3623 .set = dce_v8_0_set_hpd_interrupt_state,
3624 .process = dce_v8_0_hpd_irq,
3625};
3626
3627static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3628{
3629 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3630 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3631
3632 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3633 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3634
3635 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3636 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3637}
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