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drm/amdgpu/si: fix ring size for compute
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v6_0.c
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2cd46ad2
KW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h"
28#include "si/clearstate_si.h"
29#include "si/sid.h"
30
31#define GFX6_NUM_GFX_RINGS 1
32#define GFX6_NUM_COMPUTE_RINGS 2
33#define STATIC_PER_CU_PG_ENABLE (1 << 3)
34#define DYN_PER_CU_PG_ENABLE (1 << 2)
35#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
36#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
37
38
39static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
40static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
41static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
42
43MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
44MODULE_FIRMWARE("radeon/tahiti_me.bin");
45MODULE_FIRMWARE("radeon/tahiti_ce.bin");
46MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
47
48MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
49MODULE_FIRMWARE("radeon/pitcairn_me.bin");
50MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
51MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
52
53MODULE_FIRMWARE("radeon/verde_pfp.bin");
54MODULE_FIRMWARE("radeon/verde_me.bin");
55MODULE_FIRMWARE("radeon/verde_ce.bin");
56MODULE_FIRMWARE("radeon/verde_rlc.bin");
57
58MODULE_FIRMWARE("radeon/oland_pfp.bin");
59MODULE_FIRMWARE("radeon/oland_me.bin");
60MODULE_FIRMWARE("radeon/oland_ce.bin");
61MODULE_FIRMWARE("radeon/oland_rlc.bin");
62
63MODULE_FIRMWARE("radeon/hainan_pfp.bin");
64MODULE_FIRMWARE("radeon/hainan_me.bin");
65MODULE_FIRMWARE("radeon/hainan_ce.bin");
66MODULE_FIRMWARE("radeon/hainan_rlc.bin");
67
68static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
69static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
70//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
71static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
72
73
74static const u32 verde_rlc_save_restore_register_list[] =
75{
76 (0x8000 << 16) | (0x98f4 >> 2),
77 0x00000000,
78 (0x8040 << 16) | (0x98f4 >> 2),
79 0x00000000,
80 (0x8000 << 16) | (0xe80 >> 2),
81 0x00000000,
82 (0x8040 << 16) | (0xe80 >> 2),
83 0x00000000,
84 (0x8000 << 16) | (0x89bc >> 2),
85 0x00000000,
86 (0x8040 << 16) | (0x89bc >> 2),
87 0x00000000,
88 (0x8000 << 16) | (0x8c1c >> 2),
89 0x00000000,
90 (0x8040 << 16) | (0x8c1c >> 2),
91 0x00000000,
92 (0x9c00 << 16) | (0x98f0 >> 2),
93 0x00000000,
94 (0x9c00 << 16) | (0xe7c >> 2),
95 0x00000000,
96 (0x8000 << 16) | (0x9148 >> 2),
97 0x00000000,
98 (0x8040 << 16) | (0x9148 >> 2),
99 0x00000000,
100 (0x9c00 << 16) | (0x9150 >> 2),
101 0x00000000,
102 (0x9c00 << 16) | (0x897c >> 2),
103 0x00000000,
104 (0x9c00 << 16) | (0x8d8c >> 2),
105 0x00000000,
106 (0x9c00 << 16) | (0xac54 >> 2),
107 0X00000000,
108 0x3,
109 (0x9c00 << 16) | (0x98f8 >> 2),
110 0x00000000,
111 (0x9c00 << 16) | (0x9910 >> 2),
112 0x00000000,
113 (0x9c00 << 16) | (0x9914 >> 2),
114 0x00000000,
115 (0x9c00 << 16) | (0x9918 >> 2),
116 0x00000000,
117 (0x9c00 << 16) | (0x991c >> 2),
118 0x00000000,
119 (0x9c00 << 16) | (0x9920 >> 2),
120 0x00000000,
121 (0x9c00 << 16) | (0x9924 >> 2),
122 0x00000000,
123 (0x9c00 << 16) | (0x9928 >> 2),
124 0x00000000,
125 (0x9c00 << 16) | (0x992c >> 2),
126 0x00000000,
127 (0x9c00 << 16) | (0x9930 >> 2),
128 0x00000000,
129 (0x9c00 << 16) | (0x9934 >> 2),
130 0x00000000,
131 (0x9c00 << 16) | (0x9938 >> 2),
132 0x00000000,
133 (0x9c00 << 16) | (0x993c >> 2),
134 0x00000000,
135 (0x9c00 << 16) | (0x9940 >> 2),
136 0x00000000,
137 (0x9c00 << 16) | (0x9944 >> 2),
138 0x00000000,
139 (0x9c00 << 16) | (0x9948 >> 2),
140 0x00000000,
141 (0x9c00 << 16) | (0x994c >> 2),
142 0x00000000,
143 (0x9c00 << 16) | (0x9950 >> 2),
144 0x00000000,
145 (0x9c00 << 16) | (0x9954 >> 2),
146 0x00000000,
147 (0x9c00 << 16) | (0x9958 >> 2),
148 0x00000000,
149 (0x9c00 << 16) | (0x995c >> 2),
150 0x00000000,
151 (0x9c00 << 16) | (0x9960 >> 2),
152 0x00000000,
153 (0x9c00 << 16) | (0x9964 >> 2),
154 0x00000000,
155 (0x9c00 << 16) | (0x9968 >> 2),
156 0x00000000,
157 (0x9c00 << 16) | (0x996c >> 2),
158 0x00000000,
159 (0x9c00 << 16) | (0x9970 >> 2),
160 0x00000000,
161 (0x9c00 << 16) | (0x9974 >> 2),
162 0x00000000,
163 (0x9c00 << 16) | (0x9978 >> 2),
164 0x00000000,
165 (0x9c00 << 16) | (0x997c >> 2),
166 0x00000000,
167 (0x9c00 << 16) | (0x9980 >> 2),
168 0x00000000,
169 (0x9c00 << 16) | (0x9984 >> 2),
170 0x00000000,
171 (0x9c00 << 16) | (0x9988 >> 2),
172 0x00000000,
173 (0x9c00 << 16) | (0x998c >> 2),
174 0x00000000,
175 (0x9c00 << 16) | (0x8c00 >> 2),
176 0x00000000,
177 (0x9c00 << 16) | (0x8c14 >> 2),
178 0x00000000,
179 (0x9c00 << 16) | (0x8c04 >> 2),
180 0x00000000,
181 (0x9c00 << 16) | (0x8c08 >> 2),
182 0x00000000,
183 (0x8000 << 16) | (0x9b7c >> 2),
184 0x00000000,
185 (0x8040 << 16) | (0x9b7c >> 2),
186 0x00000000,
187 (0x8000 << 16) | (0xe84 >> 2),
188 0x00000000,
189 (0x8040 << 16) | (0xe84 >> 2),
190 0x00000000,
191 (0x8000 << 16) | (0x89c0 >> 2),
192 0x00000000,
193 (0x8040 << 16) | (0x89c0 >> 2),
194 0x00000000,
195 (0x8000 << 16) | (0x914c >> 2),
196 0x00000000,
197 (0x8040 << 16) | (0x914c >> 2),
198 0x00000000,
199 (0x8000 << 16) | (0x8c20 >> 2),
200 0x00000000,
201 (0x8040 << 16) | (0x8c20 >> 2),
202 0x00000000,
203 (0x8000 << 16) | (0x9354 >> 2),
204 0x00000000,
205 (0x8040 << 16) | (0x9354 >> 2),
206 0x00000000,
207 (0x9c00 << 16) | (0x9060 >> 2),
208 0x00000000,
209 (0x9c00 << 16) | (0x9364 >> 2),
210 0x00000000,
211 (0x9c00 << 16) | (0x9100 >> 2),
212 0x00000000,
213 (0x9c00 << 16) | (0x913c >> 2),
214 0x00000000,
215 (0x8000 << 16) | (0x90e0 >> 2),
216 0x00000000,
217 (0x8000 << 16) | (0x90e4 >> 2),
218 0x00000000,
219 (0x8000 << 16) | (0x90e8 >> 2),
220 0x00000000,
221 (0x8040 << 16) | (0x90e0 >> 2),
222 0x00000000,
223 (0x8040 << 16) | (0x90e4 >> 2),
224 0x00000000,
225 (0x8040 << 16) | (0x90e8 >> 2),
226 0x00000000,
227 (0x9c00 << 16) | (0x8bcc >> 2),
228 0x00000000,
229 (0x9c00 << 16) | (0x8b24 >> 2),
230 0x00000000,
231 (0x9c00 << 16) | (0x88c4 >> 2),
232 0x00000000,
233 (0x9c00 << 16) | (0x8e50 >> 2),
234 0x00000000,
235 (0x9c00 << 16) | (0x8c0c >> 2),
236 0x00000000,
237 (0x9c00 << 16) | (0x8e58 >> 2),
238 0x00000000,
239 (0x9c00 << 16) | (0x8e5c >> 2),
240 0x00000000,
241 (0x9c00 << 16) | (0x9508 >> 2),
242 0x00000000,
243 (0x9c00 << 16) | (0x950c >> 2),
244 0x00000000,
245 (0x9c00 << 16) | (0x9494 >> 2),
246 0x00000000,
247 (0x9c00 << 16) | (0xac0c >> 2),
248 0x00000000,
249 (0x9c00 << 16) | (0xac10 >> 2),
250 0x00000000,
251 (0x9c00 << 16) | (0xac14 >> 2),
252 0x00000000,
253 (0x9c00 << 16) | (0xae00 >> 2),
254 0x00000000,
255 (0x9c00 << 16) | (0xac08 >> 2),
256 0x00000000,
257 (0x9c00 << 16) | (0x88d4 >> 2),
258 0x00000000,
259 (0x9c00 << 16) | (0x88c8 >> 2),
260 0x00000000,
261 (0x9c00 << 16) | (0x88cc >> 2),
262 0x00000000,
263 (0x9c00 << 16) | (0x89b0 >> 2),
264 0x00000000,
265 (0x9c00 << 16) | (0x8b10 >> 2),
266 0x00000000,
267 (0x9c00 << 16) | (0x8a14 >> 2),
268 0x00000000,
269 (0x9c00 << 16) | (0x9830 >> 2),
270 0x00000000,
271 (0x9c00 << 16) | (0x9834 >> 2),
272 0x00000000,
273 (0x9c00 << 16) | (0x9838 >> 2),
274 0x00000000,
275 (0x9c00 << 16) | (0x9a10 >> 2),
276 0x00000000,
277 (0x8000 << 16) | (0x9870 >> 2),
278 0x00000000,
279 (0x8000 << 16) | (0x9874 >> 2),
280 0x00000000,
281 (0x8001 << 16) | (0x9870 >> 2),
282 0x00000000,
283 (0x8001 << 16) | (0x9874 >> 2),
284 0x00000000,
285 (0x8040 << 16) | (0x9870 >> 2),
286 0x00000000,
287 (0x8040 << 16) | (0x9874 >> 2),
288 0x00000000,
289 (0x8041 << 16) | (0x9870 >> 2),
290 0x00000000,
291 (0x8041 << 16) | (0x9874 >> 2),
292 0x00000000,
293 0x00000000
294};
295
296static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
297{
298 const char *chip_name;
299 char fw_name[30];
300 int err;
301 const struct gfx_firmware_header_v1_0 *cp_hdr;
302 const struct rlc_firmware_header_v1_0 *rlc_hdr;
303
304 DRM_DEBUG("\n");
305
306 switch (adev->asic_type) {
307 case CHIP_TAHITI:
308 chip_name = "tahiti";
309 break;
310 case CHIP_PITCAIRN:
311 chip_name = "pitcairn";
312 break;
313 case CHIP_VERDE:
314 chip_name = "verde";
315 break;
316 case CHIP_OLAND:
317 chip_name = "oland";
318 break;
319 case CHIP_HAINAN:
320 chip_name = "hainan";
321 break;
322 default: BUG();
323 }
324
325 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
326 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
327 if (err)
328 goto out;
329 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
330 if (err)
331 goto out;
332 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
333 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
334 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
335
336 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
337 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
338 if (err)
339 goto out;
340 err = amdgpu_ucode_validate(adev->gfx.me_fw);
341 if (err)
342 goto out;
343 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
344 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
345 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
346
347 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
348 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
349 if (err)
350 goto out;
351 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
352 if (err)
353 goto out;
354 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
355 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
356 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
357
358 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
359 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
360 if (err)
361 goto out;
362 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
363 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
364 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
365 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
366
367out:
368 if (err) {
369 printk(KERN_ERR
370 "gfx6: Failed to load firmware \"%s\"\n",
371 fw_name);
372 release_firmware(adev->gfx.pfp_fw);
373 adev->gfx.pfp_fw = NULL;
374 release_firmware(adev->gfx.me_fw);
375 adev->gfx.me_fw = NULL;
376 release_firmware(adev->gfx.ce_fw);
377 adev->gfx.ce_fw = NULL;
378 release_firmware(adev->gfx.rlc_fw);
379 adev->gfx.rlc_fw = NULL;
380 }
381 return err;
382}
383
384static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
385{
386 const u32 num_tile_mode_states = 32;
387 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
388
389 switch (adev->gfx.config.mem_row_size_in_kb) {
390 case 1:
391 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
392 break;
393 case 2:
394 default:
395 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
396 break;
397 case 4:
398 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
399 break;
400 }
401
402 if (adev->asic_type == CHIP_VERDE ||
403 adev->asic_type == CHIP_OLAND ||
404 adev->asic_type == CHIP_HAINAN) {
405 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
406 switch (reg_offset) {
407 case 0:
408 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
409 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
410 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
411 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
412 NUM_BANKS(ADDR_SURF_16_BANK) |
413 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
414 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
415 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
416 break;
417 case 1:
418 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
419 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
420 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
421 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
422 NUM_BANKS(ADDR_SURF_16_BANK) |
423 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
424 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
425 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
426 break;
427 case 2:
428 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
429 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
430 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
431 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
432 NUM_BANKS(ADDR_SURF_16_BANK) |
433 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
435 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
436 break;
437 case 3:
438 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
439 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
440 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
441 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
442 NUM_BANKS(ADDR_SURF_16_BANK) |
443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
446 break;
447 case 4:
448 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
449 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
451 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
452 NUM_BANKS(ADDR_SURF_16_BANK) |
453 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
456 break;
457 case 5:
458 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
459 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
460 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
461 TILE_SPLIT(split_equal_to_row_size) |
462 NUM_BANKS(ADDR_SURF_16_BANK) |
463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
466 break;
467 case 6:
468 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
469 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
471 TILE_SPLIT(split_equal_to_row_size) |
472 NUM_BANKS(ADDR_SURF_16_BANK) |
473 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
476 break;
477 case 7:
478 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
479 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
480 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
481 TILE_SPLIT(split_equal_to_row_size) |
482 NUM_BANKS(ADDR_SURF_16_BANK) |
483 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
485 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
486 break;
487 case 8:
488 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
489 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
490 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
492 NUM_BANKS(ADDR_SURF_16_BANK) |
493 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
496 break;
497 case 9:
498 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
499 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
500 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
502 NUM_BANKS(ADDR_SURF_16_BANK) |
503 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
504 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
505 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
506 break;
507 case 10:
508 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
509 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
510 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
511 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
512 NUM_BANKS(ADDR_SURF_16_BANK) |
513 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
516 break;
517 case 11:
518 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
519 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
520 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
522 NUM_BANKS(ADDR_SURF_16_BANK) |
523 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
526 break;
527 case 12:
528 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
529 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
530 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
531 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
532 NUM_BANKS(ADDR_SURF_16_BANK) |
533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
536 break;
537 case 13:
538 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
539 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
540 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
541 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
542 NUM_BANKS(ADDR_SURF_16_BANK) |
543 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
544 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
545 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
546 break;
547 case 14:
548 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
549 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
550 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
551 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
552 NUM_BANKS(ADDR_SURF_16_BANK) |
553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
556 break;
557 case 15:
558 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
559 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
560 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
562 NUM_BANKS(ADDR_SURF_16_BANK) |
563 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
564 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
565 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
566 break;
567 case 16:
568 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
569 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
570 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
571 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
572 NUM_BANKS(ADDR_SURF_16_BANK) |
573 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
574 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
575 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
576 break;
577 case 17:
578 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
579 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
580 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
581 TILE_SPLIT(split_equal_to_row_size) |
582 NUM_BANKS(ADDR_SURF_16_BANK) |
583 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
586 break;
587 case 21:
588 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
589 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
590 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
591 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
592 NUM_BANKS(ADDR_SURF_16_BANK) |
593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
596 break;
597 case 22:
598 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
599 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
600 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
602 NUM_BANKS(ADDR_SURF_16_BANK) |
603 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
604 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
605 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
606 break;
607 case 23:
608 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
609 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
610 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
611 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
612 NUM_BANKS(ADDR_SURF_16_BANK) |
613 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
614 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
616 break;
617 case 24:
618 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
619 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
620 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
621 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
622 NUM_BANKS(ADDR_SURF_16_BANK) |
623 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
625 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
626 break;
627 case 25:
628 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
629 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
630 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
631 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
632 NUM_BANKS(ADDR_SURF_8_BANK) |
633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
636 break;
637 default:
638 gb_tile_moden = 0;
639 break;
640 }
641 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
642 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
643 }
644 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
646 switch (reg_offset) {
647 case 0: /* non-AA compressed depth or any compressed stencil */
648 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
649 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
650 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
652 NUM_BANKS(ADDR_SURF_16_BANK) |
653 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
654 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
655 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
656 break;
657 case 1: /* 2xAA/4xAA compressed depth only */
658 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
659 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
660 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
661 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
662 NUM_BANKS(ADDR_SURF_16_BANK) |
663 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
664 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
665 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
666 break;
667 case 2: /* 8xAA compressed depth only */
668 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
669 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
670 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
671 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
672 NUM_BANKS(ADDR_SURF_16_BANK) |
673 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
674 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
675 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
676 break;
677 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
678 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
679 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
680 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
681 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
682 NUM_BANKS(ADDR_SURF_16_BANK) |
683 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
684 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
685 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
686 break;
687 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
688 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
689 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
690 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
691 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
692 NUM_BANKS(ADDR_SURF_16_BANK) |
693 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
696 break;
697 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
698 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
699 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
700 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
701 TILE_SPLIT(split_equal_to_row_size) |
702 NUM_BANKS(ADDR_SURF_16_BANK) |
703 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
704 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
705 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
706 break;
707 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
708 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
709 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
710 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
711 TILE_SPLIT(split_equal_to_row_size) |
712 NUM_BANKS(ADDR_SURF_16_BANK) |
713 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
714 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
715 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
716 break;
717 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
718 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
719 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
720 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
721 TILE_SPLIT(split_equal_to_row_size) |
722 NUM_BANKS(ADDR_SURF_16_BANK) |
723 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
724 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
725 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
726 break;
727 case 8: /* 1D and 1D Array Surfaces */
728 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
729 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
730 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
731 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
732 NUM_BANKS(ADDR_SURF_16_BANK) |
733 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
734 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
735 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
736 break;
737 case 9: /* Displayable maps. */
738 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
739 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
740 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
741 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
742 NUM_BANKS(ADDR_SURF_16_BANK) |
743 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
744 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
745 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
746 break;
747 case 10: /* Display 8bpp. */
748 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
749 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
750 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
751 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
752 NUM_BANKS(ADDR_SURF_16_BANK) |
753 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
754 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
755 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
756 break;
757 case 11: /* Display 16bpp. */
758 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
759 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
760 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
761 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
762 NUM_BANKS(ADDR_SURF_16_BANK) |
763 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
764 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
765 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
766 break;
767 case 12: /* Display 32bpp. */
768 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
769 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
770 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
771 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
772 NUM_BANKS(ADDR_SURF_16_BANK) |
773 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
774 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
775 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
776 break;
777 case 13: /* Thin. */
778 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
779 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
780 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
781 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
782 NUM_BANKS(ADDR_SURF_16_BANK) |
783 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
784 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
785 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
786 break;
787 case 14: /* Thin 8 bpp. */
788 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
789 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
790 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
791 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
792 NUM_BANKS(ADDR_SURF_16_BANK) |
793 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
795 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
796 break;
797 case 15: /* Thin 16 bpp. */
798 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
799 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
800 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
801 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
802 NUM_BANKS(ADDR_SURF_16_BANK) |
803 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
804 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
805 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
806 break;
807 case 16: /* Thin 32 bpp. */
808 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
809 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
810 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
811 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
812 NUM_BANKS(ADDR_SURF_16_BANK) |
813 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
816 break;
817 case 17: /* Thin 64 bpp. */
818 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
819 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
820 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
821 TILE_SPLIT(split_equal_to_row_size) |
822 NUM_BANKS(ADDR_SURF_16_BANK) |
823 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
824 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
825 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
826 break;
827 case 21: /* 8 bpp PRT. */
828 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
829 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
830 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
831 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
832 NUM_BANKS(ADDR_SURF_16_BANK) |
833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
836 break;
837 case 22: /* 16 bpp PRT */
838 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
839 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
840 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
841 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
842 NUM_BANKS(ADDR_SURF_16_BANK) |
843 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
846 break;
847 case 23: /* 32 bpp PRT */
848 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
849 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
850 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
851 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
852 NUM_BANKS(ADDR_SURF_16_BANK) |
853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
856 break;
857 case 24: /* 64 bpp PRT */
858 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
859 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
860 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
861 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
862 NUM_BANKS(ADDR_SURF_16_BANK) |
863 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
864 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
865 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
866 break;
867 case 25: /* 128 bpp PRT */
868 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
869 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
870 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
871 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
872 NUM_BANKS(ADDR_SURF_8_BANK) |
873 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
876 break;
877 default:
878 gb_tile_moden = 0;
879 break;
880 }
881 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
882 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
883 }
884 } else{
885
886 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
887 }
888
889}
890
891static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
892 u32 sh_num, u32 instance)
893{
894 u32 data;
895
896 if (instance == 0xffffffff)
897 data = INSTANCE_BROADCAST_WRITES;
898 else
899 data = INSTANCE_INDEX(instance);
900
901 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
902 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
903 else if (se_num == 0xffffffff)
904 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
905 else if (sh_num == 0xffffffff)
906 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
907 else
908 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
909 WREG32(GRBM_GFX_INDEX, data);
910}
911
912static u32 gfx_v6_0_create_bitmask(u32 bit_width)
913{
142333db 914 return (u32)(((u64)1 << bit_width) - 1);
2cd46ad2
KW		 915}
916
917static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
918 u32 max_rb_num_per_se,
919 u32 sh_per_se)
920{
921 u32 data, mask;
922
923 data = RREG32(CC_RB_BACKEND_DISABLE);
924 data &= BACKEND_DISABLE_MASK;
925 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
926
927 data >>= BACKEND_DISABLE_SHIFT;
928
929 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se);
930
931 return data & mask;
932}
933
934static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
935 u32 se_num, u32 sh_per_se,
936 u32 max_rb_num_per_se)
937{
938 int i, j;
939 u32 data, mask;
940 u32 disabled_rbs = 0;
941 u32 enabled_rbs = 0;
942
deca1d1f 943 mutex_lock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 944 for (i = 0; i < se_num; i++) {
945 for (j = 0; j < sh_per_se; j++) {
946 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
947 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
948 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
949 }
950 }
951 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 952 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 953
954 mask = 1;
955 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
956 if (!(disabled_rbs & mask))
957 enabled_rbs |= mask;
958 mask <<= 1;
959 }
960
961 adev->gfx.config.backend_enable_mask = enabled_rbs;
962 adev->gfx.config.num_rbs = hweight32(enabled_rbs);
963
deca1d1f 964 mutex_lock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 965 for (i = 0; i < se_num; i++) {
966 gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
967 data = 0;
968 for (j = 0; j < sh_per_se; j++) {
969 switch (enabled_rbs & 3) {
970 case 1:
971 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
972 break;
973 case 2:
974 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
975 break;
976 case 3:
977 default:
978 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
979 break;
980 }
981 enabled_rbs >>= 2;
982 }
983 WREG32(PA_SC_RASTER_CONFIG, data);
984 }
985 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 986 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 987}
988/*
989static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
990{
991}
992*/
993
994static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh)
995{
996 u32 data, mask;
997
998 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
999 data &= INACTIVE_CUS_MASK;
1000 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1001
1002 data >>= INACTIVE_CUS_SHIFT;
1003
1004 mask = gfx_v6_0_create_bitmask(cu_per_sh);
1005
1006 return ~data & mask;
1007}
1008
1009
1010static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1011 u32 se_num, u32 sh_per_se,
1012 u32 cu_per_sh)
1013{
1014 int i, j, k;
1015 u32 data, mask;
1016 u32 active_cu = 0;
1017
deca1d1f 1018 mutex_lock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1019 for (i = 0; i < se_num; i++) {
1020 for (j = 0; j < sh_per_se; j++) {
1021 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1022 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1023 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh);
1024
1025 mask = 1;
1026 for (k = 0; k < 16; k++) {
1027 mask <<= k;
1028 if (active_cu & mask) {
1029 data &= ~mask;
1030 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1031 break;
1032 }
1033 }
1034 }
1035 }
1036 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 1037 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1038}
1039
1040static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1041{
1042 u32 gb_addr_config = 0;
1043 u32 mc_shared_chmap, mc_arb_ramcfg;
1044 u32 sx_debug_1;
1045 u32 hdp_host_path_cntl;
1046 u32 tmp;
1047
1048 switch (adev->asic_type) {
1049 case CHIP_TAHITI:
1050 adev->gfx.config.max_shader_engines = 2;
1051 adev->gfx.config.max_tile_pipes = 12;
1052 adev->gfx.config.max_cu_per_sh = 8;
1053 adev->gfx.config.max_sh_per_se = 2;
1054 adev->gfx.config.max_backends_per_se = 4;
1055 adev->gfx.config.max_texture_channel_caches = 12;
1056 adev->gfx.config.max_gprs = 256;
1057 adev->gfx.config.max_gs_threads = 32;
1058 adev->gfx.config.max_hw_contexts = 8;
1059
1060 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1061 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1062 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1063 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1064 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1065 break;
1066 case CHIP_PITCAIRN:
1067 adev->gfx.config.max_shader_engines = 2;
1068 adev->gfx.config.max_tile_pipes = 8;
1069 adev->gfx.config.max_cu_per_sh = 5;
1070 adev->gfx.config.max_sh_per_se = 2;
1071 adev->gfx.config.max_backends_per_se = 4;
1072 adev->gfx.config.max_texture_channel_caches = 8;
1073 adev->gfx.config.max_gprs = 256;
1074 adev->gfx.config.max_gs_threads = 32;
1075 adev->gfx.config.max_hw_contexts = 8;
1076
1077 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1078 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1079 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1080 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1081 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1082 break;
1083
1084 case CHIP_VERDE:
1085 adev->gfx.config.max_shader_engines = 1;
1086 adev->gfx.config.max_tile_pipes = 4;
1087 adev->gfx.config.max_cu_per_sh = 5;
1088 adev->gfx.config.max_sh_per_se = 2;
1089 adev->gfx.config.max_backends_per_se = 4;
1090 adev->gfx.config.max_texture_channel_caches = 4;
1091 adev->gfx.config.max_gprs = 256;
1092 adev->gfx.config.max_gs_threads = 32;
1093 adev->gfx.config.max_hw_contexts = 8;
1094
1095 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1096 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1097 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1098 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1099 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1100 break;
1101 case CHIP_OLAND:
1102 adev->gfx.config.max_shader_engines = 1;
1103 adev->gfx.config.max_tile_pipes = 4;
1104 adev->gfx.config.max_cu_per_sh = 6;
1105 adev->gfx.config.max_sh_per_se = 1;
1106 adev->gfx.config.max_backends_per_se = 2;
1107 adev->gfx.config.max_texture_channel_caches = 4;
1108 adev->gfx.config.max_gprs = 256;
1109 adev->gfx.config.max_gs_threads = 16;
1110 adev->gfx.config.max_hw_contexts = 8;
1111
1112 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1113 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1114 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1115 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1116 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1117 break;
1118 case CHIP_HAINAN:
1119 adev->gfx.config.max_shader_engines = 1;
1120 adev->gfx.config.max_tile_pipes = 4;
1121 adev->gfx.config.max_cu_per_sh = 5;
1122 adev->gfx.config.max_sh_per_se = 1;
1123 adev->gfx.config.max_backends_per_se = 1;
1124 adev->gfx.config.max_texture_channel_caches = 2;
1125 adev->gfx.config.max_gprs = 256;
1126 adev->gfx.config.max_gs_threads = 16;
1127 adev->gfx.config.max_hw_contexts = 8;
1128
1129 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1130 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1131 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1132 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1133 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1134 break;
1135 default:
1136 BUG();
1137 break;
1138 }
1139
1140 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1141 WREG32(SRBM_INT_CNTL, 1);
1142 WREG32(SRBM_INT_ACK, 1);
1143
1144 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1145
1146 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1147 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1148
1149 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1150 adev->gfx.config.mem_max_burst_length_bytes = 256;
1151 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1152 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1153 if (adev->gfx.config.mem_row_size_in_kb > 4)
1154 adev->gfx.config.mem_row_size_in_kb = 4;
1155 adev->gfx.config.shader_engine_tile_size = 32;
1156 adev->gfx.config.num_gpus = 1;
1157 adev->gfx.config.multi_gpu_tile_size = 64;
1158
1159 gb_addr_config &= ~ROW_SIZE_MASK;
1160 switch (adev->gfx.config.mem_row_size_in_kb) {
1161 case 1:
1162 default:
1163 gb_addr_config |= ROW_SIZE(0);
1164 break;
1165 case 2:
1166 gb_addr_config |= ROW_SIZE(1);
1167 break;
1168 case 4:
1169 gb_addr_config |= ROW_SIZE(2);
1170 break;
1171 }
1172 adev->gfx.config.gb_addr_config = gb_addr_config;
1173
1174 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1175 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1176 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1177 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1178 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1179 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1180#if 0
1181 if (adev->has_uvd) {
1182 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1183 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1184 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1185 }
1186#endif
1187 gfx_v6_0_tiling_mode_table_init(adev);
1188
1189 gfx_v6_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
1190 adev->gfx.config.max_sh_per_se,
1191 adev->gfx.config.max_backends_per_se);
1192
1193 gfx_v6_0_setup_spi(adev, adev->gfx.config.max_shader_engines,
1194 adev->gfx.config.max_sh_per_se,
1195 adev->gfx.config.max_cu_per_sh);
1196
1197 gfx_v6_0_get_cu_info(adev);
1198
1199 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1200 ROQ_IB2_START(0x2b)));
1201 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1202
1203 sx_debug_1 = RREG32(SX_DEBUG_1);
1204 WREG32(SX_DEBUG_1, sx_debug_1);
1205
1206 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1207
1208 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_frontend) |
1209 SC_BACKEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_backend) |
1210 SC_HIZ_TILE_FIFO_SIZE(adev->gfx.config.sc_hiz_tile_fifo_size) |
1211 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
1212
1213 WREG32(VGT_NUM_INSTANCES, 1);
2cd46ad2 1214 WREG32(CP_PERFMON_CNTL, 0);
2cd46ad2 1215 WREG32(SQ_CONFIG, 0);
2cd46ad2
KW		 1216 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1217 FORCE_EOV_MAX_REZ_CNT(255)));
1218
1219 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1220 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1221
1222 WREG32(VGT_GS_VERTEX_REUSE, 16);
1223 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1224
1225 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1226 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1227 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1228 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1229 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1230 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1231 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1232 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1233
1234 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1235 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1236
1237 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1238
1239 udelay(50);
2cd46ad2
KW		 1240}
1241
1242
1243static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1244{
1245 int i;
1246
1247 adev->gfx.scratch.num_reg = 7;
1248 adev->gfx.scratch.reg_base = SCRATCH_REG0;
1249 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1250 adev->gfx.scratch.free[i] = true;
1251 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1252 }
1253}
1254
1255static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1256{
1257 struct amdgpu_device *adev = ring->adev;
1258 uint32_t scratch;
1259 uint32_t tmp = 0;
1260 unsigned i;
1261 int r;
1262
1263 r = amdgpu_gfx_scratch_get(adev, &scratch);
1264 if (r) {
1265 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1266 return r;
1267 }
1268 WREG32(scratch, 0xCAFEDEAD);
1269
1270 r = amdgpu_ring_alloc(ring, 3);
1271 if (r) {
1272 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1273 amdgpu_gfx_scratch_free(adev, scratch);
1274 return r;
1275 }
1276 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1277 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1278 amdgpu_ring_write(ring, 0xDEADBEEF);
1279 amdgpu_ring_commit(ring);
1280
1281 for (i = 0; i < adev->usec_timeout; i++) {
1282 tmp = RREG32(scratch);
1283 if (tmp == 0xDEADBEEF)
1284 break;
1285 DRM_UDELAY(1);
1286 }
1287 if (i < adev->usec_timeout) {
1288 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1289 } else {
1290 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1291 ring->idx, scratch, tmp);
1292 r = -EINVAL;
1293 }
1294 amdgpu_gfx_scratch_free(adev, scratch);
1295 return r;
1296}
1297
1298static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1299{
1300 /* flush hdp cache */
1301 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1302 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1303 WRITE_DATA_DST_SEL(0)));
1304 amdgpu_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL);
1305 amdgpu_ring_write(ring, 0);
1306 amdgpu_ring_write(ring, 0x1);
1307}
1308
1309/**
1310 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1311 *
1312 * @adev: amdgpu_device pointer
1313 * @ridx: amdgpu ring index
1314 *
1315 * Emits an hdp invalidate on the cp.
1316 */
1317static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1318{
1319 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1320 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1321 WRITE_DATA_DST_SEL(0)));
1322 amdgpu_ring_write(ring, HDP_DEBUG0);
1323 amdgpu_ring_write(ring, 0);
1324 amdgpu_ring_write(ring, 0x1);
1325}
1326
1327static void gfx_v6_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
1328 u64 seq, unsigned flags)
1329{
1330 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1331 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1332 /* flush read cache over gart */
1333 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1334 amdgpu_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1335 amdgpu_ring_write(ring, 0);
1336 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1337 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1338 PACKET3_TC_ACTION_ENA |
1339 PACKET3_SH_KCACHE_ACTION_ENA |
1340 PACKET3_SH_ICACHE_ACTION_ENA);
1341 amdgpu_ring_write(ring, 0xFFFFFFFF);
1342 amdgpu_ring_write(ring, 0);
1343 amdgpu_ring_write(ring, 10); /* poll interval */
1344 /* EVENT_WRITE_EOP - flush caches, send int */
1345 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1346 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1347 amdgpu_ring_write(ring, addr & 0xfffffffc);
1348 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1349 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
1350 amdgpu_ring_write(ring, lower_32_bits(seq));
1351 amdgpu_ring_write(ring, upper_32_bits(seq));
1352}
1353
1354static void gfx_v6_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
1355 u64 addr, u64 seq,
1356 unsigned flags)
1357{
1358 gfx_v6_0_ring_emit_fence_gfx(ring, addr, seq, flags);
1359}
1360
1361
1362static void gfx_v6_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
1363 struct amdgpu_ib *ib,
1364 unsigned vm_id, bool ctx_switch)
1365{
1366 u32 header, control = 0;
1367
1368 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1369 if (ctx_switch) {
1370 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1371 amdgpu_ring_write(ring, 0);
1372 }
1373
1374 if (ib->flags & AMDGPU_IB_FLAG_CE)
1375 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1376 else
1377 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1378
1379 control |= ib->length_dw | (vm_id << 24);
1380
1381 amdgpu_ring_write(ring, header);
1382 amdgpu_ring_write(ring,
1383#ifdef __BIG_ENDIAN
1384 (2 << 0) |
1385#endif
1386 (ib->gpu_addr & 0xFFFFFFFC));
1387 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1388 amdgpu_ring_write(ring, control);
1389}
1390
1391static void gfx_v6_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
1392 struct amdgpu_ib *ib,
1393 unsigned vm_id, bool ctx_switch)
1394{
1395 gfx_v6_0_ring_emit_ib_gfx(ring, ib, vm_id, ctx_switch);
1396}
1397
1398/**
1399 * gfx_v6_0_ring_test_ib - basic ring IB test
1400 *
1401 * @ring: amdgpu_ring structure holding ring information
1402 *
1403 * Allocate an IB and execute it on the gfx ring (SI).
1404 * Provides a basic gfx ring test to verify that IBs are working.
1405 * Returns 0 on success, error on failure.
1406 */
1407static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1408{
1409 struct amdgpu_device *adev = ring->adev;
1410 struct amdgpu_ib ib;
1411 struct fence *f = NULL;
1412 uint32_t scratch;
1413 uint32_t tmp = 0;
1414 long r;
1415
1416 r = amdgpu_gfx_scratch_get(adev, &scratch);
1417 if (r) {
1418 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1419 return r;
1420 }
1421 WREG32(scratch, 0xCAFEDEAD);
1422 memset(&ib, 0, sizeof(ib));
1423 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1424 if (r) {
1425 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1426 goto err1;
1427 }
1428 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1429 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1430 ib.ptr[2] = 0xDEADBEEF;
1431 ib.length_dw = 3;
1432
1433 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
1434 if (r)
1435 goto err2;
1436
1437 r = fence_wait_timeout(f, false, timeout);
1438 if (r == 0) {
1439 DRM_ERROR("amdgpu: IB test timed out\n");
1440 r = -ETIMEDOUT;
1441 goto err2;
1442 } else if (r < 0) {
1443 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1444 goto err2;
1445 }
1446 tmp = RREG32(scratch);
1447 if (tmp == 0xDEADBEEF) {
1448 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1449 r = 0;
1450 } else {
1451 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1452 scratch, tmp);
1453 r = -EINVAL;
1454 }
1455
1456err2:
1457 amdgpu_ib_free(adev, &ib, NULL);
1458 fence_put(f);
1459err1:
1460 amdgpu_gfx_scratch_free(adev, scratch);
1461 return r;
1462}
1463
1464static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1465{
1466 int i;
1467 if (enable)
1468 WREG32(CP_ME_CNTL, 0);
1469 else {
1470 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1471 WREG32(SCRATCH_UMSK, 0);
1472 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1473 adev->gfx.gfx_ring[i].ready = false;
1474 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1475 adev->gfx.compute_ring[i].ready = false;
1476 }
1477 udelay(50);
1478}
1479
1480static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1481{
1482 unsigned i;
1483 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1484 const struct gfx_firmware_header_v1_0 *ce_hdr;
1485 const struct gfx_firmware_header_v1_0 *me_hdr;
1486 const __le32 *fw_data;
1487 u32 fw_size;
1488
1489 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1490 return -EINVAL;
1491
1492 gfx_v6_0_cp_gfx_enable(adev, false);
1493 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1494 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1495 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1496
1497 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1498 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1499 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1500
1501 /* PFP */
1502 fw_data = (const __le32 *)
1503 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1504 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1505 WREG32(CP_PFP_UCODE_ADDR, 0);
1506 for (i = 0; i < fw_size; i++)
1507 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1508 WREG32(CP_PFP_UCODE_ADDR, 0);
1509
1510 /* CE */
1511 fw_data = (const __le32 *)
1512 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1513 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1514 WREG32(CP_CE_UCODE_ADDR, 0);
1515 for (i = 0; i < fw_size; i++)
1516 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1517 WREG32(CP_CE_UCODE_ADDR, 0);
1518
1519 /* ME */
1520 fw_data = (const __be32 *)
1521 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1522 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1523 WREG32(CP_ME_RAM_WADDR, 0);
1524 for (i = 0; i < fw_size; i++)
1525 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1526 WREG32(CP_ME_RAM_WADDR, 0);
1527
1528
1529 WREG32(CP_PFP_UCODE_ADDR, 0);
1530 WREG32(CP_CE_UCODE_ADDR, 0);
1531 WREG32(CP_ME_RAM_WADDR, 0);
1532 WREG32(CP_ME_RAM_RADDR, 0);
1533 return 0;
1534}
1535
1536static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1537{
1538 const struct cs_section_def *sect = NULL;
1539 const struct cs_extent_def *ext = NULL;
1540 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1541 int r, i;
1542
1543 r = amdgpu_ring_alloc(ring, 7 + 4);
1544 if (r) {
1545 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1546 return r;
1547 }
1548 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1549 amdgpu_ring_write(ring, 0x1);
1550 amdgpu_ring_write(ring, 0x0);
1551 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
1552 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1553 amdgpu_ring_write(ring, 0);
1554 amdgpu_ring_write(ring, 0);
1555
1556 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1557 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1558 amdgpu_ring_write(ring, 0xc000);
1559 amdgpu_ring_write(ring, 0xe000);
1560 amdgpu_ring_commit(ring);
1561
1562 gfx_v6_0_cp_gfx_enable(adev, true);
1563
1564 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
1565 if (r) {
1566 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1567 return r;
1568 }
1569
1570 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1571 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1572
1573 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1574 for (ext = sect->section; ext->extent != NULL; ++ext) {
1575 if (sect->id == SECT_CONTEXT) {
1576 amdgpu_ring_write(ring,
1577 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1578 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1579 for (i = 0; i < ext->reg_count; i++)
1580 amdgpu_ring_write(ring, ext->extent[i]);
1581 }
1582 }
1583 }
1584
1585 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1586 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1587
1588 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1589 amdgpu_ring_write(ring, 0);
1590
1591 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1592 amdgpu_ring_write(ring, 0x00000316);
1593 amdgpu_ring_write(ring, 0x0000000e);
1594 amdgpu_ring_write(ring, 0x00000010);
1595
1596 amdgpu_ring_commit(ring);
1597
1598 return 0;
1599}
1600
1601static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1602{
1603 struct amdgpu_ring *ring;
1604 u32 tmp;
1605 u32 rb_bufsz;
1606 int r;
1607 u64 rptr_addr;
1608
1609 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1610 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1611
1612 /* Set the write pointer delay */
1613 WREG32(CP_RB_WPTR_DELAY, 0);
1614
1615 WREG32(CP_DEBUG, 0);
1616 WREG32(SCRATCH_ADDR, 0);
1617
1618 /* ring 0 - compute and gfx */
1619 /* Set ring buffer size */
1620 ring = &adev->gfx.gfx_ring[0];
1621 rb_bufsz = order_base_2(ring->ring_size / 8);
1622 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1623
1624#ifdef __BIG_ENDIAN
1625 tmp |= BUF_SWAP_32BIT;
1626#endif
1627 WREG32(CP_RB0_CNTL, tmp);
1628
1629 /* Initialize the ring buffer's read and write pointers */
1630 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1631 ring->wptr = 0;
1632 WREG32(CP_RB0_WPTR, ring->wptr);
1633
1634 /* set the wb address whether it's enabled or not */
1635 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1636 WREG32(CP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1637 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1638
1639 WREG32(SCRATCH_UMSK, 0);
1640
1641 mdelay(1);
1642 WREG32(CP_RB0_CNTL, tmp);
1643
1644 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1645
1646 /* start the rings */
1647 gfx_v6_0_cp_gfx_start(adev);
1648 ring->ready = true;
1649 r = amdgpu_ring_test_ring(ring);
1650 if (r) {
1651 ring->ready = false;
1652 return r;
1653 }
1654
1655 return 0;
1656}
1657
6f924e20 1658static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2cd46ad2 1659{
4aeacf0f 1660 return ring->adev->wb.wb[ring->rptr_offs];
2cd46ad2
KW		 1661}
1662
832c6ef7 1663static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2cd46ad2
KW		 1664{
1665 struct amdgpu_device *adev = ring->adev;
2cd46ad2 1666
832c6ef7
TSD		 1667 if (ring == &adev->gfx.gfx_ring[0])
1668 return RREG32(CP_RB0_WPTR);
1669 else if (ring == &adev->gfx.compute_ring[0])
1670 return RREG32(CP_RB1_WPTR);
1671 else if (ring == &adev->gfx.compute_ring[1])
1672 return RREG32(CP_RB2_WPTR);
1673 else
1674 BUG();
2cd46ad2
KW		 1675}
1676
1677static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
1678{
1679 struct amdgpu_device *adev = ring->adev;
1680
1681 WREG32(CP_RB0_WPTR, ring->wptr);
1682 (void)RREG32(CP_RB0_WPTR);
1683}
1684
2cd46ad2
KW		 1685static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
1686{
1687 struct amdgpu_device *adev = ring->adev;
1688
1689 if (ring == &adev->gfx.compute_ring[0]) {
1690 WREG32(CP_RB1_WPTR, ring->wptr);
1691 (void)RREG32(CP_RB1_WPTR);
1692 } else if (ring == &adev->gfx.compute_ring[1]) {
1693 WREG32(CP_RB2_WPTR, ring->wptr);
1694 (void)RREG32(CP_RB2_WPTR);
1695 } else {
1696 BUG();
1697 }
1698
1699}
1700
2cd46ad2
KW		 1701static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1702{
1703 struct amdgpu_ring *ring;
1704 u32 tmp;
1705 u32 rb_bufsz;
1706 int r;
1707 u64 rptr_addr;
1708
1709 /* ring1 - compute only */
1710 /* Set ring buffer size */
1711
1712 ring = &adev->gfx.compute_ring[0];
1713 rb_bufsz = order_base_2(ring->ring_size / 8);
1714 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1715#ifdef __BIG_ENDIAN
1716 tmp |= BUF_SWAP_32BIT;
1717#endif
1718 WREG32(CP_RB1_CNTL, tmp);
1719
1720 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1721 ring->wptr = 0;
1722 WREG32(CP_RB1_WPTR, ring->wptr);
1723
2cd46ad2
KW		 1724 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1725 WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
1726 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1727
1728 mdelay(1);
1729 WREG32(CP_RB1_CNTL, tmp);
2cd46ad2
KW		 1730 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1731
1732 ring = &adev->gfx.compute_ring[1];
1733 rb_bufsz = order_base_2(ring->ring_size / 8);
1734 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1735#ifdef __BIG_ENDIAN
1736 tmp |= BUF_SWAP_32BIT;
1737#endif
1738 WREG32(CP_RB2_CNTL, tmp);
1739
1740 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1741 ring->wptr = 0;
1742 WREG32(CP_RB2_WPTR, ring->wptr);
1743 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1744 WREG32(CP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
1745 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1746
1747 mdelay(1);
1748 WREG32(CP_RB2_CNTL, tmp);
2cd46ad2
KW		 1749 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1750
1751 adev->gfx.compute_ring[0].ready = true;
1752 adev->gfx.compute_ring[1].ready = true;
1753
1754 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[0]);
1755 if (r) {
1756 adev->gfx.compute_ring[0].ready = false;
1757 return r;
1758 }
1759
1760 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[1]);
1761 if (r) {
1762 adev->gfx.compute_ring[1].ready = false;
1763 return r;
1764 }
1765
1766 return 0;
1767}
1768
1769static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
1770{
1771 gfx_v6_0_cp_gfx_enable(adev, enable);
1772}
1773
1774static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
1775{
4aeacf0f 1776 return gfx_v6_0_cp_gfx_load_microcode(adev);
2cd46ad2
KW		 1777}
1778
1779static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1780 bool enable)
1781{
1782 u32 tmp = RREG32(CP_INT_CNTL_RING0);
1783 u32 mask;
1784 int i;
1785
1786 if (enable)
1787 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1788 else
1789 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1790 WREG32(CP_INT_CNTL_RING0, tmp);
1791
1792 if (!enable) {
1793 /* read a gfx register */
1794 tmp = RREG32(DB_DEPTH_INFO);
1795
1796 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
1797 for (i = 0; i < adev->usec_timeout; i++) {
1798 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
1799 break;
1800 udelay(1);
1801 }
1802 }
1803}
1804
1805static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
1806{
1807 int r;
1808
1809 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
1810
1811 r = gfx_v6_0_cp_load_microcode(adev);
1812 if (r)
1813 return r;
1814
1815 r = gfx_v6_0_cp_gfx_resume(adev);
1816 if (r)
1817 return r;
1818 r = gfx_v6_0_cp_compute_resume(adev);
1819 if (r)
1820 return r;
1821
1822 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
1823
1824 return 0;
1825}
1826
1827static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1828{
1829 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1830 uint32_t seq = ring->fence_drv.sync_seq;
1831 uint64_t addr = ring->fence_drv.gpu_addr;
1832
1833 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1834 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
1835 WAIT_REG_MEM_FUNCTION(3) | /* equal */
1836 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
1837 amdgpu_ring_write(ring, addr & 0xfffffffc);
1838 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1839 amdgpu_ring_write(ring, seq);
1840 amdgpu_ring_write(ring, 0xffffffff);
1841 amdgpu_ring_write(ring, 4); /* poll interval */
1842
1843 if (usepfp) {
1844 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1845 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1846 amdgpu_ring_write(ring, 0);
1847 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1848 amdgpu_ring_write(ring, 0);
1849 }
1850}
1851
1852static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1853 unsigned vm_id, uint64_t pd_addr)
1854{
1855 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1856
1857 /* write new base address */
1858 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1859 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1860 WRITE_DATA_DST_SEL(0)));
1861 if (vm_id < 8) {
1862 amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
1863 } else {
1864 amdgpu_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
1865 }
1866 amdgpu_ring_write(ring, 0);
1867 amdgpu_ring_write(ring, pd_addr >> 12);
1868
1869 /* bits 0-15 are the VM contexts0-15 */
1870 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1871 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1872 WRITE_DATA_DST_SEL(0)));
1873 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1874 amdgpu_ring_write(ring, 0);
1875 amdgpu_ring_write(ring, 1 << vm_id);
1876
1877 /* wait for the invalidate to complete */
1878 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1879 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
1880 WAIT_REG_MEM_ENGINE(0))); /* me */
1881 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1882 amdgpu_ring_write(ring, 0);
1883 amdgpu_ring_write(ring, 0); /* ref */
1884 amdgpu_ring_write(ring, 0); /* mask */
1885 amdgpu_ring_write(ring, 0x20); /* poll interval */
1886
1887 if (usepfp) {
1888 /* sync PFP to ME, otherwise we might get invalid PFP reads */
1889 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
1890 amdgpu_ring_write(ring, 0x0);
1891
1892 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1893 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1894 amdgpu_ring_write(ring, 0);
1895 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1896 amdgpu_ring_write(ring, 0);
1897 }
1898}
1899
1900
1901static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
1902{
1903 int r;
1904
1905 if (adev->gfx.rlc.save_restore_obj) {
1906 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
1907 if (unlikely(r != 0))
1908 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
1909 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
1910 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
1911
1912 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
1913 adev->gfx.rlc.save_restore_obj = NULL;
1914 }
1915
1916 if (adev->gfx.rlc.clear_state_obj) {
1917 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1918 if (unlikely(r != 0))
1919 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
1920 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1921 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1922
1923 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
1924 adev->gfx.rlc.clear_state_obj = NULL;
1925 }
1926
1927 if (adev->gfx.rlc.cp_table_obj) {
1928 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
1929 if (unlikely(r != 0))
1930 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
1931 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
1932 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1933
1934 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
1935 adev->gfx.rlc.cp_table_obj = NULL;
1936 }
1937}
1938
1939static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
1940{
1941 const u32 *src_ptr;
1942 volatile u32 *dst_ptr;
1943 u32 dws, i;
1944 u64 reg_list_mc_addr;
1945 const struct cs_section_def *cs_data;
1946 int r;
1947
1948 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
1949 adev->gfx.rlc.reg_list_size =
1950 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
1951
1952 adev->gfx.rlc.cs_data = si_cs_data;
1953 src_ptr = adev->gfx.rlc.reg_list;
1954 dws = adev->gfx.rlc.reg_list_size;
1955 cs_data = adev->gfx.rlc.cs_data;
1956
1957 if (src_ptr) {
1958 /* save restore block */
1959 if (adev->gfx.rlc.save_restore_obj == NULL) {
1960
1961 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
1962 AMDGPU_GEM_DOMAIN_VRAM,
1963 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1964 NULL, NULL,
1965 &adev->gfx.rlc.save_restore_obj);
1966
1967 if (r) {
1968 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
1969 return r;
1970 }
1971 }
1972
1973 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
1974 if (unlikely(r != 0)) {
1975 gfx_v6_0_rlc_fini(adev);
1976 return r;
1977 }
1978 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
1979 &adev->gfx.rlc.save_restore_gpu_addr);
1980 if (r) {
1981 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
1982 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
1983 gfx_v6_0_rlc_fini(adev);
1984 return r;
1985 }
1986
1987 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
1988 if (r) {
1989 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
1990 gfx_v6_0_rlc_fini(adev);
1991 return r;
1992 }
1993 /* write the sr buffer */
1994 dst_ptr = adev->gfx.rlc.sr_ptr;
1995 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
1996 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
1997 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
1998 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
1999 }
2000
2001 if (cs_data) {
2002 /* clear state block */
2003 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2004 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2005
2006 if (adev->gfx.rlc.clear_state_obj == NULL) {
2007 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2008 AMDGPU_GEM_DOMAIN_VRAM,
2009 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2010 NULL, NULL,
2011 &adev->gfx.rlc.clear_state_obj);
2012
2013 if (r) {
2014 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2015 gfx_v6_0_rlc_fini(adev);
2016 return r;
2017 }
2018 }
2019 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2020 if (unlikely(r != 0)) {
2021 gfx_v6_0_rlc_fini(adev);
2022 return r;
2023 }
2024 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
2025 &adev->gfx.rlc.clear_state_gpu_addr);
2026 if (r) {
2027 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2028 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
2029 gfx_v6_0_rlc_fini(adev);
2030 return r;
2031 }
2032
2033 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
2034 if (r) {
2035 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
2036 gfx_v6_0_rlc_fini(adev);
2037 return r;
2038 }
2039 /* set up the cs buffer */
2040 dst_ptr = adev->gfx.rlc.cs_ptr;
2041 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2042 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2043 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2044 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2045 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2046 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2047 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2048 }
2049
2050 return 0;
2051}
2052
2053static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2054{
2055 u32 tmp;
2056
2057 tmp = RREG32(RLC_LB_CNTL);
2058 if (enable)
2059 tmp |= LOAD_BALANCE_ENABLE;
2060 else
2061 tmp &= ~LOAD_BALANCE_ENABLE;
2062 WREG32(RLC_LB_CNTL, tmp);
2063
2064 if (!enable) {
2065 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2066 WREG32(SPI_LB_CU_MASK, 0x00ff);
2067 }
2068
2069}
2070
2071static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2072{
2073 int i;
2074
2075 for (i = 0; i < adev->usec_timeout; i++) {
2076 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
2077 break;
2078 udelay(1);
2079 }
2080
2081 for (i = 0; i < adev->usec_timeout; i++) {
2082 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
2083 break;
2084 udelay(1);
2085 }
2086}
2087
2088static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2089{
2090 u32 tmp;
2091
2092 tmp = RREG32(RLC_CNTL);
2093 if (tmp != rlc)
2094 WREG32(RLC_CNTL, rlc);
2095}
2096
2097static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2098{
2099 u32 data, orig;
2100
2101 orig = data = RREG32(RLC_CNTL);
2102
2103 if (data & RLC_ENABLE) {
2104 data &= ~RLC_ENABLE;
2105 WREG32(RLC_CNTL, data);
2106
2107 gfx_v6_0_wait_for_rlc_serdes(adev);
2108 }
2109
2110 return orig;
2111}
2112
2113static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2114{
2115 WREG32(RLC_CNTL, 0);
2116
2117 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2cd46ad2
KW		 2118 gfx_v6_0_wait_for_rlc_serdes(adev);
2119}
2120
2121static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2122{
2123 WREG32(RLC_CNTL, RLC_ENABLE);
2124
2125 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2126
2127 udelay(50);
2128}
2129
2130static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2131{
2132 u32 tmp = RREG32(GRBM_SOFT_RESET);
2133
2134 tmp |= SOFT_RESET_RLC;
2135 WREG32(GRBM_SOFT_RESET, tmp);
2136 udelay(50);
2137 tmp &= ~SOFT_RESET_RLC;
2138 WREG32(GRBM_SOFT_RESET, tmp);
2139 udelay(50);
2140}
2141
2142static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2143{
2144 u32 tmp;
2145
2146 /* Enable LBPW only for DDR3 */
2147 tmp = RREG32(MC_SEQ_MISC0);
2148 if ((tmp & 0xF0000000) == 0xB0000000)
2149 return true;
2150 return false;
2151}
2152static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2153{
2154}
2155
2156static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2157{
2158 u32 i;
2159 const struct rlc_firmware_header_v1_0 *hdr;
2160 const __le32 *fw_data;
2161 u32 fw_size;
2162
2163
2164 if (!adev->gfx.rlc_fw)
2165 return -EINVAL;
2166
2167 gfx_v6_0_rlc_stop(adev);
2cd46ad2 2168 gfx_v6_0_rlc_reset(adev);
2cd46ad2 2169 gfx_v6_0_init_pg(adev);
2cd46ad2
KW		 2170 gfx_v6_0_init_cg(adev);
2171
2172 WREG32(RLC_RL_BASE, 0);
2173 WREG32(RLC_RL_SIZE, 0);
2174 WREG32(RLC_LB_CNTL, 0);
2175 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
2176 WREG32(RLC_LB_CNTR_INIT, 0);
2177 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
2178
2179 WREG32(RLC_MC_CNTL, 0);
2180 WREG32(RLC_UCODE_CNTL, 0);
2181
2182 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2183 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2184 fw_data = (const __le32 *)
2185 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2186
2187 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2188
2189 for (i = 0; i < fw_size; i++) {
2190 WREG32(RLC_UCODE_ADDR, i);
2191 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
2192 }
2193 WREG32(RLC_UCODE_ADDR, 0);
2194
2195 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2cd46ad2
KW		 2196 gfx_v6_0_rlc_start(adev);
2197
2198 return 0;
2199}
2200
2201static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2202{
2203 u32 data, orig, tmp;
2204
2205 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
2206
2207 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2208 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2209
2210 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
2211
2212 tmp = gfx_v6_0_halt_rlc(adev);
2213
2214 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2215 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2216 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
2217
2218 gfx_v6_0_wait_for_rlc_serdes(adev);
2cd46ad2
KW		 2219 gfx_v6_0_update_rlc(adev, tmp);
2220
2221 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
2222
2223 data |= CGCG_EN | CGLS_EN;
2224 } else {
2225 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2226
2227 RREG32(CB_CGTT_SCLK_CTRL);
2228 RREG32(CB_CGTT_SCLK_CTRL);
2229 RREG32(CB_CGTT_SCLK_CTRL);
2230 RREG32(CB_CGTT_SCLK_CTRL);
2231
2232 data &= ~(CGCG_EN | CGLS_EN);
2233 }
2234
2235 if (orig != data)
2236 WREG32(RLC_CGCG_CGLS_CTRL, data);
2237
2238}
2239
2240static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2241{
2242
2243 u32 data, orig, tmp = 0;
2244
2245 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2246 orig = data = RREG32(CGTS_SM_CTRL_REG);
2247 data = 0x96940200;
2248 if (orig != data)
2249 WREG32(CGTS_SM_CTRL_REG, data);
2250
2251 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2252 orig = data = RREG32(CP_MEM_SLP_CNTL);
2253 data |= CP_MEM_LS_EN;
2254 if (orig != data)
2255 WREG32(CP_MEM_SLP_CNTL, data);
2256 }
2257
2258 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2259 data &= 0xffffffc0;
2260 if (orig != data)
2261 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2262
2263 tmp = gfx_v6_0_halt_rlc(adev);
2264
2265 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2266 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2267 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
2268
2269 gfx_v6_0_update_rlc(adev, tmp);
2270 } else {
2271 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2272 data |= 0x00000003;
2273 if (orig != data)
2274 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2275
2276 data = RREG32(CP_MEM_SLP_CNTL);
2277 if (data & CP_MEM_LS_EN) {
2278 data &= ~CP_MEM_LS_EN;
2279 WREG32(CP_MEM_SLP_CNTL, data);
2280 }
2281 orig = data = RREG32(CGTS_SM_CTRL_REG);
2282 data |= LS_OVERRIDE | OVERRIDE;
2283 if (orig != data)
2284 WREG32(CGTS_SM_CTRL_REG, data);
2285
2286 tmp = gfx_v6_0_halt_rlc(adev);
2287
2288 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2289 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2290 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
2291
2292 gfx_v6_0_update_rlc(adev, tmp);
2293 }
2294}
2295/*
2296static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2297 bool enable)
2298{
2299 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2300 if (enable) {
2301 gfx_v6_0_enable_mgcg(adev, true);
2302 gfx_v6_0_enable_cgcg(adev, true);
2303 } else {
2304 gfx_v6_0_enable_cgcg(adev, false);
2305 gfx_v6_0_enable_mgcg(adev, false);
2306 }
2307 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2308}
2309*/
2310static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2311 bool enable)
2312{
2313}
2314
2315static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2316 bool enable)
2317{
2318}
2319
2320static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2321{
2322 u32 data, orig;
2323
2324 orig = data = RREG32(RLC_PG_CNTL);
2325 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2326 data &= ~0x8000;
2327 else
2328 data |= 0x8000;
2329 if (orig != data)
2330 WREG32(RLC_PG_CNTL, data);
2331}
2332
2333static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2334{
2335}
2336/*
2337static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2338{
2339 const __le32 *fw_data;
2340 volatile u32 *dst_ptr;
2341 int me, i, max_me = 4;
2342 u32 bo_offset = 0;
2343 u32 table_offset, table_size;
2344
2345 if (adev->asic_type == CHIP_KAVERI)
2346 max_me = 5;
2347
2348 if (adev->gfx.rlc.cp_table_ptr == NULL)
2349 return;
2350
2351 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2352 for (me = 0; me < max_me; me++) {
2353 if (me == 0) {
2354 const struct gfx_firmware_header_v1_0 *hdr =
2355 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2356 fw_data = (const __le32 *)
2357 (adev->gfx.ce_fw->data +
2358 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2359 table_offset = le32_to_cpu(hdr->jt_offset);
2360 table_size = le32_to_cpu(hdr->jt_size);
2361 } else if (me == 1) {
2362 const struct gfx_firmware_header_v1_0 *hdr =
2363 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2364 fw_data = (const __le32 *)
2365 (adev->gfx.pfp_fw->data +
2366 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2367 table_offset = le32_to_cpu(hdr->jt_offset);
2368 table_size = le32_to_cpu(hdr->jt_size);
2369 } else if (me == 2) {
2370 const struct gfx_firmware_header_v1_0 *hdr =
2371 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2372 fw_data = (const __le32 *)
2373 (adev->gfx.me_fw->data +
2374 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2375 table_offset = le32_to_cpu(hdr->jt_offset);
2376 table_size = le32_to_cpu(hdr->jt_size);
2377 } else if (me == 3) {
2378 const struct gfx_firmware_header_v1_0 *hdr =
2379 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2380 fw_data = (const __le32 *)
2381 (adev->gfx.mec_fw->data +
2382 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2383 table_offset = le32_to_cpu(hdr->jt_offset);
2384 table_size = le32_to_cpu(hdr->jt_size);
2385 } else {
2386 const struct gfx_firmware_header_v1_0 *hdr =
2387 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2388 fw_data = (const __le32 *)
2389 (adev->gfx.mec2_fw->data +
2390 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2391 table_offset = le32_to_cpu(hdr->jt_offset);
2392 table_size = le32_to_cpu(hdr->jt_size);
2393 }
2394
2395 for (i = 0; i < table_size; i ++) {
2396 dst_ptr[bo_offset + i] =
2397 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2398 }
2399
2400 bo_offset += table_size;
2401 }
2402}
2403*/
2404static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2405 bool enable)
2406{
2407
2408 u32 tmp;
2409
2410 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2411 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
2412 WREG32(RLC_TTOP_D, tmp);
2413
2414 tmp = RREG32(RLC_PG_CNTL);
2415 tmp |= GFX_PG_ENABLE;
2416 WREG32(RLC_PG_CNTL, tmp);
2417
2418 tmp = RREG32(RLC_AUTO_PG_CTRL);
2419 tmp |= AUTO_PG_EN;
2420 WREG32(RLC_AUTO_PG_CTRL, tmp);
2421 } else {
2422 tmp = RREG32(RLC_AUTO_PG_CTRL);
2423 tmp &= ~AUTO_PG_EN;
2424 WREG32(RLC_AUTO_PG_CTRL, tmp);
2425
2426 tmp = RREG32(DB_RENDER_CONTROL);
2427 }
2428}
2429
2430static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2431 u32 se, u32 sh)
2432{
2433
2434 u32 mask = 0, tmp, tmp1;
2435 int i;
2436
deca1d1f 2437 mutex_lock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 2438 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
2439 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2440 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2441 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 2442 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 2443
2444 tmp &= 0xffff0000;
2445
2446 tmp |= tmp1;
2447 tmp >>= 16;
2448
2449 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
2450 mask <<= 1;
2451 mask |= 1;
2452 }
2453
2454 return (~tmp) & mask;
2455}
2456
2457static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2458{
2459 u32 i, j, k, active_cu_number = 0;
2460
2461 u32 mask, counter, cu_bitmap;
2462 u32 tmp = 0;
2463
2464 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2465 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2466 mask = 1;
2467 cu_bitmap = 0;
2468 counter = 0;
2469 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2470 if (gfx_v6_0_get_cu_active_bitmap(adev, i, j) & mask) {
2471 if (counter < 2)
2472 cu_bitmap |= mask;
2473 counter++;
2474 }
2475 mask <<= 1;
2476 }
2477
2478 active_cu_number += counter;
2479 tmp |= (cu_bitmap << (i * 16 + j * 8));
2480 }
2481 }
2482
2483 WREG32(RLC_PG_AO_CU_MASK, tmp);
2484
2485 tmp = RREG32(RLC_MAX_PG_CU);
2486 tmp &= ~MAX_PU_CU_MASK;
2487 tmp |= MAX_PU_CU(active_cu_number);
2488 WREG32(RLC_MAX_PG_CU, tmp);
2489}
2490
2491static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2492 bool enable)
2493{
2494 u32 data, orig;
2495
2496 orig = data = RREG32(RLC_PG_CNTL);
2497 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2498 data |= STATIC_PER_CU_PG_ENABLE;
2499 else
2500 data &= ~STATIC_PER_CU_PG_ENABLE;
2501 if (orig != data)
2502 WREG32(RLC_PG_CNTL, data);
2503}
2504
2505static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2506 bool enable)
2507{
2508 u32 data, orig;
2509
2510 orig = data = RREG32(RLC_PG_CNTL);
2511 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2512 data |= DYN_PER_CU_PG_ENABLE;
2513 else
2514 data &= ~DYN_PER_CU_PG_ENABLE;
2515 if (orig != data)
2516 WREG32(RLC_PG_CNTL, data);
2517}
2518
2519static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2520{
2521 u32 tmp;
2522
2523 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2524
2525 tmp = RREG32(RLC_PG_CNTL);
2526 tmp |= GFX_PG_SRC;
2527 WREG32(RLC_PG_CNTL, tmp);
2528
2529 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2530
2531 tmp = RREG32(RLC_AUTO_PG_CTRL);
2532
2533 tmp &= ~GRBM_REG_SGIT_MASK;
2534 tmp |= GRBM_REG_SGIT(0x700);
2535 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
2536 WREG32(RLC_AUTO_PG_CTRL, tmp);
2537}
2538
2539static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2540{
2541 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2542 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2543 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2544}
2545
2546static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2547{
2548 u32 count = 0;
2549 const struct cs_section_def *sect = NULL;
2550 const struct cs_extent_def *ext = NULL;
2551
2552 if (adev->gfx.rlc.cs_data == NULL)
2553 return 0;
2554
2555 /* begin clear state */
2556 count += 2;
2557 /* context control state */
2558 count += 3;
2559
2560 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2561 for (ext = sect->section; ext->extent != NULL; ++ext) {
2562 if (sect->id == SECT_CONTEXT)
2563 count += 2 + ext->reg_count;
2564 else
2565 return 0;
2566 }
2567 }
2568 /* pa_sc_raster_config */
2569 count += 3;
2570 /* end clear state */
2571 count += 2;
2572 /* clear state */
2573 count += 2;
2574
2575 return count;
2576}
2577
2578static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2579 volatile u32 *buffer)
2580{
2581 u32 count = 0, i;
2582 const struct cs_section_def *sect = NULL;
2583 const struct cs_extent_def *ext = NULL;
2584
2585 if (adev->gfx.rlc.cs_data == NULL)
2586 return;
2587 if (buffer == NULL)
2588 return;
2589
2590 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2591 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2592
2593 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2594 buffer[count++] = cpu_to_le32(0x80000000);
2595 buffer[count++] = cpu_to_le32(0x80000000);
2596
2597 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2598 for (ext = sect->section; ext->extent != NULL; ++ext) {
2599 if (sect->id == SECT_CONTEXT) {
2600 buffer[count++] =
2601 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2602 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2603 for (i = 0; i < ext->reg_count; i++)
2604 buffer[count++] = cpu_to_le32(ext->extent[i]);
2605 } else {
2606 return;
2607 }
2608 }
2609 }
2610
2611 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2612 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2613
2614 switch (adev->asic_type) {
2615 case CHIP_TAHITI:
2616 case CHIP_PITCAIRN:
2617 buffer[count++] = cpu_to_le32(0x2a00126a);
2618 break;
2619 case CHIP_VERDE:
2620 buffer[count++] = cpu_to_le32(0x0000124a);
2621 break;
2622 case CHIP_OLAND:
2623 buffer[count++] = cpu_to_le32(0x00000082);
2624 break;
2625 case CHIP_HAINAN:
2626 buffer[count++] = cpu_to_le32(0x00000000);
2627 break;
2628 default:
2629 buffer[count++] = cpu_to_le32(0x00000000);
2630 break;
2631 }
2632
2633 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2634 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2635
2636 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2637 buffer[count++] = cpu_to_le32(0);
2638}
2639
2640static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2641{
2642 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2643 AMD_PG_SUPPORT_GFX_SMG |
2644 AMD_PG_SUPPORT_GFX_DMG |
2645 AMD_PG_SUPPORT_CP |
2646 AMD_PG_SUPPORT_GDS |
2647 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2648 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2649 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2650 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2651 gfx_v6_0_init_gfx_cgpg(adev);
2652 gfx_v6_0_enable_cp_pg(adev, true);
2653 gfx_v6_0_enable_gds_pg(adev, true);
2654 } else {
2655 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2656 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2657
2658 }
2659 gfx_v6_0_init_ao_cu_mask(adev);
2660 gfx_v6_0_update_gfx_pg(adev, true);
2661 } else {
2662
2663 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2664 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2665 }
2666}
2667
2668static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2669{
2670 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2671 AMD_PG_SUPPORT_GFX_SMG |
2672 AMD_PG_SUPPORT_GFX_DMG |
2673 AMD_PG_SUPPORT_CP |
2674 AMD_PG_SUPPORT_GDS |
2675 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2676 gfx_v6_0_update_gfx_pg(adev, false);
2677 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2678 gfx_v6_0_enable_cp_pg(adev, false);
2679 gfx_v6_0_enable_gds_pg(adev, false);
2680 }
2681 }
2682}
2683
2684static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2685{
2686 uint64_t clock;
2687
2688 mutex_lock(&adev->gfx.gpu_clock_mutex);
2689 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2690 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
2691 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2692 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2693 return clock;
2694}
2695
2696static void gfx_v6_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
2697 uint32_t vmid,
2698 uint32_t gds_base, uint32_t gds_size,
2699 uint32_t gws_base, uint32_t gws_size,
2700 uint32_t oa_base, uint32_t oa_size)
2701{
2702}
2703
2704static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
2705 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
2706 .select_se_sh = &gfx_v6_0_select_se_sh,
2707};
2708
2709static int gfx_v6_0_early_init(void *handle)
2710{
2711 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2712
2713 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
2714 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
2715 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
2716 gfx_v6_0_set_ring_funcs(adev);
2717 gfx_v6_0_set_irq_funcs(adev);
2718
2719 return 0;
2720}
2721
2722static int gfx_v6_0_sw_init(void *handle)
2723{
2724 struct amdgpu_ring *ring;
2725 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2726 int i, r;
2727
2728 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
2729 if (r)
2730 return r;
2731
2732 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
2733 if (r)
2734 return r;
2735
2736 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
2737 if (r)
2738 return r;
2739
2740 gfx_v6_0_scratch_init(adev);
2741
2742 r = gfx_v6_0_init_microcode(adev);
2743 if (r) {
2744 DRM_ERROR("Failed to load gfx firmware!\n");
2745 return r;
2746 }
2747
2748 r = gfx_v6_0_rlc_init(adev);
2749 if (r) {
2750 DRM_ERROR("Failed to init rlc BOs!\n");
2751 return r;
2752 }
2753
2754 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2755 ring = &adev->gfx.gfx_ring[i];
2756 ring->ring_obj = NULL;
2757 sprintf(ring->name, "gfx");
2758 r = amdgpu_ring_init(adev, ring, 1024,
2759 0x80000000, 0xf,
2760 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
2761 AMDGPU_RING_TYPE_GFX);
2762 if (r)
2763 return r;
2764 }
2765
2766 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2767 unsigned irq_type;
2768
2769 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
2770 DRM_ERROR("Too many (%d) compute rings!\n", i);
2771 break;
2772 }
2773 ring = &adev->gfx.compute_ring[i];
2774 ring->ring_obj = NULL;
2775 ring->use_doorbell = false;
2776 ring->doorbell_index = 0;
2777 ring->me = 1;
2778 ring->pipe = i;
2779 ring->queue = i;
2780 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
2781 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2255e8c1 2782 r = amdgpu_ring_init(adev, ring, 1024,
2cd46ad2
KW		 2783 0x80000000, 0xf,
2784 &adev->gfx.eop_irq, irq_type,
2785 AMDGPU_RING_TYPE_COMPUTE);
2786 if (r)
2787 return r;
2788 }
2789
2790 return r;
2791}
2792
2793static int gfx_v6_0_sw_fini(void *handle)
2794{
2795 int i;
2796 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2797
2798 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
2799 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
2800 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
2801
2802 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2803 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2804 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2805 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2806
2cd46ad2
KW		 2807 gfx_v6_0_rlc_fini(adev);
2808
2809 return 0;
2810}
2811
2812static int gfx_v6_0_hw_init(void *handle)
2813{
2814 int r;
2815 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2816
2817 gfx_v6_0_gpu_init(adev);
2818
2819 r = gfx_v6_0_rlc_resume(adev);
2820 if (r)
2821 return r;
2822
2823 r = gfx_v6_0_cp_resume(adev);
2824 if (r)
2825 return r;
2826
2827 adev->gfx.ce_ram_size = 0x8000;
2828
2829 return r;
2830}
2831
2832static int gfx_v6_0_hw_fini(void *handle)
2833{
2834 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2835
2836 gfx_v6_0_cp_enable(adev, false);
2837 gfx_v6_0_rlc_stop(adev);
2838 gfx_v6_0_fini_pg(adev);
2839
2840 return 0;
2841}
2842
2843static int gfx_v6_0_suspend(void *handle)
2844{
2845 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2846
2847 return gfx_v6_0_hw_fini(adev);
2848}
2849
2850static int gfx_v6_0_resume(void *handle)
2851{
2852 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2853
2854 return gfx_v6_0_hw_init(adev);
2855}
2856
2857static bool gfx_v6_0_is_idle(void *handle)
2858{
2859 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2860
2861 if (RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
2862 return false;
2863 else
2864 return true;
2865}
2866
2867static int gfx_v6_0_wait_for_idle(void *handle)
2868{
2869 unsigned i;
2cd46ad2
KW		 2870 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2871
2872 for (i = 0; i < adev->usec_timeout; i++) {
4aeacf0f 2873 if (gfx_v6_0_is_idle(handle))
2cd46ad2
KW		 2874 return 0;
2875 udelay(1);
2876 }
2877 return -ETIMEDOUT;
2878}
2879
2880static int gfx_v6_0_soft_reset(void *handle)
2881{
2882 return 0;
2883}
2884
2885static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
2886 enum amdgpu_interrupt_state state)
2887{
2888 u32 cp_int_cntl;
2889
2890 switch (state) {
2891 case AMDGPU_IRQ_STATE_DISABLE:
2892 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2893 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2894 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2895 break;
2896 case AMDGPU_IRQ_STATE_ENABLE:
2897 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2898 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2899 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2900 break;
2901 default:
2902 break;
2903 }
2904}
2905
2906static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
2907 int ring,
2908 enum amdgpu_interrupt_state state)
2909{
2910 u32 cp_int_cntl;
2911 switch (state){
2912 case AMDGPU_IRQ_STATE_DISABLE:
2913 if (ring == 0) {
2914 cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
2915 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2916 WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
2917 break;
2918 } else {
2919 cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
2920 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2921 WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
2922 break;
2923
2924 }
2925 case AMDGPU_IRQ_STATE_ENABLE:
2926 if (ring == 0) {
2927 cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
2928 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2929 WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
2930 break;
2931 } else {
2932 cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
2933 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2934 WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
2935 break;
2936
2937 }
2938
2939 default:
2940 BUG();
2941 break;
2942
2943 }
2944}
2945
2946static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
2947 struct amdgpu_irq_src *src,
2948 unsigned type,
2949 enum amdgpu_interrupt_state state)
2950{
2951 u32 cp_int_cntl;
2952
2953 switch (state) {
2954 case AMDGPU_IRQ_STATE_DISABLE:
2955 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2956 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
2957 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2958 break;
2959 case AMDGPU_IRQ_STATE_ENABLE:
2960 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2961 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
2962 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2963 break;
2964 default:
2965 break;
2966 }
2967
2968 return 0;
2969}
2970
2971static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
2972 struct amdgpu_irq_src *src,
2973 unsigned type,
2974 enum amdgpu_interrupt_state state)
2975{
2976 u32 cp_int_cntl;
2977
2978 switch (state) {
2979 case AMDGPU_IRQ_STATE_DISABLE:
2980 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2981 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
2982 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2983 break;
2984 case AMDGPU_IRQ_STATE_ENABLE:
2985 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2986 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
2987 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2988 break;
2989 default:
2990 break;
2991 }
2992
2993 return 0;
2994}
2995
2996static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
2997 struct amdgpu_irq_src *src,
2998 unsigned type,
2999 enum amdgpu_interrupt_state state)
3000{
3001 switch (type) {
3002 case AMDGPU_CP_IRQ_GFX_EOP:
3003 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3004 break;
3005 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3006 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3007 break;
3008 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3009 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3010 break;
3011 default:
3012 break;
3013 }
3014 return 0;
3015}
3016
3017static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3018 struct amdgpu_irq_src *source,
3019 struct amdgpu_iv_entry *entry)
3020{
3021 switch (entry->ring_id) {
3022 case 0:
3023 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3024 break;
3025 case 1:
3026 case 2:
3027 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id -1]);
3028 break;
3029 default:
3030 break;
3031 }
3032 return 0;
3033}
3034
3035static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3036 struct amdgpu_irq_src *source,
3037 struct amdgpu_iv_entry *entry)
3038{
3039 DRM_ERROR("Illegal register access in command stream\n");
3040 schedule_work(&adev->reset_work);
3041 return 0;
3042}
3043
3044static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3045 struct amdgpu_irq_src *source,
3046 struct amdgpu_iv_entry *entry)
3047{
3048 DRM_ERROR("Illegal instruction in command stream\n");
3049 schedule_work(&adev->reset_work);
3050 return 0;
3051}
3052
3053static int gfx_v6_0_set_clockgating_state(void *handle,
3054 enum amd_clockgating_state state)
3055{
3056 bool gate = false;
3057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3058
3059 if (state == AMD_CG_STATE_GATE)
3060 gate = true;
3061
3062 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3063 if (gate) {
3064 gfx_v6_0_enable_mgcg(adev, true);
3065 gfx_v6_0_enable_cgcg(adev, true);
3066 } else {
3067 gfx_v6_0_enable_cgcg(adev, false);
3068 gfx_v6_0_enable_mgcg(adev, false);
3069 }
3070 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3071
3072 return 0;
3073}
3074
3075static int gfx_v6_0_set_powergating_state(void *handle,
3076 enum amd_powergating_state state)
3077{
3078 bool gate = false;
3079 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3080
3081 if (state == AMD_PG_STATE_GATE)
3082 gate = true;
3083
3084 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3085 AMD_PG_SUPPORT_GFX_SMG |
3086 AMD_PG_SUPPORT_GFX_DMG |
3087 AMD_PG_SUPPORT_CP |
3088 AMD_PG_SUPPORT_GDS |
3089 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3090 gfx_v6_0_update_gfx_pg(adev, gate);
3091 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3092 gfx_v6_0_enable_cp_pg(adev, gate);
3093 gfx_v6_0_enable_gds_pg(adev, gate);
3094 }
3095 }
3096
3097 return 0;
3098}
3099
3100const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3101 .name = "gfx_v6_0",
3102 .early_init = gfx_v6_0_early_init,
3103 .late_init = NULL,
3104 .sw_init = gfx_v6_0_sw_init,
3105 .sw_fini = gfx_v6_0_sw_fini,
3106 .hw_init = gfx_v6_0_hw_init,
3107 .hw_fini = gfx_v6_0_hw_fini,
3108 .suspend = gfx_v6_0_suspend,
3109 .resume = gfx_v6_0_resume,
3110 .is_idle = gfx_v6_0_is_idle,
3111 .wait_for_idle = gfx_v6_0_wait_for_idle,
3112 .soft_reset = gfx_v6_0_soft_reset,
3113 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3114 .set_powergating_state = gfx_v6_0_set_powergating_state,
3115};
3116
3117static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
6f924e20 3118 .get_rptr = gfx_v6_0_ring_get_rptr,
832c6ef7 3119 .get_wptr = gfx_v6_0_ring_get_wptr,
2cd46ad2
KW		 3120 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3121 .parse_cs = NULL,
3122 .emit_ib = gfx_v6_0_ring_emit_ib_gfx,
3123 .emit_fence = gfx_v6_0_ring_emit_fence_gfx,
3124 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3125 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3126 .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
3127 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3128 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3129 .test_ring = gfx_v6_0_ring_test_ring,
3130 .test_ib = gfx_v6_0_ring_test_ib,
3131 .insert_nop = amdgpu_ring_insert_nop,
3132};
3133
3134static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
6f924e20 3135 .get_rptr = gfx_v6_0_ring_get_rptr,
832c6ef7 3136 .get_wptr = gfx_v6_0_ring_get_wptr,
2cd46ad2
KW		 3137 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3138 .parse_cs = NULL,
3139 .emit_ib = gfx_v6_0_ring_emit_ib_compute,
3140 .emit_fence = gfx_v6_0_ring_emit_fence_compute,
3141 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3142 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3143 .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
3144 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3145 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3146 .test_ring = gfx_v6_0_ring_test_ring,
3147 .test_ib = gfx_v6_0_ring_test_ib,
3148 .insert_nop = amdgpu_ring_insert_nop,
3149};
3150
3151static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3152{
3153 int i;
3154
3155 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3156 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3157 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3158 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3159}
3160
3161static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3162 .set = gfx_v6_0_set_eop_interrupt_state,
3163 .process = gfx_v6_0_eop_irq,
3164};
3165
3166static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3167 .set = gfx_v6_0_set_priv_reg_fault_state,
3168 .process = gfx_v6_0_priv_reg_irq,
3169};
3170
3171static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3172 .set = gfx_v6_0_set_priv_inst_fault_state,
3173 .process = gfx_v6_0_priv_inst_irq,
3174};
3175
3176static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3177{
3178 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3179 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3180
3181 adev->gfx.priv_reg_irq.num_types = 1;
3182 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3183
3184 adev->gfx.priv_inst_irq.num_types = 1;
3185 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3186}
3187
3188static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3189{
3190 int i, j, k, counter, active_cu_number = 0;
3191 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3192 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3193
3194 memset(cu_info, 0, sizeof(*cu_info));
3195
2cd46ad2
KW		 3196 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3197 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3198 mask = 1;
3199 ao_bitmap = 0;
3200 counter = 0;
2cd46ad2
KW		 3201 bitmap = gfx_v6_0_get_cu_active_bitmap(adev, i, j);
3202 cu_info->bitmap[i][j] = bitmap;
3203
3204 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
3205 if (bitmap & mask) {
3206 if (counter < 2)
3207 ao_bitmap |= mask;
3208 counter ++;
3209 }
3210 mask <<= 1;
3211 }
3212 active_cu_number += counter;
3213 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3214 }
3215 }
2cd46ad2
KW		 3216
3217 cu_info->number = active_cu_number;
3218 cu_info->ao_cu_mask = ao_cu_mask;
3219}
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