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drm/amdgpu/gfx: free memory of mqd backup
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v6_0.c
CommitLineData
2cd46ad2
KW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h"
689957b1 28#include "clearstate_si.h"
25069e06
TSD		 29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gca/gfx_6_0_d.h"
34#include "gca/gfx_6_0_sh_mask.h"
35#include "gmc/gmc_6_0_d.h"
36#include "gmc/gmc_6_0_sh_mask.h"
37#include "dce/dce_6_0_d.h"
38#include "dce/dce_6_0_sh_mask.h"
39#include "gca/gfx_7_2_enum.h"
40#include "si_enums.h"
2cd46ad2
KW		 41
42static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
43static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
44static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
45
46MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
47MODULE_FIRMWARE("radeon/tahiti_me.bin");
48MODULE_FIRMWARE("radeon/tahiti_ce.bin");
49MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
50
51MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
52MODULE_FIRMWARE("radeon/pitcairn_me.bin");
53MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
54MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
55
56MODULE_FIRMWARE("radeon/verde_pfp.bin");
57MODULE_FIRMWARE("radeon/verde_me.bin");
58MODULE_FIRMWARE("radeon/verde_ce.bin");
59MODULE_FIRMWARE("radeon/verde_rlc.bin");
60
61MODULE_FIRMWARE("radeon/oland_pfp.bin");
62MODULE_FIRMWARE("radeon/oland_me.bin");
63MODULE_FIRMWARE("radeon/oland_ce.bin");
64MODULE_FIRMWARE("radeon/oland_rlc.bin");
65
66MODULE_FIRMWARE("radeon/hainan_pfp.bin");
67MODULE_FIRMWARE("radeon/hainan_me.bin");
68MODULE_FIRMWARE("radeon/hainan_ce.bin");
69MODULE_FIRMWARE("radeon/hainan_rlc.bin");
70
71static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
72static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
73//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
74static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
75
25069e06
TSD		 76#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
77#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
78#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
79#define MICRO_TILE_MODE(x) ((x) << 0)
80#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
81#define BANK_WIDTH(x) ((x) << 14)
82#define BANK_HEIGHT(x) ((x) << 16)
83#define MACRO_TILE_ASPECT(x) ((x) << 18)
84#define NUM_BANKS(x) ((x) << 20)
2cd46ad2
KW		 85
86static const u32 verde_rlc_save_restore_register_list[] =
87{
88 (0x8000 << 16) | (0x98f4 >> 2),
89 0x00000000,
90 (0x8040 << 16) | (0x98f4 >> 2),
91 0x00000000,
92 (0x8000 << 16) | (0xe80 >> 2),
93 0x00000000,
94 (0x8040 << 16) | (0xe80 >> 2),
95 0x00000000,
96 (0x8000 << 16) | (0x89bc >> 2),
97 0x00000000,
98 (0x8040 << 16) | (0x89bc >> 2),
99 0x00000000,
100 (0x8000 << 16) | (0x8c1c >> 2),
101 0x00000000,
102 (0x8040 << 16) | (0x8c1c >> 2),
103 0x00000000,
104 (0x9c00 << 16) | (0x98f0 >> 2),
105 0x00000000,
106 (0x9c00 << 16) | (0xe7c >> 2),
107 0x00000000,
108 (0x8000 << 16) | (0x9148 >> 2),
109 0x00000000,
110 (0x8040 << 16) | (0x9148 >> 2),
111 0x00000000,
112 (0x9c00 << 16) | (0x9150 >> 2),
113 0x00000000,
114 (0x9c00 << 16) | (0x897c >> 2),
115 0x00000000,
116 (0x9c00 << 16) | (0x8d8c >> 2),
117 0x00000000,
118 (0x9c00 << 16) | (0xac54 >> 2),
119 0X00000000,
120 0x3,
121 (0x9c00 << 16) | (0x98f8 >> 2),
122 0x00000000,
123 (0x9c00 << 16) | (0x9910 >> 2),
124 0x00000000,
125 (0x9c00 << 16) | (0x9914 >> 2),
126 0x00000000,
127 (0x9c00 << 16) | (0x9918 >> 2),
128 0x00000000,
129 (0x9c00 << 16) | (0x991c >> 2),
130 0x00000000,
131 (0x9c00 << 16) | (0x9920 >> 2),
132 0x00000000,
133 (0x9c00 << 16) | (0x9924 >> 2),
134 0x00000000,
135 (0x9c00 << 16) | (0x9928 >> 2),
136 0x00000000,
137 (0x9c00 << 16) | (0x992c >> 2),
138 0x00000000,
139 (0x9c00 << 16) | (0x9930 >> 2),
140 0x00000000,
141 (0x9c00 << 16) | (0x9934 >> 2),
142 0x00000000,
143 (0x9c00 << 16) | (0x9938 >> 2),
144 0x00000000,
145 (0x9c00 << 16) | (0x993c >> 2),
146 0x00000000,
147 (0x9c00 << 16) | (0x9940 >> 2),
148 0x00000000,
149 (0x9c00 << 16) | (0x9944 >> 2),
150 0x00000000,
151 (0x9c00 << 16) | (0x9948 >> 2),
152 0x00000000,
153 (0x9c00 << 16) | (0x994c >> 2),
154 0x00000000,
155 (0x9c00 << 16) | (0x9950 >> 2),
156 0x00000000,
157 (0x9c00 << 16) | (0x9954 >> 2),
158 0x00000000,
159 (0x9c00 << 16) | (0x9958 >> 2),
160 0x00000000,
161 (0x9c00 << 16) | (0x995c >> 2),
162 0x00000000,
163 (0x9c00 << 16) | (0x9960 >> 2),
164 0x00000000,
165 (0x9c00 << 16) | (0x9964 >> 2),
166 0x00000000,
167 (0x9c00 << 16) | (0x9968 >> 2),
168 0x00000000,
169 (0x9c00 << 16) | (0x996c >> 2),
170 0x00000000,
171 (0x9c00 << 16) | (0x9970 >> 2),
172 0x00000000,
173 (0x9c00 << 16) | (0x9974 >> 2),
174 0x00000000,
175 (0x9c00 << 16) | (0x9978 >> 2),
176 0x00000000,
177 (0x9c00 << 16) | (0x997c >> 2),
178 0x00000000,
179 (0x9c00 << 16) | (0x9980 >> 2),
180 0x00000000,
181 (0x9c00 << 16) | (0x9984 >> 2),
182 0x00000000,
183 (0x9c00 << 16) | (0x9988 >> 2),
184 0x00000000,
185 (0x9c00 << 16) | (0x998c >> 2),
186 0x00000000,
187 (0x9c00 << 16) | (0x8c00 >> 2),
188 0x00000000,
189 (0x9c00 << 16) | (0x8c14 >> 2),
190 0x00000000,
191 (0x9c00 << 16) | (0x8c04 >> 2),
192 0x00000000,
193 (0x9c00 << 16) | (0x8c08 >> 2),
194 0x00000000,
195 (0x8000 << 16) | (0x9b7c >> 2),
196 0x00000000,
197 (0x8040 << 16) | (0x9b7c >> 2),
198 0x00000000,
199 (0x8000 << 16) | (0xe84 >> 2),
200 0x00000000,
201 (0x8040 << 16) | (0xe84 >> 2),
202 0x00000000,
203 (0x8000 << 16) | (0x89c0 >> 2),
204 0x00000000,
205 (0x8040 << 16) | (0x89c0 >> 2),
206 0x00000000,
207 (0x8000 << 16) | (0x914c >> 2),
208 0x00000000,
209 (0x8040 << 16) | (0x914c >> 2),
210 0x00000000,
211 (0x8000 << 16) | (0x8c20 >> 2),
212 0x00000000,
213 (0x8040 << 16) | (0x8c20 >> 2),
214 0x00000000,
215 (0x8000 << 16) | (0x9354 >> 2),
216 0x00000000,
217 (0x8040 << 16) | (0x9354 >> 2),
218 0x00000000,
219 (0x9c00 << 16) | (0x9060 >> 2),
220 0x00000000,
221 (0x9c00 << 16) | (0x9364 >> 2),
222 0x00000000,
223 (0x9c00 << 16) | (0x9100 >> 2),
224 0x00000000,
225 (0x9c00 << 16) | (0x913c >> 2),
226 0x00000000,
227 (0x8000 << 16) | (0x90e0 >> 2),
228 0x00000000,
229 (0x8000 << 16) | (0x90e4 >> 2),
230 0x00000000,
231 (0x8000 << 16) | (0x90e8 >> 2),
232 0x00000000,
233 (0x8040 << 16) | (0x90e0 >> 2),
234 0x00000000,
235 (0x8040 << 16) | (0x90e4 >> 2),
236 0x00000000,
237 (0x8040 << 16) | (0x90e8 >> 2),
238 0x00000000,
239 (0x9c00 << 16) | (0x8bcc >> 2),
240 0x00000000,
241 (0x9c00 << 16) | (0x8b24 >> 2),
242 0x00000000,
243 (0x9c00 << 16) | (0x88c4 >> 2),
244 0x00000000,
245 (0x9c00 << 16) | (0x8e50 >> 2),
246 0x00000000,
247 (0x9c00 << 16) | (0x8c0c >> 2),
248 0x00000000,
249 (0x9c00 << 16) | (0x8e58 >> 2),
250 0x00000000,
251 (0x9c00 << 16) | (0x8e5c >> 2),
252 0x00000000,
253 (0x9c00 << 16) | (0x9508 >> 2),
254 0x00000000,
255 (0x9c00 << 16) | (0x950c >> 2),
256 0x00000000,
257 (0x9c00 << 16) | (0x9494 >> 2),
258 0x00000000,
259 (0x9c00 << 16) | (0xac0c >> 2),
260 0x00000000,
261 (0x9c00 << 16) | (0xac10 >> 2),
262 0x00000000,
263 (0x9c00 << 16) | (0xac14 >> 2),
264 0x00000000,
265 (0x9c00 << 16) | (0xae00 >> 2),
266 0x00000000,
267 (0x9c00 << 16) | (0xac08 >> 2),
268 0x00000000,
269 (0x9c00 << 16) | (0x88d4 >> 2),
270 0x00000000,
271 (0x9c00 << 16) | (0x88c8 >> 2),
272 0x00000000,
273 (0x9c00 << 16) | (0x88cc >> 2),
274 0x00000000,
275 (0x9c00 << 16) | (0x89b0 >> 2),
276 0x00000000,
277 (0x9c00 << 16) | (0x8b10 >> 2),
278 0x00000000,
279 (0x9c00 << 16) | (0x8a14 >> 2),
280 0x00000000,
281 (0x9c00 << 16) | (0x9830 >> 2),
282 0x00000000,
283 (0x9c00 << 16) | (0x9834 >> 2),
284 0x00000000,
285 (0x9c00 << 16) | (0x9838 >> 2),
286 0x00000000,
287 (0x9c00 << 16) | (0x9a10 >> 2),
288 0x00000000,
289 (0x8000 << 16) | (0x9870 >> 2),
290 0x00000000,
291 (0x8000 << 16) | (0x9874 >> 2),
292 0x00000000,
293 (0x8001 << 16) | (0x9870 >> 2),
294 0x00000000,
295 (0x8001 << 16) | (0x9874 >> 2),
296 0x00000000,
297 (0x8040 << 16) | (0x9870 >> 2),
298 0x00000000,
299 (0x8040 << 16) | (0x9874 >> 2),
300 0x00000000,
301 (0x8041 << 16) | (0x9870 >> 2),
302 0x00000000,
303 (0x8041 << 16) | (0x9874 >> 2),
304 0x00000000,
305 0x00000000
306};
307
308static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
309{
310 const char *chip_name;
311 char fw_name[30];
312 int err;
313 const struct gfx_firmware_header_v1_0 *cp_hdr;
314 const struct rlc_firmware_header_v1_0 *rlc_hdr;
315
316 DRM_DEBUG("\n");
317
318 switch (adev->asic_type) {
319 case CHIP_TAHITI:
320 chip_name = "tahiti";
321 break;
322 case CHIP_PITCAIRN:
323 chip_name = "pitcairn";
324 break;
325 case CHIP_VERDE:
326 chip_name = "verde";
327 break;
328 case CHIP_OLAND:
329 chip_name = "oland";
330 break;
331 case CHIP_HAINAN:
332 chip_name = "hainan";
333 break;
334 default: BUG();
335 }
336
337 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
338 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
339 if (err)
340 goto out;
341 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
342 if (err)
343 goto out;
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
347
348 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
349 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
350 if (err)
351 goto out;
352 err = amdgpu_ucode_validate(adev->gfx.me_fw);
353 if (err)
354 goto out;
355 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
356 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
357 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
358
359 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
360 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
361 if (err)
362 goto out;
363 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
364 if (err)
365 goto out;
366 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
367 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
368 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
369
370 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
371 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
372 if (err)
373 goto out;
374 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
375 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
376 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
377 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
378
379out:
380 if (err) {
381 printk(KERN_ERR
382 "gfx6: Failed to load firmware \"%s\"\n",
383 fw_name);
384 release_firmware(adev->gfx.pfp_fw);
385 adev->gfx.pfp_fw = NULL;
386 release_firmware(adev->gfx.me_fw);
387 adev->gfx.me_fw = NULL;
388 release_firmware(adev->gfx.ce_fw);
389 adev->gfx.ce_fw = NULL;
390 release_firmware(adev->gfx.rlc_fw);
391 adev->gfx.rlc_fw = NULL;
392 }
393 return err;
394}
395
396static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
397{
398 const u32 num_tile_mode_states = 32;
399 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
400
401 switch (adev->gfx.config.mem_row_size_in_kb) {
402 case 1:
403 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
404 break;
405 case 2:
406 default:
407 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
408 break;
409 case 4:
410 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
411 break;
412 }
413
3548f9a8
FC		 414 if (adev->asic_type == CHIP_VERDE) {
415 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
416 switch (reg_offset) {
417 case 0:
418 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
419 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
420 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
421 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
422 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
423 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
424 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
425 NUM_BANKS(ADDR_SURF_16_BANK));
426 break;
427 case 1:
428 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
429 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
430 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
431 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
432 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
435 NUM_BANKS(ADDR_SURF_16_BANK));
436 break;
437 case 2:
438 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
439 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
440 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
441 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
442 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
443 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
444 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
445 NUM_BANKS(ADDR_SURF_16_BANK));
446 break;
447 case 3:
448 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
449 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
453 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
454 NUM_BANKS(ADDR_SURF_8_BANK) |
455 TILE_SPLIT(split_equal_to_row_size));
456 break;
457 case 4:
458 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
459 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
460 PIPE_CONFIG(ADDR_SURF_P4_8x16));
461 break;
462 case 5:
463 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
464 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
465 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
466 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
467 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
468 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
469 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
470 NUM_BANKS(ADDR_SURF_4_BANK));
471 break;
472 case 6:
473 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
474 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
475 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
476 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
477 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
480 NUM_BANKS(ADDR_SURF_4_BANK));
481 break;
482 case 7:
483 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
484 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
485 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
486 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
487 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
488 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
489 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
490 NUM_BANKS(ADDR_SURF_2_BANK));
491 break;
492 case 8:
493 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
494 break;
495 case 9:
496 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
497 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
498 PIPE_CONFIG(ADDR_SURF_P4_8x16));
499 break;
500 case 10:
501 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
502 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
503 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
504 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
505 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
508 NUM_BANKS(ADDR_SURF_16_BANK));
509 break;
510 case 11:
511 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
512 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
513 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
514 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
515 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
518 NUM_BANKS(ADDR_SURF_16_BANK));
519 break;
520 case 12:
521 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
522 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
523 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
524 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
528 NUM_BANKS(ADDR_SURF_16_BANK));
529 break;
530 case 13:
531 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
532 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
533 PIPE_CONFIG(ADDR_SURF_P4_8x16));
534 break;
535 case 14:
536 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
537 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
538 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
539 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
543 NUM_BANKS(ADDR_SURF_16_BANK));
544 break;
545 case 15:
546 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
547 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
548 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
549 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
550 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
553 NUM_BANKS(ADDR_SURF_16_BANK));
554 break;
555 case 16:
556 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
557 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
558 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
559 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
560 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
561 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
562 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
563 NUM_BANKS(ADDR_SURF_16_BANK));
564 break;
565 case 17:
566 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
568 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
572 NUM_BANKS(ADDR_SURF_16_BANK) |
573 TILE_SPLIT(split_equal_to_row_size));
574 break;
575 case 18:
576 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
577 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
578 PIPE_CONFIG(ADDR_SURF_P4_8x16));
579 break;
580 case 19:
581 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
582 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
583 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
584 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
585 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
586 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
587 NUM_BANKS(ADDR_SURF_16_BANK) |
588 TILE_SPLIT(split_equal_to_row_size));
589 break;
590 case 20:
591 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
592 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
593 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
597 NUM_BANKS(ADDR_SURF_16_BANK) |
598 TILE_SPLIT(split_equal_to_row_size));
599 break;
600 case 21:
601 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
602 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
603 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
604 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
608 NUM_BANKS(ADDR_SURF_8_BANK));
609 break;
610 case 22:
611 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
612 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
613 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
614 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
615 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
616 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
617 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
618 NUM_BANKS(ADDR_SURF_8_BANK));
619 break;
620 case 23:
621 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
622 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
623 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
628 NUM_BANKS(ADDR_SURF_4_BANK));
629 break;
630 case 24:
631 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
632 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
633 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
634 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
635 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
637 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
638 NUM_BANKS(ADDR_SURF_4_BANK));
639 break;
640 case 25:
641 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
643 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
645 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
646 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
647 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
648 NUM_BANKS(ADDR_SURF_2_BANK));
649 break;
650 case 26:
651 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
652 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
653 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
654 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
655 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
656 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
657 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
658 NUM_BANKS(ADDR_SURF_2_BANK));
659 break;
660 case 27:
661 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
662 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
663 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
664 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
666 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
667 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
668 NUM_BANKS(ADDR_SURF_2_BANK));
669 break;
670 case 28:
671 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
672 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
673 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
674 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
675 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
676 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
677 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
678 NUM_BANKS(ADDR_SURF_2_BANK));
679 break;
680 case 29:
681 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
683 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
684 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
685 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
686 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
688 NUM_BANKS(ADDR_SURF_2_BANK));
689 break;
690 case 30:
691 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
692 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
693 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
694 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
695 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
696 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
697 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
698 NUM_BANKS(ADDR_SURF_2_BANK));
699 break;
700 default:
701 continue;
702 }
703 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
704 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
705 }
706 } else if (adev->asic_type == CHIP_OLAND ||
25069e06 707 adev->asic_type == CHIP_HAINAN) {
2cd46ad2
KW		 708 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
709 switch (reg_offset) {
710 case 0:
f8d9422e
FC		 711 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
712 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
713 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2cd46ad2
KW		 715 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
716 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 717 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
718 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 719 break;
45682886 720 case 1:
f8d9422e
FC		 721 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
722 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
723 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2cd46ad2
KW		 725 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
726 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 727 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
728 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2
KW		 729 break;
730 case 2:
f8d9422e
FC		 731 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
732 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
733 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 734 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 735 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
736 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 737 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
738 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 739 break;
45682886 740 case 3:
f8d9422e
FC		 741 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
742 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
743 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 744 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
f8d9422e
FC		 745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
746 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
747 NUM_BANKS(ADDR_SURF_8_BANK) |
748 TILE_SPLIT(split_equal_to_row_size));
2cd46ad2 749 break;
45682886 750 case 4:
f8d9422e
FC		 751 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
752 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
753 PIPE_CONFIG(ADDR_SURF_P2));
2cd46ad2 754 break;
45682886 755 case 5:
f8d9422e
FC		 756 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
757 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
758 PIPE_CONFIG(ADDR_SURF_P2) |
759 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2 760 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
f8d9422e
FC		 761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
763 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 764 break;
45682886 765 case 6:
f8d9422e
FC		 766 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
767 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
768 PIPE_CONFIG(ADDR_SURF_P2) |
769 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2 770 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
f8d9422e
FC		 771 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
772 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
773 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 774 break;
45682886 775 case 7:
f8d9422e
FC		 776 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
777 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
778 PIPE_CONFIG(ADDR_SURF_P2) |
779 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2cd46ad2 780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
f8d9422e
FC		 781 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
782 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
783 NUM_BANKS(ADDR_SURF_4_BANK));
2cd46ad2 784 break;
45682886 785 case 8:
f8d9422e 786 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
2cd46ad2 787 break;
45682886 788 case 9:
f8d9422e
FC		 789 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
790 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
791 PIPE_CONFIG(ADDR_SURF_P2));
2cd46ad2 792 break;
45682886 793 case 10:
f8d9422e
FC		 794 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
795 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
796 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 797 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
801 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 802 break;
45682886 803 case 11:
f8d9422e
FC		 804 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
805 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
806 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 807 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 808 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
809 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
f8d9422e
FC		 810 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
811 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 812 break;
45682886 813 case 12:
f8d9422e
FC		 814 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
815 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
816 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 817 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2
KW		 818 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
819 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
f8d9422e
FC		 820 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
821 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 822 break;
45682886 823 case 13:
f8d9422e
FC		 824 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
825 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
826 PIPE_CONFIG(ADDR_SURF_P2));
2cd46ad2 827 break;
45682886 828 case 14:
f8d9422e
FC		 829 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
830 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
831 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 832 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
836 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 837 break;
45682886 838 case 15:
f8d9422e
FC		 839 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
840 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
841 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 842 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 843 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
f8d9422e
FC		 845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
846 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 847 break;
45682886 848 case 16:
f8d9422e
FC		 849 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
850 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
851 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 852 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2
KW		 853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
f8d9422e
FC		 855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
856 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 857 break;
45682886 858 case 17:
f8d9422e
FC		 859 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
860 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
861 PIPE_CONFIG(ADDR_SURF_P2) |
862 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
863 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
864 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2cd46ad2 865 NUM_BANKS(ADDR_SURF_16_BANK) |
f8d9422e
FC		 866 TILE_SPLIT(split_equal_to_row_size));
867 break;
868 case 18:
869 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
870 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
871 PIPE_CONFIG(ADDR_SURF_P2));
872 break;
873 case 19:
874 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
875 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
876 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2
KW		 877 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
878 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
f8d9422e
FC		 879 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
880 NUM_BANKS(ADDR_SURF_16_BANK) |
881 TILE_SPLIT(split_equal_to_row_size));
882 break;
883 case 20:
884 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
885 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
886 PIPE_CONFIG(ADDR_SURF_P2) |
887 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
888 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
889 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
890 NUM_BANKS(ADDR_SURF_16_BANK) |
891 TILE_SPLIT(split_equal_to_row_size));
2cd46ad2 892 break;
45682886 893 case 21:
f8d9422e
FC		 894 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
895 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
896 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 897 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 898 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
899 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 900 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
901 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 902 break;
45682886 903 case 22:
f8d9422e
FC		 904 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
905 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
906 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 907 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
f8d9422e
FC		 908 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
911 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 912 break;
45682886 913 case 23:
f8d9422e
FC		 914 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
915 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
916 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 918 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
919 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
f8d9422e
FC		 920 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
921 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 922 break;
45682886 923 case 24:
f8d9422e
FC		 924 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
925 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
926 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2
KW		 928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
f8d9422e
FC		 930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
931 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 932 break;
45682886 933 case 25:
f8d9422e
FC		 934 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
935 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
936 PIPE_CONFIG(ADDR_SURF_P2) |
937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
941 NUM_BANKS(ADDR_SURF_4_BANK));
942 break;
943 case 26:
944 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
945 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
946 PIPE_CONFIG(ADDR_SURF_P2) |
947 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
948 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
949 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
950 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
951 NUM_BANKS(ADDR_SURF_4_BANK));
952 break;
953 case 27:
954 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
955 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 957 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
f8d9422e
FC		 958 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
959 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
960 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
961 NUM_BANKS(ADDR_SURF_4_BANK));
962 break;
963 case 28:
964 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
965 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
966 PIPE_CONFIG(ADDR_SURF_P2) |
967 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
968 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
971 NUM_BANKS(ADDR_SURF_4_BANK));
972 break;
973 case 29:
974 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
975 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
976 PIPE_CONFIG(ADDR_SURF_P2) |
977 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
978 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
979 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
980 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
981 NUM_BANKS(ADDR_SURF_4_BANK));
982 break;
983 case 30:
984 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
985 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
986 PIPE_CONFIG(ADDR_SURF_P2) |
987 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2cd46ad2
KW		 988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
f8d9422e
FC		 990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
991 NUM_BANKS(ADDR_SURF_4_BANK));
2cd46ad2
KW		 992 break;
993 default:
f8d9422e 994 continue;
2cd46ad2
KW		 995 }
996 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
25069e06 997 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2cd46ad2
KW		 998 }
999 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1000 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1001 switch (reg_offset) {
7c0a705e
FC		 1002 case 0:
1003 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1004 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1005 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1006 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2cd46ad2
KW		 1007 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1008 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1009 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1010 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1011 break;
7c0a705e
FC		 1012 case 1:
1013 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1014 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1015 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1016 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2cd46ad2
KW		 1017 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1018 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1019 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1020 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1021 break;
7c0a705e
FC		 1022 case 2:
1023 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1024 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1025 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1027 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1028 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1029 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1030 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1031 break;
7c0a705e
FC		 1032 case 3:
1033 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1034 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2 1035 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2cd46ad2
KW		 1036 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1039 NUM_BANKS(ADDR_SURF_4_BANK) |
1040 TILE_SPLIT(split_equal_to_row_size));
2cd46ad2 1041 break;
7c0a705e
FC		 1042 case 4:
1043 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1044 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1045 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
2cd46ad2 1046 break;
7c0a705e
FC		 1047 case 5:
1048 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1049 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2 1050 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
7c0a705e 1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2 1052 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
7c0a705e
FC		 1053 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1054 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1055 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1056 break;
7c0a705e
FC		 1057 case 6:
1058 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1059 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2 1060 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
7c0a705e 1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2 1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
7c0a705e
FC		 1063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1065 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1066 break;
7c0a705e
FC		 1067 case 7:
1068 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1069 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1071 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2cd46ad2
KW		 1072 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1073 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1074 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1075 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1076 break;
7c0a705e
FC		 1077 case 8:
1078 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
2cd46ad2 1079 break;
7c0a705e
FC		 1080 case 9:
1081 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1082 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1083 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
2cd46ad2 1084 break;
7c0a705e
FC		 1085 case 10:
1086 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1087 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1088 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1089 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1093 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1094 break;
7c0a705e
FC		 1095 case 11:
1096 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1097 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1098 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1099 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1100 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1101 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
7c0a705e
FC		 1102 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1103 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1104 break;
7c0a705e
FC		 1105 case 12:
1106 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1107 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1108 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1109 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2
KW		 1110 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
7c0a705e
FC		 1112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1113 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1114 break;
7c0a705e
FC		 1115 case 13:
1116 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1117 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1118 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
2cd46ad2 1119 break;
7c0a705e
FC		 1120 case 14:
1121 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1122 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1123 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1125 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1128 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1129 break;
7c0a705e
FC		 1130 case 15:
1131 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1132 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1135 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
7c0a705e
FC		 1137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1138 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1139 break;
7c0a705e
FC		 1140 case 16:
1141 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1142 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1143 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2
KW		 1145 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1146 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
7c0a705e
FC		 1147 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1148 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1149 break;
7c0a705e
FC		 1150 case 17:
1151 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1152 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2 1153 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
7c0a705e
FC		 1154 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2cd46ad2 1157 NUM_BANKS(ADDR_SURF_16_BANK) |
7c0a705e
FC		 1158 TILE_SPLIT(split_equal_to_row_size));
1159 break;
1160 case 18:
1161 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1162 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1163 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
1164 break;
1165 case 19:
1166 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1167 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1168 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2cd46ad2
KW		 1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
7c0a705e
FC		 1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1172 NUM_BANKS(ADDR_SURF_16_BANK) |
1173 TILE_SPLIT(split_equal_to_row_size));
2cd46ad2 1174 break;
7c0a705e
FC		 1175 case 20:
1176 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1177 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2cd46ad2 1178 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
7c0a705e
FC		 1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2cd46ad2 1182 NUM_BANKS(ADDR_SURF_16_BANK) |
7c0a705e 1183 TILE_SPLIT(split_equal_to_row_size));
2cd46ad2 1184 break;
7c0a705e
FC		 1185 case 21:
1186 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1187 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1188 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1189 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1190 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1193 NUM_BANKS(ADDR_SURF_4_BANK));
1194 break;
1195 case 22:
1196 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1197 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1198 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1199 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1200 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1203 NUM_BANKS(ADDR_SURF_4_BANK));
2cd46ad2 1204 break;
7c0a705e
FC		 1205 case 23:
1206 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1207 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1208 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1209 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2 1210 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
7c0a705e
FC		 1211 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1212 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1213 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1214 break;
7c0a705e
FC		 1215 case 24:
1216 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1217 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1218 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1219 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2 1220 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
7c0a705e
FC		 1221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1223 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1224 break;
7c0a705e
FC		 1225 case 25:
1226 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1227 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1228 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2cd46ad2 1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2cd46ad2 1230 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
7c0a705e
FC		 1231 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1232 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1233 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1234 break;
7c0a705e
FC		 1235 case 26:
1236 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1237 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1238 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1239 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1240 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1241 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1242 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1243 NUM_BANKS(ADDR_SURF_2_BANK));
1244 break;
1245 case 27:
1246 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1247 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1248 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1249 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1250 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1253 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1254 break;
7c0a705e
FC		 1255 case 28:
1256 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1257 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1260 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1261 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1262 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1263 NUM_BANKS(ADDR_SURF_2_BANK));
1264 break;
1265 case 29:
1266 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1267 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1268 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1269 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1270 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1273 NUM_BANKS(ADDR_SURF_2_BANK));
1274 break;
1275 case 30:
1276 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1277 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1278 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1279 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1280 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1281 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1282 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1283 NUM_BANKS(ADDR_SURF_2_BANK));
1284 break;
1285 default:
1286 continue;
2cd46ad2
KW		 1287 }
1288 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
25069e06 1289 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2cd46ad2
KW		 1290 }
1291 } else{
1292
1293 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1294 }
1295
1296}
1297
1298static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1299 u32 sh_num, u32 instance)
1300{
1301 u32 data;
1302
1303 if (instance == 0xffffffff)
25069e06 1304 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2cd46ad2 1305 else
25069e06 1306 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
2cd46ad2
KW		 1307
1308 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
25069e06
TSD		 1309 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1310 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
2cd46ad2 1311 else if (se_num == 0xffffffff)
25069e06
TSD		 1312 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1313 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
2cd46ad2 1314 else if (sh_num == 0xffffffff)
25069e06
TSD		 1315 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1316 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
2cd46ad2 1317 else
25069e06
TSD		 1318 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1319 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1320 WREG32(mmGRBM_GFX_INDEX, data);
2cd46ad2
KW		 1321}
1322
1323static u32 gfx_v6_0_create_bitmask(u32 bit_width)
1324{
142333db 1325 return (u32)(((u64)1 << bit_width) - 1);
2cd46ad2
KW		 1326}
1327
69dd3d2c 1328static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
2cd46ad2
KW		 1329{
1330 u32 data, mask;
1331
69dd3d2c
FC		 1332 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1333 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
2cd46ad2 1334
69dd3d2c 1335 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
2cd46ad2 1336
69dd3d2c
FC		 1337 mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_backends_per_se/
1338 adev->gfx.config.max_sh_per_se);
2cd46ad2 1339
69dd3d2c 1340 return ~data & mask;
2cd46ad2
KW		 1341}
1342
865ab832
HR		 1343static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1344{
1345 switch (adev->asic_type) {
1346 case CHIP_TAHITI:
1347 case CHIP_PITCAIRN:
25069e06
TSD		 1348 *rconf |=
1349 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1350 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1351 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1352 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1353 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1354 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1355 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
865ab832
HR		 1356 break;
1357 case CHIP_VERDE:
25069e06
TSD		 1358 *rconf |=
1359 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1360 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1361 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
865ab832
HR		 1362 break;
1363 case CHIP_OLAND:
25069e06 1364 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
865ab832
HR		 1365 break;
1366 case CHIP_HAINAN:
1367 *rconf |= 0x0;
1368 break;
1369 default:
1370 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1371 break;
1372 }
1373}
1374
1375static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1376 u32 raster_config, unsigned rb_mask,
1377 unsigned num_rb)
1378{
1379 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1380 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1381 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1382 unsigned rb_per_se = num_rb / num_se;
1383 unsigned se_mask[4];
1384 unsigned se;
1385
1386 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1387 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1388 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1389 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1390
1391 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1392 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1393 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1394
1395 for (se = 0; se < num_se; se++) {
1396 unsigned raster_config_se = raster_config;
1397 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1398 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1399 int idx = (se / 2) * 2;
1400
1401 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
25069e06 1402 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
865ab832
HR		 1403
1404 if (!se_mask[idx]) {
25069e06 1405 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
865ab832 1406 } else {
25069e06 1407 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
865ab832
HR		 1408 }
1409 }
1410
1411 pkr0_mask &= rb_mask;
1412 pkr1_mask &= rb_mask;
1413 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
25069e06 1414 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
865ab832
HR		 1415
1416 if (!pkr0_mask) {
25069e06 1417 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
865ab832 1418 } else {
25069e06 1419 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
865ab832
HR		 1420 }
1421 }
1422
1423 if (rb_per_se >= 2) {
1424 unsigned rb0_mask = 1 << (se * rb_per_se);
1425 unsigned rb1_mask = rb0_mask << 1;
1426
1427 rb0_mask &= rb_mask;
1428 rb1_mask &= rb_mask;
1429 if (!rb0_mask || !rb1_mask) {
25069e06 1430 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
865ab832
HR		 1431
1432 if (!rb0_mask) {
1433 raster_config_se |=
25069e06 1434 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
865ab832
HR		 1435 } else {
1436 raster_config_se |=
25069e06 1437 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
865ab832
HR		 1438 }
1439 }
1440
1441 if (rb_per_se > 2) {
1442 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1443 rb1_mask = rb0_mask << 1;
1444 rb0_mask &= rb_mask;
1445 rb1_mask &= rb_mask;
1446 if (!rb0_mask || !rb1_mask) {
25069e06 1447 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
865ab832
HR		 1448
1449 if (!rb0_mask) {
1450 raster_config_se |=
25069e06 1451 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
865ab832
HR		 1452 } else {
1453 raster_config_se |=
25069e06 1454 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
865ab832
HR		 1455 }
1456 }
1457 }
1458 }
1459
1460 /* GRBM_GFX_INDEX has a different offset on SI */
1461 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
25069e06 1462 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
865ab832
HR		 1463 }
1464
1465 /* GRBM_GFX_INDEX has a different offset on SI */
1466 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1467}
1468
69dd3d2c 1469static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
2cd46ad2
KW		 1470{
1471 int i, j;
69dd3d2c
FC		 1472 u32 data;
1473 u32 raster_config = 0;
1474 u32 active_rbs = 0;
1475 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1476 adev->gfx.config.max_sh_per_se;
865ab832 1477 unsigned num_rb_pipes;
2cd46ad2 1478
deca1d1f 1479 mutex_lock(&adev->grbm_idx_mutex);
69dd3d2c
FC		 1480 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1481 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2cd46ad2 1482 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
69dd3d2c
FC		 1483 data = gfx_v6_0_get_rb_active_bitmap(adev);
1484 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1485 rb_bitmap_width_per_sh);
2cd46ad2
KW		 1486 }
1487 }
1488 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1489
69dd3d2c
FC		 1490 adev->gfx.config.backend_enable_mask = active_rbs;
1491 adev->gfx.config.num_rbs = hweight32(active_rbs);
2cd46ad2 1492
865ab832
HR		 1493 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1494 adev->gfx.config.max_shader_engines, 16);
1495
69dd3d2c
FC		 1496 gfx_v6_0_raster_config(adev, &raster_config);
1497
1498 if (!adev->gfx.config.backend_enable_mask ||
1499 adev->gfx.config.num_rbs >= num_rb_pipes) {
1500 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1501 } else {
1502 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1503 adev->gfx.config.backend_enable_mask,
1504 num_rb_pipes);
1505 }
1506
1507 /* cache the values for userspace */
1508 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1509 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1510 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1511 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1512 RREG32(mmCC_RB_BACKEND_DISABLE);
1513 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1514 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1515 adev->gfx.config.rb_config[i][j].raster_config =
1516 RREG32(mmPA_SC_RASTER_CONFIG);
2cd46ad2 1517 }
2cd46ad2
KW		 1518 }
1519 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 1520 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1521}
1522/*
1523static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
1524{
1525}
1526*/
1527
375d6f70
FC		 1528static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1529 u32 bitmap)
2cd46ad2 1530{
375d6f70 1531 u32 data;
2cd46ad2 1532
375d6f70
FC		 1533 if (!bitmap)
1534 return;
2cd46ad2 1535
375d6f70
FC		 1536 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1537 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
2cd46ad2 1538
375d6f70
FC		 1539 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1540}
2cd46ad2 1541
375d6f70
FC		 1542static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1543{
1544 u32 data, mask;
1545
1546 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1547 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1548
1549 mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
1550 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
2cd46ad2
KW		 1551}
1552
1553
c5dc14fb 1554static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
2cd46ad2
KW		 1555{
1556 int i, j, k;
1557 u32 data, mask;
1558 u32 active_cu = 0;
1559
deca1d1f 1560 mutex_lock(&adev->grbm_idx_mutex);
c5dc14fb
FC		 1561 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1562 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2cd46ad2 1563 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
25069e06 1564 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
375d6f70 1565 active_cu = gfx_v6_0_get_cu_enabled(adev);
2cd46ad2
KW		 1566
1567 mask = 1;
1568 for (k = 0; k < 16; k++) {
1569 mask <<= k;
1570 if (active_cu & mask) {
1571 data &= ~mask;
25069e06 1572 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
2cd46ad2
KW		 1573 break;
1574 }
1575 }
1576 }
1577 }
1578 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 1579 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1580}
1581
1582static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1583{
1584 u32 gb_addr_config = 0;
1585 u32 mc_shared_chmap, mc_arb_ramcfg;
1586 u32 sx_debug_1;
1587 u32 hdp_host_path_cntl;
1588 u32 tmp;
1589
1590 switch (adev->asic_type) {
1591 case CHIP_TAHITI:
1592 adev->gfx.config.max_shader_engines = 2;
1593 adev->gfx.config.max_tile_pipes = 12;
1594 adev->gfx.config.max_cu_per_sh = 8;
1595 adev->gfx.config.max_sh_per_se = 2;
1596 adev->gfx.config.max_backends_per_se = 4;
1597 adev->gfx.config.max_texture_channel_caches = 12;
1598 adev->gfx.config.max_gprs = 256;
1599 adev->gfx.config.max_gs_threads = 32;
1600 adev->gfx.config.max_hw_contexts = 8;
1601
1602 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1603 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1604 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1605 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1606 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1607 break;
1608 case CHIP_PITCAIRN:
1609 adev->gfx.config.max_shader_engines = 2;
1610 adev->gfx.config.max_tile_pipes = 8;
1611 adev->gfx.config.max_cu_per_sh = 5;
1612 adev->gfx.config.max_sh_per_se = 2;
1613 adev->gfx.config.max_backends_per_se = 4;
1614 adev->gfx.config.max_texture_channel_caches = 8;
1615 adev->gfx.config.max_gprs = 256;
1616 adev->gfx.config.max_gs_threads = 32;
1617 adev->gfx.config.max_hw_contexts = 8;
1618
1619 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1620 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1621 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1622 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1623 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1624 break;
2cd46ad2
KW		 1625 case CHIP_VERDE:
1626 adev->gfx.config.max_shader_engines = 1;
1627 adev->gfx.config.max_tile_pipes = 4;
1628 adev->gfx.config.max_cu_per_sh = 5;
1629 adev->gfx.config.max_sh_per_se = 2;
1630 adev->gfx.config.max_backends_per_se = 4;
1631 adev->gfx.config.max_texture_channel_caches = 4;
1632 adev->gfx.config.max_gprs = 256;
1633 adev->gfx.config.max_gs_threads = 32;
1634 adev->gfx.config.max_hw_contexts = 8;
1635
1636 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1637 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1638 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1639 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1640 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1641 break;
1642 case CHIP_OLAND:
1643 adev->gfx.config.max_shader_engines = 1;
1644 adev->gfx.config.max_tile_pipes = 4;
1645 adev->gfx.config.max_cu_per_sh = 6;
1646 adev->gfx.config.max_sh_per_se = 1;
1647 adev->gfx.config.max_backends_per_se = 2;
1648 adev->gfx.config.max_texture_channel_caches = 4;
1649 adev->gfx.config.max_gprs = 256;
1650 adev->gfx.config.max_gs_threads = 16;
1651 adev->gfx.config.max_hw_contexts = 8;
1652
1653 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1654 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1655 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1656 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1657 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1658 break;
1659 case CHIP_HAINAN:
1660 adev->gfx.config.max_shader_engines = 1;
1661 adev->gfx.config.max_tile_pipes = 4;
1662 adev->gfx.config.max_cu_per_sh = 5;
1663 adev->gfx.config.max_sh_per_se = 1;
1664 adev->gfx.config.max_backends_per_se = 1;
1665 adev->gfx.config.max_texture_channel_caches = 2;
1666 adev->gfx.config.max_gprs = 256;
1667 adev->gfx.config.max_gs_threads = 16;
1668 adev->gfx.config.max_hw_contexts = 8;
1669
1670 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1671 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1672 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1673 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1674 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1675 break;
1676 default:
1677 BUG();
1678 break;
1679 }
1680
25069e06
TSD		 1681 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1682 WREG32(mmSRBM_INT_CNTL, 1);
1683 WREG32(mmSRBM_INT_ACK, 1);
2cd46ad2 1684
25069e06 1685 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
2cd46ad2 1686
25069e06
TSD		 1687 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1688 mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2cd46ad2
KW		 1689
1690 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1691 adev->gfx.config.mem_max_burst_length_bytes = 256;
25069e06 1692 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
2cd46ad2
KW		 1693 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1694 if (adev->gfx.config.mem_row_size_in_kb > 4)
1695 adev->gfx.config.mem_row_size_in_kb = 4;
1696 adev->gfx.config.shader_engine_tile_size = 32;
1697 adev->gfx.config.num_gpus = 1;
1698 adev->gfx.config.multi_gpu_tile_size = 64;
1699
25069e06 1700 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
2cd46ad2
KW		 1701 switch (adev->gfx.config.mem_row_size_in_kb) {
1702 case 1:
1703 default:
25069e06 1704 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
2cd46ad2
KW		 1705 break;
1706 case 2:
25069e06 1707 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
2cd46ad2
KW		 1708 break;
1709 case 4:
25069e06 1710 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
2cd46ad2
KW		 1711 break;
1712 }
0d09a096
FC		 1713 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1714 if (adev->gfx.config.max_shader_engines == 2)
1715 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
2cd46ad2
KW		 1716 adev->gfx.config.gb_addr_config = gb_addr_config;
1717
25069e06
TSD		 1718 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1719 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1720 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1721 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1722 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1723 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1724
2cd46ad2
KW		 1725#if 0
1726 if (adev->has_uvd) {
25069e06
TSD		 1727 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1728 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1729 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2cd46ad2
KW		 1730 }
1731#endif
1732 gfx_v6_0_tiling_mode_table_init(adev);
1733
69dd3d2c 1734 gfx_v6_0_setup_rb(adev);
2cd46ad2 1735
c5dc14fb 1736 gfx_v6_0_setup_spi(adev);
2cd46ad2
KW		 1737
1738 gfx_v6_0_get_cu_info(adev);
1739
25069e06
TSD		 1740 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1741 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1742 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1743 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
2cd46ad2 1744
25069e06
TSD		 1745 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1746 WREG32(mmSX_DEBUG_1, sx_debug_1);
2cd46ad2 1747
25069e06 1748 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
2cd46ad2 1749
25069e06
TSD		 1750 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1751 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1752 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1753 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
2cd46ad2 1754
25069e06
TSD		 1755 WREG32(mmVGT_NUM_INSTANCES, 1);
1756 WREG32(mmCP_PERFMON_CNTL, 0);
1757 WREG32(mmSQ_CONFIG, 0);
1758 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1759 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
2cd46ad2 1760
25069e06
TSD		 1761 WREG32(mmVGT_CACHE_INVALIDATION,
1762 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1763 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2cd46ad2 1764
25069e06
TSD		 1765 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1766 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2cd46ad2 1767
25069e06
TSD		 1768 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1769 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1770 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1771 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1772 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1773 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1774 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1775 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
2cd46ad2 1776
25069e06
TSD		 1777 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1778 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2cd46ad2 1779
25069e06
TSD		 1780 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1781 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2cd46ad2
KW		 1782
1783 udelay(50);
2cd46ad2
KW		 1784}
1785
1786
1787static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1788{
2cd46ad2 1789 adev->gfx.scratch.num_reg = 7;
25069e06 1790 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
50261151 1791 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
2cd46ad2
KW		 1792}
1793
1794static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1795{
1796 struct amdgpu_device *adev = ring->adev;
1797 uint32_t scratch;
1798 uint32_t tmp = 0;
1799 unsigned i;
1800 int r;
1801
1802 r = amdgpu_gfx_scratch_get(adev, &scratch);
1803 if (r) {
1804 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1805 return r;
1806 }
1807 WREG32(scratch, 0xCAFEDEAD);
1808
1809 r = amdgpu_ring_alloc(ring, 3);
1810 if (r) {
1811 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1812 amdgpu_gfx_scratch_free(adev, scratch);
1813 return r;
1814 }
1815 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1816 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1817 amdgpu_ring_write(ring, 0xDEADBEEF);
1818 amdgpu_ring_commit(ring);
1819
1820 for (i = 0; i < adev->usec_timeout; i++) {
1821 tmp = RREG32(scratch);
1822 if (tmp == 0xDEADBEEF)
1823 break;
1824 DRM_UDELAY(1);
1825 }
1826 if (i < adev->usec_timeout) {
1827 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1828 } else {
1829 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1830 ring->idx, scratch, tmp);
1831 r = -EINVAL;
1832 }
1833 amdgpu_gfx_scratch_free(adev, scratch);
1834 return r;
1835}
1836
1837static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1838{
1839 /* flush hdp cache */
1840 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1841 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1842 WRITE_DATA_DST_SEL(0)));
25069e06 1843 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
2cd46ad2
KW		 1844 amdgpu_ring_write(ring, 0);
1845 amdgpu_ring_write(ring, 0x1);
1846}
1847
45682886
ML		 1848static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1849{
1850 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1851 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1852 EVENT_INDEX(0));
1853}
1854
2cd46ad2
KW		 1855/**
1856 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1857 *
1858 * @adev: amdgpu_device pointer
1859 * @ridx: amdgpu ring index
1860 *
1861 * Emits an hdp invalidate on the cp.
1862 */
1863static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1864{
1865 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1866 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1867 WRITE_DATA_DST_SEL(0)));
25069e06 1868 amdgpu_ring_write(ring, mmHDP_DEBUG0);
2cd46ad2
KW		 1869 amdgpu_ring_write(ring, 0);
1870 amdgpu_ring_write(ring, 0x1);
1871}
1872
668f52c3
AD		 1873static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1874 u64 seq, unsigned flags)
2cd46ad2
KW		 1875{
1876 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1877 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1878 /* flush read cache over gart */
1879 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
25069e06 1880 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
2cd46ad2
KW		 1881 amdgpu_ring_write(ring, 0);
1882 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1883 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1884 PACKET3_TC_ACTION_ENA |
1885 PACKET3_SH_KCACHE_ACTION_ENA |
1886 PACKET3_SH_ICACHE_ACTION_ENA);
1887 amdgpu_ring_write(ring, 0xFFFFFFFF);
1888 amdgpu_ring_write(ring, 0);
1889 amdgpu_ring_write(ring, 10); /* poll interval */
1890 /* EVENT_WRITE_EOP - flush caches, send int */
1891 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1892 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1893 amdgpu_ring_write(ring, addr & 0xfffffffc);
1894 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
25069e06
TSD		 1895 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1896 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
2cd46ad2
KW		 1897 amdgpu_ring_write(ring, lower_32_bits(seq));
1898 amdgpu_ring_write(ring, upper_32_bits(seq));
1899}
1900
668f52c3
AD		 1901static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1902 struct amdgpu_ib *ib,
1903 unsigned vm_id, bool ctx_switch)
2cd46ad2
KW		 1904{
1905 u32 header, control = 0;
1906
1907 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1908 if (ctx_switch) {
1909 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1910 amdgpu_ring_write(ring, 0);
1911 }
1912
1913 if (ib->flags & AMDGPU_IB_FLAG_CE)
1914 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1915 else
1916 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1917
1918 control |= ib->length_dw | (vm_id << 24);
1919
1920 amdgpu_ring_write(ring, header);
1921 amdgpu_ring_write(ring,
1922#ifdef __BIG_ENDIAN
1923 (2 << 0) |
1924#endif
1925 (ib->gpu_addr & 0xFFFFFFFC));
1926 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1927 amdgpu_ring_write(ring, control);
1928}
1929
2cd46ad2
KW		 1930/**
1931 * gfx_v6_0_ring_test_ib - basic ring IB test
1932 *
1933 * @ring: amdgpu_ring structure holding ring information
1934 *
1935 * Allocate an IB and execute it on the gfx ring (SI).
1936 * Provides a basic gfx ring test to verify that IBs are working.
1937 * Returns 0 on success, error on failure.
1938 */
1939static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1940{
1941 struct amdgpu_device *adev = ring->adev;
1942 struct amdgpu_ib ib;
f54d1867 1943 struct dma_fence *f = NULL;
2cd46ad2
KW		 1944 uint32_t scratch;
1945 uint32_t tmp = 0;
1946 long r;
1947
1948 r = amdgpu_gfx_scratch_get(adev, &scratch);
1949 if (r) {
1950 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1951 return r;
1952 }
1953 WREG32(scratch, 0xCAFEDEAD);
1954 memset(&ib, 0, sizeof(ib));
1955 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1956 if (r) {
1957 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1958 goto err1;
1959 }
1960 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1961 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1962 ib.ptr[2] = 0xDEADBEEF;
1963 ib.length_dw = 3;
1964
50ddc75e 1965 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2cd46ad2
KW		 1966 if (r)
1967 goto err2;
1968
f54d1867 1969 r = dma_fence_wait_timeout(f, false, timeout);
2cd46ad2
KW		 1970 if (r == 0) {
1971 DRM_ERROR("amdgpu: IB test timed out\n");
1972 r = -ETIMEDOUT;
1973 goto err2;
1974 } else if (r < 0) {
1975 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1976 goto err2;
1977 }
1978 tmp = RREG32(scratch);
1979 if (tmp == 0xDEADBEEF) {
1980 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1981 r = 0;
1982 } else {
1983 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1984 scratch, tmp);
1985 r = -EINVAL;
1986 }
1987
1988err2:
1989 amdgpu_ib_free(adev, &ib, NULL);
f54d1867 1990 dma_fence_put(f);
2cd46ad2
KW		 1991err1:
1992 amdgpu_gfx_scratch_free(adev, scratch);
1993 return r;
1994}
1995
1996static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1997{
1998 int i;
25069e06
TSD		 1999 if (enable) {
2000 WREG32(mmCP_ME_CNTL, 0);
2001 } else {
2002 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
2003 CP_ME_CNTL__PFP_HALT_MASK |
2004 CP_ME_CNTL__CE_HALT_MASK));
2005 WREG32(mmSCRATCH_UMSK, 0);
2cd46ad2
KW		 2006 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2007 adev->gfx.gfx_ring[i].ready = false;
2008 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2009 adev->gfx.compute_ring[i].ready = false;
2010 }
2011 udelay(50);
2012}
2013
2014static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2015{
2016 unsigned i;
2017 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2018 const struct gfx_firmware_header_v1_0 *ce_hdr;
2019 const struct gfx_firmware_header_v1_0 *me_hdr;
2020 const __le32 *fw_data;
2021 u32 fw_size;
2022
2023 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2024 return -EINVAL;
2025
2026 gfx_v6_0_cp_gfx_enable(adev, false);
2027 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2028 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2029 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2030
2031 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2032 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2033 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2034
2035 /* PFP */
2036 fw_data = (const __le32 *)
2037 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2038 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
25069e06 2039 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2cd46ad2 2040 for (i = 0; i < fw_size; i++)
25069e06
TSD		 2041 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2042 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2cd46ad2
KW		 2043
2044 /* CE */
2045 fw_data = (const __le32 *)
2046 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2047 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
25069e06 2048 WREG32(mmCP_CE_UCODE_ADDR, 0);
2cd46ad2 2049 for (i = 0; i < fw_size; i++)
25069e06
TSD		 2050 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2051 WREG32(mmCP_CE_UCODE_ADDR, 0);
2cd46ad2
KW		 2052
2053 /* ME */
2054 fw_data = (const __be32 *)
2055 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2056 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
25069e06 2057 WREG32(mmCP_ME_RAM_WADDR, 0);
2cd46ad2 2058 for (i = 0; i < fw_size; i++)
25069e06
TSD		 2059 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2060 WREG32(mmCP_ME_RAM_WADDR, 0);
2cd46ad2 2061
25069e06
TSD		 2062 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2063 WREG32(mmCP_CE_UCODE_ADDR, 0);
2064 WREG32(mmCP_ME_RAM_WADDR, 0);
2065 WREG32(mmCP_ME_RAM_RADDR, 0);
2cd46ad2
KW		 2066 return 0;
2067}
2068
2069static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2070{
2071 const struct cs_section_def *sect = NULL;
2072 const struct cs_extent_def *ext = NULL;
2073 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2074 int r, i;
2075
2076 r = amdgpu_ring_alloc(ring, 7 + 4);
2077 if (r) {
2078 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2079 return r;
2080 }
2081 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2082 amdgpu_ring_write(ring, 0x1);
2083 amdgpu_ring_write(ring, 0x0);
2084 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2085 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2086 amdgpu_ring_write(ring, 0);
2087 amdgpu_ring_write(ring, 0);
2088
2089 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2090 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2091 amdgpu_ring_write(ring, 0xc000);
2092 amdgpu_ring_write(ring, 0xe000);
2093 amdgpu_ring_commit(ring);
2094
2095 gfx_v6_0_cp_gfx_enable(adev, true);
2096
2097 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2098 if (r) {
2099 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2100 return r;
2101 }
2102
2103 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2104 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2105
2106 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2107 for (ext = sect->section; ext->extent != NULL; ++ext) {
2108 if (sect->id == SECT_CONTEXT) {
2109 amdgpu_ring_write(ring,
2110 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2111 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2112 for (i = 0; i < ext->reg_count; i++)
2113 amdgpu_ring_write(ring, ext->extent[i]);
2114 }
2115 }
2116 }
2117
2118 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2119 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2120
2121 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2122 amdgpu_ring_write(ring, 0);
2123
2124 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2125 amdgpu_ring_write(ring, 0x00000316);
2126 amdgpu_ring_write(ring, 0x0000000e);
2127 amdgpu_ring_write(ring, 0x00000010);
2128
2129 amdgpu_ring_commit(ring);
2130
2131 return 0;
2132}
2133
2134static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2135{
2136 struct amdgpu_ring *ring;
2137 u32 tmp;
2138 u32 rb_bufsz;
2139 int r;
2140 u64 rptr_addr;
2141
25069e06
TSD		 2142 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2143 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2cd46ad2
KW		 2144
2145 /* Set the write pointer delay */
25069e06 2146 WREG32(mmCP_RB_WPTR_DELAY, 0);
2cd46ad2 2147
25069e06
TSD		 2148 WREG32(mmCP_DEBUG, 0);
2149 WREG32(mmSCRATCH_ADDR, 0);
2cd46ad2
KW		 2150
2151 /* ring 0 - compute and gfx */
2152 /* Set ring buffer size */
2153 ring = &adev->gfx.gfx_ring[0];
2154 rb_bufsz = order_base_2(ring->ring_size / 8);
2155 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2156
2157#ifdef __BIG_ENDIAN
2158 tmp |= BUF_SWAP_32BIT;
2159#endif
25069e06 2160 WREG32(mmCP_RB0_CNTL, tmp);
2cd46ad2
KW		 2161
2162 /* Initialize the ring buffer's read and write pointers */
25069e06 2163 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2cd46ad2 2164 ring->wptr = 0;
25069e06 2165 WREG32(mmCP_RB0_WPTR, ring->wptr);
2cd46ad2
KW		 2166
2167 /* set the wb address whether it's enabled or not */
2168 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
25069e06
TSD		 2169 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2170 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2cd46ad2 2171
25069e06 2172 WREG32(mmSCRATCH_UMSK, 0);
2cd46ad2
KW		 2173
2174 mdelay(1);
25069e06 2175 WREG32(mmCP_RB0_CNTL, tmp);
2cd46ad2 2176
25069e06 2177 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2cd46ad2
KW		 2178
2179 /* start the rings */
2180 gfx_v6_0_cp_gfx_start(adev);
2181 ring->ready = true;
2182 r = amdgpu_ring_test_ring(ring);
2183 if (r) {
2184 ring->ready = false;
2185 return r;
2186 }
2187
2188 return 0;
2189}
2190
6f924e20 2191static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2cd46ad2 2192{
4aeacf0f 2193 return ring->adev->wb.wb[ring->rptr_offs];
2cd46ad2
KW		 2194}
2195
832c6ef7 2196static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2cd46ad2
KW		 2197{
2198 struct amdgpu_device *adev = ring->adev;
2cd46ad2 2199
832c6ef7 2200 if (ring == &adev->gfx.gfx_ring[0])
25069e06 2201 return RREG32(mmCP_RB0_WPTR);
832c6ef7 2202 else if (ring == &adev->gfx.compute_ring[0])
25069e06 2203 return RREG32(mmCP_RB1_WPTR);
832c6ef7 2204 else if (ring == &adev->gfx.compute_ring[1])
25069e06 2205 return RREG32(mmCP_RB2_WPTR);
832c6ef7
TSD		 2206 else
2207 BUG();
2cd46ad2
KW		 2208}
2209
2210static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2211{
2212 struct amdgpu_device *adev = ring->adev;
2213
25069e06
TSD		 2214 WREG32(mmCP_RB0_WPTR, ring->wptr);
2215 (void)RREG32(mmCP_RB0_WPTR);
2cd46ad2
KW		 2216}
2217
2cd46ad2
KW		 2218static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2219{
2220 struct amdgpu_device *adev = ring->adev;
2221
2222 if (ring == &adev->gfx.compute_ring[0]) {
25069e06
TSD		 2223 WREG32(mmCP_RB1_WPTR, ring->wptr);
2224 (void)RREG32(mmCP_RB1_WPTR);
2cd46ad2 2225 } else if (ring == &adev->gfx.compute_ring[1]) {
25069e06
TSD		 2226 WREG32(mmCP_RB2_WPTR, ring->wptr);
2227 (void)RREG32(mmCP_RB2_WPTR);
2cd46ad2
KW		 2228 } else {
2229 BUG();
2230 }
2231
2232}
2233
2cd46ad2
KW		 2234static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2235{
2236 struct amdgpu_ring *ring;
2237 u32 tmp;
2238 u32 rb_bufsz;
25069e06 2239 int i, r;
2cd46ad2
KW		 2240 u64 rptr_addr;
2241
2242 /* ring1 - compute only */
2243 /* Set ring buffer size */
2244
2245 ring = &adev->gfx.compute_ring[0];
2246 rb_bufsz = order_base_2(ring->ring_size / 8);
2247 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2248#ifdef __BIG_ENDIAN
2249 tmp |= BUF_SWAP_32BIT;
2250#endif
25069e06 2251 WREG32(mmCP_RB1_CNTL, tmp);
2cd46ad2 2252
25069e06 2253 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2cd46ad2 2254 ring->wptr = 0;
25069e06 2255 WREG32(mmCP_RB1_WPTR, ring->wptr);
2cd46ad2 2256
2cd46ad2 2257 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
25069e06
TSD		 2258 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2259 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2cd46ad2
KW		 2260
2261 mdelay(1);
25069e06
TSD		 2262 WREG32(mmCP_RB1_CNTL, tmp);
2263 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2cd46ad2
KW		 2264
2265 ring = &adev->gfx.compute_ring[1];
2266 rb_bufsz = order_base_2(ring->ring_size / 8);
2267 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2268#ifdef __BIG_ENDIAN
2269 tmp |= BUF_SWAP_32BIT;
2270#endif
25069e06 2271 WREG32(mmCP_RB2_CNTL, tmp);
2cd46ad2 2272
25069e06 2273 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2cd46ad2 2274 ring->wptr = 0;
25069e06 2275 WREG32(mmCP_RB2_WPTR, ring->wptr);
2cd46ad2 2276 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
25069e06
TSD		 2277 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2278 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2cd46ad2
KW		 2279
2280 mdelay(1);
25069e06
TSD		 2281 WREG32(mmCP_RB2_CNTL, tmp);
2282 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2cd46ad2 2283
25069e06
TSD		 2284 adev->gfx.compute_ring[0].ready = false;
2285 adev->gfx.compute_ring[1].ready = false;
2cd46ad2 2286
25069e06
TSD		 2287 for (i = 0; i < 2; i++) {
2288 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2289 if (r)
2290 return r;
2291 adev->gfx.compute_ring[i].ready = true;
2cd46ad2
KW		 2292 }
2293
2294 return 0;
2295}
2296
2297static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2298{
2299 gfx_v6_0_cp_gfx_enable(adev, enable);
2300}
2301
2302static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2303{
4aeacf0f 2304 return gfx_v6_0_cp_gfx_load_microcode(adev);
2cd46ad2
KW		 2305}
2306
2307static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2308 bool enable)
45682886 2309{
25069e06 2310 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2
KW		 2311 u32 mask;
2312 int i;
2313
2314 if (enable)
25069e06
TSD		 2315 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2316 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2cd46ad2 2317 else
25069e06
TSD		 2318 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2319 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2320 WREG32(mmCP_INT_CNTL_RING0, tmp);
2cd46ad2
KW		 2321
2322 if (!enable) {
2323 /* read a gfx register */
25069e06 2324 tmp = RREG32(mmDB_DEPTH_INFO);
2cd46ad2
KW		 2325
2326 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2327 for (i = 0; i < adev->usec_timeout; i++) {
25069e06 2328 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2cd46ad2
KW		 2329 break;
2330 udelay(1);
2331 }
2332 }
2333}
2334
2335static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2336{
2337 int r;
2338
2339 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2340
2341 r = gfx_v6_0_cp_load_microcode(adev);
2342 if (r)
2343 return r;
2344
2345 r = gfx_v6_0_cp_gfx_resume(adev);
2346 if (r)
2347 return r;
2348 r = gfx_v6_0_cp_compute_resume(adev);
2349 if (r)
2350 return r;
2351
2352 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2353
2354 return 0;
2355}
2356
2357static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2358{
21cd942e 2359 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2cd46ad2
KW		 2360 uint32_t seq = ring->fence_drv.sync_seq;
2361 uint64_t addr = ring->fence_drv.gpu_addr;
2362
2363 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2364 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2365 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2366 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2367 amdgpu_ring_write(ring, addr & 0xfffffffc);
2368 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2369 amdgpu_ring_write(ring, seq);
2370 amdgpu_ring_write(ring, 0xffffffff);
2371 amdgpu_ring_write(ring, 4); /* poll interval */
2372
2373 if (usepfp) {
2374 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2375 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2376 amdgpu_ring_write(ring, 0);
2377 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2378 amdgpu_ring_write(ring, 0);
2379 }
2380}
2381
2382static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2383 unsigned vm_id, uint64_t pd_addr)
2384{
21cd942e 2385 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2cd46ad2
KW		 2386
2387 /* write new base address */
2388 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2389 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2390 WRITE_DATA_DST_SEL(0)));
2391 if (vm_id < 8) {
25069e06 2392 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
2cd46ad2 2393 } else {
25069e06 2394 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
2cd46ad2
KW		 2395 }
2396 amdgpu_ring_write(ring, 0);
2397 amdgpu_ring_write(ring, pd_addr >> 12);
2398
2399 /* bits 0-15 are the VM contexts0-15 */
2400 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2401 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2402 WRITE_DATA_DST_SEL(0)));
25069e06 2403 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2cd46ad2
KW		 2404 amdgpu_ring_write(ring, 0);
2405 amdgpu_ring_write(ring, 1 << vm_id);
2406
2407 /* wait for the invalidate to complete */
2408 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2409 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2410 WAIT_REG_MEM_ENGINE(0))); /* me */
25069e06 2411 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2cd46ad2
KW		 2412 amdgpu_ring_write(ring, 0);
2413 amdgpu_ring_write(ring, 0); /* ref */
2414 amdgpu_ring_write(ring, 0); /* mask */
2415 amdgpu_ring_write(ring, 0x20); /* poll interval */
2416
2417 if (usepfp) {
2418 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2419 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2420 amdgpu_ring_write(ring, 0x0);
2421
2422 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2423 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2424 amdgpu_ring_write(ring, 0);
2425 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2426 amdgpu_ring_write(ring, 0);
2427 }
2428}
2429
2430
2431static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2432{
2433 int r;
2434
2435 if (adev->gfx.rlc.save_restore_obj) {
2436 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2437 if (unlikely(r != 0))
2438 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
2439 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
2440 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2441
2442 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
2443 adev->gfx.rlc.save_restore_obj = NULL;
2444 }
2445
2446 if (adev->gfx.rlc.clear_state_obj) {
2447 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2448 if (unlikely(r != 0))
2449 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
2450 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
2451 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2452
2453 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
2454 adev->gfx.rlc.clear_state_obj = NULL;
2455 }
2456
2457 if (adev->gfx.rlc.cp_table_obj) {
2458 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
2459 if (unlikely(r != 0))
2460 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
2461 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
2462 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
2463
2464 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
2465 adev->gfx.rlc.cp_table_obj = NULL;
2466 }
2467}
2468
2469static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2470{
2471 const u32 *src_ptr;
2472 volatile u32 *dst_ptr;
2473 u32 dws, i;
2474 u64 reg_list_mc_addr;
2475 const struct cs_section_def *cs_data;
2476 int r;
2477
2478 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2479 adev->gfx.rlc.reg_list_size =
2480 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2481
2482 adev->gfx.rlc.cs_data = si_cs_data;
2483 src_ptr = adev->gfx.rlc.reg_list;
2484 dws = adev->gfx.rlc.reg_list_size;
2485 cs_data = adev->gfx.rlc.cs_data;
2486
2487 if (src_ptr) {
2488 /* save restore block */
2489 if (adev->gfx.rlc.save_restore_obj == NULL) {
2cd46ad2
KW		 2490 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2491 AMDGPU_GEM_DOMAIN_VRAM,
2492 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2493 NULL, NULL,
2494 &adev->gfx.rlc.save_restore_obj);
2495
2496 if (r) {
2497 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
2498 return r;
2499 }
2500 }
2501
2502 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2503 if (unlikely(r != 0)) {
2504 gfx_v6_0_rlc_fini(adev);
2505 return r;
2506 }
2507 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
2508 &adev->gfx.rlc.save_restore_gpu_addr);
2509 if (r) {
2510 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2511 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
2512 gfx_v6_0_rlc_fini(adev);
2513 return r;
2514 }
2515
2516 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
2517 if (r) {
2518 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
2519 gfx_v6_0_rlc_fini(adev);
2520 return r;
2521 }
2522 /* write the sr buffer */
2523 dst_ptr = adev->gfx.rlc.sr_ptr;
2524 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2525 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2526 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2527 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2528 }
2529
2530 if (cs_data) {
2531 /* clear state block */
2532 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2533 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2534
2535 if (adev->gfx.rlc.clear_state_obj == NULL) {
2536 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2537 AMDGPU_GEM_DOMAIN_VRAM,
2538 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2539 NULL, NULL,
2540 &adev->gfx.rlc.clear_state_obj);
2541
2542 if (r) {
2543 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2544 gfx_v6_0_rlc_fini(adev);
2545 return r;
2546 }
2547 }
2548 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2549 if (unlikely(r != 0)) {
2550 gfx_v6_0_rlc_fini(adev);
2551 return r;
2552 }
2553 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
2554 &adev->gfx.rlc.clear_state_gpu_addr);
2555 if (r) {
2556 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2557 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
2558 gfx_v6_0_rlc_fini(adev);
2559 return r;
2560 }
2561
2562 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
2563 if (r) {
2564 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
2565 gfx_v6_0_rlc_fini(adev);
2566 return r;
2567 }
2568 /* set up the cs buffer */
2569 dst_ptr = adev->gfx.rlc.cs_ptr;
2570 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2571 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2572 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2573 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2574 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2575 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2576 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2577 }
2578
2579 return 0;
2580}
2581
2582static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2583{
25069e06 2584 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2cd46ad2
KW		 2585
2586 if (!enable) {
2587 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
25069e06 2588 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2cd46ad2 2589 }
2cd46ad2
KW		 2590}
2591
2592static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2593{
2594 int i;
2595
2596 for (i = 0; i < adev->usec_timeout; i++) {
25069e06 2597 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2cd46ad2
KW		 2598 break;
2599 udelay(1);
2600 }
2601
2602 for (i = 0; i < adev->usec_timeout; i++) {
25069e06 2603 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2cd46ad2
KW		 2604 break;
2605 udelay(1);
2606 }
2607}
2608
2609static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2610{
2611 u32 tmp;
2612
25069e06 2613 tmp = RREG32(mmRLC_CNTL);
2cd46ad2 2614 if (tmp != rlc)
25069e06 2615 WREG32(mmRLC_CNTL, rlc);
2cd46ad2
KW		 2616}
2617
2618static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2619{
2620 u32 data, orig;
2621
25069e06 2622 orig = data = RREG32(mmRLC_CNTL);
2cd46ad2 2623
25069e06
TSD		 2624 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2625 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2626 WREG32(mmRLC_CNTL, data);
2cd46ad2
KW		 2627
2628 gfx_v6_0_wait_for_rlc_serdes(adev);
2629 }
2630
2631 return orig;
2632}
2633
2634static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2635{
25069e06 2636 WREG32(mmRLC_CNTL, 0);
2cd46ad2
KW		 2637
2638 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2cd46ad2
KW		 2639 gfx_v6_0_wait_for_rlc_serdes(adev);
2640}
2641
2642static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2643{
25069e06 2644 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2cd46ad2
KW		 2645
2646 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2647
2648 udelay(50);
2649}
2650
2651static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2652{
25069e06 2653 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2cd46ad2 2654 udelay(50);
25069e06 2655 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2cd46ad2
KW		 2656 udelay(50);
2657}
2658
2659static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2660{
2661 u32 tmp;
2662
2663 /* Enable LBPW only for DDR3 */
25069e06 2664 tmp = RREG32(mmMC_SEQ_MISC0);
2cd46ad2
KW		 2665 if ((tmp & 0xF0000000) == 0xB0000000)
2666 return true;
2667 return false;
2668}
25069e06 2669
2cd46ad2
KW		 2670static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2671{
2672}
2673
2674static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2675{
2676 u32 i;
2677 const struct rlc_firmware_header_v1_0 *hdr;
2678 const __le32 *fw_data;
2679 u32 fw_size;
2680
2681
2682 if (!adev->gfx.rlc_fw)
2683 return -EINVAL;
2684
2685 gfx_v6_0_rlc_stop(adev);
2cd46ad2 2686 gfx_v6_0_rlc_reset(adev);
2cd46ad2 2687 gfx_v6_0_init_pg(adev);
2cd46ad2
KW		 2688 gfx_v6_0_init_cg(adev);
2689
25069e06
TSD		 2690 WREG32(mmRLC_RL_BASE, 0);
2691 WREG32(mmRLC_RL_SIZE, 0);
2692 WREG32(mmRLC_LB_CNTL, 0);
2693 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2694 WREG32(mmRLC_LB_CNTR_INIT, 0);
2695 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2cd46ad2 2696
25069e06
TSD		 2697 WREG32(mmRLC_MC_CNTL, 0);
2698 WREG32(mmRLC_UCODE_CNTL, 0);
2cd46ad2
KW		 2699
2700 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2701 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2702 fw_data = (const __le32 *)
2703 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2704
2705 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2706
2707 for (i = 0; i < fw_size; i++) {
25069e06
TSD		 2708 WREG32(mmRLC_UCODE_ADDR, i);
2709 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2cd46ad2 2710 }
25069e06 2711 WREG32(mmRLC_UCODE_ADDR, 0);
2cd46ad2
KW		 2712
2713 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2cd46ad2
KW		 2714 gfx_v6_0_rlc_start(adev);
2715
2716 return 0;
2717}
2718
2719static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2720{
2721 u32 data, orig, tmp;
2722
25069e06 2723 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2cd46ad2
KW		 2724
2725 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2726 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2727
25069e06 2728 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2cd46ad2
KW		 2729
2730 tmp = gfx_v6_0_halt_rlc(adev);
2731
25069e06
TSD		 2732 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2733 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2734 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2cd46ad2
KW		 2735
2736 gfx_v6_0_wait_for_rlc_serdes(adev);
2cd46ad2
KW		 2737 gfx_v6_0_update_rlc(adev, tmp);
2738
25069e06 2739 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2cd46ad2 2740
25069e06 2741 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2cd46ad2
KW		 2742 } else {
2743 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2744
25069e06
TSD		 2745 RREG32(mmCB_CGTT_SCLK_CTRL);
2746 RREG32(mmCB_CGTT_SCLK_CTRL);
2747 RREG32(mmCB_CGTT_SCLK_CTRL);
2748 RREG32(mmCB_CGTT_SCLK_CTRL);
2cd46ad2 2749
25069e06 2750 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2cd46ad2
KW		 2751 }
2752
2753 if (orig != data)
25069e06 2754 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2cd46ad2
KW		 2755
2756}
2757
2758static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2759{
2760
2761 u32 data, orig, tmp = 0;
2762
2763 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
25069e06 2764 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2cd46ad2
KW		 2765 data = 0x96940200;
2766 if (orig != data)
25069e06 2767 WREG32(mmCGTS_SM_CTRL_REG, data);
2cd46ad2
KW		 2768
2769 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
25069e06
TSD		 2770 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2771 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2cd46ad2 2772 if (orig != data)
25069e06 2773 WREG32(mmCP_MEM_SLP_CNTL, data);
2cd46ad2
KW		 2774 }
2775
25069e06 2776 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2cd46ad2
KW		 2777 data &= 0xffffffc0;
2778 if (orig != data)
25069e06 2779 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2cd46ad2
KW		 2780
2781 tmp = gfx_v6_0_halt_rlc(adev);
2782
25069e06
TSD		 2783 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2784 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2785 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2cd46ad2
KW		 2786
2787 gfx_v6_0_update_rlc(adev, tmp);
2788 } else {
25069e06 2789 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2cd46ad2
KW		 2790 data |= 0x00000003;
2791 if (orig != data)
25069e06 2792 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2cd46ad2 2793
25069e06
TSD		 2794 data = RREG32(mmCP_MEM_SLP_CNTL);
2795 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2796 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2797 WREG32(mmCP_MEM_SLP_CNTL, data);
2cd46ad2 2798 }
25069e06
TSD		 2799 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2800 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2cd46ad2 2801 if (orig != data)
25069e06 2802 WREG32(mmCGTS_SM_CTRL_REG, data);
2cd46ad2
KW		 2803
2804 tmp = gfx_v6_0_halt_rlc(adev);
2805
25069e06
TSD		 2806 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2807 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2808 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2cd46ad2
KW		 2809
2810 gfx_v6_0_update_rlc(adev, tmp);
2811 }
2812}
2813/*
2814static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2815 bool enable)
2816{
2817 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2818 if (enable) {
2819 gfx_v6_0_enable_mgcg(adev, true);
2820 gfx_v6_0_enable_cgcg(adev, true);
2821 } else {
2822 gfx_v6_0_enable_cgcg(adev, false);
2823 gfx_v6_0_enable_mgcg(adev, false);
2824 }
2825 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2826}
2827*/
25069e06 2828
2cd46ad2
KW		 2829static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2830 bool enable)
2831{
2832}
2833
2834static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2835 bool enable)
2836{
2837}
2838
2839static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2840{
2841 u32 data, orig;
2842
25069e06 2843 orig = data = RREG32(mmRLC_PG_CNTL);
2cd46ad2
KW		 2844 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2845 data &= ~0x8000;
2846 else
2847 data |= 0x8000;
2848 if (orig != data)
25069e06 2849 WREG32(mmRLC_PG_CNTL, data);
2cd46ad2
KW		 2850}
2851
2852static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2853{
2854}
2855/*
2856static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2857{
2858 const __le32 *fw_data;
2859 volatile u32 *dst_ptr;
2860 int me, i, max_me = 4;
2861 u32 bo_offset = 0;
2862 u32 table_offset, table_size;
2863
2864 if (adev->asic_type == CHIP_KAVERI)
2865 max_me = 5;
2866
2867 if (adev->gfx.rlc.cp_table_ptr == NULL)
2868 return;
2869
2870 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2871 for (me = 0; me < max_me; me++) {
2872 if (me == 0) {
2873 const struct gfx_firmware_header_v1_0 *hdr =
2874 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2875 fw_data = (const __le32 *)
2876 (adev->gfx.ce_fw->data +
2877 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2878 table_offset = le32_to_cpu(hdr->jt_offset);
2879 table_size = le32_to_cpu(hdr->jt_size);
2880 } else if (me == 1) {
2881 const struct gfx_firmware_header_v1_0 *hdr =
2882 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2883 fw_data = (const __le32 *)
2884 (adev->gfx.pfp_fw->data +
2885 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2886 table_offset = le32_to_cpu(hdr->jt_offset);
2887 table_size = le32_to_cpu(hdr->jt_size);
2888 } else if (me == 2) {
2889 const struct gfx_firmware_header_v1_0 *hdr =
2890 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2891 fw_data = (const __le32 *)
2892 (adev->gfx.me_fw->data +
2893 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2894 table_offset = le32_to_cpu(hdr->jt_offset);
2895 table_size = le32_to_cpu(hdr->jt_size);
2896 } else if (me == 3) {
2897 const struct gfx_firmware_header_v1_0 *hdr =
2898 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2899 fw_data = (const __le32 *)
2900 (adev->gfx.mec_fw->data +
2901 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2902 table_offset = le32_to_cpu(hdr->jt_offset);
2903 table_size = le32_to_cpu(hdr->jt_size);
2904 } else {
2905 const struct gfx_firmware_header_v1_0 *hdr =
2906 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2907 fw_data = (const __le32 *)
2908 (adev->gfx.mec2_fw->data +
2909 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2910 table_offset = le32_to_cpu(hdr->jt_offset);
2911 table_size = le32_to_cpu(hdr->jt_size);
2912 }
2913
2914 for (i = 0; i < table_size; i ++) {
2915 dst_ptr[bo_offset + i] =
2916 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2917 }
2918
2919 bo_offset += table_size;
2920 }
2921}
2922*/
2923static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2924 bool enable)
2925{
2cd46ad2 2926 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
25069e06
TSD		 2927 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2928 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2929 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2cd46ad2 2930 } else {
25069e06
TSD		 2931 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2932 (void)RREG32(mmDB_RENDER_CONTROL);
2cd46ad2
KW		 2933 }
2934}
2935
2cd46ad2
KW		 2936static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2937{
375d6f70 2938 u32 tmp;
2cd46ad2 2939
375d6f70 2940 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2cd46ad2 2941
375d6f70
FC		 2942 tmp = RREG32(mmRLC_MAX_PG_CU);
2943 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2944 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2945 WREG32(mmRLC_MAX_PG_CU, tmp);
2cd46ad2
KW		 2946}
2947
2948static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2949 bool enable)
2950{
2951 u32 data, orig;
2952
25069e06 2953 orig = data = RREG32(mmRLC_PG_CNTL);
2cd46ad2 2954 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
25069e06 2955 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2cd46ad2 2956 else
25069e06 2957 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2cd46ad2 2958 if (orig != data)
25069e06 2959 WREG32(mmRLC_PG_CNTL, data);
2cd46ad2
KW		 2960}
2961
2962static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2963 bool enable)
2964{
2965 u32 data, orig;
2966
25069e06 2967 orig = data = RREG32(mmRLC_PG_CNTL);
2cd46ad2 2968 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
25069e06 2969 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2cd46ad2 2970 else
25069e06 2971 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2cd46ad2 2972 if (orig != data)
25069e06 2973 WREG32(mmRLC_PG_CNTL, data);
2cd46ad2
KW		 2974}
2975
2976static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2977{
2978 u32 tmp;
2979
25069e06
TSD		 2980 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2981 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2982 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2cd46ad2 2983
25069e06
TSD		 2984 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2985 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2986 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2987 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2988 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2cd46ad2
KW		 2989}
2990
2991static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2992{
2993 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2994 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2995 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2996}
2997
2998static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2999{
3000 u32 count = 0;
3001 const struct cs_section_def *sect = NULL;
3002 const struct cs_extent_def *ext = NULL;
3003
3004 if (adev->gfx.rlc.cs_data == NULL)
3005 return 0;
3006
3007 /* begin clear state */
3008 count += 2;
3009 /* context control state */
3010 count += 3;
3011
3012 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3013 for (ext = sect->section; ext->extent != NULL; ++ext) {
3014 if (sect->id == SECT_CONTEXT)
3015 count += 2 + ext->reg_count;
3016 else
3017 return 0;
3018 }
3019 }
3020 /* pa_sc_raster_config */
3021 count += 3;
3022 /* end clear state */
3023 count += 2;
3024 /* clear state */
3025 count += 2;
3026
3027 return count;
3028}
3029
3030static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
3031 volatile u32 *buffer)
3032{
3033 u32 count = 0, i;
3034 const struct cs_section_def *sect = NULL;
3035 const struct cs_extent_def *ext = NULL;
3036
3037 if (adev->gfx.rlc.cs_data == NULL)
3038 return;
3039 if (buffer == NULL)
3040 return;
3041
3042 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3043 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2cd46ad2
KW		 3044 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3045 buffer[count++] = cpu_to_le32(0x80000000);
3046 buffer[count++] = cpu_to_le32(0x80000000);
3047
3048 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3049 for (ext = sect->section; ext->extent != NULL; ++ext) {
3050 if (sect->id == SECT_CONTEXT) {
3051 buffer[count++] =
3052 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3053 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
3054 for (i = 0; i < ext->reg_count; i++)
3055 buffer[count++] = cpu_to_le32(ext->extent[i]);
3056 } else {
3057 return;
3058 }
3059 }
3060 }
3061
3062 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
25069e06 3063 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2cd46ad2
KW		 3064
3065 switch (adev->asic_type) {
3066 case CHIP_TAHITI:
3067 case CHIP_PITCAIRN:
3068 buffer[count++] = cpu_to_le32(0x2a00126a);
3069 break;
3070 case CHIP_VERDE:
3071 buffer[count++] = cpu_to_le32(0x0000124a);
3072 break;
3073 case CHIP_OLAND:
3074 buffer[count++] = cpu_to_le32(0x00000082);
3075 break;
3076 case CHIP_HAINAN:
3077 buffer[count++] = cpu_to_le32(0x00000000);
3078 break;
3079 default:
3080 buffer[count++] = cpu_to_le32(0x00000000);
3081 break;
3082 }
3083
3084 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3085 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3086
3087 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3088 buffer[count++] = cpu_to_le32(0);
3089}
3090
3091static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
3092{
3093 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3094 AMD_PG_SUPPORT_GFX_SMG |
3095 AMD_PG_SUPPORT_GFX_DMG |
3096 AMD_PG_SUPPORT_CP |
3097 AMD_PG_SUPPORT_GDS |
3098 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3099 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
3100 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
3101 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3102 gfx_v6_0_init_gfx_cgpg(adev);
3103 gfx_v6_0_enable_cp_pg(adev, true);
3104 gfx_v6_0_enable_gds_pg(adev, true);
3105 } else {
25069e06
TSD		 3106 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3107 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2cd46ad2
KW		 3108
3109 }
3110 gfx_v6_0_init_ao_cu_mask(adev);
3111 gfx_v6_0_update_gfx_pg(adev, true);
3112 } else {
3113
25069e06
TSD		 3114 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3115 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2cd46ad2
KW		 3116 }
3117}
3118
3119static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
3120{
3121 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3122 AMD_PG_SUPPORT_GFX_SMG |
3123 AMD_PG_SUPPORT_GFX_DMG |
3124 AMD_PG_SUPPORT_CP |
3125 AMD_PG_SUPPORT_GDS |
3126 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3127 gfx_v6_0_update_gfx_pg(adev, false);
3128 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3129 gfx_v6_0_enable_cp_pg(adev, false);
3130 gfx_v6_0_enable_gds_pg(adev, false);
3131 }
3132 }
3133}
3134
3135static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3136{
3137 uint64_t clock;
3138
3139 mutex_lock(&adev->gfx.gpu_clock_mutex);
25069e06
TSD		 3140 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3141 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3142 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2cd46ad2
KW		 3143 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3144 return clock;
3145}
3146
0f444c24
AD		 3147static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3148{
45682886
ML		 3149 if (flags & AMDGPU_HAVE_CTX_SWITCH)
3150 gfx_v6_0_ring_emit_vgt_flush(ring);
0f444c24
AD		 3151 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3152 amdgpu_ring_write(ring, 0x80000000);
3153 amdgpu_ring_write(ring, 0);
3154}
3155
3ee73ed8
TSD		 3156
3157static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
3158{
3159 WREG32(mmSQ_IND_INDEX,
3160 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3161 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3162 (address << SQ_IND_INDEX__INDEX__SHIFT) |
3163 (SQ_IND_INDEX__FORCE_READ_MASK));
3164 return RREG32(mmSQ_IND_DATA);
3165}
3166
34e646f4
TSD		 3167static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
3168 uint32_t wave, uint32_t thread,
3169 uint32_t regno, uint32_t num, uint32_t *out)
3170{
3171 WREG32(mmSQ_IND_INDEX,
3172 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3173 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3174 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3175 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3176 (SQ_IND_INDEX__FORCE_READ_MASK) |
3177 (SQ_IND_INDEX__AUTO_INCR_MASK));
3178 while (num--)
3179 *(out++) = RREG32(mmSQ_IND_DATA);
3180}
3181
3ee73ed8
TSD		 3182static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3183{
3184 /* type 0 wave data */
3185 dst[(*no_fields)++] = 0;
3186 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3187 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3188 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3189 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3190 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3191 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3192 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3193 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3194 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3195 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3196 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3197 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3198 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3199 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3200 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3201 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3202 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3203 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3204}
3205
34e646f4
TSD		 3206static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3207 uint32_t wave, uint32_t start,
3208 uint32_t size, uint32_t *dst)
3209{
3210 wave_read_regs(
3211 adev, simd, wave, 0,
3212 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3213}
3214
2cd46ad2
KW		 3215static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3216 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3217 .select_se_sh = &gfx_v6_0_select_se_sh,
3ee73ed8 3218 .read_wave_data = &gfx_v6_0_read_wave_data,
34e646f4 3219 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
2cd46ad2
KW		 3220};
3221
3222static int gfx_v6_0_early_init(void *handle)
3223{
3224 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3225
3226 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3227 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3228 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3229 gfx_v6_0_set_ring_funcs(adev);
3230 gfx_v6_0_set_irq_funcs(adev);
3231
3232 return 0;
3233}
3234
3235static int gfx_v6_0_sw_init(void *handle)
3236{
3237 struct amdgpu_ring *ring;
3238 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3239 int i, r;
3240
3241 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
3242 if (r)
3243 return r;
3244
3245 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
3246 if (r)
3247 return r;
3248
3249 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
3250 if (r)
3251 return r;
3252
3253 gfx_v6_0_scratch_init(adev);
3254
3255 r = gfx_v6_0_init_microcode(adev);
3256 if (r) {
3257 DRM_ERROR("Failed to load gfx firmware!\n");
3258 return r;
3259 }
3260
3261 r = gfx_v6_0_rlc_init(adev);
3262 if (r) {
3263 DRM_ERROR("Failed to init rlc BOs!\n");
3264 return r;
3265 }
3266
3267 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3268 ring = &adev->gfx.gfx_ring[i];
3269 ring->ring_obj = NULL;
3270 sprintf(ring->name, "gfx");
3271 r = amdgpu_ring_init(adev, ring, 1024,
21cd942e 3272 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
2cd46ad2
KW		 3273 if (r)
3274 return r;
3275 }
3276
3277 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3278 unsigned irq_type;
3279
3280 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3281 DRM_ERROR("Too many (%d) compute rings!\n", i);
3282 break;
3283 }
3284 ring = &adev->gfx.compute_ring[i];
3285 ring->ring_obj = NULL;
3286 ring->use_doorbell = false;
3287 ring->doorbell_index = 0;
3288 ring->me = 1;
3289 ring->pipe = i;
3290 ring->queue = i;
3291 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
3292 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2255e8c1 3293 r = amdgpu_ring_init(adev, ring, 1024,
21cd942e 3294 &adev->gfx.eop_irq, irq_type);
2cd46ad2
KW		 3295 if (r)
3296 return r;
3297 }
3298
3299 return r;
3300}
3301
3302static int gfx_v6_0_sw_fini(void *handle)
3303{
3304 int i;
3305 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3306
3307 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
3308 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
3309 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
3310
3311 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3312 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3313 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3314 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3315
2cd46ad2
KW		 3316 gfx_v6_0_rlc_fini(adev);
3317
3318 return 0;
3319}
3320
3321static int gfx_v6_0_hw_init(void *handle)
3322{
3323 int r;
3324 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3325
3326 gfx_v6_0_gpu_init(adev);
3327
3328 r = gfx_v6_0_rlc_resume(adev);
3329 if (r)
3330 return r;
3331
3332 r = gfx_v6_0_cp_resume(adev);
3333 if (r)
3334 return r;
3335
3336 adev->gfx.ce_ram_size = 0x8000;
3337
3338 return r;
3339}
3340
3341static int gfx_v6_0_hw_fini(void *handle)
3342{
3343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3344
3345 gfx_v6_0_cp_enable(adev, false);
3346 gfx_v6_0_rlc_stop(adev);
3347 gfx_v6_0_fini_pg(adev);
3348
3349 return 0;
3350}
3351
3352static int gfx_v6_0_suspend(void *handle)
3353{
3354 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3355
3356 return gfx_v6_0_hw_fini(adev);
3357}
3358
3359static int gfx_v6_0_resume(void *handle)
3360{
3361 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3362
3363 return gfx_v6_0_hw_init(adev);
3364}
3365
3366static bool gfx_v6_0_is_idle(void *handle)
3367{
3368 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3369
25069e06 3370 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
2cd46ad2
KW		 3371 return false;
3372 else
3373 return true;
3374}
3375
3376static int gfx_v6_0_wait_for_idle(void *handle)
3377{
3378 unsigned i;
2cd46ad2
KW		 3379 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3380
3381 for (i = 0; i < adev->usec_timeout; i++) {
4aeacf0f 3382 if (gfx_v6_0_is_idle(handle))
2cd46ad2
KW		 3383 return 0;
3384 udelay(1);
3385 }
3386 return -ETIMEDOUT;
3387}
3388
3389static int gfx_v6_0_soft_reset(void *handle)
3390{
3391 return 0;
3392}
3393
3394static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3395 enum amdgpu_interrupt_state state)
3396{
3397 u32 cp_int_cntl;
3398
3399 switch (state) {
3400 case AMDGPU_IRQ_STATE_DISABLE:
25069e06
TSD		 3401 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3402 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3403 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3404 break;
3405 case AMDGPU_IRQ_STATE_ENABLE:
25069e06
TSD		 3406 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3407 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3408 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3409 break;
3410 default:
3411 break;
3412 }
3413}
3414
3415static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3416 int ring,
3417 enum amdgpu_interrupt_state state)
3418{
3419 u32 cp_int_cntl;
3420 switch (state){
3421 case AMDGPU_IRQ_STATE_DISABLE:
3422 if (ring == 0) {
25069e06
TSD		 3423 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3424 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3425 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
2cd46ad2
KW		 3426 break;
3427 } else {
25069e06
TSD		 3428 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3429 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3430 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
2cd46ad2
KW		 3431 break;
3432
3433 }
3434 case AMDGPU_IRQ_STATE_ENABLE:
3435 if (ring == 0) {
25069e06
TSD		 3436 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3437 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3438 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
2cd46ad2
KW		 3439 break;
3440 } else {
25069e06
TSD		 3441 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3442 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3443 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
2cd46ad2
KW		 3444 break;
3445
3446 }
3447
3448 default:
3449 BUG();
3450 break;
3451
3452 }
3453}
3454
3455static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3456 struct amdgpu_irq_src *src,
3457 unsigned type,
3458 enum amdgpu_interrupt_state state)
3459{
3460 u32 cp_int_cntl;
3461
3462 switch (state) {
3463 case AMDGPU_IRQ_STATE_DISABLE:
25069e06 3464 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3465 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
25069e06 3466 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3467 break;
3468 case AMDGPU_IRQ_STATE_ENABLE:
25069e06 3469 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3470 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
25069e06 3471 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3472 break;
3473 default:
3474 break;
3475 }
3476
3477 return 0;
3478}
3479
3480static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3481 struct amdgpu_irq_src *src,
3482 unsigned type,
3483 enum amdgpu_interrupt_state state)
3484{
3485 u32 cp_int_cntl;
3486
3487 switch (state) {
3488 case AMDGPU_IRQ_STATE_DISABLE:
25069e06 3489 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3490 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
25069e06 3491 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3492 break;
3493 case AMDGPU_IRQ_STATE_ENABLE:
25069e06 3494 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3495 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
25069e06 3496 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3497 break;
3498 default:
3499 break;
3500 }
3501
3502 return 0;
3503}
3504
3505static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3506 struct amdgpu_irq_src *src,
3507 unsigned type,
3508 enum amdgpu_interrupt_state state)
3509{
3510 switch (type) {
3511 case AMDGPU_CP_IRQ_GFX_EOP:
3512 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3513 break;
3514 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3515 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3516 break;
3517 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3518 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3519 break;
3520 default:
3521 break;
3522 }
3523 return 0;
3524}
3525
3526static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3527 struct amdgpu_irq_src *source,
3528 struct amdgpu_iv_entry *entry)
3529{
3530 switch (entry->ring_id) {
3531 case 0:
3532 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3533 break;
3534 case 1:
3535 case 2:
25069e06 3536 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
2cd46ad2
KW		 3537 break;
3538 default:
3539 break;
3540 }
3541 return 0;
3542}
3543
3544static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3545 struct amdgpu_irq_src *source,
3546 struct amdgpu_iv_entry *entry)
3547{
3548 DRM_ERROR("Illegal register access in command stream\n");
3549 schedule_work(&adev->reset_work);
3550 return 0;
3551}
3552
3553static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3554 struct amdgpu_irq_src *source,
3555 struct amdgpu_iv_entry *entry)
3556{
3557 DRM_ERROR("Illegal instruction in command stream\n");
3558 schedule_work(&adev->reset_work);
3559 return 0;
3560}
3561
3562static int gfx_v6_0_set_clockgating_state(void *handle,
3563 enum amd_clockgating_state state)
3564{
3565 bool gate = false;
3566 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3567
3568 if (state == AMD_CG_STATE_GATE)
3569 gate = true;
3570
3571 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3572 if (gate) {
3573 gfx_v6_0_enable_mgcg(adev, true);
3574 gfx_v6_0_enable_cgcg(adev, true);
3575 } else {
3576 gfx_v6_0_enable_cgcg(adev, false);
3577 gfx_v6_0_enable_mgcg(adev, false);
3578 }
3579 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3580
3581 return 0;
3582}
3583
3584static int gfx_v6_0_set_powergating_state(void *handle,
3585 enum amd_powergating_state state)
3586{
3587 bool gate = false;
3588 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3589
3590 if (state == AMD_PG_STATE_GATE)
3591 gate = true;
3592
3593 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3594 AMD_PG_SUPPORT_GFX_SMG |
3595 AMD_PG_SUPPORT_GFX_DMG |
3596 AMD_PG_SUPPORT_CP |
3597 AMD_PG_SUPPORT_GDS |
3598 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3599 gfx_v6_0_update_gfx_pg(adev, gate);
3600 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3601 gfx_v6_0_enable_cp_pg(adev, gate);
3602 gfx_v6_0_enable_gds_pg(adev, gate);
3603 }
3604 }
3605
3606 return 0;
3607}
3608
a1255107 3609static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
2cd46ad2
KW		 3610 .name = "gfx_v6_0",
3611 .early_init = gfx_v6_0_early_init,
3612 .late_init = NULL,
3613 .sw_init = gfx_v6_0_sw_init,
3614 .sw_fini = gfx_v6_0_sw_fini,
3615 .hw_init = gfx_v6_0_hw_init,
3616 .hw_fini = gfx_v6_0_hw_fini,
3617 .suspend = gfx_v6_0_suspend,
3618 .resume = gfx_v6_0_resume,
3619 .is_idle = gfx_v6_0_is_idle,
3620 .wait_for_idle = gfx_v6_0_wait_for_idle,
3621 .soft_reset = gfx_v6_0_soft_reset,
3622 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3623 .set_powergating_state = gfx_v6_0_set_powergating_state,
3624};
3625
3626static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
21cd942e 3627 .type = AMDGPU_RING_TYPE_GFX,
79887142
CK		 3628 .align_mask = 0xff,
3629 .nop = 0x80000000,
6f924e20 3630 .get_rptr = gfx_v6_0_ring_get_rptr,
832c6ef7 3631 .get_wptr = gfx_v6_0_ring_get_wptr,
2cd46ad2 3632 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
e12f3d7a
CK		 3633 .emit_frame_size =
3634 5 + /* gfx_v6_0_ring_emit_hdp_flush */
3635 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
3636 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3637 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3638 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
45682886 3639 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
e12f3d7a 3640 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
668f52c3
AD		 3641 .emit_ib = gfx_v6_0_ring_emit_ib,
3642 .emit_fence = gfx_v6_0_ring_emit_fence,
2cd46ad2
KW		 3643 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3644 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
2cd46ad2
KW		 3645 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3646 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3647 .test_ring = gfx_v6_0_ring_test_ring,
3648 .test_ib = gfx_v6_0_ring_test_ib,
3649 .insert_nop = amdgpu_ring_insert_nop,
0f444c24 3650 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
2cd46ad2
KW		 3651};
3652
3653static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
21cd942e 3654 .type = AMDGPU_RING_TYPE_COMPUTE,
79887142
CK		 3655 .align_mask = 0xff,
3656 .nop = 0x80000000,
6f924e20 3657 .get_rptr = gfx_v6_0_ring_get_rptr,
832c6ef7 3658 .get_wptr = gfx_v6_0_ring_get_wptr,
2cd46ad2 3659 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
e12f3d7a
CK		 3660 .emit_frame_size =
3661 5 + /* gfx_v6_0_ring_emit_hdp_flush */
3662 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
3663 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3664 17 + /* gfx_v6_0_ring_emit_vm_flush */
3665 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3666 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
668f52c3
AD		 3667 .emit_ib = gfx_v6_0_ring_emit_ib,
3668 .emit_fence = gfx_v6_0_ring_emit_fence,
2cd46ad2
KW		 3669 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3670 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
2cd46ad2
KW		 3671 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3672 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3673 .test_ring = gfx_v6_0_ring_test_ring,
3674 .test_ib = gfx_v6_0_ring_test_ib,
3675 .insert_nop = amdgpu_ring_insert_nop,
3676};
3677
3678static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3679{
3680 int i;
3681
3682 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3683 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3684 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3685 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3686}
3687
3688static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3689 .set = gfx_v6_0_set_eop_interrupt_state,
3690 .process = gfx_v6_0_eop_irq,
3691};
3692
3693static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3694 .set = gfx_v6_0_set_priv_reg_fault_state,
3695 .process = gfx_v6_0_priv_reg_irq,
3696};
3697
3698static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3699 .set = gfx_v6_0_set_priv_inst_fault_state,
3700 .process = gfx_v6_0_priv_inst_irq,
3701};
3702
3703static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3704{
3705 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3706 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3707
3708 adev->gfx.priv_reg_irq.num_types = 1;
3709 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3710
3711 adev->gfx.priv_inst_irq.num_types = 1;
3712 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3713}
3714
3715static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3716{
3717 int i, j, k, counter, active_cu_number = 0;
3718 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3719 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
375d6f70 3720 unsigned disable_masks[4 * 2];
2cd46ad2
KW		 3721
3722 memset(cu_info, 0, sizeof(*cu_info));
3723
375d6f70
FC		 3724 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3725
3726 mutex_lock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 3727 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3728 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3729 mask = 1;
3730 ao_bitmap = 0;
3731 counter = 0;
375d6f70
FC		 3732 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3733 if (i < 4 && j < 2)
3734 gfx_v6_0_set_user_cu_inactive_bitmap(
3735 adev, disable_masks[i * 2 + j]);
3736 bitmap = gfx_v6_0_get_cu_enabled(adev);
2cd46ad2
KW		 3737 cu_info->bitmap[i][j] = bitmap;
3738
375d6f70 3739 for (k = 0; k < 16; k++) {
2cd46ad2
KW		 3740 if (bitmap & mask) {
3741 if (counter < 2)
3742 ao_bitmap |= mask;
3743 counter ++;
3744 }
3745 mask <<= 1;
3746 }
3747 active_cu_number += counter;
3748 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3749 }
3750 }
2cd46ad2 3751
375d6f70
FC		 3752 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3753 mutex_unlock(&adev->grbm_idx_mutex);
3754
2cd46ad2
KW		 3755 cu_info->number = active_cu_number;
3756 cu_info->ao_cu_mask = ao_cu_mask;
3757}
a1255107
AD		 3758
3759const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3760{
3761 .type = AMD_IP_BLOCK_TYPE_GFX,
3762 .major = 6,
3763 .minor = 0,
3764 .rev = 0,
3765 .funcs = &gfx_v6_0_ip_funcs,
3766};
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