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[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v6_0.c
CommitLineData
2cd46ad2
KW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h"
28#include "si/clearstate_si.h"
29#include "si/sid.h"
30
31#define GFX6_NUM_GFX_RINGS 1
32#define GFX6_NUM_COMPUTE_RINGS 2
33#define STATIC_PER_CU_PG_ENABLE (1 << 3)
34#define DYN_PER_CU_PG_ENABLE (1 << 2)
35#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
36#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
37
38
39static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
40static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
41static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
42
43MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
44MODULE_FIRMWARE("radeon/tahiti_me.bin");
45MODULE_FIRMWARE("radeon/tahiti_ce.bin");
46MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
47
48MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
49MODULE_FIRMWARE("radeon/pitcairn_me.bin");
50MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
51MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
52
53MODULE_FIRMWARE("radeon/verde_pfp.bin");
54MODULE_FIRMWARE("radeon/verde_me.bin");
55MODULE_FIRMWARE("radeon/verde_ce.bin");
56MODULE_FIRMWARE("radeon/verde_rlc.bin");
57
58MODULE_FIRMWARE("radeon/oland_pfp.bin");
59MODULE_FIRMWARE("radeon/oland_me.bin");
60MODULE_FIRMWARE("radeon/oland_ce.bin");
61MODULE_FIRMWARE("radeon/oland_rlc.bin");
62
63MODULE_FIRMWARE("radeon/hainan_pfp.bin");
64MODULE_FIRMWARE("radeon/hainan_me.bin");
65MODULE_FIRMWARE("radeon/hainan_ce.bin");
66MODULE_FIRMWARE("radeon/hainan_rlc.bin");
67
68static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
69static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
70//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
71static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
72
73
74static const u32 verde_rlc_save_restore_register_list[] =
75{
76 (0x8000 << 16) | (0x98f4 >> 2),
77 0x00000000,
78 (0x8040 << 16) | (0x98f4 >> 2),
79 0x00000000,
80 (0x8000 << 16) | (0xe80 >> 2),
81 0x00000000,
82 (0x8040 << 16) | (0xe80 >> 2),
83 0x00000000,
84 (0x8000 << 16) | (0x89bc >> 2),
85 0x00000000,
86 (0x8040 << 16) | (0x89bc >> 2),
87 0x00000000,
88 (0x8000 << 16) | (0x8c1c >> 2),
89 0x00000000,
90 (0x8040 << 16) | (0x8c1c >> 2),
91 0x00000000,
92 (0x9c00 << 16) | (0x98f0 >> 2),
93 0x00000000,
94 (0x9c00 << 16) | (0xe7c >> 2),
95 0x00000000,
96 (0x8000 << 16) | (0x9148 >> 2),
97 0x00000000,
98 (0x8040 << 16) | (0x9148 >> 2),
99 0x00000000,
100 (0x9c00 << 16) | (0x9150 >> 2),
101 0x00000000,
102 (0x9c00 << 16) | (0x897c >> 2),
103 0x00000000,
104 (0x9c00 << 16) | (0x8d8c >> 2),
105 0x00000000,
106 (0x9c00 << 16) | (0xac54 >> 2),
107 0X00000000,
108 0x3,
109 (0x9c00 << 16) | (0x98f8 >> 2),
110 0x00000000,
111 (0x9c00 << 16) | (0x9910 >> 2),
112 0x00000000,
113 (0x9c00 << 16) | (0x9914 >> 2),
114 0x00000000,
115 (0x9c00 << 16) | (0x9918 >> 2),
116 0x00000000,
117 (0x9c00 << 16) | (0x991c >> 2),
118 0x00000000,
119 (0x9c00 << 16) | (0x9920 >> 2),
120 0x00000000,
121 (0x9c00 << 16) | (0x9924 >> 2),
122 0x00000000,
123 (0x9c00 << 16) | (0x9928 >> 2),
124 0x00000000,
125 (0x9c00 << 16) | (0x992c >> 2),
126 0x00000000,
127 (0x9c00 << 16) | (0x9930 >> 2),
128 0x00000000,
129 (0x9c00 << 16) | (0x9934 >> 2),
130 0x00000000,
131 (0x9c00 << 16) | (0x9938 >> 2),
132 0x00000000,
133 (0x9c00 << 16) | (0x993c >> 2),
134 0x00000000,
135 (0x9c00 << 16) | (0x9940 >> 2),
136 0x00000000,
137 (0x9c00 << 16) | (0x9944 >> 2),
138 0x00000000,
139 (0x9c00 << 16) | (0x9948 >> 2),
140 0x00000000,
141 (0x9c00 << 16) | (0x994c >> 2),
142 0x00000000,
143 (0x9c00 << 16) | (0x9950 >> 2),
144 0x00000000,
145 (0x9c00 << 16) | (0x9954 >> 2),
146 0x00000000,
147 (0x9c00 << 16) | (0x9958 >> 2),
148 0x00000000,
149 (0x9c00 << 16) | (0x995c >> 2),
150 0x00000000,
151 (0x9c00 << 16) | (0x9960 >> 2),
152 0x00000000,
153 (0x9c00 << 16) | (0x9964 >> 2),
154 0x00000000,
155 (0x9c00 << 16) | (0x9968 >> 2),
156 0x00000000,
157 (0x9c00 << 16) | (0x996c >> 2),
158 0x00000000,
159 (0x9c00 << 16) | (0x9970 >> 2),
160 0x00000000,
161 (0x9c00 << 16) | (0x9974 >> 2),
162 0x00000000,
163 (0x9c00 << 16) | (0x9978 >> 2),
164 0x00000000,
165 (0x9c00 << 16) | (0x997c >> 2),
166 0x00000000,
167 (0x9c00 << 16) | (0x9980 >> 2),
168 0x00000000,
169 (0x9c00 << 16) | (0x9984 >> 2),
170 0x00000000,
171 (0x9c00 << 16) | (0x9988 >> 2),
172 0x00000000,
173 (0x9c00 << 16) | (0x998c >> 2),
174 0x00000000,
175 (0x9c00 << 16) | (0x8c00 >> 2),
176 0x00000000,
177 (0x9c00 << 16) | (0x8c14 >> 2),
178 0x00000000,
179 (0x9c00 << 16) | (0x8c04 >> 2),
180 0x00000000,
181 (0x9c00 << 16) | (0x8c08 >> 2),
182 0x00000000,
183 (0x8000 << 16) | (0x9b7c >> 2),
184 0x00000000,
185 (0x8040 << 16) | (0x9b7c >> 2),
186 0x00000000,
187 (0x8000 << 16) | (0xe84 >> 2),
188 0x00000000,
189 (0x8040 << 16) | (0xe84 >> 2),
190 0x00000000,
191 (0x8000 << 16) | (0x89c0 >> 2),
192 0x00000000,
193 (0x8040 << 16) | (0x89c0 >> 2),
194 0x00000000,
195 (0x8000 << 16) | (0x914c >> 2),
196 0x00000000,
197 (0x8040 << 16) | (0x914c >> 2),
198 0x00000000,
199 (0x8000 << 16) | (0x8c20 >> 2),
200 0x00000000,
201 (0x8040 << 16) | (0x8c20 >> 2),
202 0x00000000,
203 (0x8000 << 16) | (0x9354 >> 2),
204 0x00000000,
205 (0x8040 << 16) | (0x9354 >> 2),
206 0x00000000,
207 (0x9c00 << 16) | (0x9060 >> 2),
208 0x00000000,
209 (0x9c00 << 16) | (0x9364 >> 2),
210 0x00000000,
211 (0x9c00 << 16) | (0x9100 >> 2),
212 0x00000000,
213 (0x9c00 << 16) | (0x913c >> 2),
214 0x00000000,
215 (0x8000 << 16) | (0x90e0 >> 2),
216 0x00000000,
217 (0x8000 << 16) | (0x90e4 >> 2),
218 0x00000000,
219 (0x8000 << 16) | (0x90e8 >> 2),
220 0x00000000,
221 (0x8040 << 16) | (0x90e0 >> 2),
222 0x00000000,
223 (0x8040 << 16) | (0x90e4 >> 2),
224 0x00000000,
225 (0x8040 << 16) | (0x90e8 >> 2),
226 0x00000000,
227 (0x9c00 << 16) | (0x8bcc >> 2),
228 0x00000000,
229 (0x9c00 << 16) | (0x8b24 >> 2),
230 0x00000000,
231 (0x9c00 << 16) | (0x88c4 >> 2),
232 0x00000000,
233 (0x9c00 << 16) | (0x8e50 >> 2),
234 0x00000000,
235 (0x9c00 << 16) | (0x8c0c >> 2),
236 0x00000000,
237 (0x9c00 << 16) | (0x8e58 >> 2),
238 0x00000000,
239 (0x9c00 << 16) | (0x8e5c >> 2),
240 0x00000000,
241 (0x9c00 << 16) | (0x9508 >> 2),
242 0x00000000,
243 (0x9c00 << 16) | (0x950c >> 2),
244 0x00000000,
245 (0x9c00 << 16) | (0x9494 >> 2),
246 0x00000000,
247 (0x9c00 << 16) | (0xac0c >> 2),
248 0x00000000,
249 (0x9c00 << 16) | (0xac10 >> 2),
250 0x00000000,
251 (0x9c00 << 16) | (0xac14 >> 2),
252 0x00000000,
253 (0x9c00 << 16) | (0xae00 >> 2),
254 0x00000000,
255 (0x9c00 << 16) | (0xac08 >> 2),
256 0x00000000,
257 (0x9c00 << 16) | (0x88d4 >> 2),
258 0x00000000,
259 (0x9c00 << 16) | (0x88c8 >> 2),
260 0x00000000,
261 (0x9c00 << 16) | (0x88cc >> 2),
262 0x00000000,
263 (0x9c00 << 16) | (0x89b0 >> 2),
264 0x00000000,
265 (0x9c00 << 16) | (0x8b10 >> 2),
266 0x00000000,
267 (0x9c00 << 16) | (0x8a14 >> 2),
268 0x00000000,
269 (0x9c00 << 16) | (0x9830 >> 2),
270 0x00000000,
271 (0x9c00 << 16) | (0x9834 >> 2),
272 0x00000000,
273 (0x9c00 << 16) | (0x9838 >> 2),
274 0x00000000,
275 (0x9c00 << 16) | (0x9a10 >> 2),
276 0x00000000,
277 (0x8000 << 16) | (0x9870 >> 2),
278 0x00000000,
279 (0x8000 << 16) | (0x9874 >> 2),
280 0x00000000,
281 (0x8001 << 16) | (0x9870 >> 2),
282 0x00000000,
283 (0x8001 << 16) | (0x9874 >> 2),
284 0x00000000,
285 (0x8040 << 16) | (0x9870 >> 2),
286 0x00000000,
287 (0x8040 << 16) | (0x9874 >> 2),
288 0x00000000,
289 (0x8041 << 16) | (0x9870 >> 2),
290 0x00000000,
291 (0x8041 << 16) | (0x9874 >> 2),
292 0x00000000,
293 0x00000000
294};
295
296static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
297{
298 const char *chip_name;
299 char fw_name[30];
300 int err;
301 const struct gfx_firmware_header_v1_0 *cp_hdr;
302 const struct rlc_firmware_header_v1_0 *rlc_hdr;
303
304 DRM_DEBUG("\n");
305
306 switch (adev->asic_type) {
307 case CHIP_TAHITI:
308 chip_name = "tahiti";
309 break;
310 case CHIP_PITCAIRN:
311 chip_name = "pitcairn";
312 break;
313 case CHIP_VERDE:
314 chip_name = "verde";
315 break;
316 case CHIP_OLAND:
317 chip_name = "oland";
318 break;
319 case CHIP_HAINAN:
320 chip_name = "hainan";
321 break;
322 default: BUG();
323 }
324
325 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
326 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
327 if (err)
328 goto out;
329 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
330 if (err)
331 goto out;
332 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
333 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
334 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
335
336 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
337 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
338 if (err)
339 goto out;
340 err = amdgpu_ucode_validate(adev->gfx.me_fw);
341 if (err)
342 goto out;
343 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
344 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
345 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
346
347 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
348 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
349 if (err)
350 goto out;
351 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
352 if (err)
353 goto out;
354 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
355 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
356 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
357
358 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
359 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
360 if (err)
361 goto out;
362 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
363 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
364 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
365 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
366
367out:
368 if (err) {
369 printk(KERN_ERR
370 "gfx6: Failed to load firmware \"%s\"\n",
371 fw_name);
372 release_firmware(adev->gfx.pfp_fw);
373 adev->gfx.pfp_fw = NULL;
374 release_firmware(adev->gfx.me_fw);
375 adev->gfx.me_fw = NULL;
376 release_firmware(adev->gfx.ce_fw);
377 adev->gfx.ce_fw = NULL;
378 release_firmware(adev->gfx.rlc_fw);
379 adev->gfx.rlc_fw = NULL;
380 }
381 return err;
382}
383
384static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
385{
386 const u32 num_tile_mode_states = 32;
387 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
388
389 switch (adev->gfx.config.mem_row_size_in_kb) {
390 case 1:
391 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
392 break;
393 case 2:
394 default:
395 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
396 break;
397 case 4:
398 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
399 break;
400 }
401
402 if (adev->asic_type == CHIP_VERDE ||
403 adev->asic_type == CHIP_OLAND ||
404 adev->asic_type == CHIP_HAINAN) {
405 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
406 switch (reg_offset) {
407 case 0:
408 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
409 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
410 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
411 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
412 NUM_BANKS(ADDR_SURF_16_BANK) |
413 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
414 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
415 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
416 break;
417 case 1:
418 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
419 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
420 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
421 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
422 NUM_BANKS(ADDR_SURF_16_BANK) |
423 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
424 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
425 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
426 break;
427 case 2:
428 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
429 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
430 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
431 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
432 NUM_BANKS(ADDR_SURF_16_BANK) |
433 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
435 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
436 break;
437 case 3:
438 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
439 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
440 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
441 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
442 NUM_BANKS(ADDR_SURF_16_BANK) |
443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
446 break;
447 case 4:
448 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
449 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
451 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
452 NUM_BANKS(ADDR_SURF_16_BANK) |
453 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
456 break;
457 case 5:
458 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
459 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
460 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
461 TILE_SPLIT(split_equal_to_row_size) |
462 NUM_BANKS(ADDR_SURF_16_BANK) |
463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
466 break;
467 case 6:
468 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
469 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
471 TILE_SPLIT(split_equal_to_row_size) |
472 NUM_BANKS(ADDR_SURF_16_BANK) |
473 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
476 break;
477 case 7:
478 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
479 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
480 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
481 TILE_SPLIT(split_equal_to_row_size) |
482 NUM_BANKS(ADDR_SURF_16_BANK) |
483 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
485 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
486 break;
487 case 8:
488 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
489 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
490 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
492 NUM_BANKS(ADDR_SURF_16_BANK) |
493 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
496 break;
497 case 9:
498 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
499 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
500 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
502 NUM_BANKS(ADDR_SURF_16_BANK) |
503 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
504 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
505 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
506 break;
507 case 10:
508 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
509 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
510 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
511 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
512 NUM_BANKS(ADDR_SURF_16_BANK) |
513 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
516 break;
517 case 11:
518 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
519 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
520 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
522 NUM_BANKS(ADDR_SURF_16_BANK) |
523 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
526 break;
527 case 12:
528 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
529 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
530 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
531 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
532 NUM_BANKS(ADDR_SURF_16_BANK) |
533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
536 break;
537 case 13:
538 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
539 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
540 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
541 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
542 NUM_BANKS(ADDR_SURF_16_BANK) |
543 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
544 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
545 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
546 break;
547 case 14:
548 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
549 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
550 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
551 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
552 NUM_BANKS(ADDR_SURF_16_BANK) |
553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
556 break;
557 case 15:
558 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
559 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
560 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
562 NUM_BANKS(ADDR_SURF_16_BANK) |
563 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
564 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
565 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
566 break;
567 case 16:
568 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
569 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
570 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
571 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
572 NUM_BANKS(ADDR_SURF_16_BANK) |
573 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
574 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
575 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
576 break;
577 case 17:
578 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
579 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
580 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
581 TILE_SPLIT(split_equal_to_row_size) |
582 NUM_BANKS(ADDR_SURF_16_BANK) |
583 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
586 break;
587 case 21:
588 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
589 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
590 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
591 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
592 NUM_BANKS(ADDR_SURF_16_BANK) |
593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
596 break;
597 case 22:
598 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
599 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
600 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
602 NUM_BANKS(ADDR_SURF_16_BANK) |
603 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
604 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
605 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
606 break;
607 case 23:
608 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
609 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
610 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
611 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
612 NUM_BANKS(ADDR_SURF_16_BANK) |
613 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
614 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
616 break;
617 case 24:
618 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
619 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
620 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
621 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
622 NUM_BANKS(ADDR_SURF_16_BANK) |
623 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
625 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
626 break;
627 case 25:
628 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
629 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
630 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
631 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
632 NUM_BANKS(ADDR_SURF_8_BANK) |
633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
636 break;
637 default:
638 gb_tile_moden = 0;
639 break;
640 }
641 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
642 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
643 }
644 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
646 switch (reg_offset) {
647 case 0: /* non-AA compressed depth or any compressed stencil */
648 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
649 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
650 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
652 NUM_BANKS(ADDR_SURF_16_BANK) |
653 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
654 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
655 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
656 break;
657 case 1: /* 2xAA/4xAA compressed depth only */
658 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
659 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
660 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
661 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
662 NUM_BANKS(ADDR_SURF_16_BANK) |
663 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
664 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
665 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
666 break;
667 case 2: /* 8xAA compressed depth only */
668 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
669 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
670 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
671 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
672 NUM_BANKS(ADDR_SURF_16_BANK) |
673 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
674 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
675 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
676 break;
677 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
678 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
679 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
680 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
681 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
682 NUM_BANKS(ADDR_SURF_16_BANK) |
683 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
684 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
685 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
686 break;
687 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
688 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
689 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
690 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
691 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
692 NUM_BANKS(ADDR_SURF_16_BANK) |
693 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
696 break;
697 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
698 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
699 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
700 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
701 TILE_SPLIT(split_equal_to_row_size) |
702 NUM_BANKS(ADDR_SURF_16_BANK) |
703 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
704 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
705 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
706 break;
707 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
708 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
709 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
710 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
711 TILE_SPLIT(split_equal_to_row_size) |
712 NUM_BANKS(ADDR_SURF_16_BANK) |
713 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
714 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
715 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
716 break;
717 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
718 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
719 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
720 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
721 TILE_SPLIT(split_equal_to_row_size) |
722 NUM_BANKS(ADDR_SURF_16_BANK) |
723 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
724 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
725 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
726 break;
727 case 8: /* 1D and 1D Array Surfaces */
728 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
729 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
730 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
731 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
732 NUM_BANKS(ADDR_SURF_16_BANK) |
733 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
734 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
735 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
736 break;
737 case 9: /* Displayable maps. */
738 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
739 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
740 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
741 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
742 NUM_BANKS(ADDR_SURF_16_BANK) |
743 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
744 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
745 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
746 break;
747 case 10: /* Display 8bpp. */
748 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
749 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
750 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
751 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
752 NUM_BANKS(ADDR_SURF_16_BANK) |
753 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
754 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
755 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
756 break;
757 case 11: /* Display 16bpp. */
758 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
759 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
760 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
761 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
762 NUM_BANKS(ADDR_SURF_16_BANK) |
763 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
764 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
765 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
766 break;
767 case 12: /* Display 32bpp. */
768 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
769 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
770 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
771 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
772 NUM_BANKS(ADDR_SURF_16_BANK) |
773 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
774 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
775 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
776 break;
777 case 13: /* Thin. */
778 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
779 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
780 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
781 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
782 NUM_BANKS(ADDR_SURF_16_BANK) |
783 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
784 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
785 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
786 break;
787 case 14: /* Thin 8 bpp. */
788 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
789 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
790 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
791 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
792 NUM_BANKS(ADDR_SURF_16_BANK) |
793 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
795 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
796 break;
797 case 15: /* Thin 16 bpp. */
798 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
799 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
800 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
801 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
802 NUM_BANKS(ADDR_SURF_16_BANK) |
803 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
804 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
805 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
806 break;
807 case 16: /* Thin 32 bpp. */
808 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
809 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
810 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
811 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
812 NUM_BANKS(ADDR_SURF_16_BANK) |
813 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
816 break;
817 case 17: /* Thin 64 bpp. */
818 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
819 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
820 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
821 TILE_SPLIT(split_equal_to_row_size) |
822 NUM_BANKS(ADDR_SURF_16_BANK) |
823 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
824 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
825 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
826 break;
827 case 21: /* 8 bpp PRT. */
828 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
829 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
830 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
831 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
832 NUM_BANKS(ADDR_SURF_16_BANK) |
833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
836 break;
837 case 22: /* 16 bpp PRT */
838 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
839 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
840 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
841 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
842 NUM_BANKS(ADDR_SURF_16_BANK) |
843 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
846 break;
847 case 23: /* 32 bpp PRT */
848 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
849 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
850 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
851 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
852 NUM_BANKS(ADDR_SURF_16_BANK) |
853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
856 break;
857 case 24: /* 64 bpp PRT */
858 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
859 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
860 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
861 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
862 NUM_BANKS(ADDR_SURF_16_BANK) |
863 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
864 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
865 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
866 break;
867 case 25: /* 128 bpp PRT */
868 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
869 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
870 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
871 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
872 NUM_BANKS(ADDR_SURF_8_BANK) |
873 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
876 break;
877 default:
878 gb_tile_moden = 0;
879 break;
880 }
881 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
882 WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden);
883 }
884 } else{
885
886 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
887 }
888
889}
890
891static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
892 u32 sh_num, u32 instance)
893{
894 u32 data;
895
896 if (instance == 0xffffffff)
897 data = INSTANCE_BROADCAST_WRITES;
898 else
899 data = INSTANCE_INDEX(instance);
900
901 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
902 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
903 else if (se_num == 0xffffffff)
904 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
905 else if (sh_num == 0xffffffff)
906 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
907 else
908 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
909 WREG32(GRBM_GFX_INDEX, data);
910}
911
912static u32 gfx_v6_0_create_bitmask(u32 bit_width)
913{
914 u32 i, mask = 0;
915
916 for (i = 0; i < bit_width; i++) {
917 mask <<= 1;
918 mask |= 1;
919 }
920 return mask;
921}
922
923static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
924 u32 max_rb_num_per_se,
925 u32 sh_per_se)
926{
927 u32 data, mask;
928
929 data = RREG32(CC_RB_BACKEND_DISABLE);
930 data &= BACKEND_DISABLE_MASK;
931 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
932
933 data >>= BACKEND_DISABLE_SHIFT;
934
935 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se);
936
937 return data & mask;
938}
939
940static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
941 u32 se_num, u32 sh_per_se,
942 u32 max_rb_num_per_se)
943{
944 int i, j;
945 u32 data, mask;
946 u32 disabled_rbs = 0;
947 u32 enabled_rbs = 0;
948
949 for (i = 0; i < se_num; i++) {
950 for (j = 0; j < sh_per_se; j++) {
951 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
952 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
953 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
954 }
955 }
956 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
957
958 mask = 1;
959 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
960 if (!(disabled_rbs & mask))
961 enabled_rbs |= mask;
962 mask <<= 1;
963 }
964
965 adev->gfx.config.backend_enable_mask = enabled_rbs;
966 adev->gfx.config.num_rbs = hweight32(enabled_rbs);
967
968 for (i = 0; i < se_num; i++) {
969 gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
970 data = 0;
971 for (j = 0; j < sh_per_se; j++) {
972 switch (enabled_rbs & 3) {
973 case 1:
974 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
975 break;
976 case 2:
977 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
978 break;
979 case 3:
980 default:
981 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
982 break;
983 }
984 enabled_rbs >>= 2;
985 }
986 WREG32(PA_SC_RASTER_CONFIG, data);
987 }
988 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
989}
990/*
991static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
992{
993}
994*/
995
996static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh)
997{
998 u32 data, mask;
999
1000 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1001 data &= INACTIVE_CUS_MASK;
1002 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1003
1004 data >>= INACTIVE_CUS_SHIFT;
1005
1006 mask = gfx_v6_0_create_bitmask(cu_per_sh);
1007
1008 return ~data & mask;
1009}
1010
1011
1012static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1013 u32 se_num, u32 sh_per_se,
1014 u32 cu_per_sh)
1015{
1016 int i, j, k;
1017 u32 data, mask;
1018 u32 active_cu = 0;
1019
1020 for (i = 0; i < se_num; i++) {
1021 for (j = 0; j < sh_per_se; j++) {
1022 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1023 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1024 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh);
1025
1026 mask = 1;
1027 for (k = 0; k < 16; k++) {
1028 mask <<= k;
1029 if (active_cu & mask) {
1030 data &= ~mask;
1031 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1032 break;
1033 }
1034 }
1035 }
1036 }
1037 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1038}
1039
1040static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1041{
1042 u32 gb_addr_config = 0;
1043 u32 mc_shared_chmap, mc_arb_ramcfg;
1044 u32 sx_debug_1;
1045 u32 hdp_host_path_cntl;
1046 u32 tmp;
1047
1048 switch (adev->asic_type) {
1049 case CHIP_TAHITI:
1050 adev->gfx.config.max_shader_engines = 2;
1051 adev->gfx.config.max_tile_pipes = 12;
1052 adev->gfx.config.max_cu_per_sh = 8;
1053 adev->gfx.config.max_sh_per_se = 2;
1054 adev->gfx.config.max_backends_per_se = 4;
1055 adev->gfx.config.max_texture_channel_caches = 12;
1056 adev->gfx.config.max_gprs = 256;
1057 adev->gfx.config.max_gs_threads = 32;
1058 adev->gfx.config.max_hw_contexts = 8;
1059
1060 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1061 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1062 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1063 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1064 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1065 break;
1066 case CHIP_PITCAIRN:
1067 adev->gfx.config.max_shader_engines = 2;
1068 adev->gfx.config.max_tile_pipes = 8;
1069 adev->gfx.config.max_cu_per_sh = 5;
1070 adev->gfx.config.max_sh_per_se = 2;
1071 adev->gfx.config.max_backends_per_se = 4;
1072 adev->gfx.config.max_texture_channel_caches = 8;
1073 adev->gfx.config.max_gprs = 256;
1074 adev->gfx.config.max_gs_threads = 32;
1075 adev->gfx.config.max_hw_contexts = 8;
1076
1077 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1078 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1079 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1080 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1081 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1082 break;
1083
1084 case CHIP_VERDE:
1085 adev->gfx.config.max_shader_engines = 1;
1086 adev->gfx.config.max_tile_pipes = 4;
1087 adev->gfx.config.max_cu_per_sh = 5;
1088 adev->gfx.config.max_sh_per_se = 2;
1089 adev->gfx.config.max_backends_per_se = 4;
1090 adev->gfx.config.max_texture_channel_caches = 4;
1091 adev->gfx.config.max_gprs = 256;
1092 adev->gfx.config.max_gs_threads = 32;
1093 adev->gfx.config.max_hw_contexts = 8;
1094
1095 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1096 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1097 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1098 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1099 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1100 break;
1101 case CHIP_OLAND:
1102 adev->gfx.config.max_shader_engines = 1;
1103 adev->gfx.config.max_tile_pipes = 4;
1104 adev->gfx.config.max_cu_per_sh = 6;
1105 adev->gfx.config.max_sh_per_se = 1;
1106 adev->gfx.config.max_backends_per_se = 2;
1107 adev->gfx.config.max_texture_channel_caches = 4;
1108 adev->gfx.config.max_gprs = 256;
1109 adev->gfx.config.max_gs_threads = 16;
1110 adev->gfx.config.max_hw_contexts = 8;
1111
1112 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1113 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1114 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1115 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1116 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1117 break;
1118 case CHIP_HAINAN:
1119 adev->gfx.config.max_shader_engines = 1;
1120 adev->gfx.config.max_tile_pipes = 4;
1121 adev->gfx.config.max_cu_per_sh = 5;
1122 adev->gfx.config.max_sh_per_se = 1;
1123 adev->gfx.config.max_backends_per_se = 1;
1124 adev->gfx.config.max_texture_channel_caches = 2;
1125 adev->gfx.config.max_gprs = 256;
1126 adev->gfx.config.max_gs_threads = 16;
1127 adev->gfx.config.max_hw_contexts = 8;
1128
1129 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1130 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1131 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1132 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1133 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1134 break;
1135 default:
1136 BUG();
1137 break;
1138 }
1139
1140 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1141 WREG32(SRBM_INT_CNTL, 1);
1142 WREG32(SRBM_INT_ACK, 1);
1143
1144 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1145
1146 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1147 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1148
1149 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1150 adev->gfx.config.mem_max_burst_length_bytes = 256;
1151 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1152 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1153 if (adev->gfx.config.mem_row_size_in_kb > 4)
1154 adev->gfx.config.mem_row_size_in_kb = 4;
1155 adev->gfx.config.shader_engine_tile_size = 32;
1156 adev->gfx.config.num_gpus = 1;
1157 adev->gfx.config.multi_gpu_tile_size = 64;
1158
1159 gb_addr_config &= ~ROW_SIZE_MASK;
1160 switch (adev->gfx.config.mem_row_size_in_kb) {
1161 case 1:
1162 default:
1163 gb_addr_config |= ROW_SIZE(0);
1164 break;
1165 case 2:
1166 gb_addr_config |= ROW_SIZE(1);
1167 break;
1168 case 4:
1169 gb_addr_config |= ROW_SIZE(2);
1170 break;
1171 }
1172 adev->gfx.config.gb_addr_config = gb_addr_config;
1173
1174 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1175 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1176 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1177 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1178 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1179 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1180#if 0
1181 if (adev->has_uvd) {
1182 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1183 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1184 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1185 }
1186#endif
1187 gfx_v6_0_tiling_mode_table_init(adev);
1188
1189 gfx_v6_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
1190 adev->gfx.config.max_sh_per_se,
1191 adev->gfx.config.max_backends_per_se);
1192
1193 gfx_v6_0_setup_spi(adev, adev->gfx.config.max_shader_engines,
1194 adev->gfx.config.max_sh_per_se,
1195 adev->gfx.config.max_cu_per_sh);
1196
1197 gfx_v6_0_get_cu_info(adev);
1198
1199 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1200 ROQ_IB2_START(0x2b)));
1201 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1202
1203 sx_debug_1 = RREG32(SX_DEBUG_1);
1204 WREG32(SX_DEBUG_1, sx_debug_1);
1205
1206 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1207
1208 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_frontend) |
1209 SC_BACKEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_backend) |
1210 SC_HIZ_TILE_FIFO_SIZE(adev->gfx.config.sc_hiz_tile_fifo_size) |
1211 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
1212
1213 WREG32(VGT_NUM_INSTANCES, 1);
1214
1215 WREG32(CP_PERFMON_CNTL, 0);
1216
1217 WREG32(SQ_CONFIG, 0);
1218
1219 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1220 FORCE_EOV_MAX_REZ_CNT(255)));
1221
1222 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1223 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1224
1225 WREG32(VGT_GS_VERTEX_REUSE, 16);
1226 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1227
1228 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1229 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1230 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1231 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1232 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1233 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1234 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1235 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1236
1237 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1238 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1239
1240 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1241
1242 udelay(50);
1243
1244}
1245
1246
1247static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1248{
1249 int i;
1250
1251 adev->gfx.scratch.num_reg = 7;
1252 adev->gfx.scratch.reg_base = SCRATCH_REG0;
1253 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1254 adev->gfx.scratch.free[i] = true;
1255 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1256 }
1257}
1258
1259static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1260{
1261 struct amdgpu_device *adev = ring->adev;
1262 uint32_t scratch;
1263 uint32_t tmp = 0;
1264 unsigned i;
1265 int r;
1266
1267 r = amdgpu_gfx_scratch_get(adev, &scratch);
1268 if (r) {
1269 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1270 return r;
1271 }
1272 WREG32(scratch, 0xCAFEDEAD);
1273
1274 r = amdgpu_ring_alloc(ring, 3);
1275 if (r) {
1276 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1277 amdgpu_gfx_scratch_free(adev, scratch);
1278 return r;
1279 }
1280 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1281 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1282 amdgpu_ring_write(ring, 0xDEADBEEF);
1283 amdgpu_ring_commit(ring);
1284
1285 for (i = 0; i < adev->usec_timeout; i++) {
1286 tmp = RREG32(scratch);
1287 if (tmp == 0xDEADBEEF)
1288 break;
1289 DRM_UDELAY(1);
1290 }
1291 if (i < adev->usec_timeout) {
1292 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1293 } else {
1294 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1295 ring->idx, scratch, tmp);
1296 r = -EINVAL;
1297 }
1298 amdgpu_gfx_scratch_free(adev, scratch);
1299 return r;
1300}
1301
1302static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1303{
1304 /* flush hdp cache */
1305 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1306 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1307 WRITE_DATA_DST_SEL(0)));
1308 amdgpu_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL);
1309 amdgpu_ring_write(ring, 0);
1310 amdgpu_ring_write(ring, 0x1);
1311}
1312
1313/**
1314 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1315 *
1316 * @adev: amdgpu_device pointer
1317 * @ridx: amdgpu ring index
1318 *
1319 * Emits an hdp invalidate on the cp.
1320 */
1321static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1322{
1323 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1324 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1325 WRITE_DATA_DST_SEL(0)));
1326 amdgpu_ring_write(ring, HDP_DEBUG0);
1327 amdgpu_ring_write(ring, 0);
1328 amdgpu_ring_write(ring, 0x1);
1329}
1330
1331static void gfx_v6_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
1332 u64 seq, unsigned flags)
1333{
1334 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1335 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1336 /* flush read cache over gart */
1337 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1338 amdgpu_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1339 amdgpu_ring_write(ring, 0);
1340 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1341 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1342 PACKET3_TC_ACTION_ENA |
1343 PACKET3_SH_KCACHE_ACTION_ENA |
1344 PACKET3_SH_ICACHE_ACTION_ENA);
1345 amdgpu_ring_write(ring, 0xFFFFFFFF);
1346 amdgpu_ring_write(ring, 0);
1347 amdgpu_ring_write(ring, 10); /* poll interval */
1348 /* EVENT_WRITE_EOP - flush caches, send int */
1349 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1350 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1351 amdgpu_ring_write(ring, addr & 0xfffffffc);
1352 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1353 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
1354 amdgpu_ring_write(ring, lower_32_bits(seq));
1355 amdgpu_ring_write(ring, upper_32_bits(seq));
1356}
1357
1358static void gfx_v6_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
1359 u64 addr, u64 seq,
1360 unsigned flags)
1361{
1362 gfx_v6_0_ring_emit_fence_gfx(ring, addr, seq, flags);
1363}
1364
1365
1366static void gfx_v6_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
1367 struct amdgpu_ib *ib,
1368 unsigned vm_id, bool ctx_switch)
1369{
1370 u32 header, control = 0;
1371
1372 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1373 if (ctx_switch) {
1374 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1375 amdgpu_ring_write(ring, 0);
1376 }
1377
1378 if (ib->flags & AMDGPU_IB_FLAG_CE)
1379 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1380 else
1381 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1382
1383 control |= ib->length_dw | (vm_id << 24);
1384
1385 amdgpu_ring_write(ring, header);
1386 amdgpu_ring_write(ring,
1387#ifdef __BIG_ENDIAN
1388 (2 << 0) |
1389#endif
1390 (ib->gpu_addr & 0xFFFFFFFC));
1391 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1392 amdgpu_ring_write(ring, control);
1393}
1394
1395static void gfx_v6_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
1396 struct amdgpu_ib *ib,
1397 unsigned vm_id, bool ctx_switch)
1398{
1399 gfx_v6_0_ring_emit_ib_gfx(ring, ib, vm_id, ctx_switch);
1400}
1401
1402/**
1403 * gfx_v6_0_ring_test_ib - basic ring IB test
1404 *
1405 * @ring: amdgpu_ring structure holding ring information
1406 *
1407 * Allocate an IB and execute it on the gfx ring (SI).
1408 * Provides a basic gfx ring test to verify that IBs are working.
1409 * Returns 0 on success, error on failure.
1410 */
1411static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1412{
1413 struct amdgpu_device *adev = ring->adev;
1414 struct amdgpu_ib ib;
1415 struct fence *f = NULL;
1416 uint32_t scratch;
1417 uint32_t tmp = 0;
1418 long r;
1419
1420 r = amdgpu_gfx_scratch_get(adev, &scratch);
1421 if (r) {
1422 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1423 return r;
1424 }
1425 WREG32(scratch, 0xCAFEDEAD);
1426 memset(&ib, 0, sizeof(ib));
1427 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1428 if (r) {
1429 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1430 goto err1;
1431 }
1432 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1433 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1434 ib.ptr[2] = 0xDEADBEEF;
1435 ib.length_dw = 3;
1436
1437 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
1438 if (r)
1439 goto err2;
1440
1441 r = fence_wait_timeout(f, false, timeout);
1442 if (r == 0) {
1443 DRM_ERROR("amdgpu: IB test timed out\n");
1444 r = -ETIMEDOUT;
1445 goto err2;
1446 } else if (r < 0) {
1447 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1448 goto err2;
1449 }
1450 tmp = RREG32(scratch);
1451 if (tmp == 0xDEADBEEF) {
1452 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1453 r = 0;
1454 } else {
1455 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1456 scratch, tmp);
1457 r = -EINVAL;
1458 }
1459
1460err2:
1461 amdgpu_ib_free(adev, &ib, NULL);
1462 fence_put(f);
1463err1:
1464 amdgpu_gfx_scratch_free(adev, scratch);
1465 return r;
1466}
1467
1468static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1469{
1470 int i;
1471 if (enable)
1472 WREG32(CP_ME_CNTL, 0);
1473 else {
1474 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1475 WREG32(SCRATCH_UMSK, 0);
1476 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1477 adev->gfx.gfx_ring[i].ready = false;
1478 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1479 adev->gfx.compute_ring[i].ready = false;
1480 }
1481 udelay(50);
1482}
1483
1484static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1485{
1486 unsigned i;
1487 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1488 const struct gfx_firmware_header_v1_0 *ce_hdr;
1489 const struct gfx_firmware_header_v1_0 *me_hdr;
1490 const __le32 *fw_data;
1491 u32 fw_size;
1492
1493 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1494 return -EINVAL;
1495
1496 gfx_v6_0_cp_gfx_enable(adev, false);
1497 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1498 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1499 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1500
1501 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1502 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1503 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1504
1505 /* PFP */
1506 fw_data = (const __le32 *)
1507 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1508 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1509 WREG32(CP_PFP_UCODE_ADDR, 0);
1510 for (i = 0; i < fw_size; i++)
1511 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1512 WREG32(CP_PFP_UCODE_ADDR, 0);
1513
1514 /* CE */
1515 fw_data = (const __le32 *)
1516 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1517 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1518 WREG32(CP_CE_UCODE_ADDR, 0);
1519 for (i = 0; i < fw_size; i++)
1520 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1521 WREG32(CP_CE_UCODE_ADDR, 0);
1522
1523 /* ME */
1524 fw_data = (const __be32 *)
1525 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1526 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1527 WREG32(CP_ME_RAM_WADDR, 0);
1528 for (i = 0; i < fw_size; i++)
1529 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1530 WREG32(CP_ME_RAM_WADDR, 0);
1531
1532
1533 WREG32(CP_PFP_UCODE_ADDR, 0);
1534 WREG32(CP_CE_UCODE_ADDR, 0);
1535 WREG32(CP_ME_RAM_WADDR, 0);
1536 WREG32(CP_ME_RAM_RADDR, 0);
1537 return 0;
1538}
1539
1540static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1541{
1542 const struct cs_section_def *sect = NULL;
1543 const struct cs_extent_def *ext = NULL;
1544 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1545 int r, i;
1546
1547 r = amdgpu_ring_alloc(ring, 7 + 4);
1548 if (r) {
1549 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1550 return r;
1551 }
1552 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1553 amdgpu_ring_write(ring, 0x1);
1554 amdgpu_ring_write(ring, 0x0);
1555 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
1556 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1557 amdgpu_ring_write(ring, 0);
1558 amdgpu_ring_write(ring, 0);
1559
1560 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1561 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1562 amdgpu_ring_write(ring, 0xc000);
1563 amdgpu_ring_write(ring, 0xe000);
1564 amdgpu_ring_commit(ring);
1565
1566 gfx_v6_0_cp_gfx_enable(adev, true);
1567
1568 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
1569 if (r) {
1570 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1571 return r;
1572 }
1573
1574 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1575 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1576
1577 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1578 for (ext = sect->section; ext->extent != NULL; ++ext) {
1579 if (sect->id == SECT_CONTEXT) {
1580 amdgpu_ring_write(ring,
1581 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1582 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1583 for (i = 0; i < ext->reg_count; i++)
1584 amdgpu_ring_write(ring, ext->extent[i]);
1585 }
1586 }
1587 }
1588
1589 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1590 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1591
1592 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1593 amdgpu_ring_write(ring, 0);
1594
1595 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1596 amdgpu_ring_write(ring, 0x00000316);
1597 amdgpu_ring_write(ring, 0x0000000e);
1598 amdgpu_ring_write(ring, 0x00000010);
1599
1600 amdgpu_ring_commit(ring);
1601
1602 return 0;
1603}
1604
1605static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
1606{
1607 struct amdgpu_ring *ring;
1608 u32 tmp;
1609 u32 rb_bufsz;
1610 int r;
1611 u64 rptr_addr;
1612
1613 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1614 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1615
1616 /* Set the write pointer delay */
1617 WREG32(CP_RB_WPTR_DELAY, 0);
1618
1619 WREG32(CP_DEBUG, 0);
1620 WREG32(SCRATCH_ADDR, 0);
1621
1622 /* ring 0 - compute and gfx */
1623 /* Set ring buffer size */
1624 ring = &adev->gfx.gfx_ring[0];
1625 rb_bufsz = order_base_2(ring->ring_size / 8);
1626 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1627
1628#ifdef __BIG_ENDIAN
1629 tmp |= BUF_SWAP_32BIT;
1630#endif
1631 WREG32(CP_RB0_CNTL, tmp);
1632
1633 /* Initialize the ring buffer's read and write pointers */
1634 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1635 ring->wptr = 0;
1636 WREG32(CP_RB0_WPTR, ring->wptr);
1637
1638 /* set the wb address whether it's enabled or not */
1639 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1640 WREG32(CP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1641 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1642
1643 WREG32(SCRATCH_UMSK, 0);
1644
1645 mdelay(1);
1646 WREG32(CP_RB0_CNTL, tmp);
1647
1648 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1649
1650 /* start the rings */
1651 gfx_v6_0_cp_gfx_start(adev);
1652 ring->ready = true;
1653 r = amdgpu_ring_test_ring(ring);
1654 if (r) {
1655 ring->ready = false;
1656 return r;
1657 }
1658
1659 return 0;
1660}
1661
1662static u32 gfx_v6_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
1663{
1664 u32 rptr;
1665
1666 rptr = ring->adev->wb.wb[ring->rptr_offs];
1667
1668 return rptr;
1669}
1670
1671static u32 gfx_v6_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
1672{
1673 struct amdgpu_device *adev = ring->adev;
1674 u32 wptr;
1675
1676 wptr = RREG32(CP_RB0_WPTR);
1677
1678 return wptr;
1679}
1680
1681static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
1682{
1683 struct amdgpu_device *adev = ring->adev;
1684
1685 WREG32(CP_RB0_WPTR, ring->wptr);
1686 (void)RREG32(CP_RB0_WPTR);
1687}
1688
1689static u32 gfx_v6_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
1690{
1691 u32 rptr = ring->adev->wb.wb[ring->rptr_offs];
1692
1693 return rptr;
1694}
1695
1696static u32 gfx_v6_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
1697{
1698 struct amdgpu_device *adev = ring->adev;
1699 u32 wptr;
1700
1701 if (ring == &adev->gfx.compute_ring[0]) {
1702 wptr = RREG32(CP_RB1_WPTR);
1703 } else if (ring == &adev->gfx.compute_ring[1]) {
1704 wptr = RREG32(CP_RB2_WPTR);
1705 } else {
1706 BUG();
1707 }
1708
1709 return wptr;
1710}
1711
1712static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
1713{
1714 struct amdgpu_device *adev = ring->adev;
1715
1716 if (ring == &adev->gfx.compute_ring[0]) {
1717 WREG32(CP_RB1_WPTR, ring->wptr);
1718 (void)RREG32(CP_RB1_WPTR);
1719 } else if (ring == &adev->gfx.compute_ring[1]) {
1720 WREG32(CP_RB2_WPTR, ring->wptr);
1721 (void)RREG32(CP_RB2_WPTR);
1722 } else {
1723 BUG();
1724 }
1725
1726}
1727
2cd46ad2
KW		 1728static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
1729{
1730 struct amdgpu_ring *ring;
1731 u32 tmp;
1732 u32 rb_bufsz;
1733 int r;
1734 u64 rptr_addr;
1735
1736 /* ring1 - compute only */
1737 /* Set ring buffer size */
1738
1739 ring = &adev->gfx.compute_ring[0];
1740 rb_bufsz = order_base_2(ring->ring_size / 8);
1741 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1742#ifdef __BIG_ENDIAN
1743 tmp |= BUF_SWAP_32BIT;
1744#endif
1745 WREG32(CP_RB1_CNTL, tmp);
1746
1747 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1748 ring->wptr = 0;
1749 WREG32(CP_RB1_WPTR, ring->wptr);
1750
1751
1752 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1753 WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
1754 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1755
1756 mdelay(1);
1757 WREG32(CP_RB1_CNTL, tmp);
1758
1759 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1760
1761 ring = &adev->gfx.compute_ring[1];
1762 rb_bufsz = order_base_2(ring->ring_size / 8);
1763 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1764#ifdef __BIG_ENDIAN
1765 tmp |= BUF_SWAP_32BIT;
1766#endif
1767 WREG32(CP_RB2_CNTL, tmp);
1768
1769 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1770 ring->wptr = 0;
1771 WREG32(CP_RB2_WPTR, ring->wptr);
1772 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1773 WREG32(CP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
1774 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
1775
1776 mdelay(1);
1777 WREG32(CP_RB2_CNTL, tmp);
1778
1779 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1780
1781 adev->gfx.compute_ring[0].ready = true;
1782 adev->gfx.compute_ring[1].ready = true;
1783
1784 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[0]);
1785 if (r) {
1786 adev->gfx.compute_ring[0].ready = false;
1787 return r;
1788 }
1789
1790 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[1]);
1791 if (r) {
1792 adev->gfx.compute_ring[1].ready = false;
1793 return r;
1794 }
1795
1796 return 0;
1797}
1798
1799static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
1800{
1801 gfx_v6_0_cp_gfx_enable(adev, enable);
1802}
1803
1804static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
1805{
1806 int r;
1807
1808 r = gfx_v6_0_cp_gfx_load_microcode(adev);
1809
1810 return r;
1811
1812}
1813
1814static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1815 bool enable)
1816{
1817 u32 tmp = RREG32(CP_INT_CNTL_RING0);
1818 u32 mask;
1819 int i;
1820
1821 if (enable)
1822 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1823 else
1824 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1825 WREG32(CP_INT_CNTL_RING0, tmp);
1826
1827 if (!enable) {
1828 /* read a gfx register */
1829 tmp = RREG32(DB_DEPTH_INFO);
1830
1831 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
1832 for (i = 0; i < adev->usec_timeout; i++) {
1833 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
1834 break;
1835 udelay(1);
1836 }
1837 }
1838}
1839
1840static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
1841{
1842 int r;
1843
1844 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
1845
1846 r = gfx_v6_0_cp_load_microcode(adev);
1847 if (r)
1848 return r;
1849
1850 r = gfx_v6_0_cp_gfx_resume(adev);
1851 if (r)
1852 return r;
1853 r = gfx_v6_0_cp_compute_resume(adev);
1854 if (r)
1855 return r;
1856
1857 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
1858
1859 return 0;
1860}
1861
1862static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1863{
1864 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1865 uint32_t seq = ring->fence_drv.sync_seq;
1866 uint64_t addr = ring->fence_drv.gpu_addr;
1867
1868 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1869 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
1870 WAIT_REG_MEM_FUNCTION(3) | /* equal */
1871 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
1872 amdgpu_ring_write(ring, addr & 0xfffffffc);
1873 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1874 amdgpu_ring_write(ring, seq);
1875 amdgpu_ring_write(ring, 0xffffffff);
1876 amdgpu_ring_write(ring, 4); /* poll interval */
1877
1878 if (usepfp) {
1879 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1880 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1881 amdgpu_ring_write(ring, 0);
1882 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1883 amdgpu_ring_write(ring, 0);
1884 }
1885}
1886
1887static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1888 unsigned vm_id, uint64_t pd_addr)
1889{
1890 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
1891
1892 /* write new base address */
1893 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1894 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1895 WRITE_DATA_DST_SEL(0)));
1896 if (vm_id < 8) {
1897 amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
1898 } else {
1899 amdgpu_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
1900 }
1901 amdgpu_ring_write(ring, 0);
1902 amdgpu_ring_write(ring, pd_addr >> 12);
1903
1904 /* bits 0-15 are the VM contexts0-15 */
1905 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1906 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1907 WRITE_DATA_DST_SEL(0)));
1908 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1909 amdgpu_ring_write(ring, 0);
1910 amdgpu_ring_write(ring, 1 << vm_id);
1911
1912 /* wait for the invalidate to complete */
1913 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1914 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
1915 WAIT_REG_MEM_ENGINE(0))); /* me */
1916 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
1917 amdgpu_ring_write(ring, 0);
1918 amdgpu_ring_write(ring, 0); /* ref */
1919 amdgpu_ring_write(ring, 0); /* mask */
1920 amdgpu_ring_write(ring, 0x20); /* poll interval */
1921
1922 if (usepfp) {
1923 /* sync PFP to ME, otherwise we might get invalid PFP reads */
1924 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
1925 amdgpu_ring_write(ring, 0x0);
1926
1927 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
1928 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1929 amdgpu_ring_write(ring, 0);
1930 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1931 amdgpu_ring_write(ring, 0);
1932 }
1933}
1934
1935
1936static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
1937{
1938 int r;
1939
1940 if (adev->gfx.rlc.save_restore_obj) {
1941 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
1942 if (unlikely(r != 0))
1943 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
1944 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
1945 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
1946
1947 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
1948 adev->gfx.rlc.save_restore_obj = NULL;
1949 }
1950
1951 if (adev->gfx.rlc.clear_state_obj) {
1952 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1953 if (unlikely(r != 0))
1954 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
1955 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1956 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1957
1958 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
1959 adev->gfx.rlc.clear_state_obj = NULL;
1960 }
1961
1962 if (adev->gfx.rlc.cp_table_obj) {
1963 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
1964 if (unlikely(r != 0))
1965 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
1966 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
1967 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1968
1969 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
1970 adev->gfx.rlc.cp_table_obj = NULL;
1971 }
1972}
1973
1974static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
1975{
1976 const u32 *src_ptr;
1977 volatile u32 *dst_ptr;
1978 u32 dws, i;
1979 u64 reg_list_mc_addr;
1980 const struct cs_section_def *cs_data;
1981 int r;
1982
1983 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
1984 adev->gfx.rlc.reg_list_size =
1985 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
1986
1987 adev->gfx.rlc.cs_data = si_cs_data;
1988 src_ptr = adev->gfx.rlc.reg_list;
1989 dws = adev->gfx.rlc.reg_list_size;
1990 cs_data = adev->gfx.rlc.cs_data;
1991
1992 if (src_ptr) {
1993 /* save restore block */
1994 if (adev->gfx.rlc.save_restore_obj == NULL) {
1995
1996 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
1997 AMDGPU_GEM_DOMAIN_VRAM,
1998 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1999 NULL, NULL,
2000 &adev->gfx.rlc.save_restore_obj);
2001
2002 if (r) {
2003 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
2004 return r;
2005 }
2006 }
2007
2008 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2009 if (unlikely(r != 0)) {
2010 gfx_v6_0_rlc_fini(adev);
2011 return r;
2012 }
2013 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
2014 &adev->gfx.rlc.save_restore_gpu_addr);
2015 if (r) {
2016 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2017 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
2018 gfx_v6_0_rlc_fini(adev);
2019 return r;
2020 }
2021
2022 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
2023 if (r) {
2024 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
2025 gfx_v6_0_rlc_fini(adev);
2026 return r;
2027 }
2028 /* write the sr buffer */
2029 dst_ptr = adev->gfx.rlc.sr_ptr;
2030 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2031 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2032 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2033 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2034 }
2035
2036 if (cs_data) {
2037 /* clear state block */
2038 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2039 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2040
2041 if (adev->gfx.rlc.clear_state_obj == NULL) {
2042 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2043 AMDGPU_GEM_DOMAIN_VRAM,
2044 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2045 NULL, NULL,
2046 &adev->gfx.rlc.clear_state_obj);
2047
2048 if (r) {
2049 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2050 gfx_v6_0_rlc_fini(adev);
2051 return r;
2052 }
2053 }
2054 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2055 if (unlikely(r != 0)) {
2056 gfx_v6_0_rlc_fini(adev);
2057 return r;
2058 }
2059 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
2060 &adev->gfx.rlc.clear_state_gpu_addr);
2061 if (r) {
2062 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2063 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
2064 gfx_v6_0_rlc_fini(adev);
2065 return r;
2066 }
2067
2068 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
2069 if (r) {
2070 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
2071 gfx_v6_0_rlc_fini(adev);
2072 return r;
2073 }
2074 /* set up the cs buffer */
2075 dst_ptr = adev->gfx.rlc.cs_ptr;
2076 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2077 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2078 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2079 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2080 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2081 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2082 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2083 }
2084
2085 return 0;
2086}
2087
2088static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2089{
2090 u32 tmp;
2091
2092 tmp = RREG32(RLC_LB_CNTL);
2093 if (enable)
2094 tmp |= LOAD_BALANCE_ENABLE;
2095 else
2096 tmp &= ~LOAD_BALANCE_ENABLE;
2097 WREG32(RLC_LB_CNTL, tmp);
2098
2099 if (!enable) {
2100 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2101 WREG32(SPI_LB_CU_MASK, 0x00ff);
2102 }
2103
2104}
2105
2106static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2107{
2108 int i;
2109
2110 for (i = 0; i < adev->usec_timeout; i++) {
2111 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
2112 break;
2113 udelay(1);
2114 }
2115
2116 for (i = 0; i < adev->usec_timeout; i++) {
2117 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
2118 break;
2119 udelay(1);
2120 }
2121}
2122
2123static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2124{
2125 u32 tmp;
2126
2127 tmp = RREG32(RLC_CNTL);
2128 if (tmp != rlc)
2129 WREG32(RLC_CNTL, rlc);
2130}
2131
2132static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2133{
2134 u32 data, orig;
2135
2136 orig = data = RREG32(RLC_CNTL);
2137
2138 if (data & RLC_ENABLE) {
2139 data &= ~RLC_ENABLE;
2140 WREG32(RLC_CNTL, data);
2141
2142 gfx_v6_0_wait_for_rlc_serdes(adev);
2143 }
2144
2145 return orig;
2146}
2147
2148static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2149{
2150 WREG32(RLC_CNTL, 0);
2151
2152 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2153
2154 gfx_v6_0_wait_for_rlc_serdes(adev);
2155}
2156
2157static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2158{
2159 WREG32(RLC_CNTL, RLC_ENABLE);
2160
2161 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2162
2163 udelay(50);
2164}
2165
2166static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2167{
2168 u32 tmp = RREG32(GRBM_SOFT_RESET);
2169
2170 tmp |= SOFT_RESET_RLC;
2171 WREG32(GRBM_SOFT_RESET, tmp);
2172 udelay(50);
2173 tmp &= ~SOFT_RESET_RLC;
2174 WREG32(GRBM_SOFT_RESET, tmp);
2175 udelay(50);
2176}
2177
2178static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2179{
2180 u32 tmp;
2181
2182 /* Enable LBPW only for DDR3 */
2183 tmp = RREG32(MC_SEQ_MISC0);
2184 if ((tmp & 0xF0000000) == 0xB0000000)
2185 return true;
2186 return false;
2187}
2188static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2189{
2190}
2191
2192static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2193{
2194 u32 i;
2195 const struct rlc_firmware_header_v1_0 *hdr;
2196 const __le32 *fw_data;
2197 u32 fw_size;
2198
2199
2200 if (!adev->gfx.rlc_fw)
2201 return -EINVAL;
2202
2203 gfx_v6_0_rlc_stop(adev);
2204
2205 gfx_v6_0_rlc_reset(adev);
2206
2207 gfx_v6_0_init_pg(adev);
2208
2209 gfx_v6_0_init_cg(adev);
2210
2211 WREG32(RLC_RL_BASE, 0);
2212 WREG32(RLC_RL_SIZE, 0);
2213 WREG32(RLC_LB_CNTL, 0);
2214 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
2215 WREG32(RLC_LB_CNTR_INIT, 0);
2216 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
2217
2218 WREG32(RLC_MC_CNTL, 0);
2219 WREG32(RLC_UCODE_CNTL, 0);
2220
2221 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2222 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2223 fw_data = (const __le32 *)
2224 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2225
2226 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2227
2228 for (i = 0; i < fw_size; i++) {
2229 WREG32(RLC_UCODE_ADDR, i);
2230 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
2231 }
2232 WREG32(RLC_UCODE_ADDR, 0);
2233
2234 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2235
2236 gfx_v6_0_rlc_start(adev);
2237
2238 return 0;
2239}
2240
2241static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2242{
2243 u32 data, orig, tmp;
2244
2245 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
2246
2247 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2248 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2249
2250 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
2251
2252 tmp = gfx_v6_0_halt_rlc(adev);
2253
2254 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2255 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2256 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
2257
2258 gfx_v6_0_wait_for_rlc_serdes(adev);
2259
2260 gfx_v6_0_update_rlc(adev, tmp);
2261
2262 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
2263
2264 data |= CGCG_EN | CGLS_EN;
2265 } else {
2266 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2267
2268 RREG32(CB_CGTT_SCLK_CTRL);
2269 RREG32(CB_CGTT_SCLK_CTRL);
2270 RREG32(CB_CGTT_SCLK_CTRL);
2271 RREG32(CB_CGTT_SCLK_CTRL);
2272
2273 data &= ~(CGCG_EN | CGLS_EN);
2274 }
2275
2276 if (orig != data)
2277 WREG32(RLC_CGCG_CGLS_CTRL, data);
2278
2279}
2280
2281static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2282{
2283
2284 u32 data, orig, tmp = 0;
2285
2286 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2287 orig = data = RREG32(CGTS_SM_CTRL_REG);
2288 data = 0x96940200;
2289 if (orig != data)
2290 WREG32(CGTS_SM_CTRL_REG, data);
2291
2292 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2293 orig = data = RREG32(CP_MEM_SLP_CNTL);
2294 data |= CP_MEM_LS_EN;
2295 if (orig != data)
2296 WREG32(CP_MEM_SLP_CNTL, data);
2297 }
2298
2299 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2300 data &= 0xffffffc0;
2301 if (orig != data)
2302 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2303
2304 tmp = gfx_v6_0_halt_rlc(adev);
2305
2306 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2307 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2308 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
2309
2310 gfx_v6_0_update_rlc(adev, tmp);
2311 } else {
2312 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
2313 data |= 0x00000003;
2314 if (orig != data)
2315 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
2316
2317 data = RREG32(CP_MEM_SLP_CNTL);
2318 if (data & CP_MEM_LS_EN) {
2319 data &= ~CP_MEM_LS_EN;
2320 WREG32(CP_MEM_SLP_CNTL, data);
2321 }
2322 orig = data = RREG32(CGTS_SM_CTRL_REG);
2323 data |= LS_OVERRIDE | OVERRIDE;
2324 if (orig != data)
2325 WREG32(CGTS_SM_CTRL_REG, data);
2326
2327 tmp = gfx_v6_0_halt_rlc(adev);
2328
2329 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2330 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2331 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
2332
2333 gfx_v6_0_update_rlc(adev, tmp);
2334 }
2335}
2336/*
2337static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2338 bool enable)
2339{
2340 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2341 if (enable) {
2342 gfx_v6_0_enable_mgcg(adev, true);
2343 gfx_v6_0_enable_cgcg(adev, true);
2344 } else {
2345 gfx_v6_0_enable_cgcg(adev, false);
2346 gfx_v6_0_enable_mgcg(adev, false);
2347 }
2348 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2349}
2350*/
2351static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2352 bool enable)
2353{
2354}
2355
2356static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2357 bool enable)
2358{
2359}
2360
2361static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2362{
2363 u32 data, orig;
2364
2365 orig = data = RREG32(RLC_PG_CNTL);
2366 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2367 data &= ~0x8000;
2368 else
2369 data |= 0x8000;
2370 if (orig != data)
2371 WREG32(RLC_PG_CNTL, data);
2372}
2373
2374static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2375{
2376}
2377/*
2378static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2379{
2380 const __le32 *fw_data;
2381 volatile u32 *dst_ptr;
2382 int me, i, max_me = 4;
2383 u32 bo_offset = 0;
2384 u32 table_offset, table_size;
2385
2386 if (adev->asic_type == CHIP_KAVERI)
2387 max_me = 5;
2388
2389 if (adev->gfx.rlc.cp_table_ptr == NULL)
2390 return;
2391
2392 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2393 for (me = 0; me < max_me; me++) {
2394 if (me == 0) {
2395 const struct gfx_firmware_header_v1_0 *hdr =
2396 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2397 fw_data = (const __le32 *)
2398 (adev->gfx.ce_fw->data +
2399 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2400 table_offset = le32_to_cpu(hdr->jt_offset);
2401 table_size = le32_to_cpu(hdr->jt_size);
2402 } else if (me == 1) {
2403 const struct gfx_firmware_header_v1_0 *hdr =
2404 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2405 fw_data = (const __le32 *)
2406 (adev->gfx.pfp_fw->data +
2407 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2408 table_offset = le32_to_cpu(hdr->jt_offset);
2409 table_size = le32_to_cpu(hdr->jt_size);
2410 } else if (me == 2) {
2411 const struct gfx_firmware_header_v1_0 *hdr =
2412 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2413 fw_data = (const __le32 *)
2414 (adev->gfx.me_fw->data +
2415 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2416 table_offset = le32_to_cpu(hdr->jt_offset);
2417 table_size = le32_to_cpu(hdr->jt_size);
2418 } else if (me == 3) {
2419 const struct gfx_firmware_header_v1_0 *hdr =
2420 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2421 fw_data = (const __le32 *)
2422 (adev->gfx.mec_fw->data +
2423 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2424 table_offset = le32_to_cpu(hdr->jt_offset);
2425 table_size = le32_to_cpu(hdr->jt_size);
2426 } else {
2427 const struct gfx_firmware_header_v1_0 *hdr =
2428 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2429 fw_data = (const __le32 *)
2430 (adev->gfx.mec2_fw->data +
2431 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2432 table_offset = le32_to_cpu(hdr->jt_offset);
2433 table_size = le32_to_cpu(hdr->jt_size);
2434 }
2435
2436 for (i = 0; i < table_size; i ++) {
2437 dst_ptr[bo_offset + i] =
2438 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2439 }
2440
2441 bo_offset += table_size;
2442 }
2443}
2444*/
2445static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2446 bool enable)
2447{
2448
2449 u32 tmp;
2450
2451 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2452 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
2453 WREG32(RLC_TTOP_D, tmp);
2454
2455 tmp = RREG32(RLC_PG_CNTL);
2456 tmp |= GFX_PG_ENABLE;
2457 WREG32(RLC_PG_CNTL, tmp);
2458
2459 tmp = RREG32(RLC_AUTO_PG_CTRL);
2460 tmp |= AUTO_PG_EN;
2461 WREG32(RLC_AUTO_PG_CTRL, tmp);
2462 } else {
2463 tmp = RREG32(RLC_AUTO_PG_CTRL);
2464 tmp &= ~AUTO_PG_EN;
2465 WREG32(RLC_AUTO_PG_CTRL, tmp);
2466
2467 tmp = RREG32(DB_RENDER_CONTROL);
2468 }
2469}
2470
2471static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2472 u32 se, u32 sh)
2473{
2474
2475 u32 mask = 0, tmp, tmp1;
2476 int i;
2477
2478 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
2479 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2480 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2481 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2482
2483 tmp &= 0xffff0000;
2484
2485 tmp |= tmp1;
2486 tmp >>= 16;
2487
2488 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
2489 mask <<= 1;
2490 mask |= 1;
2491 }
2492
2493 return (~tmp) & mask;
2494}
2495
2496static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2497{
2498 u32 i, j, k, active_cu_number = 0;
2499
2500 u32 mask, counter, cu_bitmap;
2501 u32 tmp = 0;
2502
2503 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2504 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2505 mask = 1;
2506 cu_bitmap = 0;
2507 counter = 0;
2508 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2509 if (gfx_v6_0_get_cu_active_bitmap(adev, i, j) & mask) {
2510 if (counter < 2)
2511 cu_bitmap |= mask;
2512 counter++;
2513 }
2514 mask <<= 1;
2515 }
2516
2517 active_cu_number += counter;
2518 tmp |= (cu_bitmap << (i * 16 + j * 8));
2519 }
2520 }
2521
2522 WREG32(RLC_PG_AO_CU_MASK, tmp);
2523
2524 tmp = RREG32(RLC_MAX_PG_CU);
2525 tmp &= ~MAX_PU_CU_MASK;
2526 tmp |= MAX_PU_CU(active_cu_number);
2527 WREG32(RLC_MAX_PG_CU, tmp);
2528}
2529
2530static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2531 bool enable)
2532{
2533 u32 data, orig;
2534
2535 orig = data = RREG32(RLC_PG_CNTL);
2536 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2537 data |= STATIC_PER_CU_PG_ENABLE;
2538 else
2539 data &= ~STATIC_PER_CU_PG_ENABLE;
2540 if (orig != data)
2541 WREG32(RLC_PG_CNTL, data);
2542}
2543
2544static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2545 bool enable)
2546{
2547 u32 data, orig;
2548
2549 orig = data = RREG32(RLC_PG_CNTL);
2550 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2551 data |= DYN_PER_CU_PG_ENABLE;
2552 else
2553 data &= ~DYN_PER_CU_PG_ENABLE;
2554 if (orig != data)
2555 WREG32(RLC_PG_CNTL, data);
2556}
2557
2558static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2559{
2560 u32 tmp;
2561
2562 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2563
2564 tmp = RREG32(RLC_PG_CNTL);
2565 tmp |= GFX_PG_SRC;
2566 WREG32(RLC_PG_CNTL, tmp);
2567
2568 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2569
2570 tmp = RREG32(RLC_AUTO_PG_CTRL);
2571
2572 tmp &= ~GRBM_REG_SGIT_MASK;
2573 tmp |= GRBM_REG_SGIT(0x700);
2574 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
2575 WREG32(RLC_AUTO_PG_CTRL, tmp);
2576}
2577
2578static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2579{
2580 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2581 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2582 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2583}
2584
2585static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2586{
2587 u32 count = 0;
2588 const struct cs_section_def *sect = NULL;
2589 const struct cs_extent_def *ext = NULL;
2590
2591 if (adev->gfx.rlc.cs_data == NULL)
2592 return 0;
2593
2594 /* begin clear state */
2595 count += 2;
2596 /* context control state */
2597 count += 3;
2598
2599 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2600 for (ext = sect->section; ext->extent != NULL; ++ext) {
2601 if (sect->id == SECT_CONTEXT)
2602 count += 2 + ext->reg_count;
2603 else
2604 return 0;
2605 }
2606 }
2607 /* pa_sc_raster_config */
2608 count += 3;
2609 /* end clear state */
2610 count += 2;
2611 /* clear state */
2612 count += 2;
2613
2614 return count;
2615}
2616
2617static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2618 volatile u32 *buffer)
2619{
2620 u32 count = 0, i;
2621 const struct cs_section_def *sect = NULL;
2622 const struct cs_extent_def *ext = NULL;
2623
2624 if (adev->gfx.rlc.cs_data == NULL)
2625 return;
2626 if (buffer == NULL)
2627 return;
2628
2629 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2630 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2631
2632 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2633 buffer[count++] = cpu_to_le32(0x80000000);
2634 buffer[count++] = cpu_to_le32(0x80000000);
2635
2636 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2637 for (ext = sect->section; ext->extent != NULL; ++ext) {
2638 if (sect->id == SECT_CONTEXT) {
2639 buffer[count++] =
2640 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2641 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2642 for (i = 0; i < ext->reg_count; i++)
2643 buffer[count++] = cpu_to_le32(ext->extent[i]);
2644 } else {
2645 return;
2646 }
2647 }
2648 }
2649
2650 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2651 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2652
2653 switch (adev->asic_type) {
2654 case CHIP_TAHITI:
2655 case CHIP_PITCAIRN:
2656 buffer[count++] = cpu_to_le32(0x2a00126a);
2657 break;
2658 case CHIP_VERDE:
2659 buffer[count++] = cpu_to_le32(0x0000124a);
2660 break;
2661 case CHIP_OLAND:
2662 buffer[count++] = cpu_to_le32(0x00000082);
2663 break;
2664 case CHIP_HAINAN:
2665 buffer[count++] = cpu_to_le32(0x00000000);
2666 break;
2667 default:
2668 buffer[count++] = cpu_to_le32(0x00000000);
2669 break;
2670 }
2671
2672 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2673 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2674
2675 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2676 buffer[count++] = cpu_to_le32(0);
2677}
2678
2679static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2680{
2681 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2682 AMD_PG_SUPPORT_GFX_SMG |
2683 AMD_PG_SUPPORT_GFX_DMG |
2684 AMD_PG_SUPPORT_CP |
2685 AMD_PG_SUPPORT_GDS |
2686 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2687 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2688 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2689 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2690 gfx_v6_0_init_gfx_cgpg(adev);
2691 gfx_v6_0_enable_cp_pg(adev, true);
2692 gfx_v6_0_enable_gds_pg(adev, true);
2693 } else {
2694 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2695 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2696
2697 }
2698 gfx_v6_0_init_ao_cu_mask(adev);
2699 gfx_v6_0_update_gfx_pg(adev, true);
2700 } else {
2701
2702 WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2703 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2704 }
2705}
2706
2707static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2708{
2709 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2710 AMD_PG_SUPPORT_GFX_SMG |
2711 AMD_PG_SUPPORT_GFX_DMG |
2712 AMD_PG_SUPPORT_CP |
2713 AMD_PG_SUPPORT_GDS |
2714 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2715 gfx_v6_0_update_gfx_pg(adev, false);
2716 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2717 gfx_v6_0_enable_cp_pg(adev, false);
2718 gfx_v6_0_enable_gds_pg(adev, false);
2719 }
2720 }
2721}
2722
2723static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2724{
2725 uint64_t clock;
2726
2727 mutex_lock(&adev->gfx.gpu_clock_mutex);
2728 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2729 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
2730 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2731 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2732 return clock;
2733}
2734
2735static void gfx_v6_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
2736 uint32_t vmid,
2737 uint32_t gds_base, uint32_t gds_size,
2738 uint32_t gws_base, uint32_t gws_size,
2739 uint32_t oa_base, uint32_t oa_size)
2740{
2741}
2742
2743static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
2744 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
2745 .select_se_sh = &gfx_v6_0_select_se_sh,
2746};
2747
2748static int gfx_v6_0_early_init(void *handle)
2749{
2750 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2751
2752 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
2753 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
2754 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
2755 gfx_v6_0_set_ring_funcs(adev);
2756 gfx_v6_0_set_irq_funcs(adev);
2757
2758 return 0;
2759}
2760
2761static int gfx_v6_0_sw_init(void *handle)
2762{
2763 struct amdgpu_ring *ring;
2764 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2765 int i, r;
2766
2767 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
2768 if (r)
2769 return r;
2770
2771 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
2772 if (r)
2773 return r;
2774
2775 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
2776 if (r)
2777 return r;
2778
2779 gfx_v6_0_scratch_init(adev);
2780
2781 r = gfx_v6_0_init_microcode(adev);
2782 if (r) {
2783 DRM_ERROR("Failed to load gfx firmware!\n");
2784 return r;
2785 }
2786
2787 r = gfx_v6_0_rlc_init(adev);
2788 if (r) {
2789 DRM_ERROR("Failed to init rlc BOs!\n");
2790 return r;
2791 }
2792
2793 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2794 ring = &adev->gfx.gfx_ring[i];
2795 ring->ring_obj = NULL;
2796 sprintf(ring->name, "gfx");
2797 r = amdgpu_ring_init(adev, ring, 1024,
2798 0x80000000, 0xf,
2799 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
2800 AMDGPU_RING_TYPE_GFX);
2801 if (r)
2802 return r;
2803 }
2804
2805 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2806 unsigned irq_type;
2807
2808 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
2809 DRM_ERROR("Too many (%d) compute rings!\n", i);
2810 break;
2811 }
2812 ring = &adev->gfx.compute_ring[i];
2813 ring->ring_obj = NULL;
2814 ring->use_doorbell = false;
2815 ring->doorbell_index = 0;
2816 ring->me = 1;
2817 ring->pipe = i;
2818 ring->queue = i;
2819 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
2820 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2821 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
2822 0x80000000, 0xf,
2823 &adev->gfx.eop_irq, irq_type,
2824 AMDGPU_RING_TYPE_COMPUTE);
2825 if (r)
2826 return r;
2827 }
2828
2829 return r;
2830}
2831
2832static int gfx_v6_0_sw_fini(void *handle)
2833{
2834 int i;
2835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2836
2837 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
2838 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
2839 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
2840
2841 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2842 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2843 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2844 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2845
2cd46ad2
KW		 2846 gfx_v6_0_rlc_fini(adev);
2847
2848 return 0;
2849}
2850
2851static int gfx_v6_0_hw_init(void *handle)
2852{
2853 int r;
2854 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2855
2856 gfx_v6_0_gpu_init(adev);
2857
2858 r = gfx_v6_0_rlc_resume(adev);
2859 if (r)
2860 return r;
2861
2862 r = gfx_v6_0_cp_resume(adev);
2863 if (r)
2864 return r;
2865
2866 adev->gfx.ce_ram_size = 0x8000;
2867
2868 return r;
2869}
2870
2871static int gfx_v6_0_hw_fini(void *handle)
2872{
2873 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2874
2875 gfx_v6_0_cp_enable(adev, false);
2876 gfx_v6_0_rlc_stop(adev);
2877 gfx_v6_0_fini_pg(adev);
2878
2879 return 0;
2880}
2881
2882static int gfx_v6_0_suspend(void *handle)
2883{
2884 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2885
2886 return gfx_v6_0_hw_fini(adev);
2887}
2888
2889static int gfx_v6_0_resume(void *handle)
2890{
2891 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2892
2893 return gfx_v6_0_hw_init(adev);
2894}
2895
2896static bool gfx_v6_0_is_idle(void *handle)
2897{
2898 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2899
2900 if (RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
2901 return false;
2902 else
2903 return true;
2904}
2905
2906static int gfx_v6_0_wait_for_idle(void *handle)
2907{
2908 unsigned i;
2909 u32 tmp;
2910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2911
2912 for (i = 0; i < adev->usec_timeout; i++) {
2913 tmp = RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
2914
2915 if (!tmp)
2916 return 0;
2917 udelay(1);
2918 }
2919 return -ETIMEDOUT;
2920}
2921
2922static int gfx_v6_0_soft_reset(void *handle)
2923{
2924 return 0;
2925}
2926
2927static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
2928 enum amdgpu_interrupt_state state)
2929{
2930 u32 cp_int_cntl;
2931
2932 switch (state) {
2933 case AMDGPU_IRQ_STATE_DISABLE:
2934 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2935 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2936 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2937 break;
2938 case AMDGPU_IRQ_STATE_ENABLE:
2939 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2940 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2941 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
2942 break;
2943 default:
2944 break;
2945 }
2946}
2947
2948static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
2949 int ring,
2950 enum amdgpu_interrupt_state state)
2951{
2952 u32 cp_int_cntl;
2953 switch (state){
2954 case AMDGPU_IRQ_STATE_DISABLE:
2955 if (ring == 0) {
2956 cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
2957 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2958 WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
2959 break;
2960 } else {
2961 cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
2962 cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2963 WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
2964 break;
2965
2966 }
2967 case AMDGPU_IRQ_STATE_ENABLE:
2968 if (ring == 0) {
2969 cp_int_cntl = RREG32(CP_INT_CNTL_RING1);
2970 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2971 WREG32(CP_INT_CNTL_RING1, cp_int_cntl);
2972 break;
2973 } else {
2974 cp_int_cntl = RREG32(CP_INT_CNTL_RING2);
2975 cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK;
2976 WREG32(CP_INT_CNTL_RING2, cp_int_cntl);
2977 break;
2978
2979 }
2980
2981 default:
2982 BUG();
2983 break;
2984
2985 }
2986}
2987
2988static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
2989 struct amdgpu_irq_src *src,
2990 unsigned type,
2991 enum amdgpu_interrupt_state state)
2992{
2993 u32 cp_int_cntl;
2994
2995 switch (state) {
2996 case AMDGPU_IRQ_STATE_DISABLE:
2997 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
2998 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
2999 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3000 break;
3001 case AMDGPU_IRQ_STATE_ENABLE:
3002 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3003 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3004 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3005 break;
3006 default:
3007 break;
3008 }
3009
3010 return 0;
3011}
3012
3013static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3014 struct amdgpu_irq_src *src,
3015 unsigned type,
3016 enum amdgpu_interrupt_state state)
3017{
3018 u32 cp_int_cntl;
3019
3020 switch (state) {
3021 case AMDGPU_IRQ_STATE_DISABLE:
3022 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3023 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3024 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3025 break;
3026 case AMDGPU_IRQ_STATE_ENABLE:
3027 cp_int_cntl = RREG32(CP_INT_CNTL_RING0);
3028 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3029 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3030 break;
3031 default:
3032 break;
3033 }
3034
3035 return 0;
3036}
3037
3038static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3039 struct amdgpu_irq_src *src,
3040 unsigned type,
3041 enum amdgpu_interrupt_state state)
3042{
3043 switch (type) {
3044 case AMDGPU_CP_IRQ_GFX_EOP:
3045 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3046 break;
3047 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3048 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3049 break;
3050 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3051 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3052 break;
3053 default:
3054 break;
3055 }
3056 return 0;
3057}
3058
3059static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3060 struct amdgpu_irq_src *source,
3061 struct amdgpu_iv_entry *entry)
3062{
3063 switch (entry->ring_id) {
3064 case 0:
3065 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3066 break;
3067 case 1:
3068 case 2:
3069 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id -1]);
3070 break;
3071 default:
3072 break;
3073 }
3074 return 0;
3075}
3076
3077static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3078 struct amdgpu_irq_src *source,
3079 struct amdgpu_iv_entry *entry)
3080{
3081 DRM_ERROR("Illegal register access in command stream\n");
3082 schedule_work(&adev->reset_work);
3083 return 0;
3084}
3085
3086static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3087 struct amdgpu_irq_src *source,
3088 struct amdgpu_iv_entry *entry)
3089{
3090 DRM_ERROR("Illegal instruction in command stream\n");
3091 schedule_work(&adev->reset_work);
3092 return 0;
3093}
3094
3095static int gfx_v6_0_set_clockgating_state(void *handle,
3096 enum amd_clockgating_state state)
3097{
3098 bool gate = false;
3099 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3100
3101 if (state == AMD_CG_STATE_GATE)
3102 gate = true;
3103
3104 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3105 if (gate) {
3106 gfx_v6_0_enable_mgcg(adev, true);
3107 gfx_v6_0_enable_cgcg(adev, true);
3108 } else {
3109 gfx_v6_0_enable_cgcg(adev, false);
3110 gfx_v6_0_enable_mgcg(adev, false);
3111 }
3112 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3113
3114 return 0;
3115}
3116
3117static int gfx_v6_0_set_powergating_state(void *handle,
3118 enum amd_powergating_state state)
3119{
3120 bool gate = false;
3121 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3122
3123 if (state == AMD_PG_STATE_GATE)
3124 gate = true;
3125
3126 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3127 AMD_PG_SUPPORT_GFX_SMG |
3128 AMD_PG_SUPPORT_GFX_DMG |
3129 AMD_PG_SUPPORT_CP |
3130 AMD_PG_SUPPORT_GDS |
3131 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3132 gfx_v6_0_update_gfx_pg(adev, gate);
3133 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3134 gfx_v6_0_enable_cp_pg(adev, gate);
3135 gfx_v6_0_enable_gds_pg(adev, gate);
3136 }
3137 }
3138
3139 return 0;
3140}
3141
3142const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3143 .name = "gfx_v6_0",
3144 .early_init = gfx_v6_0_early_init,
3145 .late_init = NULL,
3146 .sw_init = gfx_v6_0_sw_init,
3147 .sw_fini = gfx_v6_0_sw_fini,
3148 .hw_init = gfx_v6_0_hw_init,
3149 .hw_fini = gfx_v6_0_hw_fini,
3150 .suspend = gfx_v6_0_suspend,
3151 .resume = gfx_v6_0_resume,
3152 .is_idle = gfx_v6_0_is_idle,
3153 .wait_for_idle = gfx_v6_0_wait_for_idle,
3154 .soft_reset = gfx_v6_0_soft_reset,
3155 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3156 .set_powergating_state = gfx_v6_0_set_powergating_state,
3157};
3158
3159static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3160 .get_rptr = gfx_v6_0_ring_get_rptr_gfx,
3161 .get_wptr = gfx_v6_0_ring_get_wptr_gfx,
3162 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3163 .parse_cs = NULL,
3164 .emit_ib = gfx_v6_0_ring_emit_ib_gfx,
3165 .emit_fence = gfx_v6_0_ring_emit_fence_gfx,
3166 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3167 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3168 .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
3169 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3170 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3171 .test_ring = gfx_v6_0_ring_test_ring,
3172 .test_ib = gfx_v6_0_ring_test_ib,
3173 .insert_nop = amdgpu_ring_insert_nop,
3174};
3175
3176static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3177 .get_rptr = gfx_v6_0_ring_get_rptr_compute,
3178 .get_wptr = gfx_v6_0_ring_get_wptr_compute,
3179 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3180 .parse_cs = NULL,
3181 .emit_ib = gfx_v6_0_ring_emit_ib_compute,
3182 .emit_fence = gfx_v6_0_ring_emit_fence_compute,
3183 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3184 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3185 .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
3186 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3187 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3188 .test_ring = gfx_v6_0_ring_test_ring,
3189 .test_ib = gfx_v6_0_ring_test_ib,
3190 .insert_nop = amdgpu_ring_insert_nop,
3191};
3192
3193static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3194{
3195 int i;
3196
3197 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3198 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3199 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3200 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3201}
3202
3203static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3204 .set = gfx_v6_0_set_eop_interrupt_state,
3205 .process = gfx_v6_0_eop_irq,
3206};
3207
3208static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3209 .set = gfx_v6_0_set_priv_reg_fault_state,
3210 .process = gfx_v6_0_priv_reg_irq,
3211};
3212
3213static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3214 .set = gfx_v6_0_set_priv_inst_fault_state,
3215 .process = gfx_v6_0_priv_inst_irq,
3216};
3217
3218static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3219{
3220 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3221 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3222
3223 adev->gfx.priv_reg_irq.num_types = 1;
3224 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3225
3226 adev->gfx.priv_inst_irq.num_types = 1;
3227 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3228}
3229
3230static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3231{
3232 int i, j, k, counter, active_cu_number = 0;
3233 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3234 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3235
3236 memset(cu_info, 0, sizeof(*cu_info));
3237
3238 mutex_lock(&adev->grbm_idx_mutex);
3239 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3240 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3241 mask = 1;
3242 ao_bitmap = 0;
3243 counter = 0;
3244 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3245 bitmap = gfx_v6_0_get_cu_active_bitmap(adev, i, j);
3246 cu_info->bitmap[i][j] = bitmap;
3247
3248 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
3249 if (bitmap & mask) {
3250 if (counter < 2)
3251 ao_bitmap |= mask;
3252 counter ++;
3253 }
3254 mask <<= 1;
3255 }
3256 active_cu_number += counter;
3257 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3258 }
3259 }
3260 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3261 mutex_unlock(&adev->grbm_idx_mutex);
3262
3263 cu_info->number = active_cu_number;
3264 cu_info->ao_cu_mask = ao_cu_mask;
3265}
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