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drm/amdgpu: Change AMDGPU_CSA_SIZE to 128K
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v6_0.c
CommitLineData
2cd46ad2
KW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h"
689957b1 28#include "clearstate_si.h"
25069e06
TSD		 29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gca/gfx_6_0_d.h"
34#include "gca/gfx_6_0_sh_mask.h"
35#include "gmc/gmc_6_0_d.h"
36#include "gmc/gmc_6_0_sh_mask.h"
37#include "dce/dce_6_0_d.h"
38#include "dce/dce_6_0_sh_mask.h"
39#include "gca/gfx_7_2_enum.h"
40#include "si_enums.h"
4fef88bd 41#include "si.h"
2cd46ad2
KW		 42
43static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
44static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
45static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
46
8eaf2b1f
AD		 47MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin");
48MODULE_FIRMWARE("amdgpu/tahiti_me.bin");
49MODULE_FIRMWARE("amdgpu/tahiti_ce.bin");
50MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin");
2cd46ad2 51
8eaf2b1f
AD		 52MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin");
53MODULE_FIRMWARE("amdgpu/pitcairn_me.bin");
54MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin");
55MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin");
2cd46ad2 56
8eaf2b1f
AD		 57MODULE_FIRMWARE("amdgpu/verde_pfp.bin");
58MODULE_FIRMWARE("amdgpu/verde_me.bin");
59MODULE_FIRMWARE("amdgpu/verde_ce.bin");
60MODULE_FIRMWARE("amdgpu/verde_rlc.bin");
2cd46ad2 61
8eaf2b1f
AD		 62MODULE_FIRMWARE("amdgpu/oland_pfp.bin");
63MODULE_FIRMWARE("amdgpu/oland_me.bin");
64MODULE_FIRMWARE("amdgpu/oland_ce.bin");
65MODULE_FIRMWARE("amdgpu/oland_rlc.bin");
2cd46ad2 66
8eaf2b1f
AD		 67MODULE_FIRMWARE("amdgpu/hainan_pfp.bin");
68MODULE_FIRMWARE("amdgpu/hainan_me.bin");
69MODULE_FIRMWARE("amdgpu/hainan_ce.bin");
70MODULE_FIRMWARE("amdgpu/hainan_rlc.bin");
2cd46ad2
KW		 71
72static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
73static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
74//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
75static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
76
25069e06
TSD		 77#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
78#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
79#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
80#define MICRO_TILE_MODE(x) ((x) << 0)
81#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
82#define BANK_WIDTH(x) ((x) << 14)
83#define BANK_HEIGHT(x) ((x) << 16)
84#define MACRO_TILE_ASPECT(x) ((x) << 18)
85#define NUM_BANKS(x) ((x) << 20)
2cd46ad2
KW		 86
87static const u32 verde_rlc_save_restore_register_list[] =
88{
89 (0x8000 << 16) | (0x98f4 >> 2),
90 0x00000000,
91 (0x8040 << 16) | (0x98f4 >> 2),
92 0x00000000,
93 (0x8000 << 16) | (0xe80 >> 2),
94 0x00000000,
95 (0x8040 << 16) | (0xe80 >> 2),
96 0x00000000,
97 (0x8000 << 16) | (0x89bc >> 2),
98 0x00000000,
99 (0x8040 << 16) | (0x89bc >> 2),
100 0x00000000,
101 (0x8000 << 16) | (0x8c1c >> 2),
102 0x00000000,
103 (0x8040 << 16) | (0x8c1c >> 2),
104 0x00000000,
105 (0x9c00 << 16) | (0x98f0 >> 2),
106 0x00000000,
107 (0x9c00 << 16) | (0xe7c >> 2),
108 0x00000000,
109 (0x8000 << 16) | (0x9148 >> 2),
110 0x00000000,
111 (0x8040 << 16) | (0x9148 >> 2),
112 0x00000000,
113 (0x9c00 << 16) | (0x9150 >> 2),
114 0x00000000,
115 (0x9c00 << 16) | (0x897c >> 2),
116 0x00000000,
117 (0x9c00 << 16) | (0x8d8c >> 2),
118 0x00000000,
119 (0x9c00 << 16) | (0xac54 >> 2),
120 0X00000000,
121 0x3,
122 (0x9c00 << 16) | (0x98f8 >> 2),
123 0x00000000,
124 (0x9c00 << 16) | (0x9910 >> 2),
125 0x00000000,
126 (0x9c00 << 16) | (0x9914 >> 2),
127 0x00000000,
128 (0x9c00 << 16) | (0x9918 >> 2),
129 0x00000000,
130 (0x9c00 << 16) | (0x991c >> 2),
131 0x00000000,
132 (0x9c00 << 16) | (0x9920 >> 2),
133 0x00000000,
134 (0x9c00 << 16) | (0x9924 >> 2),
135 0x00000000,
136 (0x9c00 << 16) | (0x9928 >> 2),
137 0x00000000,
138 (0x9c00 << 16) | (0x992c >> 2),
139 0x00000000,
140 (0x9c00 << 16) | (0x9930 >> 2),
141 0x00000000,
142 (0x9c00 << 16) | (0x9934 >> 2),
143 0x00000000,
144 (0x9c00 << 16) | (0x9938 >> 2),
145 0x00000000,
146 (0x9c00 << 16) | (0x993c >> 2),
147 0x00000000,
148 (0x9c00 << 16) | (0x9940 >> 2),
149 0x00000000,
150 (0x9c00 << 16) | (0x9944 >> 2),
151 0x00000000,
152 (0x9c00 << 16) | (0x9948 >> 2),
153 0x00000000,
154 (0x9c00 << 16) | (0x994c >> 2),
155 0x00000000,
156 (0x9c00 << 16) | (0x9950 >> 2),
157 0x00000000,
158 (0x9c00 << 16) | (0x9954 >> 2),
159 0x00000000,
160 (0x9c00 << 16) | (0x9958 >> 2),
161 0x00000000,
162 (0x9c00 << 16) | (0x995c >> 2),
163 0x00000000,
164 (0x9c00 << 16) | (0x9960 >> 2),
165 0x00000000,
166 (0x9c00 << 16) | (0x9964 >> 2),
167 0x00000000,
168 (0x9c00 << 16) | (0x9968 >> 2),
169 0x00000000,
170 (0x9c00 << 16) | (0x996c >> 2),
171 0x00000000,
172 (0x9c00 << 16) | (0x9970 >> 2),
173 0x00000000,
174 (0x9c00 << 16) | (0x9974 >> 2),
175 0x00000000,
176 (0x9c00 << 16) | (0x9978 >> 2),
177 0x00000000,
178 (0x9c00 << 16) | (0x997c >> 2),
179 0x00000000,
180 (0x9c00 << 16) | (0x9980 >> 2),
181 0x00000000,
182 (0x9c00 << 16) | (0x9984 >> 2),
183 0x00000000,
184 (0x9c00 << 16) | (0x9988 >> 2),
185 0x00000000,
186 (0x9c00 << 16) | (0x998c >> 2),
187 0x00000000,
188 (0x9c00 << 16) | (0x8c00 >> 2),
189 0x00000000,
190 (0x9c00 << 16) | (0x8c14 >> 2),
191 0x00000000,
192 (0x9c00 << 16) | (0x8c04 >> 2),
193 0x00000000,
194 (0x9c00 << 16) | (0x8c08 >> 2),
195 0x00000000,
196 (0x8000 << 16) | (0x9b7c >> 2),
197 0x00000000,
198 (0x8040 << 16) | (0x9b7c >> 2),
199 0x00000000,
200 (0x8000 << 16) | (0xe84 >> 2),
201 0x00000000,
202 (0x8040 << 16) | (0xe84 >> 2),
203 0x00000000,
204 (0x8000 << 16) | (0x89c0 >> 2),
205 0x00000000,
206 (0x8040 << 16) | (0x89c0 >> 2),
207 0x00000000,
208 (0x8000 << 16) | (0x914c >> 2),
209 0x00000000,
210 (0x8040 << 16) | (0x914c >> 2),
211 0x00000000,
212 (0x8000 << 16) | (0x8c20 >> 2),
213 0x00000000,
214 (0x8040 << 16) | (0x8c20 >> 2),
215 0x00000000,
216 (0x8000 << 16) | (0x9354 >> 2),
217 0x00000000,
218 (0x8040 << 16) | (0x9354 >> 2),
219 0x00000000,
220 (0x9c00 << 16) | (0x9060 >> 2),
221 0x00000000,
222 (0x9c00 << 16) | (0x9364 >> 2),
223 0x00000000,
224 (0x9c00 << 16) | (0x9100 >> 2),
225 0x00000000,
226 (0x9c00 << 16) | (0x913c >> 2),
227 0x00000000,
228 (0x8000 << 16) | (0x90e0 >> 2),
229 0x00000000,
230 (0x8000 << 16) | (0x90e4 >> 2),
231 0x00000000,
232 (0x8000 << 16) | (0x90e8 >> 2),
233 0x00000000,
234 (0x8040 << 16) | (0x90e0 >> 2),
235 0x00000000,
236 (0x8040 << 16) | (0x90e4 >> 2),
237 0x00000000,
238 (0x8040 << 16) | (0x90e8 >> 2),
239 0x00000000,
240 (0x9c00 << 16) | (0x8bcc >> 2),
241 0x00000000,
242 (0x9c00 << 16) | (0x8b24 >> 2),
243 0x00000000,
244 (0x9c00 << 16) | (0x88c4 >> 2),
245 0x00000000,
246 (0x9c00 << 16) | (0x8e50 >> 2),
247 0x00000000,
248 (0x9c00 << 16) | (0x8c0c >> 2),
249 0x00000000,
250 (0x9c00 << 16) | (0x8e58 >> 2),
251 0x00000000,
252 (0x9c00 << 16) | (0x8e5c >> 2),
253 0x00000000,
254 (0x9c00 << 16) | (0x9508 >> 2),
255 0x00000000,
256 (0x9c00 << 16) | (0x950c >> 2),
257 0x00000000,
258 (0x9c00 << 16) | (0x9494 >> 2),
259 0x00000000,
260 (0x9c00 << 16) | (0xac0c >> 2),
261 0x00000000,
262 (0x9c00 << 16) | (0xac10 >> 2),
263 0x00000000,
264 (0x9c00 << 16) | (0xac14 >> 2),
265 0x00000000,
266 (0x9c00 << 16) | (0xae00 >> 2),
267 0x00000000,
268 (0x9c00 << 16) | (0xac08 >> 2),
269 0x00000000,
270 (0x9c00 << 16) | (0x88d4 >> 2),
271 0x00000000,
272 (0x9c00 << 16) | (0x88c8 >> 2),
273 0x00000000,
274 (0x9c00 << 16) | (0x88cc >> 2),
275 0x00000000,
276 (0x9c00 << 16) | (0x89b0 >> 2),
277 0x00000000,
278 (0x9c00 << 16) | (0x8b10 >> 2),
279 0x00000000,
280 (0x9c00 << 16) | (0x8a14 >> 2),
281 0x00000000,
282 (0x9c00 << 16) | (0x9830 >> 2),
283 0x00000000,
284 (0x9c00 << 16) | (0x9834 >> 2),
285 0x00000000,
286 (0x9c00 << 16) | (0x9838 >> 2),
287 0x00000000,
288 (0x9c00 << 16) | (0x9a10 >> 2),
289 0x00000000,
290 (0x8000 << 16) | (0x9870 >> 2),
291 0x00000000,
292 (0x8000 << 16) | (0x9874 >> 2),
293 0x00000000,
294 (0x8001 << 16) | (0x9870 >> 2),
295 0x00000000,
296 (0x8001 << 16) | (0x9874 >> 2),
297 0x00000000,
298 (0x8040 << 16) | (0x9870 >> 2),
299 0x00000000,
300 (0x8040 << 16) | (0x9874 >> 2),
301 0x00000000,
302 (0x8041 << 16) | (0x9870 >> 2),
303 0x00000000,
304 (0x8041 << 16) | (0x9874 >> 2),
305 0x00000000,
306 0x00000000
307};
308
309static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
310{
311 const char *chip_name;
312 char fw_name[30];
313 int err;
314 const struct gfx_firmware_header_v1_0 *cp_hdr;
315 const struct rlc_firmware_header_v1_0 *rlc_hdr;
316
317 DRM_DEBUG("\n");
318
319 switch (adev->asic_type) {
320 case CHIP_TAHITI:
321 chip_name = "tahiti";
322 break;
323 case CHIP_PITCAIRN:
324 chip_name = "pitcairn";
325 break;
326 case CHIP_VERDE:
327 chip_name = "verde";
328 break;
329 case CHIP_OLAND:
330 chip_name = "oland";
331 break;
332 case CHIP_HAINAN:
333 chip_name = "hainan";
334 break;
335 default: BUG();
336 }
337
8eaf2b1f 338 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
2cd46ad2
KW		 339 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
340 if (err)
341 goto out;
342 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
343 if (err)
344 goto out;
345 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
346 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
347 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
348
8eaf2b1f 349 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
2cd46ad2
KW		 350 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
351 if (err)
352 goto out;
353 err = amdgpu_ucode_validate(adev->gfx.me_fw);
354 if (err)
355 goto out;
356 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
357 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
358 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
359
8eaf2b1f 360 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
2cd46ad2
KW		 361 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
362 if (err)
363 goto out;
364 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
365 if (err)
366 goto out;
367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
368 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
369 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
370
8eaf2b1f 371 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
2cd46ad2
KW		 372 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
373 if (err)
374 goto out;
375 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
376 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
377 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
378 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
379
380out:
381 if (err) {
7ca85295 382 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
2cd46ad2
KW		 383 release_firmware(adev->gfx.pfp_fw);
384 adev->gfx.pfp_fw = NULL;
385 release_firmware(adev->gfx.me_fw);
386 adev->gfx.me_fw = NULL;
387 release_firmware(adev->gfx.ce_fw);
388 adev->gfx.ce_fw = NULL;
389 release_firmware(adev->gfx.rlc_fw);
390 adev->gfx.rlc_fw = NULL;
391 }
392 return err;
393}
394
395static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
396{
167327d6
TSD		 397 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
398 u32 reg_offset, split_equal_to_row_size, *tilemode;
399
400 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
401 tilemode = adev->gfx.config.tile_mode_array;
2cd46ad2
KW		 402
403 switch (adev->gfx.config.mem_row_size_in_kb) {
404 case 1:
405 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
406 break;
407 case 2:
408 default:
409 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
410 break;
411 case 4:
412 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
413 break;
414 }
415
3548f9a8 416 if (adev->asic_type == CHIP_VERDE) {
167327d6
TSD		 417 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
418 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
419 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
421 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
424 NUM_BANKS(ADDR_SURF_16_BANK);
425 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
426 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
427 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
428 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
429 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
432 NUM_BANKS(ADDR_SURF_16_BANK);
433 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
434 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
435 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
436 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
437 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
440 NUM_BANKS(ADDR_SURF_16_BANK);
441 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
442 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
443 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
447 NUM_BANKS(ADDR_SURF_8_BANK) |
448 TILE_SPLIT(split_equal_to_row_size);
449 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
450 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
451 PIPE_CONFIG(ADDR_SURF_P4_8x16);
452 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
453 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
454 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
456 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
459 NUM_BANKS(ADDR_SURF_4_BANK);
460 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
461 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
462 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
464 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
466 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
467 NUM_BANKS(ADDR_SURF_4_BANK);
468 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
469 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
475 NUM_BANKS(ADDR_SURF_2_BANK);
476 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
477 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
478 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
479 PIPE_CONFIG(ADDR_SURF_P4_8x16);
480 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
481 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
482 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
483 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
484 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
487 NUM_BANKS(ADDR_SURF_16_BANK);
488 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
489 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
490 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
492 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
495 NUM_BANKS(ADDR_SURF_16_BANK);
496 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
497 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
498 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
499 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
500 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
501 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
502 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
503 NUM_BANKS(ADDR_SURF_16_BANK);
504 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
505 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
506 PIPE_CONFIG(ADDR_SURF_P4_8x16);
507 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
508 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
509 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
510 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
514 NUM_BANKS(ADDR_SURF_16_BANK);
515 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
516 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
517 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
519 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
522 NUM_BANKS(ADDR_SURF_16_BANK);
523 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
524 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
525 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
527 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
530 NUM_BANKS(ADDR_SURF_16_BANK);
531 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
532 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
533 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
534 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
537 NUM_BANKS(ADDR_SURF_16_BANK) |
538 TILE_SPLIT(split_equal_to_row_size);
539 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
540 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
541 PIPE_CONFIG(ADDR_SURF_P4_8x16);
542 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
543 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
544 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
545 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
548 NUM_BANKS(ADDR_SURF_16_BANK) |
549 TILE_SPLIT(split_equal_to_row_size);
550 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
551 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
552 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
556 NUM_BANKS(ADDR_SURF_16_BANK) |
557 TILE_SPLIT(split_equal_to_row_size);
558 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
559 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
560 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
562 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
563 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
564 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
565 NUM_BANKS(ADDR_SURF_8_BANK);
566 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
568 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
569 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
570 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
571 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
572 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
573 NUM_BANKS(ADDR_SURF_8_BANK);
574 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
575 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
576 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
577 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
579 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
580 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
581 NUM_BANKS(ADDR_SURF_4_BANK);
582 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
583 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
584 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
585 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
586 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
587 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
588 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
589 NUM_BANKS(ADDR_SURF_4_BANK);
590 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
591 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
592 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
593 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
597 NUM_BANKS(ADDR_SURF_2_BANK);
598 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
599 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
600 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
602 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
603 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
604 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
605 NUM_BANKS(ADDR_SURF_2_BANK);
606 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
607 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
608 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
609 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
610 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
611 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
612 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
613 NUM_BANKS(ADDR_SURF_2_BANK);
614 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
615 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
616 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
617 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
618 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
621 NUM_BANKS(ADDR_SURF_2_BANK);
622 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
623 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
624 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
625 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
626 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
629 NUM_BANKS(ADDR_SURF_2_BANK);
630 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
631 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
632 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
634 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
637 NUM_BANKS(ADDR_SURF_2_BANK);
638 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
639 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
4cf97582
JD		 640 } else if (adev->asic_type == CHIP_OLAND) {
641 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
643 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
645 NUM_BANKS(ADDR_SURF_16_BANK) |
646 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
649 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
650 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
651 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
652 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
653 NUM_BANKS(ADDR_SURF_16_BANK) |
654 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
657 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
658 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
659 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
660 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
661 NUM_BANKS(ADDR_SURF_16_BANK) |
662 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
665 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
666 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
667 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
668 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
669 NUM_BANKS(ADDR_SURF_16_BANK) |
670 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
673 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
674 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
675 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
676 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
677 NUM_BANKS(ADDR_SURF_16_BANK) |
678 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
681 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
683 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
684 TILE_SPLIT(split_equal_to_row_size) |
685 NUM_BANKS(ADDR_SURF_16_BANK) |
686 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
687 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
688 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
689 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
690 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
691 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
692 TILE_SPLIT(split_equal_to_row_size) |
693 NUM_BANKS(ADDR_SURF_16_BANK) |
694 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
697 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
698 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
699 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
700 TILE_SPLIT(split_equal_to_row_size) |
701 NUM_BANKS(ADDR_SURF_16_BANK) |
702 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
703 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
704 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
705 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
706 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
707 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
708 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
709 NUM_BANKS(ADDR_SURF_16_BANK) |
710 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
711 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
712 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
713 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
714 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
715 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
716 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
717 NUM_BANKS(ADDR_SURF_16_BANK) |
718 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
721 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
722 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
723 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
725 NUM_BANKS(ADDR_SURF_16_BANK) |
726 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
727 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
728 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
729 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
730 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
731 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
732 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
733 NUM_BANKS(ADDR_SURF_16_BANK) |
734 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
737 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
738 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
739 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
740 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
741 NUM_BANKS(ADDR_SURF_16_BANK) |
742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
745 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
746 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
747 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
748 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
749 NUM_BANKS(ADDR_SURF_16_BANK) |
750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
753 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
754 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
755 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
756 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
757 NUM_BANKS(ADDR_SURF_16_BANK) |
758 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
759 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
760 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
761 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
762 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
763 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
764 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
765 NUM_BANKS(ADDR_SURF_16_BANK) |
766 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
767 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
768 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
769 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
770 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
771 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
772 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
773 NUM_BANKS(ADDR_SURF_16_BANK) |
774 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
775 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
776 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
777 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
778 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
779 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
780 TILE_SPLIT(split_equal_to_row_size) |
781 NUM_BANKS(ADDR_SURF_16_BANK) |
782 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
785 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
786 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
787 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
789 NUM_BANKS(ADDR_SURF_16_BANK) |
790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
791 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
792 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
793 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
794 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
795 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
796 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
797 NUM_BANKS(ADDR_SURF_16_BANK) |
798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
801 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
802 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
803 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
804 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
805 NUM_BANKS(ADDR_SURF_16_BANK) |
806 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
807 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
808 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
809 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
810 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
811 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
812 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
813 NUM_BANKS(ADDR_SURF_16_BANK) |
814 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
815 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
816 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
817 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
818 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
819 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
820 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
821 NUM_BANKS(ADDR_SURF_8_BANK) |
822 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
825 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
826 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
827 } else if (adev->asic_type == CHIP_HAINAN) {
167327d6
TSD		 828 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
829 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
830 PIPE_CONFIG(ADDR_SURF_P2) |
831 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
832 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
835 NUM_BANKS(ADDR_SURF_16_BANK);
836 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
837 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
838 PIPE_CONFIG(ADDR_SURF_P2) |
839 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
840 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
843 NUM_BANKS(ADDR_SURF_16_BANK);
844 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
845 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
846 PIPE_CONFIG(ADDR_SURF_P2) |
847 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
848 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
851 NUM_BANKS(ADDR_SURF_16_BANK);
852 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
853 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
854 PIPE_CONFIG(ADDR_SURF_P2) |
855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
858 NUM_BANKS(ADDR_SURF_8_BANK) |
859 TILE_SPLIT(split_equal_to_row_size);
860 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
861 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
862 PIPE_CONFIG(ADDR_SURF_P2);
863 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
864 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
865 PIPE_CONFIG(ADDR_SURF_P2) |
866 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
867 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
868 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
869 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
870 NUM_BANKS(ADDR_SURF_8_BANK);
871 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
872 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
873 PIPE_CONFIG(ADDR_SURF_P2) |
874 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
875 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
876 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
877 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
878 NUM_BANKS(ADDR_SURF_8_BANK);
879 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
880 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
881 PIPE_CONFIG(ADDR_SURF_P2) |
882 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
883 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
884 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
885 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
886 NUM_BANKS(ADDR_SURF_4_BANK);
887 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
888 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
889 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
890 PIPE_CONFIG(ADDR_SURF_P2);
891 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
892 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
893 PIPE_CONFIG(ADDR_SURF_P2) |
894 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
895 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
896 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
897 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
898 NUM_BANKS(ADDR_SURF_16_BANK);
899 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
900 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
901 PIPE_CONFIG(ADDR_SURF_P2) |
902 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
903 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
904 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
905 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
906 NUM_BANKS(ADDR_SURF_16_BANK);
907 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
908 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
909 PIPE_CONFIG(ADDR_SURF_P2) |
910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
911 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
912 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
913 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
914 NUM_BANKS(ADDR_SURF_16_BANK);
915 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
916 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
917 PIPE_CONFIG(ADDR_SURF_P2);
918 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
919 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
920 PIPE_CONFIG(ADDR_SURF_P2) |
921 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
922 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
925 NUM_BANKS(ADDR_SURF_16_BANK);
926 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
927 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
928 PIPE_CONFIG(ADDR_SURF_P2) |
929 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
933 NUM_BANKS(ADDR_SURF_16_BANK);
934 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
935 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
936 PIPE_CONFIG(ADDR_SURF_P2) |
937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
941 NUM_BANKS(ADDR_SURF_16_BANK);
942 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
943 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
944 PIPE_CONFIG(ADDR_SURF_P2) |
945 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
946 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
947 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
948 NUM_BANKS(ADDR_SURF_16_BANK) |
949 TILE_SPLIT(split_equal_to_row_size);
950 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
951 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
952 PIPE_CONFIG(ADDR_SURF_P2);
953 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
954 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
955 PIPE_CONFIG(ADDR_SURF_P2) |
956 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
957 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
958 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
959 NUM_BANKS(ADDR_SURF_16_BANK) |
960 TILE_SPLIT(split_equal_to_row_size);
961 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
962 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
963 PIPE_CONFIG(ADDR_SURF_P2) |
964 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
967 NUM_BANKS(ADDR_SURF_16_BANK) |
968 TILE_SPLIT(split_equal_to_row_size);
969 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
970 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
971 PIPE_CONFIG(ADDR_SURF_P2) |
972 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
973 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
974 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
975 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
976 NUM_BANKS(ADDR_SURF_8_BANK);
977 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
978 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
979 PIPE_CONFIG(ADDR_SURF_P2) |
980 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
981 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
982 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
983 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
984 NUM_BANKS(ADDR_SURF_8_BANK);
985 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
986 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
987 PIPE_CONFIG(ADDR_SURF_P2) |
988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
989 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
992 NUM_BANKS(ADDR_SURF_8_BANK);
993 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
994 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
995 PIPE_CONFIG(ADDR_SURF_P2) |
996 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
997 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
998 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
999 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1000 NUM_BANKS(ADDR_SURF_8_BANK);
1001 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1002 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1003 PIPE_CONFIG(ADDR_SURF_P2) |
1004 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1005 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1006 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1007 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1008 NUM_BANKS(ADDR_SURF_4_BANK);
1009 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1010 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1011 PIPE_CONFIG(ADDR_SURF_P2) |
1012 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1013 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1014 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1015 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1016 NUM_BANKS(ADDR_SURF_4_BANK);
1017 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1018 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1019 PIPE_CONFIG(ADDR_SURF_P2) |
1020 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1021 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1022 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1023 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1024 NUM_BANKS(ADDR_SURF_4_BANK);
1025 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1026 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1027 PIPE_CONFIG(ADDR_SURF_P2) |
1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1029 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1032 NUM_BANKS(ADDR_SURF_4_BANK);
1033 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1034 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1035 PIPE_CONFIG(ADDR_SURF_P2) |
1036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1037 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1038 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1039 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1040 NUM_BANKS(ADDR_SURF_4_BANK);
1041 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1042 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1043 PIPE_CONFIG(ADDR_SURF_P2) |
1044 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1045 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1046 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1047 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1048 NUM_BANKS(ADDR_SURF_4_BANK);
1049 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1050 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
2cd46ad2 1051 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
167327d6
TSD		 1052 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1053 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1059 NUM_BANKS(ADDR_SURF_16_BANK);
1060 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1061 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1064 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1065 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1066 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1067 NUM_BANKS(ADDR_SURF_16_BANK);
1068 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1069 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1071 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1072 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1073 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1074 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1075 NUM_BANKS(ADDR_SURF_16_BANK);
1076 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1077 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1078 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1079 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1082 NUM_BANKS(ADDR_SURF_4_BANK) |
1083 TILE_SPLIT(split_equal_to_row_size);
1084 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1085 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1086 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1087 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1088 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1089 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1091 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1092 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1093 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1094 NUM_BANKS(ADDR_SURF_2_BANK);
1095 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1096 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1099 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1100 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1101 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1102 NUM_BANKS(ADDR_SURF_2_BANK);
1103 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1104 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1105 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1107 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1108 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1109 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1110 NUM_BANKS(ADDR_SURF_2_BANK);
1111 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1112 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1113 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1114 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1115 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1116 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1119 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1120 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1121 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1122 NUM_BANKS(ADDR_SURF_16_BANK);
1123 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1124 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1125 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1126 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1127 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1128 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1129 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1130 NUM_BANKS(ADDR_SURF_16_BANK);
1131 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1132 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1135 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1138 NUM_BANKS(ADDR_SURF_16_BANK);
1139 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1140 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1141 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1142 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1143 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1144 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1149 NUM_BANKS(ADDR_SURF_16_BANK);
1150 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1151 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1152 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1154 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1157 NUM_BANKS(ADDR_SURF_16_BANK);
1158 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1159 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1160 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1162 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1165 NUM_BANKS(ADDR_SURF_16_BANK);
1166 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1167 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1168 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1172 NUM_BANKS(ADDR_SURF_16_BANK) |
1173 TILE_SPLIT(split_equal_to_row_size);
1174 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1175 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1176 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1177 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1178 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1179 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1180 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183 NUM_BANKS(ADDR_SURF_16_BANK) |
1184 TILE_SPLIT(split_equal_to_row_size);
1185 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1186 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1187 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1188 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1191 NUM_BANKS(ADDR_SURF_16_BANK) |
1192 TILE_SPLIT(split_equal_to_row_size);
1193 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1194 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1196 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1197 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1200 NUM_BANKS(ADDR_SURF_4_BANK);
1201 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1202 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1203 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1205 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1208 NUM_BANKS(ADDR_SURF_4_BANK);
1209 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1210 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1211 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1212 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1213 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1216 NUM_BANKS(ADDR_SURF_2_BANK);
1217 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1218 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1219 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1220 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1221 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1222 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1223 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1224 NUM_BANKS(ADDR_SURF_2_BANK);
1225 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1226 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1227 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1228 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1232 NUM_BANKS(ADDR_SURF_2_BANK);
1233 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1234 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1236 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1240 NUM_BANKS(ADDR_SURF_2_BANK);
1241 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1242 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1244 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1245 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1246 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1247 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1248 NUM_BANKS(ADDR_SURF_2_BANK);
1249 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1250 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1251 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1252 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1253 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1256 NUM_BANKS(ADDR_SURF_2_BANK);
1257 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1258 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1259 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1260 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1261 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1264 NUM_BANKS(ADDR_SURF_2_BANK);
1265 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1266 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1267 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1268 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1272 NUM_BANKS(ADDR_SURF_2_BANK);
1273 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1274 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1275 } else {
2cd46ad2
KW		 1276 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1277 }
2cd46ad2
KW		 1278}
1279
1280static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1281 u32 sh_num, u32 instance)
1282{
1283 u32 data;
1284
1285 if (instance == 0xffffffff)
25069e06 1286 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2cd46ad2 1287 else
25069e06 1288 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
2cd46ad2
KW		 1289
1290 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
25069e06
TSD		 1291 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1292 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
2cd46ad2 1293 else if (se_num == 0xffffffff)
25069e06
TSD		 1294 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1295 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
2cd46ad2 1296 else if (sh_num == 0xffffffff)
25069e06
TSD		 1297 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1298 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
2cd46ad2 1299 else
25069e06
TSD		 1300 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1301 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1302 WREG32(mmGRBM_GFX_INDEX, data);
2cd46ad2
KW		 1303}
1304
69dd3d2c 1305static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
2cd46ad2
KW		 1306{
1307 u32 data, mask;
1308
69dd3d2c
FC		 1309 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1310 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
2cd46ad2 1311
69dd3d2c 1312 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
2cd46ad2 1313
378506a7
AD		 1314 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1315 adev->gfx.config.max_sh_per_se);
2cd46ad2 1316
69dd3d2c 1317 return ~data & mask;
2cd46ad2
KW		 1318}
1319
865ab832
HR		 1320static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1321{
1322 switch (adev->asic_type) {
1323 case CHIP_TAHITI:
1324 case CHIP_PITCAIRN:
25069e06
TSD		 1325 *rconf |=
1326 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1327 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1328 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1329 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1330 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1331 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1332 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
865ab832
HR		 1333 break;
1334 case CHIP_VERDE:
25069e06
TSD		 1335 *rconf |=
1336 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1337 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1338 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
865ab832
HR		 1339 break;
1340 case CHIP_OLAND:
25069e06 1341 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
865ab832
HR		 1342 break;
1343 case CHIP_HAINAN:
1344 *rconf |= 0x0;
1345 break;
1346 default:
1347 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1348 break;
1349 }
1350}
1351
1352static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1353 u32 raster_config, unsigned rb_mask,
1354 unsigned num_rb)
1355{
1356 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1357 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1358 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1359 unsigned rb_per_se = num_rb / num_se;
1360 unsigned se_mask[4];
1361 unsigned se;
1362
1363 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1364 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1365 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1366 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1367
1368 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1369 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1370 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1371
1372 for (se = 0; se < num_se; se++) {
1373 unsigned raster_config_se = raster_config;
1374 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1375 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1376 int idx = (se / 2) * 2;
1377
1378 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
25069e06 1379 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
865ab832 1380
5a7bfded 1381 if (!se_mask[idx])
25069e06 1382 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
5a7bfded 1383 else
25069e06 1384 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
865ab832
HR		 1385 }
1386
1387 pkr0_mask &= rb_mask;
1388 pkr1_mask &= rb_mask;
1389 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
25069e06 1390 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
865ab832 1391
5a7bfded 1392 if (!pkr0_mask)
25069e06 1393 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
5a7bfded 1394 else
25069e06 1395 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
865ab832
HR		 1396 }
1397
1398 if (rb_per_se >= 2) {
1399 unsigned rb0_mask = 1 << (se * rb_per_se);
1400 unsigned rb1_mask = rb0_mask << 1;
1401
1402 rb0_mask &= rb_mask;
1403 rb1_mask &= rb_mask;
1404 if (!rb0_mask || !rb1_mask) {
25069e06 1405 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
865ab832 1406
5a7bfded 1407 if (!rb0_mask)
865ab832 1408 raster_config_se |=
25069e06 1409 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
5a7bfded 1410 else
865ab832 1411 raster_config_se |=
25069e06 1412 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
865ab832
HR		 1413 }
1414
1415 if (rb_per_se > 2) {
1416 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1417 rb1_mask = rb0_mask << 1;
1418 rb0_mask &= rb_mask;
1419 rb1_mask &= rb_mask;
1420 if (!rb0_mask || !rb1_mask) {
25069e06 1421 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
865ab832 1422
5a7bfded 1423 if (!rb0_mask)
865ab832 1424 raster_config_se |=
25069e06 1425 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
5a7bfded 1426 else
865ab832 1427 raster_config_se |=
25069e06 1428 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
865ab832
HR		 1429 }
1430 }
1431 }
1432
1433 /* GRBM_GFX_INDEX has a different offset on SI */
1434 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
25069e06 1435 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
865ab832
HR		 1436 }
1437
1438 /* GRBM_GFX_INDEX has a different offset on SI */
1439 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1440}
1441
69dd3d2c 1442static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
2cd46ad2
KW		 1443{
1444 int i, j;
69dd3d2c
FC		 1445 u32 data;
1446 u32 raster_config = 0;
1447 u32 active_rbs = 0;
1448 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1449 adev->gfx.config.max_sh_per_se;
865ab832 1450 unsigned num_rb_pipes;
2cd46ad2 1451
deca1d1f 1452 mutex_lock(&adev->grbm_idx_mutex);
69dd3d2c
FC		 1453 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1454 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2cd46ad2 1455 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
69dd3d2c 1456 data = gfx_v6_0_get_rb_active_bitmap(adev);
2de3aac9
TSD		 1457 active_rbs |= data <<
1458 ((i * adev->gfx.config.max_sh_per_se + j) *
1459 rb_bitmap_width_per_sh);
2cd46ad2
KW		 1460 }
1461 }
1462 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1463
69dd3d2c
FC		 1464 adev->gfx.config.backend_enable_mask = active_rbs;
1465 adev->gfx.config.num_rbs = hweight32(active_rbs);
2cd46ad2 1466
865ab832
HR		 1467 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1468 adev->gfx.config.max_shader_engines, 16);
1469
69dd3d2c
FC		 1470 gfx_v6_0_raster_config(adev, &raster_config);
1471
1472 if (!adev->gfx.config.backend_enable_mask ||
2de3aac9 1473 adev->gfx.config.num_rbs >= num_rb_pipes)
69dd3d2c 1474 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
2de3aac9 1475 else
69dd3d2c
FC		 1476 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1477 adev->gfx.config.backend_enable_mask,
1478 num_rb_pipes);
69dd3d2c
FC		 1479
1480 /* cache the values for userspace */
1481 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1482 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1483 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1484 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1485 RREG32(mmCC_RB_BACKEND_DISABLE);
1486 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1487 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1488 adev->gfx.config.rb_config[i][j].raster_config =
1489 RREG32(mmPA_SC_RASTER_CONFIG);
2cd46ad2 1490 }
2cd46ad2
KW		 1491 }
1492 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 1493 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2 1494}
2cd46ad2 1495
375d6f70
FC		 1496static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1497 u32 bitmap)
2cd46ad2 1498{
375d6f70 1499 u32 data;
2cd46ad2 1500
375d6f70
FC		 1501 if (!bitmap)
1502 return;
2cd46ad2 1503
375d6f70
FC		 1504 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1505 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
2cd46ad2 1506
375d6f70
FC		 1507 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1508}
2cd46ad2 1509
375d6f70
FC		 1510static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1511{
1512 u32 data, mask;
1513
1514 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1515 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1516
378506a7 1517 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
375d6f70 1518 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
2cd46ad2
KW		 1519}
1520
1521
c5dc14fb 1522static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
2cd46ad2
KW		 1523{
1524 int i, j, k;
1525 u32 data, mask;
1526 u32 active_cu = 0;
1527
deca1d1f 1528 mutex_lock(&adev->grbm_idx_mutex);
c5dc14fb
FC		 1529 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1530 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2cd46ad2 1531 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
25069e06 1532 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
375d6f70 1533 active_cu = gfx_v6_0_get_cu_enabled(adev);
2cd46ad2
KW		 1534
1535 mask = 1;
1536 for (k = 0; k < 16; k++) {
1537 mask <<= k;
1538 if (active_cu & mask) {
1539 data &= ~mask;
25069e06 1540 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
2cd46ad2
KW		 1541 break;
1542 }
1543 }
1544 }
1545 }
1546 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 1547 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1548}
1549
df6e2c4a
JZ		 1550static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1551{
ad2fed9a 1552 adev->gfx.config.double_offchip_lds_buf = 0;
df6e2c4a
JZ		 1553}
1554
434e6df2 1555static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
2cd46ad2
KW		 1556{
1557 u32 gb_addr_config = 0;
1558 u32 mc_shared_chmap, mc_arb_ramcfg;
1559 u32 sx_debug_1;
1560 u32 hdp_host_path_cntl;
1561 u32 tmp;
1562
1563 switch (adev->asic_type) {
1564 case CHIP_TAHITI:
1565 adev->gfx.config.max_shader_engines = 2;
1566 adev->gfx.config.max_tile_pipes = 12;
1567 adev->gfx.config.max_cu_per_sh = 8;
1568 adev->gfx.config.max_sh_per_se = 2;
1569 adev->gfx.config.max_backends_per_se = 4;
1570 adev->gfx.config.max_texture_channel_caches = 12;
1571 adev->gfx.config.max_gprs = 256;
1572 adev->gfx.config.max_gs_threads = 32;
1573 adev->gfx.config.max_hw_contexts = 8;
1574
1575 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1576 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1577 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1578 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1579 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1580 break;
1581 case CHIP_PITCAIRN:
1582 adev->gfx.config.max_shader_engines = 2;
1583 adev->gfx.config.max_tile_pipes = 8;
1584 adev->gfx.config.max_cu_per_sh = 5;
1585 adev->gfx.config.max_sh_per_se = 2;
1586 adev->gfx.config.max_backends_per_se = 4;
1587 adev->gfx.config.max_texture_channel_caches = 8;
1588 adev->gfx.config.max_gprs = 256;
1589 adev->gfx.config.max_gs_threads = 32;
1590 adev->gfx.config.max_hw_contexts = 8;
1591
1592 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1593 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1594 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1595 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1596 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1597 break;
2cd46ad2
KW		 1598 case CHIP_VERDE:
1599 adev->gfx.config.max_shader_engines = 1;
1600 adev->gfx.config.max_tile_pipes = 4;
1601 adev->gfx.config.max_cu_per_sh = 5;
1602 adev->gfx.config.max_sh_per_se = 2;
1603 adev->gfx.config.max_backends_per_se = 4;
1604 adev->gfx.config.max_texture_channel_caches = 4;
1605 adev->gfx.config.max_gprs = 256;
1606 adev->gfx.config.max_gs_threads = 32;
1607 adev->gfx.config.max_hw_contexts = 8;
1608
1609 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1610 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1611 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1612 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1613 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1614 break;
1615 case CHIP_OLAND:
1616 adev->gfx.config.max_shader_engines = 1;
1617 adev->gfx.config.max_tile_pipes = 4;
1618 adev->gfx.config.max_cu_per_sh = 6;
1619 adev->gfx.config.max_sh_per_se = 1;
1620 adev->gfx.config.max_backends_per_se = 2;
1621 adev->gfx.config.max_texture_channel_caches = 4;
1622 adev->gfx.config.max_gprs = 256;
1623 adev->gfx.config.max_gs_threads = 16;
1624 adev->gfx.config.max_hw_contexts = 8;
1625
1626 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1627 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1628 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1629 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1630 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1631 break;
1632 case CHIP_HAINAN:
1633 adev->gfx.config.max_shader_engines = 1;
1634 adev->gfx.config.max_tile_pipes = 4;
1635 adev->gfx.config.max_cu_per_sh = 5;
1636 adev->gfx.config.max_sh_per_se = 1;
1637 adev->gfx.config.max_backends_per_se = 1;
1638 adev->gfx.config.max_texture_channel_caches = 2;
1639 adev->gfx.config.max_gprs = 256;
1640 adev->gfx.config.max_gs_threads = 16;
1641 adev->gfx.config.max_hw_contexts = 8;
1642
1643 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1644 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1645 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1646 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1647 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1648 break;
1649 default:
1650 BUG();
1651 break;
1652 }
1653
25069e06
TSD		 1654 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1655 WREG32(mmSRBM_INT_CNTL, 1);
1656 WREG32(mmSRBM_INT_ACK, 1);
2cd46ad2 1657
25069e06 1658 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
2cd46ad2 1659
25069e06 1660 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
6653ebd4
AD		 1661 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1662 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2cd46ad2
KW		 1663
1664 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1665 adev->gfx.config.mem_max_burst_length_bytes = 256;
25069e06 1666 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
2cd46ad2
KW		 1667 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1668 if (adev->gfx.config.mem_row_size_in_kb > 4)
1669 adev->gfx.config.mem_row_size_in_kb = 4;
1670 adev->gfx.config.shader_engine_tile_size = 32;
1671 adev->gfx.config.num_gpus = 1;
1672 adev->gfx.config.multi_gpu_tile_size = 64;
1673
25069e06 1674 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
2cd46ad2
KW		 1675 switch (adev->gfx.config.mem_row_size_in_kb) {
1676 case 1:
1677 default:
25069e06 1678 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
2cd46ad2
KW		 1679 break;
1680 case 2:
25069e06 1681 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
2cd46ad2
KW		 1682 break;
1683 case 4:
25069e06 1684 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
2cd46ad2
KW		 1685 break;
1686 }
0d09a096
FC		 1687 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1688 if (adev->gfx.config.max_shader_engines == 2)
1689 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
2cd46ad2
KW		 1690 adev->gfx.config.gb_addr_config = gb_addr_config;
1691
25069e06
TSD		 1692 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1693 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1694 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1695 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1696 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1697 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1698
2cd46ad2
KW		 1699#if 0
1700 if (adev->has_uvd) {
25069e06
TSD		 1701 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1702 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1703 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2cd46ad2
KW		 1704 }
1705#endif
1706 gfx_v6_0_tiling_mode_table_init(adev);
1707
69dd3d2c 1708 gfx_v6_0_setup_rb(adev);
2cd46ad2 1709
c5dc14fb 1710 gfx_v6_0_setup_spi(adev);
2cd46ad2
KW		 1711
1712 gfx_v6_0_get_cu_info(adev);
df6e2c4a 1713 gfx_v6_0_config_init(adev);
2cd46ad2 1714
25069e06
TSD		 1715 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1716 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1717 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1718 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
2cd46ad2 1719
25069e06
TSD		 1720 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1721 WREG32(mmSX_DEBUG_1, sx_debug_1);
2cd46ad2 1722
25069e06 1723 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
2cd46ad2 1724
25069e06
TSD		 1725 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1726 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1727 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1728 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
2cd46ad2 1729
25069e06
TSD		 1730 WREG32(mmVGT_NUM_INSTANCES, 1);
1731 WREG32(mmCP_PERFMON_CNTL, 0);
1732 WREG32(mmSQ_CONFIG, 0);
1733 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1734 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
2cd46ad2 1735
25069e06
TSD		 1736 WREG32(mmVGT_CACHE_INVALIDATION,
1737 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1738 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2cd46ad2 1739
25069e06
TSD		 1740 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1741 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2cd46ad2 1742
25069e06
TSD		 1743 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1744 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1745 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1746 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1747 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1748 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1749 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1750 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
2cd46ad2 1751
25069e06
TSD		 1752 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1753 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2cd46ad2 1754
25069e06
TSD		 1755 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1756 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2cd46ad2
KW		 1757
1758 udelay(50);
2cd46ad2
KW		 1759}
1760
1761
1762static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1763{
c5c35790 1764 adev->gfx.scratch.num_reg = 8;
25069e06 1765 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
50261151 1766 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
2cd46ad2
KW		 1767}
1768
1769static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1770{
1771 struct amdgpu_device *adev = ring->adev;
1772 uint32_t scratch;
1773 uint32_t tmp = 0;
1774 unsigned i;
1775 int r;
1776
1777 r = amdgpu_gfx_scratch_get(adev, &scratch);
dc9eeff8 1778 if (r)
2cd46ad2 1779 return r;
dc9eeff8 1780
2cd46ad2
KW		 1781 WREG32(scratch, 0xCAFEDEAD);
1782
1783 r = amdgpu_ring_alloc(ring, 3);
dc9eeff8
CK		 1784 if (r)
1785 goto error_free_scratch;
1786
2cd46ad2
KW		 1787 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1788 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1789 amdgpu_ring_write(ring, 0xDEADBEEF);
1790 amdgpu_ring_commit(ring);
1791
1792 for (i = 0; i < adev->usec_timeout; i++) {
1793 tmp = RREG32(scratch);
1794 if (tmp == 0xDEADBEEF)
1795 break;
1796 DRM_UDELAY(1);
1797 }
dc9eeff8
CK		 1798
1799 if (i >= adev->usec_timeout)
1800 r = -ETIMEDOUT;
1801
1802error_free_scratch:
2cd46ad2
KW		 1803 amdgpu_gfx_scratch_free(adev, scratch);
1804 return r;
1805}
1806
45682886
ML		 1807static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1808{
1809 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1810 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1811 EVENT_INDEX(0));
1812}
1813
668f52c3
AD		 1814static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1815 u64 seq, unsigned flags)
2cd46ad2
KW		 1816{
1817 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1818 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1819 /* flush read cache over gart */
1820 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
25069e06 1821 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
2cd46ad2
KW		 1822 amdgpu_ring_write(ring, 0);
1823 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1824 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1825 PACKET3_TC_ACTION_ENA |
1826 PACKET3_SH_KCACHE_ACTION_ENA |
1827 PACKET3_SH_ICACHE_ACTION_ENA);
1828 amdgpu_ring_write(ring, 0xFFFFFFFF);
1829 amdgpu_ring_write(ring, 0);
1830 amdgpu_ring_write(ring, 10); /* poll interval */
1831 /* EVENT_WRITE_EOP - flush caches, send int */
1832 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1833 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1834 amdgpu_ring_write(ring, addr & 0xfffffffc);
1835 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
25069e06
TSD		 1836 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1837 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
2cd46ad2
KW		 1838 amdgpu_ring_write(ring, lower_32_bits(seq));
1839 amdgpu_ring_write(ring, upper_32_bits(seq));
1840}
1841
668f52c3
AD		 1842static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1843 struct amdgpu_ib *ib,
c4f46f22 1844 unsigned vmid, bool ctx_switch)
2cd46ad2
KW		 1845{
1846 u32 header, control = 0;
1847
1848 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1849 if (ctx_switch) {
1850 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1851 amdgpu_ring_write(ring, 0);
1852 }
1853
1854 if (ib->flags & AMDGPU_IB_FLAG_CE)
1855 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1856 else
1857 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1858
c4f46f22 1859 control |= ib->length_dw | (vmid << 24);
2cd46ad2
KW		 1860
1861 amdgpu_ring_write(ring, header);
1862 amdgpu_ring_write(ring,
1863#ifdef __BIG_ENDIAN
1864 (2 << 0) |
1865#endif
1866 (ib->gpu_addr & 0xFFFFFFFC));
1867 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1868 amdgpu_ring_write(ring, control);
1869}
1870
2cd46ad2
KW		 1871/**
1872 * gfx_v6_0_ring_test_ib - basic ring IB test
1873 *
1874 * @ring: amdgpu_ring structure holding ring information
1875 *
1876 * Allocate an IB and execute it on the gfx ring (SI).
1877 * Provides a basic gfx ring test to verify that IBs are working.
1878 * Returns 0 on success, error on failure.
1879 */
1880static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1881{
1882 struct amdgpu_device *adev = ring->adev;
1883 struct amdgpu_ib ib;
f54d1867 1884 struct dma_fence *f = NULL;
2cd46ad2
KW		 1885 uint32_t scratch;
1886 uint32_t tmp = 0;
1887 long r;
1888
1889 r = amdgpu_gfx_scratch_get(adev, &scratch);
98079389 1890 if (r)
2cd46ad2 1891 return r;
98079389 1892
2cd46ad2
KW		 1893 WREG32(scratch, 0xCAFEDEAD);
1894 memset(&ib, 0, sizeof(ib));
1895 r = amdgpu_ib_get(adev, NULL, 256, &ib);
98079389 1896 if (r)
2cd46ad2 1897 goto err1;
98079389 1898
2cd46ad2
KW		 1899 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1900 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1901 ib.ptr[2] = 0xDEADBEEF;
1902 ib.length_dw = 3;
1903
50ddc75e 1904 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2cd46ad2
KW		 1905 if (r)
1906 goto err2;
1907
f54d1867 1908 r = dma_fence_wait_timeout(f, false, timeout);
2cd46ad2 1909 if (r == 0) {
2cd46ad2
KW		 1910 r = -ETIMEDOUT;
1911 goto err2;
1912 } else if (r < 0) {
2cd46ad2
KW		 1913 goto err2;
1914 }
1915 tmp = RREG32(scratch);
98079389 1916 if (tmp == 0xDEADBEEF)
2cd46ad2 1917 r = 0;
98079389 1918 else
2cd46ad2 1919 r = -EINVAL;
2cd46ad2
KW		 1920
1921err2:
1922 amdgpu_ib_free(adev, &ib, NULL);
f54d1867 1923 dma_fence_put(f);
2cd46ad2
KW		 1924err1:
1925 amdgpu_gfx_scratch_free(adev, scratch);
1926 return r;
1927}
1928
1929static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1930{
1931 int i;
25069e06
TSD		 1932 if (enable) {
1933 WREG32(mmCP_ME_CNTL, 0);
1934 } else {
1935 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1936 CP_ME_CNTL__PFP_HALT_MASK |
1937 CP_ME_CNTL__CE_HALT_MASK));
1938 WREG32(mmSCRATCH_UMSK, 0);
2cd46ad2 1939 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
c66ed765 1940 adev->gfx.gfx_ring[i].sched.ready = false;
2cd46ad2 1941 for (i = 0; i < adev->gfx.num_compute_rings; i++)
c66ed765 1942 adev->gfx.compute_ring[i].sched.ready = false;
2cd46ad2
KW		 1943 }
1944 udelay(50);
1945}
1946
1947static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1948{
1949 unsigned i;
1950 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1951 const struct gfx_firmware_header_v1_0 *ce_hdr;
1952 const struct gfx_firmware_header_v1_0 *me_hdr;
1953 const __le32 *fw_data;
1954 u32 fw_size;
1955
1956 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1957 return -EINVAL;
1958
1959 gfx_v6_0_cp_gfx_enable(adev, false);
1960 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1961 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1962 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1963
1964 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1965 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1966 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1967
1968 /* PFP */
1969 fw_data = (const __le32 *)
1970 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1971 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
25069e06 1972 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2cd46ad2 1973 for (i = 0; i < fw_size; i++)
25069e06
TSD		 1974 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1975 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2cd46ad2
KW		 1976
1977 /* CE */
1978 fw_data = (const __le32 *)
1979 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1980 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
25069e06 1981 WREG32(mmCP_CE_UCODE_ADDR, 0);
2cd46ad2 1982 for (i = 0; i < fw_size; i++)
25069e06
TSD		 1983 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1984 WREG32(mmCP_CE_UCODE_ADDR, 0);
2cd46ad2
KW		 1985
1986 /* ME */
1987 fw_data = (const __be32 *)
1988 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1989 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
25069e06 1990 WREG32(mmCP_ME_RAM_WADDR, 0);
2cd46ad2 1991 for (i = 0; i < fw_size; i++)
25069e06
TSD		 1992 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1993 WREG32(mmCP_ME_RAM_WADDR, 0);
2cd46ad2 1994
25069e06
TSD		 1995 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1996 WREG32(mmCP_CE_UCODE_ADDR, 0);
1997 WREG32(mmCP_ME_RAM_WADDR, 0);
1998 WREG32(mmCP_ME_RAM_RADDR, 0);
2cd46ad2
KW		 1999 return 0;
2000}
2001
2002static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2003{
2004 const struct cs_section_def *sect = NULL;
2005 const struct cs_extent_def *ext = NULL;
2006 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2007 int r, i;
2008
2009 r = amdgpu_ring_alloc(ring, 7 + 4);
2010 if (r) {
2011 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2012 return r;
2013 }
2014 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2015 amdgpu_ring_write(ring, 0x1);
2016 amdgpu_ring_write(ring, 0x0);
2017 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2018 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2019 amdgpu_ring_write(ring, 0);
2020 amdgpu_ring_write(ring, 0);
2021
2022 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2023 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2024 amdgpu_ring_write(ring, 0xc000);
2025 amdgpu_ring_write(ring, 0xe000);
2026 amdgpu_ring_commit(ring);
2027
2028 gfx_v6_0_cp_gfx_enable(adev, true);
2029
2030 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2031 if (r) {
2032 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2033 return r;
2034 }
2035
2036 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2037 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2038
2039 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2040 for (ext = sect->section; ext->extent != NULL; ++ext) {
2041 if (sect->id == SECT_CONTEXT) {
2042 amdgpu_ring_write(ring,
2043 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2044 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2045 for (i = 0; i < ext->reg_count; i++)
2046 amdgpu_ring_write(ring, ext->extent[i]);
2047 }
2048 }
2049 }
2050
2051 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2052 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2053
2054 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2055 amdgpu_ring_write(ring, 0);
2056
2057 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2058 amdgpu_ring_write(ring, 0x00000316);
2059 amdgpu_ring_write(ring, 0x0000000e);
2060 amdgpu_ring_write(ring, 0x00000010);
2061
2062 amdgpu_ring_commit(ring);
2063
2064 return 0;
2065}
2066
2067static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2068{
2069 struct amdgpu_ring *ring;
2070 u32 tmp;
2071 u32 rb_bufsz;
2072 int r;
2073 u64 rptr_addr;
2074
25069e06
TSD		 2075 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2076 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2cd46ad2
KW		 2077
2078 /* Set the write pointer delay */
25069e06 2079 WREG32(mmCP_RB_WPTR_DELAY, 0);
2cd46ad2 2080
25069e06
TSD		 2081 WREG32(mmCP_DEBUG, 0);
2082 WREG32(mmSCRATCH_ADDR, 0);
2cd46ad2
KW		 2083
2084 /* ring 0 - compute and gfx */
2085 /* Set ring buffer size */
2086 ring = &adev->gfx.gfx_ring[0];
2087 rb_bufsz = order_base_2(ring->ring_size / 8);
2088 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2089
2090#ifdef __BIG_ENDIAN
2091 tmp |= BUF_SWAP_32BIT;
2092#endif
25069e06 2093 WREG32(mmCP_RB0_CNTL, tmp);
2cd46ad2
KW		 2094
2095 /* Initialize the ring buffer's read and write pointers */
25069e06 2096 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2cd46ad2 2097 ring->wptr = 0;
25069e06 2098 WREG32(mmCP_RB0_WPTR, ring->wptr);
2cd46ad2
KW		 2099
2100 /* set the wb address whether it's enabled or not */
2101 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
25069e06
TSD		 2102 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2103 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2cd46ad2 2104
25069e06 2105 WREG32(mmSCRATCH_UMSK, 0);
2cd46ad2
KW		 2106
2107 mdelay(1);
25069e06 2108 WREG32(mmCP_RB0_CNTL, tmp);
2cd46ad2 2109
25069e06 2110 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2cd46ad2
KW		 2111
2112 /* start the rings */
2113 gfx_v6_0_cp_gfx_start(adev);
c66ed765
AG		 2114 r = amdgpu_ring_test_helper(ring);
2115 if (r)
2cd46ad2 2116 return r;
2cd46ad2
KW		 2117
2118 return 0;
2119}
2120
536fbf94 2121static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2cd46ad2 2122{
4aeacf0f 2123 return ring->adev->wb.wb[ring->rptr_offs];
2cd46ad2
KW		 2124}
2125
536fbf94 2126static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2cd46ad2
KW		 2127{
2128 struct amdgpu_device *adev = ring->adev;
2cd46ad2 2129
832c6ef7 2130 if (ring == &adev->gfx.gfx_ring[0])
25069e06 2131 return RREG32(mmCP_RB0_WPTR);
832c6ef7 2132 else if (ring == &adev->gfx.compute_ring[0])
25069e06 2133 return RREG32(mmCP_RB1_WPTR);
832c6ef7 2134 else if (ring == &adev->gfx.compute_ring[1])
25069e06 2135 return RREG32(mmCP_RB2_WPTR);
832c6ef7
TSD		 2136 else
2137 BUG();
2cd46ad2
KW		 2138}
2139
2140static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2141{
2142 struct amdgpu_device *adev = ring->adev;
2143
536fbf94 2144 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
25069e06 2145 (void)RREG32(mmCP_RB0_WPTR);
2cd46ad2
KW		 2146}
2147
2cd46ad2
KW		 2148static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2149{
2150 struct amdgpu_device *adev = ring->adev;
2151
2152 if (ring == &adev->gfx.compute_ring[0]) {
536fbf94 2153 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
25069e06 2154 (void)RREG32(mmCP_RB1_WPTR);
2cd46ad2 2155 } else if (ring == &adev->gfx.compute_ring[1]) {
536fbf94 2156 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
25069e06 2157 (void)RREG32(mmCP_RB2_WPTR);
2cd46ad2
KW		 2158 } else {
2159 BUG();
2160 }
2161
2162}
2163
2cd46ad2
KW		 2164static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2165{
2166 struct amdgpu_ring *ring;
2167 u32 tmp;
2168 u32 rb_bufsz;
25069e06 2169 int i, r;
2cd46ad2
KW		 2170 u64 rptr_addr;
2171
2172 /* ring1 - compute only */
2173 /* Set ring buffer size */
2174
2175 ring = &adev->gfx.compute_ring[0];
2176 rb_bufsz = order_base_2(ring->ring_size / 8);
2177 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2178#ifdef __BIG_ENDIAN
2179 tmp |= BUF_SWAP_32BIT;
2180#endif
25069e06 2181 WREG32(mmCP_RB1_CNTL, tmp);
2cd46ad2 2182
25069e06 2183 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2cd46ad2 2184 ring->wptr = 0;
25069e06 2185 WREG32(mmCP_RB1_WPTR, ring->wptr);
2cd46ad2 2186
2cd46ad2 2187 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
25069e06
TSD		 2188 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2189 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2cd46ad2
KW		 2190
2191 mdelay(1);
25069e06
TSD		 2192 WREG32(mmCP_RB1_CNTL, tmp);
2193 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2cd46ad2
KW		 2194
2195 ring = &adev->gfx.compute_ring[1];
2196 rb_bufsz = order_base_2(ring->ring_size / 8);
2197 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2198#ifdef __BIG_ENDIAN
2199 tmp |= BUF_SWAP_32BIT;
2200#endif
25069e06 2201 WREG32(mmCP_RB2_CNTL, tmp);
2cd46ad2 2202
25069e06 2203 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2cd46ad2 2204 ring->wptr = 0;
25069e06 2205 WREG32(mmCP_RB2_WPTR, ring->wptr);
2cd46ad2 2206 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
25069e06
TSD		 2207 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2208 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2cd46ad2
KW		 2209
2210 mdelay(1);
25069e06
TSD		 2211 WREG32(mmCP_RB2_CNTL, tmp);
2212 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2cd46ad2 2213
2cd46ad2 2214
25069e06 2215 for (i = 0; i < 2; i++) {
c66ed765 2216 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]);
25069e06
TSD		 2217 if (r)
2218 return r;
2cd46ad2
KW		 2219 }
2220
2221 return 0;
2222}
2223
2224static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2225{
2226 gfx_v6_0_cp_gfx_enable(adev, enable);
2227}
2228
2229static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2230{
4aeacf0f 2231 return gfx_v6_0_cp_gfx_load_microcode(adev);
2cd46ad2
KW		 2232}
2233
2234static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2235 bool enable)
45682886 2236{
25069e06 2237 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2
KW		 2238 u32 mask;
2239 int i;
2240
2241 if (enable)
25069e06
TSD		 2242 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2243 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2cd46ad2 2244 else
25069e06
TSD		 2245 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2246 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2247 WREG32(mmCP_INT_CNTL_RING0, tmp);
2cd46ad2
KW		 2248
2249 if (!enable) {
2250 /* read a gfx register */
25069e06 2251 tmp = RREG32(mmDB_DEPTH_INFO);
2cd46ad2
KW		 2252
2253 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2254 for (i = 0; i < adev->usec_timeout; i++) {
25069e06 2255 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2cd46ad2
KW		 2256 break;
2257 udelay(1);
2258 }
2259 }
2260}
2261
2262static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2263{
2264 int r;
2265
2266 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2267
2268 r = gfx_v6_0_cp_load_microcode(adev);
2269 if (r)
2270 return r;
2271
2272 r = gfx_v6_0_cp_gfx_resume(adev);
2273 if (r)
2274 return r;
2275 r = gfx_v6_0_cp_compute_resume(adev);
2276 if (r)
2277 return r;
2278
2279 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2280
2281 return 0;
2282}
2283
2284static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2285{
21cd942e 2286 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2cd46ad2
KW		 2287 uint32_t seq = ring->fence_drv.sync_seq;
2288 uint64_t addr = ring->fence_drv.gpu_addr;
2289
2290 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2291 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2292 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2293 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2294 amdgpu_ring_write(ring, addr & 0xfffffffc);
2295 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2296 amdgpu_ring_write(ring, seq);
2297 amdgpu_ring_write(ring, 0xffffffff);
2298 amdgpu_ring_write(ring, 4); /* poll interval */
2299
2300 if (usepfp) {
2301 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2302 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2303 amdgpu_ring_write(ring, 0);
2304 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2305 amdgpu_ring_write(ring, 0);
2306 }
2307}
2308
2309static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
c633c00b 2310 unsigned vmid, uint64_t pd_addr)
2cd46ad2 2311{
21cd942e 2312 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2cd46ad2 2313
c633c00b 2314 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2cd46ad2
KW		 2315
2316 /* wait for the invalidate to complete */
2317 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2318 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2319 WAIT_REG_MEM_ENGINE(0))); /* me */
25069e06 2320 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2cd46ad2
KW		 2321 amdgpu_ring_write(ring, 0);
2322 amdgpu_ring_write(ring, 0); /* ref */
2323 amdgpu_ring_write(ring, 0); /* mask */
2324 amdgpu_ring_write(ring, 0x20); /* poll interval */
2325
2326 if (usepfp) {
2327 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2328 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2329 amdgpu_ring_write(ring, 0x0);
2330
2331 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2332 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2333 amdgpu_ring_write(ring, 0);
2334 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2335 amdgpu_ring_write(ring, 0);
2336 }
2337}
2338
e18fb1fd
CK		 2339static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2340 uint32_t reg, uint32_t val)
2341{
2342 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2343
2344 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2345 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2346 WRITE_DATA_DST_SEL(0)));
2347 amdgpu_ring_write(ring, reg);
2348 amdgpu_ring_write(ring, 0);
2349 amdgpu_ring_write(ring, val);
2350}
2cd46ad2
KW		 2351
2352static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2353{
078af1a3
CK		 2354 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
2355 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
2356 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
2cd46ad2
KW		 2357}
2358
2359static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2360{
2361 const u32 *src_ptr;
2362 volatile u32 *dst_ptr;
2363 u32 dws, i;
2364 u64 reg_list_mc_addr;
2365 const struct cs_section_def *cs_data;
2366 int r;
2367
2368 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2369 adev->gfx.rlc.reg_list_size =
2370 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2371
2372 adev->gfx.rlc.cs_data = si_cs_data;
2373 src_ptr = adev->gfx.rlc.reg_list;
2374 dws = adev->gfx.rlc.reg_list_size;
2375 cs_data = adev->gfx.rlc.cs_data;
2376
2377 if (src_ptr) {
2378 /* save restore block */
a4a02777
CK		 2379 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2380 AMDGPU_GEM_DOMAIN_VRAM,
2381 &adev->gfx.rlc.save_restore_obj,
2382 &adev->gfx.rlc.save_restore_gpu_addr,
2383 (void **)&adev->gfx.rlc.sr_ptr);
2cd46ad2 2384 if (r) {
a4a02777
CK		 2385 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
2386 r);
2cd46ad2
KW		 2387 gfx_v6_0_rlc_fini(adev);
2388 return r;
2389 }
2390
2cd46ad2
KW		 2391 /* write the sr buffer */
2392 dst_ptr = adev->gfx.rlc.sr_ptr;
2393 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2394 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
a4a02777 2395
2cd46ad2
KW		 2396 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2397 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2398 }
2399
2400 if (cs_data) {
2401 /* clear state block */
2402 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2403 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2404
a4a02777
CK		 2405 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2406 AMDGPU_GEM_DOMAIN_VRAM,
2407 &adev->gfx.rlc.clear_state_obj,
2408 &adev->gfx.rlc.clear_state_gpu_addr,
2409 (void **)&adev->gfx.rlc.cs_ptr);
2cd46ad2 2410 if (r) {
a4a02777 2411 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2cd46ad2
KW		 2412 gfx_v6_0_rlc_fini(adev);
2413 return r;
2414 }
2415
2cd46ad2
KW		 2416 /* set up the cs buffer */
2417 dst_ptr = adev->gfx.rlc.cs_ptr;
2418 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2419 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2420 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2421 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2422 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2423 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2424 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2425 }
2426
2427 return 0;
2428}
2429
2430static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2431{
25069e06 2432 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2cd46ad2
KW		 2433
2434 if (!enable) {
2435 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
25069e06 2436 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2cd46ad2 2437 }
2cd46ad2
KW		 2438}
2439
2440static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2441{
2442 int i;
2443
2444 for (i = 0; i < adev->usec_timeout; i++) {
25069e06 2445 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2cd46ad2
KW		 2446 break;
2447 udelay(1);
2448 }
2449
2450 for (i = 0; i < adev->usec_timeout; i++) {
25069e06 2451 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2cd46ad2
KW		 2452 break;
2453 udelay(1);
2454 }
2455}
2456
2457static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2458{
2459 u32 tmp;
2460
25069e06 2461 tmp = RREG32(mmRLC_CNTL);
2cd46ad2 2462 if (tmp != rlc)
25069e06 2463 WREG32(mmRLC_CNTL, rlc);
2cd46ad2
KW		 2464}
2465
2466static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2467{
2468 u32 data, orig;
2469
25069e06 2470 orig = data = RREG32(mmRLC_CNTL);
2cd46ad2 2471
25069e06
TSD		 2472 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2473 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2474 WREG32(mmRLC_CNTL, data);
2cd46ad2
KW		 2475
2476 gfx_v6_0_wait_for_rlc_serdes(adev);
2477 }
2478
2479 return orig;
2480}
2481
2482static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2483{
25069e06 2484 WREG32(mmRLC_CNTL, 0);
2cd46ad2
KW		 2485
2486 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2cd46ad2
KW		 2487 gfx_v6_0_wait_for_rlc_serdes(adev);
2488}
2489
2490static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2491{
25069e06 2492 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2cd46ad2
KW		 2493
2494 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2495
2496 udelay(50);
2497}
2498
2499static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2500{
25069e06 2501 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2cd46ad2 2502 udelay(50);
25069e06 2503 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2cd46ad2
KW		 2504 udelay(50);
2505}
2506
2507static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2508{
2509 u32 tmp;
2510
2511 /* Enable LBPW only for DDR3 */
25069e06 2512 tmp = RREG32(mmMC_SEQ_MISC0);
2cd46ad2
KW		 2513 if ((tmp & 0xF0000000) == 0xB0000000)
2514 return true;
2515 return false;
2516}
25069e06 2517
2cd46ad2
KW		 2518static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2519{
2520}
2521
2522static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2523{
2524 u32 i;
2525 const struct rlc_firmware_header_v1_0 *hdr;
2526 const __le32 *fw_data;
2527 u32 fw_size;
2528
2529
2530 if (!adev->gfx.rlc_fw)
2531 return -EINVAL;
2532
2533 gfx_v6_0_rlc_stop(adev);
2cd46ad2 2534 gfx_v6_0_rlc_reset(adev);
2cd46ad2 2535 gfx_v6_0_init_pg(adev);
2cd46ad2
KW		 2536 gfx_v6_0_init_cg(adev);
2537
25069e06
TSD		 2538 WREG32(mmRLC_RL_BASE, 0);
2539 WREG32(mmRLC_RL_SIZE, 0);
2540 WREG32(mmRLC_LB_CNTL, 0);
2541 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2542 WREG32(mmRLC_LB_CNTR_INIT, 0);
2543 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2cd46ad2 2544
25069e06
TSD		 2545 WREG32(mmRLC_MC_CNTL, 0);
2546 WREG32(mmRLC_UCODE_CNTL, 0);
2cd46ad2
KW		 2547
2548 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2549 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2550 fw_data = (const __le32 *)
2551 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2552
2553 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2554
2555 for (i = 0; i < fw_size; i++) {
25069e06
TSD		 2556 WREG32(mmRLC_UCODE_ADDR, i);
2557 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2cd46ad2 2558 }
25069e06 2559 WREG32(mmRLC_UCODE_ADDR, 0);
2cd46ad2
KW		 2560
2561 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2cd46ad2
KW		 2562 gfx_v6_0_rlc_start(adev);
2563
2564 return 0;
2565}
2566
2567static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2568{
2569 u32 data, orig, tmp;
2570
25069e06 2571 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2cd46ad2
KW		 2572
2573 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2574 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2575
25069e06 2576 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2cd46ad2
KW		 2577
2578 tmp = gfx_v6_0_halt_rlc(adev);
2579
25069e06
TSD		 2580 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2581 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2582 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2cd46ad2
KW		 2583
2584 gfx_v6_0_wait_for_rlc_serdes(adev);
2cd46ad2
KW		 2585 gfx_v6_0_update_rlc(adev, tmp);
2586
25069e06 2587 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2cd46ad2 2588
25069e06 2589 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2cd46ad2
KW		 2590 } else {
2591 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2592
25069e06
TSD		 2593 RREG32(mmCB_CGTT_SCLK_CTRL);
2594 RREG32(mmCB_CGTT_SCLK_CTRL);
2595 RREG32(mmCB_CGTT_SCLK_CTRL);
2596 RREG32(mmCB_CGTT_SCLK_CTRL);
2cd46ad2 2597
25069e06 2598 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2cd46ad2
KW		 2599 }
2600
2601 if (orig != data)
25069e06 2602 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2cd46ad2
KW		 2603
2604}
2605
2606static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2607{
2608
2609 u32 data, orig, tmp = 0;
2610
2611 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
25069e06 2612 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2cd46ad2
KW		 2613 data = 0x96940200;
2614 if (orig != data)
25069e06 2615 WREG32(mmCGTS_SM_CTRL_REG, data);
2cd46ad2
KW		 2616
2617 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
25069e06
TSD		 2618 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2619 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2cd46ad2 2620 if (orig != data)
25069e06 2621 WREG32(mmCP_MEM_SLP_CNTL, data);
2cd46ad2
KW		 2622 }
2623
25069e06 2624 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2cd46ad2
KW		 2625 data &= 0xffffffc0;
2626 if (orig != data)
25069e06 2627 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2cd46ad2
KW		 2628
2629 tmp = gfx_v6_0_halt_rlc(adev);
2630
25069e06
TSD		 2631 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2632 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2633 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2cd46ad2
KW		 2634
2635 gfx_v6_0_update_rlc(adev, tmp);
2636 } else {
25069e06 2637 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2cd46ad2
KW		 2638 data |= 0x00000003;
2639 if (orig != data)
25069e06 2640 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2cd46ad2 2641
25069e06
TSD		 2642 data = RREG32(mmCP_MEM_SLP_CNTL);
2643 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2644 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2645 WREG32(mmCP_MEM_SLP_CNTL, data);
2cd46ad2 2646 }
25069e06
TSD		 2647 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2648 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2cd46ad2 2649 if (orig != data)
25069e06 2650 WREG32(mmCGTS_SM_CTRL_REG, data);
2cd46ad2
KW		 2651
2652 tmp = gfx_v6_0_halt_rlc(adev);
2653
25069e06
TSD		 2654 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2655 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2656 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2cd46ad2
KW		 2657
2658 gfx_v6_0_update_rlc(adev, tmp);
2659 }
2660}
2661/*
2662static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2663 bool enable)
2664{
2665 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2666 if (enable) {
2667 gfx_v6_0_enable_mgcg(adev, true);
2668 gfx_v6_0_enable_cgcg(adev, true);
2669 } else {
2670 gfx_v6_0_enable_cgcg(adev, false);
2671 gfx_v6_0_enable_mgcg(adev, false);
2672 }
2673 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2674}
2675*/
25069e06 2676
2cd46ad2
KW		 2677static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2678 bool enable)
2679{
2680}
2681
2682static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2683 bool enable)
2684{
2685}
2686
2687static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2688{
2689 u32 data, orig;
2690
25069e06 2691 orig = data = RREG32(mmRLC_PG_CNTL);
2cd46ad2
KW		 2692 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2693 data &= ~0x8000;
2694 else
2695 data |= 0x8000;
2696 if (orig != data)
25069e06 2697 WREG32(mmRLC_PG_CNTL, data);
2cd46ad2
KW		 2698}
2699
2700static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2701{
2702}
2703/*
2704static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2705{
2706 const __le32 *fw_data;
2707 volatile u32 *dst_ptr;
2708 int me, i, max_me = 4;
2709 u32 bo_offset = 0;
2710 u32 table_offset, table_size;
2711
2712 if (adev->asic_type == CHIP_KAVERI)
2713 max_me = 5;
2714
2715 if (adev->gfx.rlc.cp_table_ptr == NULL)
2716 return;
2717
2718 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2719 for (me = 0; me < max_me; me++) {
2720 if (me == 0) {
2721 const struct gfx_firmware_header_v1_0 *hdr =
2722 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2723 fw_data = (const __le32 *)
2724 (adev->gfx.ce_fw->data +
2725 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2726 table_offset = le32_to_cpu(hdr->jt_offset);
2727 table_size = le32_to_cpu(hdr->jt_size);
2728 } else if (me == 1) {
2729 const struct gfx_firmware_header_v1_0 *hdr =
2730 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2731 fw_data = (const __le32 *)
2732 (adev->gfx.pfp_fw->data +
2733 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2734 table_offset = le32_to_cpu(hdr->jt_offset);
2735 table_size = le32_to_cpu(hdr->jt_size);
2736 } else if (me == 2) {
2737 const struct gfx_firmware_header_v1_0 *hdr =
2738 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2739 fw_data = (const __le32 *)
2740 (adev->gfx.me_fw->data +
2741 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2742 table_offset = le32_to_cpu(hdr->jt_offset);
2743 table_size = le32_to_cpu(hdr->jt_size);
2744 } else if (me == 3) {
2745 const struct gfx_firmware_header_v1_0 *hdr =
2746 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2747 fw_data = (const __le32 *)
2748 (adev->gfx.mec_fw->data +
2749 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2750 table_offset = le32_to_cpu(hdr->jt_offset);
2751 table_size = le32_to_cpu(hdr->jt_size);
2752 } else {
2753 const struct gfx_firmware_header_v1_0 *hdr =
2754 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2755 fw_data = (const __le32 *)
2756 (adev->gfx.mec2_fw->data +
2757 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2758 table_offset = le32_to_cpu(hdr->jt_offset);
2759 table_size = le32_to_cpu(hdr->jt_size);
2760 }
2761
2762 for (i = 0; i < table_size; i ++) {
2763 dst_ptr[bo_offset + i] =
2764 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2765 }
2766
2767 bo_offset += table_size;
2768 }
2769}
2770*/
2771static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2772 bool enable)
2773{
2cd46ad2 2774 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
25069e06
TSD		 2775 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2776 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2777 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2cd46ad2 2778 } else {
25069e06
TSD		 2779 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2780 (void)RREG32(mmDB_RENDER_CONTROL);
2cd46ad2
KW		 2781 }
2782}
2783
2cd46ad2
KW		 2784static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2785{
375d6f70 2786 u32 tmp;
2cd46ad2 2787
375d6f70 2788 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2cd46ad2 2789
375d6f70
FC		 2790 tmp = RREG32(mmRLC_MAX_PG_CU);
2791 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2792 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2793 WREG32(mmRLC_MAX_PG_CU, tmp);
2cd46ad2
KW		 2794}
2795
2796static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2797 bool enable)
2798{
2799 u32 data, orig;
2800
25069e06 2801 orig = data = RREG32(mmRLC_PG_CNTL);
2cd46ad2 2802 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
25069e06 2803 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2cd46ad2 2804 else
25069e06 2805 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2cd46ad2 2806 if (orig != data)
25069e06 2807 WREG32(mmRLC_PG_CNTL, data);
2cd46ad2
KW		 2808}
2809
2810static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2811 bool enable)
2812{
2813 u32 data, orig;
2814
25069e06 2815 orig = data = RREG32(mmRLC_PG_CNTL);
2cd46ad2 2816 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
25069e06 2817 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2cd46ad2 2818 else
25069e06 2819 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2cd46ad2 2820 if (orig != data)
25069e06 2821 WREG32(mmRLC_PG_CNTL, data);
2cd46ad2
KW		 2822}
2823
2824static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2825{
2826 u32 tmp;
2827
25069e06
TSD		 2828 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2829 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2830 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2cd46ad2 2831
25069e06
TSD		 2832 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2833 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2834 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2835 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2836 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2cd46ad2
KW		 2837}
2838
2839static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2840{
2841 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2842 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2843 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2844}
2845
2846static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2847{
2848 u32 count = 0;
2849 const struct cs_section_def *sect = NULL;
2850 const struct cs_extent_def *ext = NULL;
2851
2852 if (adev->gfx.rlc.cs_data == NULL)
2853 return 0;
2854
2855 /* begin clear state */
2856 count += 2;
2857 /* context control state */
2858 count += 3;
2859
2860 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2861 for (ext = sect->section; ext->extent != NULL; ++ext) {
2862 if (sect->id == SECT_CONTEXT)
2863 count += 2 + ext->reg_count;
2864 else
2865 return 0;
2866 }
2867 }
2868 /* pa_sc_raster_config */
2869 count += 3;
2870 /* end clear state */
2871 count += 2;
2872 /* clear state */
2873 count += 2;
2874
2875 return count;
2876}
2877
2878static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2879 volatile u32 *buffer)
2880{
2881 u32 count = 0, i;
2882 const struct cs_section_def *sect = NULL;
2883 const struct cs_extent_def *ext = NULL;
2884
2885 if (adev->gfx.rlc.cs_data == NULL)
2886 return;
2887 if (buffer == NULL)
2888 return;
2889
2890 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2891 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2cd46ad2
KW		 2892 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2893 buffer[count++] = cpu_to_le32(0x80000000);
2894 buffer[count++] = cpu_to_le32(0x80000000);
2895
2896 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2897 for (ext = sect->section; ext->extent != NULL; ++ext) {
2898 if (sect->id == SECT_CONTEXT) {
2899 buffer[count++] =
2900 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2901 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2902 for (i = 0; i < ext->reg_count; i++)
2903 buffer[count++] = cpu_to_le32(ext->extent[i]);
2904 } else {
2905 return;
2906 }
2907 }
2908 }
2909
2910 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
25069e06 2911 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
56f3df44 2912 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2cd46ad2
KW		 2913
2914 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2915 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2916
2917 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2918 buffer[count++] = cpu_to_le32(0);
2919}
2920
2921static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2922{
2923 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2924 AMD_PG_SUPPORT_GFX_SMG |
2925 AMD_PG_SUPPORT_GFX_DMG |
2926 AMD_PG_SUPPORT_CP |
2927 AMD_PG_SUPPORT_GDS |
2928 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2929 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2930 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2931 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2932 gfx_v6_0_init_gfx_cgpg(adev);
2933 gfx_v6_0_enable_cp_pg(adev, true);
2934 gfx_v6_0_enable_gds_pg(adev, true);
2935 } else {
25069e06
TSD		 2936 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2937 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2cd46ad2
KW		 2938
2939 }
2940 gfx_v6_0_init_ao_cu_mask(adev);
2941 gfx_v6_0_update_gfx_pg(adev, true);
2942 } else {
2943
25069e06
TSD		 2944 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2945 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2cd46ad2
KW		 2946 }
2947}
2948
2949static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2950{
2951 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2952 AMD_PG_SUPPORT_GFX_SMG |
2953 AMD_PG_SUPPORT_GFX_DMG |
2954 AMD_PG_SUPPORT_CP |
2955 AMD_PG_SUPPORT_GDS |
2956 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2957 gfx_v6_0_update_gfx_pg(adev, false);
2958 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2959 gfx_v6_0_enable_cp_pg(adev, false);
2960 gfx_v6_0_enable_gds_pg(adev, false);
2961 }
2962 }
2963}
2964
2965static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2966{
2967 uint64_t clock;
2968
2969 mutex_lock(&adev->gfx.gpu_clock_mutex);
25069e06
TSD		 2970 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2971 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2972 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2cd46ad2
KW		 2973 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2974 return clock;
2975}
2976
0f444c24
AD		 2977static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2978{
45682886
ML		 2979 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2980 gfx_v6_0_ring_emit_vgt_flush(ring);
0f444c24
AD		 2981 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2982 amdgpu_ring_write(ring, 0x80000000);
2983 amdgpu_ring_write(ring, 0);
2984}
2985
3ee73ed8
TSD		 2986
2987static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2988{
2989 WREG32(mmSQ_IND_INDEX,
2990 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2991 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2992 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2993 (SQ_IND_INDEX__FORCE_READ_MASK));
2994 return RREG32(mmSQ_IND_DATA);
2995}
2996
34e646f4
TSD		 2997static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2998 uint32_t wave, uint32_t thread,
2999 uint32_t regno, uint32_t num, uint32_t *out)
3000{
3001 WREG32(mmSQ_IND_INDEX,
3002 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3003 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3004 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3005 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3006 (SQ_IND_INDEX__FORCE_READ_MASK) |
3007 (SQ_IND_INDEX__AUTO_INCR_MASK));
3008 while (num--)
3009 *(out++) = RREG32(mmSQ_IND_DATA);
3010}
3011
3ee73ed8
TSD		 3012static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3013{
3014 /* type 0 wave data */
3015 dst[(*no_fields)++] = 0;
3016 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3017 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3018 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3019 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3020 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3021 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3022 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3023 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3024 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3025 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3026 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3027 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3028 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3029 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3030 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3031 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3032 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3033 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3034}
3035
34e646f4
TSD		 3036static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3037 uint32_t wave, uint32_t start,
3038 uint32_t size, uint32_t *dst)
3039{
3040 wave_read_regs(
3041 adev, simd, wave, 0,
3042 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3043}
3044
f7a9ee81
AG		 3045static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3046 u32 me, u32 pipe, u32 q)
3047{
3048 DRM_INFO("Not implemented\n");
3049}
3050
2cd46ad2
KW		 3051static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3052 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3053 .select_se_sh = &gfx_v6_0_select_se_sh,
3ee73ed8 3054 .read_wave_data = &gfx_v6_0_read_wave_data,
34e646f4 3055 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
f7a9ee81 3056 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
2cd46ad2
KW		 3057};
3058
3059static int gfx_v6_0_early_init(void *handle)
3060{
3061 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3062
3063 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3064 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3065 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3066 gfx_v6_0_set_ring_funcs(adev);
3067 gfx_v6_0_set_irq_funcs(adev);
3068
3069 return 0;
3070}
3071
3072static int gfx_v6_0_sw_init(void *handle)
3073{
3074 struct amdgpu_ring *ring;
3075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3076 int i, r;
3077
1ffdeca6 3078 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
2cd46ad2
KW		 3079 if (r)
3080 return r;
3081
1ffdeca6 3082 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
2cd46ad2
KW		 3083 if (r)
3084 return r;
3085
1ffdeca6 3086 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
2cd46ad2
KW		 3087 if (r)
3088 return r;
3089
3090 gfx_v6_0_scratch_init(adev);
3091
3092 r = gfx_v6_0_init_microcode(adev);
3093 if (r) {
3094 DRM_ERROR("Failed to load gfx firmware!\n");
3095 return r;
3096 }
3097
3098 r = gfx_v6_0_rlc_init(adev);
3099 if (r) {
3100 DRM_ERROR("Failed to init rlc BOs!\n");
3101 return r;
3102 }
3103
3104 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3105 ring = &adev->gfx.gfx_ring[i];
3106 ring->ring_obj = NULL;
3107 sprintf(ring->name, "gfx");
3108 r = amdgpu_ring_init(adev, ring, 1024,
21cd942e 3109 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
2cd46ad2
KW		 3110 if (r)
3111 return r;
3112 }
3113
3114 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3115 unsigned irq_type;
3116
3117 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3118 DRM_ERROR("Too many (%d) compute rings!\n", i);
3119 break;
3120 }
3121 ring = &adev->gfx.compute_ring[i];
3122 ring->ring_obj = NULL;
3123 ring->use_doorbell = false;
3124 ring->doorbell_index = 0;
3125 ring->me = 1;
3126 ring->pipe = i;
3127 ring->queue = i;
15ff510b 3128 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
2cd46ad2 3129 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2255e8c1 3130 r = amdgpu_ring_init(adev, ring, 1024,
21cd942e 3131 &adev->gfx.eop_irq, irq_type);
2cd46ad2
KW		 3132 if (r)
3133 return r;
3134 }
3135
3136 return r;
3137}
3138
3139static int gfx_v6_0_sw_fini(void *handle)
3140{
3141 int i;
3142 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3143
2cd46ad2
KW		 3144 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3145 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3146 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3147 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3148
2cd46ad2
KW		 3149 gfx_v6_0_rlc_fini(adev);
3150
3151 return 0;
3152}
3153
3154static int gfx_v6_0_hw_init(void *handle)
3155{
3156 int r;
3157 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3158
434e6df2 3159 gfx_v6_0_constants_init(adev);
2cd46ad2
KW		 3160
3161 r = gfx_v6_0_rlc_resume(adev);
3162 if (r)
3163 return r;
3164
3165 r = gfx_v6_0_cp_resume(adev);
3166 if (r)
3167 return r;
3168
3169 adev->gfx.ce_ram_size = 0x8000;
3170
3171 return r;
3172}
3173
3174static int gfx_v6_0_hw_fini(void *handle)
3175{
3176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3177
3178 gfx_v6_0_cp_enable(adev, false);
3179 gfx_v6_0_rlc_stop(adev);
3180 gfx_v6_0_fini_pg(adev);
3181
3182 return 0;
3183}
3184
3185static int gfx_v6_0_suspend(void *handle)
3186{
3187 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3188
3189 return gfx_v6_0_hw_fini(adev);
3190}
3191
3192static int gfx_v6_0_resume(void *handle)
3193{
3194 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3195
3196 return gfx_v6_0_hw_init(adev);
3197}
3198
3199static bool gfx_v6_0_is_idle(void *handle)
3200{
3201 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3202
25069e06 3203 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
2cd46ad2
KW		 3204 return false;
3205 else
3206 return true;
3207}
3208
3209static int gfx_v6_0_wait_for_idle(void *handle)
3210{
3211 unsigned i;
2cd46ad2
KW		 3212 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3213
3214 for (i = 0; i < adev->usec_timeout; i++) {
4aeacf0f 3215 if (gfx_v6_0_is_idle(handle))
2cd46ad2
KW		 3216 return 0;
3217 udelay(1);
3218 }
3219 return -ETIMEDOUT;
3220}
3221
3222static int gfx_v6_0_soft_reset(void *handle)
3223{
3224 return 0;
3225}
3226
3227static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3228 enum amdgpu_interrupt_state state)
3229{
3230 u32 cp_int_cntl;
3231
3232 switch (state) {
3233 case AMDGPU_IRQ_STATE_DISABLE:
25069e06
TSD		 3234 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3235 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3236 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3237 break;
3238 case AMDGPU_IRQ_STATE_ENABLE:
25069e06
TSD		 3239 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3240 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3241 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3242 break;
3243 default:
3244 break;
3245 }
3246}
3247
3248static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3249 int ring,
3250 enum amdgpu_interrupt_state state)
3251{
3252 u32 cp_int_cntl;
3253 switch (state){
3254 case AMDGPU_IRQ_STATE_DISABLE:
3255 if (ring == 0) {
25069e06
TSD		 3256 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3257 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3258 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
2cd46ad2
KW		 3259 break;
3260 } else {
25069e06
TSD		 3261 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3262 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3263 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
2cd46ad2
KW		 3264 break;
3265
3266 }
3267 case AMDGPU_IRQ_STATE_ENABLE:
3268 if (ring == 0) {
25069e06
TSD		 3269 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3270 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3271 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
2cd46ad2
KW		 3272 break;
3273 } else {
25069e06
TSD		 3274 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3275 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3276 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
2cd46ad2
KW		 3277 break;
3278
3279 }
3280
3281 default:
3282 BUG();
3283 break;
3284
3285 }
3286}
3287
3288static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3289 struct amdgpu_irq_src *src,
3290 unsigned type,
3291 enum amdgpu_interrupt_state state)
3292{
3293 u32 cp_int_cntl;
3294
3295 switch (state) {
3296 case AMDGPU_IRQ_STATE_DISABLE:
25069e06 3297 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3298 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
25069e06 3299 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3300 break;
3301 case AMDGPU_IRQ_STATE_ENABLE:
25069e06 3302 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3303 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
25069e06 3304 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3305 break;
3306 default:
3307 break;
3308 }
3309
3310 return 0;
3311}
3312
3313static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3314 struct amdgpu_irq_src *src,
3315 unsigned type,
3316 enum amdgpu_interrupt_state state)
3317{
3318 u32 cp_int_cntl;
3319
3320 switch (state) {
3321 case AMDGPU_IRQ_STATE_DISABLE:
25069e06 3322 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3323 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
25069e06 3324 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3325 break;
3326 case AMDGPU_IRQ_STATE_ENABLE:
25069e06 3327 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3328 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
25069e06 3329 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3330 break;
3331 default:
3332 break;
3333 }
3334
3335 return 0;
3336}
3337
3338static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3339 struct amdgpu_irq_src *src,
3340 unsigned type,
3341 enum amdgpu_interrupt_state state)
3342{
3343 switch (type) {
3344 case AMDGPU_CP_IRQ_GFX_EOP:
3345 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3346 break;
3347 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3348 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3349 break;
3350 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3351 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3352 break;
3353 default:
3354 break;
3355 }
3356 return 0;
3357}
3358
3359static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3360 struct amdgpu_irq_src *source,
3361 struct amdgpu_iv_entry *entry)
3362{
3363 switch (entry->ring_id) {
3364 case 0:
3365 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3366 break;
3367 case 1:
3368 case 2:
25069e06 3369 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
2cd46ad2
KW		 3370 break;
3371 default:
3372 break;
3373 }
3374 return 0;
3375}
3376
898c2cb5
CK		 3377static void gfx_v6_0_fault(struct amdgpu_device *adev,
3378 struct amdgpu_iv_entry *entry)
3379{
3380 struct amdgpu_ring *ring;
3381
3382 switch (entry->ring_id) {
3383 case 0:
3384 ring = &adev->gfx.gfx_ring[0];
3385 break;
3386 case 1:
3387 case 2:
3388 ring = &adev->gfx.compute_ring[entry->ring_id - 1];
3389 break;
3390 default:
3391 return;
3392 }
3393 drm_sched_fault(&ring->sched);
3394}
3395
2cd46ad2
KW		 3396static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3397 struct amdgpu_irq_src *source,
3398 struct amdgpu_iv_entry *entry)
3399{
3400 DRM_ERROR("Illegal register access in command stream\n");
898c2cb5 3401 gfx_v6_0_fault(adev, entry);
2cd46ad2
KW		 3402 return 0;
3403}
3404
3405static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3406 struct amdgpu_irq_src *source,
3407 struct amdgpu_iv_entry *entry)
3408{
3409 DRM_ERROR("Illegal instruction in command stream\n");
898c2cb5 3410 gfx_v6_0_fault(adev, entry);
2cd46ad2
KW		 3411 return 0;
3412}
3413
3414static int gfx_v6_0_set_clockgating_state(void *handle,
3415 enum amd_clockgating_state state)
3416{
3417 bool gate = false;
3418 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3419
3420 if (state == AMD_CG_STATE_GATE)
3421 gate = true;
3422
3423 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3424 if (gate) {
3425 gfx_v6_0_enable_mgcg(adev, true);
3426 gfx_v6_0_enable_cgcg(adev, true);
3427 } else {
3428 gfx_v6_0_enable_cgcg(adev, false);
3429 gfx_v6_0_enable_mgcg(adev, false);
3430 }
3431 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3432
3433 return 0;
3434}
3435
3436static int gfx_v6_0_set_powergating_state(void *handle,
3437 enum amd_powergating_state state)
3438{
3439 bool gate = false;
3440 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3441
3442 if (state == AMD_PG_STATE_GATE)
3443 gate = true;
3444
3445 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3446 AMD_PG_SUPPORT_GFX_SMG |
3447 AMD_PG_SUPPORT_GFX_DMG |
3448 AMD_PG_SUPPORT_CP |
3449 AMD_PG_SUPPORT_GDS |
3450 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3451 gfx_v6_0_update_gfx_pg(adev, gate);
3452 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3453 gfx_v6_0_enable_cp_pg(adev, gate);
3454 gfx_v6_0_enable_gds_pg(adev, gate);
3455 }
3456 }
3457
3458 return 0;
3459}
3460
a1255107 3461static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
2cd46ad2
KW		 3462 .name = "gfx_v6_0",
3463 .early_init = gfx_v6_0_early_init,
3464 .late_init = NULL,
3465 .sw_init = gfx_v6_0_sw_init,
3466 .sw_fini = gfx_v6_0_sw_fini,
3467 .hw_init = gfx_v6_0_hw_init,
3468 .hw_fini = gfx_v6_0_hw_fini,
3469 .suspend = gfx_v6_0_suspend,
3470 .resume = gfx_v6_0_resume,
3471 .is_idle = gfx_v6_0_is_idle,
3472 .wait_for_idle = gfx_v6_0_wait_for_idle,
3473 .soft_reset = gfx_v6_0_soft_reset,
3474 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3475 .set_powergating_state = gfx_v6_0_set_powergating_state,
3476};
3477
3478static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
21cd942e 3479 .type = AMDGPU_RING_TYPE_GFX,
79887142
CK		 3480 .align_mask = 0xff,
3481 .nop = 0x80000000,
536fbf94 3482 .support_64bit_ptrs = false,
6f924e20 3483 .get_rptr = gfx_v6_0_ring_get_rptr,
832c6ef7 3484 .get_wptr = gfx_v6_0_ring_get_wptr,
2cd46ad2 3485 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
e12f3d7a 3486 .emit_frame_size =
2ee150cd 3487 5 + 5 + /* hdp flush / invalidate */
e12f3d7a
CK		 3488 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3489 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
4fef88bd 3490 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
45682886 3491 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
e12f3d7a 3492 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
668f52c3
AD		 3493 .emit_ib = gfx_v6_0_ring_emit_ib,
3494 .emit_fence = gfx_v6_0_ring_emit_fence,
2cd46ad2
KW		 3495 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3496 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
2cd46ad2
KW		 3497 .test_ring = gfx_v6_0_ring_test_ring,
3498 .test_ib = gfx_v6_0_ring_test_ib,
3499 .insert_nop = amdgpu_ring_insert_nop,
0f444c24 3500 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
e18fb1fd 3501 .emit_wreg = gfx_v6_0_ring_emit_wreg,
2cd46ad2
KW		 3502};
3503
3504static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
21cd942e 3505 .type = AMDGPU_RING_TYPE_COMPUTE,
79887142
CK		 3506 .align_mask = 0xff,
3507 .nop = 0x80000000,
6f924e20 3508 .get_rptr = gfx_v6_0_ring_get_rptr,
832c6ef7 3509 .get_wptr = gfx_v6_0_ring_get_wptr,
2cd46ad2 3510 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
e12f3d7a 3511 .emit_frame_size =
2ee150cd 3512 5 + 5 + /* hdp flush / invalidate */
e12f3d7a 3513 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
4fef88bd 3514 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
e12f3d7a
CK		 3515 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3516 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
668f52c3
AD		 3517 .emit_ib = gfx_v6_0_ring_emit_ib,
3518 .emit_fence = gfx_v6_0_ring_emit_fence,
2cd46ad2
KW		 3519 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3520 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
2cd46ad2
KW		 3521 .test_ring = gfx_v6_0_ring_test_ring,
3522 .test_ib = gfx_v6_0_ring_test_ib,
3523 .insert_nop = amdgpu_ring_insert_nop,
e18fb1fd 3524 .emit_wreg = gfx_v6_0_ring_emit_wreg,
2cd46ad2
KW		 3525};
3526
3527static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3528{
3529 int i;
3530
3531 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3532 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3533 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3534 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3535}
3536
3537static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3538 .set = gfx_v6_0_set_eop_interrupt_state,
3539 .process = gfx_v6_0_eop_irq,
3540};
3541
3542static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3543 .set = gfx_v6_0_set_priv_reg_fault_state,
3544 .process = gfx_v6_0_priv_reg_irq,
3545};
3546
3547static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3548 .set = gfx_v6_0_set_priv_inst_fault_state,
3549 .process = gfx_v6_0_priv_inst_irq,
3550};
3551
3552static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3553{
3554 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3555 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3556
3557 adev->gfx.priv_reg_irq.num_types = 1;
3558 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3559
3560 adev->gfx.priv_inst_irq.num_types = 1;
3561 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3562}
3563
3564static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3565{
3566 int i, j, k, counter, active_cu_number = 0;
3567 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3568 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
375d6f70 3569 unsigned disable_masks[4 * 2];
fe723cd3
RZ		 3570 u32 ao_cu_num;
3571
3572 if (adev->flags & AMD_IS_APU)
3573 ao_cu_num = 2;
3574 else
3575 ao_cu_num = adev->gfx.config.max_cu_per_sh;
2cd46ad2
KW		 3576
3577 memset(cu_info, 0, sizeof(*cu_info));
3578
375d6f70
FC		 3579 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3580
3581 mutex_lock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 3582 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3583 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3584 mask = 1;
3585 ao_bitmap = 0;
3586 counter = 0;
375d6f70
FC		 3587 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3588 if (i < 4 && j < 2)
3589 gfx_v6_0_set_user_cu_inactive_bitmap(
3590 adev, disable_masks[i * 2 + j]);
3591 bitmap = gfx_v6_0_get_cu_enabled(adev);
2cd46ad2
KW		 3592 cu_info->bitmap[i][j] = bitmap;
3593
fe723cd3 3594 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2cd46ad2 3595 if (bitmap & mask) {
fe723cd3 3596 if (counter < ao_cu_num)
2cd46ad2
KW		 3597 ao_bitmap |= mask;
3598 counter ++;
3599 }
3600 mask <<= 1;
3601 }
3602 active_cu_number += counter;
dbfe85ea
FC		 3603 if (i < 2 && j < 2)
3604 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3605 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
2cd46ad2
KW		 3606 }
3607 }
2cd46ad2 3608
375d6f70
FC		 3609 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3610 mutex_unlock(&adev->grbm_idx_mutex);
3611
2cd46ad2
KW		 3612 cu_info->number = active_cu_number;
3613 cu_info->ao_cu_mask = ao_cu_mask;
3614}
a1255107
AD		 3615
3616const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3617{
3618 .type = AMD_IP_BLOCK_TYPE_GFX,
3619 .major = 6,
3620 .minor = 0,
3621 .rev = 0,
3622 .funcs = &gfx_v6_0_ip_funcs,
3623};
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