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drm/amdgpu: move the context from the IBs into the job
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_ih.h"
27#include "amdgpu_gfx.h"
28#include "cikd.h"
29#include "cik.h"
30#include "atom.h"
31#include "amdgpu_ucode.h"
32#include "clearstate_ci.h"
33
a2e73f56
AD		 34#include "dce/dce_8_0_d.h"
35#include "dce/dce_8_0_sh_mask.h"
36
37#include "bif/bif_4_1_d.h"
38#include "bif/bif_4_1_sh_mask.h"
39
40#include "gca/gfx_7_0_d.h"
41#include "gca/gfx_7_2_enum.h"
42#include "gca/gfx_7_2_sh_mask.h"
43
44#include "gmc/gmc_7_0_d.h"
45#include "gmc/gmc_7_0_sh_mask.h"
46
47#include "oss/oss_2_0_d.h"
48#include "oss/oss_2_0_sh_mask.h"
49
50#define GFX7_NUM_GFX_RINGS 1
51#define GFX7_NUM_COMPUTE_RINGS 8
52
53static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
a2e73f56
AD		 56
57MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
58MODULE_FIRMWARE("radeon/bonaire_me.bin");
59MODULE_FIRMWARE("radeon/bonaire_ce.bin");
60MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
61MODULE_FIRMWARE("radeon/bonaire_mec.bin");
62
63MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
64MODULE_FIRMWARE("radeon/hawaii_me.bin");
65MODULE_FIRMWARE("radeon/hawaii_ce.bin");
66MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
67MODULE_FIRMWARE("radeon/hawaii_mec.bin");
68
69MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
70MODULE_FIRMWARE("radeon/kaveri_me.bin");
71MODULE_FIRMWARE("radeon/kaveri_ce.bin");
72MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
73MODULE_FIRMWARE("radeon/kaveri_mec.bin");
74MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
75
76MODULE_FIRMWARE("radeon/kabini_pfp.bin");
77MODULE_FIRMWARE("radeon/kabini_me.bin");
78MODULE_FIRMWARE("radeon/kabini_ce.bin");
79MODULE_FIRMWARE("radeon/kabini_rlc.bin");
80MODULE_FIRMWARE("radeon/kabini_mec.bin");
81
82MODULE_FIRMWARE("radeon/mullins_pfp.bin");
83MODULE_FIRMWARE("radeon/mullins_me.bin");
84MODULE_FIRMWARE("radeon/mullins_ce.bin");
85MODULE_FIRMWARE("radeon/mullins_rlc.bin");
86MODULE_FIRMWARE("radeon/mullins_mec.bin");
87
88static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
89{
90 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
91 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
92 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
93 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
94 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
95 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
96 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
97 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
98 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
99 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
100 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
101 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
102 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
103 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
104 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
105 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
106};
107
108static const u32 spectre_rlc_save_restore_register_list[] =
109{
110 (0x0e00 << 16) | (0xc12c >> 2),
111 0x00000000,
112 (0x0e00 << 16) | (0xc140 >> 2),
113 0x00000000,
114 (0x0e00 << 16) | (0xc150 >> 2),
115 0x00000000,
116 (0x0e00 << 16) | (0xc15c >> 2),
117 0x00000000,
118 (0x0e00 << 16) | (0xc168 >> 2),
119 0x00000000,
120 (0x0e00 << 16) | (0xc170 >> 2),
121 0x00000000,
122 (0x0e00 << 16) | (0xc178 >> 2),
123 0x00000000,
124 (0x0e00 << 16) | (0xc204 >> 2),
125 0x00000000,
126 (0x0e00 << 16) | (0xc2b4 >> 2),
127 0x00000000,
128 (0x0e00 << 16) | (0xc2b8 >> 2),
129 0x00000000,
130 (0x0e00 << 16) | (0xc2bc >> 2),
131 0x00000000,
132 (0x0e00 << 16) | (0xc2c0 >> 2),
133 0x00000000,
134 (0x0e00 << 16) | (0x8228 >> 2),
135 0x00000000,
136 (0x0e00 << 16) | (0x829c >> 2),
137 0x00000000,
138 (0x0e00 << 16) | (0x869c >> 2),
139 0x00000000,
140 (0x0600 << 16) | (0x98f4 >> 2),
141 0x00000000,
142 (0x0e00 << 16) | (0x98f8 >> 2),
143 0x00000000,
144 (0x0e00 << 16) | (0x9900 >> 2),
145 0x00000000,
146 (0x0e00 << 16) | (0xc260 >> 2),
147 0x00000000,
148 (0x0e00 << 16) | (0x90e8 >> 2),
149 0x00000000,
150 (0x0e00 << 16) | (0x3c000 >> 2),
151 0x00000000,
152 (0x0e00 << 16) | (0x3c00c >> 2),
153 0x00000000,
154 (0x0e00 << 16) | (0x8c1c >> 2),
155 0x00000000,
156 (0x0e00 << 16) | (0x9700 >> 2),
157 0x00000000,
158 (0x0e00 << 16) | (0xcd20 >> 2),
159 0x00000000,
160 (0x4e00 << 16) | (0xcd20 >> 2),
161 0x00000000,
162 (0x5e00 << 16) | (0xcd20 >> 2),
163 0x00000000,
164 (0x6e00 << 16) | (0xcd20 >> 2),
165 0x00000000,
166 (0x7e00 << 16) | (0xcd20 >> 2),
167 0x00000000,
168 (0x8e00 << 16) | (0xcd20 >> 2),
169 0x00000000,
170 (0x9e00 << 16) | (0xcd20 >> 2),
171 0x00000000,
172 (0xae00 << 16) | (0xcd20 >> 2),
173 0x00000000,
174 (0xbe00 << 16) | (0xcd20 >> 2),
175 0x00000000,
176 (0x0e00 << 16) | (0x89bc >> 2),
177 0x00000000,
178 (0x0e00 << 16) | (0x8900 >> 2),
179 0x00000000,
180 0x3,
181 (0x0e00 << 16) | (0xc130 >> 2),
182 0x00000000,
183 (0x0e00 << 16) | (0xc134 >> 2),
184 0x00000000,
185 (0x0e00 << 16) | (0xc1fc >> 2),
186 0x00000000,
187 (0x0e00 << 16) | (0xc208 >> 2),
188 0x00000000,
189 (0x0e00 << 16) | (0xc264 >> 2),
190 0x00000000,
191 (0x0e00 << 16) | (0xc268 >> 2),
192 0x00000000,
193 (0x0e00 << 16) | (0xc26c >> 2),
194 0x00000000,
195 (0x0e00 << 16) | (0xc270 >> 2),
196 0x00000000,
197 (0x0e00 << 16) | (0xc274 >> 2),
198 0x00000000,
199 (0x0e00 << 16) | (0xc278 >> 2),
200 0x00000000,
201 (0x0e00 << 16) | (0xc27c >> 2),
202 0x00000000,
203 (0x0e00 << 16) | (0xc280 >> 2),
204 0x00000000,
205 (0x0e00 << 16) | (0xc284 >> 2),
206 0x00000000,
207 (0x0e00 << 16) | (0xc288 >> 2),
208 0x00000000,
209 (0x0e00 << 16) | (0xc28c >> 2),
210 0x00000000,
211 (0x0e00 << 16) | (0xc290 >> 2),
212 0x00000000,
213 (0x0e00 << 16) | (0xc294 >> 2),
214 0x00000000,
215 (0x0e00 << 16) | (0xc298 >> 2),
216 0x00000000,
217 (0x0e00 << 16) | (0xc29c >> 2),
218 0x00000000,
219 (0x0e00 << 16) | (0xc2a0 >> 2),
220 0x00000000,
221 (0x0e00 << 16) | (0xc2a4 >> 2),
222 0x00000000,
223 (0x0e00 << 16) | (0xc2a8 >> 2),
224 0x00000000,
225 (0x0e00 << 16) | (0xc2ac >> 2),
226 0x00000000,
227 (0x0e00 << 16) | (0xc2b0 >> 2),
228 0x00000000,
229 (0x0e00 << 16) | (0x301d0 >> 2),
230 0x00000000,
231 (0x0e00 << 16) | (0x30238 >> 2),
232 0x00000000,
233 (0x0e00 << 16) | (0x30250 >> 2),
234 0x00000000,
235 (0x0e00 << 16) | (0x30254 >> 2),
236 0x00000000,
237 (0x0e00 << 16) | (0x30258 >> 2),
238 0x00000000,
239 (0x0e00 << 16) | (0x3025c >> 2),
240 0x00000000,
241 (0x4e00 << 16) | (0xc900 >> 2),
242 0x00000000,
243 (0x5e00 << 16) | (0xc900 >> 2),
244 0x00000000,
245 (0x6e00 << 16) | (0xc900 >> 2),
246 0x00000000,
247 (0x7e00 << 16) | (0xc900 >> 2),
248 0x00000000,
249 (0x8e00 << 16) | (0xc900 >> 2),
250 0x00000000,
251 (0x9e00 << 16) | (0xc900 >> 2),
252 0x00000000,
253 (0xae00 << 16) | (0xc900 >> 2),
254 0x00000000,
255 (0xbe00 << 16) | (0xc900 >> 2),
256 0x00000000,
257 (0x4e00 << 16) | (0xc904 >> 2),
258 0x00000000,
259 (0x5e00 << 16) | (0xc904 >> 2),
260 0x00000000,
261 (0x6e00 << 16) | (0xc904 >> 2),
262 0x00000000,
263 (0x7e00 << 16) | (0xc904 >> 2),
264 0x00000000,
265 (0x8e00 << 16) | (0xc904 >> 2),
266 0x00000000,
267 (0x9e00 << 16) | (0xc904 >> 2),
268 0x00000000,
269 (0xae00 << 16) | (0xc904 >> 2),
270 0x00000000,
271 (0xbe00 << 16) | (0xc904 >> 2),
272 0x00000000,
273 (0x4e00 << 16) | (0xc908 >> 2),
274 0x00000000,
275 (0x5e00 << 16) | (0xc908 >> 2),
276 0x00000000,
277 (0x6e00 << 16) | (0xc908 >> 2),
278 0x00000000,
279 (0x7e00 << 16) | (0xc908 >> 2),
280 0x00000000,
281 (0x8e00 << 16) | (0xc908 >> 2),
282 0x00000000,
283 (0x9e00 << 16) | (0xc908 >> 2),
284 0x00000000,
285 (0xae00 << 16) | (0xc908 >> 2),
286 0x00000000,
287 (0xbe00 << 16) | (0xc908 >> 2),
288 0x00000000,
289 (0x4e00 << 16) | (0xc90c >> 2),
290 0x00000000,
291 (0x5e00 << 16) | (0xc90c >> 2),
292 0x00000000,
293 (0x6e00 << 16) | (0xc90c >> 2),
294 0x00000000,
295 (0x7e00 << 16) | (0xc90c >> 2),
296 0x00000000,
297 (0x8e00 << 16) | (0xc90c >> 2),
298 0x00000000,
299 (0x9e00 << 16) | (0xc90c >> 2),
300 0x00000000,
301 (0xae00 << 16) | (0xc90c >> 2),
302 0x00000000,
303 (0xbe00 << 16) | (0xc90c >> 2),
304 0x00000000,
305 (0x4e00 << 16) | (0xc910 >> 2),
306 0x00000000,
307 (0x5e00 << 16) | (0xc910 >> 2),
308 0x00000000,
309 (0x6e00 << 16) | (0xc910 >> 2),
310 0x00000000,
311 (0x7e00 << 16) | (0xc910 >> 2),
312 0x00000000,
313 (0x8e00 << 16) | (0xc910 >> 2),
314 0x00000000,
315 (0x9e00 << 16) | (0xc910 >> 2),
316 0x00000000,
317 (0xae00 << 16) | (0xc910 >> 2),
318 0x00000000,
319 (0xbe00 << 16) | (0xc910 >> 2),
320 0x00000000,
321 (0x0e00 << 16) | (0xc99c >> 2),
322 0x00000000,
323 (0x0e00 << 16) | (0x9834 >> 2),
324 0x00000000,
325 (0x0000 << 16) | (0x30f00 >> 2),
326 0x00000000,
327 (0x0001 << 16) | (0x30f00 >> 2),
328 0x00000000,
329 (0x0000 << 16) | (0x30f04 >> 2),
330 0x00000000,
331 (0x0001 << 16) | (0x30f04 >> 2),
332 0x00000000,
333 (0x0000 << 16) | (0x30f08 >> 2),
334 0x00000000,
335 (0x0001 << 16) | (0x30f08 >> 2),
336 0x00000000,
337 (0x0000 << 16) | (0x30f0c >> 2),
338 0x00000000,
339 (0x0001 << 16) | (0x30f0c >> 2),
340 0x00000000,
341 (0x0600 << 16) | (0x9b7c >> 2),
342 0x00000000,
343 (0x0e00 << 16) | (0x8a14 >> 2),
344 0x00000000,
345 (0x0e00 << 16) | (0x8a18 >> 2),
346 0x00000000,
347 (0x0600 << 16) | (0x30a00 >> 2),
348 0x00000000,
349 (0x0e00 << 16) | (0x8bf0 >> 2),
350 0x00000000,
351 (0x0e00 << 16) | (0x8bcc >> 2),
352 0x00000000,
353 (0x0e00 << 16) | (0x8b24 >> 2),
354 0x00000000,
355 (0x0e00 << 16) | (0x30a04 >> 2),
356 0x00000000,
357 (0x0600 << 16) | (0x30a10 >> 2),
358 0x00000000,
359 (0x0600 << 16) | (0x30a14 >> 2),
360 0x00000000,
361 (0x0600 << 16) | (0x30a18 >> 2),
362 0x00000000,
363 (0x0600 << 16) | (0x30a2c >> 2),
364 0x00000000,
365 (0x0e00 << 16) | (0xc700 >> 2),
366 0x00000000,
367 (0x0e00 << 16) | (0xc704 >> 2),
368 0x00000000,
369 (0x0e00 << 16) | (0xc708 >> 2),
370 0x00000000,
371 (0x0e00 << 16) | (0xc768 >> 2),
372 0x00000000,
373 (0x0400 << 16) | (0xc770 >> 2),
374 0x00000000,
375 (0x0400 << 16) | (0xc774 >> 2),
376 0x00000000,
377 (0x0400 << 16) | (0xc778 >> 2),
378 0x00000000,
379 (0x0400 << 16) | (0xc77c >> 2),
380 0x00000000,
381 (0x0400 << 16) | (0xc780 >> 2),
382 0x00000000,
383 (0x0400 << 16) | (0xc784 >> 2),
384 0x00000000,
385 (0x0400 << 16) | (0xc788 >> 2),
386 0x00000000,
387 (0x0400 << 16) | (0xc78c >> 2),
388 0x00000000,
389 (0x0400 << 16) | (0xc798 >> 2),
390 0x00000000,
391 (0x0400 << 16) | (0xc79c >> 2),
392 0x00000000,
393 (0x0400 << 16) | (0xc7a0 >> 2),
394 0x00000000,
395 (0x0400 << 16) | (0xc7a4 >> 2),
396 0x00000000,
397 (0x0400 << 16) | (0xc7a8 >> 2),
398 0x00000000,
399 (0x0400 << 16) | (0xc7ac >> 2),
400 0x00000000,
401 (0x0400 << 16) | (0xc7b0 >> 2),
402 0x00000000,
403 (0x0400 << 16) | (0xc7b4 >> 2),
404 0x00000000,
405 (0x0e00 << 16) | (0x9100 >> 2),
406 0x00000000,
407 (0x0e00 << 16) | (0x3c010 >> 2),
408 0x00000000,
409 (0x0e00 << 16) | (0x92a8 >> 2),
410 0x00000000,
411 (0x0e00 << 16) | (0x92ac >> 2),
412 0x00000000,
413 (0x0e00 << 16) | (0x92b4 >> 2),
414 0x00000000,
415 (0x0e00 << 16) | (0x92b8 >> 2),
416 0x00000000,
417 (0x0e00 << 16) | (0x92bc >> 2),
418 0x00000000,
419 (0x0e00 << 16) | (0x92c0 >> 2),
420 0x00000000,
421 (0x0e00 << 16) | (0x92c4 >> 2),
422 0x00000000,
423 (0x0e00 << 16) | (0x92c8 >> 2),
424 0x00000000,
425 (0x0e00 << 16) | (0x92cc >> 2),
426 0x00000000,
427 (0x0e00 << 16) | (0x92d0 >> 2),
428 0x00000000,
429 (0x0e00 << 16) | (0x8c00 >> 2),
430 0x00000000,
431 (0x0e00 << 16) | (0x8c04 >> 2),
432 0x00000000,
433 (0x0e00 << 16) | (0x8c20 >> 2),
434 0x00000000,
435 (0x0e00 << 16) | (0x8c38 >> 2),
436 0x00000000,
437 (0x0e00 << 16) | (0x8c3c >> 2),
438 0x00000000,
439 (0x0e00 << 16) | (0xae00 >> 2),
440 0x00000000,
441 (0x0e00 << 16) | (0x9604 >> 2),
442 0x00000000,
443 (0x0e00 << 16) | (0xac08 >> 2),
444 0x00000000,
445 (0x0e00 << 16) | (0xac0c >> 2),
446 0x00000000,
447 (0x0e00 << 16) | (0xac10 >> 2),
448 0x00000000,
449 (0x0e00 << 16) | (0xac14 >> 2),
450 0x00000000,
451 (0x0e00 << 16) | (0xac58 >> 2),
452 0x00000000,
453 (0x0e00 << 16) | (0xac68 >> 2),
454 0x00000000,
455 (0x0e00 << 16) | (0xac6c >> 2),
456 0x00000000,
457 (0x0e00 << 16) | (0xac70 >> 2),
458 0x00000000,
459 (0x0e00 << 16) | (0xac74 >> 2),
460 0x00000000,
461 (0x0e00 << 16) | (0xac78 >> 2),
462 0x00000000,
463 (0x0e00 << 16) | (0xac7c >> 2),
464 0x00000000,
465 (0x0e00 << 16) | (0xac80 >> 2),
466 0x00000000,
467 (0x0e00 << 16) | (0xac84 >> 2),
468 0x00000000,
469 (0x0e00 << 16) | (0xac88 >> 2),
470 0x00000000,
471 (0x0e00 << 16) | (0xac8c >> 2),
472 0x00000000,
473 (0x0e00 << 16) | (0x970c >> 2),
474 0x00000000,
475 (0x0e00 << 16) | (0x9714 >> 2),
476 0x00000000,
477 (0x0e00 << 16) | (0x9718 >> 2),
478 0x00000000,
479 (0x0e00 << 16) | (0x971c >> 2),
480 0x00000000,
481 (0x0e00 << 16) | (0x31068 >> 2),
482 0x00000000,
483 (0x4e00 << 16) | (0x31068 >> 2),
484 0x00000000,
485 (0x5e00 << 16) | (0x31068 >> 2),
486 0x00000000,
487 (0x6e00 << 16) | (0x31068 >> 2),
488 0x00000000,
489 (0x7e00 << 16) | (0x31068 >> 2),
490 0x00000000,
491 (0x8e00 << 16) | (0x31068 >> 2),
492 0x00000000,
493 (0x9e00 << 16) | (0x31068 >> 2),
494 0x00000000,
495 (0xae00 << 16) | (0x31068 >> 2),
496 0x00000000,
497 (0xbe00 << 16) | (0x31068 >> 2),
498 0x00000000,
499 (0x0e00 << 16) | (0xcd10 >> 2),
500 0x00000000,
501 (0x0e00 << 16) | (0xcd14 >> 2),
502 0x00000000,
503 (0x0e00 << 16) | (0x88b0 >> 2),
504 0x00000000,
505 (0x0e00 << 16) | (0x88b4 >> 2),
506 0x00000000,
507 (0x0e00 << 16) | (0x88b8 >> 2),
508 0x00000000,
509 (0x0e00 << 16) | (0x88bc >> 2),
510 0x00000000,
511 (0x0400 << 16) | (0x89c0 >> 2),
512 0x00000000,
513 (0x0e00 << 16) | (0x88c4 >> 2),
514 0x00000000,
515 (0x0e00 << 16) | (0x88c8 >> 2),
516 0x00000000,
517 (0x0e00 << 16) | (0x88d0 >> 2),
518 0x00000000,
519 (0x0e00 << 16) | (0x88d4 >> 2),
520 0x00000000,
521 (0x0e00 << 16) | (0x88d8 >> 2),
522 0x00000000,
523 (0x0e00 << 16) | (0x8980 >> 2),
524 0x00000000,
525 (0x0e00 << 16) | (0x30938 >> 2),
526 0x00000000,
527 (0x0e00 << 16) | (0x3093c >> 2),
528 0x00000000,
529 (0x0e00 << 16) | (0x30940 >> 2),
530 0x00000000,
531 (0x0e00 << 16) | (0x89a0 >> 2),
532 0x00000000,
533 (0x0e00 << 16) | (0x30900 >> 2),
534 0x00000000,
535 (0x0e00 << 16) | (0x30904 >> 2),
536 0x00000000,
537 (0x0e00 << 16) | (0x89b4 >> 2),
538 0x00000000,
539 (0x0e00 << 16) | (0x3c210 >> 2),
540 0x00000000,
541 (0x0e00 << 16) | (0x3c214 >> 2),
542 0x00000000,
543 (0x0e00 << 16) | (0x3c218 >> 2),
544 0x00000000,
545 (0x0e00 << 16) | (0x8904 >> 2),
546 0x00000000,
547 0x5,
548 (0x0e00 << 16) | (0x8c28 >> 2),
549 (0x0e00 << 16) | (0x8c2c >> 2),
550 (0x0e00 << 16) | (0x8c30 >> 2),
551 (0x0e00 << 16) | (0x8c34 >> 2),
552 (0x0e00 << 16) | (0x9600 >> 2),
553};
554
555static const u32 kalindi_rlc_save_restore_register_list[] =
556{
557 (0x0e00 << 16) | (0xc12c >> 2),
558 0x00000000,
559 (0x0e00 << 16) | (0xc140 >> 2),
560 0x00000000,
561 (0x0e00 << 16) | (0xc150 >> 2),
562 0x00000000,
563 (0x0e00 << 16) | (0xc15c >> 2),
564 0x00000000,
565 (0x0e00 << 16) | (0xc168 >> 2),
566 0x00000000,
567 (0x0e00 << 16) | (0xc170 >> 2),
568 0x00000000,
569 (0x0e00 << 16) | (0xc204 >> 2),
570 0x00000000,
571 (0x0e00 << 16) | (0xc2b4 >> 2),
572 0x00000000,
573 (0x0e00 << 16) | (0xc2b8 >> 2),
574 0x00000000,
575 (0x0e00 << 16) | (0xc2bc >> 2),
576 0x00000000,
577 (0x0e00 << 16) | (0xc2c0 >> 2),
578 0x00000000,
579 (0x0e00 << 16) | (0x8228 >> 2),
580 0x00000000,
581 (0x0e00 << 16) | (0x829c >> 2),
582 0x00000000,
583 (0x0e00 << 16) | (0x869c >> 2),
584 0x00000000,
585 (0x0600 << 16) | (0x98f4 >> 2),
586 0x00000000,
587 (0x0e00 << 16) | (0x98f8 >> 2),
588 0x00000000,
589 (0x0e00 << 16) | (0x9900 >> 2),
590 0x00000000,
591 (0x0e00 << 16) | (0xc260 >> 2),
592 0x00000000,
593 (0x0e00 << 16) | (0x90e8 >> 2),
594 0x00000000,
595 (0x0e00 << 16) | (0x3c000 >> 2),
596 0x00000000,
597 (0x0e00 << 16) | (0x3c00c >> 2),
598 0x00000000,
599 (0x0e00 << 16) | (0x8c1c >> 2),
600 0x00000000,
601 (0x0e00 << 16) | (0x9700 >> 2),
602 0x00000000,
603 (0x0e00 << 16) | (0xcd20 >> 2),
604 0x00000000,
605 (0x4e00 << 16) | (0xcd20 >> 2),
606 0x00000000,
607 (0x5e00 << 16) | (0xcd20 >> 2),
608 0x00000000,
609 (0x6e00 << 16) | (0xcd20 >> 2),
610 0x00000000,
611 (0x7e00 << 16) | (0xcd20 >> 2),
612 0x00000000,
613 (0x0e00 << 16) | (0x89bc >> 2),
614 0x00000000,
615 (0x0e00 << 16) | (0x8900 >> 2),
616 0x00000000,
617 0x3,
618 (0x0e00 << 16) | (0xc130 >> 2),
619 0x00000000,
620 (0x0e00 << 16) | (0xc134 >> 2),
621 0x00000000,
622 (0x0e00 << 16) | (0xc1fc >> 2),
623 0x00000000,
624 (0x0e00 << 16) | (0xc208 >> 2),
625 0x00000000,
626 (0x0e00 << 16) | (0xc264 >> 2),
627 0x00000000,
628 (0x0e00 << 16) | (0xc268 >> 2),
629 0x00000000,
630 (0x0e00 << 16) | (0xc26c >> 2),
631 0x00000000,
632 (0x0e00 << 16) | (0xc270 >> 2),
633 0x00000000,
634 (0x0e00 << 16) | (0xc274 >> 2),
635 0x00000000,
636 (0x0e00 << 16) | (0xc28c >> 2),
637 0x00000000,
638 (0x0e00 << 16) | (0xc290 >> 2),
639 0x00000000,
640 (0x0e00 << 16) | (0xc294 >> 2),
641 0x00000000,
642 (0x0e00 << 16) | (0xc298 >> 2),
643 0x00000000,
644 (0x0e00 << 16) | (0xc2a0 >> 2),
645 0x00000000,
646 (0x0e00 << 16) | (0xc2a4 >> 2),
647 0x00000000,
648 (0x0e00 << 16) | (0xc2a8 >> 2),
649 0x00000000,
650 (0x0e00 << 16) | (0xc2ac >> 2),
651 0x00000000,
652 (0x0e00 << 16) | (0x301d0 >> 2),
653 0x00000000,
654 (0x0e00 << 16) | (0x30238 >> 2),
655 0x00000000,
656 (0x0e00 << 16) | (0x30250 >> 2),
657 0x00000000,
658 (0x0e00 << 16) | (0x30254 >> 2),
659 0x00000000,
660 (0x0e00 << 16) | (0x30258 >> 2),
661 0x00000000,
662 (0x0e00 << 16) | (0x3025c >> 2),
663 0x00000000,
664 (0x4e00 << 16) | (0xc900 >> 2),
665 0x00000000,
666 (0x5e00 << 16) | (0xc900 >> 2),
667 0x00000000,
668 (0x6e00 << 16) | (0xc900 >> 2),
669 0x00000000,
670 (0x7e00 << 16) | (0xc900 >> 2),
671 0x00000000,
672 (0x4e00 << 16) | (0xc904 >> 2),
673 0x00000000,
674 (0x5e00 << 16) | (0xc904 >> 2),
675 0x00000000,
676 (0x6e00 << 16) | (0xc904 >> 2),
677 0x00000000,
678 (0x7e00 << 16) | (0xc904 >> 2),
679 0x00000000,
680 (0x4e00 << 16) | (0xc908 >> 2),
681 0x00000000,
682 (0x5e00 << 16) | (0xc908 >> 2),
683 0x00000000,
684 (0x6e00 << 16) | (0xc908 >> 2),
685 0x00000000,
686 (0x7e00 << 16) | (0xc908 >> 2),
687 0x00000000,
688 (0x4e00 << 16) | (0xc90c >> 2),
689 0x00000000,
690 (0x5e00 << 16) | (0xc90c >> 2),
691 0x00000000,
692 (0x6e00 << 16) | (0xc90c >> 2),
693 0x00000000,
694 (0x7e00 << 16) | (0xc90c >> 2),
695 0x00000000,
696 (0x4e00 << 16) | (0xc910 >> 2),
697 0x00000000,
698 (0x5e00 << 16) | (0xc910 >> 2),
699 0x00000000,
700 (0x6e00 << 16) | (0xc910 >> 2),
701 0x00000000,
702 (0x7e00 << 16) | (0xc910 >> 2),
703 0x00000000,
704 (0x0e00 << 16) | (0xc99c >> 2),
705 0x00000000,
706 (0x0e00 << 16) | (0x9834 >> 2),
707 0x00000000,
708 (0x0000 << 16) | (0x30f00 >> 2),
709 0x00000000,
710 (0x0000 << 16) | (0x30f04 >> 2),
711 0x00000000,
712 (0x0000 << 16) | (0x30f08 >> 2),
713 0x00000000,
714 (0x0000 << 16) | (0x30f0c >> 2),
715 0x00000000,
716 (0x0600 << 16) | (0x9b7c >> 2),
717 0x00000000,
718 (0x0e00 << 16) | (0x8a14 >> 2),
719 0x00000000,
720 (0x0e00 << 16) | (0x8a18 >> 2),
721 0x00000000,
722 (0x0600 << 16) | (0x30a00 >> 2),
723 0x00000000,
724 (0x0e00 << 16) | (0x8bf0 >> 2),
725 0x00000000,
726 (0x0e00 << 16) | (0x8bcc >> 2),
727 0x00000000,
728 (0x0e00 << 16) | (0x8b24 >> 2),
729 0x00000000,
730 (0x0e00 << 16) | (0x30a04 >> 2),
731 0x00000000,
732 (0x0600 << 16) | (0x30a10 >> 2),
733 0x00000000,
734 (0x0600 << 16) | (0x30a14 >> 2),
735 0x00000000,
736 (0x0600 << 16) | (0x30a18 >> 2),
737 0x00000000,
738 (0x0600 << 16) | (0x30a2c >> 2),
739 0x00000000,
740 (0x0e00 << 16) | (0xc700 >> 2),
741 0x00000000,
742 (0x0e00 << 16) | (0xc704 >> 2),
743 0x00000000,
744 (0x0e00 << 16) | (0xc708 >> 2),
745 0x00000000,
746 (0x0e00 << 16) | (0xc768 >> 2),
747 0x00000000,
748 (0x0400 << 16) | (0xc770 >> 2),
749 0x00000000,
750 (0x0400 << 16) | (0xc774 >> 2),
751 0x00000000,
752 (0x0400 << 16) | (0xc798 >> 2),
753 0x00000000,
754 (0x0400 << 16) | (0xc79c >> 2),
755 0x00000000,
756 (0x0e00 << 16) | (0x9100 >> 2),
757 0x00000000,
758 (0x0e00 << 16) | (0x3c010 >> 2),
759 0x00000000,
760 (0x0e00 << 16) | (0x8c00 >> 2),
761 0x00000000,
762 (0x0e00 << 16) | (0x8c04 >> 2),
763 0x00000000,
764 (0x0e00 << 16) | (0x8c20 >> 2),
765 0x00000000,
766 (0x0e00 << 16) | (0x8c38 >> 2),
767 0x00000000,
768 (0x0e00 << 16) | (0x8c3c >> 2),
769 0x00000000,
770 (0x0e00 << 16) | (0xae00 >> 2),
771 0x00000000,
772 (0x0e00 << 16) | (0x9604 >> 2),
773 0x00000000,
774 (0x0e00 << 16) | (0xac08 >> 2),
775 0x00000000,
776 (0x0e00 << 16) | (0xac0c >> 2),
777 0x00000000,
778 (0x0e00 << 16) | (0xac10 >> 2),
779 0x00000000,
780 (0x0e00 << 16) | (0xac14 >> 2),
781 0x00000000,
782 (0x0e00 << 16) | (0xac58 >> 2),
783 0x00000000,
784 (0x0e00 << 16) | (0xac68 >> 2),
785 0x00000000,
786 (0x0e00 << 16) | (0xac6c >> 2),
787 0x00000000,
788 (0x0e00 << 16) | (0xac70 >> 2),
789 0x00000000,
790 (0x0e00 << 16) | (0xac74 >> 2),
791 0x00000000,
792 (0x0e00 << 16) | (0xac78 >> 2),
793 0x00000000,
794 (0x0e00 << 16) | (0xac7c >> 2),
795 0x00000000,
796 (0x0e00 << 16) | (0xac80 >> 2),
797 0x00000000,
798 (0x0e00 << 16) | (0xac84 >> 2),
799 0x00000000,
800 (0x0e00 << 16) | (0xac88 >> 2),
801 0x00000000,
802 (0x0e00 << 16) | (0xac8c >> 2),
803 0x00000000,
804 (0x0e00 << 16) | (0x970c >> 2),
805 0x00000000,
806 (0x0e00 << 16) | (0x9714 >> 2),
807 0x00000000,
808 (0x0e00 << 16) | (0x9718 >> 2),
809 0x00000000,
810 (0x0e00 << 16) | (0x971c >> 2),
811 0x00000000,
812 (0x0e00 << 16) | (0x31068 >> 2),
813 0x00000000,
814 (0x4e00 << 16) | (0x31068 >> 2),
815 0x00000000,
816 (0x5e00 << 16) | (0x31068 >> 2),
817 0x00000000,
818 (0x6e00 << 16) | (0x31068 >> 2),
819 0x00000000,
820 (0x7e00 << 16) | (0x31068 >> 2),
821 0x00000000,
822 (0x0e00 << 16) | (0xcd10 >> 2),
823 0x00000000,
824 (0x0e00 << 16) | (0xcd14 >> 2),
825 0x00000000,
826 (0x0e00 << 16) | (0x88b0 >> 2),
827 0x00000000,
828 (0x0e00 << 16) | (0x88b4 >> 2),
829 0x00000000,
830 (0x0e00 << 16) | (0x88b8 >> 2),
831 0x00000000,
832 (0x0e00 << 16) | (0x88bc >> 2),
833 0x00000000,
834 (0x0400 << 16) | (0x89c0 >> 2),
835 0x00000000,
836 (0x0e00 << 16) | (0x88c4 >> 2),
837 0x00000000,
838 (0x0e00 << 16) | (0x88c8 >> 2),
839 0x00000000,
840 (0x0e00 << 16) | (0x88d0 >> 2),
841 0x00000000,
842 (0x0e00 << 16) | (0x88d4 >> 2),
843 0x00000000,
844 (0x0e00 << 16) | (0x88d8 >> 2),
845 0x00000000,
846 (0x0e00 << 16) | (0x8980 >> 2),
847 0x00000000,
848 (0x0e00 << 16) | (0x30938 >> 2),
849 0x00000000,
850 (0x0e00 << 16) | (0x3093c >> 2),
851 0x00000000,
852 (0x0e00 << 16) | (0x30940 >> 2),
853 0x00000000,
854 (0x0e00 << 16) | (0x89a0 >> 2),
855 0x00000000,
856 (0x0e00 << 16) | (0x30900 >> 2),
857 0x00000000,
858 (0x0e00 << 16) | (0x30904 >> 2),
859 0x00000000,
860 (0x0e00 << 16) | (0x89b4 >> 2),
861 0x00000000,
862 (0x0e00 << 16) | (0x3e1fc >> 2),
863 0x00000000,
864 (0x0e00 << 16) | (0x3c210 >> 2),
865 0x00000000,
866 (0x0e00 << 16) | (0x3c214 >> 2),
867 0x00000000,
868 (0x0e00 << 16) | (0x3c218 >> 2),
869 0x00000000,
870 (0x0e00 << 16) | (0x8904 >> 2),
871 0x00000000,
872 0x5,
873 (0x0e00 << 16) | (0x8c28 >> 2),
874 (0x0e00 << 16) | (0x8c2c >> 2),
875 (0x0e00 << 16) | (0x8c30 >> 2),
876 (0x0e00 << 16) | (0x8c34 >> 2),
877 (0x0e00 << 16) | (0x9600 >> 2),
878};
879
880static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
881static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
882static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
883static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
7dae69a2 884static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
a2e73f56
AD		 885
886/*
887 * Core functions
888 */
889/**
890 * gfx_v7_0_init_microcode - load ucode images from disk
891 *
892 * @adev: amdgpu_device pointer
893 *
894 * Use the firmware interface to load the ucode images into
895 * the driver (not loaded into hw).
896 * Returns 0 on success, error on failure.
897 */
898static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
899{
900 const char *chip_name;
901 char fw_name[30];
902 int err;
903
904 DRM_DEBUG("\n");
905
906 switch (adev->asic_type) {
907 case CHIP_BONAIRE:
908 chip_name = "bonaire";
909 break;
910 case CHIP_HAWAII:
911 chip_name = "hawaii";
912 break;
913 case CHIP_KAVERI:
914 chip_name = "kaveri";
915 break;
916 case CHIP_KABINI:
917 chip_name = "kabini";
918 break;
919 case CHIP_MULLINS:
920 chip_name = "mullins";
921 break;
922 default: BUG();
923 }
924
925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
927 if (err)
928 goto out;
929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
930 if (err)
931 goto out;
932
933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
935 if (err)
936 goto out;
937 err = amdgpu_ucode_validate(adev->gfx.me_fw);
938 if (err)
939 goto out;
940
941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
943 if (err)
944 goto out;
945 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
946 if (err)
947 goto out;
948
949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
951 if (err)
952 goto out;
953 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
954 if (err)
955 goto out;
956
957 if (adev->asic_type == CHIP_KAVERI) {
958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
960 if (err)
961 goto out;
962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
963 if (err)
964 goto out;
965 }
966
967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
969 if (err)
970 goto out;
971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
972
973out:
974 if (err) {
975 printk(KERN_ERR
976 "gfx7: Failed to load firmware \"%s\"\n",
977 fw_name);
978 release_firmware(adev->gfx.pfp_fw);
979 adev->gfx.pfp_fw = NULL;
980 release_firmware(adev->gfx.me_fw);
981 adev->gfx.me_fw = NULL;
982 release_firmware(adev->gfx.ce_fw);
983 adev->gfx.ce_fw = NULL;
984 release_firmware(adev->gfx.mec_fw);
985 adev->gfx.mec_fw = NULL;
986 release_firmware(adev->gfx.mec2_fw);
987 adev->gfx.mec2_fw = NULL;
988 release_firmware(adev->gfx.rlc_fw);
989 adev->gfx.rlc_fw = NULL;
990 }
991 return err;
992}
993
994/**
995 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
996 *
997 * @adev: amdgpu_device pointer
998 *
999 * Starting with SI, the tiling setup is done globally in a
1000 * set of 32 tiling modes. Rather than selecting each set of
1001 * parameters per surface as on older asics, we just select
1002 * which index in the tiling table we want to use, and the
1003 * surface uses those parameters (CIK).
1004 */
1005static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1006{
840a20d3
TSD		 1007 const u32 num_tile_mode_states =
1008 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1009 const u32 num_secondary_tile_mode_states =
1010 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1011 u32 reg_offset, split_equal_to_row_size;
1012 uint32_t *tile, *macrotile;
1013
1014 tile = adev->gfx.config.tile_mode_array;
1015 macrotile = adev->gfx.config.macrotile_mode_array;
a2e73f56
AD		 1016
1017 switch (adev->gfx.config.mem_row_size_in_kb) {
1018 case 1:
1019 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1020 break;
1021 case 2:
1022 default:
1023 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1024 break;
1025 case 4:
1026 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1027 break;
1028 }
1029
840a20d3
TSD		 1030 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1031 tile[reg_offset] = 0;
1032 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1033 macrotile[reg_offset] = 0;
1034
a2e73f56
AD		 1035 switch (adev->asic_type) {
1036 case CHIP_BONAIRE:
840a20d3
TSD		 1037 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1039 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1040 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1041 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1043 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1044 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1045 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1047 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1048 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1049 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1050 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1052 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1053 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1056 TILE_SPLIT(split_equal_to_row_size));
1057 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1060 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1061 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1062 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1063 TILE_SPLIT(split_equal_to_row_size));
1064 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1065 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1066 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1067 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1068 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1069 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1070 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1072 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1073 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1074 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1075 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1076 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1077 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1078 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1079 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1080 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1082 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1083 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1084 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1085 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1086 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1095 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1098 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1099 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1100 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1101 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1102 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1106 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1110 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1111 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1112 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1114 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1115 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1118 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1119 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1120 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1121 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1123 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1124 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1125 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1126 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1127 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1128 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1129 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1130 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1131 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1132 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1134 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1135 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1136 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1138 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1139
1140 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1143 NUM_BANKS(ADDR_SURF_16_BANK));
1144 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1147 NUM_BANKS(ADDR_SURF_16_BANK));
1148 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151 NUM_BANKS(ADDR_SURF_16_BANK));
1152 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1155 NUM_BANKS(ADDR_SURF_16_BANK));
1156 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1159 NUM_BANKS(ADDR_SURF_16_BANK));
1160 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1163 NUM_BANKS(ADDR_SURF_8_BANK));
1164 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1167 NUM_BANKS(ADDR_SURF_4_BANK));
1168 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1171 NUM_BANKS(ADDR_SURF_16_BANK));
1172 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1179 NUM_BANKS(ADDR_SURF_16_BANK));
1180 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1183 NUM_BANKS(ADDR_SURF_16_BANK));
1184 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1191 NUM_BANKS(ADDR_SURF_8_BANK));
1192 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1195 NUM_BANKS(ADDR_SURF_4_BANK));
a2e73f56 1196
840a20d3
TSD		 1197 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1198 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1199 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1200 if (reg_offset != 7)
1201 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1202 break;
1203 case CHIP_HAWAII:
840a20d3
TSD		 1204 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1206 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1207 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1208 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1209 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1210 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1211 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1212 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1213 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1214 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1215 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1216 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1217 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1218 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1219 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1220 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1223 TILE_SPLIT(split_equal_to_row_size));
1224 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1227 TILE_SPLIT(split_equal_to_row_size));
1228 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1231 TILE_SPLIT(split_equal_to_row_size));
1232 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1234 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1235 TILE_SPLIT(split_equal_to_row_size));
1236 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1238 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1239 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1240 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1241 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1243 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1244 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1245 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1246 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1247 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1248 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1249 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1250 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1251 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1252 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1253 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1254 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1255 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1256 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1258 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1260 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1262 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1264 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1265 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1266 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1267 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1268 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1269 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1270 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1271 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1272 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1276 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1279 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1283 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1284 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1287 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1291 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1292 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1293 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1294 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1295 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1308 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1310 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1312 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1314 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1316 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1318 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1319 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1320 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
a2e73f56 1322
840a20d3
TSD		 1323 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1324 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1325 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1326 NUM_BANKS(ADDR_SURF_16_BANK));
1327 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1330 NUM_BANKS(ADDR_SURF_16_BANK));
1331 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1334 NUM_BANKS(ADDR_SURF_16_BANK));
1335 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1336 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1337 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1338 NUM_BANKS(ADDR_SURF_16_BANK));
1339 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1342 NUM_BANKS(ADDR_SURF_8_BANK));
1343 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1346 NUM_BANKS(ADDR_SURF_4_BANK));
1347 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350 NUM_BANKS(ADDR_SURF_4_BANK));
1351 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1354 NUM_BANKS(ADDR_SURF_16_BANK));
1355 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1358 NUM_BANKS(ADDR_SURF_16_BANK));
1359 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362 NUM_BANKS(ADDR_SURF_16_BANK));
1363 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366 NUM_BANKS(ADDR_SURF_8_BANK));
1367 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370 NUM_BANKS(ADDR_SURF_16_BANK));
1371 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374 NUM_BANKS(ADDR_SURF_8_BANK));
1375 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378 NUM_BANKS(ADDR_SURF_4_BANK));
1379
1380 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1381 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1382 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1383 if (reg_offset != 7)
1384 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1385 break;
1386 case CHIP_KABINI:
1387 case CHIP_KAVERI:
1388 case CHIP_MULLINS:
1389 default:
840a20d3
TSD		 1390 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1391 PIPE_CONFIG(ADDR_SURF_P2) |
1392 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1393 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1394 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1395 PIPE_CONFIG(ADDR_SURF_P2) |
1396 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1397 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1398 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1399 PIPE_CONFIG(ADDR_SURF_P2) |
1400 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1401 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1402 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1403 PIPE_CONFIG(ADDR_SURF_P2) |
1404 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1405 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1406 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P2) |
1408 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1409 TILE_SPLIT(split_equal_to_row_size));
1410 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1411 PIPE_CONFIG(ADDR_SURF_P2) |
1412 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1413 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1414 PIPE_CONFIG(ADDR_SURF_P2) |
1415 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1416 TILE_SPLIT(split_equal_to_row_size));
1417 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1418 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1419 PIPE_CONFIG(ADDR_SURF_P2));
1420 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1421 PIPE_CONFIG(ADDR_SURF_P2) |
1422 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1423 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1424 PIPE_CONFIG(ADDR_SURF_P2) |
1425 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1426 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1427 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1428 PIPE_CONFIG(ADDR_SURF_P2) |
1429 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1430 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1431 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1432 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1433 PIPE_CONFIG(ADDR_SURF_P2) |
1434 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1435 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1436 PIPE_CONFIG(ADDR_SURF_P2) |
1437 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1438 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1439 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1440 PIPE_CONFIG(ADDR_SURF_P2) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444 PIPE_CONFIG(ADDR_SURF_P2) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1448 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1449 PIPE_CONFIG(ADDR_SURF_P2) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1451 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1452 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1453 PIPE_CONFIG(ADDR_SURF_P2) |
1454 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1455 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1456 PIPE_CONFIG(ADDR_SURF_P2) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1459 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1460 PIPE_CONFIG(ADDR_SURF_P2) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1463 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1464 PIPE_CONFIG(ADDR_SURF_P2) |
1465 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1467 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1468 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1469 PIPE_CONFIG(ADDR_SURF_P2) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1471 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1472 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1473 PIPE_CONFIG(ADDR_SURF_P2) |
1474 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1476 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1477 PIPE_CONFIG(ADDR_SURF_P2) |
1478 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1479 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1480 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1481 PIPE_CONFIG(ADDR_SURF_P2) |
1482 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1483 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1484 PIPE_CONFIG(ADDR_SURF_P2) |
1485 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1486 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1487 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1488 PIPE_CONFIG(ADDR_SURF_P2) |
1489 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1491 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1492
1493 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1496 NUM_BANKS(ADDR_SURF_8_BANK));
1497 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1500 NUM_BANKS(ADDR_SURF_8_BANK));
1501 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1504 NUM_BANKS(ADDR_SURF_8_BANK));
1505 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1508 NUM_BANKS(ADDR_SURF_8_BANK));
1509 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1512 NUM_BANKS(ADDR_SURF_8_BANK));
1513 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1516 NUM_BANKS(ADDR_SURF_8_BANK));
1517 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520 NUM_BANKS(ADDR_SURF_8_BANK));
1521 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1524 NUM_BANKS(ADDR_SURF_16_BANK));
1525 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1528 NUM_BANKS(ADDR_SURF_16_BANK));
1529 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1532 NUM_BANKS(ADDR_SURF_16_BANK));
1533 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1536 NUM_BANKS(ADDR_SURF_16_BANK));
1537 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540 NUM_BANKS(ADDR_SURF_16_BANK));
1541 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544 NUM_BANKS(ADDR_SURF_16_BANK));
1545 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1548 NUM_BANKS(ADDR_SURF_8_BANK));
a2e73f56 1549
840a20d3
TSD		 1550 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1551 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1552 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1553 if (reg_offset != 7)
1554 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1555 break;
1556 }
1557}
1558
1559/**
1560 * gfx_v7_0_select_se_sh - select which SE, SH to address
1561 *
1562 * @adev: amdgpu_device pointer
1563 * @se_num: shader engine to address
1564 * @sh_num: sh block to address
1565 *
1566 * Select which SE, SH combinations to address. Certain
1567 * registers are instanced per SE or SH. 0xffffffff means
1568 * broadcast to all SEs or SHs (CIK).
1569 */
1570void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1571{
1572 u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
1573
1574 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1575 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1576 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1577 else if (se_num == 0xffffffff)
1578 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1579 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1580 else if (sh_num == 0xffffffff)
1581 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1582 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1583 else
1584 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1585 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1586 WREG32(mmGRBM_GFX_INDEX, data);
1587}
1588
1589/**
1590 * gfx_v7_0_create_bitmask - create a bitmask
1591 *
1592 * @bit_width: length of the mask
1593 *
1594 * create a variable length bit mask (CIK).
1595 * Returns the bitmask.
1596 */
1597static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1598{
8f8e00c1 1599 return (u32)((1ULL << bit_width) - 1);
a2e73f56
AD		 1600}
1601
1602/**
8f8e00c1 1603 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
a2e73f56
AD		 1604 *
1605 * @adev: amdgpu_device pointer
a2e73f56 1606 *
8f8e00c1
AD		 1607 * Calculates the bitmask of enabled RBs (CIK).
1608 * Returns the enabled RB bitmask.
a2e73f56 1609 */
8f8e00c1 1610static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
a2e73f56
AD		 1611{
1612 u32 data, mask;
1613
1614 data = RREG32(mmCC_RB_BACKEND_DISABLE);
a2e73f56
AD		 1615 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1616
8f8e00c1 1617 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
a2e73f56
AD		 1618 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1619
8f8e00c1
AD		 1620 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1621 adev->gfx.config.max_sh_per_se);
a2e73f56 1622
8f8e00c1 1623 return (~data) & mask;
a2e73f56
AD		 1624}
1625
1626/**
1627 * gfx_v7_0_setup_rb - setup the RBs on the asic
1628 *
1629 * @adev: amdgpu_device pointer
1630 * @se_num: number of SEs (shader engines) for the asic
1631 * @sh_per_se: number of SH blocks per SE for the asic
a2e73f56
AD		 1632 *
1633 * Configures per-SE/SH RB registers (CIK).
1634 */
8f8e00c1 1635static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
a2e73f56
AD		 1636{
1637 int i, j;
aac1e3ca 1638 u32 data;
8f8e00c1 1639 u32 active_rbs = 0;
6157bd7a
FC		 1640 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1641 adev->gfx.config.max_sh_per_se;
a2e73f56
AD		 1642
1643 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 1644 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1645 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
a2e73f56 1646 gfx_v7_0_select_se_sh(adev, i, j);
8f8e00c1 1647 data = gfx_v7_0_get_rb_active_bitmap(adev);
6157bd7a
FC		 1648 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1649 rb_bitmap_width_per_sh);
a2e73f56
AD		 1650 }
1651 }
1652 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1653 mutex_unlock(&adev->grbm_idx_mutex);
1654
8f8e00c1 1655 adev->gfx.config.backend_enable_mask = active_rbs;
aac1e3ca 1656 adev->gfx.config.num_rbs = hweight32(active_rbs);
a2e73f56
AD		 1657}
1658
cd06bf68
BG		 1659/**
1660 * gmc_v7_0_init_compute_vmid - gart enable
1661 *
1662 * @rdev: amdgpu_device pointer
1663 *
1664 * Initialize compute vmid sh_mem registers
1665 *
1666 */
1667#define DEFAULT_SH_MEM_BASES (0x6000)
1668#define FIRST_COMPUTE_VMID (8)
1669#define LAST_COMPUTE_VMID (16)
1670static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1671{
1672 int i;
1673 uint32_t sh_mem_config;
1674 uint32_t sh_mem_bases;
1675
1676 /*
1677 * Configure apertures:
1678 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1679 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1680 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1681 */
1682 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1683 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1684 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1685 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1686 mutex_lock(&adev->srbm_mutex);
1687 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1688 cik_srbm_select(adev, 0, 0, 0, i);
1689 /* CP and shaders */
1690 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1691 WREG32(mmSH_MEM_APE1_BASE, 1);
1692 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1693 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1694 }
1695 cik_srbm_select(adev, 0, 0, 0, 0);
1696 mutex_unlock(&adev->srbm_mutex);
1697}
1698
a2e73f56
AD		 1699/**
1700 * gfx_v7_0_gpu_init - setup the 3D engine
1701 *
1702 * @adev: amdgpu_device pointer
1703 *
1704 * Configures the 3D engine and tiling configuration
1705 * registers so that the 3D engine is usable.
1706 */
1707static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1708{
d93f3ca7 1709 u32 tmp, sh_mem_cfg;
a2e73f56
AD		 1710 int i;
1711
a2e73f56
AD		 1712 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1713
d93f3ca7
AD		 1714 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1715 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1716 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
a2e73f56
AD		 1717
1718 gfx_v7_0_tiling_mode_table_init(adev);
1719
8f8e00c1 1720 gfx_v7_0_setup_rb(adev);
7dae69a2 1721 gfx_v7_0_get_cu_info(adev);
a2e73f56
AD		 1722
1723 /* set HW defaults for 3D engine */
1724 WREG32(mmCP_MEQ_THRESHOLDS,
d93f3ca7
AD		 1725 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1726 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
a2e73f56
AD		 1727
1728 mutex_lock(&adev->grbm_idx_mutex);
1729 /*
1730 * making sure that the following register writes will be broadcasted
1731 * to all the shaders
1732 */
1733 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1734
1735 /* XXX SH_MEM regs */
1736 /* where to put LDS, scratch, GPUVM in FSA64 space */
d93f3ca7 1737 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165
JX		 1738 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1739
a2e73f56
AD		 1740 mutex_lock(&adev->srbm_mutex);
1741 for (i = 0; i < 16; i++) {
1742 cik_srbm_select(adev, 0, 0, 0, i);
1743 /* CP and shaders */
74a5d165 1744 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
a2e73f56
AD		 1745 WREG32(mmSH_MEM_APE1_BASE, 1);
1746 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1747 WREG32(mmSH_MEM_BASES, 0);
1748 }
1749 cik_srbm_select(adev, 0, 0, 0, 0);
1750 mutex_unlock(&adev->srbm_mutex);
1751
cd06bf68
BG		 1752 gmc_v7_0_init_compute_vmid(adev);
1753
a2e73f56
AD		 1754 WREG32(mmSX_DEBUG_1, 0x20);
1755
1756 WREG32(mmTA_CNTL_AUX, 0x00010000);
1757
1758 tmp = RREG32(mmSPI_CONFIG_CNTL);
1759 tmp |= 0x03000000;
1760 WREG32(mmSPI_CONFIG_CNTL, tmp);
1761
1762 WREG32(mmSQ_CONFIG, 1);
1763
1764 WREG32(mmDB_DEBUG, 0);
1765
1766 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1767 tmp |= 0x00000400;
1768 WREG32(mmDB_DEBUG2, tmp);
1769
1770 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1771 tmp |= 0x00020200;
1772 WREG32(mmDB_DEBUG3, tmp);
1773
1774 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1775 tmp |= 0x00018208;
1776 WREG32(mmCB_HW_CONTROL, tmp);
1777
1778 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1779
1780 WREG32(mmPA_SC_FIFO_SIZE,
1781 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1782 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1783 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1784 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1785
1786 WREG32(mmVGT_NUM_INSTANCES, 1);
1787
1788 WREG32(mmCP_PERFMON_CNTL, 0);
1789
1790 WREG32(mmSQ_CONFIG, 0);
1791
1792 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1793 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1794 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1795
1796 WREG32(mmVGT_CACHE_INVALIDATION,
1797 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1798 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1799
1800 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1801 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1802
1803 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1804 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1805 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1806 mutex_unlock(&adev->grbm_idx_mutex);
1807
1808 udelay(50);
1809}
1810
1811/*
1812 * GPU scratch registers helpers function.
1813 */
1814/**
1815 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1816 *
1817 * @adev: amdgpu_device pointer
1818 *
1819 * Set up the number and offset of the CP scratch registers.
1820 * NOTE: use of CP scratch registers is a legacy inferface and
1821 * is not used by default on newer asics (r6xx+). On newer asics,
1822 * memory buffers are used for fences rather than scratch regs.
1823 */
1824static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
1825{
1826 int i;
1827
1828 adev->gfx.scratch.num_reg = 7;
1829 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1830 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1831 adev->gfx.scratch.free[i] = true;
1832 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1833 }
1834}
1835
1836/**
1837 * gfx_v7_0_ring_test_ring - basic gfx ring test
1838 *
1839 * @adev: amdgpu_device pointer
1840 * @ring: amdgpu_ring structure holding ring information
1841 *
1842 * Allocate a scratch register and write to it using the gfx ring (CIK).
1843 * Provides a basic gfx ring test to verify that the ring is working.
1844 * Used by gfx_v7_0_cp_gfx_resume();
1845 * Returns 0 on success, error on failure.
1846 */
1847static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1848{
1849 struct amdgpu_device *adev = ring->adev;
1850 uint32_t scratch;
1851 uint32_t tmp = 0;
1852 unsigned i;
1853 int r;
1854
1855 r = amdgpu_gfx_scratch_get(adev, &scratch);
1856 if (r) {
1857 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1858 return r;
1859 }
1860 WREG32(scratch, 0xCAFEDEAD);
a27de35c 1861 r = amdgpu_ring_alloc(ring, 3);
a2e73f56
AD		 1862 if (r) {
1863 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1864 amdgpu_gfx_scratch_free(adev, scratch);
1865 return r;
1866 }
1867 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1868 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
1869 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 1870 amdgpu_ring_commit(ring);
a2e73f56
AD		 1871
1872 for (i = 0; i < adev->usec_timeout; i++) {
1873 tmp = RREG32(scratch);
1874 if (tmp == 0xDEADBEEF)
1875 break;
1876 DRM_UDELAY(1);
1877 }
1878 if (i < adev->usec_timeout) {
1879 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1880 } else {
1881 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1882 ring->idx, scratch, tmp);
1883 r = -EINVAL;
1884 }
1885 amdgpu_gfx_scratch_free(adev, scratch);
1886 return r;
1887}
1888
1889/**
d2edb07b 1890 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
a2e73f56
AD		 1891 *
1892 * @adev: amdgpu_device pointer
1893 * @ridx: amdgpu ring index
1894 *
1895 * Emits an hdp flush on the cp.
1896 */
d2edb07b 1897static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 1898{
1899 u32 ref_and_mask;
d9b5327a 1900 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
a2e73f56
AD		 1901
1902 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
1903 switch (ring->me) {
1904 case 1:
1905 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
1906 break;
1907 case 2:
1908 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
1909 break;
1910 default:
1911 return;
1912 }
1913 } else {
1914 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
1915 }
1916
1917 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1918 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
1919 WAIT_REG_MEM_FUNCTION(3) | /* == */
d9b5327a 1920 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
a2e73f56
AD		 1921 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
1922 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
1923 amdgpu_ring_write(ring, ref_and_mask);
1924 amdgpu_ring_write(ring, ref_and_mask);
1925 amdgpu_ring_write(ring, 0x20); /* poll interval */
1926}
1927
0955860b
CZ		 1928/**
1929 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1930 *
1931 * @adev: amdgpu_device pointer
1932 * @ridx: amdgpu ring index
1933 *
1934 * Emits an hdp invalidate on the cp.
1935 */
1936static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1937{
1938 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1939 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
1940 WRITE_DATA_DST_SEL(0) |
1941 WR_CONFIRM));
1942 amdgpu_ring_write(ring, mmHDP_DEBUG0);
1943 amdgpu_ring_write(ring, 0);
1944 amdgpu_ring_write(ring, 1);
1945}
1946
a2e73f56
AD		 1947/**
1948 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
1949 *
1950 * @adev: amdgpu_device pointer
1951 * @fence: amdgpu fence object
1952 *
1953 * Emits a fence sequnce number on the gfx ring and flushes
1954 * GPU caches.
1955 */
1956static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 1957 u64 seq, unsigned flags)
a2e73f56 1958{
890ee23f
CZ		 1959 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1960 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
a2e73f56
AD		 1961 /* Workaround for cache flush problems. First send a dummy EOP
1962 * event down the pipe with seq one below.
1963 */
1964 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1965 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1966 EOP_TC_ACTION_EN |
1967 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1968 EVENT_INDEX(5)));
1969 amdgpu_ring_write(ring, addr & 0xfffffffc);
1970 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1971 DATA_SEL(1) | INT_SEL(0));
1972 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
1973 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
1974
1975 /* Then send the real EOP event down the pipe. */
1976 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1977 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1978 EOP_TC_ACTION_EN |
1979 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1980 EVENT_INDEX(5)));
1981 amdgpu_ring_write(ring, addr & 0xfffffffc);
1982 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 1983 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 1984 amdgpu_ring_write(ring, lower_32_bits(seq));
1985 amdgpu_ring_write(ring, upper_32_bits(seq));
1986}
1987
1988/**
1989 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
1990 *
1991 * @adev: amdgpu_device pointer
1992 * @fence: amdgpu fence object
1993 *
1994 * Emits a fence sequnce number on the compute ring and flushes
1995 * GPU caches.
1996 */
1997static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
1998 u64 addr, u64 seq,
890ee23f 1999 unsigned flags)
a2e73f56 2000{
890ee23f
CZ		 2001 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2002 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2003
a2e73f56
AD		 2004 /* RELEASE_MEM - flush caches, send int */
2005 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2006 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2007 EOP_TC_ACTION_EN |
2008 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2009 EVENT_INDEX(5)));
890ee23f 2010 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2011 amdgpu_ring_write(ring, addr & 0xfffffffc);
2012 amdgpu_ring_write(ring, upper_32_bits(addr));
2013 amdgpu_ring_write(ring, lower_32_bits(seq));
2014 amdgpu_ring_write(ring, upper_32_bits(seq));
2015}
2016
a2e73f56
AD		 2017/*
2018 * IB stuff
2019 */
2020/**
2021 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2022 *
2023 * @ring: amdgpu_ring structure holding ring information
2024 * @ib: amdgpu indirect buffer object
2025 *
2026 * Emits an DE (drawing engine) or CE (constant engine) IB
2027 * on the gfx ring. IBs are usually generated by userspace
2028 * acceleration drivers and submitted to the kernel for
2029 * sheduling on the ring. This function schedules the IB
2030 * on the gfx ring for execution by the GPU.
2031 */
93323131 2032static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
f153d286 2033 struct amdgpu_ib *ib, bool ctx_switch)
a2e73f56
AD		 2034{
2035 u32 header, control = 0;
2036 u32 next_rptr = ring->wptr + 5;
aa2bdb24 2037
f153d286 2038 if (ctx_switch)
a2e73f56
AD		 2039 next_rptr += 2;
2040
2041 next_rptr += 4;
2042 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2043 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2044 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2045 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2046 amdgpu_ring_write(ring, next_rptr);
2047
a2e73f56 2048 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
f153d286 2049 if (ctx_switch) {
a2e73f56
AD		 2050 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2051 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 2052 }
2053
de807f81 2054 if (ib->flags & AMDGPU_IB_FLAG_CE)
a2e73f56
AD		 2055 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2056 else
2057 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2058
4ff37a83 2059 control |= ib->length_dw | (ib->vm_id << 24);
a2e73f56
AD		 2060
2061 amdgpu_ring_write(ring, header);
2062 amdgpu_ring_write(ring,
2063#ifdef __BIG_ENDIAN
2064 (2 << 0) |
2065#endif
2066 (ib->gpu_addr & 0xFFFFFFFC));
2067 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2068 amdgpu_ring_write(ring, control);
2069}
2070
93323131 2071static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
f153d286 2072 struct amdgpu_ib *ib, bool ctx_switch)
93323131 2073{
2074 u32 header, control = 0;
2075 u32 next_rptr = ring->wptr + 5;
2076
2077 control |= INDIRECT_BUFFER_VALID;
2078 next_rptr += 4;
2079 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2080 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2081 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2082 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2083 amdgpu_ring_write(ring, next_rptr);
2084
2085 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2086
4ff37a83 2087 control |= ib->length_dw | (ib->vm_id << 24);
93323131 2088
2089 amdgpu_ring_write(ring, header);
2090 amdgpu_ring_write(ring,
2091#ifdef __BIG_ENDIAN
2092 (2 << 0) |
2093#endif
2094 (ib->gpu_addr & 0xFFFFFFFC));
2095 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2096 amdgpu_ring_write(ring, control);
2097}
2098
a2e73f56
AD		 2099/**
2100 * gfx_v7_0_ring_test_ib - basic ring IB test
2101 *
2102 * @ring: amdgpu_ring structure holding ring information
2103 *
2104 * Allocate an IB and execute it on the gfx ring (CIK).
2105 * Provides a basic gfx ring test to verify that IBs are working.
2106 * Returns 0 on success, error on failure.
2107 */
2108static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2109{
2110 struct amdgpu_device *adev = ring->adev;
2111 struct amdgpu_ib ib;
1763552e 2112 struct fence *f = NULL;
a2e73f56
AD		 2113 uint32_t scratch;
2114 uint32_t tmp = 0;
2115 unsigned i;
2116 int r;
2117
2118 r = amdgpu_gfx_scratch_get(adev, &scratch);
2119 if (r) {
2120 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2121 return r;
2122 }
2123 WREG32(scratch, 0xCAFEDEAD);
b203dd95 2124 memset(&ib, 0, sizeof(ib));
b07c60c0 2125 r = amdgpu_ib_get(adev, NULL, 256, &ib);
a2e73f56
AD		 2126 if (r) {
2127 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
42d13693 2128 goto err1;
a2e73f56
AD		 2129 }
2130 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2131 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2132 ib.ptr[2] = 0xDEADBEEF;
2133 ib.length_dw = 3;
42d13693 2134
c5637837 2135 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
42d13693
CZ		 2136 if (r)
2137 goto err2;
2138
1763552e 2139 r = fence_wait(f, false);
a2e73f56
AD		 2140 if (r) {
2141 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
42d13693 2142 goto err2;
a2e73f56
AD		 2143 }
2144 for (i = 0; i < adev->usec_timeout; i++) {
2145 tmp = RREG32(scratch);
2146 if (tmp == 0xDEADBEEF)
2147 break;
2148 DRM_UDELAY(1);
2149 }
2150 if (i < adev->usec_timeout) {
2151 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
42d13693
CZ		 2152 ring->idx, i);
2153 goto err2;
a2e73f56
AD		 2154 } else {
2155 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2156 scratch, tmp);
2157 r = -EINVAL;
2158 }
42d13693
CZ		 2159
2160err2:
281b4223 2161 fence_put(f);
cc55c45d 2162 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 2163 fence_put(f);
42d13693
CZ		 2164err1:
2165 amdgpu_gfx_scratch_free(adev, scratch);
a2e73f56
AD		 2166 return r;
2167}
2168
2169/*
2170 * CP.
2171 * On CIK, gfx and compute now have independant command processors.
2172 *
2173 * GFX
2174 * Gfx consists of a single ring and can process both gfx jobs and
2175 * compute jobs. The gfx CP consists of three microengines (ME):
2176 * PFP - Pre-Fetch Parser
2177 * ME - Micro Engine
2178 * CE - Constant Engine
2179 * The PFP and ME make up what is considered the Drawing Engine (DE).
2180 * The CE is an asynchronous engine used for updating buffer desciptors
2181 * used by the DE so that they can be loaded into cache in parallel
2182 * while the DE is processing state update packets.
2183 *
2184 * Compute
2185 * The compute CP consists of two microengines (ME):
2186 * MEC1 - Compute MicroEngine 1
2187 * MEC2 - Compute MicroEngine 2
2188 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2189 * The queues are exposed to userspace and are programmed directly
2190 * by the compute runtime.
2191 */
2192/**
2193 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2194 *
2195 * @adev: amdgpu_device pointer
2196 * @enable: enable or disable the MEs
2197 *
2198 * Halts or unhalts the gfx MEs.
2199 */
2200static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2201{
2202 int i;
2203
2204 if (enable) {
2205 WREG32(mmCP_ME_CNTL, 0);
2206 } else {
2207 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2208 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2209 adev->gfx.gfx_ring[i].ready = false;
2210 }
2211 udelay(50);
2212}
2213
2214/**
2215 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2216 *
2217 * @adev: amdgpu_device pointer
2218 *
2219 * Loads the gfx PFP, ME, and CE ucode.
2220 * Returns 0 for success, -EINVAL if the ucode is not available.
2221 */
2222static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2223{
2224 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2225 const struct gfx_firmware_header_v1_0 *ce_hdr;
2226 const struct gfx_firmware_header_v1_0 *me_hdr;
2227 const __le32 *fw_data;
2228 unsigned i, fw_size;
2229
2230 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2231 return -EINVAL;
2232
2233 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2234 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2235 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2236
2237 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2238 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2239 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2240 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2241 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2242 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
02558a00
KW		 2243 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2244 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2245 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
a2e73f56
AD		 2246
2247 gfx_v7_0_cp_gfx_enable(adev, false);
2248
2249 /* PFP */
2250 fw_data = (const __le32 *)
2251 (adev->gfx.pfp_fw->data +
2252 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2253 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2254 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2255 for (i = 0; i < fw_size; i++)
2256 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2257 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2258
2259 /* CE */
2260 fw_data = (const __le32 *)
2261 (adev->gfx.ce_fw->data +
2262 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2263 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2264 WREG32(mmCP_CE_UCODE_ADDR, 0);
2265 for (i = 0; i < fw_size; i++)
2266 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2267 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2268
2269 /* ME */
2270 fw_data = (const __le32 *)
2271 (adev->gfx.me_fw->data +
2272 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2273 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2274 WREG32(mmCP_ME_RAM_WADDR, 0);
2275 for (i = 0; i < fw_size; i++)
2276 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2277 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2278
2279 return 0;
2280}
2281
2282/**
2283 * gfx_v7_0_cp_gfx_start - start the gfx ring
2284 *
2285 * @adev: amdgpu_device pointer
2286 *
2287 * Enables the ring and loads the clear state context and other
2288 * packets required to init the ring.
2289 * Returns 0 for success, error for failure.
2290 */
2291static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2292{
2293 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2294 const struct cs_section_def *sect = NULL;
2295 const struct cs_extent_def *ext = NULL;
2296 int r, i;
2297
2298 /* init the CP */
2299 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2300 WREG32(mmCP_ENDIAN_SWAP, 0);
2301 WREG32(mmCP_DEVICE_ID, 1);
2302
2303 gfx_v7_0_cp_gfx_enable(adev, true);
2304
a27de35c 2305 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
a2e73f56
AD		 2306 if (r) {
2307 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2308 return r;
2309 }
2310
2311 /* init the CE partitions. CE only used for gfx on CIK */
2312 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2313 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2314 amdgpu_ring_write(ring, 0x8000);
2315 amdgpu_ring_write(ring, 0x8000);
2316
2317 /* clear state buffer */
2318 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2319 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2320
2321 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2322 amdgpu_ring_write(ring, 0x80000000);
2323 amdgpu_ring_write(ring, 0x80000000);
2324
2325 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2326 for (ext = sect->section; ext->extent != NULL; ++ext) {
2327 if (sect->id == SECT_CONTEXT) {
2328 amdgpu_ring_write(ring,
2329 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2330 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2331 for (i = 0; i < ext->reg_count; i++)
2332 amdgpu_ring_write(ring, ext->extent[i]);
2333 }
2334 }
2335 }
2336
2337 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2338 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2339 switch (adev->asic_type) {
2340 case CHIP_BONAIRE:
2341 amdgpu_ring_write(ring, 0x16000012);
2342 amdgpu_ring_write(ring, 0x00000000);
2343 break;
2344 case CHIP_KAVERI:
2345 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2346 amdgpu_ring_write(ring, 0x00000000);
2347 break;
2348 case CHIP_KABINI:
2349 case CHIP_MULLINS:
2350 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2351 amdgpu_ring_write(ring, 0x00000000);
2352 break;
2353 case CHIP_HAWAII:
2354 amdgpu_ring_write(ring, 0x3a00161a);
2355 amdgpu_ring_write(ring, 0x0000002e);
2356 break;
2357 default:
2358 amdgpu_ring_write(ring, 0x00000000);
2359 amdgpu_ring_write(ring, 0x00000000);
2360 break;
2361 }
2362
2363 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2364 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2365
2366 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2367 amdgpu_ring_write(ring, 0);
2368
2369 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2370 amdgpu_ring_write(ring, 0x00000316);
2371 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2372 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2373
a27de35c 2374 amdgpu_ring_commit(ring);
a2e73f56
AD		 2375
2376 return 0;
2377}
2378
2379/**
2380 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2381 *
2382 * @adev: amdgpu_device pointer
2383 *
2384 * Program the location and size of the gfx ring buffer
2385 * and test it to make sure it's working.
2386 * Returns 0 for success, error for failure.
2387 */
2388static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2389{
2390 struct amdgpu_ring *ring;
2391 u32 tmp;
2392 u32 rb_bufsz;
2393 u64 rb_addr, rptr_addr;
2394 int r;
2395
2396 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2397 if (adev->asic_type != CHIP_HAWAII)
2398 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2399
2400 /* Set the write pointer delay */
2401 WREG32(mmCP_RB_WPTR_DELAY, 0);
2402
2403 /* set the RB to use vmid 0 */
2404 WREG32(mmCP_RB_VMID, 0);
2405
2406 WREG32(mmSCRATCH_ADDR, 0);
2407
2408 /* ring 0 - compute and gfx */
2409 /* Set ring buffer size */
2410 ring = &adev->gfx.gfx_ring[0];
2411 rb_bufsz = order_base_2(ring->ring_size / 8);
2412 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2413#ifdef __BIG_ENDIAN
454fc95e 2414 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
a2e73f56
AD		 2415#endif
2416 WREG32(mmCP_RB0_CNTL, tmp);
2417
2418 /* Initialize the ring buffer's read and write pointers */
2419 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2420 ring->wptr = 0;
2421 WREG32(mmCP_RB0_WPTR, ring->wptr);
2422
2423 /* set the wb address wether it's enabled or not */
2424 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2425 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2426 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2427
2428 /* scratch register shadowing is no longer supported */
2429 WREG32(mmSCRATCH_UMSK, 0);
2430
2431 mdelay(1);
2432 WREG32(mmCP_RB0_CNTL, tmp);
2433
2434 rb_addr = ring->gpu_addr >> 8;
2435 WREG32(mmCP_RB0_BASE, rb_addr);
2436 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2437
2438 /* start the ring */
2439 gfx_v7_0_cp_gfx_start(adev);
2440 ring->ready = true;
2441 r = amdgpu_ring_test_ring(ring);
2442 if (r) {
2443 ring->ready = false;
2444 return r;
2445 }
2446
2447 return 0;
2448}
2449
2450static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2451{
7edd6b2f 2452 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2453}
2454
2455static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2456{
2457 struct amdgpu_device *adev = ring->adev;
a2e73f56 2458
7edd6b2f 2459 return RREG32(mmCP_RB0_WPTR);
a2e73f56
AD		 2460}
2461
2462static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2463{
2464 struct amdgpu_device *adev = ring->adev;
2465
2466 WREG32(mmCP_RB0_WPTR, ring->wptr);
2467 (void)RREG32(mmCP_RB0_WPTR);
2468}
2469
2470static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2471{
7edd6b2f 2472 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2473}
2474
2475static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2476{
a2e73f56 2477 /* XXX check if swapping is necessary on BE */
7edd6b2f 2478 return ring->adev->wb.wb[ring->wptr_offs];
a2e73f56
AD		 2479}
2480
2481static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2482{
2483 struct amdgpu_device *adev = ring->adev;
2484
2485 /* XXX check if swapping is necessary on BE */
2486 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2487 WDOORBELL32(ring->doorbell_index, ring->wptr);
2488}
2489
2490/**
2491 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2492 *
2493 * @adev: amdgpu_device pointer
2494 * @enable: enable or disable the MEs
2495 *
2496 * Halts or unhalts the compute MEs.
2497 */
2498static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2499{
2500 int i;
2501
2502 if (enable) {
2503 WREG32(mmCP_MEC_CNTL, 0);
2504 } else {
2505 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2506 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2507 adev->gfx.compute_ring[i].ready = false;
2508 }
2509 udelay(50);
2510}
2511
2512/**
2513 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2514 *
2515 * @adev: amdgpu_device pointer
2516 *
2517 * Loads the compute MEC1&2 ucode.
2518 * Returns 0 for success, -EINVAL if the ucode is not available.
2519 */
2520static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2521{
2522 const struct gfx_firmware_header_v1_0 *mec_hdr;
2523 const __le32 *fw_data;
2524 unsigned i, fw_size;
2525
2526 if (!adev->gfx.mec_fw)
2527 return -EINVAL;
2528
2529 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2530 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2531 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
351643d7
JZ		 2532 adev->gfx.mec_feature_version = le32_to_cpu(
2533 mec_hdr->ucode_feature_version);
a2e73f56
AD		 2534
2535 gfx_v7_0_cp_compute_enable(adev, false);
2536
2537 /* MEC1 */
2538 fw_data = (const __le32 *)
2539 (adev->gfx.mec_fw->data +
2540 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2541 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2542 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2543 for (i = 0; i < fw_size; i++)
2544 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2545 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2546
2547 if (adev->asic_type == CHIP_KAVERI) {
2548 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2549
2550 if (!adev->gfx.mec2_fw)
2551 return -EINVAL;
2552
2553 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2554 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2555 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
351643d7
JZ		 2556 adev->gfx.mec2_feature_version = le32_to_cpu(
2557 mec2_hdr->ucode_feature_version);
a2e73f56
AD		 2558
2559 /* MEC2 */
2560 fw_data = (const __le32 *)
2561 (adev->gfx.mec2_fw->data +
2562 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2563 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2564 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2565 for (i = 0; i < fw_size; i++)
2566 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2567 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2568 }
2569
2570 return 0;
2571}
2572
a2e73f56
AD		 2573/**
2574 * gfx_v7_0_cp_compute_fini - stop the compute queues
2575 *
2576 * @adev: amdgpu_device pointer
2577 *
2578 * Stop the compute queues and tear down the driver queue
2579 * info.
2580 */
2581static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2582{
2583 int i, r;
2584
2585 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2586 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2587
2588 if (ring->mqd_obj) {
2589 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2590 if (unlikely(r != 0))
2591 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2592
2593 amdgpu_bo_unpin(ring->mqd_obj);
2594 amdgpu_bo_unreserve(ring->mqd_obj);
2595
2596 amdgpu_bo_unref(&ring->mqd_obj);
2597 ring->mqd_obj = NULL;
2598 }
2599 }
2600}
2601
2602static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2603{
2604 int r;
2605
2606 if (adev->gfx.mec.hpd_eop_obj) {
2607 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2608 if (unlikely(r != 0))
2609 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2610 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2611 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2612
2613 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2614 adev->gfx.mec.hpd_eop_obj = NULL;
2615 }
2616}
2617
2618#define MEC_HPD_SIZE 2048
2619
2620static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2621{
2622 int r;
2623 u32 *hpd;
2624
2625 /*
2626 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2627 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2628 * Nonetheless, we assign only 1 pipe because all other pipes will
2629 * be handled by KFD
2630 */
2631 adev->gfx.mec.num_mec = 1;
2632 adev->gfx.mec.num_pipe = 1;
2633 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2634
2635 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2636 r = amdgpu_bo_create(adev,
2637 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2638 PAGE_SIZE, true,
72d7668b 2639 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2640 &adev->gfx.mec.hpd_eop_obj);
2641 if (r) {
2642 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2643 return r;
2644 }
2645 }
2646
2647 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2648 if (unlikely(r != 0)) {
2649 gfx_v7_0_mec_fini(adev);
2650 return r;
2651 }
2652 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2653 &adev->gfx.mec.hpd_eop_gpu_addr);
2654 if (r) {
2655 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2656 gfx_v7_0_mec_fini(adev);
2657 return r;
2658 }
2659 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2660 if (r) {
2661 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2662 gfx_v7_0_mec_fini(adev);
2663 return r;
2664 }
2665
2666 /* clear memory. Not sure if this is required or not */
2667 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2668
2669 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2670 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2671
2672 return 0;
2673}
2674
2675struct hqd_registers
2676{
2677 u32 cp_mqd_base_addr;
2678 u32 cp_mqd_base_addr_hi;
2679 u32 cp_hqd_active;
2680 u32 cp_hqd_vmid;
2681 u32 cp_hqd_persistent_state;
2682 u32 cp_hqd_pipe_priority;
2683 u32 cp_hqd_queue_priority;
2684 u32 cp_hqd_quantum;
2685 u32 cp_hqd_pq_base;
2686 u32 cp_hqd_pq_base_hi;
2687 u32 cp_hqd_pq_rptr;
2688 u32 cp_hqd_pq_rptr_report_addr;
2689 u32 cp_hqd_pq_rptr_report_addr_hi;
2690 u32 cp_hqd_pq_wptr_poll_addr;
2691 u32 cp_hqd_pq_wptr_poll_addr_hi;
2692 u32 cp_hqd_pq_doorbell_control;
2693 u32 cp_hqd_pq_wptr;
2694 u32 cp_hqd_pq_control;
2695 u32 cp_hqd_ib_base_addr;
2696 u32 cp_hqd_ib_base_addr_hi;
2697 u32 cp_hqd_ib_rptr;
2698 u32 cp_hqd_ib_control;
2699 u32 cp_hqd_iq_timer;
2700 u32 cp_hqd_iq_rptr;
2701 u32 cp_hqd_dequeue_request;
2702 u32 cp_hqd_dma_offload;
2703 u32 cp_hqd_sema_cmd;
2704 u32 cp_hqd_msg_type;
2705 u32 cp_hqd_atomic0_preop_lo;
2706 u32 cp_hqd_atomic0_preop_hi;
2707 u32 cp_hqd_atomic1_preop_lo;
2708 u32 cp_hqd_atomic1_preop_hi;
2709 u32 cp_hqd_hq_scheduler0;
2710 u32 cp_hqd_hq_scheduler1;
2711 u32 cp_mqd_control;
2712};
2713
2714struct bonaire_mqd
2715{
2716 u32 header;
2717 u32 dispatch_initiator;
2718 u32 dimensions[3];
2719 u32 start_idx[3];
2720 u32 num_threads[3];
2721 u32 pipeline_stat_enable;
2722 u32 perf_counter_enable;
2723 u32 pgm[2];
2724 u32 tba[2];
2725 u32 tma[2];
2726 u32 pgm_rsrc[2];
2727 u32 vmid;
2728 u32 resource_limits;
2729 u32 static_thread_mgmt01[2];
2730 u32 tmp_ring_size;
2731 u32 static_thread_mgmt23[2];
2732 u32 restart[3];
2733 u32 thread_trace_enable;
2734 u32 reserved1;
2735 u32 user_data[16];
2736 u32 vgtcs_invoke_count[2];
2737 struct hqd_registers queue_state;
2738 u32 dequeue_cntr;
2739 u32 interrupt_queue[64];
2740};
2741
2742/**
2743 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2744 *
2745 * @adev: amdgpu_device pointer
2746 *
2747 * Program the compute queues and test them to make sure they
2748 * are working.
2749 * Returns 0 for success, error for failure.
2750 */
2751static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2752{
2753 int r, i, j;
2754 u32 tmp;
2755 bool use_doorbell = true;
2756 u64 hqd_gpu_addr;
2757 u64 mqd_gpu_addr;
2758 u64 eop_gpu_addr;
2759 u64 wb_gpu_addr;
2760 u32 *buf;
2761 struct bonaire_mqd *mqd;
2762
6e9821b2 2763 gfx_v7_0_cp_compute_enable(adev, true);
a2e73f56
AD		 2764
2765 /* fix up chicken bits */
2766 tmp = RREG32(mmCP_CPF_DEBUG);
2767 tmp |= (1 << 23);
2768 WREG32(mmCP_CPF_DEBUG, tmp);
2769
2770 /* init the pipes */
2771 mutex_lock(&adev->srbm_mutex);
2772 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2773 int me = (i < 4) ? 1 : 2;
2774 int pipe = (i < 4) ? i : (i - 4);
2775
2776 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2777
2778 cik_srbm_select(adev, me, pipe, 0, 0);
2779
2780 /* write the EOP addr */
2781 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2782 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2783
2784 /* set the VMID assigned */
2785 WREG32(mmCP_HPD_EOP_VMID, 0);
2786
2787 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2788 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2789 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2790 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2791 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2792 }
2793 cik_srbm_select(adev, 0, 0, 0, 0);
2794 mutex_unlock(&adev->srbm_mutex);
2795
2796 /* init the queues. Just two for now. */
2797 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2798 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2799
2800 if (ring->mqd_obj == NULL) {
2801 r = amdgpu_bo_create(adev,
2802 sizeof(struct bonaire_mqd),
2803 PAGE_SIZE, true,
72d7668b 2804 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2805 &ring->mqd_obj);
2806 if (r) {
2807 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2808 return r;
2809 }
2810 }
2811
2812 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2813 if (unlikely(r != 0)) {
2814 gfx_v7_0_cp_compute_fini(adev);
2815 return r;
2816 }
2817 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2818 &mqd_gpu_addr);
2819 if (r) {
2820 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2821 gfx_v7_0_cp_compute_fini(adev);
2822 return r;
2823 }
2824 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2825 if (r) {
2826 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2827 gfx_v7_0_cp_compute_fini(adev);
2828 return r;
2829 }
2830
2831 /* init the mqd struct */
2832 memset(buf, 0, sizeof(struct bonaire_mqd));
2833
2834 mqd = (struct bonaire_mqd *)buf;
2835 mqd->header = 0xC0310800;
2836 mqd->static_thread_mgmt01[0] = 0xffffffff;
2837 mqd->static_thread_mgmt01[1] = 0xffffffff;
2838 mqd->static_thread_mgmt23[0] = 0xffffffff;
2839 mqd->static_thread_mgmt23[1] = 0xffffffff;
2840
2841 mutex_lock(&adev->srbm_mutex);
2842 cik_srbm_select(adev, ring->me,
2843 ring->pipe,
2844 ring->queue, 0);
2845
2846 /* disable wptr polling */
2847 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2848 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
2849 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2850
2851 /* enable doorbell? */
2852 mqd->queue_state.cp_hqd_pq_doorbell_control =
2853 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2854 if (use_doorbell)
2855 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2856 else
2857 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2858 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2859 mqd->queue_state.cp_hqd_pq_doorbell_control);
2860
2861 /* disable the queue if it's active */
2862 mqd->queue_state.cp_hqd_dequeue_request = 0;
2863 mqd->queue_state.cp_hqd_pq_rptr = 0;
2864 mqd->queue_state.cp_hqd_pq_wptr= 0;
2865 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2866 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2867 for (j = 0; j < adev->usec_timeout; j++) {
2868 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2869 break;
2870 udelay(1);
2871 }
2872 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
2873 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
2874 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2875 }
2876
2877 /* set the pointer to the MQD */
2878 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
2879 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2880 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
2881 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
2882 /* set MQD vmid to 0 */
2883 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2884 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2885 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
2886
2887 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2888 hqd_gpu_addr = ring->gpu_addr >> 8;
2889 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
2890 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2891 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
2892 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
2893
2894 /* set up the HQD, this is similar to CP_RB0_CNTL */
2895 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2896 mqd->queue_state.cp_hqd_pq_control &=
2897 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2898 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2899
2900 mqd->queue_state.cp_hqd_pq_control |=
2901 order_base_2(ring->ring_size / 8);
2902 mqd->queue_state.cp_hqd_pq_control |=
2903 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2904#ifdef __BIG_ENDIAN
454fc95e
AD		 2905 mqd->queue_state.cp_hqd_pq_control |=
2906 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
a2e73f56
AD		 2907#endif
2908 mqd->queue_state.cp_hqd_pq_control &=
2909 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2910 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2911 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2912 mqd->queue_state.cp_hqd_pq_control |=
2913 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2914 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2915 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
2916
2917 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2918 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2919 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
2920 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2921 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
2922 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2923 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
2924
2925 /* set the wb address wether it's enabled or not */
2926 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2927 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
2928 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
2929 upper_32_bits(wb_gpu_addr) & 0xffff;
2930 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2931 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
2932 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2933 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
2934
2935 /* enable the doorbell if requested */
2936 if (use_doorbell) {
2937 mqd->queue_state.cp_hqd_pq_doorbell_control =
2938 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2939 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2940 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2941 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2942 (ring->doorbell_index <<
2943 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2944 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2945 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2946 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2947 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2948 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2949
2950 } else {
2951 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
2952 }
2953 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2954 mqd->queue_state.cp_hqd_pq_doorbell_control);
2955
2956 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2957 ring->wptr = 0;
2958 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
2959 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2960 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2961
2962 /* set the vmid for the queue */
2963 mqd->queue_state.cp_hqd_vmid = 0;
2964 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
2965
2966 /* activate the queue */
2967 mqd->queue_state.cp_hqd_active = 1;
2968 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
2969
2970 cik_srbm_select(adev, 0, 0, 0, 0);
2971 mutex_unlock(&adev->srbm_mutex);
2972
2973 amdgpu_bo_kunmap(ring->mqd_obj);
2974 amdgpu_bo_unreserve(ring->mqd_obj);
2975
2976 ring->ready = true;
2977 r = amdgpu_ring_test_ring(ring);
2978 if (r)
2979 ring->ready = false;
2980 }
2981
2982 return 0;
2983}
2984
2985static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
2986{
2987 gfx_v7_0_cp_gfx_enable(adev, enable);
2988 gfx_v7_0_cp_compute_enable(adev, enable);
2989}
2990
2991static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
2992{
2993 int r;
2994
2995 r = gfx_v7_0_cp_gfx_load_microcode(adev);
2996 if (r)
2997 return r;
2998 r = gfx_v7_0_cp_compute_load_microcode(adev);
2999 if (r)
3000 return r;
3001
3002 return 0;
3003}
3004
3005static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3006 bool enable)
3007{
3008 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3009
3010 if (enable)
3011 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3012 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3013 else
3014 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3015 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3016 WREG32(mmCP_INT_CNTL_RING0, tmp);
3017}
3018
3019static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3020{
3021 int r;
3022
3023 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3024
3025 r = gfx_v7_0_cp_load_microcode(adev);
3026 if (r)
3027 return r;
3028
3029 r = gfx_v7_0_cp_gfx_resume(adev);
3030 if (r)
3031 return r;
3032 r = gfx_v7_0_cp_compute_resume(adev);
3033 if (r)
3034 return r;
3035
3036 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3037
3038 return 0;
3039}
3040
b8c7b39e
CK		 3041/**
3042 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3043 *
3044 * @ring: the ring to emmit the commands to
3045 *
3046 * Sync the command pipeline with the PFP. E.g. wait for everything
3047 * to be completed.
3048 */
3049static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3050{
3051 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
914f9e18
CZ		 3052 uint32_t seq = ring->fence_drv.sync_seq;
3053 uint64_t addr = ring->fence_drv.gpu_addr;
3054
3055 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3056 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3057 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3058 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3059 amdgpu_ring_write(ring, addr & 0xfffffffc);
3060 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3061 amdgpu_ring_write(ring, seq);
3062 amdgpu_ring_write(ring, 0xffffffff);
3063 amdgpu_ring_write(ring, 4); /* poll interval */
3064
b8c7b39e
CK		 3065 if (usepfp) {
3066 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3067 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3068 amdgpu_ring_write(ring, 0);
3069 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3070 amdgpu_ring_write(ring, 0);
3071 }
3072}
3073
a2e73f56
AD		 3074/*
3075 * vm
3076 * VMID 0 is the physical GPU addresses as used by the kernel.
3077 * VMIDs 1-15 are used for userspace clients and are handled
3078 * by the amdgpu vm/hsa code.
3079 */
3080/**
3081 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3082 *
3083 * @adev: amdgpu_device pointer
3084 *
3085 * Update the page table base and flush the VM TLB
3086 * using the CP (CIK).
3087 */
3088static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3089 unsigned vm_id, uint64_t pd_addr)
3090{
3091 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
feebe91a 3092
a2e73f56
AD		 3093 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3094 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3095 WRITE_DATA_DST_SEL(0)));
3096 if (vm_id < 8) {
3097 amdgpu_ring_write(ring,
3098 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3099 } else {
3100 amdgpu_ring_write(ring,
3101 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3102 }
3103 amdgpu_ring_write(ring, 0);
3104 amdgpu_ring_write(ring, pd_addr >> 12);
3105
a2e73f56
AD		 3106 /* bits 0-15 are the VM contexts0-15 */
3107 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3108 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3109 WRITE_DATA_DST_SEL(0)));
3110 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3111 amdgpu_ring_write(ring, 0);
3112 amdgpu_ring_write(ring, 1 << vm_id);
3113
3114 /* wait for the invalidate to complete */
3115 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3116 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3117 WAIT_REG_MEM_FUNCTION(0) | /* always */
3118 WAIT_REG_MEM_ENGINE(0))); /* me */
3119 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3120 amdgpu_ring_write(ring, 0);
3121 amdgpu_ring_write(ring, 0); /* ref */
3122 amdgpu_ring_write(ring, 0); /* mask */
3123 amdgpu_ring_write(ring, 0x20); /* poll interval */
3124
3125 /* compute doesn't have PFP */
3126 if (usepfp) {
3127 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3128 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3129 amdgpu_ring_write(ring, 0x0);
3130
3131 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
5c3422b0 3132 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3133 amdgpu_ring_write(ring, 0);
3134 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3135 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 3136 }
3137}
3138
3139/*
3140 * RLC
3141 * The RLC is a multi-purpose microengine that handles a
3142 * variety of functions.
3143 */
3144static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3145{
3146 int r;
3147
3148 /* save restore block */
3149 if (adev->gfx.rlc.save_restore_obj) {
3150 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3151 if (unlikely(r != 0))
3152 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3153 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3154 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3155
3156 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3157 adev->gfx.rlc.save_restore_obj = NULL;
3158 }
3159
3160 /* clear state block */
3161 if (adev->gfx.rlc.clear_state_obj) {
3162 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3163 if (unlikely(r != 0))
3164 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3165 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3166 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3167
3168 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3169 adev->gfx.rlc.clear_state_obj = NULL;
3170 }
3171
3172 /* clear state block */
3173 if (adev->gfx.rlc.cp_table_obj) {
3174 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3175 if (unlikely(r != 0))
3176 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3177 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3178 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3179
3180 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3181 adev->gfx.rlc.cp_table_obj = NULL;
3182 }
3183}
3184
3185static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3186{
3187 const u32 *src_ptr;
3188 volatile u32 *dst_ptr;
3189 u32 dws, i;
3190 const struct cs_section_def *cs_data;
3191 int r;
3192
3193 /* allocate rlc buffers */
2f7d10b3 3194 if (adev->flags & AMD_IS_APU) {
a2e73f56
AD		 3195 if (adev->asic_type == CHIP_KAVERI) {
3196 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3197 adev->gfx.rlc.reg_list_size =
3198 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3199 } else {
3200 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3201 adev->gfx.rlc.reg_list_size =
3202 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3203 }
3204 }
3205 adev->gfx.rlc.cs_data = ci_cs_data;
3206 adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
3207
3208 src_ptr = adev->gfx.rlc.reg_list;
3209 dws = adev->gfx.rlc.reg_list_size;
3210 dws += (5 * 16) + 48 + 48 + 64;
3211
3212 cs_data = adev->gfx.rlc.cs_data;
3213
3214 if (src_ptr) {
3215 /* save restore block */
3216 if (adev->gfx.rlc.save_restore_obj == NULL) {
3217 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3218 AMDGPU_GEM_DOMAIN_VRAM,
3219 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3220 NULL, NULL,
3221 &adev->gfx.rlc.save_restore_obj);
a2e73f56
AD		 3222 if (r) {
3223 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3224 return r;
3225 }
3226 }
3227
3228 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3229 if (unlikely(r != 0)) {
3230 gfx_v7_0_rlc_fini(adev);
3231 return r;
3232 }
3233 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3234 &adev->gfx.rlc.save_restore_gpu_addr);
3235 if (r) {
3236 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3237 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3238 gfx_v7_0_rlc_fini(adev);
3239 return r;
3240 }
3241
3242 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3243 if (r) {
3244 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3245 gfx_v7_0_rlc_fini(adev);
3246 return r;
3247 }
3248 /* write the sr buffer */
3249 dst_ptr = adev->gfx.rlc.sr_ptr;
3250 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3251 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3252 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3253 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3254 }
3255
3256 if (cs_data) {
3257 /* clear state block */
3258 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3259
3260 if (adev->gfx.rlc.clear_state_obj == NULL) {
3261 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3262 AMDGPU_GEM_DOMAIN_VRAM,
3263 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3264 NULL, NULL,
3265 &adev->gfx.rlc.clear_state_obj);
a2e73f56
AD		 3266 if (r) {
3267 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3268 gfx_v7_0_rlc_fini(adev);
3269 return r;
3270 }
3271 }
3272 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3273 if (unlikely(r != 0)) {
3274 gfx_v7_0_rlc_fini(adev);
3275 return r;
3276 }
3277 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3278 &adev->gfx.rlc.clear_state_gpu_addr);
3279 if (r) {
3280 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3281 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3282 gfx_v7_0_rlc_fini(adev);
3283 return r;
3284 }
3285
3286 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3287 if (r) {
3288 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3289 gfx_v7_0_rlc_fini(adev);
3290 return r;
3291 }
3292 /* set up the cs buffer */
3293 dst_ptr = adev->gfx.rlc.cs_ptr;
3294 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3295 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3296 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3297 }
3298
3299 if (adev->gfx.rlc.cp_table_size) {
3300 if (adev->gfx.rlc.cp_table_obj == NULL) {
3301 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
857d913d
AD		 3302 AMDGPU_GEM_DOMAIN_VRAM,
3303 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3304 NULL, NULL,
3305 &adev->gfx.rlc.cp_table_obj);
a2e73f56
AD		 3306 if (r) {
3307 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3308 gfx_v7_0_rlc_fini(adev);
3309 return r;
3310 }
3311 }
3312
3313 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3314 if (unlikely(r != 0)) {
3315 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3316 gfx_v7_0_rlc_fini(adev);
3317 return r;
3318 }
3319 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3320 &adev->gfx.rlc.cp_table_gpu_addr);
3321 if (r) {
3322 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3323 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3324 gfx_v7_0_rlc_fini(adev);
3325 return r;
3326 }
3327 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3328 if (r) {
3329 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3330 gfx_v7_0_rlc_fini(adev);
3331 return r;
3332 }
3333
3334 gfx_v7_0_init_cp_pg_table(adev);
3335
3336 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3337 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3338
3339 }
3340
3341 return 0;
3342}
3343
3344static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3345{
3346 u32 tmp;
3347
3348 tmp = RREG32(mmRLC_LB_CNTL);
3349 if (enable)
3350 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3351 else
3352 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3353 WREG32(mmRLC_LB_CNTL, tmp);
3354}
3355
3356static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3357{
3358 u32 i, j, k;
3359 u32 mask;
3360
3361 mutex_lock(&adev->grbm_idx_mutex);
3362 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3363 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3364 gfx_v7_0_select_se_sh(adev, i, j);
3365 for (k = 0; k < adev->usec_timeout; k++) {
3366 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3367 break;
3368 udelay(1);
3369 }
3370 }
3371 }
3372 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3373 mutex_unlock(&adev->grbm_idx_mutex);
3374
3375 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3376 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3377 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3378 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3379 for (k = 0; k < adev->usec_timeout; k++) {
3380 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3381 break;
3382 udelay(1);
3383 }
3384}
3385
3386static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3387{
3388 u32 tmp;
3389
3390 tmp = RREG32(mmRLC_CNTL);
3391 if (tmp != rlc)
3392 WREG32(mmRLC_CNTL, rlc);
3393}
3394
3395static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3396{
3397 u32 data, orig;
3398
3399 orig = data = RREG32(mmRLC_CNTL);
3400
3401 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3402 u32 i;
3403
3404 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3405 WREG32(mmRLC_CNTL, data);
3406
3407 for (i = 0; i < adev->usec_timeout; i++) {
3408 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3409 break;
3410 udelay(1);
3411 }
3412
3413 gfx_v7_0_wait_for_rlc_serdes(adev);
3414 }
3415
3416 return orig;
3417}
3418
3419void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3420{
3421 u32 tmp, i, mask;
3422
3423 tmp = 0x1 | (1 << 1);
3424 WREG32(mmRLC_GPR_REG2, tmp);
3425
3426 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3427 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3428 for (i = 0; i < adev->usec_timeout; i++) {
3429 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3430 break;
3431 udelay(1);
3432 }
3433
3434 for (i = 0; i < adev->usec_timeout; i++) {
3435 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3436 break;
3437 udelay(1);
3438 }
3439}
3440
3441void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3442{
3443 u32 tmp;
3444
3445 tmp = 0x1 | (0 << 1);
3446 WREG32(mmRLC_GPR_REG2, tmp);
3447}
3448
3449/**
3450 * gfx_v7_0_rlc_stop - stop the RLC ME
3451 *
3452 * @adev: amdgpu_device pointer
3453 *
3454 * Halt the RLC ME (MicroEngine) (CIK).
3455 */
3456void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3457{
3458 WREG32(mmRLC_CNTL, 0);
3459
3460 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3461
3462 gfx_v7_0_wait_for_rlc_serdes(adev);
3463}
3464
3465/**
3466 * gfx_v7_0_rlc_start - start the RLC ME
3467 *
3468 * @adev: amdgpu_device pointer
3469 *
3470 * Unhalt the RLC ME (MicroEngine) (CIK).
3471 */
3472static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3473{
3474 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3475
3476 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3477
3478 udelay(50);
3479}
3480
3481static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3482{
3483 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3484
3485 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3486 WREG32(mmGRBM_SOFT_RESET, tmp);
3487 udelay(50);
3488 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3489 WREG32(mmGRBM_SOFT_RESET, tmp);
3490 udelay(50);
3491}
3492
3493/**
3494 * gfx_v7_0_rlc_resume - setup the RLC hw
3495 *
3496 * @adev: amdgpu_device pointer
3497 *
3498 * Initialize the RLC registers, load the ucode,
3499 * and start the RLC (CIK).
3500 * Returns 0 for success, -EINVAL if the ucode is not available.
3501 */
3502static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3503{
3504 const struct rlc_firmware_header_v1_0 *hdr;
3505 const __le32 *fw_data;
3506 unsigned i, fw_size;
3507 u32 tmp;
3508
3509 if (!adev->gfx.rlc_fw)
3510 return -EINVAL;
3511
3512 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3513 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3514 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
351643d7
JZ		 3515 adev->gfx.rlc_feature_version = le32_to_cpu(
3516 hdr->ucode_feature_version);
a2e73f56
AD		 3517
3518 gfx_v7_0_rlc_stop(adev);
3519
3520 /* disable CG */
3521 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3522 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3523
3524 gfx_v7_0_rlc_reset(adev);
3525
3526 gfx_v7_0_init_pg(adev);
3527
3528 WREG32(mmRLC_LB_CNTR_INIT, 0);
3529 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3530
3531 mutex_lock(&adev->grbm_idx_mutex);
3532 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3533 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3534 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3535 WREG32(mmRLC_LB_CNTL, 0x80000004);
3536 mutex_unlock(&adev->grbm_idx_mutex);
3537
3538 WREG32(mmRLC_MC_CNTL, 0);
3539 WREG32(mmRLC_UCODE_CNTL, 0);
3540
3541 fw_data = (const __le32 *)
3542 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3543 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3544 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3545 for (i = 0; i < fw_size; i++)
3546 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3547 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3548
3549 /* XXX - find out what chips support lbpw */
3550 gfx_v7_0_enable_lbpw(adev, false);
3551
3552 if (adev->asic_type == CHIP_BONAIRE)
3553 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3554
3555 gfx_v7_0_rlc_start(adev);
3556
3557 return 0;
3558}
3559
3560static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3561{
3562 u32 data, orig, tmp, tmp2;
3563
3564 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3565
e3b04bc7 3566 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
a2e73f56
AD		 3567 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3568
3569 tmp = gfx_v7_0_halt_rlc(adev);
3570
3571 mutex_lock(&adev->grbm_idx_mutex);
3572 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3573 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3574 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3575 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3576 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3577 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3578 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3579 mutex_unlock(&adev->grbm_idx_mutex);
3580
3581 gfx_v7_0_update_rlc(adev, tmp);
3582
3583 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3584 } else {
3585 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3586
3587 RREG32(mmCB_CGTT_SCLK_CTRL);
3588 RREG32(mmCB_CGTT_SCLK_CTRL);
3589 RREG32(mmCB_CGTT_SCLK_CTRL);
3590 RREG32(mmCB_CGTT_SCLK_CTRL);
3591
3592 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3593 }
3594
3595 if (orig != data)
3596 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3597
3598}
3599
3600static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3601{
3602 u32 data, orig, tmp = 0;
3603
e3b04bc7
AD		 3604 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3605 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3606 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
a2e73f56
AD		 3607 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3608 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3609 if (orig != data)
3610 WREG32(mmCP_MEM_SLP_CNTL, data);
3611 }
3612 }
3613
3614 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3615 data |= 0x00000001;
3616 data &= 0xfffffffd;
3617 if (orig != data)
3618 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3619
3620 tmp = gfx_v7_0_halt_rlc(adev);
3621
3622 mutex_lock(&adev->grbm_idx_mutex);
3623 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3624 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3625 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3626 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3627 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3628 WREG32(mmRLC_SERDES_WR_CTRL, data);
3629 mutex_unlock(&adev->grbm_idx_mutex);
3630
3631 gfx_v7_0_update_rlc(adev, tmp);
3632
e3b04bc7 3633 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
a2e73f56
AD		 3634 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3635 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3636 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3637 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3638 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
e3b04bc7
AD		 3639 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3640 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
a2e73f56
AD		 3641 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3642 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3643 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3644 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3645 if (orig != data)
3646 WREG32(mmCGTS_SM_CTRL_REG, data);
3647 }
3648 } else {
3649 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3650 data |= 0x00000003;
3651 if (orig != data)
3652 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3653
3654 data = RREG32(mmRLC_MEM_SLP_CNTL);
3655 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3656 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3657 WREG32(mmRLC_MEM_SLP_CNTL, data);
3658 }
3659
3660 data = RREG32(mmCP_MEM_SLP_CNTL);
3661 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3662 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3663 WREG32(mmCP_MEM_SLP_CNTL, data);
3664 }
3665
3666 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3667 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3668 if (orig != data)
3669 WREG32(mmCGTS_SM_CTRL_REG, data);
3670
3671 tmp = gfx_v7_0_halt_rlc(adev);
3672
3673 mutex_lock(&adev->grbm_idx_mutex);
3674 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3675 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3676 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3677 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3678 WREG32(mmRLC_SERDES_WR_CTRL, data);
3679 mutex_unlock(&adev->grbm_idx_mutex);
3680
3681 gfx_v7_0_update_rlc(adev, tmp);
3682 }
3683}
3684
3685static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3686 bool enable)
3687{
3688 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3689 /* order matters! */
3690 if (enable) {
3691 gfx_v7_0_enable_mgcg(adev, true);
3692 gfx_v7_0_enable_cgcg(adev, true);
3693 } else {
3694 gfx_v7_0_enable_cgcg(adev, false);
3695 gfx_v7_0_enable_mgcg(adev, false);
3696 }
3697 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3698}
3699
3700static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3701 bool enable)
3702{
3703 u32 data, orig;
3704
3705 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3706 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
a2e73f56
AD		 3707 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3708 else
3709 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3710 if (orig != data)
3711 WREG32(mmRLC_PG_CNTL, data);
3712}
3713
3714static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3715 bool enable)
3716{
3717 u32 data, orig;
3718
3719 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3720 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
a2e73f56
AD		 3721 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3722 else
3723 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3724 if (orig != data)
3725 WREG32(mmRLC_PG_CNTL, data);
3726}
3727
3728static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3729{
3730 u32 data, orig;
3731
3732 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3733 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
a2e73f56
AD		 3734 data &= ~0x8000;
3735 else
3736 data |= 0x8000;
3737 if (orig != data)
3738 WREG32(mmRLC_PG_CNTL, data);
3739}
3740
3741static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3742{
3743 u32 data, orig;
3744
3745 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3746 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
a2e73f56
AD		 3747 data &= ~0x2000;
3748 else
3749 data |= 0x2000;
3750 if (orig != data)
3751 WREG32(mmRLC_PG_CNTL, data);
3752}
3753
3754static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3755{
3756 const __le32 *fw_data;
3757 volatile u32 *dst_ptr;
3758 int me, i, max_me = 4;
3759 u32 bo_offset = 0;
3760 u32 table_offset, table_size;
3761
3762 if (adev->asic_type == CHIP_KAVERI)
3763 max_me = 5;
3764
3765 if (adev->gfx.rlc.cp_table_ptr == NULL)
3766 return;
3767
3768 /* write the cp table buffer */
3769 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3770 for (me = 0; me < max_me; me++) {
3771 if (me == 0) {
3772 const struct gfx_firmware_header_v1_0 *hdr =
3773 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3774 fw_data = (const __le32 *)
3775 (adev->gfx.ce_fw->data +
3776 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3777 table_offset = le32_to_cpu(hdr->jt_offset);
3778 table_size = le32_to_cpu(hdr->jt_size);
3779 } else if (me == 1) {
3780 const struct gfx_firmware_header_v1_0 *hdr =
3781 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3782 fw_data = (const __le32 *)
3783 (adev->gfx.pfp_fw->data +
3784 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3785 table_offset = le32_to_cpu(hdr->jt_offset);
3786 table_size = le32_to_cpu(hdr->jt_size);
3787 } else if (me == 2) {
3788 const struct gfx_firmware_header_v1_0 *hdr =
3789 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3790 fw_data = (const __le32 *)
3791 (adev->gfx.me_fw->data +
3792 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3793 table_offset = le32_to_cpu(hdr->jt_offset);
3794 table_size = le32_to_cpu(hdr->jt_size);
3795 } else if (me == 3) {
3796 const struct gfx_firmware_header_v1_0 *hdr =
3797 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3798 fw_data = (const __le32 *)
3799 (adev->gfx.mec_fw->data +
3800 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3801 table_offset = le32_to_cpu(hdr->jt_offset);
3802 table_size = le32_to_cpu(hdr->jt_size);
3803 } else {
3804 const struct gfx_firmware_header_v1_0 *hdr =
3805 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3806 fw_data = (const __le32 *)
3807 (adev->gfx.mec2_fw->data +
3808 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3809 table_offset = le32_to_cpu(hdr->jt_offset);
3810 table_size = le32_to_cpu(hdr->jt_size);
3811 }
3812
3813 for (i = 0; i < table_size; i ++) {
3814 dst_ptr[bo_offset + i] =
3815 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3816 }
3817
3818 bo_offset += table_size;
3819 }
3820}
3821
3822static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3823 bool enable)
3824{
3825 u32 data, orig;
3826
e3b04bc7 3827 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
a2e73f56
AD		 3828 orig = data = RREG32(mmRLC_PG_CNTL);
3829 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3830 if (orig != data)
3831 WREG32(mmRLC_PG_CNTL, data);
3832
3833 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3834 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3835 if (orig != data)
3836 WREG32(mmRLC_AUTO_PG_CTRL, data);
3837 } else {
3838 orig = data = RREG32(mmRLC_PG_CNTL);
3839 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3840 if (orig != data)
3841 WREG32(mmRLC_PG_CNTL, data);
3842
3843 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3844 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3845 if (orig != data)
3846 WREG32(mmRLC_AUTO_PG_CTRL, data);
3847
3848 data = RREG32(mmDB_RENDER_CONTROL);
3849 }
3850}
3851
8f8e00c1 3852static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
a2e73f56 3853{
8f8e00c1 3854 u32 data, mask;
a2e73f56 3855
8f8e00c1
AD		 3856 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3857 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
a2e73f56 3858
8f8e00c1
AD		 3859 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3860 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
a2e73f56 3861
6157bd7a 3862 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
a2e73f56 3863
8f8e00c1 3864 return (~data) & mask;
a2e73f56
AD		 3865}
3866
3867static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3868{
7dae69a2 3869 u32 tmp;
a2e73f56 3870
7dae69a2 3871 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
a2e73f56
AD		 3872
3873 tmp = RREG32(mmRLC_MAX_PG_CU);
3874 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
7dae69a2 3875 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
a2e73f56
AD		 3876 WREG32(mmRLC_MAX_PG_CU, tmp);
3877}
3878
3879static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3880 bool enable)
3881{
3882 u32 data, orig;
3883
3884 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3885 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
a2e73f56
AD		 3886 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3887 else
3888 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3889 if (orig != data)
3890 WREG32(mmRLC_PG_CNTL, data);
3891}
3892
3893static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3894 bool enable)
3895{
3896 u32 data, orig;
3897
3898 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3899 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
a2e73f56
AD		 3900 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3901 else
3902 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3903 if (orig != data)
3904 WREG32(mmRLC_PG_CNTL, data);
3905}
3906
3907#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3908#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
3909
3910static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3911{
3912 u32 data, orig;
3913 u32 i;
3914
3915 if (adev->gfx.rlc.cs_data) {
3916 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3917 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3918 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3919 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3920 } else {
3921 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3922 for (i = 0; i < 3; i++)
3923 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3924 }
3925 if (adev->gfx.rlc.reg_list) {
3926 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3927 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3928 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3929 }
3930
3931 orig = data = RREG32(mmRLC_PG_CNTL);
3932 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3933 if (orig != data)
3934 WREG32(mmRLC_PG_CNTL, data);
3935
3936 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3937 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3938
3939 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3940 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3941 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3942 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3943
3944 data = 0x10101010;
3945 WREG32(mmRLC_PG_DELAY, data);
3946
3947 data = RREG32(mmRLC_PG_DELAY_2);
3948 data &= ~0xff;
3949 data |= 0x3;
3950 WREG32(mmRLC_PG_DELAY_2, data);
3951
3952 data = RREG32(mmRLC_AUTO_PG_CTRL);
3953 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3954 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3955 WREG32(mmRLC_AUTO_PG_CTRL, data);
3956
3957}
3958
3959static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3960{
3961 gfx_v7_0_enable_gfx_cgpg(adev, enable);
3962 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3963 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3964}
3965
3966static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3967{
3968 u32 count = 0;
3969 const struct cs_section_def *sect = NULL;
3970 const struct cs_extent_def *ext = NULL;
3971
3972 if (adev->gfx.rlc.cs_data == NULL)
3973 return 0;
3974
3975 /* begin clear state */
3976 count += 2;
3977 /* context control state */
3978 count += 3;
3979
3980 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3981 for (ext = sect->section; ext->extent != NULL; ++ext) {
3982 if (sect->id == SECT_CONTEXT)
3983 count += 2 + ext->reg_count;
3984 else
3985 return 0;
3986 }
3987 }
3988 /* pa_sc_raster_config/pa_sc_raster_config1 */
3989 count += 4;
3990 /* end clear state */
3991 count += 2;
3992 /* clear state */
3993 count += 2;
3994
3995 return count;
3996}
3997
3998static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
3999 volatile u32 *buffer)
4000{
4001 u32 count = 0, i;
4002 const struct cs_section_def *sect = NULL;
4003 const struct cs_extent_def *ext = NULL;
4004
4005 if (adev->gfx.rlc.cs_data == NULL)
4006 return;
4007 if (buffer == NULL)
4008 return;
4009
4010 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4011 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4012
4013 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4014 buffer[count++] = cpu_to_le32(0x80000000);
4015 buffer[count++] = cpu_to_le32(0x80000000);
4016
4017 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4018 for (ext = sect->section; ext->extent != NULL; ++ext) {
4019 if (sect->id == SECT_CONTEXT) {
4020 buffer[count++] =
4021 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4022 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4023 for (i = 0; i < ext->reg_count; i++)
4024 buffer[count++] = cpu_to_le32(ext->extent[i]);
4025 } else {
4026 return;
4027 }
4028 }
4029 }
4030
4031 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4032 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4033 switch (adev->asic_type) {
4034 case CHIP_BONAIRE:
4035 buffer[count++] = cpu_to_le32(0x16000012);
4036 buffer[count++] = cpu_to_le32(0x00000000);
4037 break;
4038 case CHIP_KAVERI:
4039 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4040 buffer[count++] = cpu_to_le32(0x00000000);
4041 break;
4042 case CHIP_KABINI:
4043 case CHIP_MULLINS:
4044 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4045 buffer[count++] = cpu_to_le32(0x00000000);
4046 break;
4047 case CHIP_HAWAII:
4048 buffer[count++] = cpu_to_le32(0x3a00161a);
4049 buffer[count++] = cpu_to_le32(0x0000002e);
4050 break;
4051 default:
4052 buffer[count++] = cpu_to_le32(0x00000000);
4053 buffer[count++] = cpu_to_le32(0x00000000);
4054 break;
4055 }
4056
4057 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4058 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4059
4060 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4061 buffer[count++] = cpu_to_le32(0);
4062}
4063
4064static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4065{
e3b04bc7
AD		 4066 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4067 AMD_PG_SUPPORT_GFX_SMG |
4068 AMD_PG_SUPPORT_GFX_DMG |
4069 AMD_PG_SUPPORT_CP |
4070 AMD_PG_SUPPORT_GDS |
4071 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56
AD		 4072 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4073 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
e3b04bc7 4074 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4075 gfx_v7_0_init_gfx_cgpg(adev);
4076 gfx_v7_0_enable_cp_pg(adev, true);
4077 gfx_v7_0_enable_gds_pg(adev, true);
4078 }
4079 gfx_v7_0_init_ao_cu_mask(adev);
4080 gfx_v7_0_update_gfx_pg(adev, true);
4081 }
4082}
4083
4084static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4085{
e3b04bc7
AD		 4086 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4087 AMD_PG_SUPPORT_GFX_SMG |
4088 AMD_PG_SUPPORT_GFX_DMG |
4089 AMD_PG_SUPPORT_CP |
4090 AMD_PG_SUPPORT_GDS |
4091 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56 4092 gfx_v7_0_update_gfx_pg(adev, false);
e3b04bc7 4093 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4094 gfx_v7_0_enable_cp_pg(adev, false);
4095 gfx_v7_0_enable_gds_pg(adev, false);
4096 }
4097 }
4098}
4099
4100/**
4101 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4102 *
4103 * @adev: amdgpu_device pointer
4104 *
4105 * Fetches a GPU clock counter snapshot (SI).
4106 * Returns the 64 bit clock counter snapshot.
4107 */
4108uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4109{
4110 uint64_t clock;
4111
4112 mutex_lock(&adev->gfx.gpu_clock_mutex);
4113 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4114 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4115 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4116 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4117 return clock;
4118}
4119
4120static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4121 uint32_t vmid,
4122 uint32_t gds_base, uint32_t gds_size,
4123 uint32_t gws_base, uint32_t gws_size,
4124 uint32_t oa_base, uint32_t oa_size)
4125{
4126 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4127 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4128
4129 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4130 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4131
4132 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4133 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4134
4135 /* GDS Base */
4136 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4137 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4138 WRITE_DATA_DST_SEL(0)));
4139 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4140 amdgpu_ring_write(ring, 0);
4141 amdgpu_ring_write(ring, gds_base);
4142
4143 /* GDS Size */
4144 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4145 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4146 WRITE_DATA_DST_SEL(0)));
4147 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4148 amdgpu_ring_write(ring, 0);
4149 amdgpu_ring_write(ring, gds_size);
4150
4151 /* GWS */
4152 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4153 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4154 WRITE_DATA_DST_SEL(0)));
4155 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4156 amdgpu_ring_write(ring, 0);
4157 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4158
4159 /* OA */
4160 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4161 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4162 WRITE_DATA_DST_SEL(0)));
4163 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4164 amdgpu_ring_write(ring, 0);
4165 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4166}
4167
5fc3aeeb 4168static int gfx_v7_0_early_init(void *handle)
a2e73f56 4169{
5fc3aeeb 4170 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4171
4172 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4173 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4174 gfx_v7_0_set_ring_funcs(adev);
4175 gfx_v7_0_set_irq_funcs(adev);
4176 gfx_v7_0_set_gds_init(adev);
4177
4178 return 0;
4179}
4180
ef720532
AD		 4181static int gfx_v7_0_late_init(void *handle)
4182{
4183 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4184 int r;
4185
4186 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4187 if (r)
4188 return r;
4189
4190 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4191 if (r)
4192 return r;
4193
4194 return 0;
4195}
4196
d93f3ca7
AD		 4197static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4198{
4199 u32 gb_addr_config;
4200 u32 mc_shared_chmap, mc_arb_ramcfg;
4201 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4202 u32 tmp;
4203
4204 switch (adev->asic_type) {
4205 case CHIP_BONAIRE:
4206 adev->gfx.config.max_shader_engines = 2;
4207 adev->gfx.config.max_tile_pipes = 4;
4208 adev->gfx.config.max_cu_per_sh = 7;
4209 adev->gfx.config.max_sh_per_se = 1;
4210 adev->gfx.config.max_backends_per_se = 2;
4211 adev->gfx.config.max_texture_channel_caches = 4;
4212 adev->gfx.config.max_gprs = 256;
4213 adev->gfx.config.max_gs_threads = 32;
4214 adev->gfx.config.max_hw_contexts = 8;
4215
4216 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4217 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4218 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4219 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4220 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4221 break;
4222 case CHIP_HAWAII:
4223 adev->gfx.config.max_shader_engines = 4;
4224 adev->gfx.config.max_tile_pipes = 16;
4225 adev->gfx.config.max_cu_per_sh = 11;
4226 adev->gfx.config.max_sh_per_se = 1;
4227 adev->gfx.config.max_backends_per_se = 4;
4228 adev->gfx.config.max_texture_channel_caches = 16;
4229 adev->gfx.config.max_gprs = 256;
4230 adev->gfx.config.max_gs_threads = 32;
4231 adev->gfx.config.max_hw_contexts = 8;
4232
4233 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4234 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4235 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4236 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4237 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4238 break;
4239 case CHIP_KAVERI:
4240 adev->gfx.config.max_shader_engines = 1;
4241 adev->gfx.config.max_tile_pipes = 4;
4242 if ((adev->pdev->device == 0x1304) ||
4243 (adev->pdev->device == 0x1305) ||
4244 (adev->pdev->device == 0x130C) ||
4245 (adev->pdev->device == 0x130F) ||
4246 (adev->pdev->device == 0x1310) ||
4247 (adev->pdev->device == 0x1311) ||
4248 (adev->pdev->device == 0x131C)) {
4249 adev->gfx.config.max_cu_per_sh = 8;
4250 adev->gfx.config.max_backends_per_se = 2;
4251 } else if ((adev->pdev->device == 0x1309) ||
4252 (adev->pdev->device == 0x130A) ||
4253 (adev->pdev->device == 0x130D) ||
4254 (adev->pdev->device == 0x1313) ||
4255 (adev->pdev->device == 0x131D)) {
4256 adev->gfx.config.max_cu_per_sh = 6;
4257 adev->gfx.config.max_backends_per_se = 2;
4258 } else if ((adev->pdev->device == 0x1306) ||
4259 (adev->pdev->device == 0x1307) ||
4260 (adev->pdev->device == 0x130B) ||
4261 (adev->pdev->device == 0x130E) ||
4262 (adev->pdev->device == 0x1315) ||
4263 (adev->pdev->device == 0x131B)) {
4264 adev->gfx.config.max_cu_per_sh = 4;
4265 adev->gfx.config.max_backends_per_se = 1;
4266 } else {
4267 adev->gfx.config.max_cu_per_sh = 3;
4268 adev->gfx.config.max_backends_per_se = 1;
4269 }
4270 adev->gfx.config.max_sh_per_se = 1;
4271 adev->gfx.config.max_texture_channel_caches = 4;
4272 adev->gfx.config.max_gprs = 256;
4273 adev->gfx.config.max_gs_threads = 16;
4274 adev->gfx.config.max_hw_contexts = 8;
4275
4276 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4277 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4278 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4279 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4280 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4281 break;
4282 case CHIP_KABINI:
4283 case CHIP_MULLINS:
4284 default:
4285 adev->gfx.config.max_shader_engines = 1;
4286 adev->gfx.config.max_tile_pipes = 2;
4287 adev->gfx.config.max_cu_per_sh = 2;
4288 adev->gfx.config.max_sh_per_se = 1;
4289 adev->gfx.config.max_backends_per_se = 1;
4290 adev->gfx.config.max_texture_channel_caches = 2;
4291 adev->gfx.config.max_gprs = 256;
4292 adev->gfx.config.max_gs_threads = 16;
4293 adev->gfx.config.max_hw_contexts = 8;
4294
4295 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4296 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4297 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4298 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4299 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4300 break;
4301 }
4302
4303 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4304 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4305 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4306
4307 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4308 adev->gfx.config.mem_max_burst_length_bytes = 256;
4309 if (adev->flags & AMD_IS_APU) {
4310 /* Get memory bank mapping mode. */
4311 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4312 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4313 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4314
4315 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4316 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4317 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4318
4319 /* Validate settings in case only one DIMM installed. */
4320 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4321 dimm00_addr_map = 0;
4322 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4323 dimm01_addr_map = 0;
4324 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4325 dimm10_addr_map = 0;
4326 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4327 dimm11_addr_map = 0;
4328
4329 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4330 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4331 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4332 adev->gfx.config.mem_row_size_in_kb = 2;
4333 else
4334 adev->gfx.config.mem_row_size_in_kb = 1;
4335 } else {
4336 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4337 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4338 if (adev->gfx.config.mem_row_size_in_kb > 4)
4339 adev->gfx.config.mem_row_size_in_kb = 4;
4340 }
4341 /* XXX use MC settings? */
4342 adev->gfx.config.shader_engine_tile_size = 32;
4343 adev->gfx.config.num_gpus = 1;
4344 adev->gfx.config.multi_gpu_tile_size = 64;
4345
4346 /* fix up row size */
4347 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4348 switch (adev->gfx.config.mem_row_size_in_kb) {
4349 case 1:
4350 default:
4351 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4352 break;
4353 case 2:
4354 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4355 break;
4356 case 4:
4357 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4358 break;
4359 }
4360 adev->gfx.config.gb_addr_config = gb_addr_config;
4361}
4362
5fc3aeeb 4363static int gfx_v7_0_sw_init(void *handle)
a2e73f56
AD		 4364{
4365 struct amdgpu_ring *ring;
5fc3aeeb 4366 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4367 int i, r;
4368
4369 /* EOP Event */
4370 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4371 if (r)
4372 return r;
4373
4374 /* Privileged reg */
4375 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4376 if (r)
4377 return r;
4378
4379 /* Privileged inst */
4380 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4381 if (r)
4382 return r;
4383
4384 gfx_v7_0_scratch_init(adev);
4385
4386 r = gfx_v7_0_init_microcode(adev);
4387 if (r) {
4388 DRM_ERROR("Failed to load gfx firmware!\n");
4389 return r;
4390 }
4391
4392 r = gfx_v7_0_rlc_init(adev);
4393 if (r) {
4394 DRM_ERROR("Failed to init rlc BOs!\n");
4395 return r;
4396 }
4397
4398 /* allocate mec buffers */
4399 r = gfx_v7_0_mec_init(adev);
4400 if (r) {
4401 DRM_ERROR("Failed to init MEC BOs!\n");
4402 return r;
4403 }
4404
a2e73f56
AD		 4405 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4406 ring = &adev->gfx.gfx_ring[i];
4407 ring->ring_obj = NULL;
4408 sprintf(ring->name, "gfx");
2800de2e 4409 r = amdgpu_ring_init(adev, ring, 1024,
a2e73f56
AD		 4410 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4411 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4412 AMDGPU_RING_TYPE_GFX);
4413 if (r)
4414 return r;
4415 }
4416
4417 /* set up the compute queues */
4418 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4419 unsigned irq_type;
4420
4421 /* max 32 queues per MEC */
4422 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4423 DRM_ERROR("Too many (%d) compute rings!\n", i);
4424 break;
4425 }
4426 ring = &adev->gfx.compute_ring[i];
4427 ring->ring_obj = NULL;
4428 ring->use_doorbell = true;
4429 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4430 ring->me = 1; /* first MEC */
4431 ring->pipe = i / 8;
4432 ring->queue = i % 8;
771c8ec1 4433 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
a2e73f56
AD		 4434 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4435 /* type-2 packets are deprecated on MEC, use type-3 instead */
2800de2e 4436 r = amdgpu_ring_init(adev, ring, 1024,
a2e73f56
AD		 4437 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4438 &adev->gfx.eop_irq, irq_type,
4439 AMDGPU_RING_TYPE_COMPUTE);
4440 if (r)
4441 return r;
4442 }
4443
4444 /* reserve GDS, GWS and OA resource for gfx */
4445 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4446 PAGE_SIZE, true,
4447 AMDGPU_GEM_DOMAIN_GDS, 0,
72d7668b 4448 NULL, NULL, &adev->gds.gds_gfx_bo);
a2e73f56
AD		 4449 if (r)
4450 return r;
4451
4452 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4453 PAGE_SIZE, true,
4454 AMDGPU_GEM_DOMAIN_GWS, 0,
72d7668b 4455 NULL, NULL, &adev->gds.gws_gfx_bo);
a2e73f56
AD		 4456 if (r)
4457 return r;
4458
4459 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4460 PAGE_SIZE, true,
4461 AMDGPU_GEM_DOMAIN_OA, 0,
72d7668b 4462 NULL, NULL, &adev->gds.oa_gfx_bo);
a2e73f56
AD		 4463 if (r)
4464 return r;
4465
d93f3ca7
AD		 4466 adev->gfx.ce_ram_size = 0x8000;
4467
4468 gfx_v7_0_gpu_early_init(adev);
4469
a2e73f56
AD		 4470 return r;
4471}
4472
5fc3aeeb 4473static int gfx_v7_0_sw_fini(void *handle)
a2e73f56
AD		 4474{
4475 int i;
5fc3aeeb 4476 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4477
4478 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4479 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4480 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4481
4482 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4483 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4484 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4485 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4486
a2e73f56
AD		 4487 gfx_v7_0_cp_compute_fini(adev);
4488 gfx_v7_0_rlc_fini(adev);
4489 gfx_v7_0_mec_fini(adev);
4490
4491 return 0;
4492}
4493
5fc3aeeb 4494static int gfx_v7_0_hw_init(void *handle)
a2e73f56
AD		 4495{
4496 int r;
5fc3aeeb 4497 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4498
4499 gfx_v7_0_gpu_init(adev);
4500
4501 /* init rlc */
4502 r = gfx_v7_0_rlc_resume(adev);
4503 if (r)
4504 return r;
4505
4506 r = gfx_v7_0_cp_resume(adev);
4507 if (r)
4508 return r;
4509
4510 return r;
4511}
4512
5fc3aeeb 4513static int gfx_v7_0_hw_fini(void *handle)
a2e73f56 4514{
5fc3aeeb 4515 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4516
ef720532
AD		 4517 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4518 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
a2e73f56
AD		 4519 gfx_v7_0_cp_enable(adev, false);
4520 gfx_v7_0_rlc_stop(adev);
4521 gfx_v7_0_fini_pg(adev);
4522
4523 return 0;
4524}
4525
5fc3aeeb 4526static int gfx_v7_0_suspend(void *handle)
a2e73f56 4527{
5fc3aeeb 4528 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4529
a2e73f56
AD		 4530 return gfx_v7_0_hw_fini(adev);
4531}
4532
5fc3aeeb 4533static int gfx_v7_0_resume(void *handle)
a2e73f56 4534{
5fc3aeeb 4535 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4536
a2e73f56
AD		 4537 return gfx_v7_0_hw_init(adev);
4538}
4539
5fc3aeeb 4540static bool gfx_v7_0_is_idle(void *handle)
a2e73f56 4541{
5fc3aeeb 4542 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4543
a2e73f56
AD		 4544 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4545 return false;
4546 else
4547 return true;
4548}
4549
5fc3aeeb 4550static int gfx_v7_0_wait_for_idle(void *handle)
a2e73f56
AD		 4551{
4552 unsigned i;
4553 u32 tmp;
5fc3aeeb 4554 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4555
4556 for (i = 0; i < adev->usec_timeout; i++) {
4557 /* read MC_STATUS */
4558 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4559
4560 if (!tmp)
4561 return 0;
4562 udelay(1);
4563 }
4564 return -ETIMEDOUT;
4565}
4566
5fc3aeeb 4567static int gfx_v7_0_soft_reset(void *handle)
a2e73f56
AD		 4568{
4569 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4570 u32 tmp;
5fc3aeeb 4571 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4572
4573 /* GRBM_STATUS */
4574 tmp = RREG32(mmGRBM_STATUS);
4575 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4576 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4577 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4578 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4579 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4580 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4581 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4582 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4583
4584 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4585 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4586 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4587 }
4588
4589 /* GRBM_STATUS2 */
4590 tmp = RREG32(mmGRBM_STATUS2);
4591 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4592 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4593
4594 /* SRBM_STATUS */
4595 tmp = RREG32(mmSRBM_STATUS);
4596 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4597 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4598
4599 if (grbm_soft_reset || srbm_soft_reset) {
a2e73f56
AD		 4600 /* disable CG/PG */
4601 gfx_v7_0_fini_pg(adev);
4602 gfx_v7_0_update_cg(adev, false);
4603
4604 /* stop the rlc */
4605 gfx_v7_0_rlc_stop(adev);
4606
4607 /* Disable GFX parsing/prefetching */
4608 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4609
4610 /* Disable MEC parsing/prefetching */
4611 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4612
4613 if (grbm_soft_reset) {
4614 tmp = RREG32(mmGRBM_SOFT_RESET);
4615 tmp |= grbm_soft_reset;
4616 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4617 WREG32(mmGRBM_SOFT_RESET, tmp);
4618 tmp = RREG32(mmGRBM_SOFT_RESET);
4619
4620 udelay(50);
4621
4622 tmp &= ~grbm_soft_reset;
4623 WREG32(mmGRBM_SOFT_RESET, tmp);
4624 tmp = RREG32(mmGRBM_SOFT_RESET);
4625 }
4626
4627 if (srbm_soft_reset) {
4628 tmp = RREG32(mmSRBM_SOFT_RESET);
4629 tmp |= srbm_soft_reset;
4630 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4631 WREG32(mmSRBM_SOFT_RESET, tmp);
4632 tmp = RREG32(mmSRBM_SOFT_RESET);
4633
4634 udelay(50);
4635
4636 tmp &= ~srbm_soft_reset;
4637 WREG32(mmSRBM_SOFT_RESET, tmp);
4638 tmp = RREG32(mmSRBM_SOFT_RESET);
4639 }
4640 /* Wait a little for things to settle down */
4641 udelay(50);
a2e73f56
AD		 4642 }
4643 return 0;
4644}
4645
4646static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4647 enum amdgpu_interrupt_state state)
4648{
4649 u32 cp_int_cntl;
4650
4651 switch (state) {
4652 case AMDGPU_IRQ_STATE_DISABLE:
4653 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4654 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4655 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4656 break;
4657 case AMDGPU_IRQ_STATE_ENABLE:
4658 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4659 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4660 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4661 break;
4662 default:
4663 break;
4664 }
4665}
4666
4667static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4668 int me, int pipe,
4669 enum amdgpu_interrupt_state state)
4670{
4671 u32 mec_int_cntl, mec_int_cntl_reg;
4672
4673 /*
4674 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4675 * handles the setting of interrupts for this specific pipe. All other
4676 * pipes' interrupts are set by amdkfd.
4677 */
4678
4679 if (me == 1) {
4680 switch (pipe) {
4681 case 0:
4682 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4683 break;
4684 default:
4685 DRM_DEBUG("invalid pipe %d\n", pipe);
4686 return;
4687 }
4688 } else {
4689 DRM_DEBUG("invalid me %d\n", me);
4690 return;
4691 }
4692
4693 switch (state) {
4694 case AMDGPU_IRQ_STATE_DISABLE:
4695 mec_int_cntl = RREG32(mec_int_cntl_reg);
4696 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4697 WREG32(mec_int_cntl_reg, mec_int_cntl);
4698 break;
4699 case AMDGPU_IRQ_STATE_ENABLE:
4700 mec_int_cntl = RREG32(mec_int_cntl_reg);
4701 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4702 WREG32(mec_int_cntl_reg, mec_int_cntl);
4703 break;
4704 default:
4705 break;
4706 }
4707}
4708
4709static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4710 struct amdgpu_irq_src *src,
4711 unsigned type,
4712 enum amdgpu_interrupt_state state)
4713{
4714 u32 cp_int_cntl;
4715
4716 switch (state) {
4717 case AMDGPU_IRQ_STATE_DISABLE:
4718 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4719 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4720 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4721 break;
4722 case AMDGPU_IRQ_STATE_ENABLE:
4723 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4724 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4725 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4726 break;
4727 default:
4728 break;
4729 }
4730
4731 return 0;
4732}
4733
4734static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4735 struct amdgpu_irq_src *src,
4736 unsigned type,
4737 enum amdgpu_interrupt_state state)
4738{
4739 u32 cp_int_cntl;
4740
4741 switch (state) {
4742 case AMDGPU_IRQ_STATE_DISABLE:
4743 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4744 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4745 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4746 break;
4747 case AMDGPU_IRQ_STATE_ENABLE:
4748 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4749 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4750 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4751 break;
4752 default:
4753 break;
4754 }
4755
4756 return 0;
4757}
4758
4759static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4760 struct amdgpu_irq_src *src,
4761 unsigned type,
4762 enum amdgpu_interrupt_state state)
4763{
4764 switch (type) {
4765 case AMDGPU_CP_IRQ_GFX_EOP:
4766 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4767 break;
4768 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4769 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4770 break;
4771 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4772 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4773 break;
4774 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4775 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4776 break;
4777 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4778 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4779 break;
4780 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4781 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4782 break;
4783 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4784 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4785 break;
4786 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4787 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4788 break;
4789 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4790 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4791 break;
4792 default:
4793 break;
4794 }
4795 return 0;
4796}
4797
4798static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4799 struct amdgpu_irq_src *source,
4800 struct amdgpu_iv_entry *entry)
4801{
4802 u8 me_id, pipe_id;
4803 struct amdgpu_ring *ring;
4804 int i;
4805
4806 DRM_DEBUG("IH: CP EOP\n");
4807 me_id = (entry->ring_id & 0x0c) >> 2;
4808 pipe_id = (entry->ring_id & 0x03) >> 0;
4809 switch (me_id) {
4810 case 0:
4811 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4812 break;
4813 case 1:
4814 case 2:
4815 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4816 ring = &adev->gfx.compute_ring[i];
4817 if ((ring->me == me_id) & (ring->pipe == pipe_id))
4818 amdgpu_fence_process(ring);
4819 }
4820 break;
4821 }
4822 return 0;
4823}
4824
4825static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4826 struct amdgpu_irq_src *source,
4827 struct amdgpu_iv_entry *entry)
4828{
4829 DRM_ERROR("Illegal register access in command stream\n");
4830 schedule_work(&adev->reset_work);
4831 return 0;
4832}
4833
4834static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4835 struct amdgpu_irq_src *source,
4836 struct amdgpu_iv_entry *entry)
4837{
4838 DRM_ERROR("Illegal instruction in command stream\n");
4839 // XXX soft reset the gfx block only
4840 schedule_work(&adev->reset_work);
4841 return 0;
4842}
4843
5fc3aeeb 4844static int gfx_v7_0_set_clockgating_state(void *handle,
4845 enum amd_clockgating_state state)
a2e73f56
AD		 4846{
4847 bool gate = false;
5fc3aeeb 4848 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 4849
5fc3aeeb 4850 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 4851 gate = true;
4852
4853 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4854 /* order matters! */
4855 if (gate) {
4856 gfx_v7_0_enable_mgcg(adev, true);
4857 gfx_v7_0_enable_cgcg(adev, true);
4858 } else {
4859 gfx_v7_0_enable_cgcg(adev, false);
4860 gfx_v7_0_enable_mgcg(adev, false);
4861 }
4862 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4863
4864 return 0;
4865}
4866
5fc3aeeb 4867static int gfx_v7_0_set_powergating_state(void *handle,
4868 enum amd_powergating_state state)
a2e73f56
AD		 4869{
4870 bool gate = false;
5fc3aeeb 4871 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 4872
5fc3aeeb 4873 if (state == AMD_PG_STATE_GATE)
a2e73f56
AD		 4874 gate = true;
4875
e3b04bc7
AD		 4876 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4877 AMD_PG_SUPPORT_GFX_SMG |
4878 AMD_PG_SUPPORT_GFX_DMG |
4879 AMD_PG_SUPPORT_CP |
4880 AMD_PG_SUPPORT_GDS |
4881 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56 4882 gfx_v7_0_update_gfx_pg(adev, gate);
e3b04bc7 4883 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4884 gfx_v7_0_enable_cp_pg(adev, gate);
4885 gfx_v7_0_enable_gds_pg(adev, gate);
4886 }
4887 }
4888
4889 return 0;
4890}
4891
5fc3aeeb 4892const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
88a907d6 4893 .name = "gfx_v7_0",
a2e73f56 4894 .early_init = gfx_v7_0_early_init,
ef720532 4895 .late_init = gfx_v7_0_late_init,
a2e73f56
AD		 4896 .sw_init = gfx_v7_0_sw_init,
4897 .sw_fini = gfx_v7_0_sw_fini,
4898 .hw_init = gfx_v7_0_hw_init,
4899 .hw_fini = gfx_v7_0_hw_fini,
4900 .suspend = gfx_v7_0_suspend,
4901 .resume = gfx_v7_0_resume,
4902 .is_idle = gfx_v7_0_is_idle,
4903 .wait_for_idle = gfx_v7_0_wait_for_idle,
4904 .soft_reset = gfx_v7_0_soft_reset,
a2e73f56
AD		 4905 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
4906 .set_powergating_state = gfx_v7_0_set_powergating_state,
4907};
4908
a2e73f56
AD		 4909static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
4910 .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
4911 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
4912 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
4913 .parse_cs = NULL,
93323131 4914 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
a2e73f56 4915 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
b8c7b39e 4916 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
a2e73f56
AD		 4917 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4918 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d2edb07b 4919 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
0955860b 4920 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
a2e73f56
AD		 4921 .test_ring = gfx_v7_0_ring_test_ring,
4922 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 4923 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 4924 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 4925};
4926
4927static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
4928 .get_rptr = gfx_v7_0_ring_get_rptr_compute,
4929 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
4930 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
4931 .parse_cs = NULL,
93323131 4932 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
a2e73f56 4933 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
b8c7b39e 4934 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
a2e73f56
AD		 4935 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4936 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d9b5327a 4937 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
0955860b 4938 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
a2e73f56
AD		 4939 .test_ring = gfx_v7_0_ring_test_ring,
4940 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 4941 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 4942 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 4943};
4944
4945static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
4946{
4947 int i;
4948
4949 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4950 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
4951 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4952 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
4953}
4954
4955static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
4956 .set = gfx_v7_0_set_eop_interrupt_state,
4957 .process = gfx_v7_0_eop_irq,
4958};
4959
4960static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
4961 .set = gfx_v7_0_set_priv_reg_fault_state,
4962 .process = gfx_v7_0_priv_reg_irq,
4963};
4964
4965static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
4966 .set = gfx_v7_0_set_priv_inst_fault_state,
4967 .process = gfx_v7_0_priv_inst_irq,
4968};
4969
4970static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
4971{
4972 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4973 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
4974
4975 adev->gfx.priv_reg_irq.num_types = 1;
4976 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
4977
4978 adev->gfx.priv_inst_irq.num_types = 1;
4979 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
4980}
4981
4982static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
4983{
4984 /* init asci gds info */
4985 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4986 adev->gds.gws.total_size = 64;
4987 adev->gds.oa.total_size = 16;
4988
4989 if (adev->gds.mem.total_size == 64 * 1024) {
4990 adev->gds.mem.gfx_partition_size = 4096;
4991 adev->gds.mem.cs_partition_size = 4096;
4992
4993 adev->gds.gws.gfx_partition_size = 4;
4994 adev->gds.gws.cs_partition_size = 4;
4995
4996 adev->gds.oa.gfx_partition_size = 4;
4997 adev->gds.oa.cs_partition_size = 1;
4998 } else {
4999 adev->gds.mem.gfx_partition_size = 1024;
5000 adev->gds.mem.cs_partition_size = 1024;
5001
5002 adev->gds.gws.gfx_partition_size = 16;
5003 adev->gds.gws.cs_partition_size = 16;
5004
5005 adev->gds.oa.gfx_partition_size = 4;
5006 adev->gds.oa.cs_partition_size = 4;
5007 }
5008}
5009
5010
7dae69a2 5011static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
a2e73f56
AD		 5012{
5013 int i, j, k, counter, active_cu_number = 0;
5014 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7dae69a2 5015 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
a2e73f56 5016
6157bd7a
FC		 5017 memset(cu_info, 0, sizeof(*cu_info));
5018
a2e73f56
AD		 5019 mutex_lock(&adev->grbm_idx_mutex);
5020 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5021 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5022 mask = 1;
5023 ao_bitmap = 0;
5024 counter = 0;
8f8e00c1
AD		 5025 gfx_v7_0_select_se_sh(adev, i, j);
5026 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
a2e73f56
AD		 5027 cu_info->bitmap[i][j] = bitmap;
5028
8f8e00c1 5029 for (k = 0; k < 16; k ++) {
a2e73f56
AD		 5030 if (bitmap & mask) {
5031 if (counter < 2)
5032 ao_bitmap |= mask;
5033 counter ++;
5034 }
5035 mask <<= 1;
5036 }
5037 active_cu_number += counter;
5038 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5039 }
5040 }
8f8e00c1
AD		 5041 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5042 mutex_unlock(&adev->grbm_idx_mutex);
a2e73f56
AD		 5043
5044 cu_info->number = active_cu_number;
5045 cu_info->ao_cu_mask = ao_cu_mask;
a2e73f56 5046}
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