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drm/amdgpu: move ring from IBs into job
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c
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a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_ih.h"
27#include "amdgpu_gfx.h"
28#include "cikd.h"
29#include "cik.h"
30#include "atom.h"
31#include "amdgpu_ucode.h"
32#include "clearstate_ci.h"
33
34#include "uvd/uvd_4_2_d.h"
35
36#include "dce/dce_8_0_d.h"
37#include "dce/dce_8_0_sh_mask.h"
38
39#include "bif/bif_4_1_d.h"
40#include "bif/bif_4_1_sh_mask.h"
41
42#include "gca/gfx_7_0_d.h"
43#include "gca/gfx_7_2_enum.h"
44#include "gca/gfx_7_2_sh_mask.h"
45
46#include "gmc/gmc_7_0_d.h"
47#include "gmc/gmc_7_0_sh_mask.h"
48
49#include "oss/oss_2_0_d.h"
50#include "oss/oss_2_0_sh_mask.h"
51
52#define GFX7_NUM_GFX_RINGS 1
53#define GFX7_NUM_COMPUTE_RINGS 8
54
55static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
56static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
57static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
58int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *);
59
60MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
61MODULE_FIRMWARE("radeon/bonaire_me.bin");
62MODULE_FIRMWARE("radeon/bonaire_ce.bin");
63MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
64MODULE_FIRMWARE("radeon/bonaire_mec.bin");
65
66MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
67MODULE_FIRMWARE("radeon/hawaii_me.bin");
68MODULE_FIRMWARE("radeon/hawaii_ce.bin");
69MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
70MODULE_FIRMWARE("radeon/hawaii_mec.bin");
71
72MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
73MODULE_FIRMWARE("radeon/kaveri_me.bin");
74MODULE_FIRMWARE("radeon/kaveri_ce.bin");
75MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
76MODULE_FIRMWARE("radeon/kaveri_mec.bin");
77MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
78
79MODULE_FIRMWARE("radeon/kabini_pfp.bin");
80MODULE_FIRMWARE("radeon/kabini_me.bin");
81MODULE_FIRMWARE("radeon/kabini_ce.bin");
82MODULE_FIRMWARE("radeon/kabini_rlc.bin");
83MODULE_FIRMWARE("radeon/kabini_mec.bin");
84
85MODULE_FIRMWARE("radeon/mullins_pfp.bin");
86MODULE_FIRMWARE("radeon/mullins_me.bin");
87MODULE_FIRMWARE("radeon/mullins_ce.bin");
88MODULE_FIRMWARE("radeon/mullins_rlc.bin");
89MODULE_FIRMWARE("radeon/mullins_mec.bin");
90
91static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
92{
93 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
94 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
95 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
96 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
97 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
98 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
99 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
100 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
101 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
102 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
103 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
104 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
105 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
106 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
107 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
108 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
109};
110
111static const u32 spectre_rlc_save_restore_register_list[] =
112{
113 (0x0e00 << 16) | (0xc12c >> 2),
114 0x00000000,
115 (0x0e00 << 16) | (0xc140 >> 2),
116 0x00000000,
117 (0x0e00 << 16) | (0xc150 >> 2),
118 0x00000000,
119 (0x0e00 << 16) | (0xc15c >> 2),
120 0x00000000,
121 (0x0e00 << 16) | (0xc168 >> 2),
122 0x00000000,
123 (0x0e00 << 16) | (0xc170 >> 2),
124 0x00000000,
125 (0x0e00 << 16) | (0xc178 >> 2),
126 0x00000000,
127 (0x0e00 << 16) | (0xc204 >> 2),
128 0x00000000,
129 (0x0e00 << 16) | (0xc2b4 >> 2),
130 0x00000000,
131 (0x0e00 << 16) | (0xc2b8 >> 2),
132 0x00000000,
133 (0x0e00 << 16) | (0xc2bc >> 2),
134 0x00000000,
135 (0x0e00 << 16) | (0xc2c0 >> 2),
136 0x00000000,
137 (0x0e00 << 16) | (0x8228 >> 2),
138 0x00000000,
139 (0x0e00 << 16) | (0x829c >> 2),
140 0x00000000,
141 (0x0e00 << 16) | (0x869c >> 2),
142 0x00000000,
143 (0x0600 << 16) | (0x98f4 >> 2),
144 0x00000000,
145 (0x0e00 << 16) | (0x98f8 >> 2),
146 0x00000000,
147 (0x0e00 << 16) | (0x9900 >> 2),
148 0x00000000,
149 (0x0e00 << 16) | (0xc260 >> 2),
150 0x00000000,
151 (0x0e00 << 16) | (0x90e8 >> 2),
152 0x00000000,
153 (0x0e00 << 16) | (0x3c000 >> 2),
154 0x00000000,
155 (0x0e00 << 16) | (0x3c00c >> 2),
156 0x00000000,
157 (0x0e00 << 16) | (0x8c1c >> 2),
158 0x00000000,
159 (0x0e00 << 16) | (0x9700 >> 2),
160 0x00000000,
161 (0x0e00 << 16) | (0xcd20 >> 2),
162 0x00000000,
163 (0x4e00 << 16) | (0xcd20 >> 2),
164 0x00000000,
165 (0x5e00 << 16) | (0xcd20 >> 2),
166 0x00000000,
167 (0x6e00 << 16) | (0xcd20 >> 2),
168 0x00000000,
169 (0x7e00 << 16) | (0xcd20 >> 2),
170 0x00000000,
171 (0x8e00 << 16) | (0xcd20 >> 2),
172 0x00000000,
173 (0x9e00 << 16) | (0xcd20 >> 2),
174 0x00000000,
175 (0xae00 << 16) | (0xcd20 >> 2),
176 0x00000000,
177 (0xbe00 << 16) | (0xcd20 >> 2),
178 0x00000000,
179 (0x0e00 << 16) | (0x89bc >> 2),
180 0x00000000,
181 (0x0e00 << 16) | (0x8900 >> 2),
182 0x00000000,
183 0x3,
184 (0x0e00 << 16) | (0xc130 >> 2),
185 0x00000000,
186 (0x0e00 << 16) | (0xc134 >> 2),
187 0x00000000,
188 (0x0e00 << 16) | (0xc1fc >> 2),
189 0x00000000,
190 (0x0e00 << 16) | (0xc208 >> 2),
191 0x00000000,
192 (0x0e00 << 16) | (0xc264 >> 2),
193 0x00000000,
194 (0x0e00 << 16) | (0xc268 >> 2),
195 0x00000000,
196 (0x0e00 << 16) | (0xc26c >> 2),
197 0x00000000,
198 (0x0e00 << 16) | (0xc270 >> 2),
199 0x00000000,
200 (0x0e00 << 16) | (0xc274 >> 2),
201 0x00000000,
202 (0x0e00 << 16) | (0xc278 >> 2),
203 0x00000000,
204 (0x0e00 << 16) | (0xc27c >> 2),
205 0x00000000,
206 (0x0e00 << 16) | (0xc280 >> 2),
207 0x00000000,
208 (0x0e00 << 16) | (0xc284 >> 2),
209 0x00000000,
210 (0x0e00 << 16) | (0xc288 >> 2),
211 0x00000000,
212 (0x0e00 << 16) | (0xc28c >> 2),
213 0x00000000,
214 (0x0e00 << 16) | (0xc290 >> 2),
215 0x00000000,
216 (0x0e00 << 16) | (0xc294 >> 2),
217 0x00000000,
218 (0x0e00 << 16) | (0xc298 >> 2),
219 0x00000000,
220 (0x0e00 << 16) | (0xc29c >> 2),
221 0x00000000,
222 (0x0e00 << 16) | (0xc2a0 >> 2),
223 0x00000000,
224 (0x0e00 << 16) | (0xc2a4 >> 2),
225 0x00000000,
226 (0x0e00 << 16) | (0xc2a8 >> 2),
227 0x00000000,
228 (0x0e00 << 16) | (0xc2ac >> 2),
229 0x00000000,
230 (0x0e00 << 16) | (0xc2b0 >> 2),
231 0x00000000,
232 (0x0e00 << 16) | (0x301d0 >> 2),
233 0x00000000,
234 (0x0e00 << 16) | (0x30238 >> 2),
235 0x00000000,
236 (0x0e00 << 16) | (0x30250 >> 2),
237 0x00000000,
238 (0x0e00 << 16) | (0x30254 >> 2),
239 0x00000000,
240 (0x0e00 << 16) | (0x30258 >> 2),
241 0x00000000,
242 (0x0e00 << 16) | (0x3025c >> 2),
243 0x00000000,
244 (0x4e00 << 16) | (0xc900 >> 2),
245 0x00000000,
246 (0x5e00 << 16) | (0xc900 >> 2),
247 0x00000000,
248 (0x6e00 << 16) | (0xc900 >> 2),
249 0x00000000,
250 (0x7e00 << 16) | (0xc900 >> 2),
251 0x00000000,
252 (0x8e00 << 16) | (0xc900 >> 2),
253 0x00000000,
254 (0x9e00 << 16) | (0xc900 >> 2),
255 0x00000000,
256 (0xae00 << 16) | (0xc900 >> 2),
257 0x00000000,
258 (0xbe00 << 16) | (0xc900 >> 2),
259 0x00000000,
260 (0x4e00 << 16) | (0xc904 >> 2),
261 0x00000000,
262 (0x5e00 << 16) | (0xc904 >> 2),
263 0x00000000,
264 (0x6e00 << 16) | (0xc904 >> 2),
265 0x00000000,
266 (0x7e00 << 16) | (0xc904 >> 2),
267 0x00000000,
268 (0x8e00 << 16) | (0xc904 >> 2),
269 0x00000000,
270 (0x9e00 << 16) | (0xc904 >> 2),
271 0x00000000,
272 (0xae00 << 16) | (0xc904 >> 2),
273 0x00000000,
274 (0xbe00 << 16) | (0xc904 >> 2),
275 0x00000000,
276 (0x4e00 << 16) | (0xc908 >> 2),
277 0x00000000,
278 (0x5e00 << 16) | (0xc908 >> 2),
279 0x00000000,
280 (0x6e00 << 16) | (0xc908 >> 2),
281 0x00000000,
282 (0x7e00 << 16) | (0xc908 >> 2),
283 0x00000000,
284 (0x8e00 << 16) | (0xc908 >> 2),
285 0x00000000,
286 (0x9e00 << 16) | (0xc908 >> 2),
287 0x00000000,
288 (0xae00 << 16) | (0xc908 >> 2),
289 0x00000000,
290 (0xbe00 << 16) | (0xc908 >> 2),
291 0x00000000,
292 (0x4e00 << 16) | (0xc90c >> 2),
293 0x00000000,
294 (0x5e00 << 16) | (0xc90c >> 2),
295 0x00000000,
296 (0x6e00 << 16) | (0xc90c >> 2),
297 0x00000000,
298 (0x7e00 << 16) | (0xc90c >> 2),
299 0x00000000,
300 (0x8e00 << 16) | (0xc90c >> 2),
301 0x00000000,
302 (0x9e00 << 16) | (0xc90c >> 2),
303 0x00000000,
304 (0xae00 << 16) | (0xc90c >> 2),
305 0x00000000,
306 (0xbe00 << 16) | (0xc90c >> 2),
307 0x00000000,
308 (0x4e00 << 16) | (0xc910 >> 2),
309 0x00000000,
310 (0x5e00 << 16) | (0xc910 >> 2),
311 0x00000000,
312 (0x6e00 << 16) | (0xc910 >> 2),
313 0x00000000,
314 (0x7e00 << 16) | (0xc910 >> 2),
315 0x00000000,
316 (0x8e00 << 16) | (0xc910 >> 2),
317 0x00000000,
318 (0x9e00 << 16) | (0xc910 >> 2),
319 0x00000000,
320 (0xae00 << 16) | (0xc910 >> 2),
321 0x00000000,
322 (0xbe00 << 16) | (0xc910 >> 2),
323 0x00000000,
324 (0x0e00 << 16) | (0xc99c >> 2),
325 0x00000000,
326 (0x0e00 << 16) | (0x9834 >> 2),
327 0x00000000,
328 (0x0000 << 16) | (0x30f00 >> 2),
329 0x00000000,
330 (0x0001 << 16) | (0x30f00 >> 2),
331 0x00000000,
332 (0x0000 << 16) | (0x30f04 >> 2),
333 0x00000000,
334 (0x0001 << 16) | (0x30f04 >> 2),
335 0x00000000,
336 (0x0000 << 16) | (0x30f08 >> 2),
337 0x00000000,
338 (0x0001 << 16) | (0x30f08 >> 2),
339 0x00000000,
340 (0x0000 << 16) | (0x30f0c >> 2),
341 0x00000000,
342 (0x0001 << 16) | (0x30f0c >> 2),
343 0x00000000,
344 (0x0600 << 16) | (0x9b7c >> 2),
345 0x00000000,
346 (0x0e00 << 16) | (0x8a14 >> 2),
347 0x00000000,
348 (0x0e00 << 16) | (0x8a18 >> 2),
349 0x00000000,
350 (0x0600 << 16) | (0x30a00 >> 2),
351 0x00000000,
352 (0x0e00 << 16) | (0x8bf0 >> 2),
353 0x00000000,
354 (0x0e00 << 16) | (0x8bcc >> 2),
355 0x00000000,
356 (0x0e00 << 16) | (0x8b24 >> 2),
357 0x00000000,
358 (0x0e00 << 16) | (0x30a04 >> 2),
359 0x00000000,
360 (0x0600 << 16) | (0x30a10 >> 2),
361 0x00000000,
362 (0x0600 << 16) | (0x30a14 >> 2),
363 0x00000000,
364 (0x0600 << 16) | (0x30a18 >> 2),
365 0x00000000,
366 (0x0600 << 16) | (0x30a2c >> 2),
367 0x00000000,
368 (0x0e00 << 16) | (0xc700 >> 2),
369 0x00000000,
370 (0x0e00 << 16) | (0xc704 >> 2),
371 0x00000000,
372 (0x0e00 << 16) | (0xc708 >> 2),
373 0x00000000,
374 (0x0e00 << 16) | (0xc768 >> 2),
375 0x00000000,
376 (0x0400 << 16) | (0xc770 >> 2),
377 0x00000000,
378 (0x0400 << 16) | (0xc774 >> 2),
379 0x00000000,
380 (0x0400 << 16) | (0xc778 >> 2),
381 0x00000000,
382 (0x0400 << 16) | (0xc77c >> 2),
383 0x00000000,
384 (0x0400 << 16) | (0xc780 >> 2),
385 0x00000000,
386 (0x0400 << 16) | (0xc784 >> 2),
387 0x00000000,
388 (0x0400 << 16) | (0xc788 >> 2),
389 0x00000000,
390 (0x0400 << 16) | (0xc78c >> 2),
391 0x00000000,
392 (0x0400 << 16) | (0xc798 >> 2),
393 0x00000000,
394 (0x0400 << 16) | (0xc79c >> 2),
395 0x00000000,
396 (0x0400 << 16) | (0xc7a0 >> 2),
397 0x00000000,
398 (0x0400 << 16) | (0xc7a4 >> 2),
399 0x00000000,
400 (0x0400 << 16) | (0xc7a8 >> 2),
401 0x00000000,
402 (0x0400 << 16) | (0xc7ac >> 2),
403 0x00000000,
404 (0x0400 << 16) | (0xc7b0 >> 2),
405 0x00000000,
406 (0x0400 << 16) | (0xc7b4 >> 2),
407 0x00000000,
408 (0x0e00 << 16) | (0x9100 >> 2),
409 0x00000000,
410 (0x0e00 << 16) | (0x3c010 >> 2),
411 0x00000000,
412 (0x0e00 << 16) | (0x92a8 >> 2),
413 0x00000000,
414 (0x0e00 << 16) | (0x92ac >> 2),
415 0x00000000,
416 (0x0e00 << 16) | (0x92b4 >> 2),
417 0x00000000,
418 (0x0e00 << 16) | (0x92b8 >> 2),
419 0x00000000,
420 (0x0e00 << 16) | (0x92bc >> 2),
421 0x00000000,
422 (0x0e00 << 16) | (0x92c0 >> 2),
423 0x00000000,
424 (0x0e00 << 16) | (0x92c4 >> 2),
425 0x00000000,
426 (0x0e00 << 16) | (0x92c8 >> 2),
427 0x00000000,
428 (0x0e00 << 16) | (0x92cc >> 2),
429 0x00000000,
430 (0x0e00 << 16) | (0x92d0 >> 2),
431 0x00000000,
432 (0x0e00 << 16) | (0x8c00 >> 2),
433 0x00000000,
434 (0x0e00 << 16) | (0x8c04 >> 2),
435 0x00000000,
436 (0x0e00 << 16) | (0x8c20 >> 2),
437 0x00000000,
438 (0x0e00 << 16) | (0x8c38 >> 2),
439 0x00000000,
440 (0x0e00 << 16) | (0x8c3c >> 2),
441 0x00000000,
442 (0x0e00 << 16) | (0xae00 >> 2),
443 0x00000000,
444 (0x0e00 << 16) | (0x9604 >> 2),
445 0x00000000,
446 (0x0e00 << 16) | (0xac08 >> 2),
447 0x00000000,
448 (0x0e00 << 16) | (0xac0c >> 2),
449 0x00000000,
450 (0x0e00 << 16) | (0xac10 >> 2),
451 0x00000000,
452 (0x0e00 << 16) | (0xac14 >> 2),
453 0x00000000,
454 (0x0e00 << 16) | (0xac58 >> 2),
455 0x00000000,
456 (0x0e00 << 16) | (0xac68 >> 2),
457 0x00000000,
458 (0x0e00 << 16) | (0xac6c >> 2),
459 0x00000000,
460 (0x0e00 << 16) | (0xac70 >> 2),
461 0x00000000,
462 (0x0e00 << 16) | (0xac74 >> 2),
463 0x00000000,
464 (0x0e00 << 16) | (0xac78 >> 2),
465 0x00000000,
466 (0x0e00 << 16) | (0xac7c >> 2),
467 0x00000000,
468 (0x0e00 << 16) | (0xac80 >> 2),
469 0x00000000,
470 (0x0e00 << 16) | (0xac84 >> 2),
471 0x00000000,
472 (0x0e00 << 16) | (0xac88 >> 2),
473 0x00000000,
474 (0x0e00 << 16) | (0xac8c >> 2),
475 0x00000000,
476 (0x0e00 << 16) | (0x970c >> 2),
477 0x00000000,
478 (0x0e00 << 16) | (0x9714 >> 2),
479 0x00000000,
480 (0x0e00 << 16) | (0x9718 >> 2),
481 0x00000000,
482 (0x0e00 << 16) | (0x971c >> 2),
483 0x00000000,
484 (0x0e00 << 16) | (0x31068 >> 2),
485 0x00000000,
486 (0x4e00 << 16) | (0x31068 >> 2),
487 0x00000000,
488 (0x5e00 << 16) | (0x31068 >> 2),
489 0x00000000,
490 (0x6e00 << 16) | (0x31068 >> 2),
491 0x00000000,
492 (0x7e00 << 16) | (0x31068 >> 2),
493 0x00000000,
494 (0x8e00 << 16) | (0x31068 >> 2),
495 0x00000000,
496 (0x9e00 << 16) | (0x31068 >> 2),
497 0x00000000,
498 (0xae00 << 16) | (0x31068 >> 2),
499 0x00000000,
500 (0xbe00 << 16) | (0x31068 >> 2),
501 0x00000000,
502 (0x0e00 << 16) | (0xcd10 >> 2),
503 0x00000000,
504 (0x0e00 << 16) | (0xcd14 >> 2),
505 0x00000000,
506 (0x0e00 << 16) | (0x88b0 >> 2),
507 0x00000000,
508 (0x0e00 << 16) | (0x88b4 >> 2),
509 0x00000000,
510 (0x0e00 << 16) | (0x88b8 >> 2),
511 0x00000000,
512 (0x0e00 << 16) | (0x88bc >> 2),
513 0x00000000,
514 (0x0400 << 16) | (0x89c0 >> 2),
515 0x00000000,
516 (0x0e00 << 16) | (0x88c4 >> 2),
517 0x00000000,
518 (0x0e00 << 16) | (0x88c8 >> 2),
519 0x00000000,
520 (0x0e00 << 16) | (0x88d0 >> 2),
521 0x00000000,
522 (0x0e00 << 16) | (0x88d4 >> 2),
523 0x00000000,
524 (0x0e00 << 16) | (0x88d8 >> 2),
525 0x00000000,
526 (0x0e00 << 16) | (0x8980 >> 2),
527 0x00000000,
528 (0x0e00 << 16) | (0x30938 >> 2),
529 0x00000000,
530 (0x0e00 << 16) | (0x3093c >> 2),
531 0x00000000,
532 (0x0e00 << 16) | (0x30940 >> 2),
533 0x00000000,
534 (0x0e00 << 16) | (0x89a0 >> 2),
535 0x00000000,
536 (0x0e00 << 16) | (0x30900 >> 2),
537 0x00000000,
538 (0x0e00 << 16) | (0x30904 >> 2),
539 0x00000000,
540 (0x0e00 << 16) | (0x89b4 >> 2),
541 0x00000000,
542 (0x0e00 << 16) | (0x3c210 >> 2),
543 0x00000000,
544 (0x0e00 << 16) | (0x3c214 >> 2),
545 0x00000000,
546 (0x0e00 << 16) | (0x3c218 >> 2),
547 0x00000000,
548 (0x0e00 << 16) | (0x8904 >> 2),
549 0x00000000,
550 0x5,
551 (0x0e00 << 16) | (0x8c28 >> 2),
552 (0x0e00 << 16) | (0x8c2c >> 2),
553 (0x0e00 << 16) | (0x8c30 >> 2),
554 (0x0e00 << 16) | (0x8c34 >> 2),
555 (0x0e00 << 16) | (0x9600 >> 2),
556};
557
558static const u32 kalindi_rlc_save_restore_register_list[] =
559{
560 (0x0e00 << 16) | (0xc12c >> 2),
561 0x00000000,
562 (0x0e00 << 16) | (0xc140 >> 2),
563 0x00000000,
564 (0x0e00 << 16) | (0xc150 >> 2),
565 0x00000000,
566 (0x0e00 << 16) | (0xc15c >> 2),
567 0x00000000,
568 (0x0e00 << 16) | (0xc168 >> 2),
569 0x00000000,
570 (0x0e00 << 16) | (0xc170 >> 2),
571 0x00000000,
572 (0x0e00 << 16) | (0xc204 >> 2),
573 0x00000000,
574 (0x0e00 << 16) | (0xc2b4 >> 2),
575 0x00000000,
576 (0x0e00 << 16) | (0xc2b8 >> 2),
577 0x00000000,
578 (0x0e00 << 16) | (0xc2bc >> 2),
579 0x00000000,
580 (0x0e00 << 16) | (0xc2c0 >> 2),
581 0x00000000,
582 (0x0e00 << 16) | (0x8228 >> 2),
583 0x00000000,
584 (0x0e00 << 16) | (0x829c >> 2),
585 0x00000000,
586 (0x0e00 << 16) | (0x869c >> 2),
587 0x00000000,
588 (0x0600 << 16) | (0x98f4 >> 2),
589 0x00000000,
590 (0x0e00 << 16) | (0x98f8 >> 2),
591 0x00000000,
592 (0x0e00 << 16) | (0x9900 >> 2),
593 0x00000000,
594 (0x0e00 << 16) | (0xc260 >> 2),
595 0x00000000,
596 (0x0e00 << 16) | (0x90e8 >> 2),
597 0x00000000,
598 (0x0e00 << 16) | (0x3c000 >> 2),
599 0x00000000,
600 (0x0e00 << 16) | (0x3c00c >> 2),
601 0x00000000,
602 (0x0e00 << 16) | (0x8c1c >> 2),
603 0x00000000,
604 (0x0e00 << 16) | (0x9700 >> 2),
605 0x00000000,
606 (0x0e00 << 16) | (0xcd20 >> 2),
607 0x00000000,
608 (0x4e00 << 16) | (0xcd20 >> 2),
609 0x00000000,
610 (0x5e00 << 16) | (0xcd20 >> 2),
611 0x00000000,
612 (0x6e00 << 16) | (0xcd20 >> 2),
613 0x00000000,
614 (0x7e00 << 16) | (0xcd20 >> 2),
615 0x00000000,
616 (0x0e00 << 16) | (0x89bc >> 2),
617 0x00000000,
618 (0x0e00 << 16) | (0x8900 >> 2),
619 0x00000000,
620 0x3,
621 (0x0e00 << 16) | (0xc130 >> 2),
622 0x00000000,
623 (0x0e00 << 16) | (0xc134 >> 2),
624 0x00000000,
625 (0x0e00 << 16) | (0xc1fc >> 2),
626 0x00000000,
627 (0x0e00 << 16) | (0xc208 >> 2),
628 0x00000000,
629 (0x0e00 << 16) | (0xc264 >> 2),
630 0x00000000,
631 (0x0e00 << 16) | (0xc268 >> 2),
632 0x00000000,
633 (0x0e00 << 16) | (0xc26c >> 2),
634 0x00000000,
635 (0x0e00 << 16) | (0xc270 >> 2),
636 0x00000000,
637 (0x0e00 << 16) | (0xc274 >> 2),
638 0x00000000,
639 (0x0e00 << 16) | (0xc28c >> 2),
640 0x00000000,
641 (0x0e00 << 16) | (0xc290 >> 2),
642 0x00000000,
643 (0x0e00 << 16) | (0xc294 >> 2),
644 0x00000000,
645 (0x0e00 << 16) | (0xc298 >> 2),
646 0x00000000,
647 (0x0e00 << 16) | (0xc2a0 >> 2),
648 0x00000000,
649 (0x0e00 << 16) | (0xc2a4 >> 2),
650 0x00000000,
651 (0x0e00 << 16) | (0xc2a8 >> 2),
652 0x00000000,
653 (0x0e00 << 16) | (0xc2ac >> 2),
654 0x00000000,
655 (0x0e00 << 16) | (0x301d0 >> 2),
656 0x00000000,
657 (0x0e00 << 16) | (0x30238 >> 2),
658 0x00000000,
659 (0x0e00 << 16) | (0x30250 >> 2),
660 0x00000000,
661 (0x0e00 << 16) | (0x30254 >> 2),
662 0x00000000,
663 (0x0e00 << 16) | (0x30258 >> 2),
664 0x00000000,
665 (0x0e00 << 16) | (0x3025c >> 2),
666 0x00000000,
667 (0x4e00 << 16) | (0xc900 >> 2),
668 0x00000000,
669 (0x5e00 << 16) | (0xc900 >> 2),
670 0x00000000,
671 (0x6e00 << 16) | (0xc900 >> 2),
672 0x00000000,
673 (0x7e00 << 16) | (0xc900 >> 2),
674 0x00000000,
675 (0x4e00 << 16) | (0xc904 >> 2),
676 0x00000000,
677 (0x5e00 << 16) | (0xc904 >> 2),
678 0x00000000,
679 (0x6e00 << 16) | (0xc904 >> 2),
680 0x00000000,
681 (0x7e00 << 16) | (0xc904 >> 2),
682 0x00000000,
683 (0x4e00 << 16) | (0xc908 >> 2),
684 0x00000000,
685 (0x5e00 << 16) | (0xc908 >> 2),
686 0x00000000,
687 (0x6e00 << 16) | (0xc908 >> 2),
688 0x00000000,
689 (0x7e00 << 16) | (0xc908 >> 2),
690 0x00000000,
691 (0x4e00 << 16) | (0xc90c >> 2),
692 0x00000000,
693 (0x5e00 << 16) | (0xc90c >> 2),
694 0x00000000,
695 (0x6e00 << 16) | (0xc90c >> 2),
696 0x00000000,
697 (0x7e00 << 16) | (0xc90c >> 2),
698 0x00000000,
699 (0x4e00 << 16) | (0xc910 >> 2),
700 0x00000000,
701 (0x5e00 << 16) | (0xc910 >> 2),
702 0x00000000,
703 (0x6e00 << 16) | (0xc910 >> 2),
704 0x00000000,
705 (0x7e00 << 16) | (0xc910 >> 2),
706 0x00000000,
707 (0x0e00 << 16) | (0xc99c >> 2),
708 0x00000000,
709 (0x0e00 << 16) | (0x9834 >> 2),
710 0x00000000,
711 (0x0000 << 16) | (0x30f00 >> 2),
712 0x00000000,
713 (0x0000 << 16) | (0x30f04 >> 2),
714 0x00000000,
715 (0x0000 << 16) | (0x30f08 >> 2),
716 0x00000000,
717 (0x0000 << 16) | (0x30f0c >> 2),
718 0x00000000,
719 (0x0600 << 16) | (0x9b7c >> 2),
720 0x00000000,
721 (0x0e00 << 16) | (0x8a14 >> 2),
722 0x00000000,
723 (0x0e00 << 16) | (0x8a18 >> 2),
724 0x00000000,
725 (0x0600 << 16) | (0x30a00 >> 2),
726 0x00000000,
727 (0x0e00 << 16) | (0x8bf0 >> 2),
728 0x00000000,
729 (0x0e00 << 16) | (0x8bcc >> 2),
730 0x00000000,
731 (0x0e00 << 16) | (0x8b24 >> 2),
732 0x00000000,
733 (0x0e00 << 16) | (0x30a04 >> 2),
734 0x00000000,
735 (0x0600 << 16) | (0x30a10 >> 2),
736 0x00000000,
737 (0x0600 << 16) | (0x30a14 >> 2),
738 0x00000000,
739 (0x0600 << 16) | (0x30a18 >> 2),
740 0x00000000,
741 (0x0600 << 16) | (0x30a2c >> 2),
742 0x00000000,
743 (0x0e00 << 16) | (0xc700 >> 2),
744 0x00000000,
745 (0x0e00 << 16) | (0xc704 >> 2),
746 0x00000000,
747 (0x0e00 << 16) | (0xc708 >> 2),
748 0x00000000,
749 (0x0e00 << 16) | (0xc768 >> 2),
750 0x00000000,
751 (0x0400 << 16) | (0xc770 >> 2),
752 0x00000000,
753 (0x0400 << 16) | (0xc774 >> 2),
754 0x00000000,
755 (0x0400 << 16) | (0xc798 >> 2),
756 0x00000000,
757 (0x0400 << 16) | (0xc79c >> 2),
758 0x00000000,
759 (0x0e00 << 16) | (0x9100 >> 2),
760 0x00000000,
761 (0x0e00 << 16) | (0x3c010 >> 2),
762 0x00000000,
763 (0x0e00 << 16) | (0x8c00 >> 2),
764 0x00000000,
765 (0x0e00 << 16) | (0x8c04 >> 2),
766 0x00000000,
767 (0x0e00 << 16) | (0x8c20 >> 2),
768 0x00000000,
769 (0x0e00 << 16) | (0x8c38 >> 2),
770 0x00000000,
771 (0x0e00 << 16) | (0x8c3c >> 2),
772 0x00000000,
773 (0x0e00 << 16) | (0xae00 >> 2),
774 0x00000000,
775 (0x0e00 << 16) | (0x9604 >> 2),
776 0x00000000,
777 (0x0e00 << 16) | (0xac08 >> 2),
778 0x00000000,
779 (0x0e00 << 16) | (0xac0c >> 2),
780 0x00000000,
781 (0x0e00 << 16) | (0xac10 >> 2),
782 0x00000000,
783 (0x0e00 << 16) | (0xac14 >> 2),
784 0x00000000,
785 (0x0e00 << 16) | (0xac58 >> 2),
786 0x00000000,
787 (0x0e00 << 16) | (0xac68 >> 2),
788 0x00000000,
789 (0x0e00 << 16) | (0xac6c >> 2),
790 0x00000000,
791 (0x0e00 << 16) | (0xac70 >> 2),
792 0x00000000,
793 (0x0e00 << 16) | (0xac74 >> 2),
794 0x00000000,
795 (0x0e00 << 16) | (0xac78 >> 2),
796 0x00000000,
797 (0x0e00 << 16) | (0xac7c >> 2),
798 0x00000000,
799 (0x0e00 << 16) | (0xac80 >> 2),
800 0x00000000,
801 (0x0e00 << 16) | (0xac84 >> 2),
802 0x00000000,
803 (0x0e00 << 16) | (0xac88 >> 2),
804 0x00000000,
805 (0x0e00 << 16) | (0xac8c >> 2),
806 0x00000000,
807 (0x0e00 << 16) | (0x970c >> 2),
808 0x00000000,
809 (0x0e00 << 16) | (0x9714 >> 2),
810 0x00000000,
811 (0x0e00 << 16) | (0x9718 >> 2),
812 0x00000000,
813 (0x0e00 << 16) | (0x971c >> 2),
814 0x00000000,
815 (0x0e00 << 16) | (0x31068 >> 2),
816 0x00000000,
817 (0x4e00 << 16) | (0x31068 >> 2),
818 0x00000000,
819 (0x5e00 << 16) | (0x31068 >> 2),
820 0x00000000,
821 (0x6e00 << 16) | (0x31068 >> 2),
822 0x00000000,
823 (0x7e00 << 16) | (0x31068 >> 2),
824 0x00000000,
825 (0x0e00 << 16) | (0xcd10 >> 2),
826 0x00000000,
827 (0x0e00 << 16) | (0xcd14 >> 2),
828 0x00000000,
829 (0x0e00 << 16) | (0x88b0 >> 2),
830 0x00000000,
831 (0x0e00 << 16) | (0x88b4 >> 2),
832 0x00000000,
833 (0x0e00 << 16) | (0x88b8 >> 2),
834 0x00000000,
835 (0x0e00 << 16) | (0x88bc >> 2),
836 0x00000000,
837 (0x0400 << 16) | (0x89c0 >> 2),
838 0x00000000,
839 (0x0e00 << 16) | (0x88c4 >> 2),
840 0x00000000,
841 (0x0e00 << 16) | (0x88c8 >> 2),
842 0x00000000,
843 (0x0e00 << 16) | (0x88d0 >> 2),
844 0x00000000,
845 (0x0e00 << 16) | (0x88d4 >> 2),
846 0x00000000,
847 (0x0e00 << 16) | (0x88d8 >> 2),
848 0x00000000,
849 (0x0e00 << 16) | (0x8980 >> 2),
850 0x00000000,
851 (0x0e00 << 16) | (0x30938 >> 2),
852 0x00000000,
853 (0x0e00 << 16) | (0x3093c >> 2),
854 0x00000000,
855 (0x0e00 << 16) | (0x30940 >> 2),
856 0x00000000,
857 (0x0e00 << 16) | (0x89a0 >> 2),
858 0x00000000,
859 (0x0e00 << 16) | (0x30900 >> 2),
860 0x00000000,
861 (0x0e00 << 16) | (0x30904 >> 2),
862 0x00000000,
863 (0x0e00 << 16) | (0x89b4 >> 2),
864 0x00000000,
865 (0x0e00 << 16) | (0x3e1fc >> 2),
866 0x00000000,
867 (0x0e00 << 16) | (0x3c210 >> 2),
868 0x00000000,
869 (0x0e00 << 16) | (0x3c214 >> 2),
870 0x00000000,
871 (0x0e00 << 16) | (0x3c218 >> 2),
872 0x00000000,
873 (0x0e00 << 16) | (0x8904 >> 2),
874 0x00000000,
875 0x5,
876 (0x0e00 << 16) | (0x8c28 >> 2),
877 (0x0e00 << 16) | (0x8c2c >> 2),
878 (0x0e00 << 16) | (0x8c30 >> 2),
879 (0x0e00 << 16) | (0x8c34 >> 2),
880 (0x0e00 << 16) | (0x9600 >> 2),
881};
882
883static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
884static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
885static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
886static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
887
888/*
889 * Core functions
890 */
891/**
892 * gfx_v7_0_init_microcode - load ucode images from disk
893 *
894 * @adev: amdgpu_device pointer
895 *
896 * Use the firmware interface to load the ucode images into
897 * the driver (not loaded into hw).
898 * Returns 0 on success, error on failure.
899 */
900static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
901{
902 const char *chip_name;
903 char fw_name[30];
904 int err;
905
906 DRM_DEBUG("\n");
907
908 switch (adev->asic_type) {
909 case CHIP_BONAIRE:
910 chip_name = "bonaire";
911 break;
912 case CHIP_HAWAII:
913 chip_name = "hawaii";
914 break;
915 case CHIP_KAVERI:
916 chip_name = "kaveri";
917 break;
918 case CHIP_KABINI:
919 chip_name = "kabini";
920 break;
921 case CHIP_MULLINS:
922 chip_name = "mullins";
923 break;
924 default: BUG();
925 }
926
927 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
928 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
929 if (err)
930 goto out;
931 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
932 if (err)
933 goto out;
934
935 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
936 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
937 if (err)
938 goto out;
939 err = amdgpu_ucode_validate(adev->gfx.me_fw);
940 if (err)
941 goto out;
942
943 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
944 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
945 if (err)
946 goto out;
947 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
948 if (err)
949 goto out;
950
951 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
952 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
953 if (err)
954 goto out;
955 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
956 if (err)
957 goto out;
958
959 if (adev->asic_type == CHIP_KAVERI) {
960 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
961 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
962 if (err)
963 goto out;
964 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
965 if (err)
966 goto out;
967 }
968
969 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
970 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
971 if (err)
972 goto out;
973 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
974
975out:
976 if (err) {
977 printk(KERN_ERR
978 "gfx7: Failed to load firmware \"%s\"\n",
979 fw_name);
980 release_firmware(adev->gfx.pfp_fw);
981 adev->gfx.pfp_fw = NULL;
982 release_firmware(adev->gfx.me_fw);
983 adev->gfx.me_fw = NULL;
984 release_firmware(adev->gfx.ce_fw);
985 adev->gfx.ce_fw = NULL;
986 release_firmware(adev->gfx.mec_fw);
987 adev->gfx.mec_fw = NULL;
988 release_firmware(adev->gfx.mec2_fw);
989 adev->gfx.mec2_fw = NULL;
990 release_firmware(adev->gfx.rlc_fw);
991 adev->gfx.rlc_fw = NULL;
992 }
993 return err;
994}
995
996/**
997 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
998 *
999 * @adev: amdgpu_device pointer
1000 *
1001 * Starting with SI, the tiling setup is done globally in a
1002 * set of 32 tiling modes. Rather than selecting each set of
1003 * parameters per surface as on older asics, we just select
1004 * which index in the tiling table we want to use, and the
1005 * surface uses those parameters (CIK).
1006 */
1007static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1008{
1009 const u32 num_tile_mode_states = 32;
1010 const u32 num_secondary_tile_mode_states = 16;
1011 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1012
1013 switch (adev->gfx.config.mem_row_size_in_kb) {
1014 case 1:
1015 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1016 break;
1017 case 2:
1018 default:
1019 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1020 break;
1021 case 4:
1022 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1023 break;
1024 }
1025
1026 switch (adev->asic_type) {
1027 case CHIP_BONAIRE:
1028 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1029 switch (reg_offset) {
1030 case 0:
1031 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1032 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1033 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1034 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1035 break;
1036 case 1:
1037 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1039 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1040 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1041 break;
1042 case 2:
1043 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1044 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1045 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1046 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1047 break;
1048 case 3:
1049 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1050 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1052 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1053 break;
1054 case 4:
1055 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1057 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1058 TILE_SPLIT(split_equal_to_row_size));
1059 break;
1060 case 5:
1061 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1063 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1064 break;
1065 case 6:
1066 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1067 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1068 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1069 TILE_SPLIT(split_equal_to_row_size));
1070 break;
1071 case 7:
1072 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1073 break;
1074
1075 case 8:
1076 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1077 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1078 break;
1079 case 9:
1080 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1081 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1082 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1083 break;
1084 case 10:
1085 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1087 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1088 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1089 break;
1090 case 11:
1091 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1092 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1093 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1094 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1095 break;
1096 case 12:
1097 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1098 break;
1099 case 13:
1100 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1101 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1102 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1103 break;
1104 case 14:
1105 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1106 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1107 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1108 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1109 break;
1110 case 15:
1111 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1115 break;
1116 case 16:
1117 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1118 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1119 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1120 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1121 break;
1122 case 17:
1123 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1124 break;
1125 case 18:
1126 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1127 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1128 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1130 break;
1131 case 19:
1132 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1133 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1134 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1135 break;
1136 case 20:
1137 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1138 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1139 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1140 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1141 break;
1142 case 21:
1143 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1144 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1145 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1146 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1147 break;
1148 case 22:
1149 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1150 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1151 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1152 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1153 break;
1154 case 23:
1155 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1156 break;
1157 case 24:
1158 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1159 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1160 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1161 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1162 break;
1163 case 25:
1164 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1165 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1166 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1167 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1168 break;
1169 case 26:
1170 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1171 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1172 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1173 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1174 break;
1175 case 27:
1176 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1177 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1178 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1179 break;
1180 case 28:
1181 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1182 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1183 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1184 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1185 break;
1186 case 29:
1187 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1188 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1189 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1190 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1191 break;
1192 case 30:
1193 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1194 break;
1195 default:
1196 gb_tile_moden = 0;
1197 break;
1198 }
1199 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1200 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1201 }
1202 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1203 switch (reg_offset) {
1204 case 0:
1205 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1208 NUM_BANKS(ADDR_SURF_16_BANK));
1209 break;
1210 case 1:
1211 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1214 NUM_BANKS(ADDR_SURF_16_BANK));
1215 break;
1216 case 2:
1217 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1218 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1219 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1220 NUM_BANKS(ADDR_SURF_16_BANK));
1221 break;
1222 case 3:
1223 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1224 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1225 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1226 NUM_BANKS(ADDR_SURF_16_BANK));
1227 break;
1228 case 4:
1229 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1232 NUM_BANKS(ADDR_SURF_16_BANK));
1233 break;
1234 case 5:
1235 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1236 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1237 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1238 NUM_BANKS(ADDR_SURF_8_BANK));
1239 break;
1240 case 6:
1241 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1242 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1243 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1244 NUM_BANKS(ADDR_SURF_4_BANK));
1245 break;
1246 case 8:
1247 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1250 NUM_BANKS(ADDR_SURF_16_BANK));
1251 break;
1252 case 9:
1253 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1256 NUM_BANKS(ADDR_SURF_16_BANK));
1257 break;
1258 case 10:
1259 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1262 NUM_BANKS(ADDR_SURF_16_BANK));
1263 break;
1264 case 11:
1265 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1266 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1267 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1268 NUM_BANKS(ADDR_SURF_16_BANK));
1269 break;
1270 case 12:
1271 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1272 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1273 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1274 NUM_BANKS(ADDR_SURF_16_BANK));
1275 break;
1276 case 13:
1277 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1278 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1279 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1280 NUM_BANKS(ADDR_SURF_8_BANK));
1281 break;
1282 case 14:
1283 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1284 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1285 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1286 NUM_BANKS(ADDR_SURF_4_BANK));
1287 break;
1288 default:
1289 gb_tile_moden = 0;
1290 break;
1291 }
1292 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1293 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1294 }
1295 break;
1296 case CHIP_HAWAII:
1297 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1298 switch (reg_offset) {
1299 case 0:
1300 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1301 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1302 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1303 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1304 break;
1305 case 1:
1306 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1307 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1308 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1310 break;
1311 case 2:
1312 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1313 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1314 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1315 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1316 break;
1317 case 3:
1318 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1320 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1321 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1322 break;
1323 case 4:
1324 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1325 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1326 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1327 TILE_SPLIT(split_equal_to_row_size));
1328 break;
1329 case 5:
1330 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1332 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1333 TILE_SPLIT(split_equal_to_row_size));
1334 break;
1335 case 6:
1336 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1337 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1338 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1339 TILE_SPLIT(split_equal_to_row_size));
1340 break;
1341 case 7:
1342 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1343 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1344 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1345 TILE_SPLIT(split_equal_to_row_size));
1346 break;
1347
1348 case 8:
1349 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1350 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1351 break;
1352 case 9:
1353 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1354 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1355 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1356 break;
1357 case 10:
1358 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1359 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1360 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1361 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1362 break;
1363 case 11:
1364 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1365 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1366 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1367 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1368 break;
1369 case 12:
1370 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1371 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1372 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1373 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1374 break;
1375 case 13:
1376 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1377 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1378 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1379 break;
1380 case 14:
1381 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1382 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1383 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1384 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1385 break;
1386 case 15:
1387 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1388 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1389 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1390 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1391 break;
1392 case 16:
1393 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1394 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1395 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1396 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1397 break;
1398 case 17:
1399 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1400 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1401 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1402 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1403 break;
1404 case 18:
1405 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1406 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1407 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1408 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1409 break;
1410 case 19:
1411 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1412 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1413 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1414 break;
1415 case 20:
1416 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1417 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1418 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1420 break;
1421 case 21:
1422 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1423 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1424 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1425 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1426 break;
1427 case 22:
1428 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1429 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1430 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1431 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1432 break;
1433 case 23:
1434 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1435 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1436 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1437 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1438 break;
1439 case 24:
1440 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1441 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1442 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1443 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1444 break;
1445 case 25:
1446 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1447 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1448 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1449 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1450 break;
1451 case 26:
1452 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1453 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1454 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1455 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1456 break;
1457 case 27:
1458 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1459 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1460 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1461 break;
1462 case 28:
1463 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1464 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1465 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1467 break;
1468 case 29:
1469 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1470 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1471 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1472 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1473 break;
1474 case 30:
1475 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1476 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1477 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1479 break;
1480 default:
1481 gb_tile_moden = 0;
1482 break;
1483 }
1484 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1485 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1486 }
1487 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1488 switch (reg_offset) {
1489 case 0:
1490 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1492 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1493 NUM_BANKS(ADDR_SURF_16_BANK));
1494 break;
1495 case 1:
1496 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1497 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1498 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1499 NUM_BANKS(ADDR_SURF_16_BANK));
1500 break;
1501 case 2:
1502 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1504 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1505 NUM_BANKS(ADDR_SURF_16_BANK));
1506 break;
1507 case 3:
1508 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1509 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1510 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1511 NUM_BANKS(ADDR_SURF_16_BANK));
1512 break;
1513 case 4:
1514 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1515 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1516 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1517 NUM_BANKS(ADDR_SURF_8_BANK));
1518 break;
1519 case 5:
1520 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1521 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1522 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1523 NUM_BANKS(ADDR_SURF_4_BANK));
1524 break;
1525 case 6:
1526 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1529 NUM_BANKS(ADDR_SURF_4_BANK));
1530 break;
1531 case 8:
1532 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1533 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1534 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1535 NUM_BANKS(ADDR_SURF_16_BANK));
1536 break;
1537 case 9:
1538 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1540 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1541 NUM_BANKS(ADDR_SURF_16_BANK));
1542 break;
1543 case 10:
1544 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1546 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1547 NUM_BANKS(ADDR_SURF_16_BANK));
1548 break;
1549 case 11:
1550 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1553 NUM_BANKS(ADDR_SURF_8_BANK));
1554 break;
1555 case 12:
1556 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1557 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1558 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1559 NUM_BANKS(ADDR_SURF_16_BANK));
1560 break;
1561 case 13:
1562 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1563 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1564 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1565 NUM_BANKS(ADDR_SURF_8_BANK));
1566 break;
1567 case 14:
1568 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1569 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1570 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1571 NUM_BANKS(ADDR_SURF_4_BANK));
1572 break;
1573 default:
1574 gb_tile_moden = 0;
1575 break;
1576 }
1577 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1578 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1579 }
1580 break;
1581 case CHIP_KABINI:
1582 case CHIP_KAVERI:
1583 case CHIP_MULLINS:
1584 default:
1585 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1586 switch (reg_offset) {
1587 case 0:
1588 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1589 PIPE_CONFIG(ADDR_SURF_P2) |
1590 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1591 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1592 break;
1593 case 1:
1594 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1595 PIPE_CONFIG(ADDR_SURF_P2) |
1596 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1597 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1598 break;
1599 case 2:
1600 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1601 PIPE_CONFIG(ADDR_SURF_P2) |
1602 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1603 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1604 break;
1605 case 3:
1606 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1607 PIPE_CONFIG(ADDR_SURF_P2) |
1608 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1609 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1610 break;
1611 case 4:
1612 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1613 PIPE_CONFIG(ADDR_SURF_P2) |
1614 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1615 TILE_SPLIT(split_equal_to_row_size));
1616 break;
1617 case 5:
1618 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1619 PIPE_CONFIG(ADDR_SURF_P2) |
1620 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1621 break;
1622 case 6:
1623 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1624 PIPE_CONFIG(ADDR_SURF_P2) |
1625 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1626 TILE_SPLIT(split_equal_to_row_size));
1627 break;
1628 case 7:
1629 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1630 break;
1631
1632 case 8:
1633 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1634 PIPE_CONFIG(ADDR_SURF_P2));
1635 break;
1636 case 9:
1637 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1638 PIPE_CONFIG(ADDR_SURF_P2) |
1639 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1640 break;
1641 case 10:
1642 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1643 PIPE_CONFIG(ADDR_SURF_P2) |
1644 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1645 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1646 break;
1647 case 11:
1648 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1649 PIPE_CONFIG(ADDR_SURF_P2) |
1650 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1651 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1652 break;
1653 case 12:
1654 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1655 break;
1656 case 13:
1657 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1658 PIPE_CONFIG(ADDR_SURF_P2) |
1659 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1660 break;
1661 case 14:
1662 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1663 PIPE_CONFIG(ADDR_SURF_P2) |
1664 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1665 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1666 break;
1667 case 15:
1668 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1669 PIPE_CONFIG(ADDR_SURF_P2) |
1670 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1671 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1672 break;
1673 case 16:
1674 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1675 PIPE_CONFIG(ADDR_SURF_P2) |
1676 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1677 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1678 break;
1679 case 17:
1680 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1681 break;
1682 case 18:
1683 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1684 PIPE_CONFIG(ADDR_SURF_P2) |
1685 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1686 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1687 break;
1688 case 19:
1689 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1690 PIPE_CONFIG(ADDR_SURF_P2) |
1691 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1692 break;
1693 case 20:
1694 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1695 PIPE_CONFIG(ADDR_SURF_P2) |
1696 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1697 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1698 break;
1699 case 21:
1700 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1701 PIPE_CONFIG(ADDR_SURF_P2) |
1702 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1703 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1704 break;
1705 case 22:
1706 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1707 PIPE_CONFIG(ADDR_SURF_P2) |
1708 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1709 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1710 break;
1711 case 23:
1712 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1713 break;
1714 case 24:
1715 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1716 PIPE_CONFIG(ADDR_SURF_P2) |
1717 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1718 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1719 break;
1720 case 25:
1721 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1722 PIPE_CONFIG(ADDR_SURF_P2) |
1723 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1724 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1725 break;
1726 case 26:
1727 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1728 PIPE_CONFIG(ADDR_SURF_P2) |
1729 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1730 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1731 break;
1732 case 27:
1733 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1734 PIPE_CONFIG(ADDR_SURF_P2) |
1735 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1736 break;
1737 case 28:
1738 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1739 PIPE_CONFIG(ADDR_SURF_P2) |
1740 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1741 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1742 break;
1743 case 29:
1744 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1745 PIPE_CONFIG(ADDR_SURF_P2) |
1746 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1747 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1748 break;
1749 case 30:
1750 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1751 break;
1752 default:
1753 gb_tile_moden = 0;
1754 break;
1755 }
1756 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1757 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1758 }
1759 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1760 switch (reg_offset) {
1761 case 0:
1762 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1763 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1764 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1765 NUM_BANKS(ADDR_SURF_8_BANK));
1766 break;
1767 case 1:
1768 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1769 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1770 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1771 NUM_BANKS(ADDR_SURF_8_BANK));
1772 break;
1773 case 2:
1774 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1775 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1776 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1777 NUM_BANKS(ADDR_SURF_8_BANK));
1778 break;
1779 case 3:
1780 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1781 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1782 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1783 NUM_BANKS(ADDR_SURF_8_BANK));
1784 break;
1785 case 4:
1786 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1787 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1788 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1789 NUM_BANKS(ADDR_SURF_8_BANK));
1790 break;
1791 case 5:
1792 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1793 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1794 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1795 NUM_BANKS(ADDR_SURF_8_BANK));
1796 break;
1797 case 6:
1798 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1801 NUM_BANKS(ADDR_SURF_8_BANK));
1802 break;
1803 case 8:
1804 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1805 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1806 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1807 NUM_BANKS(ADDR_SURF_16_BANK));
1808 break;
1809 case 9:
1810 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1811 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1812 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1813 NUM_BANKS(ADDR_SURF_16_BANK));
1814 break;
1815 case 10:
1816 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1817 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1818 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1819 NUM_BANKS(ADDR_SURF_16_BANK));
1820 break;
1821 case 11:
1822 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1825 NUM_BANKS(ADDR_SURF_16_BANK));
1826 break;
1827 case 12:
1828 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1829 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1830 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1831 NUM_BANKS(ADDR_SURF_16_BANK));
1832 break;
1833 case 13:
1834 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1835 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1836 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1837 NUM_BANKS(ADDR_SURF_16_BANK));
1838 break;
1839 case 14:
1840 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1843 NUM_BANKS(ADDR_SURF_8_BANK));
1844 break;
1845 default:
1846 gb_tile_moden = 0;
1847 break;
1848 }
1849 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1850 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1851 }
1852 break;
1853 }
1854}
1855
1856/**
1857 * gfx_v7_0_select_se_sh - select which SE, SH to address
1858 *
1859 * @adev: amdgpu_device pointer
1860 * @se_num: shader engine to address
1861 * @sh_num: sh block to address
1862 *
1863 * Select which SE, SH combinations to address. Certain
1864 * registers are instanced per SE or SH. 0xffffffff means
1865 * broadcast to all SEs or SHs (CIK).
1866 */
1867void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1868{
1869 u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
1870
1871 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1872 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1873 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1874 else if (se_num == 0xffffffff)
1875 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1876 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1877 else if (sh_num == 0xffffffff)
1878 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1879 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1880 else
1881 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1882 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1883 WREG32(mmGRBM_GFX_INDEX, data);
1884}
1885
1886/**
1887 * gfx_v7_0_create_bitmask - create a bitmask
1888 *
1889 * @bit_width: length of the mask
1890 *
1891 * create a variable length bit mask (CIK).
1892 * Returns the bitmask.
1893 */
1894static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1895{
1896 u32 i, mask = 0;
1897
1898 for (i = 0; i < bit_width; i++) {
1899 mask <<= 1;
1900 mask |= 1;
1901 }
1902 return mask;
1903}
1904
1905/**
1906 * gfx_v7_0_get_rb_disabled - computes the mask of disabled RBs
1907 *
1908 * @adev: amdgpu_device pointer
1909 * @max_rb_num: max RBs (render backends) for the asic
1910 * @se_num: number of SEs (shader engines) for the asic
1911 * @sh_per_se: number of SH blocks per SE for the asic
1912 *
1913 * Calculates the bitmask of disabled RBs (CIK).
1914 * Returns the disabled RB bitmask.
1915 */
1916static u32 gfx_v7_0_get_rb_disabled(struct amdgpu_device *adev,
1917 u32 max_rb_num_per_se,
1918 u32 sh_per_se)
1919{
1920 u32 data, mask;
1921
1922 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1923 if (data & 1)
1924 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1925 else
1926 data = 0;
1927
1928 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1929
1930 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1931
1932 mask = gfx_v7_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1933
1934 return data & mask;
1935}
1936
1937/**
1938 * gfx_v7_0_setup_rb - setup the RBs on the asic
1939 *
1940 * @adev: amdgpu_device pointer
1941 * @se_num: number of SEs (shader engines) for the asic
1942 * @sh_per_se: number of SH blocks per SE for the asic
1943 * @max_rb_num: max RBs (render backends) for the asic
1944 *
1945 * Configures per-SE/SH RB registers (CIK).
1946 */
1947static void gfx_v7_0_setup_rb(struct amdgpu_device *adev,
1948 u32 se_num, u32 sh_per_se,
1949 u32 max_rb_num_per_se)
1950{
1951 int i, j;
1952 u32 data, mask;
1953 u32 disabled_rbs = 0;
1954 u32 enabled_rbs = 0;
1955
1956 mutex_lock(&adev->grbm_idx_mutex);
1957 for (i = 0; i < se_num; i++) {
1958 for (j = 0; j < sh_per_se; j++) {
1959 gfx_v7_0_select_se_sh(adev, i, j);
1960 data = gfx_v7_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
1961 if (adev->asic_type == CHIP_HAWAII)
1962 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
1963 else
1964 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
1965 }
1966 }
1967 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1968 mutex_unlock(&adev->grbm_idx_mutex);
1969
1970 mask = 1;
1971 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1972 if (!(disabled_rbs & mask))
1973 enabled_rbs |= mask;
1974 mask <<= 1;
1975 }
1976
1977 adev->gfx.config.backend_enable_mask = enabled_rbs;
1978
1979 mutex_lock(&adev->grbm_idx_mutex);
1980 for (i = 0; i < se_num; i++) {
1981 gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
1982 data = 0;
1983 for (j = 0; j < sh_per_se; j++) {
1984 switch (enabled_rbs & 3) {
1985 case 0:
1986 if (j == 0)
1987 data |= (RASTER_CONFIG_RB_MAP_3 <<
1988 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1989 else
1990 data |= (RASTER_CONFIG_RB_MAP_0 <<
1991 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1992 break;
1993 case 1:
1994 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1995 break;
1996 case 2:
1997 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1998 break;
1999 case 3:
2000 default:
2001 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
2002 break;
2003 }
2004 enabled_rbs >>= 2;
2005 }
2006 WREG32(mmPA_SC_RASTER_CONFIG, data);
2007 }
2008 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2009 mutex_unlock(&adev->grbm_idx_mutex);
2010}
2011
cd06bf68
BG		 2012/**
2013 * gmc_v7_0_init_compute_vmid - gart enable
2014 *
2015 * @rdev: amdgpu_device pointer
2016 *
2017 * Initialize compute vmid sh_mem registers
2018 *
2019 */
2020#define DEFAULT_SH_MEM_BASES (0x6000)
2021#define FIRST_COMPUTE_VMID (8)
2022#define LAST_COMPUTE_VMID (16)
2023static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
2024{
2025 int i;
2026 uint32_t sh_mem_config;
2027 uint32_t sh_mem_bases;
2028
2029 /*
2030 * Configure apertures:
2031 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
2032 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
2033 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
2034 */
2035 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2036 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2037 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
2038 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
2039 mutex_lock(&adev->srbm_mutex);
2040 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2041 cik_srbm_select(adev, 0, 0, 0, i);
2042 /* CP and shaders */
2043 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2044 WREG32(mmSH_MEM_APE1_BASE, 1);
2045 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2046 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2047 }
2048 cik_srbm_select(adev, 0, 0, 0, 0);
2049 mutex_unlock(&adev->srbm_mutex);
2050}
2051
a2e73f56
AD		 2052/**
2053 * gfx_v7_0_gpu_init - setup the 3D engine
2054 *
2055 * @adev: amdgpu_device pointer
2056 *
2057 * Configures the 3D engine and tiling configuration
2058 * registers so that the 3D engine is usable.
2059 */
2060static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
2061{
2062 u32 gb_addr_config;
2063 u32 mc_shared_chmap, mc_arb_ramcfg;
2064 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
74a5d165 2065 u32 sh_mem_cfg;
a2e73f56
AD		 2066 u32 tmp;
2067 int i;
2068
2069 switch (adev->asic_type) {
2070 case CHIP_BONAIRE:
2071 adev->gfx.config.max_shader_engines = 2;
2072 adev->gfx.config.max_tile_pipes = 4;
2073 adev->gfx.config.max_cu_per_sh = 7;
2074 adev->gfx.config.max_sh_per_se = 1;
2075 adev->gfx.config.max_backends_per_se = 2;
2076 adev->gfx.config.max_texture_channel_caches = 4;
2077 adev->gfx.config.max_gprs = 256;
2078 adev->gfx.config.max_gs_threads = 32;
2079 adev->gfx.config.max_hw_contexts = 8;
2080
2081 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2082 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2083 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2084 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2085 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2086 break;
2087 case CHIP_HAWAII:
2088 adev->gfx.config.max_shader_engines = 4;
2089 adev->gfx.config.max_tile_pipes = 16;
2090 adev->gfx.config.max_cu_per_sh = 11;
2091 adev->gfx.config.max_sh_per_se = 1;
2092 adev->gfx.config.max_backends_per_se = 4;
2093 adev->gfx.config.max_texture_channel_caches = 16;
2094 adev->gfx.config.max_gprs = 256;
2095 adev->gfx.config.max_gs_threads = 32;
2096 adev->gfx.config.max_hw_contexts = 8;
2097
2098 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2099 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2100 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2101 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2102 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
2103 break;
2104 case CHIP_KAVERI:
2105 adev->gfx.config.max_shader_engines = 1;
2106 adev->gfx.config.max_tile_pipes = 4;
2107 if ((adev->pdev->device == 0x1304) ||
2108 (adev->pdev->device == 0x1305) ||
2109 (adev->pdev->device == 0x130C) ||
2110 (adev->pdev->device == 0x130F) ||
2111 (adev->pdev->device == 0x1310) ||
2112 (adev->pdev->device == 0x1311) ||
2113 (adev->pdev->device == 0x131C)) {
2114 adev->gfx.config.max_cu_per_sh = 8;
2115 adev->gfx.config.max_backends_per_se = 2;
2116 } else if ((adev->pdev->device == 0x1309) ||
2117 (adev->pdev->device == 0x130A) ||
2118 (adev->pdev->device == 0x130D) ||
2119 (adev->pdev->device == 0x1313) ||
2120 (adev->pdev->device == 0x131D)) {
2121 adev->gfx.config.max_cu_per_sh = 6;
2122 adev->gfx.config.max_backends_per_se = 2;
2123 } else if ((adev->pdev->device == 0x1306) ||
2124 (adev->pdev->device == 0x1307) ||
2125 (adev->pdev->device == 0x130B) ||
2126 (adev->pdev->device == 0x130E) ||
2127 (adev->pdev->device == 0x1315) ||
2128 (adev->pdev->device == 0x131B)) {
2129 adev->gfx.config.max_cu_per_sh = 4;
2130 adev->gfx.config.max_backends_per_se = 1;
2131 } else {
2132 adev->gfx.config.max_cu_per_sh = 3;
2133 adev->gfx.config.max_backends_per_se = 1;
2134 }
2135 adev->gfx.config.max_sh_per_se = 1;
2136 adev->gfx.config.max_texture_channel_caches = 4;
2137 adev->gfx.config.max_gprs = 256;
2138 adev->gfx.config.max_gs_threads = 16;
2139 adev->gfx.config.max_hw_contexts = 8;
2140
2141 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2142 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2143 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2144 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2145 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2146 break;
2147 case CHIP_KABINI:
2148 case CHIP_MULLINS:
2149 default:
2150 adev->gfx.config.max_shader_engines = 1;
2151 adev->gfx.config.max_tile_pipes = 2;
2152 adev->gfx.config.max_cu_per_sh = 2;
2153 adev->gfx.config.max_sh_per_se = 1;
2154 adev->gfx.config.max_backends_per_se = 1;
2155 adev->gfx.config.max_texture_channel_caches = 2;
2156 adev->gfx.config.max_gprs = 256;
2157 adev->gfx.config.max_gs_threads = 16;
2158 adev->gfx.config.max_hw_contexts = 8;
2159
2160 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2161 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2162 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2163 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2164 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2165 break;
2166 }
2167
2168 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
2169
2170 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2171 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2172 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2173
2174 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2175 adev->gfx.config.mem_max_burst_length_bytes = 256;
2f7d10b3 2176 if (adev->flags & AMD_IS_APU) {
a2e73f56
AD		 2177 /* Get memory bank mapping mode. */
2178 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2179 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2180 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2181
2182 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2183 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2184 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2185
2186 /* Validate settings in case only one DIMM installed. */
2187 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2188 dimm00_addr_map = 0;
2189 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2190 dimm01_addr_map = 0;
2191 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2192 dimm10_addr_map = 0;
2193 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2194 dimm11_addr_map = 0;
2195
2196 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2197 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2198 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2199 adev->gfx.config.mem_row_size_in_kb = 2;
2200 else
2201 adev->gfx.config.mem_row_size_in_kb = 1;
2202 } else {
2203 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
2204 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2205 if (adev->gfx.config.mem_row_size_in_kb > 4)
2206 adev->gfx.config.mem_row_size_in_kb = 4;
2207 }
2208 /* XXX use MC settings? */
2209 adev->gfx.config.shader_engine_tile_size = 32;
2210 adev->gfx.config.num_gpus = 1;
2211 adev->gfx.config.multi_gpu_tile_size = 64;
2212
2213 /* fix up row size */
2214 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
2215 switch (adev->gfx.config.mem_row_size_in_kb) {
2216 case 1:
2217 default:
2218 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
2219 break;
2220 case 2:
2221 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
2222 break;
2223 case 4:
2224 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
2225 break;
2226 }
2227 adev->gfx.config.gb_addr_config = gb_addr_config;
2228
2229 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2230 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2231 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2232 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
2233 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
2234 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2235 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2236 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2237
2238 gfx_v7_0_tiling_mode_table_init(adev);
2239
2240 gfx_v7_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2241 adev->gfx.config.max_sh_per_se,
2242 adev->gfx.config.max_backends_per_se);
2243
2244 /* set HW defaults for 3D engine */
2245 WREG32(mmCP_MEQ_THRESHOLDS,
2246 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
2247 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
2248
2249 mutex_lock(&adev->grbm_idx_mutex);
2250 /*
2251 * making sure that the following register writes will be broadcasted
2252 * to all the shaders
2253 */
2254 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2255
2256 /* XXX SH_MEM regs */
2257 /* where to put LDS, scratch, GPUVM in FSA64 space */
74a5d165
JX		 2258 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2259 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2260
a2e73f56
AD		 2261 mutex_lock(&adev->srbm_mutex);
2262 for (i = 0; i < 16; i++) {
2263 cik_srbm_select(adev, 0, 0, 0, i);
2264 /* CP and shaders */
74a5d165 2265 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
a2e73f56
AD		 2266 WREG32(mmSH_MEM_APE1_BASE, 1);
2267 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2268 WREG32(mmSH_MEM_BASES, 0);
2269 }
2270 cik_srbm_select(adev, 0, 0, 0, 0);
2271 mutex_unlock(&adev->srbm_mutex);
2272
cd06bf68
BG		 2273 gmc_v7_0_init_compute_vmid(adev);
2274
a2e73f56
AD		 2275 WREG32(mmSX_DEBUG_1, 0x20);
2276
2277 WREG32(mmTA_CNTL_AUX, 0x00010000);
2278
2279 tmp = RREG32(mmSPI_CONFIG_CNTL);
2280 tmp |= 0x03000000;
2281 WREG32(mmSPI_CONFIG_CNTL, tmp);
2282
2283 WREG32(mmSQ_CONFIG, 1);
2284
2285 WREG32(mmDB_DEBUG, 0);
2286
2287 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
2288 tmp |= 0x00000400;
2289 WREG32(mmDB_DEBUG2, tmp);
2290
2291 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
2292 tmp |= 0x00020200;
2293 WREG32(mmDB_DEBUG3, tmp);
2294
2295 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
2296 tmp |= 0x00018208;
2297 WREG32(mmCB_HW_CONTROL, tmp);
2298
2299 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
2300
2301 WREG32(mmPA_SC_FIFO_SIZE,
2302 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2303 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2304 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2305 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
2306
2307 WREG32(mmVGT_NUM_INSTANCES, 1);
2308
2309 WREG32(mmCP_PERFMON_CNTL, 0);
2310
2311 WREG32(mmSQ_CONFIG, 0);
2312
2313 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
2314 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
2315 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
2316
2317 WREG32(mmVGT_CACHE_INVALIDATION,
2318 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
2319 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2320
2321 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
2322 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2323
2324 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
2325 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2326 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
2327 mutex_unlock(&adev->grbm_idx_mutex);
2328
2329 udelay(50);
2330}
2331
2332/*
2333 * GPU scratch registers helpers function.
2334 */
2335/**
2336 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2337 *
2338 * @adev: amdgpu_device pointer
2339 *
2340 * Set up the number and offset of the CP scratch registers.
2341 * NOTE: use of CP scratch registers is a legacy inferface and
2342 * is not used by default on newer asics (r6xx+). On newer asics,
2343 * memory buffers are used for fences rather than scratch regs.
2344 */
2345static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2346{
2347 int i;
2348
2349 adev->gfx.scratch.num_reg = 7;
2350 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2351 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
2352 adev->gfx.scratch.free[i] = true;
2353 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
2354 }
2355}
2356
2357/**
2358 * gfx_v7_0_ring_test_ring - basic gfx ring test
2359 *
2360 * @adev: amdgpu_device pointer
2361 * @ring: amdgpu_ring structure holding ring information
2362 *
2363 * Allocate a scratch register and write to it using the gfx ring (CIK).
2364 * Provides a basic gfx ring test to verify that the ring is working.
2365 * Used by gfx_v7_0_cp_gfx_resume();
2366 * Returns 0 on success, error on failure.
2367 */
2368static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2369{
2370 struct amdgpu_device *adev = ring->adev;
2371 uint32_t scratch;
2372 uint32_t tmp = 0;
2373 unsigned i;
2374 int r;
2375
2376 r = amdgpu_gfx_scratch_get(adev, &scratch);
2377 if (r) {
2378 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2379 return r;
2380 }
2381 WREG32(scratch, 0xCAFEDEAD);
a27de35c 2382 r = amdgpu_ring_alloc(ring, 3);
a2e73f56
AD		 2383 if (r) {
2384 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2385 amdgpu_gfx_scratch_free(adev, scratch);
2386 return r;
2387 }
2388 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2389 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2390 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 2391 amdgpu_ring_commit(ring);
a2e73f56
AD		 2392
2393 for (i = 0; i < adev->usec_timeout; i++) {
2394 tmp = RREG32(scratch);
2395 if (tmp == 0xDEADBEEF)
2396 break;
2397 DRM_UDELAY(1);
2398 }
2399 if (i < adev->usec_timeout) {
2400 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2401 } else {
2402 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2403 ring->idx, scratch, tmp);
2404 r = -EINVAL;
2405 }
2406 amdgpu_gfx_scratch_free(adev, scratch);
2407 return r;
2408}
2409
2410/**
d2edb07b 2411 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
a2e73f56
AD		 2412 *
2413 * @adev: amdgpu_device pointer
2414 * @ridx: amdgpu ring index
2415 *
2416 * Emits an hdp flush on the cp.
2417 */
d2edb07b 2418static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 2419{
2420 u32 ref_and_mask;
d9b5327a 2421 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
a2e73f56
AD		 2422
2423 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
2424 switch (ring->me) {
2425 case 1:
2426 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2427 break;
2428 case 2:
2429 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2430 break;
2431 default:
2432 return;
2433 }
2434 } else {
2435 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2436 }
2437
2438 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2439 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2440 WAIT_REG_MEM_FUNCTION(3) | /* == */
d9b5327a 2441 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
a2e73f56
AD		 2442 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2443 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2444 amdgpu_ring_write(ring, ref_and_mask);
2445 amdgpu_ring_write(ring, ref_and_mask);
2446 amdgpu_ring_write(ring, 0x20); /* poll interval */
2447}
2448
2449/**
2450 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2451 *
2452 * @adev: amdgpu_device pointer
2453 * @fence: amdgpu fence object
2454 *
2455 * Emits a fence sequnce number on the gfx ring and flushes
2456 * GPU caches.
2457 */
2458static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 2459 u64 seq, unsigned flags)
a2e73f56 2460{
890ee23f
CZ		 2461 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2462 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
a2e73f56
AD		 2463 /* Workaround for cache flush problems. First send a dummy EOP
2464 * event down the pipe with seq one below.
2465 */
2466 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2467 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2468 EOP_TC_ACTION_EN |
2469 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2470 EVENT_INDEX(5)));
2471 amdgpu_ring_write(ring, addr & 0xfffffffc);
2472 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2473 DATA_SEL(1) | INT_SEL(0));
2474 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2475 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2476
2477 /* Then send the real EOP event down the pipe. */
2478 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2479 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2480 EOP_TC_ACTION_EN |
2481 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2482 EVENT_INDEX(5)));
2483 amdgpu_ring_write(ring, addr & 0xfffffffc);
2484 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 2485 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2486 amdgpu_ring_write(ring, lower_32_bits(seq));
2487 amdgpu_ring_write(ring, upper_32_bits(seq));
2488}
2489
2490/**
2491 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2492 *
2493 * @adev: amdgpu_device pointer
2494 * @fence: amdgpu fence object
2495 *
2496 * Emits a fence sequnce number on the compute ring and flushes
2497 * GPU caches.
2498 */
2499static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2500 u64 addr, u64 seq,
890ee23f 2501 unsigned flags)
a2e73f56 2502{
890ee23f
CZ		 2503 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2504 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2505
a2e73f56
AD		 2506 /* RELEASE_MEM - flush caches, send int */
2507 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2508 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2509 EOP_TC_ACTION_EN |
2510 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2511 EVENT_INDEX(5)));
890ee23f 2512 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2513 amdgpu_ring_write(ring, addr & 0xfffffffc);
2514 amdgpu_ring_write(ring, upper_32_bits(addr));
2515 amdgpu_ring_write(ring, lower_32_bits(seq));
2516 amdgpu_ring_write(ring, upper_32_bits(seq));
2517}
2518
a2e73f56
AD		 2519/*
2520 * IB stuff
2521 */
2522/**
2523 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2524 *
2525 * @ring: amdgpu_ring structure holding ring information
2526 * @ib: amdgpu indirect buffer object
2527 *
2528 * Emits an DE (drawing engine) or CE (constant engine) IB
2529 * on the gfx ring. IBs are usually generated by userspace
2530 * acceleration drivers and submitted to the kernel for
2531 * sheduling on the ring. This function schedules the IB
2532 * on the gfx ring for execution by the GPU.
2533 */
93323131 2534static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
a2e73f56
AD		 2535 struct amdgpu_ib *ib)
2536{
3cb485f3 2537 bool need_ctx_switch = ring->current_ctx != ib->ctx;
a2e73f56
AD		 2538 u32 header, control = 0;
2539 u32 next_rptr = ring->wptr + 5;
aa2bdb24
JZ		 2540
2541 /* drop the CE preamble IB for the same context */
93323131 2542 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
aa2bdb24
JZ		 2543 return;
2544
93323131 2545 if (need_ctx_switch)
a2e73f56
AD		 2546 next_rptr += 2;
2547
2548 next_rptr += 4;
2549 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2550 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2551 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2552 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2553 amdgpu_ring_write(ring, next_rptr);
2554
a2e73f56 2555 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
93323131 2556 if (need_ctx_switch) {
a2e73f56
AD		 2557 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2558 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 2559 }
2560
de807f81 2561 if (ib->flags & AMDGPU_IB_FLAG_CE)
a2e73f56
AD		 2562 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2563 else
2564 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2565
2566 control |= ib->length_dw |
2567 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
2568
2569 amdgpu_ring_write(ring, header);
2570 amdgpu_ring_write(ring,
2571#ifdef __BIG_ENDIAN
2572 (2 << 0) |
2573#endif
2574 (ib->gpu_addr & 0xFFFFFFFC));
2575 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2576 amdgpu_ring_write(ring, control);
2577}
2578
93323131 2579static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2580 struct amdgpu_ib *ib)
2581{
2582 u32 header, control = 0;
2583 u32 next_rptr = ring->wptr + 5;
2584
2585 control |= INDIRECT_BUFFER_VALID;
2586 next_rptr += 4;
2587 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2588 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2589 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2590 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2591 amdgpu_ring_write(ring, next_rptr);
2592
2593 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2594
2595 control |= ib->length_dw |
2596 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
2597
2598 amdgpu_ring_write(ring, header);
2599 amdgpu_ring_write(ring,
2600#ifdef __BIG_ENDIAN
2601 (2 << 0) |
2602#endif
2603 (ib->gpu_addr & 0xFFFFFFFC));
2604 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2605 amdgpu_ring_write(ring, control);
2606}
2607
a2e73f56
AD		 2608/**
2609 * gfx_v7_0_ring_test_ib - basic ring IB test
2610 *
2611 * @ring: amdgpu_ring structure holding ring information
2612 *
2613 * Allocate an IB and execute it on the gfx ring (CIK).
2614 * Provides a basic gfx ring test to verify that IBs are working.
2615 * Returns 0 on success, error on failure.
2616 */
2617static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2618{
2619 struct amdgpu_device *adev = ring->adev;
2620 struct amdgpu_ib ib;
1763552e 2621 struct fence *f = NULL;
a2e73f56
AD		 2622 uint32_t scratch;
2623 uint32_t tmp = 0;
2624 unsigned i;
2625 int r;
2626
2627 r = amdgpu_gfx_scratch_get(adev, &scratch);
2628 if (r) {
2629 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2630 return r;
2631 }
2632 WREG32(scratch, 0xCAFEDEAD);
b203dd95 2633 memset(&ib, 0, sizeof(ib));
b07c60c0 2634 r = amdgpu_ib_get(adev, NULL, 256, &ib);
a2e73f56
AD		 2635 if (r) {
2636 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
42d13693 2637 goto err1;
a2e73f56
AD		 2638 }
2639 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2640 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2641 ib.ptr[2] = 0xDEADBEEF;
2642 ib.length_dw = 3;
42d13693
CZ		 2643
2644 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
1763552e
CZ		 2645 AMDGPU_FENCE_OWNER_UNDEFINED,
2646 &f);
42d13693
CZ		 2647 if (r)
2648 goto err2;
2649
1763552e 2650 r = fence_wait(f, false);
a2e73f56
AD		 2651 if (r) {
2652 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
42d13693 2653 goto err2;
a2e73f56
AD		 2654 }
2655 for (i = 0; i < adev->usec_timeout; i++) {
2656 tmp = RREG32(scratch);
2657 if (tmp == 0xDEADBEEF)
2658 break;
2659 DRM_UDELAY(1);
2660 }
2661 if (i < adev->usec_timeout) {
2662 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
42d13693
CZ		 2663 ring->idx, i);
2664 goto err2;
a2e73f56
AD		 2665 } else {
2666 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2667 scratch, tmp);
2668 r = -EINVAL;
2669 }
42d13693
CZ		 2670
2671err2:
281b4223 2672 fence_put(f);
a2e73f56 2673 amdgpu_ib_free(adev, &ib);
42d13693
CZ		 2674err1:
2675 amdgpu_gfx_scratch_free(adev, scratch);
a2e73f56
AD		 2676 return r;
2677}
2678
2679/*
2680 * CP.
2681 * On CIK, gfx and compute now have independant command processors.
2682 *
2683 * GFX
2684 * Gfx consists of a single ring and can process both gfx jobs and
2685 * compute jobs. The gfx CP consists of three microengines (ME):
2686 * PFP - Pre-Fetch Parser
2687 * ME - Micro Engine
2688 * CE - Constant Engine
2689 * The PFP and ME make up what is considered the Drawing Engine (DE).
2690 * The CE is an asynchronous engine used for updating buffer desciptors
2691 * used by the DE so that they can be loaded into cache in parallel
2692 * while the DE is processing state update packets.
2693 *
2694 * Compute
2695 * The compute CP consists of two microengines (ME):
2696 * MEC1 - Compute MicroEngine 1
2697 * MEC2 - Compute MicroEngine 2
2698 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2699 * The queues are exposed to userspace and are programmed directly
2700 * by the compute runtime.
2701 */
2702/**
2703 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2704 *
2705 * @adev: amdgpu_device pointer
2706 * @enable: enable or disable the MEs
2707 *
2708 * Halts or unhalts the gfx MEs.
2709 */
2710static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2711{
2712 int i;
2713
2714 if (enable) {
2715 WREG32(mmCP_ME_CNTL, 0);
2716 } else {
2717 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2718 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2719 adev->gfx.gfx_ring[i].ready = false;
2720 }
2721 udelay(50);
2722}
2723
2724/**
2725 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2726 *
2727 * @adev: amdgpu_device pointer
2728 *
2729 * Loads the gfx PFP, ME, and CE ucode.
2730 * Returns 0 for success, -EINVAL if the ucode is not available.
2731 */
2732static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2733{
2734 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2735 const struct gfx_firmware_header_v1_0 *ce_hdr;
2736 const struct gfx_firmware_header_v1_0 *me_hdr;
2737 const __le32 *fw_data;
2738 unsigned i, fw_size;
2739
2740 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2741 return -EINVAL;
2742
2743 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2744 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2745 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2746
2747 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2748 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2749 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2750 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2751 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2752 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
02558a00
KW		 2753 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2754 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2755 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
a2e73f56
AD		 2756
2757 gfx_v7_0_cp_gfx_enable(adev, false);
2758
2759 /* PFP */
2760 fw_data = (const __le32 *)
2761 (adev->gfx.pfp_fw->data +
2762 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2763 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2764 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2765 for (i = 0; i < fw_size; i++)
2766 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2767 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2768
2769 /* CE */
2770 fw_data = (const __le32 *)
2771 (adev->gfx.ce_fw->data +
2772 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2773 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2774 WREG32(mmCP_CE_UCODE_ADDR, 0);
2775 for (i = 0; i < fw_size; i++)
2776 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2777 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2778
2779 /* ME */
2780 fw_data = (const __le32 *)
2781 (adev->gfx.me_fw->data +
2782 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2783 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2784 WREG32(mmCP_ME_RAM_WADDR, 0);
2785 for (i = 0; i < fw_size; i++)
2786 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2787 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2788
2789 return 0;
2790}
2791
2792/**
2793 * gfx_v7_0_cp_gfx_start - start the gfx ring
2794 *
2795 * @adev: amdgpu_device pointer
2796 *
2797 * Enables the ring and loads the clear state context and other
2798 * packets required to init the ring.
2799 * Returns 0 for success, error for failure.
2800 */
2801static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2802{
2803 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2804 const struct cs_section_def *sect = NULL;
2805 const struct cs_extent_def *ext = NULL;
2806 int r, i;
2807
2808 /* init the CP */
2809 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2810 WREG32(mmCP_ENDIAN_SWAP, 0);
2811 WREG32(mmCP_DEVICE_ID, 1);
2812
2813 gfx_v7_0_cp_gfx_enable(adev, true);
2814
a27de35c 2815 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
a2e73f56
AD		 2816 if (r) {
2817 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2818 return r;
2819 }
2820
2821 /* init the CE partitions. CE only used for gfx on CIK */
2822 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2823 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2824 amdgpu_ring_write(ring, 0x8000);
2825 amdgpu_ring_write(ring, 0x8000);
2826
2827 /* clear state buffer */
2828 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2829 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2830
2831 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2832 amdgpu_ring_write(ring, 0x80000000);
2833 amdgpu_ring_write(ring, 0x80000000);
2834
2835 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2836 for (ext = sect->section; ext->extent != NULL; ++ext) {
2837 if (sect->id == SECT_CONTEXT) {
2838 amdgpu_ring_write(ring,
2839 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2840 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2841 for (i = 0; i < ext->reg_count; i++)
2842 amdgpu_ring_write(ring, ext->extent[i]);
2843 }
2844 }
2845 }
2846
2847 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2848 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2849 switch (adev->asic_type) {
2850 case CHIP_BONAIRE:
2851 amdgpu_ring_write(ring, 0x16000012);
2852 amdgpu_ring_write(ring, 0x00000000);
2853 break;
2854 case CHIP_KAVERI:
2855 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2856 amdgpu_ring_write(ring, 0x00000000);
2857 break;
2858 case CHIP_KABINI:
2859 case CHIP_MULLINS:
2860 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2861 amdgpu_ring_write(ring, 0x00000000);
2862 break;
2863 case CHIP_HAWAII:
2864 amdgpu_ring_write(ring, 0x3a00161a);
2865 amdgpu_ring_write(ring, 0x0000002e);
2866 break;
2867 default:
2868 amdgpu_ring_write(ring, 0x00000000);
2869 amdgpu_ring_write(ring, 0x00000000);
2870 break;
2871 }
2872
2873 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2874 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2875
2876 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2877 amdgpu_ring_write(ring, 0);
2878
2879 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2880 amdgpu_ring_write(ring, 0x00000316);
2881 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2882 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2883
a27de35c 2884 amdgpu_ring_commit(ring);
a2e73f56
AD		 2885
2886 return 0;
2887}
2888
2889/**
2890 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2891 *
2892 * @adev: amdgpu_device pointer
2893 *
2894 * Program the location and size of the gfx ring buffer
2895 * and test it to make sure it's working.
2896 * Returns 0 for success, error for failure.
2897 */
2898static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2899{
2900 struct amdgpu_ring *ring;
2901 u32 tmp;
2902 u32 rb_bufsz;
2903 u64 rb_addr, rptr_addr;
2904 int r;
2905
2906 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2907 if (adev->asic_type != CHIP_HAWAII)
2908 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2909
2910 /* Set the write pointer delay */
2911 WREG32(mmCP_RB_WPTR_DELAY, 0);
2912
2913 /* set the RB to use vmid 0 */
2914 WREG32(mmCP_RB_VMID, 0);
2915
2916 WREG32(mmSCRATCH_ADDR, 0);
2917
2918 /* ring 0 - compute and gfx */
2919 /* Set ring buffer size */
2920 ring = &adev->gfx.gfx_ring[0];
2921 rb_bufsz = order_base_2(ring->ring_size / 8);
2922 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2923#ifdef __BIG_ENDIAN
454fc95e 2924 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
a2e73f56
AD		 2925#endif
2926 WREG32(mmCP_RB0_CNTL, tmp);
2927
2928 /* Initialize the ring buffer's read and write pointers */
2929 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2930 ring->wptr = 0;
2931 WREG32(mmCP_RB0_WPTR, ring->wptr);
2932
2933 /* set the wb address wether it's enabled or not */
2934 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2935 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2936 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2937
2938 /* scratch register shadowing is no longer supported */
2939 WREG32(mmSCRATCH_UMSK, 0);
2940
2941 mdelay(1);
2942 WREG32(mmCP_RB0_CNTL, tmp);
2943
2944 rb_addr = ring->gpu_addr >> 8;
2945 WREG32(mmCP_RB0_BASE, rb_addr);
2946 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2947
2948 /* start the ring */
2949 gfx_v7_0_cp_gfx_start(adev);
2950 ring->ready = true;
2951 r = amdgpu_ring_test_ring(ring);
2952 if (r) {
2953 ring->ready = false;
2954 return r;
2955 }
2956
2957 return 0;
2958}
2959
2960static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2961{
2962 u32 rptr;
2963
2964 rptr = ring->adev->wb.wb[ring->rptr_offs];
2965
2966 return rptr;
2967}
2968
2969static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2970{
2971 struct amdgpu_device *adev = ring->adev;
2972 u32 wptr;
2973
2974 wptr = RREG32(mmCP_RB0_WPTR);
2975
2976 return wptr;
2977}
2978
2979static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2980{
2981 struct amdgpu_device *adev = ring->adev;
2982
2983 WREG32(mmCP_RB0_WPTR, ring->wptr);
2984 (void)RREG32(mmCP_RB0_WPTR);
2985}
2986
2987static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2988{
2989 u32 rptr;
2990
2991 rptr = ring->adev->wb.wb[ring->rptr_offs];
2992
2993 return rptr;
2994}
2995
2996static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2997{
2998 u32 wptr;
2999
3000 /* XXX check if swapping is necessary on BE */
3001 wptr = ring->adev->wb.wb[ring->wptr_offs];
3002
3003 return wptr;
3004}
3005
3006static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3007{
3008 struct amdgpu_device *adev = ring->adev;
3009
3010 /* XXX check if swapping is necessary on BE */
3011 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3012 WDOORBELL32(ring->doorbell_index, ring->wptr);
3013}
3014
3015/**
3016 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
3017 *
3018 * @adev: amdgpu_device pointer
3019 * @enable: enable or disable the MEs
3020 *
3021 * Halts or unhalts the compute MEs.
3022 */
3023static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3024{
3025 int i;
3026
3027 if (enable) {
3028 WREG32(mmCP_MEC_CNTL, 0);
3029 } else {
3030 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
3031 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3032 adev->gfx.compute_ring[i].ready = false;
3033 }
3034 udelay(50);
3035}
3036
3037/**
3038 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
3039 *
3040 * @adev: amdgpu_device pointer
3041 *
3042 * Loads the compute MEC1&2 ucode.
3043 * Returns 0 for success, -EINVAL if the ucode is not available.
3044 */
3045static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3046{
3047 const struct gfx_firmware_header_v1_0 *mec_hdr;
3048 const __le32 *fw_data;
3049 unsigned i, fw_size;
3050
3051 if (!adev->gfx.mec_fw)
3052 return -EINVAL;
3053
3054 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3055 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3056 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
351643d7
JZ		 3057 adev->gfx.mec_feature_version = le32_to_cpu(
3058 mec_hdr->ucode_feature_version);
a2e73f56
AD		 3059
3060 gfx_v7_0_cp_compute_enable(adev, false);
3061
3062 /* MEC1 */
3063 fw_data = (const __le32 *)
3064 (adev->gfx.mec_fw->data +
3065 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3066 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
3067 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3068 for (i = 0; i < fw_size; i++)
3069 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
3070 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3071
3072 if (adev->asic_type == CHIP_KAVERI) {
3073 const struct gfx_firmware_header_v1_0 *mec2_hdr;
3074
3075 if (!adev->gfx.mec2_fw)
3076 return -EINVAL;
3077
3078 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3079 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
3080 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
351643d7
JZ		 3081 adev->gfx.mec2_feature_version = le32_to_cpu(
3082 mec2_hdr->ucode_feature_version);
a2e73f56
AD		 3083
3084 /* MEC2 */
3085 fw_data = (const __le32 *)
3086 (adev->gfx.mec2_fw->data +
3087 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
3088 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
3089 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3090 for (i = 0; i < fw_size; i++)
3091 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
3092 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3093 }
3094
3095 return 0;
3096}
3097
a2e73f56
AD		 3098/**
3099 * gfx_v7_0_cp_compute_fini - stop the compute queues
3100 *
3101 * @adev: amdgpu_device pointer
3102 *
3103 * Stop the compute queues and tear down the driver queue
3104 * info.
3105 */
3106static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
3107{
3108 int i, r;
3109
3110 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3111 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3112
3113 if (ring->mqd_obj) {
3114 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3115 if (unlikely(r != 0))
3116 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3117
3118 amdgpu_bo_unpin(ring->mqd_obj);
3119 amdgpu_bo_unreserve(ring->mqd_obj);
3120
3121 amdgpu_bo_unref(&ring->mqd_obj);
3122 ring->mqd_obj = NULL;
3123 }
3124 }
3125}
3126
3127static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
3128{
3129 int r;
3130
3131 if (adev->gfx.mec.hpd_eop_obj) {
3132 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
3133 if (unlikely(r != 0))
3134 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
3135 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
3136 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
3137
3138 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
3139 adev->gfx.mec.hpd_eop_obj = NULL;
3140 }
3141}
3142
3143#define MEC_HPD_SIZE 2048
3144
3145static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
3146{
3147 int r;
3148 u32 *hpd;
3149
3150 /*
3151 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
3152 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
3153 * Nonetheless, we assign only 1 pipe because all other pipes will
3154 * be handled by KFD
3155 */
3156 adev->gfx.mec.num_mec = 1;
3157 adev->gfx.mec.num_pipe = 1;
3158 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
3159
3160 if (adev->gfx.mec.hpd_eop_obj == NULL) {
3161 r = amdgpu_bo_create(adev,
3162 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
3163 PAGE_SIZE, true,
72d7668b 3164 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 3165 &adev->gfx.mec.hpd_eop_obj);
3166 if (r) {
3167 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
3168 return r;
3169 }
3170 }
3171
3172 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
3173 if (unlikely(r != 0)) {
3174 gfx_v7_0_mec_fini(adev);
3175 return r;
3176 }
3177 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
3178 &adev->gfx.mec.hpd_eop_gpu_addr);
3179 if (r) {
3180 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
3181 gfx_v7_0_mec_fini(adev);
3182 return r;
3183 }
3184 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
3185 if (r) {
3186 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
3187 gfx_v7_0_mec_fini(adev);
3188 return r;
3189 }
3190
3191 /* clear memory. Not sure if this is required or not */
3192 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
3193
3194 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
3195 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
3196
3197 return 0;
3198}
3199
3200struct hqd_registers
3201{
3202 u32 cp_mqd_base_addr;
3203 u32 cp_mqd_base_addr_hi;
3204 u32 cp_hqd_active;
3205 u32 cp_hqd_vmid;
3206 u32 cp_hqd_persistent_state;
3207 u32 cp_hqd_pipe_priority;
3208 u32 cp_hqd_queue_priority;
3209 u32 cp_hqd_quantum;
3210 u32 cp_hqd_pq_base;
3211 u32 cp_hqd_pq_base_hi;
3212 u32 cp_hqd_pq_rptr;
3213 u32 cp_hqd_pq_rptr_report_addr;
3214 u32 cp_hqd_pq_rptr_report_addr_hi;
3215 u32 cp_hqd_pq_wptr_poll_addr;
3216 u32 cp_hqd_pq_wptr_poll_addr_hi;
3217 u32 cp_hqd_pq_doorbell_control;
3218 u32 cp_hqd_pq_wptr;
3219 u32 cp_hqd_pq_control;
3220 u32 cp_hqd_ib_base_addr;
3221 u32 cp_hqd_ib_base_addr_hi;
3222 u32 cp_hqd_ib_rptr;
3223 u32 cp_hqd_ib_control;
3224 u32 cp_hqd_iq_timer;
3225 u32 cp_hqd_iq_rptr;
3226 u32 cp_hqd_dequeue_request;
3227 u32 cp_hqd_dma_offload;
3228 u32 cp_hqd_sema_cmd;
3229 u32 cp_hqd_msg_type;
3230 u32 cp_hqd_atomic0_preop_lo;
3231 u32 cp_hqd_atomic0_preop_hi;
3232 u32 cp_hqd_atomic1_preop_lo;
3233 u32 cp_hqd_atomic1_preop_hi;
3234 u32 cp_hqd_hq_scheduler0;
3235 u32 cp_hqd_hq_scheduler1;
3236 u32 cp_mqd_control;
3237};
3238
3239struct bonaire_mqd
3240{
3241 u32 header;
3242 u32 dispatch_initiator;
3243 u32 dimensions[3];
3244 u32 start_idx[3];
3245 u32 num_threads[3];
3246 u32 pipeline_stat_enable;
3247 u32 perf_counter_enable;
3248 u32 pgm[2];
3249 u32 tba[2];
3250 u32 tma[2];
3251 u32 pgm_rsrc[2];
3252 u32 vmid;
3253 u32 resource_limits;
3254 u32 static_thread_mgmt01[2];
3255 u32 tmp_ring_size;
3256 u32 static_thread_mgmt23[2];
3257 u32 restart[3];
3258 u32 thread_trace_enable;
3259 u32 reserved1;
3260 u32 user_data[16];
3261 u32 vgtcs_invoke_count[2];
3262 struct hqd_registers queue_state;
3263 u32 dequeue_cntr;
3264 u32 interrupt_queue[64];
3265};
3266
3267/**
3268 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3269 *
3270 * @adev: amdgpu_device pointer
3271 *
3272 * Program the compute queues and test them to make sure they
3273 * are working.
3274 * Returns 0 for success, error for failure.
3275 */
3276static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3277{
3278 int r, i, j;
3279 u32 tmp;
3280 bool use_doorbell = true;
3281 u64 hqd_gpu_addr;
3282 u64 mqd_gpu_addr;
3283 u64 eop_gpu_addr;
3284 u64 wb_gpu_addr;
3285 u32 *buf;
3286 struct bonaire_mqd *mqd;
3287
6e9821b2 3288 gfx_v7_0_cp_compute_enable(adev, true);
a2e73f56
AD		 3289
3290 /* fix up chicken bits */
3291 tmp = RREG32(mmCP_CPF_DEBUG);
3292 tmp |= (1 << 23);
3293 WREG32(mmCP_CPF_DEBUG, tmp);
3294
3295 /* init the pipes */
3296 mutex_lock(&adev->srbm_mutex);
3297 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3298 int me = (i < 4) ? 1 : 2;
3299 int pipe = (i < 4) ? i : (i - 4);
3300
3301 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
3302
3303 cik_srbm_select(adev, me, pipe, 0, 0);
3304
3305 /* write the EOP addr */
3306 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
3307 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
3308
3309 /* set the VMID assigned */
3310 WREG32(mmCP_HPD_EOP_VMID, 0);
3311
3312 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3313 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
3314 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
3315 tmp |= order_base_2(MEC_HPD_SIZE / 8);
3316 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
3317 }
3318 cik_srbm_select(adev, 0, 0, 0, 0);
3319 mutex_unlock(&adev->srbm_mutex);
3320
3321 /* init the queues. Just two for now. */
3322 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3323 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3324
3325 if (ring->mqd_obj == NULL) {
3326 r = amdgpu_bo_create(adev,
3327 sizeof(struct bonaire_mqd),
3328 PAGE_SIZE, true,
72d7668b 3329 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 3330 &ring->mqd_obj);
3331 if (r) {
3332 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3333 return r;
3334 }
3335 }
3336
3337 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3338 if (unlikely(r != 0)) {
3339 gfx_v7_0_cp_compute_fini(adev);
3340 return r;
3341 }
3342 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3343 &mqd_gpu_addr);
3344 if (r) {
3345 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3346 gfx_v7_0_cp_compute_fini(adev);
3347 return r;
3348 }
3349 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3350 if (r) {
3351 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3352 gfx_v7_0_cp_compute_fini(adev);
3353 return r;
3354 }
3355
3356 /* init the mqd struct */
3357 memset(buf, 0, sizeof(struct bonaire_mqd));
3358
3359 mqd = (struct bonaire_mqd *)buf;
3360 mqd->header = 0xC0310800;
3361 mqd->static_thread_mgmt01[0] = 0xffffffff;
3362 mqd->static_thread_mgmt01[1] = 0xffffffff;
3363 mqd->static_thread_mgmt23[0] = 0xffffffff;
3364 mqd->static_thread_mgmt23[1] = 0xffffffff;
3365
3366 mutex_lock(&adev->srbm_mutex);
3367 cik_srbm_select(adev, ring->me,
3368 ring->pipe,
3369 ring->queue, 0);
3370
3371 /* disable wptr polling */
3372 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3373 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
3374 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3375
3376 /* enable doorbell? */
3377 mqd->queue_state.cp_hqd_pq_doorbell_control =
3378 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3379 if (use_doorbell)
3380 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3381 else
3382 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3383 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3384 mqd->queue_state.cp_hqd_pq_doorbell_control);
3385
3386 /* disable the queue if it's active */
3387 mqd->queue_state.cp_hqd_dequeue_request = 0;
3388 mqd->queue_state.cp_hqd_pq_rptr = 0;
3389 mqd->queue_state.cp_hqd_pq_wptr= 0;
3390 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3391 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3392 for (j = 0; j < adev->usec_timeout; j++) {
3393 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3394 break;
3395 udelay(1);
3396 }
3397 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
3398 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
3399 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3400 }
3401
3402 /* set the pointer to the MQD */
3403 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
3404 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3405 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
3406 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
3407 /* set MQD vmid to 0 */
3408 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
3409 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
3410 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
3411
3412 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3413 hqd_gpu_addr = ring->gpu_addr >> 8;
3414 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
3415 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3416 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
3417 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
3418
3419 /* set up the HQD, this is similar to CP_RB0_CNTL */
3420 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
3421 mqd->queue_state.cp_hqd_pq_control &=
3422 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
3423 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
3424
3425 mqd->queue_state.cp_hqd_pq_control |=
3426 order_base_2(ring->ring_size / 8);
3427 mqd->queue_state.cp_hqd_pq_control |=
3428 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
3429#ifdef __BIG_ENDIAN
454fc95e
AD		 3430 mqd->queue_state.cp_hqd_pq_control |=
3431 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
a2e73f56
AD		 3432#endif
3433 mqd->queue_state.cp_hqd_pq_control &=
3434 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
3435 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
3436 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
3437 mqd->queue_state.cp_hqd_pq_control |=
3438 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
3439 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
3440 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
3441
3442 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3443 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3444 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3445 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3446 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
3447 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3448 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
3449
3450 /* set the wb address wether it's enabled or not */
3451 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3452 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
3453 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
3454 upper_32_bits(wb_gpu_addr) & 0xffff;
3455 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3456 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
3457 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3458 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
3459
3460 /* enable the doorbell if requested */
3461 if (use_doorbell) {
3462 mqd->queue_state.cp_hqd_pq_doorbell_control =
3463 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3464 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3465 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
3466 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3467 (ring->doorbell_index <<
3468 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
3469 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3470 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3471 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3472 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3473 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3474
3475 } else {
3476 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
3477 }
3478 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3479 mqd->queue_state.cp_hqd_pq_doorbell_control);
3480
3481 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3482 ring->wptr = 0;
3483 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
3484 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3485 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3486
3487 /* set the vmid for the queue */
3488 mqd->queue_state.cp_hqd_vmid = 0;
3489 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
3490
3491 /* activate the queue */
3492 mqd->queue_state.cp_hqd_active = 1;
3493 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
3494
3495 cik_srbm_select(adev, 0, 0, 0, 0);
3496 mutex_unlock(&adev->srbm_mutex);
3497
3498 amdgpu_bo_kunmap(ring->mqd_obj);
3499 amdgpu_bo_unreserve(ring->mqd_obj);
3500
3501 ring->ready = true;
3502 r = amdgpu_ring_test_ring(ring);
3503 if (r)
3504 ring->ready = false;
3505 }
3506
3507 return 0;
3508}
3509
3510static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3511{
3512 gfx_v7_0_cp_gfx_enable(adev, enable);
3513 gfx_v7_0_cp_compute_enable(adev, enable);
3514}
3515
3516static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3517{
3518 int r;
3519
3520 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3521 if (r)
3522 return r;
3523 r = gfx_v7_0_cp_compute_load_microcode(adev);
3524 if (r)
3525 return r;
3526
3527 return 0;
3528}
3529
3530static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3531 bool enable)
3532{
3533 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3534
3535 if (enable)
3536 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3537 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3538 else
3539 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3540 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3541 WREG32(mmCP_INT_CNTL_RING0, tmp);
3542}
3543
3544static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3545{
3546 int r;
3547
3548 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3549
3550 r = gfx_v7_0_cp_load_microcode(adev);
3551 if (r)
3552 return r;
3553
3554 r = gfx_v7_0_cp_gfx_resume(adev);
3555 if (r)
3556 return r;
3557 r = gfx_v7_0_cp_compute_resume(adev);
3558 if (r)
3559 return r;
3560
3561 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3562
3563 return 0;
3564}
3565
a2e73f56
AD		 3566/*
3567 * vm
3568 * VMID 0 is the physical GPU addresses as used by the kernel.
3569 * VMIDs 1-15 are used for userspace clients and are handled
3570 * by the amdgpu vm/hsa code.
3571 */
3572/**
3573 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3574 *
3575 * @adev: amdgpu_device pointer
3576 *
3577 * Update the page table base and flush the VM TLB
3578 * using the CP (CIK).
3579 */
3580static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3581 unsigned vm_id, uint64_t pd_addr)
3582{
3583 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
5c3422b0 3584 if (usepfp) {
3585 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3586 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3587 amdgpu_ring_write(ring, 0);
3588 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3589 amdgpu_ring_write(ring, 0);
3590 }
a2e73f56
AD		 3591
3592 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3593 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3594 WRITE_DATA_DST_SEL(0)));
3595 if (vm_id < 8) {
3596 amdgpu_ring_write(ring,
3597 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3598 } else {
3599 amdgpu_ring_write(ring,
3600 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3601 }
3602 amdgpu_ring_write(ring, 0);
3603 amdgpu_ring_write(ring, pd_addr >> 12);
3604
a2e73f56
AD		 3605 /* bits 0-15 are the VM contexts0-15 */
3606 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3607 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3608 WRITE_DATA_DST_SEL(0)));
3609 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3610 amdgpu_ring_write(ring, 0);
3611 amdgpu_ring_write(ring, 1 << vm_id);
3612
3613 /* wait for the invalidate to complete */
3614 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3615 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3616 WAIT_REG_MEM_FUNCTION(0) | /* always */
3617 WAIT_REG_MEM_ENGINE(0))); /* me */
3618 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3619 amdgpu_ring_write(ring, 0);
3620 amdgpu_ring_write(ring, 0); /* ref */
3621 amdgpu_ring_write(ring, 0); /* mask */
3622 amdgpu_ring_write(ring, 0x20); /* poll interval */
3623
3624 /* compute doesn't have PFP */
3625 if (usepfp) {
3626 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3627 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3628 amdgpu_ring_write(ring, 0x0);
3629
3630 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
5c3422b0 3631 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3632 amdgpu_ring_write(ring, 0);
3633 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3634 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 3635 }
3636}
3637
3638/*
3639 * RLC
3640 * The RLC is a multi-purpose microengine that handles a
3641 * variety of functions.
3642 */
3643static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3644{
3645 int r;
3646
3647 /* save restore block */
3648 if (adev->gfx.rlc.save_restore_obj) {
3649 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3650 if (unlikely(r != 0))
3651 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3652 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3653 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3654
3655 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3656 adev->gfx.rlc.save_restore_obj = NULL;
3657 }
3658
3659 /* clear state block */
3660 if (adev->gfx.rlc.clear_state_obj) {
3661 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3662 if (unlikely(r != 0))
3663 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3664 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3665 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3666
3667 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3668 adev->gfx.rlc.clear_state_obj = NULL;
3669 }
3670
3671 /* clear state block */
3672 if (adev->gfx.rlc.cp_table_obj) {
3673 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3674 if (unlikely(r != 0))
3675 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3676 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3677 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3678
3679 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3680 adev->gfx.rlc.cp_table_obj = NULL;
3681 }
3682}
3683
3684static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3685{
3686 const u32 *src_ptr;
3687 volatile u32 *dst_ptr;
3688 u32 dws, i;
3689 const struct cs_section_def *cs_data;
3690 int r;
3691
3692 /* allocate rlc buffers */
2f7d10b3 3693 if (adev->flags & AMD_IS_APU) {
a2e73f56
AD		 3694 if (adev->asic_type == CHIP_KAVERI) {
3695 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3696 adev->gfx.rlc.reg_list_size =
3697 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3698 } else {
3699 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3700 adev->gfx.rlc.reg_list_size =
3701 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3702 }
3703 }
3704 adev->gfx.rlc.cs_data = ci_cs_data;
3705 adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
3706
3707 src_ptr = adev->gfx.rlc.reg_list;
3708 dws = adev->gfx.rlc.reg_list_size;
3709 dws += (5 * 16) + 48 + 48 + 64;
3710
3711 cs_data = adev->gfx.rlc.cs_data;
3712
3713 if (src_ptr) {
3714 /* save restore block */
3715 if (adev->gfx.rlc.save_restore_obj == NULL) {
3716 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3717 AMDGPU_GEM_DOMAIN_VRAM,
3718 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3719 NULL, NULL,
3720 &adev->gfx.rlc.save_restore_obj);
a2e73f56
AD		 3721 if (r) {
3722 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3723 return r;
3724 }
3725 }
3726
3727 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3728 if (unlikely(r != 0)) {
3729 gfx_v7_0_rlc_fini(adev);
3730 return r;
3731 }
3732 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3733 &adev->gfx.rlc.save_restore_gpu_addr);
3734 if (r) {
3735 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3736 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3737 gfx_v7_0_rlc_fini(adev);
3738 return r;
3739 }
3740
3741 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3742 if (r) {
3743 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3744 gfx_v7_0_rlc_fini(adev);
3745 return r;
3746 }
3747 /* write the sr buffer */
3748 dst_ptr = adev->gfx.rlc.sr_ptr;
3749 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3750 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3751 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3752 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3753 }
3754
3755 if (cs_data) {
3756 /* clear state block */
3757 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3758
3759 if (adev->gfx.rlc.clear_state_obj == NULL) {
3760 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3761 AMDGPU_GEM_DOMAIN_VRAM,
3762 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3763 NULL, NULL,
3764 &adev->gfx.rlc.clear_state_obj);
a2e73f56
AD		 3765 if (r) {
3766 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3767 gfx_v7_0_rlc_fini(adev);
3768 return r;
3769 }
3770 }
3771 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3772 if (unlikely(r != 0)) {
3773 gfx_v7_0_rlc_fini(adev);
3774 return r;
3775 }
3776 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3777 &adev->gfx.rlc.clear_state_gpu_addr);
3778 if (r) {
3779 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3780 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3781 gfx_v7_0_rlc_fini(adev);
3782 return r;
3783 }
3784
3785 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3786 if (r) {
3787 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3788 gfx_v7_0_rlc_fini(adev);
3789 return r;
3790 }
3791 /* set up the cs buffer */
3792 dst_ptr = adev->gfx.rlc.cs_ptr;
3793 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3794 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3795 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3796 }
3797
3798 if (adev->gfx.rlc.cp_table_size) {
3799 if (adev->gfx.rlc.cp_table_obj == NULL) {
3800 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
857d913d
AD		 3801 AMDGPU_GEM_DOMAIN_VRAM,
3802 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3803 NULL, NULL,
3804 &adev->gfx.rlc.cp_table_obj);
a2e73f56
AD		 3805 if (r) {
3806 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3807 gfx_v7_0_rlc_fini(adev);
3808 return r;
3809 }
3810 }
3811
3812 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3813 if (unlikely(r != 0)) {
3814 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3815 gfx_v7_0_rlc_fini(adev);
3816 return r;
3817 }
3818 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3819 &adev->gfx.rlc.cp_table_gpu_addr);
3820 if (r) {
3821 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3822 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3823 gfx_v7_0_rlc_fini(adev);
3824 return r;
3825 }
3826 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3827 if (r) {
3828 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3829 gfx_v7_0_rlc_fini(adev);
3830 return r;
3831 }
3832
3833 gfx_v7_0_init_cp_pg_table(adev);
3834
3835 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3836 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3837
3838 }
3839
3840 return 0;
3841}
3842
3843static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3844{
3845 u32 tmp;
3846
3847 tmp = RREG32(mmRLC_LB_CNTL);
3848 if (enable)
3849 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3850 else
3851 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3852 WREG32(mmRLC_LB_CNTL, tmp);
3853}
3854
3855static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3856{
3857 u32 i, j, k;
3858 u32 mask;
3859
3860 mutex_lock(&adev->grbm_idx_mutex);
3861 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3862 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3863 gfx_v7_0_select_se_sh(adev, i, j);
3864 for (k = 0; k < adev->usec_timeout; k++) {
3865 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3866 break;
3867 udelay(1);
3868 }
3869 }
3870 }
3871 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3872 mutex_unlock(&adev->grbm_idx_mutex);
3873
3874 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3875 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3876 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3877 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3878 for (k = 0; k < adev->usec_timeout; k++) {
3879 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3880 break;
3881 udelay(1);
3882 }
3883}
3884
3885static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3886{
3887 u32 tmp;
3888
3889 tmp = RREG32(mmRLC_CNTL);
3890 if (tmp != rlc)
3891 WREG32(mmRLC_CNTL, rlc);
3892}
3893
3894static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3895{
3896 u32 data, orig;
3897
3898 orig = data = RREG32(mmRLC_CNTL);
3899
3900 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3901 u32 i;
3902
3903 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3904 WREG32(mmRLC_CNTL, data);
3905
3906 for (i = 0; i < adev->usec_timeout; i++) {
3907 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3908 break;
3909 udelay(1);
3910 }
3911
3912 gfx_v7_0_wait_for_rlc_serdes(adev);
3913 }
3914
3915 return orig;
3916}
3917
3918void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3919{
3920 u32 tmp, i, mask;
3921
3922 tmp = 0x1 | (1 << 1);
3923 WREG32(mmRLC_GPR_REG2, tmp);
3924
3925 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3926 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3927 for (i = 0; i < adev->usec_timeout; i++) {
3928 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3929 break;
3930 udelay(1);
3931 }
3932
3933 for (i = 0; i < adev->usec_timeout; i++) {
3934 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3935 break;
3936 udelay(1);
3937 }
3938}
3939
3940void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3941{
3942 u32 tmp;
3943
3944 tmp = 0x1 | (0 << 1);
3945 WREG32(mmRLC_GPR_REG2, tmp);
3946}
3947
3948/**
3949 * gfx_v7_0_rlc_stop - stop the RLC ME
3950 *
3951 * @adev: amdgpu_device pointer
3952 *
3953 * Halt the RLC ME (MicroEngine) (CIK).
3954 */
3955void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3956{
3957 WREG32(mmRLC_CNTL, 0);
3958
3959 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3960
3961 gfx_v7_0_wait_for_rlc_serdes(adev);
3962}
3963
3964/**
3965 * gfx_v7_0_rlc_start - start the RLC ME
3966 *
3967 * @adev: amdgpu_device pointer
3968 *
3969 * Unhalt the RLC ME (MicroEngine) (CIK).
3970 */
3971static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3972{
3973 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3974
3975 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3976
3977 udelay(50);
3978}
3979
3980static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3981{
3982 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3983
3984 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3985 WREG32(mmGRBM_SOFT_RESET, tmp);
3986 udelay(50);
3987 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3988 WREG32(mmGRBM_SOFT_RESET, tmp);
3989 udelay(50);
3990}
3991
3992/**
3993 * gfx_v7_0_rlc_resume - setup the RLC hw
3994 *
3995 * @adev: amdgpu_device pointer
3996 *
3997 * Initialize the RLC registers, load the ucode,
3998 * and start the RLC (CIK).
3999 * Returns 0 for success, -EINVAL if the ucode is not available.
4000 */
4001static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
4002{
4003 const struct rlc_firmware_header_v1_0 *hdr;
4004 const __le32 *fw_data;
4005 unsigned i, fw_size;
4006 u32 tmp;
4007
4008 if (!adev->gfx.rlc_fw)
4009 return -EINVAL;
4010
4011 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
4012 amdgpu_ucode_print_rlc_hdr(&hdr->header);
4013 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
351643d7
JZ		 4014 adev->gfx.rlc_feature_version = le32_to_cpu(
4015 hdr->ucode_feature_version);
a2e73f56
AD		 4016
4017 gfx_v7_0_rlc_stop(adev);
4018
4019 /* disable CG */
4020 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
4021 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
4022
4023 gfx_v7_0_rlc_reset(adev);
4024
4025 gfx_v7_0_init_pg(adev);
4026
4027 WREG32(mmRLC_LB_CNTR_INIT, 0);
4028 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
4029
4030 mutex_lock(&adev->grbm_idx_mutex);
4031 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4032 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
4033 WREG32(mmRLC_LB_PARAMS, 0x00600408);
4034 WREG32(mmRLC_LB_CNTL, 0x80000004);
4035 mutex_unlock(&adev->grbm_idx_mutex);
4036
4037 WREG32(mmRLC_MC_CNTL, 0);
4038 WREG32(mmRLC_UCODE_CNTL, 0);
4039
4040 fw_data = (const __le32 *)
4041 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4042 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4043 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
4044 for (i = 0; i < fw_size; i++)
4045 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
4046 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4047
4048 /* XXX - find out what chips support lbpw */
4049 gfx_v7_0_enable_lbpw(adev, false);
4050
4051 if (adev->asic_type == CHIP_BONAIRE)
4052 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
4053
4054 gfx_v7_0_rlc_start(adev);
4055
4056 return 0;
4057}
4058
4059static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
4060{
4061 u32 data, orig, tmp, tmp2;
4062
4063 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
4064
4065 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) {
4066 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4067
4068 tmp = gfx_v7_0_halt_rlc(adev);
4069
4070 mutex_lock(&adev->grbm_idx_mutex);
4071 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4072 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4073 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4074 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
4075 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
4076 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
4077 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
4078 mutex_unlock(&adev->grbm_idx_mutex);
4079
4080 gfx_v7_0_update_rlc(adev, tmp);
4081
4082 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4083 } else {
4084 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4085
4086 RREG32(mmCB_CGTT_SCLK_CTRL);
4087 RREG32(mmCB_CGTT_SCLK_CTRL);
4088 RREG32(mmCB_CGTT_SCLK_CTRL);
4089 RREG32(mmCB_CGTT_SCLK_CTRL);
4090
4091 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4092 }
4093
4094 if (orig != data)
4095 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
4096
4097}
4098
4099static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
4100{
4101 u32 data, orig, tmp = 0;
4102
4103 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) {
4104 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) {
4105 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) {
4106 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
4107 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4108 if (orig != data)
4109 WREG32(mmCP_MEM_SLP_CNTL, data);
4110 }
4111 }
4112
4113 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4114 data |= 0x00000001;
4115 data &= 0xfffffffd;
4116 if (orig != data)
4117 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
4118
4119 tmp = gfx_v7_0_halt_rlc(adev);
4120
4121 mutex_lock(&adev->grbm_idx_mutex);
4122 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4123 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4124 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4125 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
4126 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
4127 WREG32(mmRLC_SERDES_WR_CTRL, data);
4128 mutex_unlock(&adev->grbm_idx_mutex);
4129
4130 gfx_v7_0_update_rlc(adev, tmp);
4131
4132 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) {
4133 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
4134 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
4135 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
4136 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
4137 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
4138 if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) &&
4139 (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS))
4140 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
4141 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
4142 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
4143 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
4144 if (orig != data)
4145 WREG32(mmCGTS_SM_CTRL_REG, data);
4146 }
4147 } else {
4148 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4149 data |= 0x00000003;
4150 if (orig != data)
4151 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
4152
4153 data = RREG32(mmRLC_MEM_SLP_CNTL);
4154 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4155 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4156 WREG32(mmRLC_MEM_SLP_CNTL, data);
4157 }
4158
4159 data = RREG32(mmCP_MEM_SLP_CNTL);
4160 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4161 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4162 WREG32(mmCP_MEM_SLP_CNTL, data);
4163 }
4164
4165 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
4166 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
4167 if (orig != data)
4168 WREG32(mmCGTS_SM_CTRL_REG, data);
4169
4170 tmp = gfx_v7_0_halt_rlc(adev);
4171
4172 mutex_lock(&adev->grbm_idx_mutex);
4173 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4174 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4175 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4176 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
4177 WREG32(mmRLC_SERDES_WR_CTRL, data);
4178 mutex_unlock(&adev->grbm_idx_mutex);
4179
4180 gfx_v7_0_update_rlc(adev, tmp);
4181 }
4182}
4183
4184static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
4185 bool enable)
4186{
4187 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4188 /* order matters! */
4189 if (enable) {
4190 gfx_v7_0_enable_mgcg(adev, true);
4191 gfx_v7_0_enable_cgcg(adev, true);
4192 } else {
4193 gfx_v7_0_enable_cgcg(adev, false);
4194 gfx_v7_0_enable_mgcg(adev, false);
4195 }
4196 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4197}
4198
4199static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
4200 bool enable)
4201{
4202 u32 data, orig;
4203
4204 orig = data = RREG32(mmRLC_PG_CNTL);
4205 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
4206 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
4207 else
4208 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
4209 if (orig != data)
4210 WREG32(mmRLC_PG_CNTL, data);
4211}
4212
4213static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
4214 bool enable)
4215{
4216 u32 data, orig;
4217
4218 orig = data = RREG32(mmRLC_PG_CNTL);
4219 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
4220 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
4221 else
4222 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
4223 if (orig != data)
4224 WREG32(mmRLC_PG_CNTL, data);
4225}
4226
4227static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
4228{
4229 u32 data, orig;
4230
4231 orig = data = RREG32(mmRLC_PG_CNTL);
4232 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP))
4233 data &= ~0x8000;
4234 else
4235 data |= 0x8000;
4236 if (orig != data)
4237 WREG32(mmRLC_PG_CNTL, data);
4238}
4239
4240static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
4241{
4242 u32 data, orig;
4243
4244 orig = data = RREG32(mmRLC_PG_CNTL);
4245 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS))
4246 data &= ~0x2000;
4247 else
4248 data |= 0x2000;
4249 if (orig != data)
4250 WREG32(mmRLC_PG_CNTL, data);
4251}
4252
4253static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
4254{
4255 const __le32 *fw_data;
4256 volatile u32 *dst_ptr;
4257 int me, i, max_me = 4;
4258 u32 bo_offset = 0;
4259 u32 table_offset, table_size;
4260
4261 if (adev->asic_type == CHIP_KAVERI)
4262 max_me = 5;
4263
4264 if (adev->gfx.rlc.cp_table_ptr == NULL)
4265 return;
4266
4267 /* write the cp table buffer */
4268 dst_ptr = adev->gfx.rlc.cp_table_ptr;
4269 for (me = 0; me < max_me; me++) {
4270 if (me == 0) {
4271 const struct gfx_firmware_header_v1_0 *hdr =
4272 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4273 fw_data = (const __le32 *)
4274 (adev->gfx.ce_fw->data +
4275 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4276 table_offset = le32_to_cpu(hdr->jt_offset);
4277 table_size = le32_to_cpu(hdr->jt_size);
4278 } else if (me == 1) {
4279 const struct gfx_firmware_header_v1_0 *hdr =
4280 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4281 fw_data = (const __le32 *)
4282 (adev->gfx.pfp_fw->data +
4283 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4284 table_offset = le32_to_cpu(hdr->jt_offset);
4285 table_size = le32_to_cpu(hdr->jt_size);
4286 } else if (me == 2) {
4287 const struct gfx_firmware_header_v1_0 *hdr =
4288 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4289 fw_data = (const __le32 *)
4290 (adev->gfx.me_fw->data +
4291 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4292 table_offset = le32_to_cpu(hdr->jt_offset);
4293 table_size = le32_to_cpu(hdr->jt_size);
4294 } else if (me == 3) {
4295 const struct gfx_firmware_header_v1_0 *hdr =
4296 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4297 fw_data = (const __le32 *)
4298 (adev->gfx.mec_fw->data +
4299 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4300 table_offset = le32_to_cpu(hdr->jt_offset);
4301 table_size = le32_to_cpu(hdr->jt_size);
4302 } else {
4303 const struct gfx_firmware_header_v1_0 *hdr =
4304 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4305 fw_data = (const __le32 *)
4306 (adev->gfx.mec2_fw->data +
4307 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4308 table_offset = le32_to_cpu(hdr->jt_offset);
4309 table_size = le32_to_cpu(hdr->jt_size);
4310 }
4311
4312 for (i = 0; i < table_size; i ++) {
4313 dst_ptr[bo_offset + i] =
4314 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
4315 }
4316
4317 bo_offset += table_size;
4318 }
4319}
4320
4321static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
4322 bool enable)
4323{
4324 u32 data, orig;
4325
4326 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) {
4327 orig = data = RREG32(mmRLC_PG_CNTL);
4328 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4329 if (orig != data)
4330 WREG32(mmRLC_PG_CNTL, data);
4331
4332 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4333 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4334 if (orig != data)
4335 WREG32(mmRLC_AUTO_PG_CTRL, data);
4336 } else {
4337 orig = data = RREG32(mmRLC_PG_CNTL);
4338 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4339 if (orig != data)
4340 WREG32(mmRLC_PG_CNTL, data);
4341
4342 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4343 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4344 if (orig != data)
4345 WREG32(mmRLC_AUTO_PG_CTRL, data);
4346
4347 data = RREG32(mmDB_RENDER_CONTROL);
4348 }
4349}
4350
4351static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4352 u32 se, u32 sh)
4353{
4354 u32 mask = 0, tmp, tmp1;
4355 int i;
4356
4357 gfx_v7_0_select_se_sh(adev, se, sh);
4358 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4359 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4360 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4361
4362 tmp &= 0xffff0000;
4363
4364 tmp |= tmp1;
4365 tmp >>= 16;
4366
4367 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4368 mask <<= 1;
4369 mask |= 1;
4370 }
4371
4372 return (~tmp) & mask;
4373}
4374
4375static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
4376{
4377 uint32_t tmp, active_cu_number;
4378 struct amdgpu_cu_info cu_info;
4379
4380 gfx_v7_0_get_cu_info(adev, &cu_info);
4381 tmp = cu_info.ao_cu_mask;
4382 active_cu_number = cu_info.number;
4383
4384 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp);
4385
4386 tmp = RREG32(mmRLC_MAX_PG_CU);
4387 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
4388 tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
4389 WREG32(mmRLC_MAX_PG_CU, tmp);
4390}
4391
4392static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
4393 bool enable)
4394{
4395 u32 data, orig;
4396
4397 orig = data = RREG32(mmRLC_PG_CNTL);
4398 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG))
4399 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4400 else
4401 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4402 if (orig != data)
4403 WREG32(mmRLC_PG_CNTL, data);
4404}
4405
4406static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
4407 bool enable)
4408{
4409 u32 data, orig;
4410
4411 orig = data = RREG32(mmRLC_PG_CNTL);
4412 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG))
4413 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4414 else
4415 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4416 if (orig != data)
4417 WREG32(mmRLC_PG_CNTL, data);
4418}
4419
4420#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4421#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
4422
4423static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
4424{
4425 u32 data, orig;
4426 u32 i;
4427
4428 if (adev->gfx.rlc.cs_data) {
4429 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4430 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4431 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4432 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
4433 } else {
4434 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4435 for (i = 0; i < 3; i++)
4436 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
4437 }
4438 if (adev->gfx.rlc.reg_list) {
4439 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4440 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4441 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4442 }
4443
4444 orig = data = RREG32(mmRLC_PG_CNTL);
4445 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4446 if (orig != data)
4447 WREG32(mmRLC_PG_CNTL, data);
4448
4449 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4450 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4451
4452 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4453 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4454 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4455 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4456
4457 data = 0x10101010;
4458 WREG32(mmRLC_PG_DELAY, data);
4459
4460 data = RREG32(mmRLC_PG_DELAY_2);
4461 data &= ~0xff;
4462 data |= 0x3;
4463 WREG32(mmRLC_PG_DELAY_2, data);
4464
4465 data = RREG32(mmRLC_AUTO_PG_CTRL);
4466 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4467 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4468 WREG32(mmRLC_AUTO_PG_CTRL, data);
4469
4470}
4471
4472static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4473{
4474 gfx_v7_0_enable_gfx_cgpg(adev, enable);
4475 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4476 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4477}
4478
4479static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4480{
4481 u32 count = 0;
4482 const struct cs_section_def *sect = NULL;
4483 const struct cs_extent_def *ext = NULL;
4484
4485 if (adev->gfx.rlc.cs_data == NULL)
4486 return 0;
4487
4488 /* begin clear state */
4489 count += 2;
4490 /* context control state */
4491 count += 3;
4492
4493 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4494 for (ext = sect->section; ext->extent != NULL; ++ext) {
4495 if (sect->id == SECT_CONTEXT)
4496 count += 2 + ext->reg_count;
4497 else
4498 return 0;
4499 }
4500 }
4501 /* pa_sc_raster_config/pa_sc_raster_config1 */
4502 count += 4;
4503 /* end clear state */
4504 count += 2;
4505 /* clear state */
4506 count += 2;
4507
4508 return count;
4509}
4510
4511static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4512 volatile u32 *buffer)
4513{
4514 u32 count = 0, i;
4515 const struct cs_section_def *sect = NULL;
4516 const struct cs_extent_def *ext = NULL;
4517
4518 if (adev->gfx.rlc.cs_data == NULL)
4519 return;
4520 if (buffer == NULL)
4521 return;
4522
4523 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4524 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4525
4526 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4527 buffer[count++] = cpu_to_le32(0x80000000);
4528 buffer[count++] = cpu_to_le32(0x80000000);
4529
4530 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4531 for (ext = sect->section; ext->extent != NULL; ++ext) {
4532 if (sect->id == SECT_CONTEXT) {
4533 buffer[count++] =
4534 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4535 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4536 for (i = 0; i < ext->reg_count; i++)
4537 buffer[count++] = cpu_to_le32(ext->extent[i]);
4538 } else {
4539 return;
4540 }
4541 }
4542 }
4543
4544 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4545 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4546 switch (adev->asic_type) {
4547 case CHIP_BONAIRE:
4548 buffer[count++] = cpu_to_le32(0x16000012);
4549 buffer[count++] = cpu_to_le32(0x00000000);
4550 break;
4551 case CHIP_KAVERI:
4552 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4553 buffer[count++] = cpu_to_le32(0x00000000);
4554 break;
4555 case CHIP_KABINI:
4556 case CHIP_MULLINS:
4557 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4558 buffer[count++] = cpu_to_le32(0x00000000);
4559 break;
4560 case CHIP_HAWAII:
4561 buffer[count++] = cpu_to_le32(0x3a00161a);
4562 buffer[count++] = cpu_to_le32(0x0000002e);
4563 break;
4564 default:
4565 buffer[count++] = cpu_to_le32(0x00000000);
4566 buffer[count++] = cpu_to_le32(0x00000000);
4567 break;
4568 }
4569
4570 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4571 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4572
4573 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4574 buffer[count++] = cpu_to_le32(0);
4575}
4576
4577static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4578{
4579 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
4580 AMDGPU_PG_SUPPORT_GFX_SMG |
4581 AMDGPU_PG_SUPPORT_GFX_DMG |
4582 AMDGPU_PG_SUPPORT_CP |
4583 AMDGPU_PG_SUPPORT_GDS |
4584 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
4585 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4586 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4587 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
4588 gfx_v7_0_init_gfx_cgpg(adev);
4589 gfx_v7_0_enable_cp_pg(adev, true);
4590 gfx_v7_0_enable_gds_pg(adev, true);
4591 }
4592 gfx_v7_0_init_ao_cu_mask(adev);
4593 gfx_v7_0_update_gfx_pg(adev, true);
4594 }
4595}
4596
4597static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4598{
4599 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
4600 AMDGPU_PG_SUPPORT_GFX_SMG |
4601 AMDGPU_PG_SUPPORT_GFX_DMG |
4602 AMDGPU_PG_SUPPORT_CP |
4603 AMDGPU_PG_SUPPORT_GDS |
4604 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
4605 gfx_v7_0_update_gfx_pg(adev, false);
4606 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
4607 gfx_v7_0_enable_cp_pg(adev, false);
4608 gfx_v7_0_enable_gds_pg(adev, false);
4609 }
4610 }
4611}
4612
4613/**
4614 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4615 *
4616 * @adev: amdgpu_device pointer
4617 *
4618 * Fetches a GPU clock counter snapshot (SI).
4619 * Returns the 64 bit clock counter snapshot.
4620 */
4621uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4622{
4623 uint64_t clock;
4624
4625 mutex_lock(&adev->gfx.gpu_clock_mutex);
4626 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4627 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4628 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4629 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4630 return clock;
4631}
4632
4633static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4634 uint32_t vmid,
4635 uint32_t gds_base, uint32_t gds_size,
4636 uint32_t gws_base, uint32_t gws_size,
4637 uint32_t oa_base, uint32_t oa_size)
4638{
4639 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4640 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4641
4642 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4643 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4644
4645 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4646 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4647
4648 /* GDS Base */
4649 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4650 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4651 WRITE_DATA_DST_SEL(0)));
4652 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4653 amdgpu_ring_write(ring, 0);
4654 amdgpu_ring_write(ring, gds_base);
4655
4656 /* GDS Size */
4657 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4658 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4659 WRITE_DATA_DST_SEL(0)));
4660 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4661 amdgpu_ring_write(ring, 0);
4662 amdgpu_ring_write(ring, gds_size);
4663
4664 /* GWS */
4665 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4666 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4667 WRITE_DATA_DST_SEL(0)));
4668 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4669 amdgpu_ring_write(ring, 0);
4670 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4671
4672 /* OA */
4673 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4674 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4675 WRITE_DATA_DST_SEL(0)));
4676 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4677 amdgpu_ring_write(ring, 0);
4678 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4679}
4680
5fc3aeeb 4681static int gfx_v7_0_early_init(void *handle)
a2e73f56 4682{
5fc3aeeb 4683 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4684
4685 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4686 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4687 gfx_v7_0_set_ring_funcs(adev);
4688 gfx_v7_0_set_irq_funcs(adev);
4689 gfx_v7_0_set_gds_init(adev);
4690
4691 return 0;
4692}
4693
ef720532
AD		 4694static int gfx_v7_0_late_init(void *handle)
4695{
4696 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4697 int r;
4698
4699 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4700 if (r)
4701 return r;
4702
4703 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4704 if (r)
4705 return r;
4706
4707 return 0;
4708}
4709
5fc3aeeb 4710static int gfx_v7_0_sw_init(void *handle)
a2e73f56
AD		 4711{
4712 struct amdgpu_ring *ring;
5fc3aeeb 4713 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4714 int i, r;
4715
4716 /* EOP Event */
4717 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4718 if (r)
4719 return r;
4720
4721 /* Privileged reg */
4722 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4723 if (r)
4724 return r;
4725
4726 /* Privileged inst */
4727 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4728 if (r)
4729 return r;
4730
4731 gfx_v7_0_scratch_init(adev);
4732
4733 r = gfx_v7_0_init_microcode(adev);
4734 if (r) {
4735 DRM_ERROR("Failed to load gfx firmware!\n");
4736 return r;
4737 }
4738
4739 r = gfx_v7_0_rlc_init(adev);
4740 if (r) {
4741 DRM_ERROR("Failed to init rlc BOs!\n");
4742 return r;
4743 }
4744
4745 /* allocate mec buffers */
4746 r = gfx_v7_0_mec_init(adev);
4747 if (r) {
4748 DRM_ERROR("Failed to init MEC BOs!\n");
4749 return r;
4750 }
4751
a2e73f56
AD		 4752 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4753 ring = &adev->gfx.gfx_ring[i];
4754 ring->ring_obj = NULL;
4755 sprintf(ring->name, "gfx");
4756 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
4757 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4758 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4759 AMDGPU_RING_TYPE_GFX);
4760 if (r)
4761 return r;
4762 }
4763
4764 /* set up the compute queues */
4765 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4766 unsigned irq_type;
4767
4768 /* max 32 queues per MEC */
4769 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4770 DRM_ERROR("Too many (%d) compute rings!\n", i);
4771 break;
4772 }
4773 ring = &adev->gfx.compute_ring[i];
4774 ring->ring_obj = NULL;
4775 ring->use_doorbell = true;
4776 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4777 ring->me = 1; /* first MEC */
4778 ring->pipe = i / 8;
4779 ring->queue = i % 8;
4780 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
4781 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4782 /* type-2 packets are deprecated on MEC, use type-3 instead */
4783 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
4784 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4785 &adev->gfx.eop_irq, irq_type,
4786 AMDGPU_RING_TYPE_COMPUTE);
4787 if (r)
4788 return r;
4789 }
4790
4791 /* reserve GDS, GWS and OA resource for gfx */
4792 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4793 PAGE_SIZE, true,
4794 AMDGPU_GEM_DOMAIN_GDS, 0,
72d7668b 4795 NULL, NULL, &adev->gds.gds_gfx_bo);
a2e73f56
AD		 4796 if (r)
4797 return r;
4798
4799 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4800 PAGE_SIZE, true,
4801 AMDGPU_GEM_DOMAIN_GWS, 0,
72d7668b 4802 NULL, NULL, &adev->gds.gws_gfx_bo);
a2e73f56
AD		 4803 if (r)
4804 return r;
4805
4806 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4807 PAGE_SIZE, true,
4808 AMDGPU_GEM_DOMAIN_OA, 0,
72d7668b 4809 NULL, NULL, &adev->gds.oa_gfx_bo);
a2e73f56
AD		 4810 if (r)
4811 return r;
4812
4813 return r;
4814}
4815
5fc3aeeb 4816static int gfx_v7_0_sw_fini(void *handle)
a2e73f56
AD		 4817{
4818 int i;
5fc3aeeb 4819 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4820
4821 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4822 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4823 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4824
4825 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4826 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4827 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4828 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4829
a2e73f56
AD		 4830 gfx_v7_0_cp_compute_fini(adev);
4831 gfx_v7_0_rlc_fini(adev);
4832 gfx_v7_0_mec_fini(adev);
4833
4834 return 0;
4835}
4836
5fc3aeeb 4837static int gfx_v7_0_hw_init(void *handle)
a2e73f56
AD		 4838{
4839 int r;
5fc3aeeb 4840 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4841
4842 gfx_v7_0_gpu_init(adev);
4843
4844 /* init rlc */
4845 r = gfx_v7_0_rlc_resume(adev);
4846 if (r)
4847 return r;
4848
4849 r = gfx_v7_0_cp_resume(adev);
4850 if (r)
4851 return r;
4852
a101a899
KW		 4853 adev->gfx.ce_ram_size = 0x8000;
4854
a2e73f56
AD		 4855 return r;
4856}
4857
5fc3aeeb 4858static int gfx_v7_0_hw_fini(void *handle)
a2e73f56 4859{
5fc3aeeb 4860 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4861
ef720532
AD		 4862 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4863 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
a2e73f56
AD		 4864 gfx_v7_0_cp_enable(adev, false);
4865 gfx_v7_0_rlc_stop(adev);
4866 gfx_v7_0_fini_pg(adev);
4867
4868 return 0;
4869}
4870
5fc3aeeb 4871static int gfx_v7_0_suspend(void *handle)
a2e73f56 4872{
5fc3aeeb 4873 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4874
a2e73f56
AD		 4875 return gfx_v7_0_hw_fini(adev);
4876}
4877
5fc3aeeb 4878static int gfx_v7_0_resume(void *handle)
a2e73f56 4879{
5fc3aeeb 4880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4881
a2e73f56
AD		 4882 return gfx_v7_0_hw_init(adev);
4883}
4884
5fc3aeeb 4885static bool gfx_v7_0_is_idle(void *handle)
a2e73f56 4886{
5fc3aeeb 4887 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4888
a2e73f56
AD		 4889 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4890 return false;
4891 else
4892 return true;
4893}
4894
5fc3aeeb 4895static int gfx_v7_0_wait_for_idle(void *handle)
a2e73f56
AD		 4896{
4897 unsigned i;
4898 u32 tmp;
5fc3aeeb 4899 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4900
4901 for (i = 0; i < adev->usec_timeout; i++) {
4902 /* read MC_STATUS */
4903 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4904
4905 if (!tmp)
4906 return 0;
4907 udelay(1);
4908 }
4909 return -ETIMEDOUT;
4910}
4911
5fc3aeeb 4912static void gfx_v7_0_print_status(void *handle)
a2e73f56
AD		 4913{
4914 int i;
5fc3aeeb 4915 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4916
4917 dev_info(adev->dev, "GFX 7.x registers\n");
4918 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
4919 RREG32(mmGRBM_STATUS));
4920 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
4921 RREG32(mmGRBM_STATUS2));
4922 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
4923 RREG32(mmGRBM_STATUS_SE0));
4924 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
4925 RREG32(mmGRBM_STATUS_SE1));
4926 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
4927 RREG32(mmGRBM_STATUS_SE2));
4928 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
4929 RREG32(mmGRBM_STATUS_SE3));
4930 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
4931 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
4932 RREG32(mmCP_STALLED_STAT1));
4933 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
4934 RREG32(mmCP_STALLED_STAT2));
4935 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
4936 RREG32(mmCP_STALLED_STAT3));
4937 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
4938 RREG32(mmCP_CPF_BUSY_STAT));
4939 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
4940 RREG32(mmCP_CPF_STALLED_STAT1));
4941 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
4942 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
4943 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
4944 RREG32(mmCP_CPC_STALLED_STAT1));
4945 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
4946
4947 for (i = 0; i < 32; i++) {
4948 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
4949 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
4950 }
4951 for (i = 0; i < 16; i++) {
4952 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
4953 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
4954 }
4955 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4956 dev_info(adev->dev, " se: %d\n", i);
4957 gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
4958 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
4959 RREG32(mmPA_SC_RASTER_CONFIG));
4960 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
4961 RREG32(mmPA_SC_RASTER_CONFIG_1));
4962 }
4963 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4964
4965 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
4966 RREG32(mmGB_ADDR_CONFIG));
4967 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
4968 RREG32(mmHDP_ADDR_CONFIG));
4969 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
4970 RREG32(mmDMIF_ADDR_CALC));
4971 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n",
4972 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
4973 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n",
4974 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
4975 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
4976 RREG32(mmUVD_UDEC_ADDR_CONFIG));
4977 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
4978 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
4979 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
4980 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
4981
4982 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
4983 RREG32(mmCP_MEQ_THRESHOLDS));
4984 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
4985 RREG32(mmSX_DEBUG_1));
4986 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
4987 RREG32(mmTA_CNTL_AUX));
4988 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
4989 RREG32(mmSPI_CONFIG_CNTL));
4990 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
4991 RREG32(mmSQ_CONFIG));
4992 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
4993 RREG32(mmDB_DEBUG));
4994 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
4995 RREG32(mmDB_DEBUG2));
4996 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
4997 RREG32(mmDB_DEBUG3));
4998 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
4999 RREG32(mmCB_HW_CONTROL));
5000 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
5001 RREG32(mmSPI_CONFIG_CNTL_1));
5002 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
5003 RREG32(mmPA_SC_FIFO_SIZE));
5004 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
5005 RREG32(mmVGT_NUM_INSTANCES));
5006 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
5007 RREG32(mmCP_PERFMON_CNTL));
5008 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
5009 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
5010 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
5011 RREG32(mmVGT_CACHE_INVALIDATION));
5012 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
5013 RREG32(mmVGT_GS_VERTEX_REUSE));
5014 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
5015 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
5016 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
5017 RREG32(mmPA_CL_ENHANCE));
5018 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
5019 RREG32(mmPA_SC_ENHANCE));
5020
5021 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
5022 RREG32(mmCP_ME_CNTL));
5023 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
5024 RREG32(mmCP_MAX_CONTEXT));
5025 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
5026 RREG32(mmCP_ENDIAN_SWAP));
5027 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
5028 RREG32(mmCP_DEVICE_ID));
5029
5030 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
5031 RREG32(mmCP_SEM_WAIT_TIMER));
5032 if (adev->asic_type != CHIP_HAWAII)
5033 dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
5034 RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL));
5035
5036 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
5037 RREG32(mmCP_RB_WPTR_DELAY));
5038 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
5039 RREG32(mmCP_RB_VMID));
5040 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
5041 RREG32(mmCP_RB0_CNTL));
5042 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
5043 RREG32(mmCP_RB0_WPTR));
5044 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
5045 RREG32(mmCP_RB0_RPTR_ADDR));
5046 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
5047 RREG32(mmCP_RB0_RPTR_ADDR_HI));
5048 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
5049 RREG32(mmCP_RB0_CNTL));
5050 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
5051 RREG32(mmCP_RB0_BASE));
5052 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
5053 RREG32(mmCP_RB0_BASE_HI));
5054 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
5055 RREG32(mmCP_MEC_CNTL));
5056 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
5057 RREG32(mmCP_CPF_DEBUG));
5058
5059 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
5060 RREG32(mmSCRATCH_ADDR));
5061 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
5062 RREG32(mmSCRATCH_UMSK));
5063
5064 /* init the pipes */
5065 mutex_lock(&adev->srbm_mutex);
5066 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
5067 int me = (i < 4) ? 1 : 2;
5068 int pipe = (i < 4) ? i : (i - 4);
5069 int queue;
5070
5071 dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe);
5072 cik_srbm_select(adev, me, pipe, 0, 0);
5073 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n",
5074 RREG32(mmCP_HPD_EOP_BASE_ADDR));
5075 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n",
5076 RREG32(mmCP_HPD_EOP_BASE_ADDR_HI));
5077 dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n",
5078 RREG32(mmCP_HPD_EOP_VMID));
5079 dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n",
5080 RREG32(mmCP_HPD_EOP_CONTROL));
5081
0fd64291 5082 for (queue = 0; queue < 8; queue++) {
a2e73f56
AD		 5083 cik_srbm_select(adev, me, pipe, queue, 0);
5084 dev_info(adev->dev, " queue: %d\n", queue);
5085 dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
5086 RREG32(mmCP_PQ_WPTR_POLL_CNTL));
5087 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
5088 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
5089 dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n",
5090 RREG32(mmCP_HQD_ACTIVE));
5091 dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n",
5092 RREG32(mmCP_HQD_DEQUEUE_REQUEST));
5093 dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n",
5094 RREG32(mmCP_HQD_PQ_RPTR));
5095 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n",
5096 RREG32(mmCP_HQD_PQ_WPTR));
5097 dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n",
5098 RREG32(mmCP_HQD_PQ_BASE));
5099 dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n",
5100 RREG32(mmCP_HQD_PQ_BASE_HI));
5101 dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n",
5102 RREG32(mmCP_HQD_PQ_CONTROL));
5103 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n",
5104 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR));
5105 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n",
5106 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI));
5107 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n",
5108 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR));
5109 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n",
5110 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI));
5111 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
5112 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
5113 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n",
5114 RREG32(mmCP_HQD_PQ_WPTR));
5115 dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n",
5116 RREG32(mmCP_HQD_VMID));
5117 dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n",
5118 RREG32(mmCP_MQD_BASE_ADDR));
5119 dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n",
5120 RREG32(mmCP_MQD_BASE_ADDR_HI));
5121 dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n",
5122 RREG32(mmCP_MQD_CONTROL));
5123 }
5124 }
5125 cik_srbm_select(adev, 0, 0, 0, 0);
5126 mutex_unlock(&adev->srbm_mutex);
5127
5128 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
5129 RREG32(mmCP_INT_CNTL_RING0));
5130 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
5131 RREG32(mmRLC_LB_CNTL));
5132 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
5133 RREG32(mmRLC_CNTL));
5134 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
5135 RREG32(mmRLC_CGCG_CGLS_CTRL));
5136 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
5137 RREG32(mmRLC_LB_CNTR_INIT));
5138 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
5139 RREG32(mmRLC_LB_CNTR_MAX));
5140 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
5141 RREG32(mmRLC_LB_INIT_CU_MASK));
5142 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
5143 RREG32(mmRLC_LB_PARAMS));
5144 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
5145 RREG32(mmRLC_LB_CNTL));
5146 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
5147 RREG32(mmRLC_MC_CNTL));
5148 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
5149 RREG32(mmRLC_UCODE_CNTL));
5150
5151 if (adev->asic_type == CHIP_BONAIRE)
5152 dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n",
5153 RREG32(mmRLC_DRIVER_CPDMA_STATUS));
5154
5155 mutex_lock(&adev->srbm_mutex);
5156 for (i = 0; i < 16; i++) {
5157 cik_srbm_select(adev, 0, 0, 0, i);
5158 dev_info(adev->dev, " VM %d:\n", i);
5159 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
5160 RREG32(mmSH_MEM_CONFIG));
5161 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
5162 RREG32(mmSH_MEM_APE1_BASE));
5163 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
5164 RREG32(mmSH_MEM_APE1_LIMIT));
5165 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
5166 RREG32(mmSH_MEM_BASES));
5167 }
5168 cik_srbm_select(adev, 0, 0, 0, 0);
5169 mutex_unlock(&adev->srbm_mutex);
5170}
5171
5fc3aeeb 5172static int gfx_v7_0_soft_reset(void *handle)
a2e73f56
AD		 5173{
5174 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5175 u32 tmp;
5fc3aeeb 5176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 5177
5178 /* GRBM_STATUS */
5179 tmp = RREG32(mmGRBM_STATUS);
5180 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
5181 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
5182 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
5183 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
5184 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
5185 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
5186 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
5187 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
5188
5189 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
5190 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
5191 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
5192 }
5193
5194 /* GRBM_STATUS2 */
5195 tmp = RREG32(mmGRBM_STATUS2);
5196 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
5197 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
5198
5199 /* SRBM_STATUS */
5200 tmp = RREG32(mmSRBM_STATUS);
5201 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
5202 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
5203
5204 if (grbm_soft_reset || srbm_soft_reset) {
5fc3aeeb 5205 gfx_v7_0_print_status((void *)adev);
a2e73f56
AD		 5206 /* disable CG/PG */
5207 gfx_v7_0_fini_pg(adev);
5208 gfx_v7_0_update_cg(adev, false);
5209
5210 /* stop the rlc */
5211 gfx_v7_0_rlc_stop(adev);
5212
5213 /* Disable GFX parsing/prefetching */
5214 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
5215
5216 /* Disable MEC parsing/prefetching */
5217 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
5218
5219 if (grbm_soft_reset) {
5220 tmp = RREG32(mmGRBM_SOFT_RESET);
5221 tmp |= grbm_soft_reset;
5222 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5223 WREG32(mmGRBM_SOFT_RESET, tmp);
5224 tmp = RREG32(mmGRBM_SOFT_RESET);
5225
5226 udelay(50);
5227
5228 tmp &= ~grbm_soft_reset;
5229 WREG32(mmGRBM_SOFT_RESET, tmp);
5230 tmp = RREG32(mmGRBM_SOFT_RESET);
5231 }
5232
5233 if (srbm_soft_reset) {
5234 tmp = RREG32(mmSRBM_SOFT_RESET);
5235 tmp |= srbm_soft_reset;
5236 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5237 WREG32(mmSRBM_SOFT_RESET, tmp);
5238 tmp = RREG32(mmSRBM_SOFT_RESET);
5239
5240 udelay(50);
5241
5242 tmp &= ~srbm_soft_reset;
5243 WREG32(mmSRBM_SOFT_RESET, tmp);
5244 tmp = RREG32(mmSRBM_SOFT_RESET);
5245 }
5246 /* Wait a little for things to settle down */
5247 udelay(50);
5fc3aeeb 5248 gfx_v7_0_print_status((void *)adev);
a2e73f56
AD		 5249 }
5250 return 0;
5251}
5252
5253static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5254 enum amdgpu_interrupt_state state)
5255{
5256 u32 cp_int_cntl;
5257
5258 switch (state) {
5259 case AMDGPU_IRQ_STATE_DISABLE:
5260 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5261 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5262 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5263 break;
5264 case AMDGPU_IRQ_STATE_ENABLE:
5265 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5266 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5267 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5268 break;
5269 default:
5270 break;
5271 }
5272}
5273
5274static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5275 int me, int pipe,
5276 enum amdgpu_interrupt_state state)
5277{
5278 u32 mec_int_cntl, mec_int_cntl_reg;
5279
5280 /*
5281 * amdgpu controls only pipe 0 of MEC1. That's why this function only
5282 * handles the setting of interrupts for this specific pipe. All other
5283 * pipes' interrupts are set by amdkfd.
5284 */
5285
5286 if (me == 1) {
5287 switch (pipe) {
5288 case 0:
5289 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
5290 break;
5291 default:
5292 DRM_DEBUG("invalid pipe %d\n", pipe);
5293 return;
5294 }
5295 } else {
5296 DRM_DEBUG("invalid me %d\n", me);
5297 return;
5298 }
5299
5300 switch (state) {
5301 case AMDGPU_IRQ_STATE_DISABLE:
5302 mec_int_cntl = RREG32(mec_int_cntl_reg);
5303 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5304 WREG32(mec_int_cntl_reg, mec_int_cntl);
5305 break;
5306 case AMDGPU_IRQ_STATE_ENABLE:
5307 mec_int_cntl = RREG32(mec_int_cntl_reg);
5308 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5309 WREG32(mec_int_cntl_reg, mec_int_cntl);
5310 break;
5311 default:
5312 break;
5313 }
5314}
5315
5316static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5317 struct amdgpu_irq_src *src,
5318 unsigned type,
5319 enum amdgpu_interrupt_state state)
5320{
5321 u32 cp_int_cntl;
5322
5323 switch (state) {
5324 case AMDGPU_IRQ_STATE_DISABLE:
5325 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5326 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5327 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5328 break;
5329 case AMDGPU_IRQ_STATE_ENABLE:
5330 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5331 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5332 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5333 break;
5334 default:
5335 break;
5336 }
5337
5338 return 0;
5339}
5340
5341static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5342 struct amdgpu_irq_src *src,
5343 unsigned type,
5344 enum amdgpu_interrupt_state state)
5345{
5346 u32 cp_int_cntl;
5347
5348 switch (state) {
5349 case AMDGPU_IRQ_STATE_DISABLE:
5350 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5351 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5352 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5353 break;
5354 case AMDGPU_IRQ_STATE_ENABLE:
5355 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5356 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5357 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5358 break;
5359 default:
5360 break;
5361 }
5362
5363 return 0;
5364}
5365
5366static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5367 struct amdgpu_irq_src *src,
5368 unsigned type,
5369 enum amdgpu_interrupt_state state)
5370{
5371 switch (type) {
5372 case AMDGPU_CP_IRQ_GFX_EOP:
5373 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
5374 break;
5375 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5376 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5377 break;
5378 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5379 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5380 break;
5381 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5382 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5383 break;
5384 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5385 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5386 break;
5387 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5388 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5389 break;
5390 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5391 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5392 break;
5393 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5394 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5395 break;
5396 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5397 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5398 break;
5399 default:
5400 break;
5401 }
5402 return 0;
5403}
5404
5405static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5406 struct amdgpu_irq_src *source,
5407 struct amdgpu_iv_entry *entry)
5408{
5409 u8 me_id, pipe_id;
5410 struct amdgpu_ring *ring;
5411 int i;
5412
5413 DRM_DEBUG("IH: CP EOP\n");
5414 me_id = (entry->ring_id & 0x0c) >> 2;
5415 pipe_id = (entry->ring_id & 0x03) >> 0;
5416 switch (me_id) {
5417 case 0:
5418 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5419 break;
5420 case 1:
5421 case 2:
5422 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5423 ring = &adev->gfx.compute_ring[i];
5424 if ((ring->me == me_id) & (ring->pipe == pipe_id))
5425 amdgpu_fence_process(ring);
5426 }
5427 break;
5428 }
5429 return 0;
5430}
5431
5432static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5433 struct amdgpu_irq_src *source,
5434 struct amdgpu_iv_entry *entry)
5435{
5436 DRM_ERROR("Illegal register access in command stream\n");
5437 schedule_work(&adev->reset_work);
5438 return 0;
5439}
5440
5441static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5442 struct amdgpu_irq_src *source,
5443 struct amdgpu_iv_entry *entry)
5444{
5445 DRM_ERROR("Illegal instruction in command stream\n");
5446 // XXX soft reset the gfx block only
5447 schedule_work(&adev->reset_work);
5448 return 0;
5449}
5450
5fc3aeeb 5451static int gfx_v7_0_set_clockgating_state(void *handle,
5452 enum amd_clockgating_state state)
a2e73f56
AD		 5453{
5454 bool gate = false;
5fc3aeeb 5455 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5456
5fc3aeeb 5457 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 5458 gate = true;
5459
5460 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5461 /* order matters! */
5462 if (gate) {
5463 gfx_v7_0_enable_mgcg(adev, true);
5464 gfx_v7_0_enable_cgcg(adev, true);
5465 } else {
5466 gfx_v7_0_enable_cgcg(adev, false);
5467 gfx_v7_0_enable_mgcg(adev, false);
5468 }
5469 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5470
5471 return 0;
5472}
5473
5fc3aeeb 5474static int gfx_v7_0_set_powergating_state(void *handle,
5475 enum amd_powergating_state state)
a2e73f56
AD		 5476{
5477 bool gate = false;
5fc3aeeb 5478 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5479
5fc3aeeb 5480 if (state == AMD_PG_STATE_GATE)
a2e73f56
AD		 5481 gate = true;
5482
5483 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
5484 AMDGPU_PG_SUPPORT_GFX_SMG |
5485 AMDGPU_PG_SUPPORT_GFX_DMG |
5486 AMDGPU_PG_SUPPORT_CP |
5487 AMDGPU_PG_SUPPORT_GDS |
5488 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
5489 gfx_v7_0_update_gfx_pg(adev, gate);
5490 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
5491 gfx_v7_0_enable_cp_pg(adev, gate);
5492 gfx_v7_0_enable_gds_pg(adev, gate);
5493 }
5494 }
5495
5496 return 0;
5497}
5498
5fc3aeeb 5499const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
a2e73f56 5500 .early_init = gfx_v7_0_early_init,
ef720532 5501 .late_init = gfx_v7_0_late_init,
a2e73f56
AD		 5502 .sw_init = gfx_v7_0_sw_init,
5503 .sw_fini = gfx_v7_0_sw_fini,
5504 .hw_init = gfx_v7_0_hw_init,
5505 .hw_fini = gfx_v7_0_hw_fini,
5506 .suspend = gfx_v7_0_suspend,
5507 .resume = gfx_v7_0_resume,
5508 .is_idle = gfx_v7_0_is_idle,
5509 .wait_for_idle = gfx_v7_0_wait_for_idle,
5510 .soft_reset = gfx_v7_0_soft_reset,
5511 .print_status = gfx_v7_0_print_status,
5512 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5513 .set_powergating_state = gfx_v7_0_set_powergating_state,
5514};
5515
a2e73f56
AD		 5516static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5517 .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
5518 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5519 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5520 .parse_cs = NULL,
93323131 5521 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
a2e73f56 5522 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
a2e73f56
AD		 5523 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5524 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d2edb07b 5525 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
a2e73f56
AD		 5526 .test_ring = gfx_v7_0_ring_test_ring,
5527 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5528 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5529 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 5530};
5531
5532static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5533 .get_rptr = gfx_v7_0_ring_get_rptr_compute,
5534 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5535 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5536 .parse_cs = NULL,
93323131 5537 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
a2e73f56 5538 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
a2e73f56
AD		 5539 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5540 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d9b5327a 5541 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
a2e73f56
AD		 5542 .test_ring = gfx_v7_0_ring_test_ring,
5543 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5544 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5545 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 5546};
5547
5548static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5549{
5550 int i;
5551
5552 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5553 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5554 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5555 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5556}
5557
5558static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5559 .set = gfx_v7_0_set_eop_interrupt_state,
5560 .process = gfx_v7_0_eop_irq,
5561};
5562
5563static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5564 .set = gfx_v7_0_set_priv_reg_fault_state,
5565 .process = gfx_v7_0_priv_reg_irq,
5566};
5567
5568static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5569 .set = gfx_v7_0_set_priv_inst_fault_state,
5570 .process = gfx_v7_0_priv_inst_irq,
5571};
5572
5573static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5574{
5575 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5576 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5577
5578 adev->gfx.priv_reg_irq.num_types = 1;
5579 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5580
5581 adev->gfx.priv_inst_irq.num_types = 1;
5582 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5583}
5584
5585static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5586{
5587 /* init asci gds info */
5588 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5589 adev->gds.gws.total_size = 64;
5590 adev->gds.oa.total_size = 16;
5591
5592 if (adev->gds.mem.total_size == 64 * 1024) {
5593 adev->gds.mem.gfx_partition_size = 4096;
5594 adev->gds.mem.cs_partition_size = 4096;
5595
5596 adev->gds.gws.gfx_partition_size = 4;
5597 adev->gds.gws.cs_partition_size = 4;
5598
5599 adev->gds.oa.gfx_partition_size = 4;
5600 adev->gds.oa.cs_partition_size = 1;
5601 } else {
5602 adev->gds.mem.gfx_partition_size = 1024;
5603 adev->gds.mem.cs_partition_size = 1024;
5604
5605 adev->gds.gws.gfx_partition_size = 16;
5606 adev->gds.gws.cs_partition_size = 16;
5607
5608 adev->gds.oa.gfx_partition_size = 4;
5609 adev->gds.oa.cs_partition_size = 4;
5610 }
5611}
5612
5613
5614int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
5615 struct amdgpu_cu_info *cu_info)
5616{
5617 int i, j, k, counter, active_cu_number = 0;
5618 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5619
5620 if (!adev || !cu_info)
5621 return -EINVAL;
5622
5623 mutex_lock(&adev->grbm_idx_mutex);
5624 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5625 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5626 mask = 1;
5627 ao_bitmap = 0;
5628 counter = 0;
5629 bitmap = gfx_v7_0_get_cu_active_bitmap(adev, i, j);
5630 cu_info->bitmap[i][j] = bitmap;
5631
5632 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5633 if (bitmap & mask) {
5634 if (counter < 2)
5635 ao_bitmap |= mask;
5636 counter ++;
5637 }
5638 mask <<= 1;
5639 }
5640 active_cu_number += counter;
5641 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5642 }
5643 }
5644
5645 cu_info->number = active_cu_number;
5646 cu_info->ao_cu_mask = ao_cu_mask;
5647 mutex_unlock(&adev->grbm_idx_mutex);
5648 return 0;
5649}
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