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1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/firmware.h> | |
24 | #include "drmP.h" | |
25 | #include "amdgpu.h" | |
26 | #include "amdgpu_ih.h" | |
27 | #include "amdgpu_gfx.h" | |
28 | #include "cikd.h" | |
29 | #include "cik.h" | |
30 | #include "atom.h" | |
31 | #include "amdgpu_ucode.h" | |
32 | #include "clearstate_ci.h" | |
33 | ||
a2e73f56 AD |
34 | #include "dce/dce_8_0_d.h" |
35 | #include "dce/dce_8_0_sh_mask.h" | |
36 | ||
37 | #include "bif/bif_4_1_d.h" | |
38 | #include "bif/bif_4_1_sh_mask.h" | |
39 | ||
40 | #include "gca/gfx_7_0_d.h" | |
41 | #include "gca/gfx_7_2_enum.h" | |
42 | #include "gca/gfx_7_2_sh_mask.h" | |
43 | ||
44 | #include "gmc/gmc_7_0_d.h" | |
45 | #include "gmc/gmc_7_0_sh_mask.h" | |
46 | ||
47 | #include "oss/oss_2_0_d.h" | |
48 | #include "oss/oss_2_0_sh_mask.h" | |
49 | ||
50 | #define GFX7_NUM_GFX_RINGS 1 | |
51 | #define GFX7_NUM_COMPUTE_RINGS 8 | |
52 | ||
53 | static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); | |
54 | static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); | |
55 | static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); | |
56 | int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *); | |
57 | ||
58 | MODULE_FIRMWARE("radeon/bonaire_pfp.bin"); | |
59 | MODULE_FIRMWARE("radeon/bonaire_me.bin"); | |
60 | MODULE_FIRMWARE("radeon/bonaire_ce.bin"); | |
61 | MODULE_FIRMWARE("radeon/bonaire_rlc.bin"); | |
62 | MODULE_FIRMWARE("radeon/bonaire_mec.bin"); | |
63 | ||
64 | MODULE_FIRMWARE("radeon/hawaii_pfp.bin"); | |
65 | MODULE_FIRMWARE("radeon/hawaii_me.bin"); | |
66 | MODULE_FIRMWARE("radeon/hawaii_ce.bin"); | |
67 | MODULE_FIRMWARE("radeon/hawaii_rlc.bin"); | |
68 | MODULE_FIRMWARE("radeon/hawaii_mec.bin"); | |
69 | ||
70 | MODULE_FIRMWARE("radeon/kaveri_pfp.bin"); | |
71 | MODULE_FIRMWARE("radeon/kaveri_me.bin"); | |
72 | MODULE_FIRMWARE("radeon/kaveri_ce.bin"); | |
73 | MODULE_FIRMWARE("radeon/kaveri_rlc.bin"); | |
74 | MODULE_FIRMWARE("radeon/kaveri_mec.bin"); | |
75 | MODULE_FIRMWARE("radeon/kaveri_mec2.bin"); | |
76 | ||
77 | MODULE_FIRMWARE("radeon/kabini_pfp.bin"); | |
78 | MODULE_FIRMWARE("radeon/kabini_me.bin"); | |
79 | MODULE_FIRMWARE("radeon/kabini_ce.bin"); | |
80 | MODULE_FIRMWARE("radeon/kabini_rlc.bin"); | |
81 | MODULE_FIRMWARE("radeon/kabini_mec.bin"); | |
82 | ||
83 | MODULE_FIRMWARE("radeon/mullins_pfp.bin"); | |
84 | MODULE_FIRMWARE("radeon/mullins_me.bin"); | |
85 | MODULE_FIRMWARE("radeon/mullins_ce.bin"); | |
86 | MODULE_FIRMWARE("radeon/mullins_rlc.bin"); | |
87 | MODULE_FIRMWARE("radeon/mullins_mec.bin"); | |
88 | ||
89 | static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = | |
90 | { | |
91 | {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, | |
92 | {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, | |
93 | {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, | |
94 | {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, | |
95 | {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, | |
96 | {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, | |
97 | {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, | |
98 | {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, | |
99 | {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, | |
100 | {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, | |
101 | {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, | |
102 | {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, | |
103 | {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, | |
104 | {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, | |
105 | {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, | |
106 | {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} | |
107 | }; | |
108 | ||
109 | static const u32 spectre_rlc_save_restore_register_list[] = | |
110 | { | |
111 | (0x0e00 << 16) | (0xc12c >> 2), | |
112 | 0x00000000, | |
113 | (0x0e00 << 16) | (0xc140 >> 2), | |
114 | 0x00000000, | |
115 | (0x0e00 << 16) | (0xc150 >> 2), | |
116 | 0x00000000, | |
117 | (0x0e00 << 16) | (0xc15c >> 2), | |
118 | 0x00000000, | |
119 | (0x0e00 << 16) | (0xc168 >> 2), | |
120 | 0x00000000, | |
121 | (0x0e00 << 16) | (0xc170 >> 2), | |
122 | 0x00000000, | |
123 | (0x0e00 << 16) | (0xc178 >> 2), | |
124 | 0x00000000, | |
125 | (0x0e00 << 16) | (0xc204 >> 2), | |
126 | 0x00000000, | |
127 | (0x0e00 << 16) | (0xc2b4 >> 2), | |
128 | 0x00000000, | |
129 | (0x0e00 << 16) | (0xc2b8 >> 2), | |
130 | 0x00000000, | |
131 | (0x0e00 << 16) | (0xc2bc >> 2), | |
132 | 0x00000000, | |
133 | (0x0e00 << 16) | (0xc2c0 >> 2), | |
134 | 0x00000000, | |
135 | (0x0e00 << 16) | (0x8228 >> 2), | |
136 | 0x00000000, | |
137 | (0x0e00 << 16) | (0x829c >> 2), | |
138 | 0x00000000, | |
139 | (0x0e00 << 16) | (0x869c >> 2), | |
140 | 0x00000000, | |
141 | (0x0600 << 16) | (0x98f4 >> 2), | |
142 | 0x00000000, | |
143 | (0x0e00 << 16) | (0x98f8 >> 2), | |
144 | 0x00000000, | |
145 | (0x0e00 << 16) | (0x9900 >> 2), | |
146 | 0x00000000, | |
147 | (0x0e00 << 16) | (0xc260 >> 2), | |
148 | 0x00000000, | |
149 | (0x0e00 << 16) | (0x90e8 >> 2), | |
150 | 0x00000000, | |
151 | (0x0e00 << 16) | (0x3c000 >> 2), | |
152 | 0x00000000, | |
153 | (0x0e00 << 16) | (0x3c00c >> 2), | |
154 | 0x00000000, | |
155 | (0x0e00 << 16) | (0x8c1c >> 2), | |
156 | 0x00000000, | |
157 | (0x0e00 << 16) | (0x9700 >> 2), | |
158 | 0x00000000, | |
159 | (0x0e00 << 16) | (0xcd20 >> 2), | |
160 | 0x00000000, | |
161 | (0x4e00 << 16) | (0xcd20 >> 2), | |
162 | 0x00000000, | |
163 | (0x5e00 << 16) | (0xcd20 >> 2), | |
164 | 0x00000000, | |
165 | (0x6e00 << 16) | (0xcd20 >> 2), | |
166 | 0x00000000, | |
167 | (0x7e00 << 16) | (0xcd20 >> 2), | |
168 | 0x00000000, | |
169 | (0x8e00 << 16) | (0xcd20 >> 2), | |
170 | 0x00000000, | |
171 | (0x9e00 << 16) | (0xcd20 >> 2), | |
172 | 0x00000000, | |
173 | (0xae00 << 16) | (0xcd20 >> 2), | |
174 | 0x00000000, | |
175 | (0xbe00 << 16) | (0xcd20 >> 2), | |
176 | 0x00000000, | |
177 | (0x0e00 << 16) | (0x89bc >> 2), | |
178 | 0x00000000, | |
179 | (0x0e00 << 16) | (0x8900 >> 2), | |
180 | 0x00000000, | |
181 | 0x3, | |
182 | (0x0e00 << 16) | (0xc130 >> 2), | |
183 | 0x00000000, | |
184 | (0x0e00 << 16) | (0xc134 >> 2), | |
185 | 0x00000000, | |
186 | (0x0e00 << 16) | (0xc1fc >> 2), | |
187 | 0x00000000, | |
188 | (0x0e00 << 16) | (0xc208 >> 2), | |
189 | 0x00000000, | |
190 | (0x0e00 << 16) | (0xc264 >> 2), | |
191 | 0x00000000, | |
192 | (0x0e00 << 16) | (0xc268 >> 2), | |
193 | 0x00000000, | |
194 | (0x0e00 << 16) | (0xc26c >> 2), | |
195 | 0x00000000, | |
196 | (0x0e00 << 16) | (0xc270 >> 2), | |
197 | 0x00000000, | |
198 | (0x0e00 << 16) | (0xc274 >> 2), | |
199 | 0x00000000, | |
200 | (0x0e00 << 16) | (0xc278 >> 2), | |
201 | 0x00000000, | |
202 | (0x0e00 << 16) | (0xc27c >> 2), | |
203 | 0x00000000, | |
204 | (0x0e00 << 16) | (0xc280 >> 2), | |
205 | 0x00000000, | |
206 | (0x0e00 << 16) | (0xc284 >> 2), | |
207 | 0x00000000, | |
208 | (0x0e00 << 16) | (0xc288 >> 2), | |
209 | 0x00000000, | |
210 | (0x0e00 << 16) | (0xc28c >> 2), | |
211 | 0x00000000, | |
212 | (0x0e00 << 16) | (0xc290 >> 2), | |
213 | 0x00000000, | |
214 | (0x0e00 << 16) | (0xc294 >> 2), | |
215 | 0x00000000, | |
216 | (0x0e00 << 16) | (0xc298 >> 2), | |
217 | 0x00000000, | |
218 | (0x0e00 << 16) | (0xc29c >> 2), | |
219 | 0x00000000, | |
220 | (0x0e00 << 16) | (0xc2a0 >> 2), | |
221 | 0x00000000, | |
222 | (0x0e00 << 16) | (0xc2a4 >> 2), | |
223 | 0x00000000, | |
224 | (0x0e00 << 16) | (0xc2a8 >> 2), | |
225 | 0x00000000, | |
226 | (0x0e00 << 16) | (0xc2ac >> 2), | |
227 | 0x00000000, | |
228 | (0x0e00 << 16) | (0xc2b0 >> 2), | |
229 | 0x00000000, | |
230 | (0x0e00 << 16) | (0x301d0 >> 2), | |
231 | 0x00000000, | |
232 | (0x0e00 << 16) | (0x30238 >> 2), | |
233 | 0x00000000, | |
234 | (0x0e00 << 16) | (0x30250 >> 2), | |
235 | 0x00000000, | |
236 | (0x0e00 << 16) | (0x30254 >> 2), | |
237 | 0x00000000, | |
238 | (0x0e00 << 16) | (0x30258 >> 2), | |
239 | 0x00000000, | |
240 | (0x0e00 << 16) | (0x3025c >> 2), | |
241 | 0x00000000, | |
242 | (0x4e00 << 16) | (0xc900 >> 2), | |
243 | 0x00000000, | |
244 | (0x5e00 << 16) | (0xc900 >> 2), | |
245 | 0x00000000, | |
246 | (0x6e00 << 16) | (0xc900 >> 2), | |
247 | 0x00000000, | |
248 | (0x7e00 << 16) | (0xc900 >> 2), | |
249 | 0x00000000, | |
250 | (0x8e00 << 16) | (0xc900 >> 2), | |
251 | 0x00000000, | |
252 | (0x9e00 << 16) | (0xc900 >> 2), | |
253 | 0x00000000, | |
254 | (0xae00 << 16) | (0xc900 >> 2), | |
255 | 0x00000000, | |
256 | (0xbe00 << 16) | (0xc900 >> 2), | |
257 | 0x00000000, | |
258 | (0x4e00 << 16) | (0xc904 >> 2), | |
259 | 0x00000000, | |
260 | (0x5e00 << 16) | (0xc904 >> 2), | |
261 | 0x00000000, | |
262 | (0x6e00 << 16) | (0xc904 >> 2), | |
263 | 0x00000000, | |
264 | (0x7e00 << 16) | (0xc904 >> 2), | |
265 | 0x00000000, | |
266 | (0x8e00 << 16) | (0xc904 >> 2), | |
267 | 0x00000000, | |
268 | (0x9e00 << 16) | (0xc904 >> 2), | |
269 | 0x00000000, | |
270 | (0xae00 << 16) | (0xc904 >> 2), | |
271 | 0x00000000, | |
272 | (0xbe00 << 16) | (0xc904 >> 2), | |
273 | 0x00000000, | |
274 | (0x4e00 << 16) | (0xc908 >> 2), | |
275 | 0x00000000, | |
276 | (0x5e00 << 16) | (0xc908 >> 2), | |
277 | 0x00000000, | |
278 | (0x6e00 << 16) | (0xc908 >> 2), | |
279 | 0x00000000, | |
280 | (0x7e00 << 16) | (0xc908 >> 2), | |
281 | 0x00000000, | |
282 | (0x8e00 << 16) | (0xc908 >> 2), | |
283 | 0x00000000, | |
284 | (0x9e00 << 16) | (0xc908 >> 2), | |
285 | 0x00000000, | |
286 | (0xae00 << 16) | (0xc908 >> 2), | |
287 | 0x00000000, | |
288 | (0xbe00 << 16) | (0xc908 >> 2), | |
289 | 0x00000000, | |
290 | (0x4e00 << 16) | (0xc90c >> 2), | |
291 | 0x00000000, | |
292 | (0x5e00 << 16) | (0xc90c >> 2), | |
293 | 0x00000000, | |
294 | (0x6e00 << 16) | (0xc90c >> 2), | |
295 | 0x00000000, | |
296 | (0x7e00 << 16) | (0xc90c >> 2), | |
297 | 0x00000000, | |
298 | (0x8e00 << 16) | (0xc90c >> 2), | |
299 | 0x00000000, | |
300 | (0x9e00 << 16) | (0xc90c >> 2), | |
301 | 0x00000000, | |
302 | (0xae00 << 16) | (0xc90c >> 2), | |
303 | 0x00000000, | |
304 | (0xbe00 << 16) | (0xc90c >> 2), | |
305 | 0x00000000, | |
306 | (0x4e00 << 16) | (0xc910 >> 2), | |
307 | 0x00000000, | |
308 | (0x5e00 << 16) | (0xc910 >> 2), | |
309 | 0x00000000, | |
310 | (0x6e00 << 16) | (0xc910 >> 2), | |
311 | 0x00000000, | |
312 | (0x7e00 << 16) | (0xc910 >> 2), | |
313 | 0x00000000, | |
314 | (0x8e00 << 16) | (0xc910 >> 2), | |
315 | 0x00000000, | |
316 | (0x9e00 << 16) | (0xc910 >> 2), | |
317 | 0x00000000, | |
318 | (0xae00 << 16) | (0xc910 >> 2), | |
319 | 0x00000000, | |
320 | (0xbe00 << 16) | (0xc910 >> 2), | |
321 | 0x00000000, | |
322 | (0x0e00 << 16) | (0xc99c >> 2), | |
323 | 0x00000000, | |
324 | (0x0e00 << 16) | (0x9834 >> 2), | |
325 | 0x00000000, | |
326 | (0x0000 << 16) | (0x30f00 >> 2), | |
327 | 0x00000000, | |
328 | (0x0001 << 16) | (0x30f00 >> 2), | |
329 | 0x00000000, | |
330 | (0x0000 << 16) | (0x30f04 >> 2), | |
331 | 0x00000000, | |
332 | (0x0001 << 16) | (0x30f04 >> 2), | |
333 | 0x00000000, | |
334 | (0x0000 << 16) | (0x30f08 >> 2), | |
335 | 0x00000000, | |
336 | (0x0001 << 16) | (0x30f08 >> 2), | |
337 | 0x00000000, | |
338 | (0x0000 << 16) | (0x30f0c >> 2), | |
339 | 0x00000000, | |
340 | (0x0001 << 16) | (0x30f0c >> 2), | |
341 | 0x00000000, | |
342 | (0x0600 << 16) | (0x9b7c >> 2), | |
343 | 0x00000000, | |
344 | (0x0e00 << 16) | (0x8a14 >> 2), | |
345 | 0x00000000, | |
346 | (0x0e00 << 16) | (0x8a18 >> 2), | |
347 | 0x00000000, | |
348 | (0x0600 << 16) | (0x30a00 >> 2), | |
349 | 0x00000000, | |
350 | (0x0e00 << 16) | (0x8bf0 >> 2), | |
351 | 0x00000000, | |
352 | (0x0e00 << 16) | (0x8bcc >> 2), | |
353 | 0x00000000, | |
354 | (0x0e00 << 16) | (0x8b24 >> 2), | |
355 | 0x00000000, | |
356 | (0x0e00 << 16) | (0x30a04 >> 2), | |
357 | 0x00000000, | |
358 | (0x0600 << 16) | (0x30a10 >> 2), | |
359 | 0x00000000, | |
360 | (0x0600 << 16) | (0x30a14 >> 2), | |
361 | 0x00000000, | |
362 | (0x0600 << 16) | (0x30a18 >> 2), | |
363 | 0x00000000, | |
364 | (0x0600 << 16) | (0x30a2c >> 2), | |
365 | 0x00000000, | |
366 | (0x0e00 << 16) | (0xc700 >> 2), | |
367 | 0x00000000, | |
368 | (0x0e00 << 16) | (0xc704 >> 2), | |
369 | 0x00000000, | |
370 | (0x0e00 << 16) | (0xc708 >> 2), | |
371 | 0x00000000, | |
372 | (0x0e00 << 16) | (0xc768 >> 2), | |
373 | 0x00000000, | |
374 | (0x0400 << 16) | (0xc770 >> 2), | |
375 | 0x00000000, | |
376 | (0x0400 << 16) | (0xc774 >> 2), | |
377 | 0x00000000, | |
378 | (0x0400 << 16) | (0xc778 >> 2), | |
379 | 0x00000000, | |
380 | (0x0400 << 16) | (0xc77c >> 2), | |
381 | 0x00000000, | |
382 | (0x0400 << 16) | (0xc780 >> 2), | |
383 | 0x00000000, | |
384 | (0x0400 << 16) | (0xc784 >> 2), | |
385 | 0x00000000, | |
386 | (0x0400 << 16) | (0xc788 >> 2), | |
387 | 0x00000000, | |
388 | (0x0400 << 16) | (0xc78c >> 2), | |
389 | 0x00000000, | |
390 | (0x0400 << 16) | (0xc798 >> 2), | |
391 | 0x00000000, | |
392 | (0x0400 << 16) | (0xc79c >> 2), | |
393 | 0x00000000, | |
394 | (0x0400 << 16) | (0xc7a0 >> 2), | |
395 | 0x00000000, | |
396 | (0x0400 << 16) | (0xc7a4 >> 2), | |
397 | 0x00000000, | |
398 | (0x0400 << 16) | (0xc7a8 >> 2), | |
399 | 0x00000000, | |
400 | (0x0400 << 16) | (0xc7ac >> 2), | |
401 | 0x00000000, | |
402 | (0x0400 << 16) | (0xc7b0 >> 2), | |
403 | 0x00000000, | |
404 | (0x0400 << 16) | (0xc7b4 >> 2), | |
405 | 0x00000000, | |
406 | (0x0e00 << 16) | (0x9100 >> 2), | |
407 | 0x00000000, | |
408 | (0x0e00 << 16) | (0x3c010 >> 2), | |
409 | 0x00000000, | |
410 | (0x0e00 << 16) | (0x92a8 >> 2), | |
411 | 0x00000000, | |
412 | (0x0e00 << 16) | (0x92ac >> 2), | |
413 | 0x00000000, | |
414 | (0x0e00 << 16) | (0x92b4 >> 2), | |
415 | 0x00000000, | |
416 | (0x0e00 << 16) | (0x92b8 >> 2), | |
417 | 0x00000000, | |
418 | (0x0e00 << 16) | (0x92bc >> 2), | |
419 | 0x00000000, | |
420 | (0x0e00 << 16) | (0x92c0 >> 2), | |
421 | 0x00000000, | |
422 | (0x0e00 << 16) | (0x92c4 >> 2), | |
423 | 0x00000000, | |
424 | (0x0e00 << 16) | (0x92c8 >> 2), | |
425 | 0x00000000, | |
426 | (0x0e00 << 16) | (0x92cc >> 2), | |
427 | 0x00000000, | |
428 | (0x0e00 << 16) | (0x92d0 >> 2), | |
429 | 0x00000000, | |
430 | (0x0e00 << 16) | (0x8c00 >> 2), | |
431 | 0x00000000, | |
432 | (0x0e00 << 16) | (0x8c04 >> 2), | |
433 | 0x00000000, | |
434 | (0x0e00 << 16) | (0x8c20 >> 2), | |
435 | 0x00000000, | |
436 | (0x0e00 << 16) | (0x8c38 >> 2), | |
437 | 0x00000000, | |
438 | (0x0e00 << 16) | (0x8c3c >> 2), | |
439 | 0x00000000, | |
440 | (0x0e00 << 16) | (0xae00 >> 2), | |
441 | 0x00000000, | |
442 | (0x0e00 << 16) | (0x9604 >> 2), | |
443 | 0x00000000, | |
444 | (0x0e00 << 16) | (0xac08 >> 2), | |
445 | 0x00000000, | |
446 | (0x0e00 << 16) | (0xac0c >> 2), | |
447 | 0x00000000, | |
448 | (0x0e00 << 16) | (0xac10 >> 2), | |
449 | 0x00000000, | |
450 | (0x0e00 << 16) | (0xac14 >> 2), | |
451 | 0x00000000, | |
452 | (0x0e00 << 16) | (0xac58 >> 2), | |
453 | 0x00000000, | |
454 | (0x0e00 << 16) | (0xac68 >> 2), | |
455 | 0x00000000, | |
456 | (0x0e00 << 16) | (0xac6c >> 2), | |
457 | 0x00000000, | |
458 | (0x0e00 << 16) | (0xac70 >> 2), | |
459 | 0x00000000, | |
460 | (0x0e00 << 16) | (0xac74 >> 2), | |
461 | 0x00000000, | |
462 | (0x0e00 << 16) | (0xac78 >> 2), | |
463 | 0x00000000, | |
464 | (0x0e00 << 16) | (0xac7c >> 2), | |
465 | 0x00000000, | |
466 | (0x0e00 << 16) | (0xac80 >> 2), | |
467 | 0x00000000, | |
468 | (0x0e00 << 16) | (0xac84 >> 2), | |
469 | 0x00000000, | |
470 | (0x0e00 << 16) | (0xac88 >> 2), | |
471 | 0x00000000, | |
472 | (0x0e00 << 16) | (0xac8c >> 2), | |
473 | 0x00000000, | |
474 | (0x0e00 << 16) | (0x970c >> 2), | |
475 | 0x00000000, | |
476 | (0x0e00 << 16) | (0x9714 >> 2), | |
477 | 0x00000000, | |
478 | (0x0e00 << 16) | (0x9718 >> 2), | |
479 | 0x00000000, | |
480 | (0x0e00 << 16) | (0x971c >> 2), | |
481 | 0x00000000, | |
482 | (0x0e00 << 16) | (0x31068 >> 2), | |
483 | 0x00000000, | |
484 | (0x4e00 << 16) | (0x31068 >> 2), | |
485 | 0x00000000, | |
486 | (0x5e00 << 16) | (0x31068 >> 2), | |
487 | 0x00000000, | |
488 | (0x6e00 << 16) | (0x31068 >> 2), | |
489 | 0x00000000, | |
490 | (0x7e00 << 16) | (0x31068 >> 2), | |
491 | 0x00000000, | |
492 | (0x8e00 << 16) | (0x31068 >> 2), | |
493 | 0x00000000, | |
494 | (0x9e00 << 16) | (0x31068 >> 2), | |
495 | 0x00000000, | |
496 | (0xae00 << 16) | (0x31068 >> 2), | |
497 | 0x00000000, | |
498 | (0xbe00 << 16) | (0x31068 >> 2), | |
499 | 0x00000000, | |
500 | (0x0e00 << 16) | (0xcd10 >> 2), | |
501 | 0x00000000, | |
502 | (0x0e00 << 16) | (0xcd14 >> 2), | |
503 | 0x00000000, | |
504 | (0x0e00 << 16) | (0x88b0 >> 2), | |
505 | 0x00000000, | |
506 | (0x0e00 << 16) | (0x88b4 >> 2), | |
507 | 0x00000000, | |
508 | (0x0e00 << 16) | (0x88b8 >> 2), | |
509 | 0x00000000, | |
510 | (0x0e00 << 16) | (0x88bc >> 2), | |
511 | 0x00000000, | |
512 | (0x0400 << 16) | (0x89c0 >> 2), | |
513 | 0x00000000, | |
514 | (0x0e00 << 16) | (0x88c4 >> 2), | |
515 | 0x00000000, | |
516 | (0x0e00 << 16) | (0x88c8 >> 2), | |
517 | 0x00000000, | |
518 | (0x0e00 << 16) | (0x88d0 >> 2), | |
519 | 0x00000000, | |
520 | (0x0e00 << 16) | (0x88d4 >> 2), | |
521 | 0x00000000, | |
522 | (0x0e00 << 16) | (0x88d8 >> 2), | |
523 | 0x00000000, | |
524 | (0x0e00 << 16) | (0x8980 >> 2), | |
525 | 0x00000000, | |
526 | (0x0e00 << 16) | (0x30938 >> 2), | |
527 | 0x00000000, | |
528 | (0x0e00 << 16) | (0x3093c >> 2), | |
529 | 0x00000000, | |
530 | (0x0e00 << 16) | (0x30940 >> 2), | |
531 | 0x00000000, | |
532 | (0x0e00 << 16) | (0x89a0 >> 2), | |
533 | 0x00000000, | |
534 | (0x0e00 << 16) | (0x30900 >> 2), | |
535 | 0x00000000, | |
536 | (0x0e00 << 16) | (0x30904 >> 2), | |
537 | 0x00000000, | |
538 | (0x0e00 << 16) | (0x89b4 >> 2), | |
539 | 0x00000000, | |
540 | (0x0e00 << 16) | (0x3c210 >> 2), | |
541 | 0x00000000, | |
542 | (0x0e00 << 16) | (0x3c214 >> 2), | |
543 | 0x00000000, | |
544 | (0x0e00 << 16) | (0x3c218 >> 2), | |
545 | 0x00000000, | |
546 | (0x0e00 << 16) | (0x8904 >> 2), | |
547 | 0x00000000, | |
548 | 0x5, | |
549 | (0x0e00 << 16) | (0x8c28 >> 2), | |
550 | (0x0e00 << 16) | (0x8c2c >> 2), | |
551 | (0x0e00 << 16) | (0x8c30 >> 2), | |
552 | (0x0e00 << 16) | (0x8c34 >> 2), | |
553 | (0x0e00 << 16) | (0x9600 >> 2), | |
554 | }; | |
555 | ||
556 | static const u32 kalindi_rlc_save_restore_register_list[] = | |
557 | { | |
558 | (0x0e00 << 16) | (0xc12c >> 2), | |
559 | 0x00000000, | |
560 | (0x0e00 << 16) | (0xc140 >> 2), | |
561 | 0x00000000, | |
562 | (0x0e00 << 16) | (0xc150 >> 2), | |
563 | 0x00000000, | |
564 | (0x0e00 << 16) | (0xc15c >> 2), | |
565 | 0x00000000, | |
566 | (0x0e00 << 16) | (0xc168 >> 2), | |
567 | 0x00000000, | |
568 | (0x0e00 << 16) | (0xc170 >> 2), | |
569 | 0x00000000, | |
570 | (0x0e00 << 16) | (0xc204 >> 2), | |
571 | 0x00000000, | |
572 | (0x0e00 << 16) | (0xc2b4 >> 2), | |
573 | 0x00000000, | |
574 | (0x0e00 << 16) | (0xc2b8 >> 2), | |
575 | 0x00000000, | |
576 | (0x0e00 << 16) | (0xc2bc >> 2), | |
577 | 0x00000000, | |
578 | (0x0e00 << 16) | (0xc2c0 >> 2), | |
579 | 0x00000000, | |
580 | (0x0e00 << 16) | (0x8228 >> 2), | |
581 | 0x00000000, | |
582 | (0x0e00 << 16) | (0x829c >> 2), | |
583 | 0x00000000, | |
584 | (0x0e00 << 16) | (0x869c >> 2), | |
585 | 0x00000000, | |
586 | (0x0600 << 16) | (0x98f4 >> 2), | |
587 | 0x00000000, | |
588 | (0x0e00 << 16) | (0x98f8 >> 2), | |
589 | 0x00000000, | |
590 | (0x0e00 << 16) | (0x9900 >> 2), | |
591 | 0x00000000, | |
592 | (0x0e00 << 16) | (0xc260 >> 2), | |
593 | 0x00000000, | |
594 | (0x0e00 << 16) | (0x90e8 >> 2), | |
595 | 0x00000000, | |
596 | (0x0e00 << 16) | (0x3c000 >> 2), | |
597 | 0x00000000, | |
598 | (0x0e00 << 16) | (0x3c00c >> 2), | |
599 | 0x00000000, | |
600 | (0x0e00 << 16) | (0x8c1c >> 2), | |
601 | 0x00000000, | |
602 | (0x0e00 << 16) | (0x9700 >> 2), | |
603 | 0x00000000, | |
604 | (0x0e00 << 16) | (0xcd20 >> 2), | |
605 | 0x00000000, | |
606 | (0x4e00 << 16) | (0xcd20 >> 2), | |
607 | 0x00000000, | |
608 | (0x5e00 << 16) | (0xcd20 >> 2), | |
609 | 0x00000000, | |
610 | (0x6e00 << 16) | (0xcd20 >> 2), | |
611 | 0x00000000, | |
612 | (0x7e00 << 16) | (0xcd20 >> 2), | |
613 | 0x00000000, | |
614 | (0x0e00 << 16) | (0x89bc >> 2), | |
615 | 0x00000000, | |
616 | (0x0e00 << 16) | (0x8900 >> 2), | |
617 | 0x00000000, | |
618 | 0x3, | |
619 | (0x0e00 << 16) | (0xc130 >> 2), | |
620 | 0x00000000, | |
621 | (0x0e00 << 16) | (0xc134 >> 2), | |
622 | 0x00000000, | |
623 | (0x0e00 << 16) | (0xc1fc >> 2), | |
624 | 0x00000000, | |
625 | (0x0e00 << 16) | (0xc208 >> 2), | |
626 | 0x00000000, | |
627 | (0x0e00 << 16) | (0xc264 >> 2), | |
628 | 0x00000000, | |
629 | (0x0e00 << 16) | (0xc268 >> 2), | |
630 | 0x00000000, | |
631 | (0x0e00 << 16) | (0xc26c >> 2), | |
632 | 0x00000000, | |
633 | (0x0e00 << 16) | (0xc270 >> 2), | |
634 | 0x00000000, | |
635 | (0x0e00 << 16) | (0xc274 >> 2), | |
636 | 0x00000000, | |
637 | (0x0e00 << 16) | (0xc28c >> 2), | |
638 | 0x00000000, | |
639 | (0x0e00 << 16) | (0xc290 >> 2), | |
640 | 0x00000000, | |
641 | (0x0e00 << 16) | (0xc294 >> 2), | |
642 | 0x00000000, | |
643 | (0x0e00 << 16) | (0xc298 >> 2), | |
644 | 0x00000000, | |
645 | (0x0e00 << 16) | (0xc2a0 >> 2), | |
646 | 0x00000000, | |
647 | (0x0e00 << 16) | (0xc2a4 >> 2), | |
648 | 0x00000000, | |
649 | (0x0e00 << 16) | (0xc2a8 >> 2), | |
650 | 0x00000000, | |
651 | (0x0e00 << 16) | (0xc2ac >> 2), | |
652 | 0x00000000, | |
653 | (0x0e00 << 16) | (0x301d0 >> 2), | |
654 | 0x00000000, | |
655 | (0x0e00 << 16) | (0x30238 >> 2), | |
656 | 0x00000000, | |
657 | (0x0e00 << 16) | (0x30250 >> 2), | |
658 | 0x00000000, | |
659 | (0x0e00 << 16) | (0x30254 >> 2), | |
660 | 0x00000000, | |
661 | (0x0e00 << 16) | (0x30258 >> 2), | |
662 | 0x00000000, | |
663 | (0x0e00 << 16) | (0x3025c >> 2), | |
664 | 0x00000000, | |
665 | (0x4e00 << 16) | (0xc900 >> 2), | |
666 | 0x00000000, | |
667 | (0x5e00 << 16) | (0xc900 >> 2), | |
668 | 0x00000000, | |
669 | (0x6e00 << 16) | (0xc900 >> 2), | |
670 | 0x00000000, | |
671 | (0x7e00 << 16) | (0xc900 >> 2), | |
672 | 0x00000000, | |
673 | (0x4e00 << 16) | (0xc904 >> 2), | |
674 | 0x00000000, | |
675 | (0x5e00 << 16) | (0xc904 >> 2), | |
676 | 0x00000000, | |
677 | (0x6e00 << 16) | (0xc904 >> 2), | |
678 | 0x00000000, | |
679 | (0x7e00 << 16) | (0xc904 >> 2), | |
680 | 0x00000000, | |
681 | (0x4e00 << 16) | (0xc908 >> 2), | |
682 | 0x00000000, | |
683 | (0x5e00 << 16) | (0xc908 >> 2), | |
684 | 0x00000000, | |
685 | (0x6e00 << 16) | (0xc908 >> 2), | |
686 | 0x00000000, | |
687 | (0x7e00 << 16) | (0xc908 >> 2), | |
688 | 0x00000000, | |
689 | (0x4e00 << 16) | (0xc90c >> 2), | |
690 | 0x00000000, | |
691 | (0x5e00 << 16) | (0xc90c >> 2), | |
692 | 0x00000000, | |
693 | (0x6e00 << 16) | (0xc90c >> 2), | |
694 | 0x00000000, | |
695 | (0x7e00 << 16) | (0xc90c >> 2), | |
696 | 0x00000000, | |
697 | (0x4e00 << 16) | (0xc910 >> 2), | |
698 | 0x00000000, | |
699 | (0x5e00 << 16) | (0xc910 >> 2), | |
700 | 0x00000000, | |
701 | (0x6e00 << 16) | (0xc910 >> 2), | |
702 | 0x00000000, | |
703 | (0x7e00 << 16) | (0xc910 >> 2), | |
704 | 0x00000000, | |
705 | (0x0e00 << 16) | (0xc99c >> 2), | |
706 | 0x00000000, | |
707 | (0x0e00 << 16) | (0x9834 >> 2), | |
708 | 0x00000000, | |
709 | (0x0000 << 16) | (0x30f00 >> 2), | |
710 | 0x00000000, | |
711 | (0x0000 << 16) | (0x30f04 >> 2), | |
712 | 0x00000000, | |
713 | (0x0000 << 16) | (0x30f08 >> 2), | |
714 | 0x00000000, | |
715 | (0x0000 << 16) | (0x30f0c >> 2), | |
716 | 0x00000000, | |
717 | (0x0600 << 16) | (0x9b7c >> 2), | |
718 | 0x00000000, | |
719 | (0x0e00 << 16) | (0x8a14 >> 2), | |
720 | 0x00000000, | |
721 | (0x0e00 << 16) | (0x8a18 >> 2), | |
722 | 0x00000000, | |
723 | (0x0600 << 16) | (0x30a00 >> 2), | |
724 | 0x00000000, | |
725 | (0x0e00 << 16) | (0x8bf0 >> 2), | |
726 | 0x00000000, | |
727 | (0x0e00 << 16) | (0x8bcc >> 2), | |
728 | 0x00000000, | |
729 | (0x0e00 << 16) | (0x8b24 >> 2), | |
730 | 0x00000000, | |
731 | (0x0e00 << 16) | (0x30a04 >> 2), | |
732 | 0x00000000, | |
733 | (0x0600 << 16) | (0x30a10 >> 2), | |
734 | 0x00000000, | |
735 | (0x0600 << 16) | (0x30a14 >> 2), | |
736 | 0x00000000, | |
737 | (0x0600 << 16) | (0x30a18 >> 2), | |
738 | 0x00000000, | |
739 | (0x0600 << 16) | (0x30a2c >> 2), | |
740 | 0x00000000, | |
741 | (0x0e00 << 16) | (0xc700 >> 2), | |
742 | 0x00000000, | |
743 | (0x0e00 << 16) | (0xc704 >> 2), | |
744 | 0x00000000, | |
745 | (0x0e00 << 16) | (0xc708 >> 2), | |
746 | 0x00000000, | |
747 | (0x0e00 << 16) | (0xc768 >> 2), | |
748 | 0x00000000, | |
749 | (0x0400 << 16) | (0xc770 >> 2), | |
750 | 0x00000000, | |
751 | (0x0400 << 16) | (0xc774 >> 2), | |
752 | 0x00000000, | |
753 | (0x0400 << 16) | (0xc798 >> 2), | |
754 | 0x00000000, | |
755 | (0x0400 << 16) | (0xc79c >> 2), | |
756 | 0x00000000, | |
757 | (0x0e00 << 16) | (0x9100 >> 2), | |
758 | 0x00000000, | |
759 | (0x0e00 << 16) | (0x3c010 >> 2), | |
760 | 0x00000000, | |
761 | (0x0e00 << 16) | (0x8c00 >> 2), | |
762 | 0x00000000, | |
763 | (0x0e00 << 16) | (0x8c04 >> 2), | |
764 | 0x00000000, | |
765 | (0x0e00 << 16) | (0x8c20 >> 2), | |
766 | 0x00000000, | |
767 | (0x0e00 << 16) | (0x8c38 >> 2), | |
768 | 0x00000000, | |
769 | (0x0e00 << 16) | (0x8c3c >> 2), | |
770 | 0x00000000, | |
771 | (0x0e00 << 16) | (0xae00 >> 2), | |
772 | 0x00000000, | |
773 | (0x0e00 << 16) | (0x9604 >> 2), | |
774 | 0x00000000, | |
775 | (0x0e00 << 16) | (0xac08 >> 2), | |
776 | 0x00000000, | |
777 | (0x0e00 << 16) | (0xac0c >> 2), | |
778 | 0x00000000, | |
779 | (0x0e00 << 16) | (0xac10 >> 2), | |
780 | 0x00000000, | |
781 | (0x0e00 << 16) | (0xac14 >> 2), | |
782 | 0x00000000, | |
783 | (0x0e00 << 16) | (0xac58 >> 2), | |
784 | 0x00000000, | |
785 | (0x0e00 << 16) | (0xac68 >> 2), | |
786 | 0x00000000, | |
787 | (0x0e00 << 16) | (0xac6c >> 2), | |
788 | 0x00000000, | |
789 | (0x0e00 << 16) | (0xac70 >> 2), | |
790 | 0x00000000, | |
791 | (0x0e00 << 16) | (0xac74 >> 2), | |
792 | 0x00000000, | |
793 | (0x0e00 << 16) | (0xac78 >> 2), | |
794 | 0x00000000, | |
795 | (0x0e00 << 16) | (0xac7c >> 2), | |
796 | 0x00000000, | |
797 | (0x0e00 << 16) | (0xac80 >> 2), | |
798 | 0x00000000, | |
799 | (0x0e00 << 16) | (0xac84 >> 2), | |
800 | 0x00000000, | |
801 | (0x0e00 << 16) | (0xac88 >> 2), | |
802 | 0x00000000, | |
803 | (0x0e00 << 16) | (0xac8c >> 2), | |
804 | 0x00000000, | |
805 | (0x0e00 << 16) | (0x970c >> 2), | |
806 | 0x00000000, | |
807 | (0x0e00 << 16) | (0x9714 >> 2), | |
808 | 0x00000000, | |
809 | (0x0e00 << 16) | (0x9718 >> 2), | |
810 | 0x00000000, | |
811 | (0x0e00 << 16) | (0x971c >> 2), | |
812 | 0x00000000, | |
813 | (0x0e00 << 16) | (0x31068 >> 2), | |
814 | 0x00000000, | |
815 | (0x4e00 << 16) | (0x31068 >> 2), | |
816 | 0x00000000, | |
817 | (0x5e00 << 16) | (0x31068 >> 2), | |
818 | 0x00000000, | |
819 | (0x6e00 << 16) | (0x31068 >> 2), | |
820 | 0x00000000, | |
821 | (0x7e00 << 16) | (0x31068 >> 2), | |
822 | 0x00000000, | |
823 | (0x0e00 << 16) | (0xcd10 >> 2), | |
824 | 0x00000000, | |
825 | (0x0e00 << 16) | (0xcd14 >> 2), | |
826 | 0x00000000, | |
827 | (0x0e00 << 16) | (0x88b0 >> 2), | |
828 | 0x00000000, | |
829 | (0x0e00 << 16) | (0x88b4 >> 2), | |
830 | 0x00000000, | |
831 | (0x0e00 << 16) | (0x88b8 >> 2), | |
832 | 0x00000000, | |
833 | (0x0e00 << 16) | (0x88bc >> 2), | |
834 | 0x00000000, | |
835 | (0x0400 << 16) | (0x89c0 >> 2), | |
836 | 0x00000000, | |
837 | (0x0e00 << 16) | (0x88c4 >> 2), | |
838 | 0x00000000, | |
839 | (0x0e00 << 16) | (0x88c8 >> 2), | |
840 | 0x00000000, | |
841 | (0x0e00 << 16) | (0x88d0 >> 2), | |
842 | 0x00000000, | |
843 | (0x0e00 << 16) | (0x88d4 >> 2), | |
844 | 0x00000000, | |
845 | (0x0e00 << 16) | (0x88d8 >> 2), | |
846 | 0x00000000, | |
847 | (0x0e00 << 16) | (0x8980 >> 2), | |
848 | 0x00000000, | |
849 | (0x0e00 << 16) | (0x30938 >> 2), | |
850 | 0x00000000, | |
851 | (0x0e00 << 16) | (0x3093c >> 2), | |
852 | 0x00000000, | |
853 | (0x0e00 << 16) | (0x30940 >> 2), | |
854 | 0x00000000, | |
855 | (0x0e00 << 16) | (0x89a0 >> 2), | |
856 | 0x00000000, | |
857 | (0x0e00 << 16) | (0x30900 >> 2), | |
858 | 0x00000000, | |
859 | (0x0e00 << 16) | (0x30904 >> 2), | |
860 | 0x00000000, | |
861 | (0x0e00 << 16) | (0x89b4 >> 2), | |
862 | 0x00000000, | |
863 | (0x0e00 << 16) | (0x3e1fc >> 2), | |
864 | 0x00000000, | |
865 | (0x0e00 << 16) | (0x3c210 >> 2), | |
866 | 0x00000000, | |
867 | (0x0e00 << 16) | (0x3c214 >> 2), | |
868 | 0x00000000, | |
869 | (0x0e00 << 16) | (0x3c218 >> 2), | |
870 | 0x00000000, | |
871 | (0x0e00 << 16) | (0x8904 >> 2), | |
872 | 0x00000000, | |
873 | 0x5, | |
874 | (0x0e00 << 16) | (0x8c28 >> 2), | |
875 | (0x0e00 << 16) | (0x8c2c >> 2), | |
876 | (0x0e00 << 16) | (0x8c30 >> 2), | |
877 | (0x0e00 << 16) | (0x8c34 >> 2), | |
878 | (0x0e00 << 16) | (0x9600 >> 2), | |
879 | }; | |
880 | ||
881 | static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); | |
882 | static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); | |
883 | static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev); | |
884 | static void gfx_v7_0_init_pg(struct amdgpu_device *adev); | |
885 | ||
886 | /* | |
887 | * Core functions | |
888 | */ | |
889 | /** | |
890 | * gfx_v7_0_init_microcode - load ucode images from disk | |
891 | * | |
892 | * @adev: amdgpu_device pointer | |
893 | * | |
894 | * Use the firmware interface to load the ucode images into | |
895 | * the driver (not loaded into hw). | |
896 | * Returns 0 on success, error on failure. | |
897 | */ | |
898 | static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) | |
899 | { | |
900 | const char *chip_name; | |
901 | char fw_name[30]; | |
902 | int err; | |
903 | ||
904 | DRM_DEBUG("\n"); | |
905 | ||
906 | switch (adev->asic_type) { | |
907 | case CHIP_BONAIRE: | |
908 | chip_name = "bonaire"; | |
909 | break; | |
910 | case CHIP_HAWAII: | |
911 | chip_name = "hawaii"; | |
912 | break; | |
913 | case CHIP_KAVERI: | |
914 | chip_name = "kaveri"; | |
915 | break; | |
916 | case CHIP_KABINI: | |
917 | chip_name = "kabini"; | |
918 | break; | |
919 | case CHIP_MULLINS: | |
920 | chip_name = "mullins"; | |
921 | break; | |
922 | default: BUG(); | |
923 | } | |
924 | ||
925 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); | |
926 | err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); | |
927 | if (err) | |
928 | goto out; | |
929 | err = amdgpu_ucode_validate(adev->gfx.pfp_fw); | |
930 | if (err) | |
931 | goto out; | |
932 | ||
933 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); | |
934 | err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); | |
935 | if (err) | |
936 | goto out; | |
937 | err = amdgpu_ucode_validate(adev->gfx.me_fw); | |
938 | if (err) | |
939 | goto out; | |
940 | ||
941 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); | |
942 | err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); | |
943 | if (err) | |
944 | goto out; | |
945 | err = amdgpu_ucode_validate(adev->gfx.ce_fw); | |
946 | if (err) | |
947 | goto out; | |
948 | ||
949 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); | |
950 | err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); | |
951 | if (err) | |
952 | goto out; | |
953 | err = amdgpu_ucode_validate(adev->gfx.mec_fw); | |
954 | if (err) | |
955 | goto out; | |
956 | ||
957 | if (adev->asic_type == CHIP_KAVERI) { | |
958 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name); | |
959 | err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); | |
960 | if (err) | |
961 | goto out; | |
962 | err = amdgpu_ucode_validate(adev->gfx.mec2_fw); | |
963 | if (err) | |
964 | goto out; | |
965 | } | |
966 | ||
967 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); | |
968 | err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); | |
969 | if (err) | |
970 | goto out; | |
971 | err = amdgpu_ucode_validate(adev->gfx.rlc_fw); | |
972 | ||
973 | out: | |
974 | if (err) { | |
975 | printk(KERN_ERR | |
976 | "gfx7: Failed to load firmware \"%s\"\n", | |
977 | fw_name); | |
978 | release_firmware(adev->gfx.pfp_fw); | |
979 | adev->gfx.pfp_fw = NULL; | |
980 | release_firmware(adev->gfx.me_fw); | |
981 | adev->gfx.me_fw = NULL; | |
982 | release_firmware(adev->gfx.ce_fw); | |
983 | adev->gfx.ce_fw = NULL; | |
984 | release_firmware(adev->gfx.mec_fw); | |
985 | adev->gfx.mec_fw = NULL; | |
986 | release_firmware(adev->gfx.mec2_fw); | |
987 | adev->gfx.mec2_fw = NULL; | |
988 | release_firmware(adev->gfx.rlc_fw); | |
989 | adev->gfx.rlc_fw = NULL; | |
990 | } | |
991 | return err; | |
992 | } | |
993 | ||
994 | /** | |
995 | * gfx_v7_0_tiling_mode_table_init - init the hw tiling table | |
996 | * | |
997 | * @adev: amdgpu_device pointer | |
998 | * | |
999 | * Starting with SI, the tiling setup is done globally in a | |
1000 | * set of 32 tiling modes. Rather than selecting each set of | |
1001 | * parameters per surface as on older asics, we just select | |
1002 | * which index in the tiling table we want to use, and the | |
1003 | * surface uses those parameters (CIK). | |
1004 | */ | |
1005 | static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) | |
1006 | { | |
840a20d3 TSD |
1007 | const u32 num_tile_mode_states = |
1008 | ARRAY_SIZE(adev->gfx.config.tile_mode_array); | |
1009 | const u32 num_secondary_tile_mode_states = | |
1010 | ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); | |
1011 | u32 reg_offset, split_equal_to_row_size; | |
1012 | uint32_t *tile, *macrotile; | |
1013 | ||
1014 | tile = adev->gfx.config.tile_mode_array; | |
1015 | macrotile = adev->gfx.config.macrotile_mode_array; | |
a2e73f56 AD |
1016 | |
1017 | switch (adev->gfx.config.mem_row_size_in_kb) { | |
1018 | case 1: | |
1019 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; | |
1020 | break; | |
1021 | case 2: | |
1022 | default: | |
1023 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; | |
1024 | break; | |
1025 | case 4: | |
1026 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; | |
1027 | break; | |
1028 | } | |
1029 | ||
840a20d3 TSD |
1030 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
1031 | tile[reg_offset] = 0; | |
1032 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) | |
1033 | macrotile[reg_offset] = 0; | |
1034 | ||
a2e73f56 AD |
1035 | switch (adev->asic_type) { |
1036 | case CHIP_BONAIRE: | |
840a20d3 TSD |
1037 | tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
1038 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1039 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1040 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1041 | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1042 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1043 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | | |
1044 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1045 | tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1046 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1047 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1048 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1049 | tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1050 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1051 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | |
1052 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1053 | tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1054 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1055 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1056 | TILE_SPLIT(split_equal_to_row_size)); | |
1057 | tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1058 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1059 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1060 | tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1061 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1062 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1063 | TILE_SPLIT(split_equal_to_row_size)); | |
1064 | tile[7] = (TILE_SPLIT(split_equal_to_row_size)); | |
1065 | tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | | |
1066 | PIPE_CONFIG(ADDR_SURF_P4_16x16)); | |
1067 | tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1068 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1069 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); | |
1070 | tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1071 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1072 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1073 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1074 | tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1075 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1076 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1077 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1078 | tile[12] = (TILE_SPLIT(split_equal_to_row_size)); | |
1079 | tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1080 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1081 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); | |
1082 | tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1083 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1084 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1085 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1086 | tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | | |
1087 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1088 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1089 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1090 | tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1091 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1092 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1093 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1094 | tile[17] = (TILE_SPLIT(split_equal_to_row_size)); | |
1095 | tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | | |
1096 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1097 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1098 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1099 | tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | | |
1100 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1101 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); | |
1102 | tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | | |
1103 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1104 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1105 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1106 | tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | | |
1107 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1108 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1109 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1110 | tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | | |
1111 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1112 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1113 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1114 | tile[23] = (TILE_SPLIT(split_equal_to_row_size)); | |
1115 | tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | | |
1116 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1117 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1118 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1119 | tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | | |
1120 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1121 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1122 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1123 | tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | | |
1124 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1125 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1126 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1127 | tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1128 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1129 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); | |
1130 | tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1131 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1132 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | | |
1133 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1134 | tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1135 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1136 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | | |
1137 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1138 | tile[30] = (TILE_SPLIT(split_equal_to_row_size)); | |
1139 | ||
1140 | macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1141 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1142 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1143 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1144 | macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1145 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1146 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1147 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1148 | macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1149 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1150 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1151 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1152 | macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1153 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1154 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1155 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1156 | macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1157 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1158 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1159 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1160 | macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1161 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1162 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1163 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1164 | macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1165 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1166 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | |
1167 | NUM_BANKS(ADDR_SURF_4_BANK)); | |
1168 | macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | | |
1169 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | | |
1170 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1171 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1172 | macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | | |
1173 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1174 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1175 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1176 | macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1177 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1178 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1179 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1180 | macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1181 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1182 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1183 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1184 | macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1185 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1186 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1187 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1188 | macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1189 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1190 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1191 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1192 | macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1193 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1194 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | |
1195 | NUM_BANKS(ADDR_SURF_4_BANK)); | |
a2e73f56 | 1196 | |
840a20d3 TSD |
1197 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
1198 | WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); | |
1199 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) | |
1200 | if (reg_offset != 7) | |
1201 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); | |
a2e73f56 AD |
1202 | break; |
1203 | case CHIP_HAWAII: | |
840a20d3 TSD |
1204 | tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
1205 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1206 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1207 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1208 | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1209 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1210 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | | |
1211 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1212 | tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1213 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1214 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1215 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1216 | tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1217 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1218 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | |
1219 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1220 | tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1221 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1222 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1223 | TILE_SPLIT(split_equal_to_row_size)); | |
1224 | tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1225 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1226 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1227 | TILE_SPLIT(split_equal_to_row_size)); | |
1228 | tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1229 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1230 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1231 | TILE_SPLIT(split_equal_to_row_size)); | |
1232 | tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1233 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1234 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1235 | TILE_SPLIT(split_equal_to_row_size)); | |
1236 | tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | | |
1237 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); | |
1238 | tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1239 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1240 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); | |
1241 | tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1242 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1243 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1244 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1245 | tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1246 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1247 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1248 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1249 | tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | | |
1250 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1251 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1252 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1253 | tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1254 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1255 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); | |
1256 | tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1257 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1258 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1259 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1260 | tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | | |
1261 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1262 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1263 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1264 | tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1265 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1266 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1267 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1268 | tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1269 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1270 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1271 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1272 | tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | | |
1273 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1274 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1275 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1276 | tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | | |
1277 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1278 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); | |
1279 | tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | | |
1280 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1281 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1282 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1283 | tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | | |
1284 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1285 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1286 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1287 | tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | | |
1288 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1289 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1290 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1291 | tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | | |
1292 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1293 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1294 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1295 | tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | | |
1296 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1297 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1298 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1299 | tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | | |
1300 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1301 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1302 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1303 | tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | | |
1304 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1305 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1306 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1307 | tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1308 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1309 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); | |
1310 | tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1311 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1312 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | | |
1313 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1314 | tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1315 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | | |
1316 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | | |
1317 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1318 | tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1319 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | | |
1320 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | | |
1321 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
a2e73f56 | 1322 | |
840a20d3 TSD |
1323 | macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
1324 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1325 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1326 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1327 | macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1328 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1329 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1330 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1331 | macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1332 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1333 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | |
1334 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1335 | macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1336 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1337 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | |
1338 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1339 | macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1340 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1341 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | |
1342 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1343 | macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1344 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1345 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | |
1346 | NUM_BANKS(ADDR_SURF_4_BANK)); | |
1347 | macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1348 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1349 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | |
1350 | NUM_BANKS(ADDR_SURF_4_BANK)); | |
1351 | macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1352 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1353 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1354 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1355 | macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1356 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1357 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1358 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1359 | macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1360 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1361 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | |
1362 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1363 | macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1364 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1365 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | |
1366 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1367 | macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1368 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1369 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1370 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1371 | macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1372 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1373 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1374 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1375 | macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1376 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1377 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | | |
1378 | NUM_BANKS(ADDR_SURF_4_BANK)); | |
1379 | ||
1380 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) | |
1381 | WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); | |
1382 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) | |
1383 | if (reg_offset != 7) | |
1384 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); | |
a2e73f56 AD |
1385 | break; |
1386 | case CHIP_KABINI: | |
1387 | case CHIP_KAVERI: | |
1388 | case CHIP_MULLINS: | |
1389 | default: | |
840a20d3 TSD |
1390 | tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
1391 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1392 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1393 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1394 | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1395 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1396 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | | |
1397 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1398 | tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1399 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1400 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1401 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1402 | tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1403 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1404 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | |
1405 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1406 | tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1407 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1408 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1409 | TILE_SPLIT(split_equal_to_row_size)); | |
1410 | tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1411 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1412 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); | |
1413 | tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1414 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1415 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1416 | TILE_SPLIT(split_equal_to_row_size)); | |
1417 | tile[7] = (TILE_SPLIT(split_equal_to_row_size)); | |
1418 | tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | | |
1419 | PIPE_CONFIG(ADDR_SURF_P2)); | |
1420 | tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1421 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1422 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); | |
1423 | tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1424 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1425 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1426 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1427 | tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1428 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1429 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1430 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1431 | tile[12] = (TILE_SPLIT(split_equal_to_row_size)); | |
1432 | tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1433 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1434 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); | |
1435 | tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1436 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1437 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1438 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1439 | tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | | |
1440 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1441 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1442 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1443 | tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1444 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1445 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1446 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1447 | tile[17] = (TILE_SPLIT(split_equal_to_row_size)); | |
1448 | tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | | |
1449 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1450 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1451 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1452 | tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | | |
1453 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1454 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); | |
1455 | tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | | |
1456 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1457 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1458 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1459 | tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | | |
1460 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1461 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1462 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1463 | tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | | |
1464 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1465 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1466 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1467 | tile[23] = (TILE_SPLIT(split_equal_to_row_size)); | |
1468 | tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | | |
1469 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1470 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | | |
1471 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1472 | tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | | |
1473 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1474 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1475 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1476 | tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | | |
1477 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1478 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | | |
1479 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); | |
1480 | tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1481 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1482 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); | |
1483 | tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1484 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1485 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | | |
1486 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); | |
1487 | tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | | |
1488 | PIPE_CONFIG(ADDR_SURF_P2) | | |
1489 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | | |
1490 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); | |
1491 | tile[30] = (TILE_SPLIT(split_equal_to_row_size)); | |
1492 | ||
1493 | macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1494 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1495 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1496 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1497 | macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1498 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1499 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1500 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1501 | macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1502 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1503 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1504 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1505 | macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1506 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1507 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1508 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1509 | macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1510 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1511 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1512 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1513 | macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1514 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1515 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1516 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1517 | macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1518 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1519 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1520 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
1521 | macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | | |
1522 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | | |
1523 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1524 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1525 | macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | | |
1526 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1527 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1528 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1529 | macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | | |
1530 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1531 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1532 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1533 | macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | | |
1534 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1535 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1536 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1537 | macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1538 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1539 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1540 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1541 | macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1542 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1543 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | | |
1544 | NUM_BANKS(ADDR_SURF_16_BANK)); | |
1545 | macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1546 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1547 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | | |
1548 | NUM_BANKS(ADDR_SURF_8_BANK)); | |
a2e73f56 | 1549 | |
840a20d3 TSD |
1550 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
1551 | WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); | |
1552 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) | |
1553 | if (reg_offset != 7) | |
1554 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); | |
a2e73f56 AD |
1555 | break; |
1556 | } | |
1557 | } | |
1558 | ||
1559 | /** | |
1560 | * gfx_v7_0_select_se_sh - select which SE, SH to address | |
1561 | * | |
1562 | * @adev: amdgpu_device pointer | |
1563 | * @se_num: shader engine to address | |
1564 | * @sh_num: sh block to address | |
1565 | * | |
1566 | * Select which SE, SH combinations to address. Certain | |
1567 | * registers are instanced per SE or SH. 0xffffffff means | |
1568 | * broadcast to all SEs or SHs (CIK). | |
1569 | */ | |
1570 | void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num) | |
1571 | { | |
1572 | u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK; | |
1573 | ||
1574 | if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) | |
1575 | data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | | |
1576 | GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; | |
1577 | else if (se_num == 0xffffffff) | |
1578 | data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | | |
1579 | (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); | |
1580 | else if (sh_num == 0xffffffff) | |
1581 | data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | | |
1582 | (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); | |
1583 | else | |
1584 | data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | | |
1585 | (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); | |
1586 | WREG32(mmGRBM_GFX_INDEX, data); | |
1587 | } | |
1588 | ||
1589 | /** | |
1590 | * gfx_v7_0_create_bitmask - create a bitmask | |
1591 | * | |
1592 | * @bit_width: length of the mask | |
1593 | * | |
1594 | * create a variable length bit mask (CIK). | |
1595 | * Returns the bitmask. | |
1596 | */ | |
1597 | static u32 gfx_v7_0_create_bitmask(u32 bit_width) | |
1598 | { | |
8f8e00c1 | 1599 | return (u32)((1ULL << bit_width) - 1); |
a2e73f56 AD |
1600 | } |
1601 | ||
1602 | /** | |
8f8e00c1 | 1603 | * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs |
a2e73f56 AD |
1604 | * |
1605 | * @adev: amdgpu_device pointer | |
a2e73f56 | 1606 | * |
8f8e00c1 AD |
1607 | * Calculates the bitmask of enabled RBs (CIK). |
1608 | * Returns the enabled RB bitmask. | |
a2e73f56 | 1609 | */ |
8f8e00c1 | 1610 | static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) |
a2e73f56 AD |
1611 | { |
1612 | u32 data, mask; | |
1613 | ||
1614 | data = RREG32(mmCC_RB_BACKEND_DISABLE); | |
a2e73f56 AD |
1615 | data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); |
1616 | ||
8f8e00c1 | 1617 | data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; |
a2e73f56 AD |
1618 | data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; |
1619 | ||
8f8e00c1 AD |
1620 | mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se / |
1621 | adev->gfx.config.max_sh_per_se); | |
a2e73f56 | 1622 | |
8f8e00c1 | 1623 | return (~data) & mask; |
a2e73f56 AD |
1624 | } |
1625 | ||
1626 | /** | |
1627 | * gfx_v7_0_setup_rb - setup the RBs on the asic | |
1628 | * | |
1629 | * @adev: amdgpu_device pointer | |
1630 | * @se_num: number of SEs (shader engines) for the asic | |
1631 | * @sh_per_se: number of SH blocks per SE for the asic | |
a2e73f56 AD |
1632 | * |
1633 | * Configures per-SE/SH RB registers (CIK). | |
1634 | */ | |
8f8e00c1 | 1635 | static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) |
a2e73f56 AD |
1636 | { |
1637 | int i, j; | |
aac1e3ca | 1638 | u32 data; |
8f8e00c1 | 1639 | u32 active_rbs = 0; |
6157bd7a FC |
1640 | u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / |
1641 | adev->gfx.config.max_sh_per_se; | |
a2e73f56 AD |
1642 | |
1643 | mutex_lock(&adev->grbm_idx_mutex); | |
8f8e00c1 AD |
1644 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
1645 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { | |
a2e73f56 | 1646 | gfx_v7_0_select_se_sh(adev, i, j); |
8f8e00c1 | 1647 | data = gfx_v7_0_get_rb_active_bitmap(adev); |
6157bd7a FC |
1648 | active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * |
1649 | rb_bitmap_width_per_sh); | |
a2e73f56 AD |
1650 | } |
1651 | } | |
1652 | gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); | |
1653 | mutex_unlock(&adev->grbm_idx_mutex); | |
1654 | ||
8f8e00c1 | 1655 | adev->gfx.config.backend_enable_mask = active_rbs; |
aac1e3ca | 1656 | adev->gfx.config.num_rbs = hweight32(active_rbs); |
a2e73f56 AD |
1657 | } |
1658 | ||
cd06bf68 BG |
1659 | /** |
1660 | * gmc_v7_0_init_compute_vmid - gart enable | |
1661 | * | |
1662 | * @rdev: amdgpu_device pointer | |
1663 | * | |
1664 | * Initialize compute vmid sh_mem registers | |
1665 | * | |
1666 | */ | |
1667 | #define DEFAULT_SH_MEM_BASES (0x6000) | |
1668 | #define FIRST_COMPUTE_VMID (8) | |
1669 | #define LAST_COMPUTE_VMID (16) | |
1670 | static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) | |
1671 | { | |
1672 | int i; | |
1673 | uint32_t sh_mem_config; | |
1674 | uint32_t sh_mem_bases; | |
1675 | ||
1676 | /* | |
1677 | * Configure apertures: | |
1678 | * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) | |
1679 | * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) | |
1680 | * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) | |
1681 | */ | |
1682 | sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); | |
1683 | sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << | |
1684 | SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; | |
1685 | sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; | |
1686 | mutex_lock(&adev->srbm_mutex); | |
1687 | for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { | |
1688 | cik_srbm_select(adev, 0, 0, 0, i); | |
1689 | /* CP and shaders */ | |
1690 | WREG32(mmSH_MEM_CONFIG, sh_mem_config); | |
1691 | WREG32(mmSH_MEM_APE1_BASE, 1); | |
1692 | WREG32(mmSH_MEM_APE1_LIMIT, 0); | |
1693 | WREG32(mmSH_MEM_BASES, sh_mem_bases); | |
1694 | } | |
1695 | cik_srbm_select(adev, 0, 0, 0, 0); | |
1696 | mutex_unlock(&adev->srbm_mutex); | |
1697 | } | |
1698 | ||
a2e73f56 AD |
1699 | /** |
1700 | * gfx_v7_0_gpu_init - setup the 3D engine | |
1701 | * | |
1702 | * @adev: amdgpu_device pointer | |
1703 | * | |
1704 | * Configures the 3D engine and tiling configuration | |
1705 | * registers so that the 3D engine is usable. | |
1706 | */ | |
1707 | static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) | |
1708 | { | |
d93f3ca7 | 1709 | u32 tmp, sh_mem_cfg; |
a2e73f56 AD |
1710 | int i; |
1711 | ||
a2e73f56 AD |
1712 | WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); |
1713 | ||
d93f3ca7 AD |
1714 | WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); |
1715 | WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); | |
1716 | WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); | |
a2e73f56 AD |
1717 | |
1718 | gfx_v7_0_tiling_mode_table_init(adev); | |
1719 | ||
8f8e00c1 | 1720 | gfx_v7_0_setup_rb(adev); |
a2e73f56 AD |
1721 | |
1722 | /* set HW defaults for 3D engine */ | |
1723 | WREG32(mmCP_MEQ_THRESHOLDS, | |
d93f3ca7 AD |
1724 | (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | |
1725 | (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); | |
a2e73f56 AD |
1726 | |
1727 | mutex_lock(&adev->grbm_idx_mutex); | |
1728 | /* | |
1729 | * making sure that the following register writes will be broadcasted | |
1730 | * to all the shaders | |
1731 | */ | |
1732 | gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); | |
1733 | ||
1734 | /* XXX SH_MEM regs */ | |
1735 | /* where to put LDS, scratch, GPUVM in FSA64 space */ | |
d93f3ca7 | 1736 | sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, |
74a5d165 JX |
1737 | SH_MEM_ALIGNMENT_MODE_UNALIGNED); |
1738 | ||
a2e73f56 AD |
1739 | mutex_lock(&adev->srbm_mutex); |
1740 | for (i = 0; i < 16; i++) { | |
1741 | cik_srbm_select(adev, 0, 0, 0, i); | |
1742 | /* CP and shaders */ | |
74a5d165 | 1743 | WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); |
a2e73f56 AD |
1744 | WREG32(mmSH_MEM_APE1_BASE, 1); |
1745 | WREG32(mmSH_MEM_APE1_LIMIT, 0); | |
1746 | WREG32(mmSH_MEM_BASES, 0); | |
1747 | } | |
1748 | cik_srbm_select(adev, 0, 0, 0, 0); | |
1749 | mutex_unlock(&adev->srbm_mutex); | |
1750 | ||
cd06bf68 BG |
1751 | gmc_v7_0_init_compute_vmid(adev); |
1752 | ||
a2e73f56 AD |
1753 | WREG32(mmSX_DEBUG_1, 0x20); |
1754 | ||
1755 | WREG32(mmTA_CNTL_AUX, 0x00010000); | |
1756 | ||
1757 | tmp = RREG32(mmSPI_CONFIG_CNTL); | |
1758 | tmp |= 0x03000000; | |
1759 | WREG32(mmSPI_CONFIG_CNTL, tmp); | |
1760 | ||
1761 | WREG32(mmSQ_CONFIG, 1); | |
1762 | ||
1763 | WREG32(mmDB_DEBUG, 0); | |
1764 | ||
1765 | tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; | |
1766 | tmp |= 0x00000400; | |
1767 | WREG32(mmDB_DEBUG2, tmp); | |
1768 | ||
1769 | tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; | |
1770 | tmp |= 0x00020200; | |
1771 | WREG32(mmDB_DEBUG3, tmp); | |
1772 | ||
1773 | tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; | |
1774 | tmp |= 0x00018208; | |
1775 | WREG32(mmCB_HW_CONTROL, tmp); | |
1776 | ||
1777 | WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); | |
1778 | ||
1779 | WREG32(mmPA_SC_FIFO_SIZE, | |
1780 | ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | | |
1781 | (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | | |
1782 | (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | | |
1783 | (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); | |
1784 | ||
1785 | WREG32(mmVGT_NUM_INSTANCES, 1); | |
1786 | ||
1787 | WREG32(mmCP_PERFMON_CNTL, 0); | |
1788 | ||
1789 | WREG32(mmSQ_CONFIG, 0); | |
1790 | ||
1791 | WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, | |
1792 | ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | | |
1793 | (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); | |
1794 | ||
1795 | WREG32(mmVGT_CACHE_INVALIDATION, | |
1796 | (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | | |
1797 | (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); | |
1798 | ||
1799 | WREG32(mmVGT_GS_VERTEX_REUSE, 16); | |
1800 | WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); | |
1801 | ||
1802 | WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | | |
1803 | (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); | |
1804 | WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); | |
1805 | mutex_unlock(&adev->grbm_idx_mutex); | |
1806 | ||
1807 | udelay(50); | |
1808 | } | |
1809 | ||
1810 | /* | |
1811 | * GPU scratch registers helpers function. | |
1812 | */ | |
1813 | /** | |
1814 | * gfx_v7_0_scratch_init - setup driver info for CP scratch regs | |
1815 | * | |
1816 | * @adev: amdgpu_device pointer | |
1817 | * | |
1818 | * Set up the number and offset of the CP scratch registers. | |
1819 | * NOTE: use of CP scratch registers is a legacy inferface and | |
1820 | * is not used by default on newer asics (r6xx+). On newer asics, | |
1821 | * memory buffers are used for fences rather than scratch regs. | |
1822 | */ | |
1823 | static void gfx_v7_0_scratch_init(struct amdgpu_device *adev) | |
1824 | { | |
1825 | int i; | |
1826 | ||
1827 | adev->gfx.scratch.num_reg = 7; | |
1828 | adev->gfx.scratch.reg_base = mmSCRATCH_REG0; | |
1829 | for (i = 0; i < adev->gfx.scratch.num_reg; i++) { | |
1830 | adev->gfx.scratch.free[i] = true; | |
1831 | adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; | |
1832 | } | |
1833 | } | |
1834 | ||
1835 | /** | |
1836 | * gfx_v7_0_ring_test_ring - basic gfx ring test | |
1837 | * | |
1838 | * @adev: amdgpu_device pointer | |
1839 | * @ring: amdgpu_ring structure holding ring information | |
1840 | * | |
1841 | * Allocate a scratch register and write to it using the gfx ring (CIK). | |
1842 | * Provides a basic gfx ring test to verify that the ring is working. | |
1843 | * Used by gfx_v7_0_cp_gfx_resume(); | |
1844 | * Returns 0 on success, error on failure. | |
1845 | */ | |
1846 | static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) | |
1847 | { | |
1848 | struct amdgpu_device *adev = ring->adev; | |
1849 | uint32_t scratch; | |
1850 | uint32_t tmp = 0; | |
1851 | unsigned i; | |
1852 | int r; | |
1853 | ||
1854 | r = amdgpu_gfx_scratch_get(adev, &scratch); | |
1855 | if (r) { | |
1856 | DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); | |
1857 | return r; | |
1858 | } | |
1859 | WREG32(scratch, 0xCAFEDEAD); | |
a27de35c | 1860 | r = amdgpu_ring_alloc(ring, 3); |
a2e73f56 AD |
1861 | if (r) { |
1862 | DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); | |
1863 | amdgpu_gfx_scratch_free(adev, scratch); | |
1864 | return r; | |
1865 | } | |
1866 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); | |
1867 | amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); | |
1868 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
a27de35c | 1869 | amdgpu_ring_commit(ring); |
a2e73f56 AD |
1870 | |
1871 | for (i = 0; i < adev->usec_timeout; i++) { | |
1872 | tmp = RREG32(scratch); | |
1873 | if (tmp == 0xDEADBEEF) | |
1874 | break; | |
1875 | DRM_UDELAY(1); | |
1876 | } | |
1877 | if (i < adev->usec_timeout) { | |
1878 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); | |
1879 | } else { | |
1880 | DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", | |
1881 | ring->idx, scratch, tmp); | |
1882 | r = -EINVAL; | |
1883 | } | |
1884 | amdgpu_gfx_scratch_free(adev, scratch); | |
1885 | return r; | |
1886 | } | |
1887 | ||
1888 | /** | |
d2edb07b | 1889 | * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp |
a2e73f56 AD |
1890 | * |
1891 | * @adev: amdgpu_device pointer | |
1892 | * @ridx: amdgpu ring index | |
1893 | * | |
1894 | * Emits an hdp flush on the cp. | |
1895 | */ | |
d2edb07b | 1896 | static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
a2e73f56 AD |
1897 | { |
1898 | u32 ref_and_mask; | |
d9b5327a | 1899 | int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; |
a2e73f56 AD |
1900 | |
1901 | if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { | |
1902 | switch (ring->me) { | |
1903 | case 1: | |
1904 | ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; | |
1905 | break; | |
1906 | case 2: | |
1907 | ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; | |
1908 | break; | |
1909 | default: | |
1910 | return; | |
1911 | } | |
1912 | } else { | |
1913 | ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; | |
1914 | } | |
1915 | ||
1916 | amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); | |
1917 | amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ | |
1918 | WAIT_REG_MEM_FUNCTION(3) | /* == */ | |
d9b5327a | 1919 | WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ |
a2e73f56 AD |
1920 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); |
1921 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); | |
1922 | amdgpu_ring_write(ring, ref_and_mask); | |
1923 | amdgpu_ring_write(ring, ref_and_mask); | |
1924 | amdgpu_ring_write(ring, 0x20); /* poll interval */ | |
1925 | } | |
1926 | ||
0955860b CZ |
1927 | /** |
1928 | * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp | |
1929 | * | |
1930 | * @adev: amdgpu_device pointer | |
1931 | * @ridx: amdgpu ring index | |
1932 | * | |
1933 | * Emits an hdp invalidate on the cp. | |
1934 | */ | |
1935 | static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) | |
1936 | { | |
1937 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
1938 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | |
1939 | WRITE_DATA_DST_SEL(0) | | |
1940 | WR_CONFIRM)); | |
1941 | amdgpu_ring_write(ring, mmHDP_DEBUG0); | |
1942 | amdgpu_ring_write(ring, 0); | |
1943 | amdgpu_ring_write(ring, 1); | |
1944 | } | |
1945 | ||
a2e73f56 AD |
1946 | /** |
1947 | * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring | |
1948 | * | |
1949 | * @adev: amdgpu_device pointer | |
1950 | * @fence: amdgpu fence object | |
1951 | * | |
1952 | * Emits a fence sequnce number on the gfx ring and flushes | |
1953 | * GPU caches. | |
1954 | */ | |
1955 | static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, | |
890ee23f | 1956 | u64 seq, unsigned flags) |
a2e73f56 | 1957 | { |
890ee23f CZ |
1958 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
1959 | bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; | |
a2e73f56 AD |
1960 | /* Workaround for cache flush problems. First send a dummy EOP |
1961 | * event down the pipe with seq one below. | |
1962 | */ | |
1963 | amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); | |
1964 | amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | | |
1965 | EOP_TC_ACTION_EN | | |
1966 | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | | |
1967 | EVENT_INDEX(5))); | |
1968 | amdgpu_ring_write(ring, addr & 0xfffffffc); | |
1969 | amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | | |
1970 | DATA_SEL(1) | INT_SEL(0)); | |
1971 | amdgpu_ring_write(ring, lower_32_bits(seq - 1)); | |
1972 | amdgpu_ring_write(ring, upper_32_bits(seq - 1)); | |
1973 | ||
1974 | /* Then send the real EOP event down the pipe. */ | |
1975 | amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); | |
1976 | amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | | |
1977 | EOP_TC_ACTION_EN | | |
1978 | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | | |
1979 | EVENT_INDEX(5))); | |
1980 | amdgpu_ring_write(ring, addr & 0xfffffffc); | |
1981 | amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | | |
890ee23f | 1982 | DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); |
a2e73f56 AD |
1983 | amdgpu_ring_write(ring, lower_32_bits(seq)); |
1984 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
1985 | } | |
1986 | ||
1987 | /** | |
1988 | * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring | |
1989 | * | |
1990 | * @adev: amdgpu_device pointer | |
1991 | * @fence: amdgpu fence object | |
1992 | * | |
1993 | * Emits a fence sequnce number on the compute ring and flushes | |
1994 | * GPU caches. | |
1995 | */ | |
1996 | static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, | |
1997 | u64 addr, u64 seq, | |
890ee23f | 1998 | unsigned flags) |
a2e73f56 | 1999 | { |
890ee23f CZ |
2000 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
2001 | bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; | |
2002 | ||
a2e73f56 AD |
2003 | /* RELEASE_MEM - flush caches, send int */ |
2004 | amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); | |
2005 | amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | | |
2006 | EOP_TC_ACTION_EN | | |
2007 | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | | |
2008 | EVENT_INDEX(5))); | |
890ee23f | 2009 | amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); |
a2e73f56 AD |
2010 | amdgpu_ring_write(ring, addr & 0xfffffffc); |
2011 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
2012 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
2013 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
2014 | } | |
2015 | ||
a2e73f56 AD |
2016 | /* |
2017 | * IB stuff | |
2018 | */ | |
2019 | /** | |
2020 | * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring | |
2021 | * | |
2022 | * @ring: amdgpu_ring structure holding ring information | |
2023 | * @ib: amdgpu indirect buffer object | |
2024 | * | |
2025 | * Emits an DE (drawing engine) or CE (constant engine) IB | |
2026 | * on the gfx ring. IBs are usually generated by userspace | |
2027 | * acceleration drivers and submitted to the kernel for | |
2028 | * sheduling on the ring. This function schedules the IB | |
2029 | * on the gfx ring for execution by the GPU. | |
2030 | */ | |
93323131 | 2031 | static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, |
a2e73f56 AD |
2032 | struct amdgpu_ib *ib) |
2033 | { | |
3cb485f3 | 2034 | bool need_ctx_switch = ring->current_ctx != ib->ctx; |
a2e73f56 AD |
2035 | u32 header, control = 0; |
2036 | u32 next_rptr = ring->wptr + 5; | |
aa2bdb24 JZ |
2037 | |
2038 | /* drop the CE preamble IB for the same context */ | |
93323131 | 2039 | if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch) |
aa2bdb24 JZ |
2040 | return; |
2041 | ||
93323131 | 2042 | if (need_ctx_switch) |
a2e73f56 AD |
2043 | next_rptr += 2; |
2044 | ||
2045 | next_rptr += 4; | |
2046 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
2047 | amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); | |
2048 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | |
2049 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | |
2050 | amdgpu_ring_write(ring, next_rptr); | |
2051 | ||
a2e73f56 | 2052 | /* insert SWITCH_BUFFER packet before first IB in the ring frame */ |
93323131 | 2053 | if (need_ctx_switch) { |
a2e73f56 AD |
2054 | amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); |
2055 | amdgpu_ring_write(ring, 0); | |
a2e73f56 AD |
2056 | } |
2057 | ||
de807f81 | 2058 | if (ib->flags & AMDGPU_IB_FLAG_CE) |
a2e73f56 AD |
2059 | header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); |
2060 | else | |
2061 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); | |
2062 | ||
4ff37a83 | 2063 | control |= ib->length_dw | (ib->vm_id << 24); |
a2e73f56 AD |
2064 | |
2065 | amdgpu_ring_write(ring, header); | |
2066 | amdgpu_ring_write(ring, | |
2067 | #ifdef __BIG_ENDIAN | |
2068 | (2 << 0) | | |
2069 | #endif | |
2070 | (ib->gpu_addr & 0xFFFFFFFC)); | |
2071 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); | |
2072 | amdgpu_ring_write(ring, control); | |
2073 | } | |
2074 | ||
93323131 | 2075 | static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, |
2076 | struct amdgpu_ib *ib) | |
2077 | { | |
2078 | u32 header, control = 0; | |
2079 | u32 next_rptr = ring->wptr + 5; | |
2080 | ||
2081 | control |= INDIRECT_BUFFER_VALID; | |
2082 | next_rptr += 4; | |
2083 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
2084 | amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); | |
2085 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | |
2086 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); | |
2087 | amdgpu_ring_write(ring, next_rptr); | |
2088 | ||
2089 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); | |
2090 | ||
4ff37a83 | 2091 | control |= ib->length_dw | (ib->vm_id << 24); |
93323131 | 2092 | |
2093 | amdgpu_ring_write(ring, header); | |
2094 | amdgpu_ring_write(ring, | |
2095 | #ifdef __BIG_ENDIAN | |
2096 | (2 << 0) | | |
2097 | #endif | |
2098 | (ib->gpu_addr & 0xFFFFFFFC)); | |
2099 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); | |
2100 | amdgpu_ring_write(ring, control); | |
2101 | } | |
2102 | ||
a2e73f56 AD |
2103 | /** |
2104 | * gfx_v7_0_ring_test_ib - basic ring IB test | |
2105 | * | |
2106 | * @ring: amdgpu_ring structure holding ring information | |
2107 | * | |
2108 | * Allocate an IB and execute it on the gfx ring (CIK). | |
2109 | * Provides a basic gfx ring test to verify that IBs are working. | |
2110 | * Returns 0 on success, error on failure. | |
2111 | */ | |
2112 | static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring) | |
2113 | { | |
2114 | struct amdgpu_device *adev = ring->adev; | |
2115 | struct amdgpu_ib ib; | |
1763552e | 2116 | struct fence *f = NULL; |
a2e73f56 AD |
2117 | uint32_t scratch; |
2118 | uint32_t tmp = 0; | |
2119 | unsigned i; | |
2120 | int r; | |
2121 | ||
2122 | r = amdgpu_gfx_scratch_get(adev, &scratch); | |
2123 | if (r) { | |
2124 | DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r); | |
2125 | return r; | |
2126 | } | |
2127 | WREG32(scratch, 0xCAFEDEAD); | |
b203dd95 | 2128 | memset(&ib, 0, sizeof(ib)); |
b07c60c0 | 2129 | r = amdgpu_ib_get(adev, NULL, 256, &ib); |
a2e73f56 AD |
2130 | if (r) { |
2131 | DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); | |
42d13693 | 2132 | goto err1; |
a2e73f56 AD |
2133 | } |
2134 | ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); | |
2135 | ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); | |
2136 | ib.ptr[2] = 0xDEADBEEF; | |
2137 | ib.length_dw = 3; | |
42d13693 | 2138 | |
336d1f5e | 2139 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); |
42d13693 CZ |
2140 | if (r) |
2141 | goto err2; | |
2142 | ||
1763552e | 2143 | r = fence_wait(f, false); |
a2e73f56 AD |
2144 | if (r) { |
2145 | DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); | |
42d13693 | 2146 | goto err2; |
a2e73f56 AD |
2147 | } |
2148 | for (i = 0; i < adev->usec_timeout; i++) { | |
2149 | tmp = RREG32(scratch); | |
2150 | if (tmp == 0xDEADBEEF) | |
2151 | break; | |
2152 | DRM_UDELAY(1); | |
2153 | } | |
2154 | if (i < adev->usec_timeout) { | |
2155 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", | |
42d13693 CZ |
2156 | ring->idx, i); |
2157 | goto err2; | |
a2e73f56 AD |
2158 | } else { |
2159 | DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", | |
2160 | scratch, tmp); | |
2161 | r = -EINVAL; | |
2162 | } | |
42d13693 CZ |
2163 | |
2164 | err2: | |
281b4223 | 2165 | fence_put(f); |
cc55c45d | 2166 | amdgpu_ib_free(adev, &ib, NULL); |
42d13693 CZ |
2167 | err1: |
2168 | amdgpu_gfx_scratch_free(adev, scratch); | |
a2e73f56 AD |
2169 | return r; |
2170 | } | |
2171 | ||
2172 | /* | |
2173 | * CP. | |
2174 | * On CIK, gfx and compute now have independant command processors. | |
2175 | * | |
2176 | * GFX | |
2177 | * Gfx consists of a single ring and can process both gfx jobs and | |
2178 | * compute jobs. The gfx CP consists of three microengines (ME): | |
2179 | * PFP - Pre-Fetch Parser | |
2180 | * ME - Micro Engine | |
2181 | * CE - Constant Engine | |
2182 | * The PFP and ME make up what is considered the Drawing Engine (DE). | |
2183 | * The CE is an asynchronous engine used for updating buffer desciptors | |
2184 | * used by the DE so that they can be loaded into cache in parallel | |
2185 | * while the DE is processing state update packets. | |
2186 | * | |
2187 | * Compute | |
2188 | * The compute CP consists of two microengines (ME): | |
2189 | * MEC1 - Compute MicroEngine 1 | |
2190 | * MEC2 - Compute MicroEngine 2 | |
2191 | * Each MEC supports 4 compute pipes and each pipe supports 8 queues. | |
2192 | * The queues are exposed to userspace and are programmed directly | |
2193 | * by the compute runtime. | |
2194 | */ | |
2195 | /** | |
2196 | * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs | |
2197 | * | |
2198 | * @adev: amdgpu_device pointer | |
2199 | * @enable: enable or disable the MEs | |
2200 | * | |
2201 | * Halts or unhalts the gfx MEs. | |
2202 | */ | |
2203 | static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) | |
2204 | { | |
2205 | int i; | |
2206 | ||
2207 | if (enable) { | |
2208 | WREG32(mmCP_ME_CNTL, 0); | |
2209 | } else { | |
2210 | WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK)); | |
2211 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) | |
2212 | adev->gfx.gfx_ring[i].ready = false; | |
2213 | } | |
2214 | udelay(50); | |
2215 | } | |
2216 | ||
2217 | /** | |
2218 | * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode | |
2219 | * | |
2220 | * @adev: amdgpu_device pointer | |
2221 | * | |
2222 | * Loads the gfx PFP, ME, and CE ucode. | |
2223 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
2224 | */ | |
2225 | static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) | |
2226 | { | |
2227 | const struct gfx_firmware_header_v1_0 *pfp_hdr; | |
2228 | const struct gfx_firmware_header_v1_0 *ce_hdr; | |
2229 | const struct gfx_firmware_header_v1_0 *me_hdr; | |
2230 | const __le32 *fw_data; | |
2231 | unsigned i, fw_size; | |
2232 | ||
2233 | if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) | |
2234 | return -EINVAL; | |
2235 | ||
2236 | pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; | |
2237 | ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; | |
2238 | me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; | |
2239 | ||
2240 | amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); | |
2241 | amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); | |
2242 | amdgpu_ucode_print_gfx_hdr(&me_hdr->header); | |
2243 | adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); | |
2244 | adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); | |
2245 | adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); | |
02558a00 KW |
2246 | adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); |
2247 | adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); | |
2248 | adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); | |
a2e73f56 AD |
2249 | |
2250 | gfx_v7_0_cp_gfx_enable(adev, false); | |
2251 | ||
2252 | /* PFP */ | |
2253 | fw_data = (const __le32 *) | |
2254 | (adev->gfx.pfp_fw->data + | |
2255 | le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); | |
2256 | fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; | |
2257 | WREG32(mmCP_PFP_UCODE_ADDR, 0); | |
2258 | for (i = 0; i < fw_size; i++) | |
2259 | WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); | |
2260 | WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); | |
2261 | ||
2262 | /* CE */ | |
2263 | fw_data = (const __le32 *) | |
2264 | (adev->gfx.ce_fw->data + | |
2265 | le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); | |
2266 | fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; | |
2267 | WREG32(mmCP_CE_UCODE_ADDR, 0); | |
2268 | for (i = 0; i < fw_size; i++) | |
2269 | WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); | |
2270 | WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); | |
2271 | ||
2272 | /* ME */ | |
2273 | fw_data = (const __le32 *) | |
2274 | (adev->gfx.me_fw->data + | |
2275 | le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); | |
2276 | fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; | |
2277 | WREG32(mmCP_ME_RAM_WADDR, 0); | |
2278 | for (i = 0; i < fw_size; i++) | |
2279 | WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); | |
2280 | WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); | |
2281 | ||
2282 | return 0; | |
2283 | } | |
2284 | ||
2285 | /** | |
2286 | * gfx_v7_0_cp_gfx_start - start the gfx ring | |
2287 | * | |
2288 | * @adev: amdgpu_device pointer | |
2289 | * | |
2290 | * Enables the ring and loads the clear state context and other | |
2291 | * packets required to init the ring. | |
2292 | * Returns 0 for success, error for failure. | |
2293 | */ | |
2294 | static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) | |
2295 | { | |
2296 | struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; | |
2297 | const struct cs_section_def *sect = NULL; | |
2298 | const struct cs_extent_def *ext = NULL; | |
2299 | int r, i; | |
2300 | ||
2301 | /* init the CP */ | |
2302 | WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); | |
2303 | WREG32(mmCP_ENDIAN_SWAP, 0); | |
2304 | WREG32(mmCP_DEVICE_ID, 1); | |
2305 | ||
2306 | gfx_v7_0_cp_gfx_enable(adev, true); | |
2307 | ||
a27de35c | 2308 | r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); |
a2e73f56 AD |
2309 | if (r) { |
2310 | DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); | |
2311 | return r; | |
2312 | } | |
2313 | ||
2314 | /* init the CE partitions. CE only used for gfx on CIK */ | |
2315 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); | |
2316 | amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); | |
2317 | amdgpu_ring_write(ring, 0x8000); | |
2318 | amdgpu_ring_write(ring, 0x8000); | |
2319 | ||
2320 | /* clear state buffer */ | |
2321 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | |
2322 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); | |
2323 | ||
2324 | amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); | |
2325 | amdgpu_ring_write(ring, 0x80000000); | |
2326 | amdgpu_ring_write(ring, 0x80000000); | |
2327 | ||
2328 | for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { | |
2329 | for (ext = sect->section; ext->extent != NULL; ++ext) { | |
2330 | if (sect->id == SECT_CONTEXT) { | |
2331 | amdgpu_ring_write(ring, | |
2332 | PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); | |
2333 | amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); | |
2334 | for (i = 0; i < ext->reg_count; i++) | |
2335 | amdgpu_ring_write(ring, ext->extent[i]); | |
2336 | } | |
2337 | } | |
2338 | } | |
2339 | ||
2340 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); | |
2341 | amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); | |
2342 | switch (adev->asic_type) { | |
2343 | case CHIP_BONAIRE: | |
2344 | amdgpu_ring_write(ring, 0x16000012); | |
2345 | amdgpu_ring_write(ring, 0x00000000); | |
2346 | break; | |
2347 | case CHIP_KAVERI: | |
2348 | amdgpu_ring_write(ring, 0x00000000); /* XXX */ | |
2349 | amdgpu_ring_write(ring, 0x00000000); | |
2350 | break; | |
2351 | case CHIP_KABINI: | |
2352 | case CHIP_MULLINS: | |
2353 | amdgpu_ring_write(ring, 0x00000000); /* XXX */ | |
2354 | amdgpu_ring_write(ring, 0x00000000); | |
2355 | break; | |
2356 | case CHIP_HAWAII: | |
2357 | amdgpu_ring_write(ring, 0x3a00161a); | |
2358 | amdgpu_ring_write(ring, 0x0000002e); | |
2359 | break; | |
2360 | default: | |
2361 | amdgpu_ring_write(ring, 0x00000000); | |
2362 | amdgpu_ring_write(ring, 0x00000000); | |
2363 | break; | |
2364 | } | |
2365 | ||
2366 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | |
2367 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); | |
2368 | ||
2369 | amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); | |
2370 | amdgpu_ring_write(ring, 0); | |
2371 | ||
2372 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); | |
2373 | amdgpu_ring_write(ring, 0x00000316); | |
2374 | amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | |
2375 | amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ | |
2376 | ||
a27de35c | 2377 | amdgpu_ring_commit(ring); |
a2e73f56 AD |
2378 | |
2379 | return 0; | |
2380 | } | |
2381 | ||
2382 | /** | |
2383 | * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers | |
2384 | * | |
2385 | * @adev: amdgpu_device pointer | |
2386 | * | |
2387 | * Program the location and size of the gfx ring buffer | |
2388 | * and test it to make sure it's working. | |
2389 | * Returns 0 for success, error for failure. | |
2390 | */ | |
2391 | static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) | |
2392 | { | |
2393 | struct amdgpu_ring *ring; | |
2394 | u32 tmp; | |
2395 | u32 rb_bufsz; | |
2396 | u64 rb_addr, rptr_addr; | |
2397 | int r; | |
2398 | ||
2399 | WREG32(mmCP_SEM_WAIT_TIMER, 0x0); | |
2400 | if (adev->asic_type != CHIP_HAWAII) | |
2401 | WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); | |
2402 | ||
2403 | /* Set the write pointer delay */ | |
2404 | WREG32(mmCP_RB_WPTR_DELAY, 0); | |
2405 | ||
2406 | /* set the RB to use vmid 0 */ | |
2407 | WREG32(mmCP_RB_VMID, 0); | |
2408 | ||
2409 | WREG32(mmSCRATCH_ADDR, 0); | |
2410 | ||
2411 | /* ring 0 - compute and gfx */ | |
2412 | /* Set ring buffer size */ | |
2413 | ring = &adev->gfx.gfx_ring[0]; | |
2414 | rb_bufsz = order_base_2(ring->ring_size / 8); | |
2415 | tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | |
2416 | #ifdef __BIG_ENDIAN | |
454fc95e | 2417 | tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; |
a2e73f56 AD |
2418 | #endif |
2419 | WREG32(mmCP_RB0_CNTL, tmp); | |
2420 | ||
2421 | /* Initialize the ring buffer's read and write pointers */ | |
2422 | WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); | |
2423 | ring->wptr = 0; | |
2424 | WREG32(mmCP_RB0_WPTR, ring->wptr); | |
2425 | ||
2426 | /* set the wb address wether it's enabled or not */ | |
2427 | rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); | |
2428 | WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); | |
2429 | WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); | |
2430 | ||
2431 | /* scratch register shadowing is no longer supported */ | |
2432 | WREG32(mmSCRATCH_UMSK, 0); | |
2433 | ||
2434 | mdelay(1); | |
2435 | WREG32(mmCP_RB0_CNTL, tmp); | |
2436 | ||
2437 | rb_addr = ring->gpu_addr >> 8; | |
2438 | WREG32(mmCP_RB0_BASE, rb_addr); | |
2439 | WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); | |
2440 | ||
2441 | /* start the ring */ | |
2442 | gfx_v7_0_cp_gfx_start(adev); | |
2443 | ring->ready = true; | |
2444 | r = amdgpu_ring_test_ring(ring); | |
2445 | if (r) { | |
2446 | ring->ready = false; | |
2447 | return r; | |
2448 | } | |
2449 | ||
2450 | return 0; | |
2451 | } | |
2452 | ||
2453 | static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) | |
2454 | { | |
7edd6b2f | 2455 | return ring->adev->wb.wb[ring->rptr_offs]; |
a2e73f56 AD |
2456 | } |
2457 | ||
2458 | static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) | |
2459 | { | |
2460 | struct amdgpu_device *adev = ring->adev; | |
a2e73f56 | 2461 | |
7edd6b2f | 2462 | return RREG32(mmCP_RB0_WPTR); |
a2e73f56 AD |
2463 | } |
2464 | ||
2465 | static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) | |
2466 | { | |
2467 | struct amdgpu_device *adev = ring->adev; | |
2468 | ||
2469 | WREG32(mmCP_RB0_WPTR, ring->wptr); | |
2470 | (void)RREG32(mmCP_RB0_WPTR); | |
2471 | } | |
2472 | ||
2473 | static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring) | |
2474 | { | |
7edd6b2f | 2475 | return ring->adev->wb.wb[ring->rptr_offs]; |
a2e73f56 AD |
2476 | } |
2477 | ||
2478 | static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) | |
2479 | { | |
a2e73f56 | 2480 | /* XXX check if swapping is necessary on BE */ |
7edd6b2f | 2481 | return ring->adev->wb.wb[ring->wptr_offs]; |
a2e73f56 AD |
2482 | } |
2483 | ||
2484 | static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) | |
2485 | { | |
2486 | struct amdgpu_device *adev = ring->adev; | |
2487 | ||
2488 | /* XXX check if swapping is necessary on BE */ | |
2489 | adev->wb.wb[ring->wptr_offs] = ring->wptr; | |
2490 | WDOORBELL32(ring->doorbell_index, ring->wptr); | |
2491 | } | |
2492 | ||
2493 | /** | |
2494 | * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs | |
2495 | * | |
2496 | * @adev: amdgpu_device pointer | |
2497 | * @enable: enable or disable the MEs | |
2498 | * | |
2499 | * Halts or unhalts the compute MEs. | |
2500 | */ | |
2501 | static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) | |
2502 | { | |
2503 | int i; | |
2504 | ||
2505 | if (enable) { | |
2506 | WREG32(mmCP_MEC_CNTL, 0); | |
2507 | } else { | |
2508 | WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); | |
2509 | for (i = 0; i < adev->gfx.num_compute_rings; i++) | |
2510 | adev->gfx.compute_ring[i].ready = false; | |
2511 | } | |
2512 | udelay(50); | |
2513 | } | |
2514 | ||
2515 | /** | |
2516 | * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode | |
2517 | * | |
2518 | * @adev: amdgpu_device pointer | |
2519 | * | |
2520 | * Loads the compute MEC1&2 ucode. | |
2521 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
2522 | */ | |
2523 | static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) | |
2524 | { | |
2525 | const struct gfx_firmware_header_v1_0 *mec_hdr; | |
2526 | const __le32 *fw_data; | |
2527 | unsigned i, fw_size; | |
2528 | ||
2529 | if (!adev->gfx.mec_fw) | |
2530 | return -EINVAL; | |
2531 | ||
2532 | mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; | |
2533 | amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); | |
2534 | adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); | |
351643d7 JZ |
2535 | adev->gfx.mec_feature_version = le32_to_cpu( |
2536 | mec_hdr->ucode_feature_version); | |
a2e73f56 AD |
2537 | |
2538 | gfx_v7_0_cp_compute_enable(adev, false); | |
2539 | ||
2540 | /* MEC1 */ | |
2541 | fw_data = (const __le32 *) | |
2542 | (adev->gfx.mec_fw->data + | |
2543 | le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); | |
2544 | fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; | |
2545 | WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); | |
2546 | for (i = 0; i < fw_size; i++) | |
2547 | WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); | |
2548 | WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); | |
2549 | ||
2550 | if (adev->asic_type == CHIP_KAVERI) { | |
2551 | const struct gfx_firmware_header_v1_0 *mec2_hdr; | |
2552 | ||
2553 | if (!adev->gfx.mec2_fw) | |
2554 | return -EINVAL; | |
2555 | ||
2556 | mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; | |
2557 | amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); | |
2558 | adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); | |
351643d7 JZ |
2559 | adev->gfx.mec2_feature_version = le32_to_cpu( |
2560 | mec2_hdr->ucode_feature_version); | |
a2e73f56 AD |
2561 | |
2562 | /* MEC2 */ | |
2563 | fw_data = (const __le32 *) | |
2564 | (adev->gfx.mec2_fw->data + | |
2565 | le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); | |
2566 | fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; | |
2567 | WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); | |
2568 | for (i = 0; i < fw_size; i++) | |
2569 | WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); | |
2570 | WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); | |
2571 | } | |
2572 | ||
2573 | return 0; | |
2574 | } | |
2575 | ||
a2e73f56 AD |
2576 | /** |
2577 | * gfx_v7_0_cp_compute_fini - stop the compute queues | |
2578 | * | |
2579 | * @adev: amdgpu_device pointer | |
2580 | * | |
2581 | * Stop the compute queues and tear down the driver queue | |
2582 | * info. | |
2583 | */ | |
2584 | static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) | |
2585 | { | |
2586 | int i, r; | |
2587 | ||
2588 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { | |
2589 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; | |
2590 | ||
2591 | if (ring->mqd_obj) { | |
2592 | r = amdgpu_bo_reserve(ring->mqd_obj, false); | |
2593 | if (unlikely(r != 0)) | |
2594 | dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); | |
2595 | ||
2596 | amdgpu_bo_unpin(ring->mqd_obj); | |
2597 | amdgpu_bo_unreserve(ring->mqd_obj); | |
2598 | ||
2599 | amdgpu_bo_unref(&ring->mqd_obj); | |
2600 | ring->mqd_obj = NULL; | |
2601 | } | |
2602 | } | |
2603 | } | |
2604 | ||
2605 | static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) | |
2606 | { | |
2607 | int r; | |
2608 | ||
2609 | if (adev->gfx.mec.hpd_eop_obj) { | |
2610 | r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); | |
2611 | if (unlikely(r != 0)) | |
2612 | dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); | |
2613 | amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); | |
2614 | amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); | |
2615 | ||
2616 | amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); | |
2617 | adev->gfx.mec.hpd_eop_obj = NULL; | |
2618 | } | |
2619 | } | |
2620 | ||
2621 | #define MEC_HPD_SIZE 2048 | |
2622 | ||
2623 | static int gfx_v7_0_mec_init(struct amdgpu_device *adev) | |
2624 | { | |
2625 | int r; | |
2626 | u32 *hpd; | |
2627 | ||
2628 | /* | |
2629 | * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total | |
2630 | * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total | |
2631 | * Nonetheless, we assign only 1 pipe because all other pipes will | |
2632 | * be handled by KFD | |
2633 | */ | |
2634 | adev->gfx.mec.num_mec = 1; | |
2635 | adev->gfx.mec.num_pipe = 1; | |
2636 | adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; | |
2637 | ||
2638 | if (adev->gfx.mec.hpd_eop_obj == NULL) { | |
2639 | r = amdgpu_bo_create(adev, | |
2640 | adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, | |
2641 | PAGE_SIZE, true, | |
72d7668b | 2642 | AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, |
a2e73f56 AD |
2643 | &adev->gfx.mec.hpd_eop_obj); |
2644 | if (r) { | |
2645 | dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); | |
2646 | return r; | |
2647 | } | |
2648 | } | |
2649 | ||
2650 | r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); | |
2651 | if (unlikely(r != 0)) { | |
2652 | gfx_v7_0_mec_fini(adev); | |
2653 | return r; | |
2654 | } | |
2655 | r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, | |
2656 | &adev->gfx.mec.hpd_eop_gpu_addr); | |
2657 | if (r) { | |
2658 | dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); | |
2659 | gfx_v7_0_mec_fini(adev); | |
2660 | return r; | |
2661 | } | |
2662 | r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); | |
2663 | if (r) { | |
2664 | dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); | |
2665 | gfx_v7_0_mec_fini(adev); | |
2666 | return r; | |
2667 | } | |
2668 | ||
2669 | /* clear memory. Not sure if this is required or not */ | |
2670 | memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); | |
2671 | ||
2672 | amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); | |
2673 | amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); | |
2674 | ||
2675 | return 0; | |
2676 | } | |
2677 | ||
2678 | struct hqd_registers | |
2679 | { | |
2680 | u32 cp_mqd_base_addr; | |
2681 | u32 cp_mqd_base_addr_hi; | |
2682 | u32 cp_hqd_active; | |
2683 | u32 cp_hqd_vmid; | |
2684 | u32 cp_hqd_persistent_state; | |
2685 | u32 cp_hqd_pipe_priority; | |
2686 | u32 cp_hqd_queue_priority; | |
2687 | u32 cp_hqd_quantum; | |
2688 | u32 cp_hqd_pq_base; | |
2689 | u32 cp_hqd_pq_base_hi; | |
2690 | u32 cp_hqd_pq_rptr; | |
2691 | u32 cp_hqd_pq_rptr_report_addr; | |
2692 | u32 cp_hqd_pq_rptr_report_addr_hi; | |
2693 | u32 cp_hqd_pq_wptr_poll_addr; | |
2694 | u32 cp_hqd_pq_wptr_poll_addr_hi; | |
2695 | u32 cp_hqd_pq_doorbell_control; | |
2696 | u32 cp_hqd_pq_wptr; | |
2697 | u32 cp_hqd_pq_control; | |
2698 | u32 cp_hqd_ib_base_addr; | |
2699 | u32 cp_hqd_ib_base_addr_hi; | |
2700 | u32 cp_hqd_ib_rptr; | |
2701 | u32 cp_hqd_ib_control; | |
2702 | u32 cp_hqd_iq_timer; | |
2703 | u32 cp_hqd_iq_rptr; | |
2704 | u32 cp_hqd_dequeue_request; | |
2705 | u32 cp_hqd_dma_offload; | |
2706 | u32 cp_hqd_sema_cmd; | |
2707 | u32 cp_hqd_msg_type; | |
2708 | u32 cp_hqd_atomic0_preop_lo; | |
2709 | u32 cp_hqd_atomic0_preop_hi; | |
2710 | u32 cp_hqd_atomic1_preop_lo; | |
2711 | u32 cp_hqd_atomic1_preop_hi; | |
2712 | u32 cp_hqd_hq_scheduler0; | |
2713 | u32 cp_hqd_hq_scheduler1; | |
2714 | u32 cp_mqd_control; | |
2715 | }; | |
2716 | ||
2717 | struct bonaire_mqd | |
2718 | { | |
2719 | u32 header; | |
2720 | u32 dispatch_initiator; | |
2721 | u32 dimensions[3]; | |
2722 | u32 start_idx[3]; | |
2723 | u32 num_threads[3]; | |
2724 | u32 pipeline_stat_enable; | |
2725 | u32 perf_counter_enable; | |
2726 | u32 pgm[2]; | |
2727 | u32 tba[2]; | |
2728 | u32 tma[2]; | |
2729 | u32 pgm_rsrc[2]; | |
2730 | u32 vmid; | |
2731 | u32 resource_limits; | |
2732 | u32 static_thread_mgmt01[2]; | |
2733 | u32 tmp_ring_size; | |
2734 | u32 static_thread_mgmt23[2]; | |
2735 | u32 restart[3]; | |
2736 | u32 thread_trace_enable; | |
2737 | u32 reserved1; | |
2738 | u32 user_data[16]; | |
2739 | u32 vgtcs_invoke_count[2]; | |
2740 | struct hqd_registers queue_state; | |
2741 | u32 dequeue_cntr; | |
2742 | u32 interrupt_queue[64]; | |
2743 | }; | |
2744 | ||
2745 | /** | |
2746 | * gfx_v7_0_cp_compute_resume - setup the compute queue registers | |
2747 | * | |
2748 | * @adev: amdgpu_device pointer | |
2749 | * | |
2750 | * Program the compute queues and test them to make sure they | |
2751 | * are working. | |
2752 | * Returns 0 for success, error for failure. | |
2753 | */ | |
2754 | static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) | |
2755 | { | |
2756 | int r, i, j; | |
2757 | u32 tmp; | |
2758 | bool use_doorbell = true; | |
2759 | u64 hqd_gpu_addr; | |
2760 | u64 mqd_gpu_addr; | |
2761 | u64 eop_gpu_addr; | |
2762 | u64 wb_gpu_addr; | |
2763 | u32 *buf; | |
2764 | struct bonaire_mqd *mqd; | |
2765 | ||
6e9821b2 | 2766 | gfx_v7_0_cp_compute_enable(adev, true); |
a2e73f56 AD |
2767 | |
2768 | /* fix up chicken bits */ | |
2769 | tmp = RREG32(mmCP_CPF_DEBUG); | |
2770 | tmp |= (1 << 23); | |
2771 | WREG32(mmCP_CPF_DEBUG, tmp); | |
2772 | ||
2773 | /* init the pipes */ | |
2774 | mutex_lock(&adev->srbm_mutex); | |
2775 | for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { | |
2776 | int me = (i < 4) ? 1 : 2; | |
2777 | int pipe = (i < 4) ? i : (i - 4); | |
2778 | ||
2779 | eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2); | |
2780 | ||
2781 | cik_srbm_select(adev, me, pipe, 0, 0); | |
2782 | ||
2783 | /* write the EOP addr */ | |
2784 | WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); | |
2785 | WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); | |
2786 | ||
2787 | /* set the VMID assigned */ | |
2788 | WREG32(mmCP_HPD_EOP_VMID, 0); | |
2789 | ||
2790 | /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ | |
2791 | tmp = RREG32(mmCP_HPD_EOP_CONTROL); | |
2792 | tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; | |
2793 | tmp |= order_base_2(MEC_HPD_SIZE / 8); | |
2794 | WREG32(mmCP_HPD_EOP_CONTROL, tmp); | |
2795 | } | |
2796 | cik_srbm_select(adev, 0, 0, 0, 0); | |
2797 | mutex_unlock(&adev->srbm_mutex); | |
2798 | ||
2799 | /* init the queues. Just two for now. */ | |
2800 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { | |
2801 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; | |
2802 | ||
2803 | if (ring->mqd_obj == NULL) { | |
2804 | r = amdgpu_bo_create(adev, | |
2805 | sizeof(struct bonaire_mqd), | |
2806 | PAGE_SIZE, true, | |
72d7668b | 2807 | AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, |
a2e73f56 AD |
2808 | &ring->mqd_obj); |
2809 | if (r) { | |
2810 | dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); | |
2811 | return r; | |
2812 | } | |
2813 | } | |
2814 | ||
2815 | r = amdgpu_bo_reserve(ring->mqd_obj, false); | |
2816 | if (unlikely(r != 0)) { | |
2817 | gfx_v7_0_cp_compute_fini(adev); | |
2818 | return r; | |
2819 | } | |
2820 | r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, | |
2821 | &mqd_gpu_addr); | |
2822 | if (r) { | |
2823 | dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); | |
2824 | gfx_v7_0_cp_compute_fini(adev); | |
2825 | return r; | |
2826 | } | |
2827 | r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); | |
2828 | if (r) { | |
2829 | dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); | |
2830 | gfx_v7_0_cp_compute_fini(adev); | |
2831 | return r; | |
2832 | } | |
2833 | ||
2834 | /* init the mqd struct */ | |
2835 | memset(buf, 0, sizeof(struct bonaire_mqd)); | |
2836 | ||
2837 | mqd = (struct bonaire_mqd *)buf; | |
2838 | mqd->header = 0xC0310800; | |
2839 | mqd->static_thread_mgmt01[0] = 0xffffffff; | |
2840 | mqd->static_thread_mgmt01[1] = 0xffffffff; | |
2841 | mqd->static_thread_mgmt23[0] = 0xffffffff; | |
2842 | mqd->static_thread_mgmt23[1] = 0xffffffff; | |
2843 | ||
2844 | mutex_lock(&adev->srbm_mutex); | |
2845 | cik_srbm_select(adev, ring->me, | |
2846 | ring->pipe, | |
2847 | ring->queue, 0); | |
2848 | ||
2849 | /* disable wptr polling */ | |
2850 | tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); | |
2851 | tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK; | |
2852 | WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); | |
2853 | ||
2854 | /* enable doorbell? */ | |
2855 | mqd->queue_state.cp_hqd_pq_doorbell_control = | |
2856 | RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); | |
2857 | if (use_doorbell) | |
2858 | mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; | |
2859 | else | |
2860 | mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; | |
2861 | WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, | |
2862 | mqd->queue_state.cp_hqd_pq_doorbell_control); | |
2863 | ||
2864 | /* disable the queue if it's active */ | |
2865 | mqd->queue_state.cp_hqd_dequeue_request = 0; | |
2866 | mqd->queue_state.cp_hqd_pq_rptr = 0; | |
2867 | mqd->queue_state.cp_hqd_pq_wptr= 0; | |
2868 | if (RREG32(mmCP_HQD_ACTIVE) & 1) { | |
2869 | WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); | |
2870 | for (j = 0; j < adev->usec_timeout; j++) { | |
2871 | if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) | |
2872 | break; | |
2873 | udelay(1); | |
2874 | } | |
2875 | WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); | |
2876 | WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); | |
2877 | WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); | |
2878 | } | |
2879 | ||
2880 | /* set the pointer to the MQD */ | |
2881 | mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc; | |
2882 | mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); | |
2883 | WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); | |
2884 | WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); | |
2885 | /* set MQD vmid to 0 */ | |
2886 | mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL); | |
2887 | mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; | |
2888 | WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); | |
2889 | ||
2890 | /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ | |
2891 | hqd_gpu_addr = ring->gpu_addr >> 8; | |
2892 | mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr; | |
2893 | mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); | |
2894 | WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); | |
2895 | WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); | |
2896 | ||
2897 | /* set up the HQD, this is similar to CP_RB0_CNTL */ | |
2898 | mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); | |
2899 | mqd->queue_state.cp_hqd_pq_control &= | |
2900 | ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | | |
2901 | CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); | |
2902 | ||
2903 | mqd->queue_state.cp_hqd_pq_control |= | |
2904 | order_base_2(ring->ring_size / 8); | |
2905 | mqd->queue_state.cp_hqd_pq_control |= | |
2906 | (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); | |
2907 | #ifdef __BIG_ENDIAN | |
454fc95e AD |
2908 | mqd->queue_state.cp_hqd_pq_control |= |
2909 | 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; | |
a2e73f56 AD |
2910 | #endif |
2911 | mqd->queue_state.cp_hqd_pq_control &= | |
2912 | ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | | |
2913 | CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | | |
2914 | CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); | |
2915 | mqd->queue_state.cp_hqd_pq_control |= | |
2916 | CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | | |
2917 | CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ | |
2918 | WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); | |
2919 | ||
2920 | /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ | |
2921 | wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); | |
2922 | mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; | |
2923 | mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; | |
2924 | WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); | |
2925 | WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, | |
2926 | mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi); | |
2927 | ||
2928 | /* set the wb address wether it's enabled or not */ | |
2929 | wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); | |
2930 | mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc; | |
2931 | mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi = | |
2932 | upper_32_bits(wb_gpu_addr) & 0xffff; | |
2933 | WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, | |
2934 | mqd->queue_state.cp_hqd_pq_rptr_report_addr); | |
2935 | WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, | |
2936 | mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi); | |
2937 | ||
2938 | /* enable the doorbell if requested */ | |
2939 | if (use_doorbell) { | |
2940 | mqd->queue_state.cp_hqd_pq_doorbell_control = | |
2941 | RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); | |
2942 | mqd->queue_state.cp_hqd_pq_doorbell_control &= | |
2943 | ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; | |
2944 | mqd->queue_state.cp_hqd_pq_doorbell_control |= | |
2945 | (ring->doorbell_index << | |
2946 | CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); | |
2947 | mqd->queue_state.cp_hqd_pq_doorbell_control |= | |
2948 | CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; | |
2949 | mqd->queue_state.cp_hqd_pq_doorbell_control &= | |
2950 | ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | | |
2951 | CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); | |
2952 | ||
2953 | } else { | |
2954 | mqd->queue_state.cp_hqd_pq_doorbell_control = 0; | |
2955 | } | |
2956 | WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, | |
2957 | mqd->queue_state.cp_hqd_pq_doorbell_control); | |
2958 | ||
2959 | /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ | |
2960 | ring->wptr = 0; | |
2961 | mqd->queue_state.cp_hqd_pq_wptr = ring->wptr; | |
2962 | WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); | |
2963 | mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); | |
2964 | ||
2965 | /* set the vmid for the queue */ | |
2966 | mqd->queue_state.cp_hqd_vmid = 0; | |
2967 | WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); | |
2968 | ||
2969 | /* activate the queue */ | |
2970 | mqd->queue_state.cp_hqd_active = 1; | |
2971 | WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); | |
2972 | ||
2973 | cik_srbm_select(adev, 0, 0, 0, 0); | |
2974 | mutex_unlock(&adev->srbm_mutex); | |
2975 | ||
2976 | amdgpu_bo_kunmap(ring->mqd_obj); | |
2977 | amdgpu_bo_unreserve(ring->mqd_obj); | |
2978 | ||
2979 | ring->ready = true; | |
2980 | r = amdgpu_ring_test_ring(ring); | |
2981 | if (r) | |
2982 | ring->ready = false; | |
2983 | } | |
2984 | ||
2985 | return 0; | |
2986 | } | |
2987 | ||
2988 | static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) | |
2989 | { | |
2990 | gfx_v7_0_cp_gfx_enable(adev, enable); | |
2991 | gfx_v7_0_cp_compute_enable(adev, enable); | |
2992 | } | |
2993 | ||
2994 | static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) | |
2995 | { | |
2996 | int r; | |
2997 | ||
2998 | r = gfx_v7_0_cp_gfx_load_microcode(adev); | |
2999 | if (r) | |
3000 | return r; | |
3001 | r = gfx_v7_0_cp_compute_load_microcode(adev); | |
3002 | if (r) | |
3003 | return r; | |
3004 | ||
3005 | return 0; | |
3006 | } | |
3007 | ||
3008 | static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, | |
3009 | bool enable) | |
3010 | { | |
3011 | u32 tmp = RREG32(mmCP_INT_CNTL_RING0); | |
3012 | ||
3013 | if (enable) | |
3014 | tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | | |
3015 | CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); | |
3016 | else | |
3017 | tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | | |
3018 | CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); | |
3019 | WREG32(mmCP_INT_CNTL_RING0, tmp); | |
3020 | } | |
3021 | ||
3022 | static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) | |
3023 | { | |
3024 | int r; | |
3025 | ||
3026 | gfx_v7_0_enable_gui_idle_interrupt(adev, false); | |
3027 | ||
3028 | r = gfx_v7_0_cp_load_microcode(adev); | |
3029 | if (r) | |
3030 | return r; | |
3031 | ||
3032 | r = gfx_v7_0_cp_gfx_resume(adev); | |
3033 | if (r) | |
3034 | return r; | |
3035 | r = gfx_v7_0_cp_compute_resume(adev); | |
3036 | if (r) | |
3037 | return r; | |
3038 | ||
3039 | gfx_v7_0_enable_gui_idle_interrupt(adev, true); | |
3040 | ||
3041 | return 0; | |
3042 | } | |
3043 | ||
b8c7b39e CK |
3044 | /** |
3045 | * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP | |
3046 | * | |
3047 | * @ring: the ring to emmit the commands to | |
3048 | * | |
3049 | * Sync the command pipeline with the PFP. E.g. wait for everything | |
3050 | * to be completed. | |
3051 | */ | |
3052 | static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) | |
3053 | { | |
3054 | int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); | |
3055 | if (usepfp) { | |
3056 | /* synce CE with ME to prevent CE fetch CEIB before context switch done */ | |
3057 | amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); | |
3058 | amdgpu_ring_write(ring, 0); | |
3059 | amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); | |
3060 | amdgpu_ring_write(ring, 0); | |
3061 | } | |
3062 | } | |
3063 | ||
a2e73f56 AD |
3064 | /* |
3065 | * vm | |
3066 | * VMID 0 is the physical GPU addresses as used by the kernel. | |
3067 | * VMIDs 1-15 are used for userspace clients and are handled | |
3068 | * by the amdgpu vm/hsa code. | |
3069 | */ | |
3070 | /** | |
3071 | * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP | |
3072 | * | |
3073 | * @adev: amdgpu_device pointer | |
3074 | * | |
3075 | * Update the page table base and flush the VM TLB | |
3076 | * using the CP (CIK). | |
3077 | */ | |
3078 | static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
3079 | unsigned vm_id, uint64_t pd_addr) | |
3080 | { | |
3081 | int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); | |
3082 | ||
3083 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
3084 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | | |
3085 | WRITE_DATA_DST_SEL(0))); | |
3086 | if (vm_id < 8) { | |
3087 | amdgpu_ring_write(ring, | |
3088 | (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); | |
3089 | } else { | |
3090 | amdgpu_ring_write(ring, | |
3091 | (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); | |
3092 | } | |
3093 | amdgpu_ring_write(ring, 0); | |
3094 | amdgpu_ring_write(ring, pd_addr >> 12); | |
3095 | ||
a2e73f56 AD |
3096 | /* bits 0-15 are the VM contexts0-15 */ |
3097 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
3098 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | |
3099 | WRITE_DATA_DST_SEL(0))); | |
3100 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); | |
3101 | amdgpu_ring_write(ring, 0); | |
3102 | amdgpu_ring_write(ring, 1 << vm_id); | |
3103 | ||
3104 | /* wait for the invalidate to complete */ | |
3105 | amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); | |
3106 | amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ | |
3107 | WAIT_REG_MEM_FUNCTION(0) | /* always */ | |
3108 | WAIT_REG_MEM_ENGINE(0))); /* me */ | |
3109 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); | |
3110 | amdgpu_ring_write(ring, 0); | |
3111 | amdgpu_ring_write(ring, 0); /* ref */ | |
3112 | amdgpu_ring_write(ring, 0); /* mask */ | |
3113 | amdgpu_ring_write(ring, 0x20); /* poll interval */ | |
3114 | ||
3115 | /* compute doesn't have PFP */ | |
3116 | if (usepfp) { | |
3117 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ | |
3118 | amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); | |
3119 | amdgpu_ring_write(ring, 0x0); | |
3120 | ||
3121 | /* synce CE with ME to prevent CE fetch CEIB before context switch done */ | |
5c3422b0 | 3122 | amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); |
3123 | amdgpu_ring_write(ring, 0); | |
3124 | amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); | |
3125 | amdgpu_ring_write(ring, 0); | |
a2e73f56 AD |
3126 | } |
3127 | } | |
3128 | ||
3129 | /* | |
3130 | * RLC | |
3131 | * The RLC is a multi-purpose microengine that handles a | |
3132 | * variety of functions. | |
3133 | */ | |
3134 | static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) | |
3135 | { | |
3136 | int r; | |
3137 | ||
3138 | /* save restore block */ | |
3139 | if (adev->gfx.rlc.save_restore_obj) { | |
3140 | r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); | |
3141 | if (unlikely(r != 0)) | |
3142 | dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); | |
3143 | amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); | |
3144 | amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); | |
3145 | ||
3146 | amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); | |
3147 | adev->gfx.rlc.save_restore_obj = NULL; | |
3148 | } | |
3149 | ||
3150 | /* clear state block */ | |
3151 | if (adev->gfx.rlc.clear_state_obj) { | |
3152 | r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); | |
3153 | if (unlikely(r != 0)) | |
3154 | dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); | |
3155 | amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); | |
3156 | amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); | |
3157 | ||
3158 | amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); | |
3159 | adev->gfx.rlc.clear_state_obj = NULL; | |
3160 | } | |
3161 | ||
3162 | /* clear state block */ | |
3163 | if (adev->gfx.rlc.cp_table_obj) { | |
3164 | r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); | |
3165 | if (unlikely(r != 0)) | |
3166 | dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); | |
3167 | amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); | |
3168 | amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); | |
3169 | ||
3170 | amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); | |
3171 | adev->gfx.rlc.cp_table_obj = NULL; | |
3172 | } | |
3173 | } | |
3174 | ||
3175 | static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) | |
3176 | { | |
3177 | const u32 *src_ptr; | |
3178 | volatile u32 *dst_ptr; | |
3179 | u32 dws, i; | |
3180 | const struct cs_section_def *cs_data; | |
3181 | int r; | |
3182 | ||
3183 | /* allocate rlc buffers */ | |
2f7d10b3 | 3184 | if (adev->flags & AMD_IS_APU) { |
a2e73f56 AD |
3185 | if (adev->asic_type == CHIP_KAVERI) { |
3186 | adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; | |
3187 | adev->gfx.rlc.reg_list_size = | |
3188 | (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); | |
3189 | } else { | |
3190 | adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; | |
3191 | adev->gfx.rlc.reg_list_size = | |
3192 | (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); | |
3193 | } | |
3194 | } | |
3195 | adev->gfx.rlc.cs_data = ci_cs_data; | |
3196 | adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4; | |
3197 | ||
3198 | src_ptr = adev->gfx.rlc.reg_list; | |
3199 | dws = adev->gfx.rlc.reg_list_size; | |
3200 | dws += (5 * 16) + 48 + 48 + 64; | |
3201 | ||
3202 | cs_data = adev->gfx.rlc.cs_data; | |
3203 | ||
3204 | if (src_ptr) { | |
3205 | /* save restore block */ | |
3206 | if (adev->gfx.rlc.save_restore_obj == NULL) { | |
3207 | r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, | |
857d913d AD |
3208 | AMDGPU_GEM_DOMAIN_VRAM, |
3209 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b CK |
3210 | NULL, NULL, |
3211 | &adev->gfx.rlc.save_restore_obj); | |
a2e73f56 AD |
3212 | if (r) { |
3213 | dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); | |
3214 | return r; | |
3215 | } | |
3216 | } | |
3217 | ||
3218 | r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); | |
3219 | if (unlikely(r != 0)) { | |
3220 | gfx_v7_0_rlc_fini(adev); | |
3221 | return r; | |
3222 | } | |
3223 | r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, | |
3224 | &adev->gfx.rlc.save_restore_gpu_addr); | |
3225 | if (r) { | |
3226 | amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); | |
3227 | dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r); | |
3228 | gfx_v7_0_rlc_fini(adev); | |
3229 | return r; | |
3230 | } | |
3231 | ||
3232 | r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); | |
3233 | if (r) { | |
3234 | dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r); | |
3235 | gfx_v7_0_rlc_fini(adev); | |
3236 | return r; | |
3237 | } | |
3238 | /* write the sr buffer */ | |
3239 | dst_ptr = adev->gfx.rlc.sr_ptr; | |
3240 | for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) | |
3241 | dst_ptr[i] = cpu_to_le32(src_ptr[i]); | |
3242 | amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); | |
3243 | amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); | |
3244 | } | |
3245 | ||
3246 | if (cs_data) { | |
3247 | /* clear state block */ | |
3248 | adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); | |
3249 | ||
3250 | if (adev->gfx.rlc.clear_state_obj == NULL) { | |
3251 | r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, | |
857d913d AD |
3252 | AMDGPU_GEM_DOMAIN_VRAM, |
3253 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b CK |
3254 | NULL, NULL, |
3255 | &adev->gfx.rlc.clear_state_obj); | |
a2e73f56 AD |
3256 | if (r) { |
3257 | dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); | |
3258 | gfx_v7_0_rlc_fini(adev); | |
3259 | return r; | |
3260 | } | |
3261 | } | |
3262 | r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); | |
3263 | if (unlikely(r != 0)) { | |
3264 | gfx_v7_0_rlc_fini(adev); | |
3265 | return r; | |
3266 | } | |
3267 | r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, | |
3268 | &adev->gfx.rlc.clear_state_gpu_addr); | |
3269 | if (r) { | |
3270 | amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); | |
3271 | dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); | |
3272 | gfx_v7_0_rlc_fini(adev); | |
3273 | return r; | |
3274 | } | |
3275 | ||
3276 | r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); | |
3277 | if (r) { | |
3278 | dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); | |
3279 | gfx_v7_0_rlc_fini(adev); | |
3280 | return r; | |
3281 | } | |
3282 | /* set up the cs buffer */ | |
3283 | dst_ptr = adev->gfx.rlc.cs_ptr; | |
3284 | gfx_v7_0_get_csb_buffer(adev, dst_ptr); | |
3285 | amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); | |
3286 | amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); | |
3287 | } | |
3288 | ||
3289 | if (adev->gfx.rlc.cp_table_size) { | |
3290 | if (adev->gfx.rlc.cp_table_obj == NULL) { | |
3291 | r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, | |
857d913d AD |
3292 | AMDGPU_GEM_DOMAIN_VRAM, |
3293 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b CK |
3294 | NULL, NULL, |
3295 | &adev->gfx.rlc.cp_table_obj); | |
a2e73f56 AD |
3296 | if (r) { |
3297 | dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); | |
3298 | gfx_v7_0_rlc_fini(adev); | |
3299 | return r; | |
3300 | } | |
3301 | } | |
3302 | ||
3303 | r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); | |
3304 | if (unlikely(r != 0)) { | |
3305 | dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); | |
3306 | gfx_v7_0_rlc_fini(adev); | |
3307 | return r; | |
3308 | } | |
3309 | r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM, | |
3310 | &adev->gfx.rlc.cp_table_gpu_addr); | |
3311 | if (r) { | |
3312 | amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); | |
3313 | dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r); | |
3314 | gfx_v7_0_rlc_fini(adev); | |
3315 | return r; | |
3316 | } | |
3317 | r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); | |
3318 | if (r) { | |
3319 | dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r); | |
3320 | gfx_v7_0_rlc_fini(adev); | |
3321 | return r; | |
3322 | } | |
3323 | ||
3324 | gfx_v7_0_init_cp_pg_table(adev); | |
3325 | ||
3326 | amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); | |
3327 | amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); | |
3328 | ||
3329 | } | |
3330 | ||
3331 | return 0; | |
3332 | } | |
3333 | ||
3334 | static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) | |
3335 | { | |
3336 | u32 tmp; | |
3337 | ||
3338 | tmp = RREG32(mmRLC_LB_CNTL); | |
3339 | if (enable) | |
3340 | tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; | |
3341 | else | |
3342 | tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; | |
3343 | WREG32(mmRLC_LB_CNTL, tmp); | |
3344 | } | |
3345 | ||
3346 | static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) | |
3347 | { | |
3348 | u32 i, j, k; | |
3349 | u32 mask; | |
3350 | ||
3351 | mutex_lock(&adev->grbm_idx_mutex); | |
3352 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { | |
3353 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { | |
3354 | gfx_v7_0_select_se_sh(adev, i, j); | |
3355 | for (k = 0; k < adev->usec_timeout; k++) { | |
3356 | if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) | |
3357 | break; | |
3358 | udelay(1); | |
3359 | } | |
3360 | } | |
3361 | } | |
3362 | gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); | |
3363 | mutex_unlock(&adev->grbm_idx_mutex); | |
3364 | ||
3365 | mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | | |
3366 | RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | | |
3367 | RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | | |
3368 | RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; | |
3369 | for (k = 0; k < adev->usec_timeout; k++) { | |
3370 | if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) | |
3371 | break; | |
3372 | udelay(1); | |
3373 | } | |
3374 | } | |
3375 | ||
3376 | static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) | |
3377 | { | |
3378 | u32 tmp; | |
3379 | ||
3380 | tmp = RREG32(mmRLC_CNTL); | |
3381 | if (tmp != rlc) | |
3382 | WREG32(mmRLC_CNTL, rlc); | |
3383 | } | |
3384 | ||
3385 | static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) | |
3386 | { | |
3387 | u32 data, orig; | |
3388 | ||
3389 | orig = data = RREG32(mmRLC_CNTL); | |
3390 | ||
3391 | if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { | |
3392 | u32 i; | |
3393 | ||
3394 | data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; | |
3395 | WREG32(mmRLC_CNTL, data); | |
3396 | ||
3397 | for (i = 0; i < adev->usec_timeout; i++) { | |
3398 | if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) | |
3399 | break; | |
3400 | udelay(1); | |
3401 | } | |
3402 | ||
3403 | gfx_v7_0_wait_for_rlc_serdes(adev); | |
3404 | } | |
3405 | ||
3406 | return orig; | |
3407 | } | |
3408 | ||
3409 | void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev) | |
3410 | { | |
3411 | u32 tmp, i, mask; | |
3412 | ||
3413 | tmp = 0x1 | (1 << 1); | |
3414 | WREG32(mmRLC_GPR_REG2, tmp); | |
3415 | ||
3416 | mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | | |
3417 | RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; | |
3418 | for (i = 0; i < adev->usec_timeout; i++) { | |
3419 | if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) | |
3420 | break; | |
3421 | udelay(1); | |
3422 | } | |
3423 | ||
3424 | for (i = 0; i < adev->usec_timeout; i++) { | |
3425 | if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) | |
3426 | break; | |
3427 | udelay(1); | |
3428 | } | |
3429 | } | |
3430 | ||
3431 | void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev) | |
3432 | { | |
3433 | u32 tmp; | |
3434 | ||
3435 | tmp = 0x1 | (0 << 1); | |
3436 | WREG32(mmRLC_GPR_REG2, tmp); | |
3437 | } | |
3438 | ||
3439 | /** | |
3440 | * gfx_v7_0_rlc_stop - stop the RLC ME | |
3441 | * | |
3442 | * @adev: amdgpu_device pointer | |
3443 | * | |
3444 | * Halt the RLC ME (MicroEngine) (CIK). | |
3445 | */ | |
3446 | void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) | |
3447 | { | |
3448 | WREG32(mmRLC_CNTL, 0); | |
3449 | ||
3450 | gfx_v7_0_enable_gui_idle_interrupt(adev, false); | |
3451 | ||
3452 | gfx_v7_0_wait_for_rlc_serdes(adev); | |
3453 | } | |
3454 | ||
3455 | /** | |
3456 | * gfx_v7_0_rlc_start - start the RLC ME | |
3457 | * | |
3458 | * @adev: amdgpu_device pointer | |
3459 | * | |
3460 | * Unhalt the RLC ME (MicroEngine) (CIK). | |
3461 | */ | |
3462 | static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) | |
3463 | { | |
3464 | WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); | |
3465 | ||
3466 | gfx_v7_0_enable_gui_idle_interrupt(adev, true); | |
3467 | ||
3468 | udelay(50); | |
3469 | } | |
3470 | ||
3471 | static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) | |
3472 | { | |
3473 | u32 tmp = RREG32(mmGRBM_SOFT_RESET); | |
3474 | ||
3475 | tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; | |
3476 | WREG32(mmGRBM_SOFT_RESET, tmp); | |
3477 | udelay(50); | |
3478 | tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; | |
3479 | WREG32(mmGRBM_SOFT_RESET, tmp); | |
3480 | udelay(50); | |
3481 | } | |
3482 | ||
3483 | /** | |
3484 | * gfx_v7_0_rlc_resume - setup the RLC hw | |
3485 | * | |
3486 | * @adev: amdgpu_device pointer | |
3487 | * | |
3488 | * Initialize the RLC registers, load the ucode, | |
3489 | * and start the RLC (CIK). | |
3490 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
3491 | */ | |
3492 | static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) | |
3493 | { | |
3494 | const struct rlc_firmware_header_v1_0 *hdr; | |
3495 | const __le32 *fw_data; | |
3496 | unsigned i, fw_size; | |
3497 | u32 tmp; | |
3498 | ||
3499 | if (!adev->gfx.rlc_fw) | |
3500 | return -EINVAL; | |
3501 | ||
3502 | hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; | |
3503 | amdgpu_ucode_print_rlc_hdr(&hdr->header); | |
3504 | adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); | |
351643d7 JZ |
3505 | adev->gfx.rlc_feature_version = le32_to_cpu( |
3506 | hdr->ucode_feature_version); | |
a2e73f56 AD |
3507 | |
3508 | gfx_v7_0_rlc_stop(adev); | |
3509 | ||
3510 | /* disable CG */ | |
3511 | tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; | |
3512 | WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); | |
3513 | ||
3514 | gfx_v7_0_rlc_reset(adev); | |
3515 | ||
3516 | gfx_v7_0_init_pg(adev); | |
3517 | ||
3518 | WREG32(mmRLC_LB_CNTR_INIT, 0); | |
3519 | WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); | |
3520 | ||
3521 | mutex_lock(&adev->grbm_idx_mutex); | |
3522 | gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); | |
3523 | WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); | |
3524 | WREG32(mmRLC_LB_PARAMS, 0x00600408); | |
3525 | WREG32(mmRLC_LB_CNTL, 0x80000004); | |
3526 | mutex_unlock(&adev->grbm_idx_mutex); | |
3527 | ||
3528 | WREG32(mmRLC_MC_CNTL, 0); | |
3529 | WREG32(mmRLC_UCODE_CNTL, 0); | |
3530 | ||
3531 | fw_data = (const __le32 *) | |
3532 | (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
3533 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
3534 | WREG32(mmRLC_GPM_UCODE_ADDR, 0); | |
3535 | for (i = 0; i < fw_size; i++) | |
3536 | WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); | |
3537 | WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); | |
3538 | ||
3539 | /* XXX - find out what chips support lbpw */ | |
3540 | gfx_v7_0_enable_lbpw(adev, false); | |
3541 | ||
3542 | if (adev->asic_type == CHIP_BONAIRE) | |
3543 | WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); | |
3544 | ||
3545 | gfx_v7_0_rlc_start(adev); | |
3546 | ||
3547 | return 0; | |
3548 | } | |
3549 | ||
3550 | static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) | |
3551 | { | |
3552 | u32 data, orig, tmp, tmp2; | |
3553 | ||
3554 | orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); | |
3555 | ||
3556 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) { | |
3557 | gfx_v7_0_enable_gui_idle_interrupt(adev, true); | |
3558 | ||
3559 | tmp = gfx_v7_0_halt_rlc(adev); | |
3560 | ||
3561 | mutex_lock(&adev->grbm_idx_mutex); | |
3562 | gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); | |
3563 | WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); | |
3564 | WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); | |
3565 | tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | | |
3566 | RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | | |
3567 | RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; | |
3568 | WREG32(mmRLC_SERDES_WR_CTRL, tmp2); | |
3569 | mutex_unlock(&adev->grbm_idx_mutex); | |
3570 | ||
3571 | gfx_v7_0_update_rlc(adev, tmp); | |
3572 | ||
3573 | data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; | |
3574 | } else { | |
3575 | gfx_v7_0_enable_gui_idle_interrupt(adev, false); | |
3576 | ||
3577 | RREG32(mmCB_CGTT_SCLK_CTRL); | |
3578 | RREG32(mmCB_CGTT_SCLK_CTRL); | |
3579 | RREG32(mmCB_CGTT_SCLK_CTRL); | |
3580 | RREG32(mmCB_CGTT_SCLK_CTRL); | |
3581 | ||
3582 | data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); | |
3583 | } | |
3584 | ||
3585 | if (orig != data) | |
3586 | WREG32(mmRLC_CGCG_CGLS_CTRL, data); | |
3587 | ||
3588 | } | |
3589 | ||
3590 | static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) | |
3591 | { | |
3592 | u32 data, orig, tmp = 0; | |
3593 | ||
3594 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) { | |
3595 | if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) { | |
3596 | if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) { | |
3597 | orig = data = RREG32(mmCP_MEM_SLP_CNTL); | |
3598 | data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; | |
3599 | if (orig != data) | |
3600 | WREG32(mmCP_MEM_SLP_CNTL, data); | |
3601 | } | |
3602 | } | |
3603 | ||
3604 | orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); | |
3605 | data |= 0x00000001; | |
3606 | data &= 0xfffffffd; | |
3607 | if (orig != data) | |
3608 | WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); | |
3609 | ||
3610 | tmp = gfx_v7_0_halt_rlc(adev); | |
3611 | ||
3612 | mutex_lock(&adev->grbm_idx_mutex); | |
3613 | gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); | |
3614 | WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); | |
3615 | WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); | |
3616 | data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | | |
3617 | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; | |
3618 | WREG32(mmRLC_SERDES_WR_CTRL, data); | |
3619 | mutex_unlock(&adev->grbm_idx_mutex); | |
3620 | ||
3621 | gfx_v7_0_update_rlc(adev, tmp); | |
3622 | ||
3623 | if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) { | |
3624 | orig = data = RREG32(mmCGTS_SM_CTRL_REG); | |
3625 | data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; | |
3626 | data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); | |
3627 | data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; | |
3628 | data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; | |
3629 | if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) && | |
3630 | (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS)) | |
3631 | data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; | |
3632 | data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; | |
3633 | data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; | |
3634 | data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); | |
3635 | if (orig != data) | |
3636 | WREG32(mmCGTS_SM_CTRL_REG, data); | |
3637 | } | |
3638 | } else { | |
3639 | orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); | |
3640 | data |= 0x00000003; | |
3641 | if (orig != data) | |
3642 | WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); | |
3643 | ||
3644 | data = RREG32(mmRLC_MEM_SLP_CNTL); | |
3645 | if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { | |
3646 | data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; | |
3647 | WREG32(mmRLC_MEM_SLP_CNTL, data); | |
3648 | } | |
3649 | ||
3650 | data = RREG32(mmCP_MEM_SLP_CNTL); | |
3651 | if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { | |
3652 | data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; | |
3653 | WREG32(mmCP_MEM_SLP_CNTL, data); | |
3654 | } | |
3655 | ||
3656 | orig = data = RREG32(mmCGTS_SM_CTRL_REG); | |
3657 | data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; | |
3658 | if (orig != data) | |
3659 | WREG32(mmCGTS_SM_CTRL_REG, data); | |
3660 | ||
3661 | tmp = gfx_v7_0_halt_rlc(adev); | |
3662 | ||
3663 | mutex_lock(&adev->grbm_idx_mutex); | |
3664 | gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); | |
3665 | WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); | |
3666 | WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); | |
3667 | data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; | |
3668 | WREG32(mmRLC_SERDES_WR_CTRL, data); | |
3669 | mutex_unlock(&adev->grbm_idx_mutex); | |
3670 | ||
3671 | gfx_v7_0_update_rlc(adev, tmp); | |
3672 | } | |
3673 | } | |
3674 | ||
3675 | static void gfx_v7_0_update_cg(struct amdgpu_device *adev, | |
3676 | bool enable) | |
3677 | { | |
3678 | gfx_v7_0_enable_gui_idle_interrupt(adev, false); | |
3679 | /* order matters! */ | |
3680 | if (enable) { | |
3681 | gfx_v7_0_enable_mgcg(adev, true); | |
3682 | gfx_v7_0_enable_cgcg(adev, true); | |
3683 | } else { | |
3684 | gfx_v7_0_enable_cgcg(adev, false); | |
3685 | gfx_v7_0_enable_mgcg(adev, false); | |
3686 | } | |
3687 | gfx_v7_0_enable_gui_idle_interrupt(adev, true); | |
3688 | } | |
3689 | ||
3690 | static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, | |
3691 | bool enable) | |
3692 | { | |
3693 | u32 data, orig; | |
3694 | ||
3695 | orig = data = RREG32(mmRLC_PG_CNTL); | |
3696 | if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS)) | |
3697 | data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; | |
3698 | else | |
3699 | data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; | |
3700 | if (orig != data) | |
3701 | WREG32(mmRLC_PG_CNTL, data); | |
3702 | } | |
3703 | ||
3704 | static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, | |
3705 | bool enable) | |
3706 | { | |
3707 | u32 data, orig; | |
3708 | ||
3709 | orig = data = RREG32(mmRLC_PG_CNTL); | |
3710 | if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS)) | |
3711 | data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; | |
3712 | else | |
3713 | data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; | |
3714 | if (orig != data) | |
3715 | WREG32(mmRLC_PG_CNTL, data); | |
3716 | } | |
3717 | ||
3718 | static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) | |
3719 | { | |
3720 | u32 data, orig; | |
3721 | ||
3722 | orig = data = RREG32(mmRLC_PG_CNTL); | |
3723 | if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP)) | |
3724 | data &= ~0x8000; | |
3725 | else | |
3726 | data |= 0x8000; | |
3727 | if (orig != data) | |
3728 | WREG32(mmRLC_PG_CNTL, data); | |
3729 | } | |
3730 | ||
3731 | static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) | |
3732 | { | |
3733 | u32 data, orig; | |
3734 | ||
3735 | orig = data = RREG32(mmRLC_PG_CNTL); | |
3736 | if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS)) | |
3737 | data &= ~0x2000; | |
3738 | else | |
3739 | data |= 0x2000; | |
3740 | if (orig != data) | |
3741 | WREG32(mmRLC_PG_CNTL, data); | |
3742 | } | |
3743 | ||
3744 | static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev) | |
3745 | { | |
3746 | const __le32 *fw_data; | |
3747 | volatile u32 *dst_ptr; | |
3748 | int me, i, max_me = 4; | |
3749 | u32 bo_offset = 0; | |
3750 | u32 table_offset, table_size; | |
3751 | ||
3752 | if (adev->asic_type == CHIP_KAVERI) | |
3753 | max_me = 5; | |
3754 | ||
3755 | if (adev->gfx.rlc.cp_table_ptr == NULL) | |
3756 | return; | |
3757 | ||
3758 | /* write the cp table buffer */ | |
3759 | dst_ptr = adev->gfx.rlc.cp_table_ptr; | |
3760 | for (me = 0; me < max_me; me++) { | |
3761 | if (me == 0) { | |
3762 | const struct gfx_firmware_header_v1_0 *hdr = | |
3763 | (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; | |
3764 | fw_data = (const __le32 *) | |
3765 | (adev->gfx.ce_fw->data + | |
3766 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
3767 | table_offset = le32_to_cpu(hdr->jt_offset); | |
3768 | table_size = le32_to_cpu(hdr->jt_size); | |
3769 | } else if (me == 1) { | |
3770 | const struct gfx_firmware_header_v1_0 *hdr = | |
3771 | (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; | |
3772 | fw_data = (const __le32 *) | |
3773 | (adev->gfx.pfp_fw->data + | |
3774 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
3775 | table_offset = le32_to_cpu(hdr->jt_offset); | |
3776 | table_size = le32_to_cpu(hdr->jt_size); | |
3777 | } else if (me == 2) { | |
3778 | const struct gfx_firmware_header_v1_0 *hdr = | |
3779 | (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; | |
3780 | fw_data = (const __le32 *) | |
3781 | (adev->gfx.me_fw->data + | |
3782 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
3783 | table_offset = le32_to_cpu(hdr->jt_offset); | |
3784 | table_size = le32_to_cpu(hdr->jt_size); | |
3785 | } else if (me == 3) { | |
3786 | const struct gfx_firmware_header_v1_0 *hdr = | |
3787 | (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; | |
3788 | fw_data = (const __le32 *) | |
3789 | (adev->gfx.mec_fw->data + | |
3790 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
3791 | table_offset = le32_to_cpu(hdr->jt_offset); | |
3792 | table_size = le32_to_cpu(hdr->jt_size); | |
3793 | } else { | |
3794 | const struct gfx_firmware_header_v1_0 *hdr = | |
3795 | (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; | |
3796 | fw_data = (const __le32 *) | |
3797 | (adev->gfx.mec2_fw->data + | |
3798 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
3799 | table_offset = le32_to_cpu(hdr->jt_offset); | |
3800 | table_size = le32_to_cpu(hdr->jt_size); | |
3801 | } | |
3802 | ||
3803 | for (i = 0; i < table_size; i ++) { | |
3804 | dst_ptr[bo_offset + i] = | |
3805 | cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); | |
3806 | } | |
3807 | ||
3808 | bo_offset += table_size; | |
3809 | } | |
3810 | } | |
3811 | ||
3812 | static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, | |
3813 | bool enable) | |
3814 | { | |
3815 | u32 data, orig; | |
3816 | ||
3817 | if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) { | |
3818 | orig = data = RREG32(mmRLC_PG_CNTL); | |
3819 | data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; | |
3820 | if (orig != data) | |
3821 | WREG32(mmRLC_PG_CNTL, data); | |
3822 | ||
3823 | orig = data = RREG32(mmRLC_AUTO_PG_CTRL); | |
3824 | data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; | |
3825 | if (orig != data) | |
3826 | WREG32(mmRLC_AUTO_PG_CTRL, data); | |
3827 | } else { | |
3828 | orig = data = RREG32(mmRLC_PG_CNTL); | |
3829 | data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; | |
3830 | if (orig != data) | |
3831 | WREG32(mmRLC_PG_CNTL, data); | |
3832 | ||
3833 | orig = data = RREG32(mmRLC_AUTO_PG_CTRL); | |
3834 | data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; | |
3835 | if (orig != data) | |
3836 | WREG32(mmRLC_AUTO_PG_CTRL, data); | |
3837 | ||
3838 | data = RREG32(mmDB_RENDER_CONTROL); | |
3839 | } | |
3840 | } | |
3841 | ||
8f8e00c1 | 3842 | static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) |
a2e73f56 | 3843 | { |
8f8e00c1 | 3844 | u32 data, mask; |
a2e73f56 | 3845 | |
8f8e00c1 AD |
3846 | data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); |
3847 | data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); | |
a2e73f56 | 3848 | |
8f8e00c1 AD |
3849 | data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; |
3850 | data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; | |
a2e73f56 | 3851 | |
6157bd7a | 3852 | mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh); |
a2e73f56 | 3853 | |
8f8e00c1 | 3854 | return (~data) & mask; |
a2e73f56 AD |
3855 | } |
3856 | ||
3857 | static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) | |
3858 | { | |
3859 | uint32_t tmp, active_cu_number; | |
3860 | struct amdgpu_cu_info cu_info; | |
3861 | ||
3862 | gfx_v7_0_get_cu_info(adev, &cu_info); | |
3863 | tmp = cu_info.ao_cu_mask; | |
3864 | active_cu_number = cu_info.number; | |
3865 | ||
3866 | WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp); | |
3867 | ||
3868 | tmp = RREG32(mmRLC_MAX_PG_CU); | |
3869 | tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; | |
3870 | tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); | |
3871 | WREG32(mmRLC_MAX_PG_CU, tmp); | |
3872 | } | |
3873 | ||
3874 | static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, | |
3875 | bool enable) | |
3876 | { | |
3877 | u32 data, orig; | |
3878 | ||
3879 | orig = data = RREG32(mmRLC_PG_CNTL); | |
3880 | if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG)) | |
3881 | data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; | |
3882 | else | |
3883 | data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; | |
3884 | if (orig != data) | |
3885 | WREG32(mmRLC_PG_CNTL, data); | |
3886 | } | |
3887 | ||
3888 | static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, | |
3889 | bool enable) | |
3890 | { | |
3891 | u32 data, orig; | |
3892 | ||
3893 | orig = data = RREG32(mmRLC_PG_CNTL); | |
3894 | if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG)) | |
3895 | data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; | |
3896 | else | |
3897 | data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; | |
3898 | if (orig != data) | |
3899 | WREG32(mmRLC_PG_CNTL, data); | |
3900 | } | |
3901 | ||
3902 | #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 | |
3903 | #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D | |
3904 | ||
3905 | static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) | |
3906 | { | |
3907 | u32 data, orig; | |
3908 | u32 i; | |
3909 | ||
3910 | if (adev->gfx.rlc.cs_data) { | |
3911 | WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); | |
3912 | WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); | |
3913 | WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); | |
3914 | WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); | |
3915 | } else { | |
3916 | WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); | |
3917 | for (i = 0; i < 3; i++) | |
3918 | WREG32(mmRLC_GPM_SCRATCH_DATA, 0); | |
3919 | } | |
3920 | if (adev->gfx.rlc.reg_list) { | |
3921 | WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); | |
3922 | for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) | |
3923 | WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); | |
3924 | } | |
3925 | ||
3926 | orig = data = RREG32(mmRLC_PG_CNTL); | |
3927 | data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; | |
3928 | if (orig != data) | |
3929 | WREG32(mmRLC_PG_CNTL, data); | |
3930 | ||
3931 | WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); | |
3932 | WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); | |
3933 | ||
3934 | data = RREG32(mmCP_RB_WPTR_POLL_CNTL); | |
3935 | data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; | |
3936 | data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); | |
3937 | WREG32(mmCP_RB_WPTR_POLL_CNTL, data); | |
3938 | ||
3939 | data = 0x10101010; | |
3940 | WREG32(mmRLC_PG_DELAY, data); | |
3941 | ||
3942 | data = RREG32(mmRLC_PG_DELAY_2); | |
3943 | data &= ~0xff; | |
3944 | data |= 0x3; | |
3945 | WREG32(mmRLC_PG_DELAY_2, data); | |
3946 | ||
3947 | data = RREG32(mmRLC_AUTO_PG_CTRL); | |
3948 | data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; | |
3949 | data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); | |
3950 | WREG32(mmRLC_AUTO_PG_CTRL, data); | |
3951 | ||
3952 | } | |
3953 | ||
3954 | static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) | |
3955 | { | |
3956 | gfx_v7_0_enable_gfx_cgpg(adev, enable); | |
3957 | gfx_v7_0_enable_gfx_static_mgpg(adev, enable); | |
3958 | gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); | |
3959 | } | |
3960 | ||
3961 | static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) | |
3962 | { | |
3963 | u32 count = 0; | |
3964 | const struct cs_section_def *sect = NULL; | |
3965 | const struct cs_extent_def *ext = NULL; | |
3966 | ||
3967 | if (adev->gfx.rlc.cs_data == NULL) | |
3968 | return 0; | |
3969 | ||
3970 | /* begin clear state */ | |
3971 | count += 2; | |
3972 | /* context control state */ | |
3973 | count += 3; | |
3974 | ||
3975 | for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { | |
3976 | for (ext = sect->section; ext->extent != NULL; ++ext) { | |
3977 | if (sect->id == SECT_CONTEXT) | |
3978 | count += 2 + ext->reg_count; | |
3979 | else | |
3980 | return 0; | |
3981 | } | |
3982 | } | |
3983 | /* pa_sc_raster_config/pa_sc_raster_config1 */ | |
3984 | count += 4; | |
3985 | /* end clear state */ | |
3986 | count += 2; | |
3987 | /* clear state */ | |
3988 | count += 2; | |
3989 | ||
3990 | return count; | |
3991 | } | |
3992 | ||
3993 | static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, | |
3994 | volatile u32 *buffer) | |
3995 | { | |
3996 | u32 count = 0, i; | |
3997 | const struct cs_section_def *sect = NULL; | |
3998 | const struct cs_extent_def *ext = NULL; | |
3999 | ||
4000 | if (adev->gfx.rlc.cs_data == NULL) | |
4001 | return; | |
4002 | if (buffer == NULL) | |
4003 | return; | |
4004 | ||
4005 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | |
4006 | buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); | |
4007 | ||
4008 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); | |
4009 | buffer[count++] = cpu_to_le32(0x80000000); | |
4010 | buffer[count++] = cpu_to_le32(0x80000000); | |
4011 | ||
4012 | for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { | |
4013 | for (ext = sect->section; ext->extent != NULL; ++ext) { | |
4014 | if (sect->id == SECT_CONTEXT) { | |
4015 | buffer[count++] = | |
4016 | cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); | |
4017 | buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); | |
4018 | for (i = 0; i < ext->reg_count; i++) | |
4019 | buffer[count++] = cpu_to_le32(ext->extent[i]); | |
4020 | } else { | |
4021 | return; | |
4022 | } | |
4023 | } | |
4024 | } | |
4025 | ||
4026 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); | |
4027 | buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); | |
4028 | switch (adev->asic_type) { | |
4029 | case CHIP_BONAIRE: | |
4030 | buffer[count++] = cpu_to_le32(0x16000012); | |
4031 | buffer[count++] = cpu_to_le32(0x00000000); | |
4032 | break; | |
4033 | case CHIP_KAVERI: | |
4034 | buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ | |
4035 | buffer[count++] = cpu_to_le32(0x00000000); | |
4036 | break; | |
4037 | case CHIP_KABINI: | |
4038 | case CHIP_MULLINS: | |
4039 | buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ | |
4040 | buffer[count++] = cpu_to_le32(0x00000000); | |
4041 | break; | |
4042 | case CHIP_HAWAII: | |
4043 | buffer[count++] = cpu_to_le32(0x3a00161a); | |
4044 | buffer[count++] = cpu_to_le32(0x0000002e); | |
4045 | break; | |
4046 | default: | |
4047 | buffer[count++] = cpu_to_le32(0x00000000); | |
4048 | buffer[count++] = cpu_to_le32(0x00000000); | |
4049 | break; | |
4050 | } | |
4051 | ||
4052 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | |
4053 | buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); | |
4054 | ||
4055 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); | |
4056 | buffer[count++] = cpu_to_le32(0); | |
4057 | } | |
4058 | ||
4059 | static void gfx_v7_0_init_pg(struct amdgpu_device *adev) | |
4060 | { | |
4061 | if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | | |
4062 | AMDGPU_PG_SUPPORT_GFX_SMG | | |
4063 | AMDGPU_PG_SUPPORT_GFX_DMG | | |
4064 | AMDGPU_PG_SUPPORT_CP | | |
4065 | AMDGPU_PG_SUPPORT_GDS | | |
4066 | AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { | |
4067 | gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); | |
4068 | gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); | |
4069 | if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { | |
4070 | gfx_v7_0_init_gfx_cgpg(adev); | |
4071 | gfx_v7_0_enable_cp_pg(adev, true); | |
4072 | gfx_v7_0_enable_gds_pg(adev, true); | |
4073 | } | |
4074 | gfx_v7_0_init_ao_cu_mask(adev); | |
4075 | gfx_v7_0_update_gfx_pg(adev, true); | |
4076 | } | |
4077 | } | |
4078 | ||
4079 | static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) | |
4080 | { | |
4081 | if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | | |
4082 | AMDGPU_PG_SUPPORT_GFX_SMG | | |
4083 | AMDGPU_PG_SUPPORT_GFX_DMG | | |
4084 | AMDGPU_PG_SUPPORT_CP | | |
4085 | AMDGPU_PG_SUPPORT_GDS | | |
4086 | AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { | |
4087 | gfx_v7_0_update_gfx_pg(adev, false); | |
4088 | if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { | |
4089 | gfx_v7_0_enable_cp_pg(adev, false); | |
4090 | gfx_v7_0_enable_gds_pg(adev, false); | |
4091 | } | |
4092 | } | |
4093 | } | |
4094 | ||
4095 | /** | |
4096 | * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot | |
4097 | * | |
4098 | * @adev: amdgpu_device pointer | |
4099 | * | |
4100 | * Fetches a GPU clock counter snapshot (SI). | |
4101 | * Returns the 64 bit clock counter snapshot. | |
4102 | */ | |
4103 | uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) | |
4104 | { | |
4105 | uint64_t clock; | |
4106 | ||
4107 | mutex_lock(&adev->gfx.gpu_clock_mutex); | |
4108 | WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); | |
4109 | clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | | |
4110 | ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); | |
4111 | mutex_unlock(&adev->gfx.gpu_clock_mutex); | |
4112 | return clock; | |
4113 | } | |
4114 | ||
4115 | static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, | |
4116 | uint32_t vmid, | |
4117 | uint32_t gds_base, uint32_t gds_size, | |
4118 | uint32_t gws_base, uint32_t gws_size, | |
4119 | uint32_t oa_base, uint32_t oa_size) | |
4120 | { | |
4121 | gds_base = gds_base >> AMDGPU_GDS_SHIFT; | |
4122 | gds_size = gds_size >> AMDGPU_GDS_SHIFT; | |
4123 | ||
4124 | gws_base = gws_base >> AMDGPU_GWS_SHIFT; | |
4125 | gws_size = gws_size >> AMDGPU_GWS_SHIFT; | |
4126 | ||
4127 | oa_base = oa_base >> AMDGPU_OA_SHIFT; | |
4128 | oa_size = oa_size >> AMDGPU_OA_SHIFT; | |
4129 | ||
4130 | /* GDS Base */ | |
4131 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
4132 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | |
4133 | WRITE_DATA_DST_SEL(0))); | |
4134 | amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); | |
4135 | amdgpu_ring_write(ring, 0); | |
4136 | amdgpu_ring_write(ring, gds_base); | |
4137 | ||
4138 | /* GDS Size */ | |
4139 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
4140 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | |
4141 | WRITE_DATA_DST_SEL(0))); | |
4142 | amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); | |
4143 | amdgpu_ring_write(ring, 0); | |
4144 | amdgpu_ring_write(ring, gds_size); | |
4145 | ||
4146 | /* GWS */ | |
4147 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
4148 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | |
4149 | WRITE_DATA_DST_SEL(0))); | |
4150 | amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); | |
4151 | amdgpu_ring_write(ring, 0); | |
4152 | amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); | |
4153 | ||
4154 | /* OA */ | |
4155 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
4156 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | |
4157 | WRITE_DATA_DST_SEL(0))); | |
4158 | amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); | |
4159 | amdgpu_ring_write(ring, 0); | |
4160 | amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); | |
4161 | } | |
4162 | ||
5fc3aeeb | 4163 | static int gfx_v7_0_early_init(void *handle) |
a2e73f56 | 4164 | { |
5fc3aeeb | 4165 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
4166 | |
4167 | adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; | |
4168 | adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS; | |
4169 | gfx_v7_0_set_ring_funcs(adev); | |
4170 | gfx_v7_0_set_irq_funcs(adev); | |
4171 | gfx_v7_0_set_gds_init(adev); | |
4172 | ||
4173 | return 0; | |
4174 | } | |
4175 | ||
ef720532 AD |
4176 | static int gfx_v7_0_late_init(void *handle) |
4177 | { | |
4178 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
4179 | int r; | |
4180 | ||
4181 | r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); | |
4182 | if (r) | |
4183 | return r; | |
4184 | ||
4185 | r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); | |
4186 | if (r) | |
4187 | return r; | |
4188 | ||
4189 | return 0; | |
4190 | } | |
4191 | ||
d93f3ca7 AD |
4192 | static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) |
4193 | { | |
4194 | u32 gb_addr_config; | |
4195 | u32 mc_shared_chmap, mc_arb_ramcfg; | |
4196 | u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; | |
4197 | u32 tmp; | |
4198 | ||
4199 | switch (adev->asic_type) { | |
4200 | case CHIP_BONAIRE: | |
4201 | adev->gfx.config.max_shader_engines = 2; | |
4202 | adev->gfx.config.max_tile_pipes = 4; | |
4203 | adev->gfx.config.max_cu_per_sh = 7; | |
4204 | adev->gfx.config.max_sh_per_se = 1; | |
4205 | adev->gfx.config.max_backends_per_se = 2; | |
4206 | adev->gfx.config.max_texture_channel_caches = 4; | |
4207 | adev->gfx.config.max_gprs = 256; | |
4208 | adev->gfx.config.max_gs_threads = 32; | |
4209 | adev->gfx.config.max_hw_contexts = 8; | |
4210 | ||
4211 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | |
4212 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
4213 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | |
4214 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; | |
4215 | gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; | |
4216 | break; | |
4217 | case CHIP_HAWAII: | |
4218 | adev->gfx.config.max_shader_engines = 4; | |
4219 | adev->gfx.config.max_tile_pipes = 16; | |
4220 | adev->gfx.config.max_cu_per_sh = 11; | |
4221 | adev->gfx.config.max_sh_per_se = 1; | |
4222 | adev->gfx.config.max_backends_per_se = 4; | |
4223 | adev->gfx.config.max_texture_channel_caches = 16; | |
4224 | adev->gfx.config.max_gprs = 256; | |
4225 | adev->gfx.config.max_gs_threads = 32; | |
4226 | adev->gfx.config.max_hw_contexts = 8; | |
4227 | ||
4228 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | |
4229 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
4230 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | |
4231 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; | |
4232 | gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; | |
4233 | break; | |
4234 | case CHIP_KAVERI: | |
4235 | adev->gfx.config.max_shader_engines = 1; | |
4236 | adev->gfx.config.max_tile_pipes = 4; | |
4237 | if ((adev->pdev->device == 0x1304) || | |
4238 | (adev->pdev->device == 0x1305) || | |
4239 | (adev->pdev->device == 0x130C) || | |
4240 | (adev->pdev->device == 0x130F) || | |
4241 | (adev->pdev->device == 0x1310) || | |
4242 | (adev->pdev->device == 0x1311) || | |
4243 | (adev->pdev->device == 0x131C)) { | |
4244 | adev->gfx.config.max_cu_per_sh = 8; | |
4245 | adev->gfx.config.max_backends_per_se = 2; | |
4246 | } else if ((adev->pdev->device == 0x1309) || | |
4247 | (adev->pdev->device == 0x130A) || | |
4248 | (adev->pdev->device == 0x130D) || | |
4249 | (adev->pdev->device == 0x1313) || | |
4250 | (adev->pdev->device == 0x131D)) { | |
4251 | adev->gfx.config.max_cu_per_sh = 6; | |
4252 | adev->gfx.config.max_backends_per_se = 2; | |
4253 | } else if ((adev->pdev->device == 0x1306) || | |
4254 | (adev->pdev->device == 0x1307) || | |
4255 | (adev->pdev->device == 0x130B) || | |
4256 | (adev->pdev->device == 0x130E) || | |
4257 | (adev->pdev->device == 0x1315) || | |
4258 | (adev->pdev->device == 0x131B)) { | |
4259 | adev->gfx.config.max_cu_per_sh = 4; | |
4260 | adev->gfx.config.max_backends_per_se = 1; | |
4261 | } else { | |
4262 | adev->gfx.config.max_cu_per_sh = 3; | |
4263 | adev->gfx.config.max_backends_per_se = 1; | |
4264 | } | |
4265 | adev->gfx.config.max_sh_per_se = 1; | |
4266 | adev->gfx.config.max_texture_channel_caches = 4; | |
4267 | adev->gfx.config.max_gprs = 256; | |
4268 | adev->gfx.config.max_gs_threads = 16; | |
4269 | adev->gfx.config.max_hw_contexts = 8; | |
4270 | ||
4271 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | |
4272 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
4273 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | |
4274 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; | |
4275 | gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; | |
4276 | break; | |
4277 | case CHIP_KABINI: | |
4278 | case CHIP_MULLINS: | |
4279 | default: | |
4280 | adev->gfx.config.max_shader_engines = 1; | |
4281 | adev->gfx.config.max_tile_pipes = 2; | |
4282 | adev->gfx.config.max_cu_per_sh = 2; | |
4283 | adev->gfx.config.max_sh_per_se = 1; | |
4284 | adev->gfx.config.max_backends_per_se = 1; | |
4285 | adev->gfx.config.max_texture_channel_caches = 2; | |
4286 | adev->gfx.config.max_gprs = 256; | |
4287 | adev->gfx.config.max_gs_threads = 16; | |
4288 | adev->gfx.config.max_hw_contexts = 8; | |
4289 | ||
4290 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | |
4291 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
4292 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | |
4293 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; | |
4294 | gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; | |
4295 | break; | |
4296 | } | |
4297 | ||
4298 | mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); | |
4299 | adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); | |
4300 | mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; | |
4301 | ||
4302 | adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; | |
4303 | adev->gfx.config.mem_max_burst_length_bytes = 256; | |
4304 | if (adev->flags & AMD_IS_APU) { | |
4305 | /* Get memory bank mapping mode. */ | |
4306 | tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); | |
4307 | dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); | |
4308 | dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); | |
4309 | ||
4310 | tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); | |
4311 | dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); | |
4312 | dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); | |
4313 | ||
4314 | /* Validate settings in case only one DIMM installed. */ | |
4315 | if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) | |
4316 | dimm00_addr_map = 0; | |
4317 | if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) | |
4318 | dimm01_addr_map = 0; | |
4319 | if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) | |
4320 | dimm10_addr_map = 0; | |
4321 | if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) | |
4322 | dimm11_addr_map = 0; | |
4323 | ||
4324 | /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ | |
4325 | /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ | |
4326 | if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) | |
4327 | adev->gfx.config.mem_row_size_in_kb = 2; | |
4328 | else | |
4329 | adev->gfx.config.mem_row_size_in_kb = 1; | |
4330 | } else { | |
4331 | tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; | |
4332 | adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; | |
4333 | if (adev->gfx.config.mem_row_size_in_kb > 4) | |
4334 | adev->gfx.config.mem_row_size_in_kb = 4; | |
4335 | } | |
4336 | /* XXX use MC settings? */ | |
4337 | adev->gfx.config.shader_engine_tile_size = 32; | |
4338 | adev->gfx.config.num_gpus = 1; | |
4339 | adev->gfx.config.multi_gpu_tile_size = 64; | |
4340 | ||
4341 | /* fix up row size */ | |
4342 | gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; | |
4343 | switch (adev->gfx.config.mem_row_size_in_kb) { | |
4344 | case 1: | |
4345 | default: | |
4346 | gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); | |
4347 | break; | |
4348 | case 2: | |
4349 | gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); | |
4350 | break; | |
4351 | case 4: | |
4352 | gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); | |
4353 | break; | |
4354 | } | |
4355 | adev->gfx.config.gb_addr_config = gb_addr_config; | |
4356 | } | |
4357 | ||
5fc3aeeb | 4358 | static int gfx_v7_0_sw_init(void *handle) |
a2e73f56 AD |
4359 | { |
4360 | struct amdgpu_ring *ring; | |
5fc3aeeb | 4361 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
4362 | int i, r; |
4363 | ||
4364 | /* EOP Event */ | |
4365 | r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); | |
4366 | if (r) | |
4367 | return r; | |
4368 | ||
4369 | /* Privileged reg */ | |
4370 | r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); | |
4371 | if (r) | |
4372 | return r; | |
4373 | ||
4374 | /* Privileged inst */ | |
4375 | r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); | |
4376 | if (r) | |
4377 | return r; | |
4378 | ||
4379 | gfx_v7_0_scratch_init(adev); | |
4380 | ||
4381 | r = gfx_v7_0_init_microcode(adev); | |
4382 | if (r) { | |
4383 | DRM_ERROR("Failed to load gfx firmware!\n"); | |
4384 | return r; | |
4385 | } | |
4386 | ||
4387 | r = gfx_v7_0_rlc_init(adev); | |
4388 | if (r) { | |
4389 | DRM_ERROR("Failed to init rlc BOs!\n"); | |
4390 | return r; | |
4391 | } | |
4392 | ||
4393 | /* allocate mec buffers */ | |
4394 | r = gfx_v7_0_mec_init(adev); | |
4395 | if (r) { | |
4396 | DRM_ERROR("Failed to init MEC BOs!\n"); | |
4397 | return r; | |
4398 | } | |
4399 | ||
a2e73f56 AD |
4400 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) { |
4401 | ring = &adev->gfx.gfx_ring[i]; | |
4402 | ring->ring_obj = NULL; | |
4403 | sprintf(ring->name, "gfx"); | |
4404 | r = amdgpu_ring_init(adev, ring, 1024 * 1024, | |
4405 | PACKET3(PACKET3_NOP, 0x3FFF), 0xf, | |
4406 | &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, | |
4407 | AMDGPU_RING_TYPE_GFX); | |
4408 | if (r) | |
4409 | return r; | |
4410 | } | |
4411 | ||
4412 | /* set up the compute queues */ | |
4413 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { | |
4414 | unsigned irq_type; | |
4415 | ||
4416 | /* max 32 queues per MEC */ | |
4417 | if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { | |
4418 | DRM_ERROR("Too many (%d) compute rings!\n", i); | |
4419 | break; | |
4420 | } | |
4421 | ring = &adev->gfx.compute_ring[i]; | |
4422 | ring->ring_obj = NULL; | |
4423 | ring->use_doorbell = true; | |
4424 | ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; | |
4425 | ring->me = 1; /* first MEC */ | |
4426 | ring->pipe = i / 8; | |
4427 | ring->queue = i % 8; | |
4428 | sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); | |
4429 | irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; | |
4430 | /* type-2 packets are deprecated on MEC, use type-3 instead */ | |
4431 | r = amdgpu_ring_init(adev, ring, 1024 * 1024, | |
4432 | PACKET3(PACKET3_NOP, 0x3FFF), 0xf, | |
4433 | &adev->gfx.eop_irq, irq_type, | |
4434 | AMDGPU_RING_TYPE_COMPUTE); | |
4435 | if (r) | |
4436 | return r; | |
4437 | } | |
4438 | ||
4439 | /* reserve GDS, GWS and OA resource for gfx */ | |
4440 | r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size, | |
4441 | PAGE_SIZE, true, | |
4442 | AMDGPU_GEM_DOMAIN_GDS, 0, | |
72d7668b | 4443 | NULL, NULL, &adev->gds.gds_gfx_bo); |
a2e73f56 AD |
4444 | if (r) |
4445 | return r; | |
4446 | ||
4447 | r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size, | |
4448 | PAGE_SIZE, true, | |
4449 | AMDGPU_GEM_DOMAIN_GWS, 0, | |
72d7668b | 4450 | NULL, NULL, &adev->gds.gws_gfx_bo); |
a2e73f56 AD |
4451 | if (r) |
4452 | return r; | |
4453 | ||
4454 | r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size, | |
4455 | PAGE_SIZE, true, | |
4456 | AMDGPU_GEM_DOMAIN_OA, 0, | |
72d7668b | 4457 | NULL, NULL, &adev->gds.oa_gfx_bo); |
a2e73f56 AD |
4458 | if (r) |
4459 | return r; | |
4460 | ||
d93f3ca7 AD |
4461 | adev->gfx.ce_ram_size = 0x8000; |
4462 | ||
4463 | gfx_v7_0_gpu_early_init(adev); | |
4464 | ||
a2e73f56 AD |
4465 | return r; |
4466 | } | |
4467 | ||
5fc3aeeb | 4468 | static int gfx_v7_0_sw_fini(void *handle) |
a2e73f56 AD |
4469 | { |
4470 | int i; | |
5fc3aeeb | 4471 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
4472 | |
4473 | amdgpu_bo_unref(&adev->gds.oa_gfx_bo); | |
4474 | amdgpu_bo_unref(&adev->gds.gws_gfx_bo); | |
4475 | amdgpu_bo_unref(&adev->gds.gds_gfx_bo); | |
4476 | ||
4477 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) | |
4478 | amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); | |
4479 | for (i = 0; i < adev->gfx.num_compute_rings; i++) | |
4480 | amdgpu_ring_fini(&adev->gfx.compute_ring[i]); | |
4481 | ||
a2e73f56 AD |
4482 | gfx_v7_0_cp_compute_fini(adev); |
4483 | gfx_v7_0_rlc_fini(adev); | |
4484 | gfx_v7_0_mec_fini(adev); | |
4485 | ||
4486 | return 0; | |
4487 | } | |
4488 | ||
5fc3aeeb | 4489 | static int gfx_v7_0_hw_init(void *handle) |
a2e73f56 AD |
4490 | { |
4491 | int r; | |
5fc3aeeb | 4492 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
4493 | |
4494 | gfx_v7_0_gpu_init(adev); | |
4495 | ||
4496 | /* init rlc */ | |
4497 | r = gfx_v7_0_rlc_resume(adev); | |
4498 | if (r) | |
4499 | return r; | |
4500 | ||
4501 | r = gfx_v7_0_cp_resume(adev); | |
4502 | if (r) | |
4503 | return r; | |
4504 | ||
4505 | return r; | |
4506 | } | |
4507 | ||
5fc3aeeb | 4508 | static int gfx_v7_0_hw_fini(void *handle) |
a2e73f56 | 4509 | { |
5fc3aeeb | 4510 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4511 | ||
ef720532 AD |
4512 | amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); |
4513 | amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); | |
a2e73f56 AD |
4514 | gfx_v7_0_cp_enable(adev, false); |
4515 | gfx_v7_0_rlc_stop(adev); | |
4516 | gfx_v7_0_fini_pg(adev); | |
4517 | ||
4518 | return 0; | |
4519 | } | |
4520 | ||
5fc3aeeb | 4521 | static int gfx_v7_0_suspend(void *handle) |
a2e73f56 | 4522 | { |
5fc3aeeb | 4523 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4524 | ||
a2e73f56 AD |
4525 | return gfx_v7_0_hw_fini(adev); |
4526 | } | |
4527 | ||
5fc3aeeb | 4528 | static int gfx_v7_0_resume(void *handle) |
a2e73f56 | 4529 | { |
5fc3aeeb | 4530 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4531 | ||
a2e73f56 AD |
4532 | return gfx_v7_0_hw_init(adev); |
4533 | } | |
4534 | ||
5fc3aeeb | 4535 | static bool gfx_v7_0_is_idle(void *handle) |
a2e73f56 | 4536 | { |
5fc3aeeb | 4537 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4538 | ||
a2e73f56 AD |
4539 | if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) |
4540 | return false; | |
4541 | else | |
4542 | return true; | |
4543 | } | |
4544 | ||
5fc3aeeb | 4545 | static int gfx_v7_0_wait_for_idle(void *handle) |
a2e73f56 AD |
4546 | { |
4547 | unsigned i; | |
4548 | u32 tmp; | |
5fc3aeeb | 4549 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
4550 | |
4551 | for (i = 0; i < adev->usec_timeout; i++) { | |
4552 | /* read MC_STATUS */ | |
4553 | tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; | |
4554 | ||
4555 | if (!tmp) | |
4556 | return 0; | |
4557 | udelay(1); | |
4558 | } | |
4559 | return -ETIMEDOUT; | |
4560 | } | |
4561 | ||
5fc3aeeb | 4562 | static void gfx_v7_0_print_status(void *handle) |
a2e73f56 AD |
4563 | { |
4564 | int i; | |
5fc3aeeb | 4565 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
4566 | |
4567 | dev_info(adev->dev, "GFX 7.x registers\n"); | |
4568 | dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", | |
4569 | RREG32(mmGRBM_STATUS)); | |
4570 | dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", | |
4571 | RREG32(mmGRBM_STATUS2)); | |
4572 | dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", | |
4573 | RREG32(mmGRBM_STATUS_SE0)); | |
4574 | dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", | |
4575 | RREG32(mmGRBM_STATUS_SE1)); | |
4576 | dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", | |
4577 | RREG32(mmGRBM_STATUS_SE2)); | |
4578 | dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", | |
4579 | RREG32(mmGRBM_STATUS_SE3)); | |
4580 | dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); | |
4581 | dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", | |
4582 | RREG32(mmCP_STALLED_STAT1)); | |
4583 | dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", | |
4584 | RREG32(mmCP_STALLED_STAT2)); | |
4585 | dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", | |
4586 | RREG32(mmCP_STALLED_STAT3)); | |
4587 | dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", | |
4588 | RREG32(mmCP_CPF_BUSY_STAT)); | |
4589 | dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", | |
4590 | RREG32(mmCP_CPF_STALLED_STAT1)); | |
4591 | dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); | |
4592 | dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); | |
4593 | dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", | |
4594 | RREG32(mmCP_CPC_STALLED_STAT1)); | |
4595 | dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); | |
4596 | ||
4597 | for (i = 0; i < 32; i++) { | |
4598 | dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", | |
4599 | i, RREG32(mmGB_TILE_MODE0 + (i * 4))); | |
4600 | } | |
4601 | for (i = 0; i < 16; i++) { | |
4602 | dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", | |
4603 | i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); | |
4604 | } | |
4605 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { | |
4606 | dev_info(adev->dev, " se: %d\n", i); | |
4607 | gfx_v7_0_select_se_sh(adev, i, 0xffffffff); | |
4608 | dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", | |
4609 | RREG32(mmPA_SC_RASTER_CONFIG)); | |
4610 | dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", | |
4611 | RREG32(mmPA_SC_RASTER_CONFIG_1)); | |
4612 | } | |
4613 | gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); | |
4614 | ||
4615 | dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", | |
4616 | RREG32(mmGB_ADDR_CONFIG)); | |
4617 | dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", | |
4618 | RREG32(mmHDP_ADDR_CONFIG)); | |
4619 | dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", | |
4620 | RREG32(mmDMIF_ADDR_CALC)); | |
a2e73f56 AD |
4621 | |
4622 | dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", | |
4623 | RREG32(mmCP_MEQ_THRESHOLDS)); | |
4624 | dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", | |
4625 | RREG32(mmSX_DEBUG_1)); | |
4626 | dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", | |
4627 | RREG32(mmTA_CNTL_AUX)); | |
4628 | dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", | |
4629 | RREG32(mmSPI_CONFIG_CNTL)); | |
4630 | dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", | |
4631 | RREG32(mmSQ_CONFIG)); | |
4632 | dev_info(adev->dev, " DB_DEBUG=0x%08X\n", | |
4633 | RREG32(mmDB_DEBUG)); | |
4634 | dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", | |
4635 | RREG32(mmDB_DEBUG2)); | |
4636 | dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", | |
4637 | RREG32(mmDB_DEBUG3)); | |
4638 | dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", | |
4639 | RREG32(mmCB_HW_CONTROL)); | |
4640 | dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", | |
4641 | RREG32(mmSPI_CONFIG_CNTL_1)); | |
4642 | dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", | |
4643 | RREG32(mmPA_SC_FIFO_SIZE)); | |
4644 | dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", | |
4645 | RREG32(mmVGT_NUM_INSTANCES)); | |
4646 | dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", | |
4647 | RREG32(mmCP_PERFMON_CNTL)); | |
4648 | dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", | |
4649 | RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); | |
4650 | dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", | |
4651 | RREG32(mmVGT_CACHE_INVALIDATION)); | |
4652 | dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", | |
4653 | RREG32(mmVGT_GS_VERTEX_REUSE)); | |
4654 | dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", | |
4655 | RREG32(mmPA_SC_LINE_STIPPLE_STATE)); | |
4656 | dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", | |
4657 | RREG32(mmPA_CL_ENHANCE)); | |
4658 | dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", | |
4659 | RREG32(mmPA_SC_ENHANCE)); | |
4660 | ||
4661 | dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", | |
4662 | RREG32(mmCP_ME_CNTL)); | |
4663 | dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", | |
4664 | RREG32(mmCP_MAX_CONTEXT)); | |
4665 | dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", | |
4666 | RREG32(mmCP_ENDIAN_SWAP)); | |
4667 | dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", | |
4668 | RREG32(mmCP_DEVICE_ID)); | |
4669 | ||
4670 | dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", | |
4671 | RREG32(mmCP_SEM_WAIT_TIMER)); | |
4672 | if (adev->asic_type != CHIP_HAWAII) | |
4673 | dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", | |
4674 | RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL)); | |
4675 | ||
4676 | dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", | |
4677 | RREG32(mmCP_RB_WPTR_DELAY)); | |
4678 | dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", | |
4679 | RREG32(mmCP_RB_VMID)); | |
4680 | dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", | |
4681 | RREG32(mmCP_RB0_CNTL)); | |
4682 | dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", | |
4683 | RREG32(mmCP_RB0_WPTR)); | |
4684 | dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", | |
4685 | RREG32(mmCP_RB0_RPTR_ADDR)); | |
4686 | dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", | |
4687 | RREG32(mmCP_RB0_RPTR_ADDR_HI)); | |
4688 | dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", | |
4689 | RREG32(mmCP_RB0_CNTL)); | |
4690 | dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", | |
4691 | RREG32(mmCP_RB0_BASE)); | |
4692 | dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", | |
4693 | RREG32(mmCP_RB0_BASE_HI)); | |
4694 | dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", | |
4695 | RREG32(mmCP_MEC_CNTL)); | |
4696 | dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", | |
4697 | RREG32(mmCP_CPF_DEBUG)); | |
4698 | ||
4699 | dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", | |
4700 | RREG32(mmSCRATCH_ADDR)); | |
4701 | dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", | |
4702 | RREG32(mmSCRATCH_UMSK)); | |
4703 | ||
4704 | /* init the pipes */ | |
4705 | mutex_lock(&adev->srbm_mutex); | |
4706 | for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { | |
4707 | int me = (i < 4) ? 1 : 2; | |
4708 | int pipe = (i < 4) ? i : (i - 4); | |
4709 | int queue; | |
4710 | ||
4711 | dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe); | |
4712 | cik_srbm_select(adev, me, pipe, 0, 0); | |
4713 | dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n", | |
4714 | RREG32(mmCP_HPD_EOP_BASE_ADDR)); | |
4715 | dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n", | |
4716 | RREG32(mmCP_HPD_EOP_BASE_ADDR_HI)); | |
4717 | dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n", | |
4718 | RREG32(mmCP_HPD_EOP_VMID)); | |
4719 | dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n", | |
4720 | RREG32(mmCP_HPD_EOP_CONTROL)); | |
4721 | ||
0fd64291 | 4722 | for (queue = 0; queue < 8; queue++) { |
a2e73f56 AD |
4723 | cik_srbm_select(adev, me, pipe, queue, 0); |
4724 | dev_info(adev->dev, " queue: %d\n", queue); | |
4725 | dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n", | |
4726 | RREG32(mmCP_PQ_WPTR_POLL_CNTL)); | |
4727 | dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", | |
4728 | RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); | |
4729 | dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n", | |
4730 | RREG32(mmCP_HQD_ACTIVE)); | |
4731 | dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n", | |
4732 | RREG32(mmCP_HQD_DEQUEUE_REQUEST)); | |
4733 | dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n", | |
4734 | RREG32(mmCP_HQD_PQ_RPTR)); | |
4735 | dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", | |
4736 | RREG32(mmCP_HQD_PQ_WPTR)); | |
4737 | dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n", | |
4738 | RREG32(mmCP_HQD_PQ_BASE)); | |
4739 | dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n", | |
4740 | RREG32(mmCP_HQD_PQ_BASE_HI)); | |
4741 | dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n", | |
4742 | RREG32(mmCP_HQD_PQ_CONTROL)); | |
4743 | dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n", | |
4744 | RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR)); | |
4745 | dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n", | |
4746 | RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)); | |
4747 | dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n", | |
4748 | RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR)); | |
4749 | dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n", | |
4750 | RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)); | |
4751 | dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", | |
4752 | RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); | |
4753 | dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", | |
4754 | RREG32(mmCP_HQD_PQ_WPTR)); | |
4755 | dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n", | |
4756 | RREG32(mmCP_HQD_VMID)); | |
4757 | dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n", | |
4758 | RREG32(mmCP_MQD_BASE_ADDR)); | |
4759 | dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n", | |
4760 | RREG32(mmCP_MQD_BASE_ADDR_HI)); | |
4761 | dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n", | |
4762 | RREG32(mmCP_MQD_CONTROL)); | |
4763 | } | |
4764 | } | |
4765 | cik_srbm_select(adev, 0, 0, 0, 0); | |
4766 | mutex_unlock(&adev->srbm_mutex); | |
4767 | ||
4768 | dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", | |
4769 | RREG32(mmCP_INT_CNTL_RING0)); | |
4770 | dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", | |
4771 | RREG32(mmRLC_LB_CNTL)); | |
4772 | dev_info(adev->dev, " RLC_CNTL=0x%08X\n", | |
4773 | RREG32(mmRLC_CNTL)); | |
4774 | dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", | |
4775 | RREG32(mmRLC_CGCG_CGLS_CTRL)); | |
4776 | dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", | |
4777 | RREG32(mmRLC_LB_CNTR_INIT)); | |
4778 | dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", | |
4779 | RREG32(mmRLC_LB_CNTR_MAX)); | |
4780 | dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", | |
4781 | RREG32(mmRLC_LB_INIT_CU_MASK)); | |
4782 | dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", | |
4783 | RREG32(mmRLC_LB_PARAMS)); | |
4784 | dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", | |
4785 | RREG32(mmRLC_LB_CNTL)); | |
4786 | dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", | |
4787 | RREG32(mmRLC_MC_CNTL)); | |
4788 | dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", | |
4789 | RREG32(mmRLC_UCODE_CNTL)); | |
4790 | ||
4791 | if (adev->asic_type == CHIP_BONAIRE) | |
4792 | dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n", | |
4793 | RREG32(mmRLC_DRIVER_CPDMA_STATUS)); | |
4794 | ||
4795 | mutex_lock(&adev->srbm_mutex); | |
4796 | for (i = 0; i < 16; i++) { | |
4797 | cik_srbm_select(adev, 0, 0, 0, i); | |
4798 | dev_info(adev->dev, " VM %d:\n", i); | |
4799 | dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", | |
4800 | RREG32(mmSH_MEM_CONFIG)); | |
4801 | dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", | |
4802 | RREG32(mmSH_MEM_APE1_BASE)); | |
4803 | dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", | |
4804 | RREG32(mmSH_MEM_APE1_LIMIT)); | |
4805 | dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", | |
4806 | RREG32(mmSH_MEM_BASES)); | |
4807 | } | |
4808 | cik_srbm_select(adev, 0, 0, 0, 0); | |
4809 | mutex_unlock(&adev->srbm_mutex); | |
4810 | } | |
4811 | ||
5fc3aeeb | 4812 | static int gfx_v7_0_soft_reset(void *handle) |
a2e73f56 AD |
4813 | { |
4814 | u32 grbm_soft_reset = 0, srbm_soft_reset = 0; | |
4815 | u32 tmp; | |
5fc3aeeb | 4816 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 AD |
4817 | |
4818 | /* GRBM_STATUS */ | |
4819 | tmp = RREG32(mmGRBM_STATUS); | |
4820 | if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | | |
4821 | GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | | |
4822 | GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | | |
4823 | GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | | |
4824 | GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | | |
4825 | GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) | |
4826 | grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | | |
4827 | GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; | |
4828 | ||
4829 | if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { | |
4830 | grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; | |
4831 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; | |
4832 | } | |
4833 | ||
4834 | /* GRBM_STATUS2 */ | |
4835 | tmp = RREG32(mmGRBM_STATUS2); | |
4836 | if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) | |
4837 | grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; | |
4838 | ||
4839 | /* SRBM_STATUS */ | |
4840 | tmp = RREG32(mmSRBM_STATUS); | |
4841 | if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) | |
4842 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; | |
4843 | ||
4844 | if (grbm_soft_reset || srbm_soft_reset) { | |
5fc3aeeb | 4845 | gfx_v7_0_print_status((void *)adev); |
a2e73f56 AD |
4846 | /* disable CG/PG */ |
4847 | gfx_v7_0_fini_pg(adev); | |
4848 | gfx_v7_0_update_cg(adev, false); | |
4849 | ||
4850 | /* stop the rlc */ | |
4851 | gfx_v7_0_rlc_stop(adev); | |
4852 | ||
4853 | /* Disable GFX parsing/prefetching */ | |
4854 | WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); | |
4855 | ||
4856 | /* Disable MEC parsing/prefetching */ | |
4857 | WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); | |
4858 | ||
4859 | if (grbm_soft_reset) { | |
4860 | tmp = RREG32(mmGRBM_SOFT_RESET); | |
4861 | tmp |= grbm_soft_reset; | |
4862 | dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); | |
4863 | WREG32(mmGRBM_SOFT_RESET, tmp); | |
4864 | tmp = RREG32(mmGRBM_SOFT_RESET); | |
4865 | ||
4866 | udelay(50); | |
4867 | ||
4868 | tmp &= ~grbm_soft_reset; | |
4869 | WREG32(mmGRBM_SOFT_RESET, tmp); | |
4870 | tmp = RREG32(mmGRBM_SOFT_RESET); | |
4871 | } | |
4872 | ||
4873 | if (srbm_soft_reset) { | |
4874 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
4875 | tmp |= srbm_soft_reset; | |
4876 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
4877 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
4878 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
4879 | ||
4880 | udelay(50); | |
4881 | ||
4882 | tmp &= ~srbm_soft_reset; | |
4883 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
4884 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
4885 | } | |
4886 | /* Wait a little for things to settle down */ | |
4887 | udelay(50); | |
5fc3aeeb | 4888 | gfx_v7_0_print_status((void *)adev); |
a2e73f56 AD |
4889 | } |
4890 | return 0; | |
4891 | } | |
4892 | ||
4893 | static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, | |
4894 | enum amdgpu_interrupt_state state) | |
4895 | { | |
4896 | u32 cp_int_cntl; | |
4897 | ||
4898 | switch (state) { | |
4899 | case AMDGPU_IRQ_STATE_DISABLE: | |
4900 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); | |
4901 | cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; | |
4902 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); | |
4903 | break; | |
4904 | case AMDGPU_IRQ_STATE_ENABLE: | |
4905 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); | |
4906 | cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; | |
4907 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); | |
4908 | break; | |
4909 | default: | |
4910 | break; | |
4911 | } | |
4912 | } | |
4913 | ||
4914 | static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, | |
4915 | int me, int pipe, | |
4916 | enum amdgpu_interrupt_state state) | |
4917 | { | |
4918 | u32 mec_int_cntl, mec_int_cntl_reg; | |
4919 | ||
4920 | /* | |
4921 | * amdgpu controls only pipe 0 of MEC1. That's why this function only | |
4922 | * handles the setting of interrupts for this specific pipe. All other | |
4923 | * pipes' interrupts are set by amdkfd. | |
4924 | */ | |
4925 | ||
4926 | if (me == 1) { | |
4927 | switch (pipe) { | |
4928 | case 0: | |
4929 | mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; | |
4930 | break; | |
4931 | default: | |
4932 | DRM_DEBUG("invalid pipe %d\n", pipe); | |
4933 | return; | |
4934 | } | |
4935 | } else { | |
4936 | DRM_DEBUG("invalid me %d\n", me); | |
4937 | return; | |
4938 | } | |
4939 | ||
4940 | switch (state) { | |
4941 | case AMDGPU_IRQ_STATE_DISABLE: | |
4942 | mec_int_cntl = RREG32(mec_int_cntl_reg); | |
4943 | mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; | |
4944 | WREG32(mec_int_cntl_reg, mec_int_cntl); | |
4945 | break; | |
4946 | case AMDGPU_IRQ_STATE_ENABLE: | |
4947 | mec_int_cntl = RREG32(mec_int_cntl_reg); | |
4948 | mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; | |
4949 | WREG32(mec_int_cntl_reg, mec_int_cntl); | |
4950 | break; | |
4951 | default: | |
4952 | break; | |
4953 | } | |
4954 | } | |
4955 | ||
4956 | static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, | |
4957 | struct amdgpu_irq_src *src, | |
4958 | unsigned type, | |
4959 | enum amdgpu_interrupt_state state) | |
4960 | { | |
4961 | u32 cp_int_cntl; | |
4962 | ||
4963 | switch (state) { | |
4964 | case AMDGPU_IRQ_STATE_DISABLE: | |
4965 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); | |
4966 | cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; | |
4967 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); | |
4968 | break; | |
4969 | case AMDGPU_IRQ_STATE_ENABLE: | |
4970 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); | |
4971 | cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; | |
4972 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); | |
4973 | break; | |
4974 | default: | |
4975 | break; | |
4976 | } | |
4977 | ||
4978 | return 0; | |
4979 | } | |
4980 | ||
4981 | static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, | |
4982 | struct amdgpu_irq_src *src, | |
4983 | unsigned type, | |
4984 | enum amdgpu_interrupt_state state) | |
4985 | { | |
4986 | u32 cp_int_cntl; | |
4987 | ||
4988 | switch (state) { | |
4989 | case AMDGPU_IRQ_STATE_DISABLE: | |
4990 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); | |
4991 | cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; | |
4992 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); | |
4993 | break; | |
4994 | case AMDGPU_IRQ_STATE_ENABLE: | |
4995 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); | |
4996 | cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; | |
4997 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); | |
4998 | break; | |
4999 | default: | |
5000 | break; | |
5001 | } | |
5002 | ||
5003 | return 0; | |
5004 | } | |
5005 | ||
5006 | static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, | |
5007 | struct amdgpu_irq_src *src, | |
5008 | unsigned type, | |
5009 | enum amdgpu_interrupt_state state) | |
5010 | { | |
5011 | switch (type) { | |
5012 | case AMDGPU_CP_IRQ_GFX_EOP: | |
5013 | gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); | |
5014 | break; | |
5015 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: | |
5016 | gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); | |
5017 | break; | |
5018 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: | |
5019 | gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); | |
5020 | break; | |
5021 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: | |
5022 | gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); | |
5023 | break; | |
5024 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: | |
5025 | gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); | |
5026 | break; | |
5027 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: | |
5028 | gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); | |
5029 | break; | |
5030 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: | |
5031 | gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); | |
5032 | break; | |
5033 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: | |
5034 | gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); | |
5035 | break; | |
5036 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: | |
5037 | gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); | |
5038 | break; | |
5039 | default: | |
5040 | break; | |
5041 | } | |
5042 | return 0; | |
5043 | } | |
5044 | ||
5045 | static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, | |
5046 | struct amdgpu_irq_src *source, | |
5047 | struct amdgpu_iv_entry *entry) | |
5048 | { | |
5049 | u8 me_id, pipe_id; | |
5050 | struct amdgpu_ring *ring; | |
5051 | int i; | |
5052 | ||
5053 | DRM_DEBUG("IH: CP EOP\n"); | |
5054 | me_id = (entry->ring_id & 0x0c) >> 2; | |
5055 | pipe_id = (entry->ring_id & 0x03) >> 0; | |
5056 | switch (me_id) { | |
5057 | case 0: | |
5058 | amdgpu_fence_process(&adev->gfx.gfx_ring[0]); | |
5059 | break; | |
5060 | case 1: | |
5061 | case 2: | |
5062 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { | |
5063 | ring = &adev->gfx.compute_ring[i]; | |
5064 | if ((ring->me == me_id) & (ring->pipe == pipe_id)) | |
5065 | amdgpu_fence_process(ring); | |
5066 | } | |
5067 | break; | |
5068 | } | |
5069 | return 0; | |
5070 | } | |
5071 | ||
5072 | static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, | |
5073 | struct amdgpu_irq_src *source, | |
5074 | struct amdgpu_iv_entry *entry) | |
5075 | { | |
5076 | DRM_ERROR("Illegal register access in command stream\n"); | |
5077 | schedule_work(&adev->reset_work); | |
5078 | return 0; | |
5079 | } | |
5080 | ||
5081 | static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, | |
5082 | struct amdgpu_irq_src *source, | |
5083 | struct amdgpu_iv_entry *entry) | |
5084 | { | |
5085 | DRM_ERROR("Illegal instruction in command stream\n"); | |
5086 | // XXX soft reset the gfx block only | |
5087 | schedule_work(&adev->reset_work); | |
5088 | return 0; | |
5089 | } | |
5090 | ||
5fc3aeeb | 5091 | static int gfx_v7_0_set_clockgating_state(void *handle, |
5092 | enum amd_clockgating_state state) | |
a2e73f56 AD |
5093 | { |
5094 | bool gate = false; | |
5fc3aeeb | 5095 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 | 5096 | |
5fc3aeeb | 5097 | if (state == AMD_CG_STATE_GATE) |
a2e73f56 AD |
5098 | gate = true; |
5099 | ||
5100 | gfx_v7_0_enable_gui_idle_interrupt(adev, false); | |
5101 | /* order matters! */ | |
5102 | if (gate) { | |
5103 | gfx_v7_0_enable_mgcg(adev, true); | |
5104 | gfx_v7_0_enable_cgcg(adev, true); | |
5105 | } else { | |
5106 | gfx_v7_0_enable_cgcg(adev, false); | |
5107 | gfx_v7_0_enable_mgcg(adev, false); | |
5108 | } | |
5109 | gfx_v7_0_enable_gui_idle_interrupt(adev, true); | |
5110 | ||
5111 | return 0; | |
5112 | } | |
5113 | ||
5fc3aeeb | 5114 | static int gfx_v7_0_set_powergating_state(void *handle, |
5115 | enum amd_powergating_state state) | |
a2e73f56 AD |
5116 | { |
5117 | bool gate = false; | |
5fc3aeeb | 5118 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a2e73f56 | 5119 | |
5fc3aeeb | 5120 | if (state == AMD_PG_STATE_GATE) |
a2e73f56 AD |
5121 | gate = true; |
5122 | ||
5123 | if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | | |
5124 | AMDGPU_PG_SUPPORT_GFX_SMG | | |
5125 | AMDGPU_PG_SUPPORT_GFX_DMG | | |
5126 | AMDGPU_PG_SUPPORT_CP | | |
5127 | AMDGPU_PG_SUPPORT_GDS | | |
5128 | AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { | |
5129 | gfx_v7_0_update_gfx_pg(adev, gate); | |
5130 | if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { | |
5131 | gfx_v7_0_enable_cp_pg(adev, gate); | |
5132 | gfx_v7_0_enable_gds_pg(adev, gate); | |
5133 | } | |
5134 | } | |
5135 | ||
5136 | return 0; | |
5137 | } | |
5138 | ||
5fc3aeeb | 5139 | const struct amd_ip_funcs gfx_v7_0_ip_funcs = { |
a2e73f56 | 5140 | .early_init = gfx_v7_0_early_init, |
ef720532 | 5141 | .late_init = gfx_v7_0_late_init, |
a2e73f56 AD |
5142 | .sw_init = gfx_v7_0_sw_init, |
5143 | .sw_fini = gfx_v7_0_sw_fini, | |
5144 | .hw_init = gfx_v7_0_hw_init, | |
5145 | .hw_fini = gfx_v7_0_hw_fini, | |
5146 | .suspend = gfx_v7_0_suspend, | |
5147 | .resume = gfx_v7_0_resume, | |
5148 | .is_idle = gfx_v7_0_is_idle, | |
5149 | .wait_for_idle = gfx_v7_0_wait_for_idle, | |
5150 | .soft_reset = gfx_v7_0_soft_reset, | |
5151 | .print_status = gfx_v7_0_print_status, | |
5152 | .set_clockgating_state = gfx_v7_0_set_clockgating_state, | |
5153 | .set_powergating_state = gfx_v7_0_set_powergating_state, | |
5154 | }; | |
5155 | ||
a2e73f56 AD |
5156 | static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { |
5157 | .get_rptr = gfx_v7_0_ring_get_rptr_gfx, | |
5158 | .get_wptr = gfx_v7_0_ring_get_wptr_gfx, | |
5159 | .set_wptr = gfx_v7_0_ring_set_wptr_gfx, | |
5160 | .parse_cs = NULL, | |
93323131 | 5161 | .emit_ib = gfx_v7_0_ring_emit_ib_gfx, |
a2e73f56 | 5162 | .emit_fence = gfx_v7_0_ring_emit_fence_gfx, |
b8c7b39e | 5163 | .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, |
a2e73f56 AD |
5164 | .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, |
5165 | .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, | |
d2edb07b | 5166 | .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, |
0955860b | 5167 | .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, |
a2e73f56 AD |
5168 | .test_ring = gfx_v7_0_ring_test_ring, |
5169 | .test_ib = gfx_v7_0_ring_test_ib, | |
edff0e28 | 5170 | .insert_nop = amdgpu_ring_insert_nop, |
9e5d5309 | 5171 | .pad_ib = amdgpu_ring_generic_pad_ib, |
a2e73f56 AD |
5172 | }; |
5173 | ||
5174 | static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { | |
5175 | .get_rptr = gfx_v7_0_ring_get_rptr_compute, | |
5176 | .get_wptr = gfx_v7_0_ring_get_wptr_compute, | |
5177 | .set_wptr = gfx_v7_0_ring_set_wptr_compute, | |
5178 | .parse_cs = NULL, | |
93323131 | 5179 | .emit_ib = gfx_v7_0_ring_emit_ib_compute, |
a2e73f56 | 5180 | .emit_fence = gfx_v7_0_ring_emit_fence_compute, |
b8c7b39e | 5181 | .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, |
a2e73f56 AD |
5182 | .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, |
5183 | .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, | |
d9b5327a | 5184 | .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, |
0955860b | 5185 | .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, |
a2e73f56 AD |
5186 | .test_ring = gfx_v7_0_ring_test_ring, |
5187 | .test_ib = gfx_v7_0_ring_test_ib, | |
edff0e28 | 5188 | .insert_nop = amdgpu_ring_insert_nop, |
9e5d5309 | 5189 | .pad_ib = amdgpu_ring_generic_pad_ib, |
a2e73f56 AD |
5190 | }; |
5191 | ||
5192 | static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) | |
5193 | { | |
5194 | int i; | |
5195 | ||
5196 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) | |
5197 | adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; | |
5198 | for (i = 0; i < adev->gfx.num_compute_rings; i++) | |
5199 | adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; | |
5200 | } | |
5201 | ||
5202 | static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { | |
5203 | .set = gfx_v7_0_set_eop_interrupt_state, | |
5204 | .process = gfx_v7_0_eop_irq, | |
5205 | }; | |
5206 | ||
5207 | static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { | |
5208 | .set = gfx_v7_0_set_priv_reg_fault_state, | |
5209 | .process = gfx_v7_0_priv_reg_irq, | |
5210 | }; | |
5211 | ||
5212 | static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { | |
5213 | .set = gfx_v7_0_set_priv_inst_fault_state, | |
5214 | .process = gfx_v7_0_priv_inst_irq, | |
5215 | }; | |
5216 | ||
5217 | static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) | |
5218 | { | |
5219 | adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; | |
5220 | adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; | |
5221 | ||
5222 | adev->gfx.priv_reg_irq.num_types = 1; | |
5223 | adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; | |
5224 | ||
5225 | adev->gfx.priv_inst_irq.num_types = 1; | |
5226 | adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; | |
5227 | } | |
5228 | ||
5229 | static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) | |
5230 | { | |
5231 | /* init asci gds info */ | |
5232 | adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); | |
5233 | adev->gds.gws.total_size = 64; | |
5234 | adev->gds.oa.total_size = 16; | |
5235 | ||
5236 | if (adev->gds.mem.total_size == 64 * 1024) { | |
5237 | adev->gds.mem.gfx_partition_size = 4096; | |
5238 | adev->gds.mem.cs_partition_size = 4096; | |
5239 | ||
5240 | adev->gds.gws.gfx_partition_size = 4; | |
5241 | adev->gds.gws.cs_partition_size = 4; | |
5242 | ||
5243 | adev->gds.oa.gfx_partition_size = 4; | |
5244 | adev->gds.oa.cs_partition_size = 1; | |
5245 | } else { | |
5246 | adev->gds.mem.gfx_partition_size = 1024; | |
5247 | adev->gds.mem.cs_partition_size = 1024; | |
5248 | ||
5249 | adev->gds.gws.gfx_partition_size = 16; | |
5250 | adev->gds.gws.cs_partition_size = 16; | |
5251 | ||
5252 | adev->gds.oa.gfx_partition_size = 4; | |
5253 | adev->gds.oa.cs_partition_size = 4; | |
5254 | } | |
5255 | } | |
5256 | ||
5257 | ||
5258 | int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, | |
5cb60bf6 | 5259 | struct amdgpu_cu_info *cu_info) |
a2e73f56 AD |
5260 | { |
5261 | int i, j, k, counter, active_cu_number = 0; | |
5262 | u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; | |
5263 | ||
5264 | if (!adev || !cu_info) | |
5265 | return -EINVAL; | |
5266 | ||
6157bd7a FC |
5267 | memset(cu_info, 0, sizeof(*cu_info)); |
5268 | ||
a2e73f56 AD |
5269 | mutex_lock(&adev->grbm_idx_mutex); |
5270 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { | |
5271 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { | |
5272 | mask = 1; | |
5273 | ao_bitmap = 0; | |
5274 | counter = 0; | |
8f8e00c1 AD |
5275 | gfx_v7_0_select_se_sh(adev, i, j); |
5276 | bitmap = gfx_v7_0_get_cu_active_bitmap(adev); | |
a2e73f56 AD |
5277 | cu_info->bitmap[i][j] = bitmap; |
5278 | ||
8f8e00c1 | 5279 | for (k = 0; k < 16; k ++) { |
a2e73f56 AD |
5280 | if (bitmap & mask) { |
5281 | if (counter < 2) | |
5282 | ao_bitmap |= mask; | |
5283 | counter ++; | |
5284 | } | |
5285 | mask <<= 1; | |
5286 | } | |
5287 | active_cu_number += counter; | |
5288 | ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); | |
5289 | } | |
5290 | } | |
8f8e00c1 AD |
5291 | gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); |
5292 | mutex_unlock(&adev->grbm_idx_mutex); | |
a2e73f56 AD |
5293 | |
5294 | cu_info->number = active_cu_number; | |
5295 | cu_info->ao_cu_mask = ao_cu_mask; | |
8f8e00c1 | 5296 | |
a2e73f56 AD |
5297 | return 0; |
5298 | } |