]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm: Use pr_cont where appropriate
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_ih.h"
27#include "amdgpu_gfx.h"
28#include "cikd.h"
29#include "cik.h"
30#include "atom.h"
31#include "amdgpu_ucode.h"
32#include "clearstate_ci.h"
33
a2e73f56
AD		 34#include "dce/dce_8_0_d.h"
35#include "dce/dce_8_0_sh_mask.h"
36
37#include "bif/bif_4_1_d.h"
38#include "bif/bif_4_1_sh_mask.h"
39
40#include "gca/gfx_7_0_d.h"
41#include "gca/gfx_7_2_enum.h"
42#include "gca/gfx_7_2_sh_mask.h"
43
44#include "gmc/gmc_7_0_d.h"
45#include "gmc/gmc_7_0_sh_mask.h"
46
47#include "oss/oss_2_0_d.h"
48#include "oss/oss_2_0_sh_mask.h"
49
50#define GFX7_NUM_GFX_RINGS 1
51#define GFX7_NUM_COMPUTE_RINGS 8
52
53static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
a2e73f56
AD		 56
57MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
58MODULE_FIRMWARE("radeon/bonaire_me.bin");
59MODULE_FIRMWARE("radeon/bonaire_ce.bin");
60MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
61MODULE_FIRMWARE("radeon/bonaire_mec.bin");
62
63MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
64MODULE_FIRMWARE("radeon/hawaii_me.bin");
65MODULE_FIRMWARE("radeon/hawaii_ce.bin");
66MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
67MODULE_FIRMWARE("radeon/hawaii_mec.bin");
68
69MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
70MODULE_FIRMWARE("radeon/kaveri_me.bin");
71MODULE_FIRMWARE("radeon/kaveri_ce.bin");
72MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
73MODULE_FIRMWARE("radeon/kaveri_mec.bin");
74MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
75
76MODULE_FIRMWARE("radeon/kabini_pfp.bin");
77MODULE_FIRMWARE("radeon/kabini_me.bin");
78MODULE_FIRMWARE("radeon/kabini_ce.bin");
79MODULE_FIRMWARE("radeon/kabini_rlc.bin");
80MODULE_FIRMWARE("radeon/kabini_mec.bin");
81
82MODULE_FIRMWARE("radeon/mullins_pfp.bin");
83MODULE_FIRMWARE("radeon/mullins_me.bin");
84MODULE_FIRMWARE("radeon/mullins_ce.bin");
85MODULE_FIRMWARE("radeon/mullins_rlc.bin");
86MODULE_FIRMWARE("radeon/mullins_mec.bin");
87
88static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
89{
90 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
91 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
92 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
93 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
94 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
95 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
96 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
97 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
98 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
99 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
100 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
101 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
102 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
103 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
104 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
105 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
106};
107
108static const u32 spectre_rlc_save_restore_register_list[] =
109{
110 (0x0e00 << 16) | (0xc12c >> 2),
111 0x00000000,
112 (0x0e00 << 16) | (0xc140 >> 2),
113 0x00000000,
114 (0x0e00 << 16) | (0xc150 >> 2),
115 0x00000000,
116 (0x0e00 << 16) | (0xc15c >> 2),
117 0x00000000,
118 (0x0e00 << 16) | (0xc168 >> 2),
119 0x00000000,
120 (0x0e00 << 16) | (0xc170 >> 2),
121 0x00000000,
122 (0x0e00 << 16) | (0xc178 >> 2),
123 0x00000000,
124 (0x0e00 << 16) | (0xc204 >> 2),
125 0x00000000,
126 (0x0e00 << 16) | (0xc2b4 >> 2),
127 0x00000000,
128 (0x0e00 << 16) | (0xc2b8 >> 2),
129 0x00000000,
130 (0x0e00 << 16) | (0xc2bc >> 2),
131 0x00000000,
132 (0x0e00 << 16) | (0xc2c0 >> 2),
133 0x00000000,
134 (0x0e00 << 16) | (0x8228 >> 2),
135 0x00000000,
136 (0x0e00 << 16) | (0x829c >> 2),
137 0x00000000,
138 (0x0e00 << 16) | (0x869c >> 2),
139 0x00000000,
140 (0x0600 << 16) | (0x98f4 >> 2),
141 0x00000000,
142 (0x0e00 << 16) | (0x98f8 >> 2),
143 0x00000000,
144 (0x0e00 << 16) | (0x9900 >> 2),
145 0x00000000,
146 (0x0e00 << 16) | (0xc260 >> 2),
147 0x00000000,
148 (0x0e00 << 16) | (0x90e8 >> 2),
149 0x00000000,
150 (0x0e00 << 16) | (0x3c000 >> 2),
151 0x00000000,
152 (0x0e00 << 16) | (0x3c00c >> 2),
153 0x00000000,
154 (0x0e00 << 16) | (0x8c1c >> 2),
155 0x00000000,
156 (0x0e00 << 16) | (0x9700 >> 2),
157 0x00000000,
158 (0x0e00 << 16) | (0xcd20 >> 2),
159 0x00000000,
160 (0x4e00 << 16) | (0xcd20 >> 2),
161 0x00000000,
162 (0x5e00 << 16) | (0xcd20 >> 2),
163 0x00000000,
164 (0x6e00 << 16) | (0xcd20 >> 2),
165 0x00000000,
166 (0x7e00 << 16) | (0xcd20 >> 2),
167 0x00000000,
168 (0x8e00 << 16) | (0xcd20 >> 2),
169 0x00000000,
170 (0x9e00 << 16) | (0xcd20 >> 2),
171 0x00000000,
172 (0xae00 << 16) | (0xcd20 >> 2),
173 0x00000000,
174 (0xbe00 << 16) | (0xcd20 >> 2),
175 0x00000000,
176 (0x0e00 << 16) | (0x89bc >> 2),
177 0x00000000,
178 (0x0e00 << 16) | (0x8900 >> 2),
179 0x00000000,
180 0x3,
181 (0x0e00 << 16) | (0xc130 >> 2),
182 0x00000000,
183 (0x0e00 << 16) | (0xc134 >> 2),
184 0x00000000,
185 (0x0e00 << 16) | (0xc1fc >> 2),
186 0x00000000,
187 (0x0e00 << 16) | (0xc208 >> 2),
188 0x00000000,
189 (0x0e00 << 16) | (0xc264 >> 2),
190 0x00000000,
191 (0x0e00 << 16) | (0xc268 >> 2),
192 0x00000000,
193 (0x0e00 << 16) | (0xc26c >> 2),
194 0x00000000,
195 (0x0e00 << 16) | (0xc270 >> 2),
196 0x00000000,
197 (0x0e00 << 16) | (0xc274 >> 2),
198 0x00000000,
199 (0x0e00 << 16) | (0xc278 >> 2),
200 0x00000000,
201 (0x0e00 << 16) | (0xc27c >> 2),
202 0x00000000,
203 (0x0e00 << 16) | (0xc280 >> 2),
204 0x00000000,
205 (0x0e00 << 16) | (0xc284 >> 2),
206 0x00000000,
207 (0x0e00 << 16) | (0xc288 >> 2),
208 0x00000000,
209 (0x0e00 << 16) | (0xc28c >> 2),
210 0x00000000,
211 (0x0e00 << 16) | (0xc290 >> 2),
212 0x00000000,
213 (0x0e00 << 16) | (0xc294 >> 2),
214 0x00000000,
215 (0x0e00 << 16) | (0xc298 >> 2),
216 0x00000000,
217 (0x0e00 << 16) | (0xc29c >> 2),
218 0x00000000,
219 (0x0e00 << 16) | (0xc2a0 >> 2),
220 0x00000000,
221 (0x0e00 << 16) | (0xc2a4 >> 2),
222 0x00000000,
223 (0x0e00 << 16) | (0xc2a8 >> 2),
224 0x00000000,
225 (0x0e00 << 16) | (0xc2ac >> 2),
226 0x00000000,
227 (0x0e00 << 16) | (0xc2b0 >> 2),
228 0x00000000,
229 (0x0e00 << 16) | (0x301d0 >> 2),
230 0x00000000,
231 (0x0e00 << 16) | (0x30238 >> 2),
232 0x00000000,
233 (0x0e00 << 16) | (0x30250 >> 2),
234 0x00000000,
235 (0x0e00 << 16) | (0x30254 >> 2),
236 0x00000000,
237 (0x0e00 << 16) | (0x30258 >> 2),
238 0x00000000,
239 (0x0e00 << 16) | (0x3025c >> 2),
240 0x00000000,
241 (0x4e00 << 16) | (0xc900 >> 2),
242 0x00000000,
243 (0x5e00 << 16) | (0xc900 >> 2),
244 0x00000000,
245 (0x6e00 << 16) | (0xc900 >> 2),
246 0x00000000,
247 (0x7e00 << 16) | (0xc900 >> 2),
248 0x00000000,
249 (0x8e00 << 16) | (0xc900 >> 2),
250 0x00000000,
251 (0x9e00 << 16) | (0xc900 >> 2),
252 0x00000000,
253 (0xae00 << 16) | (0xc900 >> 2),
254 0x00000000,
255 (0xbe00 << 16) | (0xc900 >> 2),
256 0x00000000,
257 (0x4e00 << 16) | (0xc904 >> 2),
258 0x00000000,
259 (0x5e00 << 16) | (0xc904 >> 2),
260 0x00000000,
261 (0x6e00 << 16) | (0xc904 >> 2),
262 0x00000000,
263 (0x7e00 << 16) | (0xc904 >> 2),
264 0x00000000,
265 (0x8e00 << 16) | (0xc904 >> 2),
266 0x00000000,
267 (0x9e00 << 16) | (0xc904 >> 2),
268 0x00000000,
269 (0xae00 << 16) | (0xc904 >> 2),
270 0x00000000,
271 (0xbe00 << 16) | (0xc904 >> 2),
272 0x00000000,
273 (0x4e00 << 16) | (0xc908 >> 2),
274 0x00000000,
275 (0x5e00 << 16) | (0xc908 >> 2),
276 0x00000000,
277 (0x6e00 << 16) | (0xc908 >> 2),
278 0x00000000,
279 (0x7e00 << 16) | (0xc908 >> 2),
280 0x00000000,
281 (0x8e00 << 16) | (0xc908 >> 2),
282 0x00000000,
283 (0x9e00 << 16) | (0xc908 >> 2),
284 0x00000000,
285 (0xae00 << 16) | (0xc908 >> 2),
286 0x00000000,
287 (0xbe00 << 16) | (0xc908 >> 2),
288 0x00000000,
289 (0x4e00 << 16) | (0xc90c >> 2),
290 0x00000000,
291 (0x5e00 << 16) | (0xc90c >> 2),
292 0x00000000,
293 (0x6e00 << 16) | (0xc90c >> 2),
294 0x00000000,
295 (0x7e00 << 16) | (0xc90c >> 2),
296 0x00000000,
297 (0x8e00 << 16) | (0xc90c >> 2),
298 0x00000000,
299 (0x9e00 << 16) | (0xc90c >> 2),
300 0x00000000,
301 (0xae00 << 16) | (0xc90c >> 2),
302 0x00000000,
303 (0xbe00 << 16) | (0xc90c >> 2),
304 0x00000000,
305 (0x4e00 << 16) | (0xc910 >> 2),
306 0x00000000,
307 (0x5e00 << 16) | (0xc910 >> 2),
308 0x00000000,
309 (0x6e00 << 16) | (0xc910 >> 2),
310 0x00000000,
311 (0x7e00 << 16) | (0xc910 >> 2),
312 0x00000000,
313 (0x8e00 << 16) | (0xc910 >> 2),
314 0x00000000,
315 (0x9e00 << 16) | (0xc910 >> 2),
316 0x00000000,
317 (0xae00 << 16) | (0xc910 >> 2),
318 0x00000000,
319 (0xbe00 << 16) | (0xc910 >> 2),
320 0x00000000,
321 (0x0e00 << 16) | (0xc99c >> 2),
322 0x00000000,
323 (0x0e00 << 16) | (0x9834 >> 2),
324 0x00000000,
325 (0x0000 << 16) | (0x30f00 >> 2),
326 0x00000000,
327 (0x0001 << 16) | (0x30f00 >> 2),
328 0x00000000,
329 (0x0000 << 16) | (0x30f04 >> 2),
330 0x00000000,
331 (0x0001 << 16) | (0x30f04 >> 2),
332 0x00000000,
333 (0x0000 << 16) | (0x30f08 >> 2),
334 0x00000000,
335 (0x0001 << 16) | (0x30f08 >> 2),
336 0x00000000,
337 (0x0000 << 16) | (0x30f0c >> 2),
338 0x00000000,
339 (0x0001 << 16) | (0x30f0c >> 2),
340 0x00000000,
341 (0x0600 << 16) | (0x9b7c >> 2),
342 0x00000000,
343 (0x0e00 << 16) | (0x8a14 >> 2),
344 0x00000000,
345 (0x0e00 << 16) | (0x8a18 >> 2),
346 0x00000000,
347 (0x0600 << 16) | (0x30a00 >> 2),
348 0x00000000,
349 (0x0e00 << 16) | (0x8bf0 >> 2),
350 0x00000000,
351 (0x0e00 << 16) | (0x8bcc >> 2),
352 0x00000000,
353 (0x0e00 << 16) | (0x8b24 >> 2),
354 0x00000000,
355 (0x0e00 << 16) | (0x30a04 >> 2),
356 0x00000000,
357 (0x0600 << 16) | (0x30a10 >> 2),
358 0x00000000,
359 (0x0600 << 16) | (0x30a14 >> 2),
360 0x00000000,
361 (0x0600 << 16) | (0x30a18 >> 2),
362 0x00000000,
363 (0x0600 << 16) | (0x30a2c >> 2),
364 0x00000000,
365 (0x0e00 << 16) | (0xc700 >> 2),
366 0x00000000,
367 (0x0e00 << 16) | (0xc704 >> 2),
368 0x00000000,
369 (0x0e00 << 16) | (0xc708 >> 2),
370 0x00000000,
371 (0x0e00 << 16) | (0xc768 >> 2),
372 0x00000000,
373 (0x0400 << 16) | (0xc770 >> 2),
374 0x00000000,
375 (0x0400 << 16) | (0xc774 >> 2),
376 0x00000000,
377 (0x0400 << 16) | (0xc778 >> 2),
378 0x00000000,
379 (0x0400 << 16) | (0xc77c >> 2),
380 0x00000000,
381 (0x0400 << 16) | (0xc780 >> 2),
382 0x00000000,
383 (0x0400 << 16) | (0xc784 >> 2),
384 0x00000000,
385 (0x0400 << 16) | (0xc788 >> 2),
386 0x00000000,
387 (0x0400 << 16) | (0xc78c >> 2),
388 0x00000000,
389 (0x0400 << 16) | (0xc798 >> 2),
390 0x00000000,
391 (0x0400 << 16) | (0xc79c >> 2),
392 0x00000000,
393 (0x0400 << 16) | (0xc7a0 >> 2),
394 0x00000000,
395 (0x0400 << 16) | (0xc7a4 >> 2),
396 0x00000000,
397 (0x0400 << 16) | (0xc7a8 >> 2),
398 0x00000000,
399 (0x0400 << 16) | (0xc7ac >> 2),
400 0x00000000,
401 (0x0400 << 16) | (0xc7b0 >> 2),
402 0x00000000,
403 (0x0400 << 16) | (0xc7b4 >> 2),
404 0x00000000,
405 (0x0e00 << 16) | (0x9100 >> 2),
406 0x00000000,
407 (0x0e00 << 16) | (0x3c010 >> 2),
408 0x00000000,
409 (0x0e00 << 16) | (0x92a8 >> 2),
410 0x00000000,
411 (0x0e00 << 16) | (0x92ac >> 2),
412 0x00000000,
413 (0x0e00 << 16) | (0x92b4 >> 2),
414 0x00000000,
415 (0x0e00 << 16) | (0x92b8 >> 2),
416 0x00000000,
417 (0x0e00 << 16) | (0x92bc >> 2),
418 0x00000000,
419 (0x0e00 << 16) | (0x92c0 >> 2),
420 0x00000000,
421 (0x0e00 << 16) | (0x92c4 >> 2),
422 0x00000000,
423 (0x0e00 << 16) | (0x92c8 >> 2),
424 0x00000000,
425 (0x0e00 << 16) | (0x92cc >> 2),
426 0x00000000,
427 (0x0e00 << 16) | (0x92d0 >> 2),
428 0x00000000,
429 (0x0e00 << 16) | (0x8c00 >> 2),
430 0x00000000,
431 (0x0e00 << 16) | (0x8c04 >> 2),
432 0x00000000,
433 (0x0e00 << 16) | (0x8c20 >> 2),
434 0x00000000,
435 (0x0e00 << 16) | (0x8c38 >> 2),
436 0x00000000,
437 (0x0e00 << 16) | (0x8c3c >> 2),
438 0x00000000,
439 (0x0e00 << 16) | (0xae00 >> 2),
440 0x00000000,
441 (0x0e00 << 16) | (0x9604 >> 2),
442 0x00000000,
443 (0x0e00 << 16) | (0xac08 >> 2),
444 0x00000000,
445 (0x0e00 << 16) | (0xac0c >> 2),
446 0x00000000,
447 (0x0e00 << 16) | (0xac10 >> 2),
448 0x00000000,
449 (0x0e00 << 16) | (0xac14 >> 2),
450 0x00000000,
451 (0x0e00 << 16) | (0xac58 >> 2),
452 0x00000000,
453 (0x0e00 << 16) | (0xac68 >> 2),
454 0x00000000,
455 (0x0e00 << 16) | (0xac6c >> 2),
456 0x00000000,
457 (0x0e00 << 16) | (0xac70 >> 2),
458 0x00000000,
459 (0x0e00 << 16) | (0xac74 >> 2),
460 0x00000000,
461 (0x0e00 << 16) | (0xac78 >> 2),
462 0x00000000,
463 (0x0e00 << 16) | (0xac7c >> 2),
464 0x00000000,
465 (0x0e00 << 16) | (0xac80 >> 2),
466 0x00000000,
467 (0x0e00 << 16) | (0xac84 >> 2),
468 0x00000000,
469 (0x0e00 << 16) | (0xac88 >> 2),
470 0x00000000,
471 (0x0e00 << 16) | (0xac8c >> 2),
472 0x00000000,
473 (0x0e00 << 16) | (0x970c >> 2),
474 0x00000000,
475 (0x0e00 << 16) | (0x9714 >> 2),
476 0x00000000,
477 (0x0e00 << 16) | (0x9718 >> 2),
478 0x00000000,
479 (0x0e00 << 16) | (0x971c >> 2),
480 0x00000000,
481 (0x0e00 << 16) | (0x31068 >> 2),
482 0x00000000,
483 (0x4e00 << 16) | (0x31068 >> 2),
484 0x00000000,
485 (0x5e00 << 16) | (0x31068 >> 2),
486 0x00000000,
487 (0x6e00 << 16) | (0x31068 >> 2),
488 0x00000000,
489 (0x7e00 << 16) | (0x31068 >> 2),
490 0x00000000,
491 (0x8e00 << 16) | (0x31068 >> 2),
492 0x00000000,
493 (0x9e00 << 16) | (0x31068 >> 2),
494 0x00000000,
495 (0xae00 << 16) | (0x31068 >> 2),
496 0x00000000,
497 (0xbe00 << 16) | (0x31068 >> 2),
498 0x00000000,
499 (0x0e00 << 16) | (0xcd10 >> 2),
500 0x00000000,
501 (0x0e00 << 16) | (0xcd14 >> 2),
502 0x00000000,
503 (0x0e00 << 16) | (0x88b0 >> 2),
504 0x00000000,
505 (0x0e00 << 16) | (0x88b4 >> 2),
506 0x00000000,
507 (0x0e00 << 16) | (0x88b8 >> 2),
508 0x00000000,
509 (0x0e00 << 16) | (0x88bc >> 2),
510 0x00000000,
511 (0x0400 << 16) | (0x89c0 >> 2),
512 0x00000000,
513 (0x0e00 << 16) | (0x88c4 >> 2),
514 0x00000000,
515 (0x0e00 << 16) | (0x88c8 >> 2),
516 0x00000000,
517 (0x0e00 << 16) | (0x88d0 >> 2),
518 0x00000000,
519 (0x0e00 << 16) | (0x88d4 >> 2),
520 0x00000000,
521 (0x0e00 << 16) | (0x88d8 >> 2),
522 0x00000000,
523 (0x0e00 << 16) | (0x8980 >> 2),
524 0x00000000,
525 (0x0e00 << 16) | (0x30938 >> 2),
526 0x00000000,
527 (0x0e00 << 16) | (0x3093c >> 2),
528 0x00000000,
529 (0x0e00 << 16) | (0x30940 >> 2),
530 0x00000000,
531 (0x0e00 << 16) | (0x89a0 >> 2),
532 0x00000000,
533 (0x0e00 << 16) | (0x30900 >> 2),
534 0x00000000,
535 (0x0e00 << 16) | (0x30904 >> 2),
536 0x00000000,
537 (0x0e00 << 16) | (0x89b4 >> 2),
538 0x00000000,
539 (0x0e00 << 16) | (0x3c210 >> 2),
540 0x00000000,
541 (0x0e00 << 16) | (0x3c214 >> 2),
542 0x00000000,
543 (0x0e00 << 16) | (0x3c218 >> 2),
544 0x00000000,
545 (0x0e00 << 16) | (0x8904 >> 2),
546 0x00000000,
547 0x5,
548 (0x0e00 << 16) | (0x8c28 >> 2),
549 (0x0e00 << 16) | (0x8c2c >> 2),
550 (0x0e00 << 16) | (0x8c30 >> 2),
551 (0x0e00 << 16) | (0x8c34 >> 2),
552 (0x0e00 << 16) | (0x9600 >> 2),
553};
554
555static const u32 kalindi_rlc_save_restore_register_list[] =
556{
557 (0x0e00 << 16) | (0xc12c >> 2),
558 0x00000000,
559 (0x0e00 << 16) | (0xc140 >> 2),
560 0x00000000,
561 (0x0e00 << 16) | (0xc150 >> 2),
562 0x00000000,
563 (0x0e00 << 16) | (0xc15c >> 2),
564 0x00000000,
565 (0x0e00 << 16) | (0xc168 >> 2),
566 0x00000000,
567 (0x0e00 << 16) | (0xc170 >> 2),
568 0x00000000,
569 (0x0e00 << 16) | (0xc204 >> 2),
570 0x00000000,
571 (0x0e00 << 16) | (0xc2b4 >> 2),
572 0x00000000,
573 (0x0e00 << 16) | (0xc2b8 >> 2),
574 0x00000000,
575 (0x0e00 << 16) | (0xc2bc >> 2),
576 0x00000000,
577 (0x0e00 << 16) | (0xc2c0 >> 2),
578 0x00000000,
579 (0x0e00 << 16) | (0x8228 >> 2),
580 0x00000000,
581 (0x0e00 << 16) | (0x829c >> 2),
582 0x00000000,
583 (0x0e00 << 16) | (0x869c >> 2),
584 0x00000000,
585 (0x0600 << 16) | (0x98f4 >> 2),
586 0x00000000,
587 (0x0e00 << 16) | (0x98f8 >> 2),
588 0x00000000,
589 (0x0e00 << 16) | (0x9900 >> 2),
590 0x00000000,
591 (0x0e00 << 16) | (0xc260 >> 2),
592 0x00000000,
593 (0x0e00 << 16) | (0x90e8 >> 2),
594 0x00000000,
595 (0x0e00 << 16) | (0x3c000 >> 2),
596 0x00000000,
597 (0x0e00 << 16) | (0x3c00c >> 2),
598 0x00000000,
599 (0x0e00 << 16) | (0x8c1c >> 2),
600 0x00000000,
601 (0x0e00 << 16) | (0x9700 >> 2),
602 0x00000000,
603 (0x0e00 << 16) | (0xcd20 >> 2),
604 0x00000000,
605 (0x4e00 << 16) | (0xcd20 >> 2),
606 0x00000000,
607 (0x5e00 << 16) | (0xcd20 >> 2),
608 0x00000000,
609 (0x6e00 << 16) | (0xcd20 >> 2),
610 0x00000000,
611 (0x7e00 << 16) | (0xcd20 >> 2),
612 0x00000000,
613 (0x0e00 << 16) | (0x89bc >> 2),
614 0x00000000,
615 (0x0e00 << 16) | (0x8900 >> 2),
616 0x00000000,
617 0x3,
618 (0x0e00 << 16) | (0xc130 >> 2),
619 0x00000000,
620 (0x0e00 << 16) | (0xc134 >> 2),
621 0x00000000,
622 (0x0e00 << 16) | (0xc1fc >> 2),
623 0x00000000,
624 (0x0e00 << 16) | (0xc208 >> 2),
625 0x00000000,
626 (0x0e00 << 16) | (0xc264 >> 2),
627 0x00000000,
628 (0x0e00 << 16) | (0xc268 >> 2),
629 0x00000000,
630 (0x0e00 << 16) | (0xc26c >> 2),
631 0x00000000,
632 (0x0e00 << 16) | (0xc270 >> 2),
633 0x00000000,
634 (0x0e00 << 16) | (0xc274 >> 2),
635 0x00000000,
636 (0x0e00 << 16) | (0xc28c >> 2),
637 0x00000000,
638 (0x0e00 << 16) | (0xc290 >> 2),
639 0x00000000,
640 (0x0e00 << 16) | (0xc294 >> 2),
641 0x00000000,
642 (0x0e00 << 16) | (0xc298 >> 2),
643 0x00000000,
644 (0x0e00 << 16) | (0xc2a0 >> 2),
645 0x00000000,
646 (0x0e00 << 16) | (0xc2a4 >> 2),
647 0x00000000,
648 (0x0e00 << 16) | (0xc2a8 >> 2),
649 0x00000000,
650 (0x0e00 << 16) | (0xc2ac >> 2),
651 0x00000000,
652 (0x0e00 << 16) | (0x301d0 >> 2),
653 0x00000000,
654 (0x0e00 << 16) | (0x30238 >> 2),
655 0x00000000,
656 (0x0e00 << 16) | (0x30250 >> 2),
657 0x00000000,
658 (0x0e00 << 16) | (0x30254 >> 2),
659 0x00000000,
660 (0x0e00 << 16) | (0x30258 >> 2),
661 0x00000000,
662 (0x0e00 << 16) | (0x3025c >> 2),
663 0x00000000,
664 (0x4e00 << 16) | (0xc900 >> 2),
665 0x00000000,
666 (0x5e00 << 16) | (0xc900 >> 2),
667 0x00000000,
668 (0x6e00 << 16) | (0xc900 >> 2),
669 0x00000000,
670 (0x7e00 << 16) | (0xc900 >> 2),
671 0x00000000,
672 (0x4e00 << 16) | (0xc904 >> 2),
673 0x00000000,
674 (0x5e00 << 16) | (0xc904 >> 2),
675 0x00000000,
676 (0x6e00 << 16) | (0xc904 >> 2),
677 0x00000000,
678 (0x7e00 << 16) | (0xc904 >> 2),
679 0x00000000,
680 (0x4e00 << 16) | (0xc908 >> 2),
681 0x00000000,
682 (0x5e00 << 16) | (0xc908 >> 2),
683 0x00000000,
684 (0x6e00 << 16) | (0xc908 >> 2),
685 0x00000000,
686 (0x7e00 << 16) | (0xc908 >> 2),
687 0x00000000,
688 (0x4e00 << 16) | (0xc90c >> 2),
689 0x00000000,
690 (0x5e00 << 16) | (0xc90c >> 2),
691 0x00000000,
692 (0x6e00 << 16) | (0xc90c >> 2),
693 0x00000000,
694 (0x7e00 << 16) | (0xc90c >> 2),
695 0x00000000,
696 (0x4e00 << 16) | (0xc910 >> 2),
697 0x00000000,
698 (0x5e00 << 16) | (0xc910 >> 2),
699 0x00000000,
700 (0x6e00 << 16) | (0xc910 >> 2),
701 0x00000000,
702 (0x7e00 << 16) | (0xc910 >> 2),
703 0x00000000,
704 (0x0e00 << 16) | (0xc99c >> 2),
705 0x00000000,
706 (0x0e00 << 16) | (0x9834 >> 2),
707 0x00000000,
708 (0x0000 << 16) | (0x30f00 >> 2),
709 0x00000000,
710 (0x0000 << 16) | (0x30f04 >> 2),
711 0x00000000,
712 (0x0000 << 16) | (0x30f08 >> 2),
713 0x00000000,
714 (0x0000 << 16) | (0x30f0c >> 2),
715 0x00000000,
716 (0x0600 << 16) | (0x9b7c >> 2),
717 0x00000000,
718 (0x0e00 << 16) | (0x8a14 >> 2),
719 0x00000000,
720 (0x0e00 << 16) | (0x8a18 >> 2),
721 0x00000000,
722 (0x0600 << 16) | (0x30a00 >> 2),
723 0x00000000,
724 (0x0e00 << 16) | (0x8bf0 >> 2),
725 0x00000000,
726 (0x0e00 << 16) | (0x8bcc >> 2),
727 0x00000000,
728 (0x0e00 << 16) | (0x8b24 >> 2),
729 0x00000000,
730 (0x0e00 << 16) | (0x30a04 >> 2),
731 0x00000000,
732 (0x0600 << 16) | (0x30a10 >> 2),
733 0x00000000,
734 (0x0600 << 16) | (0x30a14 >> 2),
735 0x00000000,
736 (0x0600 << 16) | (0x30a18 >> 2),
737 0x00000000,
738 (0x0600 << 16) | (0x30a2c >> 2),
739 0x00000000,
740 (0x0e00 << 16) | (0xc700 >> 2),
741 0x00000000,
742 (0x0e00 << 16) | (0xc704 >> 2),
743 0x00000000,
744 (0x0e00 << 16) | (0xc708 >> 2),
745 0x00000000,
746 (0x0e00 << 16) | (0xc768 >> 2),
747 0x00000000,
748 (0x0400 << 16) | (0xc770 >> 2),
749 0x00000000,
750 (0x0400 << 16) | (0xc774 >> 2),
751 0x00000000,
752 (0x0400 << 16) | (0xc798 >> 2),
753 0x00000000,
754 (0x0400 << 16) | (0xc79c >> 2),
755 0x00000000,
756 (0x0e00 << 16) | (0x9100 >> 2),
757 0x00000000,
758 (0x0e00 << 16) | (0x3c010 >> 2),
759 0x00000000,
760 (0x0e00 << 16) | (0x8c00 >> 2),
761 0x00000000,
762 (0x0e00 << 16) | (0x8c04 >> 2),
763 0x00000000,
764 (0x0e00 << 16) | (0x8c20 >> 2),
765 0x00000000,
766 (0x0e00 << 16) | (0x8c38 >> 2),
767 0x00000000,
768 (0x0e00 << 16) | (0x8c3c >> 2),
769 0x00000000,
770 (0x0e00 << 16) | (0xae00 >> 2),
771 0x00000000,
772 (0x0e00 << 16) | (0x9604 >> 2),
773 0x00000000,
774 (0x0e00 << 16) | (0xac08 >> 2),
775 0x00000000,
776 (0x0e00 << 16) | (0xac0c >> 2),
777 0x00000000,
778 (0x0e00 << 16) | (0xac10 >> 2),
779 0x00000000,
780 (0x0e00 << 16) | (0xac14 >> 2),
781 0x00000000,
782 (0x0e00 << 16) | (0xac58 >> 2),
783 0x00000000,
784 (0x0e00 << 16) | (0xac68 >> 2),
785 0x00000000,
786 (0x0e00 << 16) | (0xac6c >> 2),
787 0x00000000,
788 (0x0e00 << 16) | (0xac70 >> 2),
789 0x00000000,
790 (0x0e00 << 16) | (0xac74 >> 2),
791 0x00000000,
792 (0x0e00 << 16) | (0xac78 >> 2),
793 0x00000000,
794 (0x0e00 << 16) | (0xac7c >> 2),
795 0x00000000,
796 (0x0e00 << 16) | (0xac80 >> 2),
797 0x00000000,
798 (0x0e00 << 16) | (0xac84 >> 2),
799 0x00000000,
800 (0x0e00 << 16) | (0xac88 >> 2),
801 0x00000000,
802 (0x0e00 << 16) | (0xac8c >> 2),
803 0x00000000,
804 (0x0e00 << 16) | (0x970c >> 2),
805 0x00000000,
806 (0x0e00 << 16) | (0x9714 >> 2),
807 0x00000000,
808 (0x0e00 << 16) | (0x9718 >> 2),
809 0x00000000,
810 (0x0e00 << 16) | (0x971c >> 2),
811 0x00000000,
812 (0x0e00 << 16) | (0x31068 >> 2),
813 0x00000000,
814 (0x4e00 << 16) | (0x31068 >> 2),
815 0x00000000,
816 (0x5e00 << 16) | (0x31068 >> 2),
817 0x00000000,
818 (0x6e00 << 16) | (0x31068 >> 2),
819 0x00000000,
820 (0x7e00 << 16) | (0x31068 >> 2),
821 0x00000000,
822 (0x0e00 << 16) | (0xcd10 >> 2),
823 0x00000000,
824 (0x0e00 << 16) | (0xcd14 >> 2),
825 0x00000000,
826 (0x0e00 << 16) | (0x88b0 >> 2),
827 0x00000000,
828 (0x0e00 << 16) | (0x88b4 >> 2),
829 0x00000000,
830 (0x0e00 << 16) | (0x88b8 >> 2),
831 0x00000000,
832 (0x0e00 << 16) | (0x88bc >> 2),
833 0x00000000,
834 (0x0400 << 16) | (0x89c0 >> 2),
835 0x00000000,
836 (0x0e00 << 16) | (0x88c4 >> 2),
837 0x00000000,
838 (0x0e00 << 16) | (0x88c8 >> 2),
839 0x00000000,
840 (0x0e00 << 16) | (0x88d0 >> 2),
841 0x00000000,
842 (0x0e00 << 16) | (0x88d4 >> 2),
843 0x00000000,
844 (0x0e00 << 16) | (0x88d8 >> 2),
845 0x00000000,
846 (0x0e00 << 16) | (0x8980 >> 2),
847 0x00000000,
848 (0x0e00 << 16) | (0x30938 >> 2),
849 0x00000000,
850 (0x0e00 << 16) | (0x3093c >> 2),
851 0x00000000,
852 (0x0e00 << 16) | (0x30940 >> 2),
853 0x00000000,
854 (0x0e00 << 16) | (0x89a0 >> 2),
855 0x00000000,
856 (0x0e00 << 16) | (0x30900 >> 2),
857 0x00000000,
858 (0x0e00 << 16) | (0x30904 >> 2),
859 0x00000000,
860 (0x0e00 << 16) | (0x89b4 >> 2),
861 0x00000000,
862 (0x0e00 << 16) | (0x3e1fc >> 2),
863 0x00000000,
864 (0x0e00 << 16) | (0x3c210 >> 2),
865 0x00000000,
866 (0x0e00 << 16) | (0x3c214 >> 2),
867 0x00000000,
868 (0x0e00 << 16) | (0x3c218 >> 2),
869 0x00000000,
870 (0x0e00 << 16) | (0x8904 >> 2),
871 0x00000000,
872 0x5,
873 (0x0e00 << 16) | (0x8c28 >> 2),
874 (0x0e00 << 16) | (0x8c2c >> 2),
875 (0x0e00 << 16) | (0x8c30 >> 2),
876 (0x0e00 << 16) | (0x8c34 >> 2),
877 (0x0e00 << 16) | (0x9600 >> 2),
878};
879
880static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
881static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
882static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
883static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
7dae69a2 884static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
a2e73f56
AD		 885
886/*
887 * Core functions
888 */
889/**
890 * gfx_v7_0_init_microcode - load ucode images from disk
891 *
892 * @adev: amdgpu_device pointer
893 *
894 * Use the firmware interface to load the ucode images into
895 * the driver (not loaded into hw).
896 * Returns 0 on success, error on failure.
897 */
898static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
899{
900 const char *chip_name;
901 char fw_name[30];
902 int err;
903
904 DRM_DEBUG("\n");
905
906 switch (adev->asic_type) {
907 case CHIP_BONAIRE:
908 chip_name = "bonaire";
909 break;
910 case CHIP_HAWAII:
911 chip_name = "hawaii";
912 break;
913 case CHIP_KAVERI:
914 chip_name = "kaveri";
915 break;
916 case CHIP_KABINI:
917 chip_name = "kabini";
918 break;
919 case CHIP_MULLINS:
920 chip_name = "mullins";
921 break;
922 default: BUG();
923 }
924
925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
927 if (err)
928 goto out;
929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
930 if (err)
931 goto out;
932
933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
935 if (err)
936 goto out;
937 err = amdgpu_ucode_validate(adev->gfx.me_fw);
938 if (err)
939 goto out;
940
941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
943 if (err)
944 goto out;
945 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
946 if (err)
947 goto out;
948
949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
951 if (err)
952 goto out;
953 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
954 if (err)
955 goto out;
956
957 if (adev->asic_type == CHIP_KAVERI) {
958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
960 if (err)
961 goto out;
962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
963 if (err)
964 goto out;
965 }
966
967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
969 if (err)
970 goto out;
971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
972
973out:
974 if (err) {
975 printk(KERN_ERR
976 "gfx7: Failed to load firmware \"%s\"\n",
977 fw_name);
978 release_firmware(adev->gfx.pfp_fw);
979 adev->gfx.pfp_fw = NULL;
980 release_firmware(adev->gfx.me_fw);
981 adev->gfx.me_fw = NULL;
982 release_firmware(adev->gfx.ce_fw);
983 adev->gfx.ce_fw = NULL;
984 release_firmware(adev->gfx.mec_fw);
985 adev->gfx.mec_fw = NULL;
986 release_firmware(adev->gfx.mec2_fw);
987 adev->gfx.mec2_fw = NULL;
988 release_firmware(adev->gfx.rlc_fw);
989 adev->gfx.rlc_fw = NULL;
990 }
991 return err;
992}
993
e517cd77
ML		 994static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
995{
996 release_firmware(adev->gfx.pfp_fw);
997 adev->gfx.pfp_fw = NULL;
998 release_firmware(adev->gfx.me_fw);
999 adev->gfx.me_fw = NULL;
1000 release_firmware(adev->gfx.ce_fw);
1001 adev->gfx.ce_fw = NULL;
1002 release_firmware(adev->gfx.mec_fw);
1003 adev->gfx.mec_fw = NULL;
1004 release_firmware(adev->gfx.mec2_fw);
1005 adev->gfx.mec2_fw = NULL;
1006 release_firmware(adev->gfx.rlc_fw);
1007 adev->gfx.rlc_fw = NULL;
1008}
1009
a2e73f56
AD		 1010/**
1011 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1012 *
1013 * @adev: amdgpu_device pointer
1014 *
1015 * Starting with SI, the tiling setup is done globally in a
1016 * set of 32 tiling modes. Rather than selecting each set of
1017 * parameters per surface as on older asics, we just select
1018 * which index in the tiling table we want to use, and the
1019 * surface uses those parameters (CIK).
1020 */
1021static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1022{
840a20d3
TSD		 1023 const u32 num_tile_mode_states =
1024 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1025 const u32 num_secondary_tile_mode_states =
1026 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1027 u32 reg_offset, split_equal_to_row_size;
1028 uint32_t *tile, *macrotile;
1029
1030 tile = adev->gfx.config.tile_mode_array;
1031 macrotile = adev->gfx.config.macrotile_mode_array;
a2e73f56
AD		 1032
1033 switch (adev->gfx.config.mem_row_size_in_kb) {
1034 case 1:
1035 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1036 break;
1037 case 2:
1038 default:
1039 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1040 break;
1041 case 4:
1042 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1043 break;
1044 }
1045
840a20d3
TSD		 1046 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1047 tile[reg_offset] = 0;
1048 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1049 macrotile[reg_offset] = 0;
1050
a2e73f56
AD		 1051 switch (adev->asic_type) {
1052 case CHIP_BONAIRE:
840a20d3
TSD		 1053 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1057 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1061 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1064 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1065 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1067 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1068 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1069 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1071 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1072 TILE_SPLIT(split_equal_to_row_size));
1073 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1074 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1075 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1076 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1077 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1078 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1079 TILE_SPLIT(split_equal_to_row_size));
1080 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1081 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1082 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1083 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1085 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1086 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1095 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1098 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1099 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1100 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1102 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1106 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1110 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1111 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1115 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1118 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1119 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1120 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1122 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1123 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1124 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1126 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1127 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1128 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1130 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1131 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1132 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1135 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1136 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1137 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1139 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1140 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1143 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1144 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1145 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1146 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1147 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1148 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1150 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1151 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1152 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1154 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1155
1156 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1159 NUM_BANKS(ADDR_SURF_16_BANK));
1160 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1163 NUM_BANKS(ADDR_SURF_16_BANK));
1164 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1167 NUM_BANKS(ADDR_SURF_16_BANK));
1168 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1171 NUM_BANKS(ADDR_SURF_16_BANK));
1172 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1179 NUM_BANKS(ADDR_SURF_8_BANK));
1180 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183 NUM_BANKS(ADDR_SURF_4_BANK));
1184 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1191 NUM_BANKS(ADDR_SURF_16_BANK));
1192 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1195 NUM_BANKS(ADDR_SURF_16_BANK));
1196 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1199 NUM_BANKS(ADDR_SURF_16_BANK));
1200 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1203 NUM_BANKS(ADDR_SURF_16_BANK));
1204 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1207 NUM_BANKS(ADDR_SURF_8_BANK));
1208 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1211 NUM_BANKS(ADDR_SURF_4_BANK));
a2e73f56 1212
840a20d3
TSD		 1213 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1214 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1215 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1216 if (reg_offset != 7)
1217 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1218 break;
1219 case CHIP_HAWAII:
840a20d3
TSD		 1220 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1224 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1228 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1232 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1236 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1238 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1239 TILE_SPLIT(split_equal_to_row_size));
1240 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1243 TILE_SPLIT(split_equal_to_row_size));
1244 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1247 TILE_SPLIT(split_equal_to_row_size));
1248 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1249 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1251 TILE_SPLIT(split_equal_to_row_size));
1252 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1254 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1255 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1257 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1259 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1261 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1262 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1263 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1265 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1266 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1267 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1268 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1269 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1270 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1271 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1272 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1276 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1279 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1280 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1282 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1284 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1285 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1286 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1288 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1290 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1292 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1294 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1295 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1308 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1311 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1312 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1313 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1314 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1315 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1316 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1319 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1320 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1321 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1323 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1324 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1325 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1326 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1328 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1330 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1332 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1334 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1335 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1336 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
a2e73f56 1338
840a20d3
TSD		 1339 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1342 NUM_BANKS(ADDR_SURF_16_BANK));
1343 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1346 NUM_BANKS(ADDR_SURF_16_BANK));
1347 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350 NUM_BANKS(ADDR_SURF_16_BANK));
1351 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1354 NUM_BANKS(ADDR_SURF_16_BANK));
1355 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1358 NUM_BANKS(ADDR_SURF_8_BANK));
1359 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362 NUM_BANKS(ADDR_SURF_4_BANK));
1363 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366 NUM_BANKS(ADDR_SURF_4_BANK));
1367 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370 NUM_BANKS(ADDR_SURF_16_BANK));
1371 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374 NUM_BANKS(ADDR_SURF_16_BANK));
1375 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378 NUM_BANKS(ADDR_SURF_16_BANK));
1379 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1382 NUM_BANKS(ADDR_SURF_8_BANK));
1383 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1386 NUM_BANKS(ADDR_SURF_16_BANK));
1387 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1390 NUM_BANKS(ADDR_SURF_8_BANK));
1391 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1394 NUM_BANKS(ADDR_SURF_4_BANK));
1395
1396 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1397 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1398 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1399 if (reg_offset != 7)
1400 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1401 break;
1402 case CHIP_KABINI:
1403 case CHIP_KAVERI:
1404 case CHIP_MULLINS:
1405 default:
840a20d3
TSD		 1406 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P2) |
1408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1410 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1411 PIPE_CONFIG(ADDR_SURF_P2) |
1412 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1414 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1415 PIPE_CONFIG(ADDR_SURF_P2) |
1416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1417 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1418 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1419 PIPE_CONFIG(ADDR_SURF_P2) |
1420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1421 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1422 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1423 PIPE_CONFIG(ADDR_SURF_P2) |
1424 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1425 TILE_SPLIT(split_equal_to_row_size));
1426 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1427 PIPE_CONFIG(ADDR_SURF_P2) |
1428 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1429 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1430 PIPE_CONFIG(ADDR_SURF_P2) |
1431 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1432 TILE_SPLIT(split_equal_to_row_size));
1433 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1434 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1435 PIPE_CONFIG(ADDR_SURF_P2));
1436 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1437 PIPE_CONFIG(ADDR_SURF_P2) |
1438 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1439 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1440 PIPE_CONFIG(ADDR_SURF_P2) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444 PIPE_CONFIG(ADDR_SURF_P2) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1448 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1449 PIPE_CONFIG(ADDR_SURF_P2) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1451 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1452 PIPE_CONFIG(ADDR_SURF_P2) |
1453 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1454 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1455 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1456 PIPE_CONFIG(ADDR_SURF_P2) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1459 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1460 PIPE_CONFIG(ADDR_SURF_P2) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1463 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1464 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1465 PIPE_CONFIG(ADDR_SURF_P2) |
1466 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1467 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1468 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1469 PIPE_CONFIG(ADDR_SURF_P2) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1471 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1472 PIPE_CONFIG(ADDR_SURF_P2) |
1473 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1475 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1476 PIPE_CONFIG(ADDR_SURF_P2) |
1477 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1479 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1480 PIPE_CONFIG(ADDR_SURF_P2) |
1481 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1482 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1483 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1484 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1485 PIPE_CONFIG(ADDR_SURF_P2) |
1486 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1488 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1489 PIPE_CONFIG(ADDR_SURF_P2) |
1490 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1491 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1492 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1493 PIPE_CONFIG(ADDR_SURF_P2) |
1494 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1495 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1496 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1497 PIPE_CONFIG(ADDR_SURF_P2) |
1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1499 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1500 PIPE_CONFIG(ADDR_SURF_P2) |
1501 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1503 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1504 PIPE_CONFIG(ADDR_SURF_P2) |
1505 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1506 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1507 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1508
1509 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1512 NUM_BANKS(ADDR_SURF_8_BANK));
1513 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1516 NUM_BANKS(ADDR_SURF_8_BANK));
1517 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520 NUM_BANKS(ADDR_SURF_8_BANK));
1521 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1524 NUM_BANKS(ADDR_SURF_8_BANK));
1525 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1528 NUM_BANKS(ADDR_SURF_8_BANK));
1529 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1532 NUM_BANKS(ADDR_SURF_8_BANK));
1533 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1536 NUM_BANKS(ADDR_SURF_8_BANK));
1537 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540 NUM_BANKS(ADDR_SURF_16_BANK));
1541 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544 NUM_BANKS(ADDR_SURF_16_BANK));
1545 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1548 NUM_BANKS(ADDR_SURF_16_BANK));
1549 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1552 NUM_BANKS(ADDR_SURF_16_BANK));
1553 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1556 NUM_BANKS(ADDR_SURF_16_BANK));
1557 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1560 NUM_BANKS(ADDR_SURF_16_BANK));
1561 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1564 NUM_BANKS(ADDR_SURF_8_BANK));
a2e73f56 1565
840a20d3
TSD		 1566 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1567 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1568 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1569 if (reg_offset != 7)
1570 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1571 break;
1572 }
1573}
1574
1575/**
1576 * gfx_v7_0_select_se_sh - select which SE, SH to address
1577 *
1578 * @adev: amdgpu_device pointer
1579 * @se_num: shader engine to address
1580 * @sh_num: sh block to address
1581 *
1582 * Select which SE, SH combinations to address. Certain
1583 * registers are instanced per SE or SH. 0xffffffff means
1584 * broadcast to all SEs or SHs (CIK).
1585 */
05fb7291 1586static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
9559ef5b 1587 u32 se_num, u32 sh_num, u32 instance)
a2e73f56 1588{
9559ef5b
TSD		 1589 u32 data;
1590
1591 if (instance == 0xffffffff)
1592 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1593 else
1594 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
a2e73f56
AD		 1595
1596 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1597 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1598 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1599 else if (se_num == 0xffffffff)
1600 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1601 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1602 else if (sh_num == 0xffffffff)
1603 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1604 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1605 else
1606 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1607 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1608 WREG32(mmGRBM_GFX_INDEX, data);
1609}
1610
1611/**
1612 * gfx_v7_0_create_bitmask - create a bitmask
1613 *
1614 * @bit_width: length of the mask
1615 *
1616 * create a variable length bit mask (CIK).
1617 * Returns the bitmask.
1618 */
1619static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1620{
8f8e00c1 1621 return (u32)((1ULL << bit_width) - 1);
a2e73f56
AD		 1622}
1623
1624/**
8f8e00c1 1625 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
a2e73f56
AD		 1626 *
1627 * @adev: amdgpu_device pointer
a2e73f56 1628 *
8f8e00c1
AD		 1629 * Calculates the bitmask of enabled RBs (CIK).
1630 * Returns the enabled RB bitmask.
a2e73f56 1631 */
8f8e00c1 1632static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
a2e73f56
AD		 1633{
1634 u32 data, mask;
1635
1636 data = RREG32(mmCC_RB_BACKEND_DISABLE);
a2e73f56
AD		 1637 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1638
8f8e00c1 1639 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
a2e73f56
AD		 1640 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1641
8f8e00c1
AD		 1642 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1643 adev->gfx.config.max_sh_per_se);
a2e73f56 1644
8f8e00c1 1645 return (~data) & mask;
a2e73f56
AD		 1646}
1647
0b2138a4
HR		 1648static void
1649gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1650{
1651 switch (adev->asic_type) {
1652 case CHIP_BONAIRE:
1653 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1654 SE_XSEL(1) | SE_YSEL(1);
1655 *rconf1 |= 0x0;
1656 break;
1657 case CHIP_HAWAII:
1658 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1659 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1660 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1661 SE_YSEL(3);
1662 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1663 SE_PAIR_YSEL(2);
1664 break;
1665 case CHIP_KAVERI:
1666 *rconf |= RB_MAP_PKR0(2);
1667 *rconf1 |= 0x0;
1668 break;
1669 case CHIP_KABINI:
1670 case CHIP_MULLINS:
1671 *rconf |= 0x0;
1672 *rconf1 |= 0x0;
1673 break;
1674 default:
1675 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1676 break;
1677 }
1678}
1679
1680static void
1681gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1682 u32 raster_config, u32 raster_config_1,
1683 unsigned rb_mask, unsigned num_rb)
1684{
1685 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1686 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1687 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1688 unsigned rb_per_se = num_rb / num_se;
1689 unsigned se_mask[4];
1690 unsigned se;
1691
1692 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1693 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1694 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1695 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1696
1697 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1698 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1699 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1700
1701 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1702 (!se_mask[2] && !se_mask[3]))) {
1703 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1704
1705 if (!se_mask[0] && !se_mask[1]) {
1706 raster_config_1 |=
1707 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1708 } else {
1709 raster_config_1 |=
1710 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1711 }
1712 }
1713
1714 for (se = 0; se < num_se; se++) {
1715 unsigned raster_config_se = raster_config;
1716 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1717 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1718 int idx = (se / 2) * 2;
1719
1720 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1721 raster_config_se &= ~SE_MAP_MASK;
1722
1723 if (!se_mask[idx]) {
1724 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1725 } else {
1726 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1727 }
1728 }
1729
1730 pkr0_mask &= rb_mask;
1731 pkr1_mask &= rb_mask;
1732 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1733 raster_config_se &= ~PKR_MAP_MASK;
1734
1735 if (!pkr0_mask) {
1736 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1737 } else {
1738 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1739 }
1740 }
1741
1742 if (rb_per_se >= 2) {
1743 unsigned rb0_mask = 1 << (se * rb_per_se);
1744 unsigned rb1_mask = rb0_mask << 1;
1745
1746 rb0_mask &= rb_mask;
1747 rb1_mask &= rb_mask;
1748 if (!rb0_mask || !rb1_mask) {
1749 raster_config_se &= ~RB_MAP_PKR0_MASK;
1750
1751 if (!rb0_mask) {
1752 raster_config_se |=
1753 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1754 } else {
1755 raster_config_se |=
1756 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1757 }
1758 }
1759
1760 if (rb_per_se > 2) {
1761 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1762 rb1_mask = rb0_mask << 1;
1763 rb0_mask &= rb_mask;
1764 rb1_mask &= rb_mask;
1765 if (!rb0_mask || !rb1_mask) {
1766 raster_config_se &= ~RB_MAP_PKR1_MASK;
1767
1768 if (!rb0_mask) {
1769 raster_config_se |=
1770 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1771 } else {
1772 raster_config_se |=
1773 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1774 }
1775 }
1776 }
1777 }
1778
1779 /* GRBM_GFX_INDEX has a different offset on CI+ */
1780 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1781 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1782 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1783 }
1784
1785 /* GRBM_GFX_INDEX has a different offset on CI+ */
1786 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1787}
1788
a2e73f56
AD		 1789/**
1790 * gfx_v7_0_setup_rb - setup the RBs on the asic
1791 *
1792 * @adev: amdgpu_device pointer
1793 * @se_num: number of SEs (shader engines) for the asic
1794 * @sh_per_se: number of SH blocks per SE for the asic
a2e73f56
AD		 1795 *
1796 * Configures per-SE/SH RB registers (CIK).
1797 */
8f8e00c1 1798static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
a2e73f56
AD		 1799{
1800 int i, j;
aac1e3ca 1801 u32 data;
0b2138a4 1802 u32 raster_config = 0, raster_config_1 = 0;
8f8e00c1 1803 u32 active_rbs = 0;
6157bd7a
FC		 1804 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1805 adev->gfx.config.max_sh_per_se;
0b2138a4 1806 unsigned num_rb_pipes;
a2e73f56
AD		 1807
1808 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 1809 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1810 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9559ef5b 1811 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
8f8e00c1 1812 data = gfx_v7_0_get_rb_active_bitmap(adev);
6157bd7a
FC		 1813 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1814 rb_bitmap_width_per_sh);
a2e73f56
AD		 1815 }
1816 }
9559ef5b 1817 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56 1818
8f8e00c1 1819 adev->gfx.config.backend_enable_mask = active_rbs;
aac1e3ca 1820 adev->gfx.config.num_rbs = hweight32(active_rbs);
0b2138a4
HR		 1821
1822 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1823 adev->gfx.config.max_shader_engines, 16);
1824
1825 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1826
1827 if (!adev->gfx.config.backend_enable_mask ||
1828 adev->gfx.config.num_rbs >= num_rb_pipes) {
1829 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1830 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1831 } else {
1832 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1833 adev->gfx.config.backend_enable_mask,
1834 num_rb_pipes);
1835 }
1836 mutex_unlock(&adev->grbm_idx_mutex);
a2e73f56
AD		 1837}
1838
cd06bf68
BG		 1839/**
1840 * gmc_v7_0_init_compute_vmid - gart enable
1841 *
1842 * @rdev: amdgpu_device pointer
1843 *
1844 * Initialize compute vmid sh_mem registers
1845 *
1846 */
1847#define DEFAULT_SH_MEM_BASES (0x6000)
1848#define FIRST_COMPUTE_VMID (8)
1849#define LAST_COMPUTE_VMID (16)
1850static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1851{
1852 int i;
1853 uint32_t sh_mem_config;
1854 uint32_t sh_mem_bases;
1855
1856 /*
1857 * Configure apertures:
1858 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1859 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1860 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1861 */
1862 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1863 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1864 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1865 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1866 mutex_lock(&adev->srbm_mutex);
1867 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1868 cik_srbm_select(adev, 0, 0, 0, i);
1869 /* CP and shaders */
1870 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1871 WREG32(mmSH_MEM_APE1_BASE, 1);
1872 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1873 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1874 }
1875 cik_srbm_select(adev, 0, 0, 0, 0);
1876 mutex_unlock(&adev->srbm_mutex);
1877}
1878
df6e2c4a
JZ		 1879static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1880{
1881 adev->gfx.config.double_offchip_lds_buf = 1;
1882}
1883
a2e73f56
AD		 1884/**
1885 * gfx_v7_0_gpu_init - setup the 3D engine
1886 *
1887 * @adev: amdgpu_device pointer
1888 *
1889 * Configures the 3D engine and tiling configuration
1890 * registers so that the 3D engine is usable.
1891 */
1892static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1893{
d93f3ca7 1894 u32 tmp, sh_mem_cfg;
a2e73f56
AD		 1895 int i;
1896
a2e73f56
AD		 1897 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1898
d93f3ca7
AD		 1899 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1900 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1901 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
a2e73f56
AD		 1902
1903 gfx_v7_0_tiling_mode_table_init(adev);
1904
8f8e00c1 1905 gfx_v7_0_setup_rb(adev);
7dae69a2 1906 gfx_v7_0_get_cu_info(adev);
df6e2c4a 1907 gfx_v7_0_config_init(adev);
a2e73f56
AD		 1908
1909 /* set HW defaults for 3D engine */
1910 WREG32(mmCP_MEQ_THRESHOLDS,
d93f3ca7
AD		 1911 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1912 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
a2e73f56
AD		 1913
1914 mutex_lock(&adev->grbm_idx_mutex);
1915 /*
1916 * making sure that the following register writes will be broadcasted
1917 * to all the shaders
1918 */
9559ef5b 1919 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 1920
1921 /* XXX SH_MEM regs */
1922 /* where to put LDS, scratch, GPUVM in FSA64 space */
d93f3ca7 1923 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165
JX		 1924 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1925
a2e73f56
AD		 1926 mutex_lock(&adev->srbm_mutex);
1927 for (i = 0; i < 16; i++) {
1928 cik_srbm_select(adev, 0, 0, 0, i);
1929 /* CP and shaders */
74a5d165 1930 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
a2e73f56
AD		 1931 WREG32(mmSH_MEM_APE1_BASE, 1);
1932 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1933 WREG32(mmSH_MEM_BASES, 0);
1934 }
1935 cik_srbm_select(adev, 0, 0, 0, 0);
1936 mutex_unlock(&adev->srbm_mutex);
1937
cd06bf68
BG		 1938 gmc_v7_0_init_compute_vmid(adev);
1939
a2e73f56
AD		 1940 WREG32(mmSX_DEBUG_1, 0x20);
1941
1942 WREG32(mmTA_CNTL_AUX, 0x00010000);
1943
1944 tmp = RREG32(mmSPI_CONFIG_CNTL);
1945 tmp |= 0x03000000;
1946 WREG32(mmSPI_CONFIG_CNTL, tmp);
1947
1948 WREG32(mmSQ_CONFIG, 1);
1949
1950 WREG32(mmDB_DEBUG, 0);
1951
1952 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1953 tmp |= 0x00000400;
1954 WREG32(mmDB_DEBUG2, tmp);
1955
1956 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1957 tmp |= 0x00020200;
1958 WREG32(mmDB_DEBUG3, tmp);
1959
1960 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1961 tmp |= 0x00018208;
1962 WREG32(mmCB_HW_CONTROL, tmp);
1963
1964 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1965
1966 WREG32(mmPA_SC_FIFO_SIZE,
1967 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1968 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1969 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1970 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1971
1972 WREG32(mmVGT_NUM_INSTANCES, 1);
1973
1974 WREG32(mmCP_PERFMON_CNTL, 0);
1975
1976 WREG32(mmSQ_CONFIG, 0);
1977
1978 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1979 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1980 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1981
1982 WREG32(mmVGT_CACHE_INVALIDATION,
1983 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1984 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1985
1986 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1987 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1988
1989 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1990 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1991 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
d2383267 1992
1993 tmp = RREG32(mmSPI_ARB_PRIORITY);
1994 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
1995 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
1996 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
1997 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
1998 WREG32(mmSPI_ARB_PRIORITY, tmp);
1999
a2e73f56
AD		 2000 mutex_unlock(&adev->grbm_idx_mutex);
2001
2002 udelay(50);
2003}
2004
2005/*
2006 * GPU scratch registers helpers function.
2007 */
2008/**
2009 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2010 *
2011 * @adev: amdgpu_device pointer
2012 *
2013 * Set up the number and offset of the CP scratch registers.
2014 * NOTE: use of CP scratch registers is a legacy inferface and
2015 * is not used by default on newer asics (r6xx+). On newer asics,
2016 * memory buffers are used for fences rather than scratch regs.
2017 */
2018static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2019{
a2e73f56
AD		 2020 adev->gfx.scratch.num_reg = 7;
2021 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
50261151 2022 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
a2e73f56
AD		 2023}
2024
2025/**
2026 * gfx_v7_0_ring_test_ring - basic gfx ring test
2027 *
2028 * @adev: amdgpu_device pointer
2029 * @ring: amdgpu_ring structure holding ring information
2030 *
2031 * Allocate a scratch register and write to it using the gfx ring (CIK).
2032 * Provides a basic gfx ring test to verify that the ring is working.
2033 * Used by gfx_v7_0_cp_gfx_resume();
2034 * Returns 0 on success, error on failure.
2035 */
2036static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2037{
2038 struct amdgpu_device *adev = ring->adev;
2039 uint32_t scratch;
2040 uint32_t tmp = 0;
2041 unsigned i;
2042 int r;
2043
2044 r = amdgpu_gfx_scratch_get(adev, &scratch);
2045 if (r) {
2046 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2047 return r;
2048 }
2049 WREG32(scratch, 0xCAFEDEAD);
a27de35c 2050 r = amdgpu_ring_alloc(ring, 3);
a2e73f56
AD		 2051 if (r) {
2052 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2053 amdgpu_gfx_scratch_free(adev, scratch);
2054 return r;
2055 }
2056 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2057 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2058 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 2059 amdgpu_ring_commit(ring);
a2e73f56
AD		 2060
2061 for (i = 0; i < adev->usec_timeout; i++) {
2062 tmp = RREG32(scratch);
2063 if (tmp == 0xDEADBEEF)
2064 break;
2065 DRM_UDELAY(1);
2066 }
2067 if (i < adev->usec_timeout) {
2068 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2069 } else {
2070 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2071 ring->idx, scratch, tmp);
2072 r = -EINVAL;
2073 }
2074 amdgpu_gfx_scratch_free(adev, scratch);
2075 return r;
2076}
2077
2078/**
d2edb07b 2079 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
a2e73f56
AD		 2080 *
2081 * @adev: amdgpu_device pointer
2082 * @ridx: amdgpu ring index
2083 *
2084 * Emits an hdp flush on the cp.
2085 */
d2edb07b 2086static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 2087{
2088 u32 ref_and_mask;
21cd942e 2089 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
a2e73f56 2090
21cd942e 2091 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
a2e73f56
AD		 2092 switch (ring->me) {
2093 case 1:
2094 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2095 break;
2096 case 2:
2097 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2098 break;
2099 default:
2100 return;
2101 }
2102 } else {
2103 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2104 }
2105
2106 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2107 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2108 WAIT_REG_MEM_FUNCTION(3) | /* == */
d9b5327a 2109 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
a2e73f56
AD		 2110 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2111 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2112 amdgpu_ring_write(ring, ref_and_mask);
2113 amdgpu_ring_write(ring, ref_and_mask);
2114 amdgpu_ring_write(ring, 0x20); /* poll interval */
2115}
2116
45682886
ML		 2117static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2118{
2119 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2120 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2121 EVENT_INDEX(4));
2122
2123 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2124 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2125 EVENT_INDEX(0));
2126}
2127
2128
0955860b
CZ		 2129/**
2130 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2131 *
2132 * @adev: amdgpu_device pointer
2133 * @ridx: amdgpu ring index
2134 *
2135 * Emits an hdp invalidate on the cp.
2136 */
2137static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2138{
2139 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2140 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2141 WRITE_DATA_DST_SEL(0) |
2142 WR_CONFIRM));
2143 amdgpu_ring_write(ring, mmHDP_DEBUG0);
2144 amdgpu_ring_write(ring, 0);
2145 amdgpu_ring_write(ring, 1);
2146}
2147
a2e73f56
AD		 2148/**
2149 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2150 *
2151 * @adev: amdgpu_device pointer
2152 * @fence: amdgpu fence object
2153 *
2154 * Emits a fence sequnce number on the gfx ring and flushes
2155 * GPU caches.
2156 */
2157static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 2158 u64 seq, unsigned flags)
a2e73f56 2159{
890ee23f
CZ		 2160 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2161 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
a2e73f56
AD		 2162 /* Workaround for cache flush problems. First send a dummy EOP
2163 * event down the pipe with seq one below.
2164 */
2165 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2166 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2167 EOP_TC_ACTION_EN |
2168 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2169 EVENT_INDEX(5)));
2170 amdgpu_ring_write(ring, addr & 0xfffffffc);
2171 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2172 DATA_SEL(1) | INT_SEL(0));
2173 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2174 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2175
2176 /* Then send the real EOP event down the pipe. */
2177 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2178 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2179 EOP_TC_ACTION_EN |
2180 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2181 EVENT_INDEX(5)));
2182 amdgpu_ring_write(ring, addr & 0xfffffffc);
2183 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 2184 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2185 amdgpu_ring_write(ring, lower_32_bits(seq));
2186 amdgpu_ring_write(ring, upper_32_bits(seq));
2187}
2188
2189/**
2190 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2191 *
2192 * @adev: amdgpu_device pointer
2193 * @fence: amdgpu fence object
2194 *
2195 * Emits a fence sequnce number on the compute ring and flushes
2196 * GPU caches.
2197 */
2198static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2199 u64 addr, u64 seq,
890ee23f 2200 unsigned flags)
a2e73f56 2201{
890ee23f
CZ		 2202 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2203 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2204
a2e73f56
AD		 2205 /* RELEASE_MEM - flush caches, send int */
2206 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2207 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2208 EOP_TC_ACTION_EN |
2209 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2210 EVENT_INDEX(5)));
890ee23f 2211 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2212 amdgpu_ring_write(ring, addr & 0xfffffffc);
2213 amdgpu_ring_write(ring, upper_32_bits(addr));
2214 amdgpu_ring_write(ring, lower_32_bits(seq));
2215 amdgpu_ring_write(ring, upper_32_bits(seq));
2216}
2217
a2e73f56
AD		 2218/*
2219 * IB stuff
2220 */
2221/**
2222 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2223 *
2224 * @ring: amdgpu_ring structure holding ring information
2225 * @ib: amdgpu indirect buffer object
2226 *
2227 * Emits an DE (drawing engine) or CE (constant engine) IB
2228 * on the gfx ring. IBs are usually generated by userspace
2229 * acceleration drivers and submitted to the kernel for
2230 * sheduling on the ring. This function schedules the IB
2231 * on the gfx ring for execution by the GPU.
2232 */
93323131 2233static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
d88bf583
CK		 2234 struct amdgpu_ib *ib,
2235 unsigned vm_id, bool ctx_switch)
a2e73f56
AD		 2236{
2237 u32 header, control = 0;
a2e73f56 2238
a2e73f56 2239 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
f153d286 2240 if (ctx_switch) {
a2e73f56
AD		 2241 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2242 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 2243 }
2244
de807f81 2245 if (ib->flags & AMDGPU_IB_FLAG_CE)
a2e73f56
AD		 2246 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2247 else
2248 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2249
d88bf583 2250 control |= ib->length_dw | (vm_id << 24);
a2e73f56
AD		 2251
2252 amdgpu_ring_write(ring, header);
2253 amdgpu_ring_write(ring,
2254#ifdef __BIG_ENDIAN
2255 (2 << 0) |
2256#endif
2257 (ib->gpu_addr & 0xFFFFFFFC));
2258 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2259 amdgpu_ring_write(ring, control);
2260}
2261
93323131 2262static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
d88bf583
CK		 2263 struct amdgpu_ib *ib,
2264 unsigned vm_id, bool ctx_switch)
93323131 2265{
33b7ed01 2266 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
93323131 2267
33b7ed01 2268 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
93323131 2269 amdgpu_ring_write(ring,
2270#ifdef __BIG_ENDIAN
2271 (2 << 0) |
2272#endif
2273 (ib->gpu_addr & 0xFFFFFFFC));
2274 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2275 amdgpu_ring_write(ring, control);
2276}
2277
753ad49c
ML		 2278static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2279{
2280 uint32_t dw2 = 0;
2281
2282 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2283 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
45682886 2284 gfx_v7_0_ring_emit_vgt_flush(ring);
753ad49c
ML		 2285 /* set load_global_config & load_global_uconfig */
2286 dw2 |= 0x8001;
2287 /* set load_cs_sh_regs */
2288 dw2 |= 0x01000000;
2289 /* set load_per_context_state & load_gfx_sh_regs */
2290 dw2 |= 0x10002;
2291 }
2292
2293 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2294 amdgpu_ring_write(ring, dw2);
2295 amdgpu_ring_write(ring, 0);
2296}
2297
a2e73f56
AD		 2298/**
2299 * gfx_v7_0_ring_test_ib - basic ring IB test
2300 *
2301 * @ring: amdgpu_ring structure holding ring information
2302 *
2303 * Allocate an IB and execute it on the gfx ring (CIK).
2304 * Provides a basic gfx ring test to verify that IBs are working.
2305 * Returns 0 on success, error on failure.
2306 */
bbec97aa 2307static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
a2e73f56
AD		 2308{
2309 struct amdgpu_device *adev = ring->adev;
2310 struct amdgpu_ib ib;
f54d1867 2311 struct dma_fence *f = NULL;
a2e73f56
AD		 2312 uint32_t scratch;
2313 uint32_t tmp = 0;
bbec97aa 2314 long r;
a2e73f56
AD		 2315
2316 r = amdgpu_gfx_scratch_get(adev, &scratch);
2317 if (r) {
bbec97aa 2318 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
a2e73f56
AD		 2319 return r;
2320 }
2321 WREG32(scratch, 0xCAFEDEAD);
b203dd95 2322 memset(&ib, 0, sizeof(ib));
b07c60c0 2323 r = amdgpu_ib_get(adev, NULL, 256, &ib);
a2e73f56 2324 if (r) {
bbec97aa 2325 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
42d13693 2326 goto err1;
a2e73f56
AD		 2327 }
2328 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2329 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2330 ib.ptr[2] = 0xDEADBEEF;
2331 ib.length_dw = 3;
42d13693 2332
50ddc75e 2333 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
42d13693
CZ		 2334 if (r)
2335 goto err2;
2336
f54d1867 2337 r = dma_fence_wait_timeout(f, false, timeout);
bbec97aa
CK		 2338 if (r == 0) {
2339 DRM_ERROR("amdgpu: IB test timed out\n");
2340 r = -ETIMEDOUT;
2341 goto err2;
2342 } else if (r < 0) {
2343 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
42d13693 2344 goto err2;
a2e73f56 2345 }
6d44565d
CK		 2346 tmp = RREG32(scratch);
2347 if (tmp == 0xDEADBEEF) {
2348 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
bbec97aa 2349 r = 0;
a2e73f56
AD		 2350 } else {
2351 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2352 scratch, tmp);
2353 r = -EINVAL;
2354 }
42d13693
CZ		 2355
2356err2:
cc55c45d 2357 amdgpu_ib_free(adev, &ib, NULL);
f54d1867 2358 dma_fence_put(f);
42d13693
CZ		 2359err1:
2360 amdgpu_gfx_scratch_free(adev, scratch);
a2e73f56
AD		 2361 return r;
2362}
2363
2364/*
2365 * CP.
2366 * On CIK, gfx and compute now have independant command processors.
2367 *
2368 * GFX
2369 * Gfx consists of a single ring and can process both gfx jobs and
2370 * compute jobs. The gfx CP consists of three microengines (ME):
2371 * PFP - Pre-Fetch Parser
2372 * ME - Micro Engine
2373 * CE - Constant Engine
2374 * The PFP and ME make up what is considered the Drawing Engine (DE).
2375 * The CE is an asynchronous engine used for updating buffer desciptors
2376 * used by the DE so that they can be loaded into cache in parallel
2377 * while the DE is processing state update packets.
2378 *
2379 * Compute
2380 * The compute CP consists of two microengines (ME):
2381 * MEC1 - Compute MicroEngine 1
2382 * MEC2 - Compute MicroEngine 2
2383 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2384 * The queues are exposed to userspace and are programmed directly
2385 * by the compute runtime.
2386 */
2387/**
2388 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2389 *
2390 * @adev: amdgpu_device pointer
2391 * @enable: enable or disable the MEs
2392 *
2393 * Halts or unhalts the gfx MEs.
2394 */
2395static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2396{
2397 int i;
2398
2399 if (enable) {
2400 WREG32(mmCP_ME_CNTL, 0);
2401 } else {
2402 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2403 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2404 adev->gfx.gfx_ring[i].ready = false;
2405 }
2406 udelay(50);
2407}
2408
2409/**
2410 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2411 *
2412 * @adev: amdgpu_device pointer
2413 *
2414 * Loads the gfx PFP, ME, and CE ucode.
2415 * Returns 0 for success, -EINVAL if the ucode is not available.
2416 */
2417static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2418{
2419 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2420 const struct gfx_firmware_header_v1_0 *ce_hdr;
2421 const struct gfx_firmware_header_v1_0 *me_hdr;
2422 const __le32 *fw_data;
2423 unsigned i, fw_size;
2424
2425 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2426 return -EINVAL;
2427
2428 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2429 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2430 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2431
2432 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2433 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2434 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2435 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2436 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2437 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
02558a00
KW		 2438 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2439 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2440 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
a2e73f56
AD		 2441
2442 gfx_v7_0_cp_gfx_enable(adev, false);
2443
2444 /* PFP */
2445 fw_data = (const __le32 *)
2446 (adev->gfx.pfp_fw->data +
2447 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2448 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2449 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2450 for (i = 0; i < fw_size; i++)
2451 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2452 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2453
2454 /* CE */
2455 fw_data = (const __le32 *)
2456 (adev->gfx.ce_fw->data +
2457 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2458 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2459 WREG32(mmCP_CE_UCODE_ADDR, 0);
2460 for (i = 0; i < fw_size; i++)
2461 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2462 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2463
2464 /* ME */
2465 fw_data = (const __le32 *)
2466 (adev->gfx.me_fw->data +
2467 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2468 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2469 WREG32(mmCP_ME_RAM_WADDR, 0);
2470 for (i = 0; i < fw_size; i++)
2471 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2472 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2473
2474 return 0;
2475}
2476
2477/**
2478 * gfx_v7_0_cp_gfx_start - start the gfx ring
2479 *
2480 * @adev: amdgpu_device pointer
2481 *
2482 * Enables the ring and loads the clear state context and other
2483 * packets required to init the ring.
2484 * Returns 0 for success, error for failure.
2485 */
2486static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2487{
2488 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2489 const struct cs_section_def *sect = NULL;
2490 const struct cs_extent_def *ext = NULL;
2491 int r, i;
2492
2493 /* init the CP */
2494 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2495 WREG32(mmCP_ENDIAN_SWAP, 0);
2496 WREG32(mmCP_DEVICE_ID, 1);
2497
2498 gfx_v7_0_cp_gfx_enable(adev, true);
2499
a27de35c 2500 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
a2e73f56
AD		 2501 if (r) {
2502 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2503 return r;
2504 }
2505
2506 /* init the CE partitions. CE only used for gfx on CIK */
2507 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2508 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2509 amdgpu_ring_write(ring, 0x8000);
2510 amdgpu_ring_write(ring, 0x8000);
2511
2512 /* clear state buffer */
2513 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2514 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2515
2516 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2517 amdgpu_ring_write(ring, 0x80000000);
2518 amdgpu_ring_write(ring, 0x80000000);
2519
2520 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2521 for (ext = sect->section; ext->extent != NULL; ++ext) {
2522 if (sect->id == SECT_CONTEXT) {
2523 amdgpu_ring_write(ring,
2524 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2525 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2526 for (i = 0; i < ext->reg_count; i++)
2527 amdgpu_ring_write(ring, ext->extent[i]);
2528 }
2529 }
2530 }
2531
2532 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2533 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2534 switch (adev->asic_type) {
2535 case CHIP_BONAIRE:
2536 amdgpu_ring_write(ring, 0x16000012);
2537 amdgpu_ring_write(ring, 0x00000000);
2538 break;
2539 case CHIP_KAVERI:
2540 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2541 amdgpu_ring_write(ring, 0x00000000);
2542 break;
2543 case CHIP_KABINI:
2544 case CHIP_MULLINS:
2545 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2546 amdgpu_ring_write(ring, 0x00000000);
2547 break;
2548 case CHIP_HAWAII:
2549 amdgpu_ring_write(ring, 0x3a00161a);
2550 amdgpu_ring_write(ring, 0x0000002e);
2551 break;
2552 default:
2553 amdgpu_ring_write(ring, 0x00000000);
2554 amdgpu_ring_write(ring, 0x00000000);
2555 break;
2556 }
2557
2558 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2559 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2560
2561 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2562 amdgpu_ring_write(ring, 0);
2563
2564 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2565 amdgpu_ring_write(ring, 0x00000316);
2566 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2567 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2568
a27de35c 2569 amdgpu_ring_commit(ring);
a2e73f56
AD		 2570
2571 return 0;
2572}
2573
2574/**
2575 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2576 *
2577 * @adev: amdgpu_device pointer
2578 *
2579 * Program the location and size of the gfx ring buffer
2580 * and test it to make sure it's working.
2581 * Returns 0 for success, error for failure.
2582 */
2583static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2584{
2585 struct amdgpu_ring *ring;
2586 u32 tmp;
2587 u32 rb_bufsz;
2588 u64 rb_addr, rptr_addr;
2589 int r;
2590
2591 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2592 if (adev->asic_type != CHIP_HAWAII)
2593 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2594
2595 /* Set the write pointer delay */
2596 WREG32(mmCP_RB_WPTR_DELAY, 0);
2597
2598 /* set the RB to use vmid 0 */
2599 WREG32(mmCP_RB_VMID, 0);
2600
2601 WREG32(mmSCRATCH_ADDR, 0);
2602
2603 /* ring 0 - compute and gfx */
2604 /* Set ring buffer size */
2605 ring = &adev->gfx.gfx_ring[0];
2606 rb_bufsz = order_base_2(ring->ring_size / 8);
2607 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2608#ifdef __BIG_ENDIAN
454fc95e 2609 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
a2e73f56
AD		 2610#endif
2611 WREG32(mmCP_RB0_CNTL, tmp);
2612
2613 /* Initialize the ring buffer's read and write pointers */
2614 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2615 ring->wptr = 0;
2616 WREG32(mmCP_RB0_WPTR, ring->wptr);
2617
2618 /* set the wb address wether it's enabled or not */
2619 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2620 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2621 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2622
2623 /* scratch register shadowing is no longer supported */
2624 WREG32(mmSCRATCH_UMSK, 0);
2625
2626 mdelay(1);
2627 WREG32(mmCP_RB0_CNTL, tmp);
2628
2629 rb_addr = ring->gpu_addr >> 8;
2630 WREG32(mmCP_RB0_BASE, rb_addr);
2631 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2632
2633 /* start the ring */
2634 gfx_v7_0_cp_gfx_start(adev);
2635 ring->ready = true;
2636 r = amdgpu_ring_test_ring(ring);
2637 if (r) {
2638 ring->ready = false;
2639 return r;
2640 }
2641
2642 return 0;
2643}
2644
f1c0efc5 2645static u32 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
a2e73f56 2646{
7edd6b2f 2647 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2648}
2649
2650static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2651{
2652 struct amdgpu_device *adev = ring->adev;
a2e73f56 2653
7edd6b2f 2654 return RREG32(mmCP_RB0_WPTR);
a2e73f56
AD		 2655}
2656
2657static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2658{
2659 struct amdgpu_device *adev = ring->adev;
2660
2661 WREG32(mmCP_RB0_WPTR, ring->wptr);
2662 (void)RREG32(mmCP_RB0_WPTR);
2663}
2664
a2e73f56
AD		 2665static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2666{
a2e73f56 2667 /* XXX check if swapping is necessary on BE */
7edd6b2f 2668 return ring->adev->wb.wb[ring->wptr_offs];
a2e73f56
AD		 2669}
2670
2671static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2672{
2673 struct amdgpu_device *adev = ring->adev;
2674
2675 /* XXX check if swapping is necessary on BE */
2676 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2677 WDOORBELL32(ring->doorbell_index, ring->wptr);
2678}
2679
2680/**
2681 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2682 *
2683 * @adev: amdgpu_device pointer
2684 * @enable: enable or disable the MEs
2685 *
2686 * Halts or unhalts the compute MEs.
2687 */
2688static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2689{
2690 int i;
2691
2692 if (enable) {
2693 WREG32(mmCP_MEC_CNTL, 0);
2694 } else {
2695 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2696 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2697 adev->gfx.compute_ring[i].ready = false;
2698 }
2699 udelay(50);
2700}
2701
2702/**
2703 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2704 *
2705 * @adev: amdgpu_device pointer
2706 *
2707 * Loads the compute MEC1&2 ucode.
2708 * Returns 0 for success, -EINVAL if the ucode is not available.
2709 */
2710static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2711{
2712 const struct gfx_firmware_header_v1_0 *mec_hdr;
2713 const __le32 *fw_data;
2714 unsigned i, fw_size;
2715
2716 if (!adev->gfx.mec_fw)
2717 return -EINVAL;
2718
2719 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2720 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2721 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
351643d7
JZ		 2722 adev->gfx.mec_feature_version = le32_to_cpu(
2723 mec_hdr->ucode_feature_version);
a2e73f56
AD		 2724
2725 gfx_v7_0_cp_compute_enable(adev, false);
2726
2727 /* MEC1 */
2728 fw_data = (const __le32 *)
2729 (adev->gfx.mec_fw->data +
2730 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2731 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2732 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2733 for (i = 0; i < fw_size; i++)
2734 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2735 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2736
2737 if (adev->asic_type == CHIP_KAVERI) {
2738 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2739
2740 if (!adev->gfx.mec2_fw)
2741 return -EINVAL;
2742
2743 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2744 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2745 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
351643d7
JZ		 2746 adev->gfx.mec2_feature_version = le32_to_cpu(
2747 mec2_hdr->ucode_feature_version);
a2e73f56
AD		 2748
2749 /* MEC2 */
2750 fw_data = (const __le32 *)
2751 (adev->gfx.mec2_fw->data +
2752 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2753 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2754 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2755 for (i = 0; i < fw_size; i++)
2756 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2757 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2758 }
2759
2760 return 0;
2761}
2762
a2e73f56
AD		 2763/**
2764 * gfx_v7_0_cp_compute_fini - stop the compute queues
2765 *
2766 * @adev: amdgpu_device pointer
2767 *
2768 * Stop the compute queues and tear down the driver queue
2769 * info.
2770 */
2771static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2772{
2773 int i, r;
2774
2775 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2776 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2777
2778 if (ring->mqd_obj) {
2779 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2780 if (unlikely(r != 0))
2781 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2782
2783 amdgpu_bo_unpin(ring->mqd_obj);
2784 amdgpu_bo_unreserve(ring->mqd_obj);
2785
2786 amdgpu_bo_unref(&ring->mqd_obj);
2787 ring->mqd_obj = NULL;
2788 }
2789 }
2790}
2791
2792static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2793{
2794 int r;
2795
2796 if (adev->gfx.mec.hpd_eop_obj) {
2797 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2798 if (unlikely(r != 0))
2799 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2800 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2801 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2802
2803 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2804 adev->gfx.mec.hpd_eop_obj = NULL;
2805 }
2806}
2807
2808#define MEC_HPD_SIZE 2048
2809
2810static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2811{
2812 int r;
2813 u32 *hpd;
2814
2815 /*
2816 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2817 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2818 * Nonetheless, we assign only 1 pipe because all other pipes will
2819 * be handled by KFD
2820 */
2821 adev->gfx.mec.num_mec = 1;
2822 adev->gfx.mec.num_pipe = 1;
2823 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2824
2825 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2826 r = amdgpu_bo_create(adev,
2827 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2828 PAGE_SIZE, true,
72d7668b 2829 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2830 &adev->gfx.mec.hpd_eop_obj);
2831 if (r) {
2832 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2833 return r;
2834 }
2835 }
2836
2837 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2838 if (unlikely(r != 0)) {
2839 gfx_v7_0_mec_fini(adev);
2840 return r;
2841 }
2842 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2843 &adev->gfx.mec.hpd_eop_gpu_addr);
2844 if (r) {
2845 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2846 gfx_v7_0_mec_fini(adev);
2847 return r;
2848 }
2849 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2850 if (r) {
2851 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2852 gfx_v7_0_mec_fini(adev);
2853 return r;
2854 }
2855
2856 /* clear memory. Not sure if this is required or not */
2857 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2858
2859 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2860 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2861
2862 return 0;
2863}
2864
2865struct hqd_registers
2866{
2867 u32 cp_mqd_base_addr;
2868 u32 cp_mqd_base_addr_hi;
2869 u32 cp_hqd_active;
2870 u32 cp_hqd_vmid;
2871 u32 cp_hqd_persistent_state;
2872 u32 cp_hqd_pipe_priority;
2873 u32 cp_hqd_queue_priority;
2874 u32 cp_hqd_quantum;
2875 u32 cp_hqd_pq_base;
2876 u32 cp_hqd_pq_base_hi;
2877 u32 cp_hqd_pq_rptr;
2878 u32 cp_hqd_pq_rptr_report_addr;
2879 u32 cp_hqd_pq_rptr_report_addr_hi;
2880 u32 cp_hqd_pq_wptr_poll_addr;
2881 u32 cp_hqd_pq_wptr_poll_addr_hi;
2882 u32 cp_hqd_pq_doorbell_control;
2883 u32 cp_hqd_pq_wptr;
2884 u32 cp_hqd_pq_control;
2885 u32 cp_hqd_ib_base_addr;
2886 u32 cp_hqd_ib_base_addr_hi;
2887 u32 cp_hqd_ib_rptr;
2888 u32 cp_hqd_ib_control;
2889 u32 cp_hqd_iq_timer;
2890 u32 cp_hqd_iq_rptr;
2891 u32 cp_hqd_dequeue_request;
2892 u32 cp_hqd_dma_offload;
2893 u32 cp_hqd_sema_cmd;
2894 u32 cp_hqd_msg_type;
2895 u32 cp_hqd_atomic0_preop_lo;
2896 u32 cp_hqd_atomic0_preop_hi;
2897 u32 cp_hqd_atomic1_preop_lo;
2898 u32 cp_hqd_atomic1_preop_hi;
2899 u32 cp_hqd_hq_scheduler0;
2900 u32 cp_hqd_hq_scheduler1;
2901 u32 cp_mqd_control;
2902};
2903
2904struct bonaire_mqd
2905{
2906 u32 header;
2907 u32 dispatch_initiator;
2908 u32 dimensions[3];
2909 u32 start_idx[3];
2910 u32 num_threads[3];
2911 u32 pipeline_stat_enable;
2912 u32 perf_counter_enable;
2913 u32 pgm[2];
2914 u32 tba[2];
2915 u32 tma[2];
2916 u32 pgm_rsrc[2];
2917 u32 vmid;
2918 u32 resource_limits;
2919 u32 static_thread_mgmt01[2];
2920 u32 tmp_ring_size;
2921 u32 static_thread_mgmt23[2];
2922 u32 restart[3];
2923 u32 thread_trace_enable;
2924 u32 reserved1;
2925 u32 user_data[16];
2926 u32 vgtcs_invoke_count[2];
2927 struct hqd_registers queue_state;
2928 u32 dequeue_cntr;
2929 u32 interrupt_queue[64];
2930};
2931
2932/**
2933 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2934 *
2935 * @adev: amdgpu_device pointer
2936 *
2937 * Program the compute queues and test them to make sure they
2938 * are working.
2939 * Returns 0 for success, error for failure.
2940 */
2941static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2942{
2943 int r, i, j;
2944 u32 tmp;
2945 bool use_doorbell = true;
2946 u64 hqd_gpu_addr;
2947 u64 mqd_gpu_addr;
2948 u64 eop_gpu_addr;
2949 u64 wb_gpu_addr;
2950 u32 *buf;
2951 struct bonaire_mqd *mqd;
53960b4f 2952 struct amdgpu_ring *ring;
a2e73f56
AD		 2953
2954 /* fix up chicken bits */
2955 tmp = RREG32(mmCP_CPF_DEBUG);
2956 tmp |= (1 << 23);
2957 WREG32(mmCP_CPF_DEBUG, tmp);
2958
2959 /* init the pipes */
2960 mutex_lock(&adev->srbm_mutex);
2961 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2962 int me = (i < 4) ? 1 : 2;
2963 int pipe = (i < 4) ? i : (i - 4);
2964
2965 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2966
2967 cik_srbm_select(adev, me, pipe, 0, 0);
2968
2969 /* write the EOP addr */
2970 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2971 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2972
2973 /* set the VMID assigned */
2974 WREG32(mmCP_HPD_EOP_VMID, 0);
2975
2976 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2977 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2978 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2979 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2980 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2981 }
2982 cik_srbm_select(adev, 0, 0, 0, 0);
2983 mutex_unlock(&adev->srbm_mutex);
2984
2985 /* init the queues. Just two for now. */
2986 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
53960b4f 2987 ring = &adev->gfx.compute_ring[i];
a2e73f56
AD		 2988
2989 if (ring->mqd_obj == NULL) {
2990 r = amdgpu_bo_create(adev,
2991 sizeof(struct bonaire_mqd),
2992 PAGE_SIZE, true,
72d7668b 2993 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2994 &ring->mqd_obj);
2995 if (r) {
2996 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2997 return r;
2998 }
2999 }
3000
3001 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3002 if (unlikely(r != 0)) {
3003 gfx_v7_0_cp_compute_fini(adev);
3004 return r;
3005 }
3006 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3007 &mqd_gpu_addr);
3008 if (r) {
3009 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3010 gfx_v7_0_cp_compute_fini(adev);
3011 return r;
3012 }
3013 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3014 if (r) {
3015 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3016 gfx_v7_0_cp_compute_fini(adev);
3017 return r;
3018 }
3019
3020 /* init the mqd struct */
3021 memset(buf, 0, sizeof(struct bonaire_mqd));
3022
3023 mqd = (struct bonaire_mqd *)buf;
3024 mqd->header = 0xC0310800;
3025 mqd->static_thread_mgmt01[0] = 0xffffffff;
3026 mqd->static_thread_mgmt01[1] = 0xffffffff;
3027 mqd->static_thread_mgmt23[0] = 0xffffffff;
3028 mqd->static_thread_mgmt23[1] = 0xffffffff;
3029
3030 mutex_lock(&adev->srbm_mutex);
3031 cik_srbm_select(adev, ring->me,
3032 ring->pipe,
3033 ring->queue, 0);
3034
3035 /* disable wptr polling */
3036 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3037 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
3038 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3039
3040 /* enable doorbell? */
3041 mqd->queue_state.cp_hqd_pq_doorbell_control =
3042 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3043 if (use_doorbell)
3044 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3045 else
3046 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3047 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3048 mqd->queue_state.cp_hqd_pq_doorbell_control);
3049
3050 /* disable the queue if it's active */
3051 mqd->queue_state.cp_hqd_dequeue_request = 0;
3052 mqd->queue_state.cp_hqd_pq_rptr = 0;
3053 mqd->queue_state.cp_hqd_pq_wptr= 0;
3054 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3055 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3056 for (j = 0; j < adev->usec_timeout; j++) {
3057 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3058 break;
3059 udelay(1);
3060 }
3061 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
3062 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
3063 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3064 }
3065
3066 /* set the pointer to the MQD */
3067 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
3068 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3069 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
3070 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
3071 /* set MQD vmid to 0 */
3072 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
3073 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
3074 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
3075
3076 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3077 hqd_gpu_addr = ring->gpu_addr >> 8;
3078 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
3079 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3080 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
3081 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
3082
3083 /* set up the HQD, this is similar to CP_RB0_CNTL */
3084 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
3085 mqd->queue_state.cp_hqd_pq_control &=
3086 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
3087 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
3088
3089 mqd->queue_state.cp_hqd_pq_control |=
3090 order_base_2(ring->ring_size / 8);
3091 mqd->queue_state.cp_hqd_pq_control |=
3092 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
3093#ifdef __BIG_ENDIAN
454fc95e
AD		 3094 mqd->queue_state.cp_hqd_pq_control |=
3095 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
a2e73f56
AD		 3096#endif
3097 mqd->queue_state.cp_hqd_pq_control &=
3098 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
3099 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
3100 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
3101 mqd->queue_state.cp_hqd_pq_control |=
3102 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
3103 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
3104 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
3105
3106 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3107 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3108 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3109 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3110 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
3111 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3112 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
3113
3114 /* set the wb address wether it's enabled or not */
3115 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3116 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
3117 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
3118 upper_32_bits(wb_gpu_addr) & 0xffff;
3119 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3120 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
3121 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3122 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
3123
3124 /* enable the doorbell if requested */
3125 if (use_doorbell) {
3126 mqd->queue_state.cp_hqd_pq_doorbell_control =
3127 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3128 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3129 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
3130 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3131 (ring->doorbell_index <<
3132 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
3133 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3134 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3135 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3136 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3137 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3138
3139 } else {
3140 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
3141 }
3142 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3143 mqd->queue_state.cp_hqd_pq_doorbell_control);
3144
3145 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3146 ring->wptr = 0;
3147 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
3148 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3149 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3150
3151 /* set the vmid for the queue */
3152 mqd->queue_state.cp_hqd_vmid = 0;
3153 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
3154
3155 /* activate the queue */
3156 mqd->queue_state.cp_hqd_active = 1;
3157 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
3158
3159 cik_srbm_select(adev, 0, 0, 0, 0);
3160 mutex_unlock(&adev->srbm_mutex);
3161
3162 amdgpu_bo_kunmap(ring->mqd_obj);
3163 amdgpu_bo_unreserve(ring->mqd_obj);
3164
3165 ring->ready = true;
53960b4f 3166 }
3167
3168 gfx_v7_0_cp_compute_enable(adev, true);
3169
3170 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3171 ring = &adev->gfx.compute_ring[i];
3172
a2e73f56
AD		 3173 r = amdgpu_ring_test_ring(ring);
3174 if (r)
3175 ring->ready = false;
3176 }
3177
3178 return 0;
3179}
3180
3181static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3182{
3183 gfx_v7_0_cp_gfx_enable(adev, enable);
3184 gfx_v7_0_cp_compute_enable(adev, enable);
3185}
3186
3187static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3188{
3189 int r;
3190
3191 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3192 if (r)
3193 return r;
3194 r = gfx_v7_0_cp_compute_load_microcode(adev);
3195 if (r)
3196 return r;
3197
3198 return 0;
3199}
3200
3201static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3202 bool enable)
3203{
3204 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3205
3206 if (enable)
3207 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3208 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3209 else
3210 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3211 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3212 WREG32(mmCP_INT_CNTL_RING0, tmp);
3213}
3214
3215static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3216{
3217 int r;
3218
3219 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3220
3221 r = gfx_v7_0_cp_load_microcode(adev);
3222 if (r)
3223 return r;
3224
3225 r = gfx_v7_0_cp_gfx_resume(adev);
3226 if (r)
3227 return r;
3228 r = gfx_v7_0_cp_compute_resume(adev);
3229 if (r)
3230 return r;
3231
3232 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3233
3234 return 0;
3235}
3236
b8c7b39e
CK		 3237/**
3238 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3239 *
3240 * @ring: the ring to emmit the commands to
3241 *
3242 * Sync the command pipeline with the PFP. E.g. wait for everything
3243 * to be completed.
3244 */
3245static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3246{
21cd942e 3247 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
914f9e18
CZ		 3248 uint32_t seq = ring->fence_drv.sync_seq;
3249 uint64_t addr = ring->fence_drv.gpu_addr;
3250
3251 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3252 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3253 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3254 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3255 amdgpu_ring_write(ring, addr & 0xfffffffc);
3256 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3257 amdgpu_ring_write(ring, seq);
3258 amdgpu_ring_write(ring, 0xffffffff);
3259 amdgpu_ring_write(ring, 4); /* poll interval */
3260
b8c7b39e
CK		 3261 if (usepfp) {
3262 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3263 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3264 amdgpu_ring_write(ring, 0);
3265 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3266 amdgpu_ring_write(ring, 0);
3267 }
3268}
3269
a2e73f56
AD		 3270/*
3271 * vm
3272 * VMID 0 is the physical GPU addresses as used by the kernel.
3273 * VMIDs 1-15 are used for userspace clients and are handled
3274 * by the amdgpu vm/hsa code.
3275 */
3276/**
3277 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3278 *
3279 * @adev: amdgpu_device pointer
3280 *
3281 * Update the page table base and flush the VM TLB
3282 * using the CP (CIK).
3283 */
3284static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3285 unsigned vm_id, uint64_t pd_addr)
3286{
21cd942e 3287 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
feebe91a 3288
a2e73f56
AD		 3289 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3290 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3291 WRITE_DATA_DST_SEL(0)));
3292 if (vm_id < 8) {
3293 amdgpu_ring_write(ring,
3294 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3295 } else {
3296 amdgpu_ring_write(ring,
3297 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3298 }
3299 amdgpu_ring_write(ring, 0);
3300 amdgpu_ring_write(ring, pd_addr >> 12);
3301
a2e73f56
AD		 3302 /* bits 0-15 are the VM contexts0-15 */
3303 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3304 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3305 WRITE_DATA_DST_SEL(0)));
3306 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3307 amdgpu_ring_write(ring, 0);
3308 amdgpu_ring_write(ring, 1 << vm_id);
3309
3310 /* wait for the invalidate to complete */
3311 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3312 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3313 WAIT_REG_MEM_FUNCTION(0) | /* always */
3314 WAIT_REG_MEM_ENGINE(0))); /* me */
3315 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3316 amdgpu_ring_write(ring, 0);
3317 amdgpu_ring_write(ring, 0); /* ref */
3318 amdgpu_ring_write(ring, 0); /* mask */
3319 amdgpu_ring_write(ring, 0x20); /* poll interval */
3320
3321 /* compute doesn't have PFP */
3322 if (usepfp) {
3323 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3324 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3325 amdgpu_ring_write(ring, 0x0);
3326
3327 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
5c3422b0 3328 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3329 amdgpu_ring_write(ring, 0);
3330 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3331 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 3332 }
3333}
3334
3335/*
3336 * RLC
3337 * The RLC is a multi-purpose microengine that handles a
3338 * variety of functions.
3339 */
3340static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3341{
3342 int r;
3343
3344 /* save restore block */
3345 if (adev->gfx.rlc.save_restore_obj) {
3346 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3347 if (unlikely(r != 0))
3348 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3349 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3350 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3351
3352 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3353 adev->gfx.rlc.save_restore_obj = NULL;
3354 }
3355
3356 /* clear state block */
3357 if (adev->gfx.rlc.clear_state_obj) {
3358 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3359 if (unlikely(r != 0))
3360 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3361 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3362 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3363
3364 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3365 adev->gfx.rlc.clear_state_obj = NULL;
3366 }
3367
3368 /* clear state block */
3369 if (adev->gfx.rlc.cp_table_obj) {
3370 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3371 if (unlikely(r != 0))
3372 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3373 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3374 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3375
3376 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3377 adev->gfx.rlc.cp_table_obj = NULL;
3378 }
3379}
3380
3381static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3382{
3383 const u32 *src_ptr;
3384 volatile u32 *dst_ptr;
3385 u32 dws, i;
3386 const struct cs_section_def *cs_data;
3387 int r;
3388
3389 /* allocate rlc buffers */
2f7d10b3 3390 if (adev->flags & AMD_IS_APU) {
a2e73f56
AD		 3391 if (adev->asic_type == CHIP_KAVERI) {
3392 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3393 adev->gfx.rlc.reg_list_size =
3394 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3395 } else {
3396 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3397 adev->gfx.rlc.reg_list_size =
3398 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3399 }
3400 }
3401 adev->gfx.rlc.cs_data = ci_cs_data;
b58bc559 3402 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
e36091ed 3403 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
a2e73f56
AD		 3404
3405 src_ptr = adev->gfx.rlc.reg_list;
3406 dws = adev->gfx.rlc.reg_list_size;
3407 dws += (5 * 16) + 48 + 48 + 64;
3408
3409 cs_data = adev->gfx.rlc.cs_data;
3410
3411 if (src_ptr) {
3412 /* save restore block */
3413 if (adev->gfx.rlc.save_restore_obj == NULL) {
3414 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d 3415 AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5
CK		 3416 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3417 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
72d7668b
CK		 3418 NULL, NULL,
3419 &adev->gfx.rlc.save_restore_obj);
a2e73f56
AD		 3420 if (r) {
3421 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3422 return r;
3423 }
3424 }
3425
3426 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3427 if (unlikely(r != 0)) {
3428 gfx_v7_0_rlc_fini(adev);
3429 return r;
3430 }
3431 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3432 &adev->gfx.rlc.save_restore_gpu_addr);
3433 if (r) {
3434 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3435 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3436 gfx_v7_0_rlc_fini(adev);
3437 return r;
3438 }
3439
3440 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3441 if (r) {
3442 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3443 gfx_v7_0_rlc_fini(adev);
3444 return r;
3445 }
3446 /* write the sr buffer */
3447 dst_ptr = adev->gfx.rlc.sr_ptr;
3448 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3449 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3450 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3451 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3452 }
3453
3454 if (cs_data) {
3455 /* clear state block */
3456 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3457
3458 if (adev->gfx.rlc.clear_state_obj == NULL) {
3459 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d 3460 AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5
CK		 3461 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3462 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
72d7668b
CK		 3463 NULL, NULL,
3464 &adev->gfx.rlc.clear_state_obj);
a2e73f56
AD		 3465 if (r) {
3466 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3467 gfx_v7_0_rlc_fini(adev);
3468 return r;
3469 }
3470 }
3471 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3472 if (unlikely(r != 0)) {
3473 gfx_v7_0_rlc_fini(adev);
3474 return r;
3475 }
3476 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3477 &adev->gfx.rlc.clear_state_gpu_addr);
3478 if (r) {
3479 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3480 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3481 gfx_v7_0_rlc_fini(adev);
3482 return r;
3483 }
3484
3485 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3486 if (r) {
3487 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3488 gfx_v7_0_rlc_fini(adev);
3489 return r;
3490 }
3491 /* set up the cs buffer */
3492 dst_ptr = adev->gfx.rlc.cs_ptr;
3493 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3494 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3495 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3496 }
3497
3498 if (adev->gfx.rlc.cp_table_size) {
3499 if (adev->gfx.rlc.cp_table_obj == NULL) {
3500 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
857d913d 3501 AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5
CK		 3502 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3503 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
72d7668b
CK		 3504 NULL, NULL,
3505 &adev->gfx.rlc.cp_table_obj);
a2e73f56
AD		 3506 if (r) {
3507 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3508 gfx_v7_0_rlc_fini(adev);
3509 return r;
3510 }
3511 }
3512
3513 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3514 if (unlikely(r != 0)) {
3515 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3516 gfx_v7_0_rlc_fini(adev);
3517 return r;
3518 }
3519 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3520 &adev->gfx.rlc.cp_table_gpu_addr);
3521 if (r) {
3522 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3523 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3524 gfx_v7_0_rlc_fini(adev);
3525 return r;
3526 }
3527 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3528 if (r) {
3529 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3530 gfx_v7_0_rlc_fini(adev);
3531 return r;
3532 }
3533
3534 gfx_v7_0_init_cp_pg_table(adev);
3535
3536 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3537 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3538
3539 }
3540
3541 return 0;
3542}
3543
3544static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3545{
3546 u32 tmp;
3547
3548 tmp = RREG32(mmRLC_LB_CNTL);
3549 if (enable)
3550 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3551 else
3552 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3553 WREG32(mmRLC_LB_CNTL, tmp);
3554}
3555
3556static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3557{
3558 u32 i, j, k;
3559 u32 mask;
3560
3561 mutex_lock(&adev->grbm_idx_mutex);
3562 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3563 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9559ef5b 3564 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
a2e73f56
AD		 3565 for (k = 0; k < adev->usec_timeout; k++) {
3566 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3567 break;
3568 udelay(1);
3569 }
3570 }
3571 }
9559ef5b 3572 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3573 mutex_unlock(&adev->grbm_idx_mutex);
3574
3575 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3576 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3577 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3578 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3579 for (k = 0; k < adev->usec_timeout; k++) {
3580 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3581 break;
3582 udelay(1);
3583 }
3584}
3585
3586static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3587{
3588 u32 tmp;
3589
3590 tmp = RREG32(mmRLC_CNTL);
3591 if (tmp != rlc)
3592 WREG32(mmRLC_CNTL, rlc);
3593}
3594
3595static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3596{
3597 u32 data, orig;
3598
3599 orig = data = RREG32(mmRLC_CNTL);
3600
3601 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3602 u32 i;
3603
3604 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3605 WREG32(mmRLC_CNTL, data);
3606
3607 for (i = 0; i < adev->usec_timeout; i++) {
3608 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3609 break;
3610 udelay(1);
3611 }
3612
3613 gfx_v7_0_wait_for_rlc_serdes(adev);
3614 }
3615
3616 return orig;
3617}
3618
06120a1e 3619static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
a2e73f56
AD		 3620{
3621 u32 tmp, i, mask;
3622
3623 tmp = 0x1 | (1 << 1);
3624 WREG32(mmRLC_GPR_REG2, tmp);
3625
3626 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3627 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3628 for (i = 0; i < adev->usec_timeout; i++) {
3629 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3630 break;
3631 udelay(1);
3632 }
3633
3634 for (i = 0; i < adev->usec_timeout; i++) {
3635 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3636 break;
3637 udelay(1);
3638 }
3639}
3640
06120a1e 3641static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
a2e73f56
AD		 3642{
3643 u32 tmp;
3644
3645 tmp = 0x1 | (0 << 1);
3646 WREG32(mmRLC_GPR_REG2, tmp);
3647}
3648
3649/**
3650 * gfx_v7_0_rlc_stop - stop the RLC ME
3651 *
3652 * @adev: amdgpu_device pointer
3653 *
3654 * Halt the RLC ME (MicroEngine) (CIK).
3655 */
4d54588e 3656static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
a2e73f56
AD		 3657{
3658 WREG32(mmRLC_CNTL, 0);
3659
3660 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3661
3662 gfx_v7_0_wait_for_rlc_serdes(adev);
3663}
3664
3665/**
3666 * gfx_v7_0_rlc_start - start the RLC ME
3667 *
3668 * @adev: amdgpu_device pointer
3669 *
3670 * Unhalt the RLC ME (MicroEngine) (CIK).
3671 */
3672static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3673{
3674 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3675
3676 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3677
3678 udelay(50);
3679}
3680
3681static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3682{
3683 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3684
3685 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3686 WREG32(mmGRBM_SOFT_RESET, tmp);
3687 udelay(50);
3688 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3689 WREG32(mmGRBM_SOFT_RESET, tmp);
3690 udelay(50);
3691}
3692
3693/**
3694 * gfx_v7_0_rlc_resume - setup the RLC hw
3695 *
3696 * @adev: amdgpu_device pointer
3697 *
3698 * Initialize the RLC registers, load the ucode,
3699 * and start the RLC (CIK).
3700 * Returns 0 for success, -EINVAL if the ucode is not available.
3701 */
3702static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3703{
3704 const struct rlc_firmware_header_v1_0 *hdr;
3705 const __le32 *fw_data;
3706 unsigned i, fw_size;
3707 u32 tmp;
3708
3709 if (!adev->gfx.rlc_fw)
3710 return -EINVAL;
3711
3712 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3713 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3714 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
351643d7
JZ		 3715 adev->gfx.rlc_feature_version = le32_to_cpu(
3716 hdr->ucode_feature_version);
a2e73f56
AD		 3717
3718 gfx_v7_0_rlc_stop(adev);
3719
3720 /* disable CG */
3721 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3722 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3723
3724 gfx_v7_0_rlc_reset(adev);
3725
3726 gfx_v7_0_init_pg(adev);
3727
3728 WREG32(mmRLC_LB_CNTR_INIT, 0);
3729 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3730
3731 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3732 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3733 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3734 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3735 WREG32(mmRLC_LB_CNTL, 0x80000004);
3736 mutex_unlock(&adev->grbm_idx_mutex);
3737
3738 WREG32(mmRLC_MC_CNTL, 0);
3739 WREG32(mmRLC_UCODE_CNTL, 0);
3740
3741 fw_data = (const __le32 *)
3742 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3743 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3744 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3745 for (i = 0; i < fw_size; i++)
3746 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3747 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3748
3749 /* XXX - find out what chips support lbpw */
3750 gfx_v7_0_enable_lbpw(adev, false);
3751
3752 if (adev->asic_type == CHIP_BONAIRE)
3753 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3754
3755 gfx_v7_0_rlc_start(adev);
3756
3757 return 0;
3758}
3759
3760static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3761{
3762 u32 data, orig, tmp, tmp2;
3763
3764 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3765
e3b04bc7 3766 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
a2e73f56
AD		 3767 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3768
3769 tmp = gfx_v7_0_halt_rlc(adev);
3770
3771 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3772 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3773 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3774 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3775 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3776 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3777 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3778 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3779 mutex_unlock(&adev->grbm_idx_mutex);
3780
3781 gfx_v7_0_update_rlc(adev, tmp);
3782
3783 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3784 } else {
3785 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3786
3787 RREG32(mmCB_CGTT_SCLK_CTRL);
3788 RREG32(mmCB_CGTT_SCLK_CTRL);
3789 RREG32(mmCB_CGTT_SCLK_CTRL);
3790 RREG32(mmCB_CGTT_SCLK_CTRL);
3791
3792 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3793 }
3794
3795 if (orig != data)
3796 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3797
3798}
3799
3800static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3801{
3802 u32 data, orig, tmp = 0;
3803
e3b04bc7
AD		 3804 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3805 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3806 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
a2e73f56
AD		 3807 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3808 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3809 if (orig != data)
3810 WREG32(mmCP_MEM_SLP_CNTL, data);
3811 }
3812 }
3813
3814 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3815 data |= 0x00000001;
3816 data &= 0xfffffffd;
3817 if (orig != data)
3818 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3819
3820 tmp = gfx_v7_0_halt_rlc(adev);
3821
3822 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3823 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3824 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3825 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3826 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3827 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3828 WREG32(mmRLC_SERDES_WR_CTRL, data);
3829 mutex_unlock(&adev->grbm_idx_mutex);
3830
3831 gfx_v7_0_update_rlc(adev, tmp);
3832
e3b04bc7 3833 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
a2e73f56
AD		 3834 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3835 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3836 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3837 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3838 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
e3b04bc7
AD		 3839 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3840 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
a2e73f56
AD		 3841 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3842 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3843 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3844 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3845 if (orig != data)
3846 WREG32(mmCGTS_SM_CTRL_REG, data);
3847 }
3848 } else {
3849 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3850 data |= 0x00000003;
3851 if (orig != data)
3852 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3853
3854 data = RREG32(mmRLC_MEM_SLP_CNTL);
3855 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3856 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3857 WREG32(mmRLC_MEM_SLP_CNTL, data);
3858 }
3859
3860 data = RREG32(mmCP_MEM_SLP_CNTL);
3861 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3862 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3863 WREG32(mmCP_MEM_SLP_CNTL, data);
3864 }
3865
3866 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3867 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3868 if (orig != data)
3869 WREG32(mmCGTS_SM_CTRL_REG, data);
3870
3871 tmp = gfx_v7_0_halt_rlc(adev);
3872
3873 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3874 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3875 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3876 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3877 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3878 WREG32(mmRLC_SERDES_WR_CTRL, data);
3879 mutex_unlock(&adev->grbm_idx_mutex);
3880
3881 gfx_v7_0_update_rlc(adev, tmp);
3882 }
3883}
3884
3885static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3886 bool enable)
3887{
3888 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3889 /* order matters! */
3890 if (enable) {
3891 gfx_v7_0_enable_mgcg(adev, true);
3892 gfx_v7_0_enable_cgcg(adev, true);
3893 } else {
3894 gfx_v7_0_enable_cgcg(adev, false);
3895 gfx_v7_0_enable_mgcg(adev, false);
3896 }
3897 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3898}
3899
3900static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3901 bool enable)
3902{
3903 u32 data, orig;
3904
3905 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3906 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
a2e73f56
AD		 3907 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3908 else
3909 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3910 if (orig != data)
3911 WREG32(mmRLC_PG_CNTL, data);
3912}
3913
3914static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3915 bool enable)
3916{
3917 u32 data, orig;
3918
3919 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3920 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
a2e73f56
AD		 3921 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3922 else
3923 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3924 if (orig != data)
3925 WREG32(mmRLC_PG_CNTL, data);
3926}
3927
3928static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3929{
3930 u32 data, orig;
3931
3932 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3933 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
a2e73f56
AD		 3934 data &= ~0x8000;
3935 else
3936 data |= 0x8000;
3937 if (orig != data)
3938 WREG32(mmRLC_PG_CNTL, data);
3939}
3940
3941static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3942{
3943 u32 data, orig;
3944
3945 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3946 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
a2e73f56
AD		 3947 data &= ~0x2000;
3948 else
3949 data |= 0x2000;
3950 if (orig != data)
3951 WREG32(mmRLC_PG_CNTL, data);
3952}
3953
3954static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3955{
3956 const __le32 *fw_data;
3957 volatile u32 *dst_ptr;
3958 int me, i, max_me = 4;
3959 u32 bo_offset = 0;
3960 u32 table_offset, table_size;
3961
3962 if (adev->asic_type == CHIP_KAVERI)
3963 max_me = 5;
3964
3965 if (adev->gfx.rlc.cp_table_ptr == NULL)
3966 return;
3967
3968 /* write the cp table buffer */
3969 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3970 for (me = 0; me < max_me; me++) {
3971 if (me == 0) {
3972 const struct gfx_firmware_header_v1_0 *hdr =
3973 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3974 fw_data = (const __le32 *)
3975 (adev->gfx.ce_fw->data +
3976 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3977 table_offset = le32_to_cpu(hdr->jt_offset);
3978 table_size = le32_to_cpu(hdr->jt_size);
3979 } else if (me == 1) {
3980 const struct gfx_firmware_header_v1_0 *hdr =
3981 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3982 fw_data = (const __le32 *)
3983 (adev->gfx.pfp_fw->data +
3984 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3985 table_offset = le32_to_cpu(hdr->jt_offset);
3986 table_size = le32_to_cpu(hdr->jt_size);
3987 } else if (me == 2) {
3988 const struct gfx_firmware_header_v1_0 *hdr =
3989 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3990 fw_data = (const __le32 *)
3991 (adev->gfx.me_fw->data +
3992 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3993 table_offset = le32_to_cpu(hdr->jt_offset);
3994 table_size = le32_to_cpu(hdr->jt_size);
3995 } else if (me == 3) {
3996 const struct gfx_firmware_header_v1_0 *hdr =
3997 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3998 fw_data = (const __le32 *)
3999 (adev->gfx.mec_fw->data +
4000 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4001 table_offset = le32_to_cpu(hdr->jt_offset);
4002 table_size = le32_to_cpu(hdr->jt_size);
4003 } else {
4004 const struct gfx_firmware_header_v1_0 *hdr =
4005 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4006 fw_data = (const __le32 *)
4007 (adev->gfx.mec2_fw->data +
4008 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4009 table_offset = le32_to_cpu(hdr->jt_offset);
4010 table_size = le32_to_cpu(hdr->jt_size);
4011 }
4012
4013 for (i = 0; i < table_size; i ++) {
4014 dst_ptr[bo_offset + i] =
4015 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
4016 }
4017
4018 bo_offset += table_size;
4019 }
4020}
4021
4022static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
4023 bool enable)
4024{
4025 u32 data, orig;
4026
e3b04bc7 4027 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
a2e73f56
AD		 4028 orig = data = RREG32(mmRLC_PG_CNTL);
4029 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4030 if (orig != data)
4031 WREG32(mmRLC_PG_CNTL, data);
4032
4033 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4034 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4035 if (orig != data)
4036 WREG32(mmRLC_AUTO_PG_CTRL, data);
4037 } else {
4038 orig = data = RREG32(mmRLC_PG_CNTL);
4039 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4040 if (orig != data)
4041 WREG32(mmRLC_PG_CNTL, data);
4042
4043 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4044 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4045 if (orig != data)
4046 WREG32(mmRLC_AUTO_PG_CTRL, data);
4047
4048 data = RREG32(mmDB_RENDER_CONTROL);
4049 }
4050}
4051
324c614a
NH		 4052static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4053 u32 bitmap)
4054{
4055 u32 data;
4056
4057 if (!bitmap)
4058 return;
4059
4060 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4061 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4062
4063 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
4064}
4065
8f8e00c1 4066static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
a2e73f56 4067{
8f8e00c1 4068 u32 data, mask;
a2e73f56 4069
8f8e00c1
AD		 4070 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4071 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
a2e73f56 4072
8f8e00c1
AD		 4073 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4074 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
a2e73f56 4075
6157bd7a 4076 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
a2e73f56 4077
8f8e00c1 4078 return (~data) & mask;
a2e73f56
AD		 4079}
4080
4081static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
4082{
7dae69a2 4083 u32 tmp;
a2e73f56 4084
7dae69a2 4085 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
a2e73f56
AD		 4086
4087 tmp = RREG32(mmRLC_MAX_PG_CU);
4088 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
7dae69a2 4089 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
a2e73f56
AD		 4090 WREG32(mmRLC_MAX_PG_CU, tmp);
4091}
4092
4093static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
4094 bool enable)
4095{
4096 u32 data, orig;
4097
4098 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 4099 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
a2e73f56
AD		 4100 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4101 else
4102 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4103 if (orig != data)
4104 WREG32(mmRLC_PG_CNTL, data);
4105}
4106
4107static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
4108 bool enable)
4109{
4110 u32 data, orig;
4111
4112 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 4113 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
a2e73f56
AD		 4114 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4115 else
4116 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4117 if (orig != data)
4118 WREG32(mmRLC_PG_CNTL, data);
4119}
4120
4121#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4122#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
4123
4124static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
4125{
4126 u32 data, orig;
4127 u32 i;
4128
4129 if (adev->gfx.rlc.cs_data) {
4130 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4131 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4132 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4133 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
4134 } else {
4135 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4136 for (i = 0; i < 3; i++)
4137 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
4138 }
4139 if (adev->gfx.rlc.reg_list) {
4140 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4141 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4142 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4143 }
4144
4145 orig = data = RREG32(mmRLC_PG_CNTL);
4146 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4147 if (orig != data)
4148 WREG32(mmRLC_PG_CNTL, data);
4149
4150 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4151 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4152
4153 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4154 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4155 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4156 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4157
4158 data = 0x10101010;
4159 WREG32(mmRLC_PG_DELAY, data);
4160
4161 data = RREG32(mmRLC_PG_DELAY_2);
4162 data &= ~0xff;
4163 data |= 0x3;
4164 WREG32(mmRLC_PG_DELAY_2, data);
4165
4166 data = RREG32(mmRLC_AUTO_PG_CTRL);
4167 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4168 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4169 WREG32(mmRLC_AUTO_PG_CTRL, data);
4170
4171}
4172
4173static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4174{
4175 gfx_v7_0_enable_gfx_cgpg(adev, enable);
4176 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4177 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4178}
4179
4180static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4181{
4182 u32 count = 0;
4183 const struct cs_section_def *sect = NULL;
4184 const struct cs_extent_def *ext = NULL;
4185
4186 if (adev->gfx.rlc.cs_data == NULL)
4187 return 0;
4188
4189 /* begin clear state */
4190 count += 2;
4191 /* context control state */
4192 count += 3;
4193
4194 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4195 for (ext = sect->section; ext->extent != NULL; ++ext) {
4196 if (sect->id == SECT_CONTEXT)
4197 count += 2 + ext->reg_count;
4198 else
4199 return 0;
4200 }
4201 }
4202 /* pa_sc_raster_config/pa_sc_raster_config1 */
4203 count += 4;
4204 /* end clear state */
4205 count += 2;
4206 /* clear state */
4207 count += 2;
4208
4209 return count;
4210}
4211
4212static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4213 volatile u32 *buffer)
4214{
4215 u32 count = 0, i;
4216 const struct cs_section_def *sect = NULL;
4217 const struct cs_extent_def *ext = NULL;
4218
4219 if (adev->gfx.rlc.cs_data == NULL)
4220 return;
4221 if (buffer == NULL)
4222 return;
4223
4224 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4225 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4226
4227 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4228 buffer[count++] = cpu_to_le32(0x80000000);
4229 buffer[count++] = cpu_to_le32(0x80000000);
4230
4231 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4232 for (ext = sect->section; ext->extent != NULL; ++ext) {
4233 if (sect->id == SECT_CONTEXT) {
4234 buffer[count++] =
4235 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4236 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4237 for (i = 0; i < ext->reg_count; i++)
4238 buffer[count++] = cpu_to_le32(ext->extent[i]);
4239 } else {
4240 return;
4241 }
4242 }
4243 }
4244
4245 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4246 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4247 switch (adev->asic_type) {
4248 case CHIP_BONAIRE:
4249 buffer[count++] = cpu_to_le32(0x16000012);
4250 buffer[count++] = cpu_to_le32(0x00000000);
4251 break;
4252 case CHIP_KAVERI:
4253 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4254 buffer[count++] = cpu_to_le32(0x00000000);
4255 break;
4256 case CHIP_KABINI:
4257 case CHIP_MULLINS:
4258 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4259 buffer[count++] = cpu_to_le32(0x00000000);
4260 break;
4261 case CHIP_HAWAII:
4262 buffer[count++] = cpu_to_le32(0x3a00161a);
4263 buffer[count++] = cpu_to_le32(0x0000002e);
4264 break;
4265 default:
4266 buffer[count++] = cpu_to_le32(0x00000000);
4267 buffer[count++] = cpu_to_le32(0x00000000);
4268 break;
4269 }
4270
4271 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4272 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4273
4274 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4275 buffer[count++] = cpu_to_le32(0);
4276}
4277
4278static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4279{
e3b04bc7
AD		 4280 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4281 AMD_PG_SUPPORT_GFX_SMG |
4282 AMD_PG_SUPPORT_GFX_DMG |
4283 AMD_PG_SUPPORT_CP |
4284 AMD_PG_SUPPORT_GDS |
4285 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56
AD		 4286 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4287 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
e3b04bc7 4288 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4289 gfx_v7_0_init_gfx_cgpg(adev);
4290 gfx_v7_0_enable_cp_pg(adev, true);
4291 gfx_v7_0_enable_gds_pg(adev, true);
4292 }
4293 gfx_v7_0_init_ao_cu_mask(adev);
4294 gfx_v7_0_update_gfx_pg(adev, true);
4295 }
4296}
4297
4298static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4299{
e3b04bc7
AD		 4300 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4301 AMD_PG_SUPPORT_GFX_SMG |
4302 AMD_PG_SUPPORT_GFX_DMG |
4303 AMD_PG_SUPPORT_CP |
4304 AMD_PG_SUPPORT_GDS |
4305 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56 4306 gfx_v7_0_update_gfx_pg(adev, false);
e3b04bc7 4307 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4308 gfx_v7_0_enable_cp_pg(adev, false);
4309 gfx_v7_0_enable_gds_pg(adev, false);
4310 }
4311 }
4312}
4313
4314/**
4315 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4316 *
4317 * @adev: amdgpu_device pointer
4318 *
4319 * Fetches a GPU clock counter snapshot (SI).
4320 * Returns the 64 bit clock counter snapshot.
4321 */
b95e31fd 4322static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
a2e73f56
AD		 4323{
4324 uint64_t clock;
4325
4326 mutex_lock(&adev->gfx.gpu_clock_mutex);
4327 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4328 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4329 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4330 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4331 return clock;
4332}
4333
4334static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4335 uint32_t vmid,
4336 uint32_t gds_base, uint32_t gds_size,
4337 uint32_t gws_base, uint32_t gws_size,
4338 uint32_t oa_base, uint32_t oa_size)
4339{
4340 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4341 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4342
4343 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4344 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4345
4346 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4347 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4348
4349 /* GDS Base */
4350 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4351 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4352 WRITE_DATA_DST_SEL(0)));
4353 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4354 amdgpu_ring_write(ring, 0);
4355 amdgpu_ring_write(ring, gds_base);
4356
4357 /* GDS Size */
4358 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4359 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4360 WRITE_DATA_DST_SEL(0)));
4361 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4362 amdgpu_ring_write(ring, 0);
4363 amdgpu_ring_write(ring, gds_size);
4364
4365 /* GWS */
4366 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4367 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4368 WRITE_DATA_DST_SEL(0)));
4369 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4370 amdgpu_ring_write(ring, 0);
4371 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4372
4373 /* OA */
4374 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4375 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4376 WRITE_DATA_DST_SEL(0)));
4377 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4378 amdgpu_ring_write(ring, 0);
4379 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4380}
4381
472259f0
TSD		 4382static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4383{
4098e6cd
TSD		 4384 WREG32(mmSQ_IND_INDEX,
4385 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4386 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4387 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4388 (SQ_IND_INDEX__FORCE_READ_MASK));
472259f0
TSD		 4389 return RREG32(mmSQ_IND_DATA);
4390}
4391
cc3f5b8d
TSD		 4392static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4393 uint32_t wave, uint32_t thread,
4394 uint32_t regno, uint32_t num, uint32_t *out)
4395{
4396 WREG32(mmSQ_IND_INDEX,
4397 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4398 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4399 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4400 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4401 (SQ_IND_INDEX__FORCE_READ_MASK) |
4402 (SQ_IND_INDEX__AUTO_INCR_MASK));
4403 while (num--)
4404 *(out++) = RREG32(mmSQ_IND_DATA);
4405}
4406
472259f0
TSD		 4407static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4408{
4409 /* type 0 wave data */
4410 dst[(*no_fields)++] = 0;
4411 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4412 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4413 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4414 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4415 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4416 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4417 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4418 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4419 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4420 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4421 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4422 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
74f3ce31
TSD		 4423 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4424 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4425 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4426 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4427 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4428 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
472259f0
TSD		 4429}
4430
cc3f5b8d
TSD		 4431static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4432 uint32_t wave, uint32_t start,
4433 uint32_t size, uint32_t *dst)
4434{
4435 wave_read_regs(
4436 adev, simd, wave, 0,
4437 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4438}
4439
b95e31fd
AD		 4440static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4441 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
05fb7291 4442 .select_se_sh = &gfx_v7_0_select_se_sh,
472259f0 4443 .read_wave_data = &gfx_v7_0_read_wave_data,
cc3f5b8d 4444 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
b95e31fd
AD		 4445};
4446
06120a1e
AD		 4447static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4448 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4449 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4450};
4451
5fc3aeeb 4452static int gfx_v7_0_early_init(void *handle)
a2e73f56 4453{
5fc3aeeb 4454 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4455
4456 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4457 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
b95e31fd 4458 adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
06120a1e 4459 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
a2e73f56
AD		 4460 gfx_v7_0_set_ring_funcs(adev);
4461 gfx_v7_0_set_irq_funcs(adev);
4462 gfx_v7_0_set_gds_init(adev);
4463
4464 return 0;
4465}
4466
ef720532
AD		 4467static int gfx_v7_0_late_init(void *handle)
4468{
4469 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4470 int r;
4471
4472 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4473 if (r)
4474 return r;
4475
4476 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4477 if (r)
4478 return r;
4479
4480 return 0;
4481}
4482
d93f3ca7
AD		 4483static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4484{
4485 u32 gb_addr_config;
4486 u32 mc_shared_chmap, mc_arb_ramcfg;
4487 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4488 u32 tmp;
4489
4490 switch (adev->asic_type) {
4491 case CHIP_BONAIRE:
4492 adev->gfx.config.max_shader_engines = 2;
4493 adev->gfx.config.max_tile_pipes = 4;
4494 adev->gfx.config.max_cu_per_sh = 7;
4495 adev->gfx.config.max_sh_per_se = 1;
4496 adev->gfx.config.max_backends_per_se = 2;
4497 adev->gfx.config.max_texture_channel_caches = 4;
4498 adev->gfx.config.max_gprs = 256;
4499 adev->gfx.config.max_gs_threads = 32;
4500 adev->gfx.config.max_hw_contexts = 8;
4501
4502 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4503 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4504 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4505 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4506 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4507 break;
4508 case CHIP_HAWAII:
4509 adev->gfx.config.max_shader_engines = 4;
4510 adev->gfx.config.max_tile_pipes = 16;
4511 adev->gfx.config.max_cu_per_sh = 11;
4512 adev->gfx.config.max_sh_per_se = 1;
4513 adev->gfx.config.max_backends_per_se = 4;
4514 adev->gfx.config.max_texture_channel_caches = 16;
4515 adev->gfx.config.max_gprs = 256;
4516 adev->gfx.config.max_gs_threads = 32;
4517 adev->gfx.config.max_hw_contexts = 8;
4518
4519 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4520 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4521 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4522 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4523 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4524 break;
4525 case CHIP_KAVERI:
4526 adev->gfx.config.max_shader_engines = 1;
4527 adev->gfx.config.max_tile_pipes = 4;
4528 if ((adev->pdev->device == 0x1304) ||
4529 (adev->pdev->device == 0x1305) ||
4530 (adev->pdev->device == 0x130C) ||
4531 (adev->pdev->device == 0x130F) ||
4532 (adev->pdev->device == 0x1310) ||
4533 (adev->pdev->device == 0x1311) ||
4534 (adev->pdev->device == 0x131C)) {
4535 adev->gfx.config.max_cu_per_sh = 8;
4536 adev->gfx.config.max_backends_per_se = 2;
4537 } else if ((adev->pdev->device == 0x1309) ||
4538 (adev->pdev->device == 0x130A) ||
4539 (adev->pdev->device == 0x130D) ||
4540 (adev->pdev->device == 0x1313) ||
4541 (adev->pdev->device == 0x131D)) {
4542 adev->gfx.config.max_cu_per_sh = 6;
4543 adev->gfx.config.max_backends_per_se = 2;
4544 } else if ((adev->pdev->device == 0x1306) ||
4545 (adev->pdev->device == 0x1307) ||
4546 (adev->pdev->device == 0x130B) ||
4547 (adev->pdev->device == 0x130E) ||
4548 (adev->pdev->device == 0x1315) ||
4549 (adev->pdev->device == 0x131B)) {
4550 adev->gfx.config.max_cu_per_sh = 4;
4551 adev->gfx.config.max_backends_per_se = 1;
4552 } else {
4553 adev->gfx.config.max_cu_per_sh = 3;
4554 adev->gfx.config.max_backends_per_se = 1;
4555 }
4556 adev->gfx.config.max_sh_per_se = 1;
4557 adev->gfx.config.max_texture_channel_caches = 4;
4558 adev->gfx.config.max_gprs = 256;
4559 adev->gfx.config.max_gs_threads = 16;
4560 adev->gfx.config.max_hw_contexts = 8;
4561
4562 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4563 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4564 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4565 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4566 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4567 break;
4568 case CHIP_KABINI:
4569 case CHIP_MULLINS:
4570 default:
4571 adev->gfx.config.max_shader_engines = 1;
4572 adev->gfx.config.max_tile_pipes = 2;
4573 adev->gfx.config.max_cu_per_sh = 2;
4574 adev->gfx.config.max_sh_per_se = 1;
4575 adev->gfx.config.max_backends_per_se = 1;
4576 adev->gfx.config.max_texture_channel_caches = 2;
4577 adev->gfx.config.max_gprs = 256;
4578 adev->gfx.config.max_gs_threads = 16;
4579 adev->gfx.config.max_hw_contexts = 8;
4580
4581 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4582 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4583 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4584 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4585 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4586 break;
4587 }
4588
4589 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4590 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4591 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4592
4593 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4594 adev->gfx.config.mem_max_burst_length_bytes = 256;
4595 if (adev->flags & AMD_IS_APU) {
4596 /* Get memory bank mapping mode. */
4597 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4598 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4599 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4600
4601 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4602 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4603 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4604
4605 /* Validate settings in case only one DIMM installed. */
4606 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4607 dimm00_addr_map = 0;
4608 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4609 dimm01_addr_map = 0;
4610 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4611 dimm10_addr_map = 0;
4612 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4613 dimm11_addr_map = 0;
4614
4615 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4616 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4617 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4618 adev->gfx.config.mem_row_size_in_kb = 2;
4619 else
4620 adev->gfx.config.mem_row_size_in_kb = 1;
4621 } else {
4622 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4623 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4624 if (adev->gfx.config.mem_row_size_in_kb > 4)
4625 adev->gfx.config.mem_row_size_in_kb = 4;
4626 }
4627 /* XXX use MC settings? */
4628 adev->gfx.config.shader_engine_tile_size = 32;
4629 adev->gfx.config.num_gpus = 1;
4630 adev->gfx.config.multi_gpu_tile_size = 64;
4631
4632 /* fix up row size */
4633 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4634 switch (adev->gfx.config.mem_row_size_in_kb) {
4635 case 1:
4636 default:
4637 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4638 break;
4639 case 2:
4640 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4641 break;
4642 case 4:
4643 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4644 break;
4645 }
4646 adev->gfx.config.gb_addr_config = gb_addr_config;
4647}
4648
5fc3aeeb 4649static int gfx_v7_0_sw_init(void *handle)
a2e73f56
AD		 4650{
4651 struct amdgpu_ring *ring;
5fc3aeeb 4652 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4653 int i, r;
4654
4655 /* EOP Event */
4656 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4657 if (r)
4658 return r;
4659
4660 /* Privileged reg */
4661 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4662 if (r)
4663 return r;
4664
4665 /* Privileged inst */
4666 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4667 if (r)
4668 return r;
4669
4670 gfx_v7_0_scratch_init(adev);
4671
4672 r = gfx_v7_0_init_microcode(adev);
4673 if (r) {
4674 DRM_ERROR("Failed to load gfx firmware!\n");
4675 return r;
4676 }
4677
4678 r = gfx_v7_0_rlc_init(adev);
4679 if (r) {
4680 DRM_ERROR("Failed to init rlc BOs!\n");
4681 return r;
4682 }
4683
4684 /* allocate mec buffers */
4685 r = gfx_v7_0_mec_init(adev);
4686 if (r) {
4687 DRM_ERROR("Failed to init MEC BOs!\n");
4688 return r;
4689 }
4690
a2e73f56
AD		 4691 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4692 ring = &adev->gfx.gfx_ring[i];
4693 ring->ring_obj = NULL;
4694 sprintf(ring->name, "gfx");
2800de2e 4695 r = amdgpu_ring_init(adev, ring, 1024,
21cd942e 4696 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
a2e73f56
AD		 4697 if (r)
4698 return r;
4699 }
4700
4701 /* set up the compute queues */
4702 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4703 unsigned irq_type;
4704
4705 /* max 32 queues per MEC */
4706 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4707 DRM_ERROR("Too many (%d) compute rings!\n", i);
4708 break;
4709 }
4710 ring = &adev->gfx.compute_ring[i];
4711 ring->ring_obj = NULL;
4712 ring->use_doorbell = true;
4713 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4714 ring->me = 1; /* first MEC */
4715 ring->pipe = i / 8;
4716 ring->queue = i % 8;
771c8ec1 4717 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
a2e73f56
AD		 4718 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4719 /* type-2 packets are deprecated on MEC, use type-3 instead */
2800de2e 4720 r = amdgpu_ring_init(adev, ring, 1024,
21cd942e 4721 &adev->gfx.eop_irq, irq_type);
a2e73f56
AD		 4722 if (r)
4723 return r;
4724 }
4725
4726 /* reserve GDS, GWS and OA resource for gfx */
78bbbd9c
CK		 4727 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
4728 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
4729 &adev->gds.gds_gfx_bo, NULL, NULL);
a2e73f56
AD		 4730 if (r)
4731 return r;
4732
78bbbd9c
CK		 4733 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
4734 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
4735 &adev->gds.gws_gfx_bo, NULL, NULL);
a2e73f56
AD		 4736 if (r)
4737 return r;
4738
78bbbd9c
CK		 4739 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
4740 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
4741 &adev->gds.oa_gfx_bo, NULL, NULL);
a2e73f56
AD		 4742 if (r)
4743 return r;
4744
d93f3ca7
AD		 4745 adev->gfx.ce_ram_size = 0x8000;
4746
4747 gfx_v7_0_gpu_early_init(adev);
4748
a2e73f56
AD		 4749 return r;
4750}
4751
5fc3aeeb 4752static int gfx_v7_0_sw_fini(void *handle)
a2e73f56
AD		 4753{
4754 int i;
5fc3aeeb 4755 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 4756
8640faed
JZ		 4757 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4758 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4759 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
a2e73f56
AD		 4760
4761 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4762 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4763 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4764 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4765
a2e73f56
AD		 4766 gfx_v7_0_cp_compute_fini(adev);
4767 gfx_v7_0_rlc_fini(adev);
4768 gfx_v7_0_mec_fini(adev);
e517cd77 4769 gfx_v7_0_free_microcode(adev);
a2e73f56
AD		 4770
4771 return 0;
4772}
4773
5fc3aeeb 4774static int gfx_v7_0_hw_init(void *handle)
a2e73f56
AD		 4775{
4776 int r;
5fc3aeeb 4777 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4778
4779 gfx_v7_0_gpu_init(adev);
4780
4781 /* init rlc */
4782 r = gfx_v7_0_rlc_resume(adev);
4783 if (r)
4784 return r;
4785
4786 r = gfx_v7_0_cp_resume(adev);
4787 if (r)
4788 return r;
4789
4790 return r;
4791}
4792
5fc3aeeb 4793static int gfx_v7_0_hw_fini(void *handle)
a2e73f56 4794{
5fc3aeeb 4795 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4796
ef720532
AD		 4797 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4798 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
a2e73f56
AD		 4799 gfx_v7_0_cp_enable(adev, false);
4800 gfx_v7_0_rlc_stop(adev);
4801 gfx_v7_0_fini_pg(adev);
4802
4803 return 0;
4804}
4805
5fc3aeeb 4806static int gfx_v7_0_suspend(void *handle)
a2e73f56 4807{
5fc3aeeb 4808 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4809
a2e73f56
AD		 4810 return gfx_v7_0_hw_fini(adev);
4811}
4812
5fc3aeeb 4813static int gfx_v7_0_resume(void *handle)
a2e73f56 4814{
5fc3aeeb 4815 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4816
a2e73f56
AD		 4817 return gfx_v7_0_hw_init(adev);
4818}
4819
5fc3aeeb 4820static bool gfx_v7_0_is_idle(void *handle)
a2e73f56 4821{
5fc3aeeb 4822 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4823
a2e73f56
AD		 4824 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4825 return false;
4826 else
4827 return true;
4828}
4829
5fc3aeeb 4830static int gfx_v7_0_wait_for_idle(void *handle)
a2e73f56
AD		 4831{
4832 unsigned i;
4833 u32 tmp;
5fc3aeeb 4834 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4835
4836 for (i = 0; i < adev->usec_timeout; i++) {
4837 /* read MC_STATUS */
4838 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4839
4840 if (!tmp)
4841 return 0;
4842 udelay(1);
4843 }
4844 return -ETIMEDOUT;
4845}
4846
5fc3aeeb 4847static int gfx_v7_0_soft_reset(void *handle)
a2e73f56
AD		 4848{
4849 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4850 u32 tmp;
5fc3aeeb 4851 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4852
4853 /* GRBM_STATUS */
4854 tmp = RREG32(mmGRBM_STATUS);
4855 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4856 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4857 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4858 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4859 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4860 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4861 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4862 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4863
4864 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4865 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4866 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4867 }
4868
4869 /* GRBM_STATUS2 */
4870 tmp = RREG32(mmGRBM_STATUS2);
4871 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4872 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4873
4874 /* SRBM_STATUS */
4875 tmp = RREG32(mmSRBM_STATUS);
4876 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4877 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4878
4879 if (grbm_soft_reset || srbm_soft_reset) {
a2e73f56
AD		 4880 /* disable CG/PG */
4881 gfx_v7_0_fini_pg(adev);
4882 gfx_v7_0_update_cg(adev, false);
4883
4884 /* stop the rlc */
4885 gfx_v7_0_rlc_stop(adev);
4886
4887 /* Disable GFX parsing/prefetching */
4888 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4889
4890 /* Disable MEC parsing/prefetching */
4891 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4892
4893 if (grbm_soft_reset) {
4894 tmp = RREG32(mmGRBM_SOFT_RESET);
4895 tmp |= grbm_soft_reset;
4896 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4897 WREG32(mmGRBM_SOFT_RESET, tmp);
4898 tmp = RREG32(mmGRBM_SOFT_RESET);
4899
4900 udelay(50);
4901
4902 tmp &= ~grbm_soft_reset;
4903 WREG32(mmGRBM_SOFT_RESET, tmp);
4904 tmp = RREG32(mmGRBM_SOFT_RESET);
4905 }
4906
4907 if (srbm_soft_reset) {
4908 tmp = RREG32(mmSRBM_SOFT_RESET);
4909 tmp |= srbm_soft_reset;
4910 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4911 WREG32(mmSRBM_SOFT_RESET, tmp);
4912 tmp = RREG32(mmSRBM_SOFT_RESET);
4913
4914 udelay(50);
4915
4916 tmp &= ~srbm_soft_reset;
4917 WREG32(mmSRBM_SOFT_RESET, tmp);
4918 tmp = RREG32(mmSRBM_SOFT_RESET);
4919 }
4920 /* Wait a little for things to settle down */
4921 udelay(50);
a2e73f56
AD		 4922 }
4923 return 0;
4924}
4925
4926static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4927 enum amdgpu_interrupt_state state)
4928{
4929 u32 cp_int_cntl;
4930
4931 switch (state) {
4932 case AMDGPU_IRQ_STATE_DISABLE:
4933 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4934 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4935 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4936 break;
4937 case AMDGPU_IRQ_STATE_ENABLE:
4938 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4939 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4940 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4941 break;
4942 default:
4943 break;
4944 }
4945}
4946
4947static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4948 int me, int pipe,
4949 enum amdgpu_interrupt_state state)
4950{
4951 u32 mec_int_cntl, mec_int_cntl_reg;
4952
4953 /*
4954 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4955 * handles the setting of interrupts for this specific pipe. All other
4956 * pipes' interrupts are set by amdkfd.
4957 */
4958
4959 if (me == 1) {
4960 switch (pipe) {
4961 case 0:
4962 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4963 break;
4964 default:
4965 DRM_DEBUG("invalid pipe %d\n", pipe);
4966 return;
4967 }
4968 } else {
4969 DRM_DEBUG("invalid me %d\n", me);
4970 return;
4971 }
4972
4973 switch (state) {
4974 case AMDGPU_IRQ_STATE_DISABLE:
4975 mec_int_cntl = RREG32(mec_int_cntl_reg);
4976 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4977 WREG32(mec_int_cntl_reg, mec_int_cntl);
4978 break;
4979 case AMDGPU_IRQ_STATE_ENABLE:
4980 mec_int_cntl = RREG32(mec_int_cntl_reg);
4981 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4982 WREG32(mec_int_cntl_reg, mec_int_cntl);
4983 break;
4984 default:
4985 break;
4986 }
4987}
4988
4989static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4990 struct amdgpu_irq_src *src,
4991 unsigned type,
4992 enum amdgpu_interrupt_state state)
4993{
4994 u32 cp_int_cntl;
4995
4996 switch (state) {
4997 case AMDGPU_IRQ_STATE_DISABLE:
4998 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4999 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5000 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5001 break;
5002 case AMDGPU_IRQ_STATE_ENABLE:
5003 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5004 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5005 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5006 break;
5007 default:
5008 break;
5009 }
5010
5011 return 0;
5012}
5013
5014static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5015 struct amdgpu_irq_src *src,
5016 unsigned type,
5017 enum amdgpu_interrupt_state state)
5018{
5019 u32 cp_int_cntl;
5020
5021 switch (state) {
5022 case AMDGPU_IRQ_STATE_DISABLE:
5023 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5024 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5025 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5026 break;
5027 case AMDGPU_IRQ_STATE_ENABLE:
5028 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5029 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5030 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5031 break;
5032 default:
5033 break;
5034 }
5035
5036 return 0;
5037}
5038
5039static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5040 struct amdgpu_irq_src *src,
5041 unsigned type,
5042 enum amdgpu_interrupt_state state)
5043{
5044 switch (type) {
5045 case AMDGPU_CP_IRQ_GFX_EOP:
5046 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
5047 break;
5048 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5049 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5050 break;
5051 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5052 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5053 break;
5054 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5055 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5056 break;
5057 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5058 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5059 break;
5060 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5061 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5062 break;
5063 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5064 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5065 break;
5066 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5067 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5068 break;
5069 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5070 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5071 break;
5072 default:
5073 break;
5074 }
5075 return 0;
5076}
5077
5078static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5079 struct amdgpu_irq_src *source,
5080 struct amdgpu_iv_entry *entry)
5081{
5082 u8 me_id, pipe_id;
5083 struct amdgpu_ring *ring;
5084 int i;
5085
5086 DRM_DEBUG("IH: CP EOP\n");
5087 me_id = (entry->ring_id & 0x0c) >> 2;
5088 pipe_id = (entry->ring_id & 0x03) >> 0;
5089 switch (me_id) {
5090 case 0:
5091 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5092 break;
5093 case 1:
5094 case 2:
5095 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5096 ring = &adev->gfx.compute_ring[i];
8b18300c 5097 if ((ring->me == me_id) && (ring->pipe == pipe_id))
a2e73f56
AD		 5098 amdgpu_fence_process(ring);
5099 }
5100 break;
5101 }
5102 return 0;
5103}
5104
5105static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5106 struct amdgpu_irq_src *source,
5107 struct amdgpu_iv_entry *entry)
5108{
5109 DRM_ERROR("Illegal register access in command stream\n");
5110 schedule_work(&adev->reset_work);
5111 return 0;
5112}
5113
5114static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5115 struct amdgpu_irq_src *source,
5116 struct amdgpu_iv_entry *entry)
5117{
5118 DRM_ERROR("Illegal instruction in command stream\n");
5119 // XXX soft reset the gfx block only
5120 schedule_work(&adev->reset_work);
5121 return 0;
5122}
5123
5fc3aeeb 5124static int gfx_v7_0_set_clockgating_state(void *handle,
5125 enum amd_clockgating_state state)
a2e73f56
AD		 5126{
5127 bool gate = false;
5fc3aeeb 5128 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5129
5fc3aeeb 5130 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 5131 gate = true;
5132
5133 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5134 /* order matters! */
5135 if (gate) {
5136 gfx_v7_0_enable_mgcg(adev, true);
5137 gfx_v7_0_enable_cgcg(adev, true);
5138 } else {
5139 gfx_v7_0_enable_cgcg(adev, false);
5140 gfx_v7_0_enable_mgcg(adev, false);
5141 }
5142 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5143
5144 return 0;
5145}
5146
5fc3aeeb 5147static int gfx_v7_0_set_powergating_state(void *handle,
5148 enum amd_powergating_state state)
a2e73f56
AD		 5149{
5150 bool gate = false;
5fc3aeeb 5151 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5152
5fc3aeeb 5153 if (state == AMD_PG_STATE_GATE)
a2e73f56
AD		 5154 gate = true;
5155
e3b04bc7
AD		 5156 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5157 AMD_PG_SUPPORT_GFX_SMG |
5158 AMD_PG_SUPPORT_GFX_DMG |
5159 AMD_PG_SUPPORT_CP |
5160 AMD_PG_SUPPORT_GDS |
5161 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56 5162 gfx_v7_0_update_gfx_pg(adev, gate);
e3b04bc7 5163 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 5164 gfx_v7_0_enable_cp_pg(adev, gate);
5165 gfx_v7_0_enable_gds_pg(adev, gate);
5166 }
5167 }
5168
5169 return 0;
5170}
5171
a1255107 5172static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
88a907d6 5173 .name = "gfx_v7_0",
a2e73f56 5174 .early_init = gfx_v7_0_early_init,
ef720532 5175 .late_init = gfx_v7_0_late_init,
a2e73f56
AD		 5176 .sw_init = gfx_v7_0_sw_init,
5177 .sw_fini = gfx_v7_0_sw_fini,
5178 .hw_init = gfx_v7_0_hw_init,
5179 .hw_fini = gfx_v7_0_hw_fini,
5180 .suspend = gfx_v7_0_suspend,
5181 .resume = gfx_v7_0_resume,
5182 .is_idle = gfx_v7_0_is_idle,
5183 .wait_for_idle = gfx_v7_0_wait_for_idle,
5184 .soft_reset = gfx_v7_0_soft_reset,
a2e73f56
AD		 5185 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5186 .set_powergating_state = gfx_v7_0_set_powergating_state,
5187};
5188
a2e73f56 5189static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
21cd942e 5190 .type = AMDGPU_RING_TYPE_GFX,
79887142
CK		 5191 .align_mask = 0xff,
5192 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
f1c0efc5 5193 .get_rptr = gfx_v7_0_ring_get_rptr,
a2e73f56
AD		 5194 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5195 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
e12f3d7a
CK		 5196 .emit_frame_size =
5197 20 + /* gfx_v7_0_ring_emit_gds_switch */
5198 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5199 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5200 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5201 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5202 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
45682886 5203 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
e12f3d7a 5204 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
93323131 5205 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
a2e73f56 5206 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
b8c7b39e 5207 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
a2e73f56
AD		 5208 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5209 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d2edb07b 5210 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
0955860b 5211 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
a2e73f56
AD		 5212 .test_ring = gfx_v7_0_ring_test_ring,
5213 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5214 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5215 .pad_ib = amdgpu_ring_generic_pad_ib,
753ad49c 5216 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
a2e73f56
AD		 5217};
5218
5219static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
21cd942e 5220 .type = AMDGPU_RING_TYPE_COMPUTE,
79887142
CK		 5221 .align_mask = 0xff,
5222 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
f1c0efc5 5223 .get_rptr = gfx_v7_0_ring_get_rptr,
a2e73f56
AD		 5224 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5225 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
e12f3d7a
CK		 5226 .emit_frame_size =
5227 20 + /* gfx_v7_0_ring_emit_gds_switch */
5228 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5229 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5230 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5231 17 + /* gfx_v7_0_ring_emit_vm_flush */
5232 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5233 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
93323131 5234 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
a2e73f56 5235 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
b8c7b39e 5236 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
a2e73f56
AD		 5237 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5238 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d9b5327a 5239 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
0955860b 5240 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
a2e73f56
AD		 5241 .test_ring = gfx_v7_0_ring_test_ring,
5242 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5243 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5244 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 5245};
5246
5247static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5248{
5249 int i;
5250
5251 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5252 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5253 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5254 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5255}
5256
5257static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5258 .set = gfx_v7_0_set_eop_interrupt_state,
5259 .process = gfx_v7_0_eop_irq,
5260};
5261
5262static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5263 .set = gfx_v7_0_set_priv_reg_fault_state,
5264 .process = gfx_v7_0_priv_reg_irq,
5265};
5266
5267static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5268 .set = gfx_v7_0_set_priv_inst_fault_state,
5269 .process = gfx_v7_0_priv_inst_irq,
5270};
5271
5272static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5273{
5274 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5275 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5276
5277 adev->gfx.priv_reg_irq.num_types = 1;
5278 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5279
5280 adev->gfx.priv_inst_irq.num_types = 1;
5281 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5282}
5283
5284static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5285{
5286 /* init asci gds info */
5287 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5288 adev->gds.gws.total_size = 64;
5289 adev->gds.oa.total_size = 16;
5290
5291 if (adev->gds.mem.total_size == 64 * 1024) {
5292 adev->gds.mem.gfx_partition_size = 4096;
5293 adev->gds.mem.cs_partition_size = 4096;
5294
5295 adev->gds.gws.gfx_partition_size = 4;
5296 adev->gds.gws.cs_partition_size = 4;
5297
5298 adev->gds.oa.gfx_partition_size = 4;
5299 adev->gds.oa.cs_partition_size = 1;
5300 } else {
5301 adev->gds.mem.gfx_partition_size = 1024;
5302 adev->gds.mem.cs_partition_size = 1024;
5303
5304 adev->gds.gws.gfx_partition_size = 16;
5305 adev->gds.gws.cs_partition_size = 16;
5306
5307 adev->gds.oa.gfx_partition_size = 4;
5308 adev->gds.oa.cs_partition_size = 4;
5309 }
5310}
5311
5312
7dae69a2 5313static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
a2e73f56
AD		 5314{
5315 int i, j, k, counter, active_cu_number = 0;
5316 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7dae69a2 5317 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
324c614a 5318 unsigned disable_masks[4 * 2];
a2e73f56 5319
6157bd7a
FC		 5320 memset(cu_info, 0, sizeof(*cu_info));
5321
324c614a
NH		 5322 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5323
a2e73f56
AD		 5324 mutex_lock(&adev->grbm_idx_mutex);
5325 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5326 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5327 mask = 1;
5328 ao_bitmap = 0;
5329 counter = 0;
9559ef5b 5330 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
324c614a
NH		 5331 if (i < 4 && j < 2)
5332 gfx_v7_0_set_user_cu_inactive_bitmap(
5333 adev, disable_masks[i * 2 + j]);
8f8e00c1 5334 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
a2e73f56
AD		 5335 cu_info->bitmap[i][j] = bitmap;
5336
8f8e00c1 5337 for (k = 0; k < 16; k ++) {
a2e73f56
AD		 5338 if (bitmap & mask) {
5339 if (counter < 2)
5340 ao_bitmap |= mask;
5341 counter ++;
5342 }
5343 mask <<= 1;
5344 }
5345 active_cu_number += counter;
5346 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5347 }
5348 }
9559ef5b 5349 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8f8e00c1 5350 mutex_unlock(&adev->grbm_idx_mutex);
a2e73f56
AD		 5351
5352 cu_info->number = active_cu_number;
5353 cu_info->ao_cu_mask = ao_cu_mask;
a2e73f56 5354}
a1255107
AD		 5355
5356const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5357{
5358 .type = AMD_IP_BLOCK_TYPE_GFX,
5359 .major = 7,
5360 .minor = 0,
5361 .rev = 0,
5362 .funcs = &gfx_v7_0_ip_funcs,
5363};
5364
5365const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5366{
5367 .type = AMD_IP_BLOCK_TYPE_GFX,
5368 .major = 7,
5369 .minor = 1,
5370 .rev = 0,
5371 .funcs = &gfx_v7_0_ip_funcs,
5372};
5373
5374const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5375{
5376 .type = AMD_IP_BLOCK_TYPE_GFX,
5377 .major = 7,
5378 .minor = 2,
5379 .rev = 0,
5380 .funcs = &gfx_v7_0_ip_funcs,
5381};
5382
5383const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5384{
5385 .type = AMD_IP_BLOCK_TYPE_GFX,
5386 .major = 7,
5387 .minor = 3,
5388 .rev = 0,
5389 .funcs = &gfx_v7_0_ip_funcs,
5390};
ubuntu-bionic-kernel mirror