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drm/amdgpu: move select_se_sh into the gfx struct
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "vi.h"
28#include "vid.h"
29#include "amdgpu_ucode.h"
68182d90 30#include "amdgpu_atombios.h"
aaa36a97
AD		 31#include "clearstate_vi.h"
32
33#include "gmc/gmc_8_2_d.h"
34#include "gmc/gmc_8_2_sh_mask.h"
35
36#include "oss/oss_3_0_d.h"
37#include "oss/oss_3_0_sh_mask.h"
38
39#include "bif/bif_5_0_d.h"
40#include "bif/bif_5_0_sh_mask.h"
41
42#include "gca/gfx_8_0_d.h"
43#include "gca/gfx_8_0_enum.h"
44#include "gca/gfx_8_0_sh_mask.h"
45#include "gca/gfx_8_0_enum.h"
46
aaa36a97
AD		 47#include "dce/dce_10_0_d.h"
48#include "dce/dce_10_0_sh_mask.h"
49
50#define GFX8_NUM_GFX_RINGS 1
51#define GFX8_NUM_COMPUTE_RINGS 8
52
53#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
54#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
2cc0c0b5 55#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
aaa36a97
AD		 56#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
57
58#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
59#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
60#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
61#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
62#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
63#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
64#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
65#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
66#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
67
6e378858
EH		 68#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
69#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
70#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
71#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
72#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
73#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
74
75/* BPM SERDES CMD */
76#define SET_BPM_SERDES_CMD 1
77#define CLE_BPM_SERDES_CMD 0
78
79/* BPM Register Address*/
80enum {
81 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
82 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
83 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
84 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
85 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
86 BPM_REG_FGCG_MAX
87};
88
2b6cd977
EH		 89#define RLC_FormatDirectRegListLength 14
90
c65444fe
JZ		 91MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
92MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
93MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
94MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
95MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
96MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
97
e3c7656c
SL		 98MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
99MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
100MODULE_FIRMWARE("amdgpu/stoney_me.bin");
101MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
102MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
103
c65444fe
JZ		 104MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
105MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
106MODULE_FIRMWARE("amdgpu/tonga_me.bin");
107MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
108MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
109MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
110
111MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
112MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
113MODULE_FIRMWARE("amdgpu/topaz_me.bin");
114MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
c65444fe 115MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
aaa36a97 116
af15a2d5
DZ		 117MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
118MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
119MODULE_FIRMWARE("amdgpu/fiji_me.bin");
120MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
121MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
122MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
123
2cc0c0b5
FC		 124MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
125MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
126MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
127MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
128MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
129MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
68182d90 130
2cc0c0b5
FC		 131MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
132MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
133MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
134MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
135MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
136MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
68182d90 137
aaa36a97
AD		 138static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
139{
140 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
141 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
142 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
143 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
144 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
145 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
146 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
147 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
148 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
149 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
150 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
151 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
152 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
153 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
154 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
155 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
156};
157
158static const u32 golden_settings_tonga_a11[] =
159{
160 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
161 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
162 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
163 mmGB_GPU_ID, 0x0000000f, 0x00000000,
164 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
165 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
166 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 167 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 168 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
169 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 170 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 171 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
172 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
173 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
6a00a09e 174 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
aaa36a97
AD		 175};
176
177static const u32 tonga_golden_common_all[] =
178{
179 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
180 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
181 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
182 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
183 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
184 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
185 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
186 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
187};
188
189static const u32 tonga_mgcg_cgcg_init[] =
190{
191 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
192 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
193 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
194 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
195 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
196 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
197 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
198 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
199 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
200 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
201 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
202 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
203 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
204 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
205 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
206 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
207 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
208 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
209 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
210 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
211 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
212 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
213 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
214 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
215 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
216 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
217 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
218 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
219 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
220 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
221 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
222 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
223 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
224 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
225 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
226 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
227 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
228 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
229 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
230 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
231 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
232 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
233 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
234 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
235 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
236 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
237 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
238 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
239 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
240 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
241 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
242 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
243 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
244 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
245 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
246 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
247 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
248 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
249 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
250 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
251 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
252 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
253 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
254 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
255 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
256 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
257 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
258 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
259 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
260 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
261 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
262 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
263 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
264 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
265 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
266};
267
2cc0c0b5 268static const u32 golden_settings_polaris11_a11[] =
68182d90 269{
b9934878 270 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00006208,
68182d90
FC		 271 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
272 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
273 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
274 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
b9934878
FC		 275 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
276 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
68182d90
FC		 277 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
278 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
279 mmSQ_CONFIG, 0x07f80000, 0x07180000,
280 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
281 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
282 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
283 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
284 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
285};
286
2cc0c0b5 287static const u32 polaris11_golden_common_all[] =
68182d90
FC		 288{
289 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
68182d90
FC		 290 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
291 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
292 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
293 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
294 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
295};
296
2cc0c0b5 297static const u32 golden_settings_polaris10_a11[] =
68182d90
FC		 298{
299 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
92d15768
RZ		 300 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
301 mmCB_HW_CONTROL_2, 0, 0x0f000000,
68182d90
FC		 302 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
303 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
304 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
305 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
306 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
307 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
308 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
309 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
310 mmSQ_CONFIG, 0x07f80000, 0x07180000,
311 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
312 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
313 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
314 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
315};
316
2cc0c0b5 317static const u32 polaris10_golden_common_all[] =
68182d90
FC		 318{
319 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
320 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
321 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
322 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
323 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
324 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
325 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
326 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
327};
328
af15a2d5
DZ		 329static const u32 fiji_golden_common_all[] =
330{
331 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
332 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
333 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
a7ca8ef9 334 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
af15a2d5
DZ		 335 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
336 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
337 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
a7ca8ef9
FC		 338 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
339 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
340 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
af15a2d5
DZ		 341};
342
343static const u32 golden_settings_fiji_a10[] =
344{
345 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
346 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
347 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
af15a2d5 348 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
a7ca8ef9
FC		 349 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
350 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
af15a2d5 351 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
a7ca8ef9
FC		 352 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
353 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
af15a2d5 354 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
a7ca8ef9 355 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
af15a2d5
DZ		 356};
357
358static const u32 fiji_mgcg_cgcg_init[] =
359{
a7ca8ef9 360 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
af15a2d5
DZ		 361 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
362 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
363 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
364 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
365 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
366 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
367 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
368 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
369 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
370 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
371 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
372 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
373 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
374 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
375 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
376 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
377 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
378 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
379 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
380 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
381 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
382 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
383 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
384 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
385 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
386 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
387 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
388 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
389 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
390 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
391 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
392 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
393 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
394 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
395};
396
aaa36a97
AD		 397static const u32 golden_settings_iceland_a11[] =
398{
399 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
400 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
401 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
402 mmGB_GPU_ID, 0x0000000f, 0x00000000,
403 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
404 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
405 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
406 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
6a00a09e 407 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 408 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
409 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 410 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 411 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
412 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
413 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
414};
415
416static const u32 iceland_golden_common_all[] =
417{
418 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
419 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
420 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
421 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
422 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
423 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
424 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
425 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
426};
427
428static const u32 iceland_mgcg_cgcg_init[] =
429{
430 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
431 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
432 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
433 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
434 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
435 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
436 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
437 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
438 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
439 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
440 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
441 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
443 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
444 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
445 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
446 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
447 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
448 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
449 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
450 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
451 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
452 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
453 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
454 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
455 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
456 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
457 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
458 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
459 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
460 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
461 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
462 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
463 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
464 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
465 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
466 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
467 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
468 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
469 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
470 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
471 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
472 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
473 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
474 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
475 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
476 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
477 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
478 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
479 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
480 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
481 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
482 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
483 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
484 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
485 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
486 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
487 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
488 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
489 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
490 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
491 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
492 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
493 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
494};
495
496static const u32 cz_golden_settings_a11[] =
497{
498 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
499 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
500 mmGB_GPU_ID, 0x0000000f, 0x00000000,
501 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
502 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 503 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97 504 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
6a00a09e 505 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 506 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
507 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
508};
509
510static const u32 cz_golden_common_all[] =
511{
512 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
513 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
514 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
515 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
516 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
517 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
518 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
519 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
520};
521
522static const u32 cz_mgcg_cgcg_init[] =
523{
524 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
525 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
526 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
527 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
528 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
529 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
530 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
531 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
532 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
533 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
534 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
535 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
536 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
537 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
538 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
539 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
540 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
541 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
542 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
543 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
544 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
545 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
546 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
547 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
548 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
549 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
550 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
551 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
552 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
553 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
554 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
555 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
556 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
557 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
558 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
559 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
560 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
561 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
562 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
563 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
564 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
565 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
566 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
567 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
568 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
569 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
570 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
571 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
572 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
573 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
574 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
575 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
576 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
577 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
578 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
579 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
580 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
581 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
582 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
583 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
584 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
585 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
586 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
587 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
588 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
589 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
590 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
591 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
592 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
593 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
594 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
595 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
596 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
597 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
598 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
599};
600
e3c7656c
SL		 601static const u32 stoney_golden_settings_a11[] =
602{
603 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
604 mmGB_GPU_ID, 0x0000000f, 0x00000000,
605 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
606 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
607 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
608 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
edf600da 609 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
e3c7656c
SL		 610 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
611 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
612 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
613};
614
615static const u32 stoney_golden_common_all[] =
616{
617 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
618 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
619 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
620 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
621 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
622 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
623 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
624 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
625};
626
627static const u32 stoney_mgcg_cgcg_init[] =
628{
629 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
630 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
631 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
632 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
633 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
634 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
635};
636
aaa36a97
AD		 637static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
638static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
639static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
dbff57bc 640static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
2b6cd977 641static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
7dae69a2 642static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
aaa36a97
AD		 643
644static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
645{
646 switch (adev->asic_type) {
647 case CHIP_TOPAZ:
648 amdgpu_program_register_sequence(adev,
649 iceland_mgcg_cgcg_init,
650 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
651 amdgpu_program_register_sequence(adev,
652 golden_settings_iceland_a11,
653 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
654 amdgpu_program_register_sequence(adev,
655 iceland_golden_common_all,
656 (const u32)ARRAY_SIZE(iceland_golden_common_all));
657 break;
af15a2d5
DZ		 658 case CHIP_FIJI:
659 amdgpu_program_register_sequence(adev,
660 fiji_mgcg_cgcg_init,
661 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
662 amdgpu_program_register_sequence(adev,
663 golden_settings_fiji_a10,
664 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
665 amdgpu_program_register_sequence(adev,
666 fiji_golden_common_all,
667 (const u32)ARRAY_SIZE(fiji_golden_common_all));
668 break;
669
aaa36a97
AD		 670 case CHIP_TONGA:
671 amdgpu_program_register_sequence(adev,
672 tonga_mgcg_cgcg_init,
673 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
674 amdgpu_program_register_sequence(adev,
675 golden_settings_tonga_a11,
676 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
677 amdgpu_program_register_sequence(adev,
678 tonga_golden_common_all,
679 (const u32)ARRAY_SIZE(tonga_golden_common_all));
680 break;
2cc0c0b5 681 case CHIP_POLARIS11:
68182d90 682 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 683 golden_settings_polaris11_a11,
684 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
68182d90 685 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 686 polaris11_golden_common_all,
687 (const u32)ARRAY_SIZE(polaris11_golden_common_all));
68182d90 688 break;
2cc0c0b5 689 case CHIP_POLARIS10:
68182d90 690 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 691 golden_settings_polaris10_a11,
692 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
68182d90 693 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 694 polaris10_golden_common_all,
695 (const u32)ARRAY_SIZE(polaris10_golden_common_all));
68182d90 696 break;
aaa36a97
AD		 697 case CHIP_CARRIZO:
698 amdgpu_program_register_sequence(adev,
699 cz_mgcg_cgcg_init,
700 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
701 amdgpu_program_register_sequence(adev,
702 cz_golden_settings_a11,
703 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
704 amdgpu_program_register_sequence(adev,
705 cz_golden_common_all,
706 (const u32)ARRAY_SIZE(cz_golden_common_all));
707 break;
e3c7656c
SL		 708 case CHIP_STONEY:
709 amdgpu_program_register_sequence(adev,
710 stoney_mgcg_cgcg_init,
711 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
712 amdgpu_program_register_sequence(adev,
713 stoney_golden_settings_a11,
714 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
715 amdgpu_program_register_sequence(adev,
716 stoney_golden_common_all,
717 (const u32)ARRAY_SIZE(stoney_golden_common_all));
718 break;
aaa36a97
AD		 719 default:
720 break;
721 }
722}
723
724static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
725{
726 int i;
727
728 adev->gfx.scratch.num_reg = 7;
729 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
730 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
731 adev->gfx.scratch.free[i] = true;
732 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
733 }
734}
735
736static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
737{
738 struct amdgpu_device *adev = ring->adev;
739 uint32_t scratch;
740 uint32_t tmp = 0;
741 unsigned i;
742 int r;
743
744 r = amdgpu_gfx_scratch_get(adev, &scratch);
745 if (r) {
746 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
747 return r;
748 }
749 WREG32(scratch, 0xCAFEDEAD);
a27de35c 750 r = amdgpu_ring_alloc(ring, 3);
aaa36a97
AD		 751 if (r) {
752 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
753 ring->idx, r);
754 amdgpu_gfx_scratch_free(adev, scratch);
755 return r;
756 }
757 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
758 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
759 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 760 amdgpu_ring_commit(ring);
aaa36a97
AD		 761
762 for (i = 0; i < adev->usec_timeout; i++) {
763 tmp = RREG32(scratch);
764 if (tmp == 0xDEADBEEF)
765 break;
766 DRM_UDELAY(1);
767 }
768 if (i < adev->usec_timeout) {
769 DRM_INFO("ring test on %d succeeded in %d usecs\n",
770 ring->idx, i);
771 } else {
772 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
773 ring->idx, scratch, tmp);
774 r = -EINVAL;
775 }
776 amdgpu_gfx_scratch_free(adev, scratch);
777 return r;
778}
779
780static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
781{
782 struct amdgpu_device *adev = ring->adev;
783 struct amdgpu_ib ib;
1763552e 784 struct fence *f = NULL;
aaa36a97
AD		 785 uint32_t scratch;
786 uint32_t tmp = 0;
787 unsigned i;
788 int r;
789
790 r = amdgpu_gfx_scratch_get(adev, &scratch);
791 if (r) {
792 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
793 return r;
794 }
795 WREG32(scratch, 0xCAFEDEAD);
b203dd95 796 memset(&ib, 0, sizeof(ib));
b07c60c0 797 r = amdgpu_ib_get(adev, NULL, 256, &ib);
aaa36a97
AD		 798 if (r) {
799 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
42d13693 800 goto err1;
aaa36a97
AD		 801 }
802 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
803 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
804 ib.ptr[2] = 0xDEADBEEF;
805 ib.length_dw = 3;
42d13693 806
c5637837 807 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
42d13693
CZ		 808 if (r)
809 goto err2;
810
1763552e 811 r = fence_wait(f, false);
aaa36a97
AD		 812 if (r) {
813 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
42d13693 814 goto err2;
aaa36a97
AD		 815 }
816 for (i = 0; i < adev->usec_timeout; i++) {
817 tmp = RREG32(scratch);
818 if (tmp == 0xDEADBEEF)
819 break;
820 DRM_UDELAY(1);
821 }
822 if (i < adev->usec_timeout) {
823 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
42d13693
CZ		 824 ring->idx, i);
825 goto err2;
aaa36a97
AD		 826 } else {
827 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
828 scratch, tmp);
829 r = -EINVAL;
830 }
42d13693 831err2:
281b4223 832 fence_put(f);
cc55c45d 833 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 834 fence_put(f);
42d13693
CZ		 835err1:
836 amdgpu_gfx_scratch_free(adev, scratch);
aaa36a97
AD		 837 return r;
838}
839
13331ac3
ML		 840
841static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) {
842 release_firmware(adev->gfx.pfp_fw);
843 adev->gfx.pfp_fw = NULL;
844 release_firmware(adev->gfx.me_fw);
845 adev->gfx.me_fw = NULL;
846 release_firmware(adev->gfx.ce_fw);
847 adev->gfx.ce_fw = NULL;
848 release_firmware(adev->gfx.rlc_fw);
849 adev->gfx.rlc_fw = NULL;
850 release_firmware(adev->gfx.mec_fw);
851 adev->gfx.mec_fw = NULL;
852 if ((adev->asic_type != CHIP_STONEY) &&
853 (adev->asic_type != CHIP_TOPAZ))
854 release_firmware(adev->gfx.mec2_fw);
855 adev->gfx.mec2_fw = NULL;
856
857 kfree(adev->gfx.rlc.register_list_format);
858}
859
aaa36a97
AD		 860static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
861{
862 const char *chip_name;
863 char fw_name[30];
864 int err;
865 struct amdgpu_firmware_info *info = NULL;
866 const struct common_firmware_header *header = NULL;
595fd013 867 const struct gfx_firmware_header_v1_0 *cp_hdr;
2b6cd977
EH		 868 const struct rlc_firmware_header_v2_0 *rlc_hdr;
869 unsigned int *tmp = NULL, i;
aaa36a97
AD		 870
871 DRM_DEBUG("\n");
872
873 switch (adev->asic_type) {
874 case CHIP_TOPAZ:
875 chip_name = "topaz";
876 break;
877 case CHIP_TONGA:
878 chip_name = "tonga";
879 break;
880 case CHIP_CARRIZO:
881 chip_name = "carrizo";
882 break;
af15a2d5
DZ		 883 case CHIP_FIJI:
884 chip_name = "fiji";
885 break;
2cc0c0b5
FC		 886 case CHIP_POLARIS11:
887 chip_name = "polaris11";
68182d90 888 break;
2cc0c0b5
FC		 889 case CHIP_POLARIS10:
890 chip_name = "polaris10";
68182d90 891 break;
e3c7656c
SL		 892 case CHIP_STONEY:
893 chip_name = "stoney";
894 break;
aaa36a97
AD		 895 default:
896 BUG();
897 }
898
c65444fe 899 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
aaa36a97
AD		 900 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
901 if (err)
902 goto out;
903 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
904 if (err)
905 goto out;
595fd013
JZ		 906 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
907 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
908 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 909
c65444fe 910 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
aaa36a97
AD		 911 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
912 if (err)
913 goto out;
914 err = amdgpu_ucode_validate(adev->gfx.me_fw);
915 if (err)
916 goto out;
595fd013
JZ		 917 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
918 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
919 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 920
c65444fe 921 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
aaa36a97
AD		 922 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
923 if (err)
924 goto out;
925 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
926 if (err)
927 goto out;
595fd013
JZ		 928 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
929 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
930 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 931
c65444fe 932 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
aaa36a97
AD		 933 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
934 if (err)
935 goto out;
936 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
2b6cd977
EH		 937 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
938 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
939 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
940
941 adev->gfx.rlc.save_and_restore_offset =
942 le32_to_cpu(rlc_hdr->save_and_restore_offset);
943 adev->gfx.rlc.clear_state_descriptor_offset =
944 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
945 adev->gfx.rlc.avail_scratch_ram_locations =
946 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
947 adev->gfx.rlc.reg_restore_list_size =
948 le32_to_cpu(rlc_hdr->reg_restore_list_size);
949 adev->gfx.rlc.reg_list_format_start =
950 le32_to_cpu(rlc_hdr->reg_list_format_start);
951 adev->gfx.rlc.reg_list_format_separate_start =
952 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
953 adev->gfx.rlc.starting_offsets_start =
954 le32_to_cpu(rlc_hdr->starting_offsets_start);
955 adev->gfx.rlc.reg_list_format_size_bytes =
956 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
957 adev->gfx.rlc.reg_list_size_bytes =
958 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
959
960 adev->gfx.rlc.register_list_format =
961 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
962 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
963
964 if (!adev->gfx.rlc.register_list_format) {
965 err = -ENOMEM;
966 goto out;
967 }
968
ae17c999 969 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
2b6cd977
EH		 970 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
971 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
972 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
973
974 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
975
ae17c999 976 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
2b6cd977
EH		 977 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
978 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
979 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
aaa36a97 980
c65444fe 981 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
aaa36a97
AD		 982 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
983 if (err)
984 goto out;
985 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
986 if (err)
987 goto out;
595fd013
JZ		 988 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
989 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
990 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 991
97dde76a
AD		 992 if ((adev->asic_type != CHIP_STONEY) &&
993 (adev->asic_type != CHIP_TOPAZ)) {
e3c7656c
SL		 994 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
995 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
996 if (!err) {
997 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
998 if (err)
999 goto out;
1000 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1001 adev->gfx.mec2_fw->data;
1002 adev->gfx.mec2_fw_version =
1003 le32_to_cpu(cp_hdr->header.ucode_version);
1004 adev->gfx.mec2_feature_version =
1005 le32_to_cpu(cp_hdr->ucode_feature_version);
1006 } else {
1007 err = 0;
1008 adev->gfx.mec2_fw = NULL;
1009 }
aaa36a97
AD		 1010 }
1011
1012 if (adev->firmware.smu_load) {
1013 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1014 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1015 info->fw = adev->gfx.pfp_fw;
1016 header = (const struct common_firmware_header *)info->fw->data;
1017 adev->firmware.fw_size +=
1018 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1019
1020 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1021 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1022 info->fw = adev->gfx.me_fw;
1023 header = (const struct common_firmware_header *)info->fw->data;
1024 adev->firmware.fw_size +=
1025 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1026
1027 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1028 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1029 info->fw = adev->gfx.ce_fw;
1030 header = (const struct common_firmware_header *)info->fw->data;
1031 adev->firmware.fw_size +=
1032 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1033
1034 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1035 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1036 info->fw = adev->gfx.rlc_fw;
1037 header = (const struct common_firmware_header *)info->fw->data;
1038 adev->firmware.fw_size +=
1039 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1040
1041 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1042 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1043 info->fw = adev->gfx.mec_fw;
1044 header = (const struct common_firmware_header *)info->fw->data;
1045 adev->firmware.fw_size +=
1046 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1047
1048 if (adev->gfx.mec2_fw) {
1049 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1050 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1051 info->fw = adev->gfx.mec2_fw;
1052 header = (const struct common_firmware_header *)info->fw->data;
1053 adev->firmware.fw_size +=
1054 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1055 }
1056
1057 }
1058
1059out:
1060 if (err) {
1061 dev_err(adev->dev,
1062 "gfx8: Failed to load firmware \"%s\"\n",
1063 fw_name);
1064 release_firmware(adev->gfx.pfp_fw);
1065 adev->gfx.pfp_fw = NULL;
1066 release_firmware(adev->gfx.me_fw);
1067 adev->gfx.me_fw = NULL;
1068 release_firmware(adev->gfx.ce_fw);
1069 adev->gfx.ce_fw = NULL;
1070 release_firmware(adev->gfx.rlc_fw);
1071 adev->gfx.rlc_fw = NULL;
1072 release_firmware(adev->gfx.mec_fw);
1073 adev->gfx.mec_fw = NULL;
1074 release_firmware(adev->gfx.mec2_fw);
1075 adev->gfx.mec2_fw = NULL;
1076 }
1077 return err;
1078}
1079
2b6cd977
EH		 1080static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1081 volatile u32 *buffer)
1082{
1083 u32 count = 0, i;
1084 const struct cs_section_def *sect = NULL;
1085 const struct cs_extent_def *ext = NULL;
1086
1087 if (adev->gfx.rlc.cs_data == NULL)
1088 return;
1089 if (buffer == NULL)
1090 return;
1091
1092 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1093 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1094
1095 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1096 buffer[count++] = cpu_to_le32(0x80000000);
1097 buffer[count++] = cpu_to_le32(0x80000000);
1098
1099 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1100 for (ext = sect->section; ext->extent != NULL; ++ext) {
1101 if (sect->id == SECT_CONTEXT) {
1102 buffer[count++] =
1103 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1104 buffer[count++] = cpu_to_le32(ext->reg_index -
1105 PACKET3_SET_CONTEXT_REG_START);
1106 for (i = 0; i < ext->reg_count; i++)
1107 buffer[count++] = cpu_to_le32(ext->extent[i]);
1108 } else {
1109 return;
1110 }
1111 }
1112 }
1113
1114 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1115 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1116 PACKET3_SET_CONTEXT_REG_START);
1117 switch (adev->asic_type) {
1118 case CHIP_TONGA:
2cc0c0b5 1119 case CHIP_POLARIS10:
2b6cd977
EH		 1120 buffer[count++] = cpu_to_le32(0x16000012);
1121 buffer[count++] = cpu_to_le32(0x0000002A);
1122 break;
2cc0c0b5 1123 case CHIP_POLARIS11:
f4bfffdd
EH		 1124 buffer[count++] = cpu_to_le32(0x16000012);
1125 buffer[count++] = cpu_to_le32(0x00000000);
1126 break;
2b6cd977
EH		 1127 case CHIP_FIJI:
1128 buffer[count++] = cpu_to_le32(0x3a00161a);
1129 buffer[count++] = cpu_to_le32(0x0000002e);
1130 break;
1131 case CHIP_TOPAZ:
1132 case CHIP_CARRIZO:
1133 buffer[count++] = cpu_to_le32(0x00000002);
1134 buffer[count++] = cpu_to_le32(0x00000000);
1135 break;
1136 case CHIP_STONEY:
1137 buffer[count++] = cpu_to_le32(0x00000000);
1138 buffer[count++] = cpu_to_le32(0x00000000);
1139 break;
1140 default:
1141 buffer[count++] = cpu_to_le32(0x00000000);
1142 buffer[count++] = cpu_to_le32(0x00000000);
1143 break;
1144 }
1145
1146 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1147 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1148
1149 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1150 buffer[count++] = cpu_to_le32(0);
1151}
1152
fb16007b
AD		 1153static void cz_init_cp_jump_table(struct amdgpu_device *adev)
1154{
1155 const __le32 *fw_data;
1156 volatile u32 *dst_ptr;
1157 int me, i, max_me = 4;
1158 u32 bo_offset = 0;
1159 u32 table_offset, table_size;
1160
1161 if (adev->asic_type == CHIP_CARRIZO)
1162 max_me = 5;
1163
1164 /* write the cp table buffer */
1165 dst_ptr = adev->gfx.rlc.cp_table_ptr;
1166 for (me = 0; me < max_me; me++) {
1167 if (me == 0) {
1168 const struct gfx_firmware_header_v1_0 *hdr =
1169 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1170 fw_data = (const __le32 *)
1171 (adev->gfx.ce_fw->data +
1172 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1173 table_offset = le32_to_cpu(hdr->jt_offset);
1174 table_size = le32_to_cpu(hdr->jt_size);
1175 } else if (me == 1) {
1176 const struct gfx_firmware_header_v1_0 *hdr =
1177 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1178 fw_data = (const __le32 *)
1179 (adev->gfx.pfp_fw->data +
1180 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1181 table_offset = le32_to_cpu(hdr->jt_offset);
1182 table_size = le32_to_cpu(hdr->jt_size);
1183 } else if (me == 2) {
1184 const struct gfx_firmware_header_v1_0 *hdr =
1185 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1186 fw_data = (const __le32 *)
1187 (adev->gfx.me_fw->data +
1188 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1189 table_offset = le32_to_cpu(hdr->jt_offset);
1190 table_size = le32_to_cpu(hdr->jt_size);
1191 } else if (me == 3) {
1192 const struct gfx_firmware_header_v1_0 *hdr =
1193 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1194 fw_data = (const __le32 *)
1195 (adev->gfx.mec_fw->data +
1196 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1197 table_offset = le32_to_cpu(hdr->jt_offset);
1198 table_size = le32_to_cpu(hdr->jt_size);
1199 } else if (me == 4) {
1200 const struct gfx_firmware_header_v1_0 *hdr =
1201 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
1202 fw_data = (const __le32 *)
1203 (adev->gfx.mec2_fw->data +
1204 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1205 table_offset = le32_to_cpu(hdr->jt_offset);
1206 table_size = le32_to_cpu(hdr->jt_size);
1207 }
1208
1209 for (i = 0; i < table_size; i ++) {
1210 dst_ptr[bo_offset + i] =
1211 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
1212 }
1213
1214 bo_offset += table_size;
1215 }
1216}
1217
2b6cd977
EH		 1218static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
1219{
1220 int r;
1221
1222 /* clear state block */
1223 if (adev->gfx.rlc.clear_state_obj) {
1224 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1225 if (unlikely(r != 0))
1226 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
1227 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1228 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1229
1230 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
1231 adev->gfx.rlc.clear_state_obj = NULL;
1232 }
fb16007b
AD		 1233
1234 /* jump table block */
1235 if (adev->gfx.rlc.cp_table_obj) {
1236 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
1237 if (unlikely(r != 0))
1238 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
1239 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
1240 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1241
1242 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
1243 adev->gfx.rlc.cp_table_obj = NULL;
1244 }
2b6cd977
EH		 1245}
1246
1247static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1248{
1249 volatile u32 *dst_ptr;
1250 u32 dws;
1251 const struct cs_section_def *cs_data;
1252 int r;
1253
1254 adev->gfx.rlc.cs_data = vi_cs_data;
1255
1256 cs_data = adev->gfx.rlc.cs_data;
1257
1258 if (cs_data) {
1259 /* clear state block */
1260 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev);
1261
1262 if (adev->gfx.rlc.clear_state_obj == NULL) {
1263 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
1264 AMDGPU_GEM_DOMAIN_VRAM,
1265 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1266 NULL, NULL,
1267 &adev->gfx.rlc.clear_state_obj);
1268 if (r) {
1269 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
1270 gfx_v8_0_rlc_fini(adev);
1271 return r;
1272 }
1273 }
1274 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1275 if (unlikely(r != 0)) {
1276 gfx_v8_0_rlc_fini(adev);
1277 return r;
1278 }
1279 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
1280 &adev->gfx.rlc.clear_state_gpu_addr);
1281 if (r) {
1282 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1283 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
1284 gfx_v8_0_rlc_fini(adev);
1285 return r;
1286 }
1287
1288 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
1289 if (r) {
1290 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
1291 gfx_v8_0_rlc_fini(adev);
1292 return r;
1293 }
1294 /* set up the cs buffer */
1295 dst_ptr = adev->gfx.rlc.cs_ptr;
1296 gfx_v8_0_get_csb_buffer(adev, dst_ptr);
1297 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1298 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1299 }
1300
fb16007b
AD		 1301 if ((adev->asic_type == CHIP_CARRIZO) ||
1302 (adev->asic_type == CHIP_STONEY)) {
07cf1a0b 1303 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
fb16007b
AD		 1304 if (adev->gfx.rlc.cp_table_obj == NULL) {
1305 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
1306 AMDGPU_GEM_DOMAIN_VRAM,
1307 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1308 NULL, NULL,
1309 &adev->gfx.rlc.cp_table_obj);
1310 if (r) {
1311 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
1312 return r;
1313 }
1314 }
1315
1316 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
1317 if (unlikely(r != 0)) {
1318 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
1319 return r;
1320 }
1321 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
1322 &adev->gfx.rlc.cp_table_gpu_addr);
1323 if (r) {
1324 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1325 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
1326 return r;
1327 }
1328 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
1329 if (r) {
1330 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
1331 return r;
1332 }
1333
1334 cz_init_cp_jump_table(adev);
1335
1336 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
1337 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1338
1339 }
1340
2b6cd977
EH		 1341 return 0;
1342}
1343
aaa36a97
AD		 1344static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1345{
1346 int r;
1347
1348 if (adev->gfx.mec.hpd_eop_obj) {
1349 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
1350 if (unlikely(r != 0))
1351 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
1352 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
1353 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1354
1355 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
1356 adev->gfx.mec.hpd_eop_obj = NULL;
1357 }
1358}
1359
1360#define MEC_HPD_SIZE 2048
1361
1362static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1363{
1364 int r;
1365 u32 *hpd;
1366
1367 /*
1368 * we assign only 1 pipe because all other pipes will
1369 * be handled by KFD
1370 */
1371 adev->gfx.mec.num_mec = 1;
1372 adev->gfx.mec.num_pipe = 1;
1373 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
1374
1375 if (adev->gfx.mec.hpd_eop_obj == NULL) {
1376 r = amdgpu_bo_create(adev,
1377 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
1378 PAGE_SIZE, true,
72d7668b 1379 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
aaa36a97
AD		 1380 &adev->gfx.mec.hpd_eop_obj);
1381 if (r) {
1382 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1383 return r;
1384 }
1385 }
1386
1387 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
1388 if (unlikely(r != 0)) {
1389 gfx_v8_0_mec_fini(adev);
1390 return r;
1391 }
1392 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
1393 &adev->gfx.mec.hpd_eop_gpu_addr);
1394 if (r) {
1395 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
1396 gfx_v8_0_mec_fini(adev);
1397 return r;
1398 }
1399 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
1400 if (r) {
1401 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
1402 gfx_v8_0_mec_fini(adev);
1403 return r;
1404 }
1405
1406 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
1407
1408 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1409 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1410
1411 return 0;
1412}
1413
ccba7691
AD		 1414static const u32 vgpr_init_compute_shader[] =
1415{
1416 0x7e000209, 0x7e020208,
1417 0x7e040207, 0x7e060206,
1418 0x7e080205, 0x7e0a0204,
1419 0x7e0c0203, 0x7e0e0202,
1420 0x7e100201, 0x7e120200,
1421 0x7e140209, 0x7e160208,
1422 0x7e180207, 0x7e1a0206,
1423 0x7e1c0205, 0x7e1e0204,
1424 0x7e200203, 0x7e220202,
1425 0x7e240201, 0x7e260200,
1426 0x7e280209, 0x7e2a0208,
1427 0x7e2c0207, 0x7e2e0206,
1428 0x7e300205, 0x7e320204,
1429 0x7e340203, 0x7e360202,
1430 0x7e380201, 0x7e3a0200,
1431 0x7e3c0209, 0x7e3e0208,
1432 0x7e400207, 0x7e420206,
1433 0x7e440205, 0x7e460204,
1434 0x7e480203, 0x7e4a0202,
1435 0x7e4c0201, 0x7e4e0200,
1436 0x7e500209, 0x7e520208,
1437 0x7e540207, 0x7e560206,
1438 0x7e580205, 0x7e5a0204,
1439 0x7e5c0203, 0x7e5e0202,
1440 0x7e600201, 0x7e620200,
1441 0x7e640209, 0x7e660208,
1442 0x7e680207, 0x7e6a0206,
1443 0x7e6c0205, 0x7e6e0204,
1444 0x7e700203, 0x7e720202,
1445 0x7e740201, 0x7e760200,
1446 0x7e780209, 0x7e7a0208,
1447 0x7e7c0207, 0x7e7e0206,
1448 0xbf8a0000, 0xbf810000,
1449};
1450
1451static const u32 sgpr_init_compute_shader[] =
1452{
1453 0xbe8a0100, 0xbe8c0102,
1454 0xbe8e0104, 0xbe900106,
1455 0xbe920108, 0xbe940100,
1456 0xbe960102, 0xbe980104,
1457 0xbe9a0106, 0xbe9c0108,
1458 0xbe9e0100, 0xbea00102,
1459 0xbea20104, 0xbea40106,
1460 0xbea60108, 0xbea80100,
1461 0xbeaa0102, 0xbeac0104,
1462 0xbeae0106, 0xbeb00108,
1463 0xbeb20100, 0xbeb40102,
1464 0xbeb60104, 0xbeb80106,
1465 0xbeba0108, 0xbebc0100,
1466 0xbebe0102, 0xbec00104,
1467 0xbec20106, 0xbec40108,
1468 0xbec60100, 0xbec80102,
1469 0xbee60004, 0xbee70005,
1470 0xbeea0006, 0xbeeb0007,
1471 0xbee80008, 0xbee90009,
1472 0xbefc0000, 0xbf8a0000,
1473 0xbf810000, 0x00000000,
1474};
1475
1476static const u32 vgpr_init_regs[] =
1477{
1478 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1479 mmCOMPUTE_RESOURCE_LIMITS, 0,
1480 mmCOMPUTE_NUM_THREAD_X, 256*4,
1481 mmCOMPUTE_NUM_THREAD_Y, 1,
1482 mmCOMPUTE_NUM_THREAD_Z, 1,
1483 mmCOMPUTE_PGM_RSRC2, 20,
1484 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1485 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1486 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1487 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1488 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1489 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1490 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1491 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1492 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1493 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1494};
1495
1496static const u32 sgpr1_init_regs[] =
1497{
1498 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1499 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1500 mmCOMPUTE_NUM_THREAD_X, 256*5,
1501 mmCOMPUTE_NUM_THREAD_Y, 1,
1502 mmCOMPUTE_NUM_THREAD_Z, 1,
1503 mmCOMPUTE_PGM_RSRC2, 20,
1504 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1505 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1506 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1507 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1508 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1509 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1510 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1511 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1512 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1513 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1514};
1515
1516static const u32 sgpr2_init_regs[] =
1517{
1518 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1519 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1520 mmCOMPUTE_NUM_THREAD_X, 256*5,
1521 mmCOMPUTE_NUM_THREAD_Y, 1,
1522 mmCOMPUTE_NUM_THREAD_Z, 1,
1523 mmCOMPUTE_PGM_RSRC2, 20,
1524 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1525 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1526 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1527 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1528 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1529 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1530 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1531 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1532 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1533 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1534};
1535
1536static const u32 sec_ded_counter_registers[] =
1537{
1538 mmCPC_EDC_ATC_CNT,
1539 mmCPC_EDC_SCRATCH_CNT,
1540 mmCPC_EDC_UCODE_CNT,
1541 mmCPF_EDC_ATC_CNT,
1542 mmCPF_EDC_ROQ_CNT,
1543 mmCPF_EDC_TAG_CNT,
1544 mmCPG_EDC_ATC_CNT,
1545 mmCPG_EDC_DMA_CNT,
1546 mmCPG_EDC_TAG_CNT,
1547 mmDC_EDC_CSINVOC_CNT,
1548 mmDC_EDC_RESTORE_CNT,
1549 mmDC_EDC_STATE_CNT,
1550 mmGDS_EDC_CNT,
1551 mmGDS_EDC_GRBM_CNT,
1552 mmGDS_EDC_OA_DED,
1553 mmSPI_EDC_CNT,
1554 mmSQC_ATC_EDC_GATCL1_CNT,
1555 mmSQC_EDC_CNT,
1556 mmSQ_EDC_DED_CNT,
1557 mmSQ_EDC_INFO,
1558 mmSQ_EDC_SEC_CNT,
1559 mmTCC_EDC_CNT,
1560 mmTCP_ATC_EDC_GATCL1_CNT,
1561 mmTCP_EDC_CNT,
1562 mmTD_EDC_CNT
1563};
1564
1565static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1566{
1567 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1568 struct amdgpu_ib ib;
1569 struct fence *f = NULL;
1570 int r, i;
1571 u32 tmp;
1572 unsigned total_size, vgpr_offset, sgpr_offset;
1573 u64 gpu_addr;
1574
1575 /* only supported on CZ */
1576 if (adev->asic_type != CHIP_CARRIZO)
1577 return 0;
1578
1579 /* bail if the compute ring is not ready */
1580 if (!ring->ready)
1581 return 0;
1582
1583 tmp = RREG32(mmGB_EDC_MODE);
1584 WREG32(mmGB_EDC_MODE, 0);
1585
1586 total_size =
1587 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1588 total_size +=
1589 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1590 total_size +=
1591 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1592 total_size = ALIGN(total_size, 256);
1593 vgpr_offset = total_size;
1594 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1595 sgpr_offset = total_size;
1596 total_size += sizeof(sgpr_init_compute_shader);
1597
1598 /* allocate an indirect buffer to put the commands in */
1599 memset(&ib, 0, sizeof(ib));
b07c60c0 1600 r = amdgpu_ib_get(adev, NULL, total_size, &ib);
ccba7691
AD		 1601 if (r) {
1602 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1603 return r;
1604 }
1605
1606 /* load the compute shaders */
1607 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1608 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1609
1610 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1611 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1612
1613 /* init the ib length to 0 */
1614 ib.length_dw = 0;
1615
1616 /* VGPR */
1617 /* write the register state for the compute dispatch */
1618 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1619 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1620 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1621 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1622 }
1623 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1624 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1625 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1626 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1627 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1628 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1629
1630 /* write dispatch packet */
1631 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1632 ib.ptr[ib.length_dw++] = 8; /* x */
1633 ib.ptr[ib.length_dw++] = 1; /* y */
1634 ib.ptr[ib.length_dw++] = 1; /* z */
1635 ib.ptr[ib.length_dw++] =
1636 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1637
1638 /* write CS partial flush packet */
1639 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1640 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1641
1642 /* SGPR1 */
1643 /* write the register state for the compute dispatch */
1644 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1645 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1646 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1647 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1648 }
1649 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1650 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1651 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1652 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1653 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1654 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1655
1656 /* write dispatch packet */
1657 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1658 ib.ptr[ib.length_dw++] = 8; /* x */
1659 ib.ptr[ib.length_dw++] = 1; /* y */
1660 ib.ptr[ib.length_dw++] = 1; /* z */
1661 ib.ptr[ib.length_dw++] =
1662 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1663
1664 /* write CS partial flush packet */
1665 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1666 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1667
1668 /* SGPR2 */
1669 /* write the register state for the compute dispatch */
1670 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1671 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1672 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1673 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1674 }
1675 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1676 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1677 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1678 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1679 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1680 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1681
1682 /* write dispatch packet */
1683 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1684 ib.ptr[ib.length_dw++] = 8; /* x */
1685 ib.ptr[ib.length_dw++] = 1; /* y */
1686 ib.ptr[ib.length_dw++] = 1; /* z */
1687 ib.ptr[ib.length_dw++] =
1688 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1689
1690 /* write CS partial flush packet */
1691 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1692 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1693
1694 /* shedule the ib on the ring */
c5637837 1695 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
ccba7691
AD		 1696 if (r) {
1697 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1698 goto fail;
1699 }
1700
1701 /* wait for the GPU to finish processing the IB */
1702 r = fence_wait(f, false);
1703 if (r) {
1704 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1705 goto fail;
1706 }
1707
1708 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1709 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1710 WREG32(mmGB_EDC_MODE, tmp);
1711
1712 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1713 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1714 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1715
1716
1717 /* read back registers to clear the counters */
1718 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1719 RREG32(sec_ded_counter_registers[i]);
1720
1721fail:
1722 fence_put(f);
cc55c45d 1723 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 1724 fence_put(f);
ccba7691
AD		 1725
1726 return r;
1727}
1728
68182d90 1729static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
0bde3a95
AD		 1730{
1731 u32 gb_addr_config;
1732 u32 mc_shared_chmap, mc_arb_ramcfg;
1733 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1734 u32 tmp;
68182d90 1735 int ret;
0bde3a95
AD		 1736
1737 switch (adev->asic_type) {
1738 case CHIP_TOPAZ:
1739 adev->gfx.config.max_shader_engines = 1;
1740 adev->gfx.config.max_tile_pipes = 2;
1741 adev->gfx.config.max_cu_per_sh = 6;
1742 adev->gfx.config.max_sh_per_se = 1;
1743 adev->gfx.config.max_backends_per_se = 2;
1744 adev->gfx.config.max_texture_channel_caches = 2;
1745 adev->gfx.config.max_gprs = 256;
1746 adev->gfx.config.max_gs_threads = 32;
1747 adev->gfx.config.max_hw_contexts = 8;
1748
1749 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1750 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1751 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1752 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1753 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1754 break;
1755 case CHIP_FIJI:
1756 adev->gfx.config.max_shader_engines = 4;
1757 adev->gfx.config.max_tile_pipes = 16;
1758 adev->gfx.config.max_cu_per_sh = 16;
1759 adev->gfx.config.max_sh_per_se = 1;
1760 adev->gfx.config.max_backends_per_se = 4;
5f2e816b 1761 adev->gfx.config.max_texture_channel_caches = 16;
0bde3a95
AD		 1762 adev->gfx.config.max_gprs = 256;
1763 adev->gfx.config.max_gs_threads = 32;
1764 adev->gfx.config.max_hw_contexts = 8;
1765
68182d90
FC		 1766 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1767 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1768 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1769 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1770 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1771 break;
2cc0c0b5 1772 case CHIP_POLARIS11:
68182d90
FC		 1773 ret = amdgpu_atombios_get_gfx_info(adev);
1774 if (ret)
1775 return ret;
1776 adev->gfx.config.max_gprs = 256;
1777 adev->gfx.config.max_gs_threads = 32;
1778 adev->gfx.config.max_hw_contexts = 8;
1779
1780 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1781 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1782 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1783 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2cc0c0b5 1784 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
68182d90 1785 break;
2cc0c0b5 1786 case CHIP_POLARIS10:
68182d90
FC		 1787 ret = amdgpu_atombios_get_gfx_info(adev);
1788 if (ret)
1789 return ret;
1790 adev->gfx.config.max_gprs = 256;
1791 adev->gfx.config.max_gs_threads = 32;
1792 adev->gfx.config.max_hw_contexts = 8;
1793
0bde3a95
AD		 1794 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1795 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1796 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1797 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1798 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1799 break;
1800 case CHIP_TONGA:
1801 adev->gfx.config.max_shader_engines = 4;
1802 adev->gfx.config.max_tile_pipes = 8;
1803 adev->gfx.config.max_cu_per_sh = 8;
1804 adev->gfx.config.max_sh_per_se = 1;
1805 adev->gfx.config.max_backends_per_se = 2;
1806 adev->gfx.config.max_texture_channel_caches = 8;
1807 adev->gfx.config.max_gprs = 256;
1808 adev->gfx.config.max_gs_threads = 32;
1809 adev->gfx.config.max_hw_contexts = 8;
1810
1811 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1812 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1813 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1814 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1815 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1816 break;
1817 case CHIP_CARRIZO:
1818 adev->gfx.config.max_shader_engines = 1;
1819 adev->gfx.config.max_tile_pipes = 2;
1820 adev->gfx.config.max_sh_per_se = 1;
1821 adev->gfx.config.max_backends_per_se = 2;
1822
1823 switch (adev->pdev->revision) {
1824 case 0xc4:
1825 case 0x84:
1826 case 0xc8:
1827 case 0xcc:
b8b339ea
AD		 1828 case 0xe1:
1829 case 0xe3:
0bde3a95
AD		 1830 /* B10 */
1831 adev->gfx.config.max_cu_per_sh = 8;
1832 break;
1833 case 0xc5:
1834 case 0x81:
1835 case 0x85:
1836 case 0xc9:
1837 case 0xcd:
b8b339ea
AD		 1838 case 0xe2:
1839 case 0xe4:
0bde3a95
AD		 1840 /* B8 */
1841 adev->gfx.config.max_cu_per_sh = 6;
1842 break;
1843 case 0xc6:
1844 case 0xca:
1845 case 0xce:
b8b339ea 1846 case 0x88:
0bde3a95
AD		 1847 /* B6 */
1848 adev->gfx.config.max_cu_per_sh = 6;
1849 break;
1850 case 0xc7:
1851 case 0x87:
1852 case 0xcb:
b8b339ea
AD		 1853 case 0xe5:
1854 case 0x89:
0bde3a95
AD		 1855 default:
1856 /* B4 */
1857 adev->gfx.config.max_cu_per_sh = 4;
1858 break;
1859 }
1860
1861 adev->gfx.config.max_texture_channel_caches = 2;
1862 adev->gfx.config.max_gprs = 256;
1863 adev->gfx.config.max_gs_threads = 32;
1864 adev->gfx.config.max_hw_contexts = 8;
1865
e3c7656c
SL		 1866 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1867 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1868 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1869 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1870 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1871 break;
1872 case CHIP_STONEY:
1873 adev->gfx.config.max_shader_engines = 1;
1874 adev->gfx.config.max_tile_pipes = 2;
1875 adev->gfx.config.max_sh_per_se = 1;
1876 adev->gfx.config.max_backends_per_se = 1;
1877
1878 switch (adev->pdev->revision) {
1879 case 0xc0:
1880 case 0xc1:
1881 case 0xc2:
1882 case 0xc4:
1883 case 0xc8:
1884 case 0xc9:
1885 adev->gfx.config.max_cu_per_sh = 3;
1886 break;
1887 case 0xd0:
1888 case 0xd1:
1889 case 0xd2:
1890 default:
1891 adev->gfx.config.max_cu_per_sh = 2;
1892 break;
1893 }
1894
1895 adev->gfx.config.max_texture_channel_caches = 2;
1896 adev->gfx.config.max_gprs = 256;
1897 adev->gfx.config.max_gs_threads = 16;
1898 adev->gfx.config.max_hw_contexts = 8;
1899
0bde3a95
AD		 1900 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1901 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1902 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1903 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1904 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1905 break;
1906 default:
1907 adev->gfx.config.max_shader_engines = 2;
1908 adev->gfx.config.max_tile_pipes = 4;
1909 adev->gfx.config.max_cu_per_sh = 2;
1910 adev->gfx.config.max_sh_per_se = 1;
1911 adev->gfx.config.max_backends_per_se = 2;
1912 adev->gfx.config.max_texture_channel_caches = 4;
1913 adev->gfx.config.max_gprs = 256;
1914 adev->gfx.config.max_gs_threads = 32;
1915 adev->gfx.config.max_hw_contexts = 8;
1916
1917 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1918 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1919 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1920 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1921 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1922 break;
1923 }
1924
1925 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1926 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1927 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1928
1929 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1930 adev->gfx.config.mem_max_burst_length_bytes = 256;
1931 if (adev->flags & AMD_IS_APU) {
1932 /* Get memory bank mapping mode. */
1933 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1934 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1935 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1936
1937 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1938 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1939 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1940
1941 /* Validate settings in case only one DIMM installed. */
1942 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1943 dimm00_addr_map = 0;
1944 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1945 dimm01_addr_map = 0;
1946 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1947 dimm10_addr_map = 0;
1948 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1949 dimm11_addr_map = 0;
1950
1951 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1952 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1953 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1954 adev->gfx.config.mem_row_size_in_kb = 2;
1955 else
1956 adev->gfx.config.mem_row_size_in_kb = 1;
1957 } else {
1958 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1959 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1960 if (adev->gfx.config.mem_row_size_in_kb > 4)
1961 adev->gfx.config.mem_row_size_in_kb = 4;
1962 }
1963
1964 adev->gfx.config.shader_engine_tile_size = 32;
1965 adev->gfx.config.num_gpus = 1;
1966 adev->gfx.config.multi_gpu_tile_size = 64;
1967
1968 /* fix up row size */
1969 switch (adev->gfx.config.mem_row_size_in_kb) {
1970 case 1:
1971 default:
1972 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1973 break;
1974 case 2:
1975 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1976 break;
1977 case 4:
1978 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1979 break;
1980 }
1981 adev->gfx.config.gb_addr_config = gb_addr_config;
68182d90
FC		 1982
1983 return 0;
0bde3a95
AD		 1984}
1985
5fc3aeeb 1986static int gfx_v8_0_sw_init(void *handle)
aaa36a97
AD		 1987{
1988 int i, r;
1989 struct amdgpu_ring *ring;
5fc3aeeb 1990 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1991
1992 /* EOP Event */
1993 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
1994 if (r)
1995 return r;
1996
1997 /* Privileged reg */
1998 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
1999 if (r)
2000 return r;
2001
2002 /* Privileged inst */
2003 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
2004 if (r)
2005 return r;
2006
2007 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
2008
2009 gfx_v8_0_scratch_init(adev);
2010
2011 r = gfx_v8_0_init_microcode(adev);
2012 if (r) {
2013 DRM_ERROR("Failed to load gfx firmware!\n");
2014 return r;
2015 }
2016
2b6cd977
EH		 2017 r = gfx_v8_0_rlc_init(adev);
2018 if (r) {
2019 DRM_ERROR("Failed to init rlc BOs!\n");
2020 return r;
2021 }
2022
aaa36a97
AD		 2023 r = gfx_v8_0_mec_init(adev);
2024 if (r) {
2025 DRM_ERROR("Failed to init MEC BOs!\n");
2026 return r;
2027 }
2028
aaa36a97
AD		 2029 /* set up the gfx ring */
2030 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2031 ring = &adev->gfx.gfx_ring[i];
2032 ring->ring_obj = NULL;
2033 sprintf(ring->name, "gfx");
2034 /* no gfx doorbells on iceland */
2035 if (adev->asic_type != CHIP_TOPAZ) {
2036 ring->use_doorbell = true;
2037 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
2038 }
2039
2800de2e 2040 r = amdgpu_ring_init(adev, ring, 1024,
aaa36a97
AD		 2041 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
2042 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
2043 AMDGPU_RING_TYPE_GFX);
2044 if (r)
2045 return r;
2046 }
2047
2048 /* set up the compute queues */
2049 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2050 unsigned irq_type;
2051
2052 /* max 32 queues per MEC */
2053 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
2054 DRM_ERROR("Too many (%d) compute rings!\n", i);
2055 break;
2056 }
2057 ring = &adev->gfx.compute_ring[i];
2058 ring->ring_obj = NULL;
2059 ring->use_doorbell = true;
2060 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
2061 ring->me = 1; /* first MEC */
2062 ring->pipe = i / 8;
2063 ring->queue = i % 8;
771c8ec1 2064 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
aaa36a97
AD		 2065 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2066 /* type-2 packets are deprecated on MEC, use type-3 instead */
2800de2e 2067 r = amdgpu_ring_init(adev, ring, 1024,
aaa36a97
AD		 2068 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
2069 &adev->gfx.eop_irq, irq_type,
2070 AMDGPU_RING_TYPE_COMPUTE);
2071 if (r)
2072 return r;
2073 }
2074
2075 /* reserve GDS, GWS and OA resource for gfx */
2076 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
2077 PAGE_SIZE, true,
72d7668b 2078 AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
aaa36a97
AD		 2079 NULL, &adev->gds.gds_gfx_bo);
2080 if (r)
2081 return r;
2082
2083 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
2084 PAGE_SIZE, true,
72d7668b 2085 AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
aaa36a97
AD		 2086 NULL, &adev->gds.gws_gfx_bo);
2087 if (r)
2088 return r;
2089
2090 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
2091 PAGE_SIZE, true,
72d7668b 2092 AMDGPU_GEM_DOMAIN_OA, 0, NULL,
aaa36a97
AD		 2093 NULL, &adev->gds.oa_gfx_bo);
2094 if (r)
2095 return r;
2096
a101a899
KW		 2097 adev->gfx.ce_ram_size = 0x8000;
2098
68182d90
FC		 2099 r = gfx_v8_0_gpu_early_init(adev);
2100 if (r)
2101 return r;
0bde3a95 2102
aaa36a97
AD		 2103 return 0;
2104}
2105
5fc3aeeb 2106static int gfx_v8_0_sw_fini(void *handle)
aaa36a97
AD		 2107{
2108 int i;
5fc3aeeb 2109 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 2110
2111 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
2112 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
2113 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
2114
2115 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2116 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2117 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2118 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2119
aaa36a97
AD		 2120 gfx_v8_0_mec_fini(adev);
2121
2b6cd977
EH		 2122 gfx_v8_0_rlc_fini(adev);
2123
13331ac3 2124 gfx_v8_0_free_microcode(adev);
2b6cd977 2125
aaa36a97
AD		 2126 return 0;
2127}
2128
2129static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2130{
90bea0ab 2131 uint32_t *modearray, *mod2array;
eb64526f
TSD		 2132 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2133 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
90bea0ab 2134 u32 reg_offset;
aaa36a97 2135
90bea0ab
TSD		 2136 modearray = adev->gfx.config.tile_mode_array;
2137 mod2array = adev->gfx.config.macrotile_mode_array;
2138
2139 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2140 modearray[reg_offset] = 0;
2141
2142 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2143 mod2array[reg_offset] = 0;
aaa36a97
AD		 2144
2145 switch (adev->asic_type) {
2146 case CHIP_TOPAZ:
90bea0ab
TSD		 2147 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2148 PIPE_CONFIG(ADDR_SURF_P2) |
2149 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2150 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2151 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2152 PIPE_CONFIG(ADDR_SURF_P2) |
2153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2154 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2155 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2156 PIPE_CONFIG(ADDR_SURF_P2) |
2157 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2158 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2159 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2160 PIPE_CONFIG(ADDR_SURF_P2) |
2161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2162 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2163 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2164 PIPE_CONFIG(ADDR_SURF_P2) |
2165 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2166 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2167 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2168 PIPE_CONFIG(ADDR_SURF_P2) |
2169 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2170 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2171 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2172 PIPE_CONFIG(ADDR_SURF_P2) |
2173 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2174 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2175 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2176 PIPE_CONFIG(ADDR_SURF_P2));
2177 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2178 PIPE_CONFIG(ADDR_SURF_P2) |
2179 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2180 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2181 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2182 PIPE_CONFIG(ADDR_SURF_P2) |
2183 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2184 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2185 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2186 PIPE_CONFIG(ADDR_SURF_P2) |
2187 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2188 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2189 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2190 PIPE_CONFIG(ADDR_SURF_P2) |
2191 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2192 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2193 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2194 PIPE_CONFIG(ADDR_SURF_P2) |
2195 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2196 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2197 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2198 PIPE_CONFIG(ADDR_SURF_P2) |
2199 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2200 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2201 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2202 PIPE_CONFIG(ADDR_SURF_P2) |
2203 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2204 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2205 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2206 PIPE_CONFIG(ADDR_SURF_P2) |
2207 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2208 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2209 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2210 PIPE_CONFIG(ADDR_SURF_P2) |
2211 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2212 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2213 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2214 PIPE_CONFIG(ADDR_SURF_P2) |
2215 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2216 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2217 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2218 PIPE_CONFIG(ADDR_SURF_P2) |
2219 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2220 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2221 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2222 PIPE_CONFIG(ADDR_SURF_P2) |
2223 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2224 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2225 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2226 PIPE_CONFIG(ADDR_SURF_P2) |
2227 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2228 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2229 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2230 PIPE_CONFIG(ADDR_SURF_P2) |
2231 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2232 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2233 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2234 PIPE_CONFIG(ADDR_SURF_P2) |
2235 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2236 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2237 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2238 PIPE_CONFIG(ADDR_SURF_P2) |
2239 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2240 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2241 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2242 PIPE_CONFIG(ADDR_SURF_P2) |
2243 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2244 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2245 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2246 PIPE_CONFIG(ADDR_SURF_P2) |
2247 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2248 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2249
2250 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2253 NUM_BANKS(ADDR_SURF_8_BANK));
2254 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2255 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2256 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2257 NUM_BANKS(ADDR_SURF_8_BANK));
2258 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2259 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2260 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2261 NUM_BANKS(ADDR_SURF_8_BANK));
2262 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2265 NUM_BANKS(ADDR_SURF_8_BANK));
2266 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2268 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2269 NUM_BANKS(ADDR_SURF_8_BANK));
2270 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2273 NUM_BANKS(ADDR_SURF_8_BANK));
2274 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2275 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2276 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2277 NUM_BANKS(ADDR_SURF_8_BANK));
2278 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2281 NUM_BANKS(ADDR_SURF_16_BANK));
2282 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2283 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2284 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2285 NUM_BANKS(ADDR_SURF_16_BANK));
2286 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2289 NUM_BANKS(ADDR_SURF_16_BANK));
2290 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2291 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2292 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2293 NUM_BANKS(ADDR_SURF_16_BANK));
2294 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2295 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2296 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2297 NUM_BANKS(ADDR_SURF_16_BANK));
2298 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2299 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2300 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2301 NUM_BANKS(ADDR_SURF_16_BANK));
2302 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2303 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2304 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2305 NUM_BANKS(ADDR_SURF_8_BANK));
2306
2307 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2308 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2309 reg_offset != 23)
2310 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2311
2312 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2313 if (reg_offset != 7)
2314 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2315
8cdacf44 2316 break;
af15a2d5 2317 case CHIP_FIJI:
90bea0ab
TSD		 2318 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2320 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2321 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2322 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2324 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2325 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2326 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2328 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2329 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2330 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2332 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2333 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2334 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2335 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2336 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2337 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2338 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2339 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2340 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2341 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2342 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2343 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2344 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2345 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2346 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2347 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2348 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2349 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2350 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2351 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2352 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2353 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2354 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2355 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2356 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2357 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2358 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2359 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2360 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2361 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2362 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2363 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2364 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2365 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2366 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2367 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2368 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2369 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2370 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2371 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2372 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2373 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2374 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2375 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2376 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2377 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2378 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2379 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2380 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2381 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2382 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2383 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2384 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2385 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2386 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2387 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2388 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2389 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2390 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2391 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2392 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2393 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2394 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2395 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2396 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2397 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2398 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2399 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2400 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2401 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2402 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2404 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2405 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2406 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2407 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2408 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2409 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2410 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2411 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2412 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2413 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2414 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2416 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2417 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2418 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2420 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2421 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2422 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2423 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2424 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2425 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2426 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2428 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2429 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2430 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2431 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2432 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2433 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2434 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2435 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2436 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2437 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2438 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2439 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2440
2441 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2442 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2443 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2444 NUM_BANKS(ADDR_SURF_8_BANK));
2445 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2448 NUM_BANKS(ADDR_SURF_8_BANK));
2449 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2452 NUM_BANKS(ADDR_SURF_8_BANK));
2453 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2456 NUM_BANKS(ADDR_SURF_8_BANK));
2457 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2459 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2460 NUM_BANKS(ADDR_SURF_8_BANK));
2461 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2464 NUM_BANKS(ADDR_SURF_8_BANK));
2465 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2468 NUM_BANKS(ADDR_SURF_8_BANK));
2469 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2471 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2472 NUM_BANKS(ADDR_SURF_8_BANK));
2473 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2476 NUM_BANKS(ADDR_SURF_8_BANK));
2477 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2480 NUM_BANKS(ADDR_SURF_8_BANK));
2481 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2484 NUM_BANKS(ADDR_SURF_8_BANK));
2485 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2488 NUM_BANKS(ADDR_SURF_8_BANK));
2489 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2490 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2491 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2492 NUM_BANKS(ADDR_SURF_8_BANK));
2493 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2496 NUM_BANKS(ADDR_SURF_4_BANK));
2497
2498 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2499 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2500
2501 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2502 if (reg_offset != 7)
2503 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2504
5f2e816b 2505 break;
aaa36a97 2506 case CHIP_TONGA:
90bea0ab
TSD		 2507 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2508 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2510 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2511 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2512 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2514 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2515 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2516 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2518 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2519 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2520 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2523 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2524 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2526 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2527 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2528 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2529 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2530 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2531 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2532 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2533 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2534 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2535 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2536 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2537 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2538 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2539 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2540 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2541 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2542 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2543 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2544 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2545 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2546 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2547 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2548 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2549 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2550 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2551 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2552 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2553 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2554 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2555 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2556 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2557 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2558 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2559 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2560 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2561 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2562 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2563 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2564 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2565 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2566 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2567 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2568 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2569 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2570 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2571 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2572 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2573 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2574 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2575 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2576 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2577 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2578 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2579 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2580 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2581 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2582 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2583 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2584 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2585 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2586 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2587 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2588 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2589 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2590 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2591 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2593 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2594 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2595 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2596 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2597 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2598 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2599 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2600 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2601 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2602 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2603 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2604 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2605 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2606 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2607 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2608 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2609 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2610 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2611 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2612 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2613 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2614 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2615 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2616 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2617 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2618 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2619 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2620 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2621 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2622 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2623 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2624 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2625 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2626 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2627 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2628 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2629
2630 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2631 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2632 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2633 NUM_BANKS(ADDR_SURF_16_BANK));
2634 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2637 NUM_BANKS(ADDR_SURF_16_BANK));
2638 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2640 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2641 NUM_BANKS(ADDR_SURF_16_BANK));
2642 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2643 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2644 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2645 NUM_BANKS(ADDR_SURF_16_BANK));
2646 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2649 NUM_BANKS(ADDR_SURF_16_BANK));
2650 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2653 NUM_BANKS(ADDR_SURF_16_BANK));
2654 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2657 NUM_BANKS(ADDR_SURF_16_BANK));
2658 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2659 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2660 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2661 NUM_BANKS(ADDR_SURF_16_BANK));
2662 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2665 NUM_BANKS(ADDR_SURF_16_BANK));
2666 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2667 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2668 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2669 NUM_BANKS(ADDR_SURF_16_BANK));
2670 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2673 NUM_BANKS(ADDR_SURF_16_BANK));
2674 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2675 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2676 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2677 NUM_BANKS(ADDR_SURF_8_BANK));
2678 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2681 NUM_BANKS(ADDR_SURF_4_BANK));
2682 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2683 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2684 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2685 NUM_BANKS(ADDR_SURF_4_BANK));
2686
2687 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2688 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2689
2690 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2691 if (reg_offset != 7)
2692 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2693
68182d90 2694 break;
2cc0c0b5 2695 case CHIP_POLARIS11:
68182d90
FC		 2696 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2697 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2698 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2699 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2700 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2701 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2702 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2703 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2704 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2705 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2706 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2707 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2708 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2709 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2710 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2711 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2712 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2713 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2715 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2716 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2717 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2718 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2719 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2720 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2721 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2722 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2723 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2724 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2725 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2726 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2727 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2728 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2729 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2730 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2731 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2732 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2733 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2734 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2735 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2736 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2737 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2738 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2739 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2740 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2741 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2742 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2743 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2744 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2745 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2746 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2747 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2748 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2749 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2750 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2751 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2752 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2753 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2754 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2755 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2756 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2757 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2758 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2759 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2760 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2761 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2762 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2763 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2764 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2765 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2766 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2767 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2768 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2769 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2770 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2771 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2772 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2773 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2774 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2775 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2776 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2777 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2778 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2779 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2780 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2781 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2782 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2783 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2784 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2785 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2786 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2787 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2788 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2789 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2790 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2791 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2792 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2793 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2794 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2795 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2796 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2797 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2798 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2799 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2800 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2801 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2802 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2803 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2804 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2805 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2806 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2807 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2808 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2809 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2810 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2811 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2812 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2813 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2814 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2815 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2816 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2817 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2818
2819 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2820 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2821 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2822 NUM_BANKS(ADDR_SURF_16_BANK));
2823
2824 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2825 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2826 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2827 NUM_BANKS(ADDR_SURF_16_BANK));
2828
2829 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2830 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2831 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2832 NUM_BANKS(ADDR_SURF_16_BANK));
2833
2834 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2835 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2836 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2837 NUM_BANKS(ADDR_SURF_16_BANK));
2838
2839 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2840 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2841 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2842 NUM_BANKS(ADDR_SURF_16_BANK));
2843
2844 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2845 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2846 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2847 NUM_BANKS(ADDR_SURF_16_BANK));
2848
2849 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2850 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2851 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2852 NUM_BANKS(ADDR_SURF_16_BANK));
2853
2854 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2855 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2856 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2857 NUM_BANKS(ADDR_SURF_16_BANK));
2858
2859 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2860 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2861 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2862 NUM_BANKS(ADDR_SURF_16_BANK));
2863
2864 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2865 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2866 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2867 NUM_BANKS(ADDR_SURF_16_BANK));
2868
2869 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2870 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2871 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2872 NUM_BANKS(ADDR_SURF_16_BANK));
2873
2874 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2875 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2876 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2877 NUM_BANKS(ADDR_SURF_16_BANK));
2878
2879 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2880 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2881 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2882 NUM_BANKS(ADDR_SURF_8_BANK));
2883
2884 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2885 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2886 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2887 NUM_BANKS(ADDR_SURF_4_BANK));
2888
2889 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2890 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2891
2892 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2893 if (reg_offset != 7)
2894 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2895
2896 break;
2cc0c0b5 2897 case CHIP_POLARIS10:
68182d90
FC		 2898 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2899 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2900 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2901 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2902 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2903 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2904 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2905 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2906 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2907 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2908 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2909 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2910 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2911 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2912 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2913 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2914 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2915 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2916 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2917 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2918 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2919 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2920 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2921 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2922 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2923 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2924 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2925 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2926 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2927 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2928 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2929 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2930 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2931 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2932 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2933 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2934 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2935 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2936 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2937 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2938 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2939 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2940 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2941 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2942 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2943 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2944 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2945 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2946 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2947 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2948 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2949 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2950 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2951 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2952 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2953 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2954 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2955 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2956 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2957 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2958 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2959 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2960 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2961 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2962 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2963 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2964 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2965 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2966 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2967 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2968 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2969 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2970 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2971 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2972 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2973 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2974 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2975 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2976 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2977 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2978 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2979 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2980 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2981 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2982 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2983 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2984 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2985 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2986 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2987 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2988 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2989 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2990 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2991 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2992 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2993 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2994 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2995 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2996 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2997 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2998 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2999 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3000 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3001 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3002 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3003 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3004 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3005 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3006 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3007 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3008 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3009 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3010 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3011 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3012 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3013 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3014 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3015 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3016 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3017 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
3018 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3019 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3020
3021 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3022 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3023 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3024 NUM_BANKS(ADDR_SURF_16_BANK));
3025
3026 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3027 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3028 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3029 NUM_BANKS(ADDR_SURF_16_BANK));
3030
3031 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3032 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3033 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3034 NUM_BANKS(ADDR_SURF_16_BANK));
3035
3036 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3039 NUM_BANKS(ADDR_SURF_16_BANK));
3040
3041 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3042 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3043 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3044 NUM_BANKS(ADDR_SURF_16_BANK));
3045
3046 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3047 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3048 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3049 NUM_BANKS(ADDR_SURF_16_BANK));
3050
3051 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3052 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3053 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3054 NUM_BANKS(ADDR_SURF_16_BANK));
3055
3056 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3059 NUM_BANKS(ADDR_SURF_16_BANK));
3060
3061 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3062 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3063 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3064 NUM_BANKS(ADDR_SURF_16_BANK));
3065
3066 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3067 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3068 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3069 NUM_BANKS(ADDR_SURF_16_BANK));
3070
3071 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3072 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3073 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3074 NUM_BANKS(ADDR_SURF_16_BANK));
3075
3076 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3077 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3078 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3079 NUM_BANKS(ADDR_SURF_8_BANK));
3080
3081 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3082 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3083 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3084 NUM_BANKS(ADDR_SURF_4_BANK));
3085
3086 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3087 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3088 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3089 NUM_BANKS(ADDR_SURF_4_BANK));
3090
3091 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3092 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3093
3094 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3095 if (reg_offset != 7)
3096 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3097
aaa36a97 3098 break;
e3c7656c 3099 case CHIP_STONEY:
90bea0ab
TSD		 3100 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3101 PIPE_CONFIG(ADDR_SURF_P2) |
3102 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3103 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3104 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3105 PIPE_CONFIG(ADDR_SURF_P2) |
3106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3107 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3108 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3109 PIPE_CONFIG(ADDR_SURF_P2) |
3110 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3111 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3112 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3113 PIPE_CONFIG(ADDR_SURF_P2) |
3114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3115 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3116 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3117 PIPE_CONFIG(ADDR_SURF_P2) |
3118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3119 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3120 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3121 PIPE_CONFIG(ADDR_SURF_P2) |
3122 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3123 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3124 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3125 PIPE_CONFIG(ADDR_SURF_P2) |
3126 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3127 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3128 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3129 PIPE_CONFIG(ADDR_SURF_P2));
3130 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3131 PIPE_CONFIG(ADDR_SURF_P2) |
3132 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3134 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3135 PIPE_CONFIG(ADDR_SURF_P2) |
3136 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3138 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3139 PIPE_CONFIG(ADDR_SURF_P2) |
3140 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3141 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3142 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3143 PIPE_CONFIG(ADDR_SURF_P2) |
3144 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3145 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3146 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3147 PIPE_CONFIG(ADDR_SURF_P2) |
3148 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3150 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3151 PIPE_CONFIG(ADDR_SURF_P2) |
3152 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3154 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3155 PIPE_CONFIG(ADDR_SURF_P2) |
3156 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3157 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3158 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3159 PIPE_CONFIG(ADDR_SURF_P2) |
3160 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3161 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3162 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3163 PIPE_CONFIG(ADDR_SURF_P2) |
3164 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3165 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3166 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3167 PIPE_CONFIG(ADDR_SURF_P2) |
3168 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3169 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3170 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3171 PIPE_CONFIG(ADDR_SURF_P2) |
3172 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3173 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3174 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3175 PIPE_CONFIG(ADDR_SURF_P2) |
3176 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3177 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3178 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3179 PIPE_CONFIG(ADDR_SURF_P2) |
3180 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3181 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3182 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3183 PIPE_CONFIG(ADDR_SURF_P2) |
3184 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3185 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3186 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3187 PIPE_CONFIG(ADDR_SURF_P2) |
3188 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3189 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3190 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3191 PIPE_CONFIG(ADDR_SURF_P2) |
3192 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3193 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3194 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3195 PIPE_CONFIG(ADDR_SURF_P2) |
3196 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3197 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3198 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3199 PIPE_CONFIG(ADDR_SURF_P2) |
3200 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3201 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3202
3203 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3206 NUM_BANKS(ADDR_SURF_8_BANK));
3207 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3210 NUM_BANKS(ADDR_SURF_8_BANK));
3211 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3214 NUM_BANKS(ADDR_SURF_8_BANK));
3215 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3216 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3217 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3218 NUM_BANKS(ADDR_SURF_8_BANK));
3219 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3222 NUM_BANKS(ADDR_SURF_8_BANK));
3223 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3224 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3225 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3226 NUM_BANKS(ADDR_SURF_8_BANK));
3227 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3230 NUM_BANKS(ADDR_SURF_8_BANK));
3231 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3232 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3233 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3234 NUM_BANKS(ADDR_SURF_16_BANK));
3235 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3236 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3237 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3238 NUM_BANKS(ADDR_SURF_16_BANK));
3239 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3242 NUM_BANKS(ADDR_SURF_16_BANK));
3243 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3244 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3245 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3246 NUM_BANKS(ADDR_SURF_16_BANK));
3247 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3250 NUM_BANKS(ADDR_SURF_16_BANK));
3251 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3252 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3253 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3254 NUM_BANKS(ADDR_SURF_16_BANK));
3255 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3256 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3257 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3258 NUM_BANKS(ADDR_SURF_8_BANK));
3259
3260 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3261 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3262 reg_offset != 23)
3263 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3264
3265 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3266 if (reg_offset != 7)
3267 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3268
e3c7656c 3269 break;
aaa36a97 3270 default:
90bea0ab
TSD		 3271 dev_warn(adev->dev,
3272 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3273 adev->asic_type);
3274
3275 case CHIP_CARRIZO:
3276 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3277 PIPE_CONFIG(ADDR_SURF_P2) |
3278 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3279 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3280 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3281 PIPE_CONFIG(ADDR_SURF_P2) |
3282 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3283 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3284 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3285 PIPE_CONFIG(ADDR_SURF_P2) |
3286 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3287 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3288 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3289 PIPE_CONFIG(ADDR_SURF_P2) |
3290 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3291 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3292 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3293 PIPE_CONFIG(ADDR_SURF_P2) |
3294 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3295 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3296 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3297 PIPE_CONFIG(ADDR_SURF_P2) |
3298 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3299 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3300 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3301 PIPE_CONFIG(ADDR_SURF_P2) |
3302 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3303 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3304 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3305 PIPE_CONFIG(ADDR_SURF_P2));
3306 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3307 PIPE_CONFIG(ADDR_SURF_P2) |
3308 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3310 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3311 PIPE_CONFIG(ADDR_SURF_P2) |
3312 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3314 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3315 PIPE_CONFIG(ADDR_SURF_P2) |
3316 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3318 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3319 PIPE_CONFIG(ADDR_SURF_P2) |
3320 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3322 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3323 PIPE_CONFIG(ADDR_SURF_P2) |
3324 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3325 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3326 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3327 PIPE_CONFIG(ADDR_SURF_P2) |
3328 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3330 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3331 PIPE_CONFIG(ADDR_SURF_P2) |
3332 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3334 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3335 PIPE_CONFIG(ADDR_SURF_P2) |
3336 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3338 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3339 PIPE_CONFIG(ADDR_SURF_P2) |
3340 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3341 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3342 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3343 PIPE_CONFIG(ADDR_SURF_P2) |
3344 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3345 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3346 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3347 PIPE_CONFIG(ADDR_SURF_P2) |
3348 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3349 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3350 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3351 PIPE_CONFIG(ADDR_SURF_P2) |
3352 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3353 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3354 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3355 PIPE_CONFIG(ADDR_SURF_P2) |
3356 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3357 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3358 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3359 PIPE_CONFIG(ADDR_SURF_P2) |
3360 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3361 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3362 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3363 PIPE_CONFIG(ADDR_SURF_P2) |
3364 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3365 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3366 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3367 PIPE_CONFIG(ADDR_SURF_P2) |
3368 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3369 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3370 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3371 PIPE_CONFIG(ADDR_SURF_P2) |
3372 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3373 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3374 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3375 PIPE_CONFIG(ADDR_SURF_P2) |
3376 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3377 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3378
3379 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3382 NUM_BANKS(ADDR_SURF_8_BANK));
3383 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3386 NUM_BANKS(ADDR_SURF_8_BANK));
3387 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3390 NUM_BANKS(ADDR_SURF_8_BANK));
3391 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3394 NUM_BANKS(ADDR_SURF_8_BANK));
3395 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3396 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3397 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3398 NUM_BANKS(ADDR_SURF_8_BANK));
3399 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3400 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3401 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3402 NUM_BANKS(ADDR_SURF_8_BANK));
3403 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3404 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3405 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3406 NUM_BANKS(ADDR_SURF_8_BANK));
3407 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3408 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3409 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3410 NUM_BANKS(ADDR_SURF_16_BANK));
3411 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3412 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3413 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3414 NUM_BANKS(ADDR_SURF_16_BANK));
3415 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3416 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3417 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3418 NUM_BANKS(ADDR_SURF_16_BANK));
3419 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3420 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3421 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3422 NUM_BANKS(ADDR_SURF_16_BANK));
3423 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3424 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3425 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3426 NUM_BANKS(ADDR_SURF_16_BANK));
3427 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3428 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3429 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3430 NUM_BANKS(ADDR_SURF_16_BANK));
3431 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3432 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3433 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3434 NUM_BANKS(ADDR_SURF_8_BANK));
3435
3436 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3437 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3438 reg_offset != 23)
3439 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3440
3441 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3442 if (reg_offset != 7)
3443 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3444
3445 break;
aaa36a97
AD		 3446 }
3447}
3448
05fb7291
AD		 3449static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
3450 u32 se_num, u32 sh_num)
aaa36a97
AD		 3451{
3452 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3453
3454 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
3455 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3456 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3457 } else if (se_num == 0xffffffff) {
3458 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3459 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3460 } else if (sh_num == 0xffffffff) {
3461 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3462 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3463 } else {
3464 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3465 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3466 }
3467 WREG32(mmGRBM_GFX_INDEX, data);
3468}
3469
8f8e00c1
AD		 3470static u32 gfx_v8_0_create_bitmask(u32 bit_width)
3471{
3472 return (u32)((1ULL << bit_width) - 1);
3473}
3474
3475static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
aaa36a97
AD		 3476{
3477 u32 data, mask;
3478
3479 data = RREG32(mmCC_RB_BACKEND_DISABLE);
aaa36a97
AD		 3480 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3481
8f8e00c1 3482 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
aaa36a97
AD		 3483 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
3484
8f8e00c1
AD		 3485 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
3486 adev->gfx.config.max_sh_per_se);
aaa36a97 3487
8f8e00c1 3488 return (~data) & mask;
aaa36a97
AD		 3489}
3490
8f8e00c1 3491static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
aaa36a97
AD		 3492{
3493 int i, j;
aac1e3ca 3494 u32 data;
8f8e00c1 3495 u32 active_rbs = 0;
6157bd7a
FC		 3496 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3497 adev->gfx.config.max_sh_per_se;
aaa36a97
AD		 3498
3499 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 3500 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3501 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
aaa36a97 3502 gfx_v8_0_select_se_sh(adev, i, j);
8f8e00c1
AD		 3503 data = gfx_v8_0_get_rb_active_bitmap(adev);
3504 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
6157bd7a 3505 rb_bitmap_width_per_sh);
aaa36a97
AD		 3506 }
3507 }
3508 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3509 mutex_unlock(&adev->grbm_idx_mutex);
3510
8f8e00c1 3511 adev->gfx.config.backend_enable_mask = active_rbs;
aac1e3ca 3512 adev->gfx.config.num_rbs = hweight32(active_rbs);
aaa36a97
AD		 3513}
3514
cd06bf68 3515/**
35c7a952 3516 * gfx_v8_0_init_compute_vmid - gart enable
cd06bf68
BG		 3517 *
3518 * @rdev: amdgpu_device pointer
3519 *
3520 * Initialize compute vmid sh_mem registers
3521 *
3522 */
3523#define DEFAULT_SH_MEM_BASES (0x6000)
3524#define FIRST_COMPUTE_VMID (8)
3525#define LAST_COMPUTE_VMID (16)
35c7a952 3526static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
cd06bf68
BG		 3527{
3528 int i;
3529 uint32_t sh_mem_config;
3530 uint32_t sh_mem_bases;
3531
3532 /*
3533 * Configure apertures:
3534 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3535 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3536 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3537 */
3538 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3539
3540 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3541 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3542 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3543 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3544 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3545 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3546
3547 mutex_lock(&adev->srbm_mutex);
3548 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
3549 vi_srbm_select(adev, 0, 0, 0, i);
3550 /* CP and shaders */
3551 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3552 WREG32(mmSH_MEM_APE1_BASE, 1);
3553 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3554 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3555 }
3556 vi_srbm_select(adev, 0, 0, 0, 0);
3557 mutex_unlock(&adev->srbm_mutex);
3558}
3559
aaa36a97
AD		 3560static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
3561{
aaa36a97
AD		 3562 u32 tmp;
3563 int i;
3564
aaa36a97
AD		 3565 tmp = RREG32(mmGRBM_CNTL);
3566 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
3567 WREG32(mmGRBM_CNTL, tmp);
3568
0bde3a95
AD		 3569 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3570 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3571 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
aaa36a97
AD		 3572
3573 gfx_v8_0_tiling_mode_table_init(adev);
3574
8f8e00c1 3575 gfx_v8_0_setup_rb(adev);
7dae69a2 3576 gfx_v8_0_get_cu_info(adev);
aaa36a97
AD		 3577
3578 /* XXX SH_MEM regs */
3579 /* where to put LDS, scratch, GPUVM in FSA64 space */
3580 mutex_lock(&adev->srbm_mutex);
3581 for (i = 0; i < 16; i++) {
3582 vi_srbm_select(adev, 0, 0, 0, i);
3583 /* CP and shaders */
3584 if (i == 0) {
3585 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3586 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
0bde3a95 3587 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165 3588 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 3589 WREG32(mmSH_MEM_CONFIG, tmp);
3590 } else {
3591 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3592 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
0bde3a95 3593 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165 3594 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 3595 WREG32(mmSH_MEM_CONFIG, tmp);
3596 }
3597
3598 WREG32(mmSH_MEM_APE1_BASE, 1);
3599 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3600 WREG32(mmSH_MEM_BASES, 0);
3601 }
3602 vi_srbm_select(adev, 0, 0, 0, 0);
3603 mutex_unlock(&adev->srbm_mutex);
3604
35c7a952 3605 gfx_v8_0_init_compute_vmid(adev);
cd06bf68 3606
aaa36a97
AD		 3607 mutex_lock(&adev->grbm_idx_mutex);
3608 /*
3609 * making sure that the following register writes will be broadcasted
3610 * to all the shaders
3611 */
3612 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3613
3614 WREG32(mmPA_SC_FIFO_SIZE,
3615 (adev->gfx.config.sc_prim_fifo_size_frontend <<
3616 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3617 (adev->gfx.config.sc_prim_fifo_size_backend <<
3618 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3619 (adev->gfx.config.sc_hiz_tile_fifo_size <<
3620 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3621 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3622 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3623 mutex_unlock(&adev->grbm_idx_mutex);
3624
3625}
3626
3627static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3628{
3629 u32 i, j, k;
3630 u32 mask;
3631
3632 mutex_lock(&adev->grbm_idx_mutex);
3633 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3634 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3635 gfx_v8_0_select_se_sh(adev, i, j);
3636 for (k = 0; k < adev->usec_timeout; k++) {
3637 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3638 break;
3639 udelay(1);
3640 }
3641 }
3642 }
3643 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3644 mutex_unlock(&adev->grbm_idx_mutex);
3645
3646 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3647 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3648 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3649 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3650 for (k = 0; k < adev->usec_timeout; k++) {
3651 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3652 break;
3653 udelay(1);
3654 }
3655}
3656
3657static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3658 bool enable)
3659{
3660 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3661
0d07db7e
TSD		 3662 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3663 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3664 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3665 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3666
aaa36a97
AD		 3667 WREG32(mmCP_INT_CNTL_RING0, tmp);
3668}
3669
2b6cd977
EH		 3670static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3671{
3672 /* csib */
3673 WREG32(mmRLC_CSIB_ADDR_HI,
3674 adev->gfx.rlc.clear_state_gpu_addr >> 32);
3675 WREG32(mmRLC_CSIB_ADDR_LO,
3676 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3677 WREG32(mmRLC_CSIB_LENGTH,
3678 adev->gfx.rlc.clear_state_size);
3679}
3680
3681static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3682 int ind_offset,
3683 int list_size,
3684 int *unique_indices,
3685 int *indices_count,
3686 int max_indices,
3687 int *ind_start_offsets,
3688 int *offset_count,
3689 int max_offset)
3690{
3691 int indices;
3692 bool new_entry = true;
3693
3694 for (; ind_offset < list_size; ind_offset++) {
3695
3696 if (new_entry) {
3697 new_entry = false;
3698 ind_start_offsets[*offset_count] = ind_offset;
3699 *offset_count = *offset_count + 1;
3700 BUG_ON(*offset_count >= max_offset);
3701 }
3702
3703 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3704 new_entry = true;
3705 continue;
3706 }
3707
3708 ind_offset += 2;
3709
3710 /* look for the matching indice */
3711 for (indices = 0;
3712 indices < *indices_count;
3713 indices++) {
3714 if (unique_indices[indices] ==
3715 register_list_format[ind_offset])
3716 break;
3717 }
3718
3719 if (indices >= *indices_count) {
3720 unique_indices[*indices_count] =
3721 register_list_format[ind_offset];
3722 indices = *indices_count;
3723 *indices_count = *indices_count + 1;
3724 BUG_ON(*indices_count >= max_indices);
3725 }
3726
3727 register_list_format[ind_offset] = indices;
3728 }
3729}
3730
3731static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3732{
3733 int i, temp, data;
3734 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3735 int indices_count = 0;
3736 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3737 int offset_count = 0;
3738
3739 int list_size;
3740 unsigned int *register_list_format =
3741 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3742 if (register_list_format == NULL)
3743 return -ENOMEM;
3744 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
3745 adev->gfx.rlc.reg_list_format_size_bytes);
3746
3747 gfx_v8_0_parse_ind_reg_list(register_list_format,
3748 RLC_FormatDirectRegListLength,
3749 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3750 unique_indices,
3751 &indices_count,
3752 sizeof(unique_indices) / sizeof(int),
3753 indirect_start_offsets,
3754 &offset_count,
3755 sizeof(indirect_start_offsets)/sizeof(int));
3756
3757 /* save and restore list */
3758 temp = RREG32(mmRLC_SRM_CNTL);
3759 temp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
3760 WREG32(mmRLC_SRM_CNTL, temp);
3761
3762 WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3763 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3764 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
3765
3766 /* indirect list */
3767 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
3768 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
3769 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3770
3771 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
3772 list_size = list_size >> 1;
3773 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
3774 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
3775
3776 /* starting offsets starts */
3777 WREG32(mmRLC_GPM_SCRATCH_ADDR,
3778 adev->gfx.rlc.starting_offsets_start);
3779 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
3780 WREG32(mmRLC_GPM_SCRATCH_DATA,
3781 indirect_start_offsets[i]);
3782
3783 /* unique indices */
3784 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
3785 data = mmRLC_SRM_INDEX_CNTL_DATA_0;
3786 for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
3787 amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
3788 amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
3789 }
3790 kfree(register_list_format);
3791
3792 return 0;
3793}
3794
3795static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
3796{
3797 uint32_t data;
3798
3799 data = RREG32(mmRLC_SRM_CNTL);
3800 data |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
3801 WREG32(mmRLC_SRM_CNTL, data);
3802}
3803
fb16007b 3804static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
f4bfffdd
EH		 3805{
3806 uint32_t data;
3807
3808 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
fb16007b
AD		 3809 AMD_PG_SUPPORT_GFX_SMG |
3810 AMD_PG_SUPPORT_GFX_DMG)) {
f4bfffdd
EH		 3811 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3812 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3813 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3814 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3815
3816 data = 0;
3817 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
3818 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
3819 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
3820 data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
3821 WREG32(mmRLC_PG_DELAY, data);
3822
3823 data = RREG32(mmRLC_PG_DELAY_2);
3824 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
3825 data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
3826 WREG32(mmRLC_PG_DELAY_2, data);
3827
3828 data = RREG32(mmRLC_AUTO_PG_CTRL);
3829 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3830 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3831 WREG32(mmRLC_AUTO_PG_CTRL, data);
3832 }
3833}
3834
2c547165
AD		 3835static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
3836 bool enable)
3837{
3838 u32 data, orig;
3839
3840 orig = data = RREG32(mmRLC_PG_CNTL);
3841
3842 if (enable)
3843 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3844 else
3845 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3846
3847 if (orig != data)
3848 WREG32(mmRLC_PG_CNTL, data);
3849}
3850
3851static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
3852 bool enable)
3853{
3854 u32 data, orig;
3855
3856 orig = data = RREG32(mmRLC_PG_CNTL);
3857
3858 if (enable)
3859 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3860 else
3861 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3862
3863 if (orig != data)
3864 WREG32(mmRLC_PG_CNTL, data);
3865}
3866
3867static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
3868{
3869 u32 data, orig;
3870
3871 orig = data = RREG32(mmRLC_PG_CNTL);
3872
3873 if (enable)
3874 data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
3875 else
3876 data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
3877
3878 if (orig != data)
3879 WREG32(mmRLC_PG_CNTL, data);
3880}
3881
2b6cd977
EH		 3882static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
3883{
3884 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3885 AMD_PG_SUPPORT_GFX_SMG |
3886 AMD_PG_SUPPORT_GFX_DMG |
3887 AMD_PG_SUPPORT_CP |
3888 AMD_PG_SUPPORT_GDS |
3889 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3890 gfx_v8_0_init_csb(adev);
3891 gfx_v8_0_init_save_restore_list(adev);
3892 gfx_v8_0_enable_save_restore_machine(adev);
f4bfffdd 3893
fb16007b
AD		 3894 if ((adev->asic_type == CHIP_CARRIZO) ||
3895 (adev->asic_type == CHIP_STONEY)) {
3896 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3897 gfx_v8_0_init_power_gating(adev);
3898 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2c547165
AD		 3899 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3900 cz_enable_sck_slow_down_on_power_up(adev, true);
3901 cz_enable_sck_slow_down_on_power_down(adev, true);
3902 } else {
3903 cz_enable_sck_slow_down_on_power_up(adev, false);
3904 cz_enable_sck_slow_down_on_power_down(adev, false);
3905 }
3906 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3907 cz_enable_cp_power_gating(adev, true);
3908 else
3909 cz_enable_cp_power_gating(adev, false);
fb16007b
AD		 3910 } else if (adev->asic_type == CHIP_POLARIS11) {
3911 gfx_v8_0_init_power_gating(adev);
3912 }
2b6cd977
EH		 3913 }
3914}
3915
aaa36a97
AD		 3916void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
3917{
3918 u32 tmp = RREG32(mmRLC_CNTL);
3919
3920 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
3921 WREG32(mmRLC_CNTL, tmp);
3922
3923 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3924
3925 gfx_v8_0_wait_for_rlc_serdes(adev);
3926}
3927
3928static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
3929{
3930 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3931
3932 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3933 WREG32(mmGRBM_SOFT_RESET, tmp);
3934 udelay(50);
3935 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
3936 WREG32(mmGRBM_SOFT_RESET, tmp);
3937 udelay(50);
3938}
3939
3940static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
3941{
3942 u32 tmp = RREG32(mmRLC_CNTL);
3943
3944 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
3945 WREG32(mmRLC_CNTL, tmp);
3946
3947 /* carrizo do enable cp interrupt after cp inited */
e3c7656c 3948 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 3949 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3950
3951 udelay(50);
3952}
3953
3954static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
3955{
3956 const struct rlc_firmware_header_v2_0 *hdr;
3957 const __le32 *fw_data;
3958 unsigned i, fw_size;
3959
3960 if (!adev->gfx.rlc_fw)
3961 return -EINVAL;
3962
3963 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3964 amdgpu_ucode_print_rlc_hdr(&hdr->header);
aaa36a97
AD		 3965
3966 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
3967 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3968 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3969
3970 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3971 for (i = 0; i < fw_size; i++)
3972 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3973 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3974
3975 return 0;
3976}
3977
3978static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
3979{
3980 int r;
3981
3982 gfx_v8_0_rlc_stop(adev);
3983
3984 /* disable CG */
3985 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2cc0c0b5
FC		 3986 if (adev->asic_type == CHIP_POLARIS11 ||
3987 adev->asic_type == CHIP_POLARIS10)
68182d90 3988 WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0);
aaa36a97
AD		 3989
3990 /* disable PG */
3991 WREG32(mmRLC_PG_CNTL, 0);
3992
3993 gfx_v8_0_rlc_reset(adev);
3994
2b6cd977
EH		 3995 gfx_v8_0_init_pg(adev);
3996
e61710c5 3997 if (!adev->pp_enabled) {
ba5c2a87
RZ		 3998 if (!adev->firmware.smu_load) {
3999 /* legacy rlc firmware loading */
4000 r = gfx_v8_0_rlc_load_microcode(adev);
4001 if (r)
4002 return r;
4003 } else {
4004 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4005 AMDGPU_UCODE_ID_RLC_G);
4006 if (r)
4007 return -EINVAL;
4008 }
aaa36a97
AD		 4009 }
4010
4011 gfx_v8_0_rlc_start(adev);
4012
4013 return 0;
4014}
4015
4016static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
4017{
4018 int i;
4019 u32 tmp = RREG32(mmCP_ME_CNTL);
4020
4021 if (enable) {
4022 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4023 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4024 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4025 } else {
4026 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4027 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4028 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
4029 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4030 adev->gfx.gfx_ring[i].ready = false;
4031 }
4032 WREG32(mmCP_ME_CNTL, tmp);
4033 udelay(50);
4034}
4035
4036static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
4037{
4038 const struct gfx_firmware_header_v1_0 *pfp_hdr;
4039 const struct gfx_firmware_header_v1_0 *ce_hdr;
4040 const struct gfx_firmware_header_v1_0 *me_hdr;
4041 const __le32 *fw_data;
4042 unsigned i, fw_size;
4043
4044 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
4045 return -EINVAL;
4046
4047 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
4048 adev->gfx.pfp_fw->data;
4049 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
4050 adev->gfx.ce_fw->data;
4051 me_hdr = (const struct gfx_firmware_header_v1_0 *)
4052 adev->gfx.me_fw->data;
4053
4054 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
4055 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
4056 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
aaa36a97
AD		 4057
4058 gfx_v8_0_cp_gfx_enable(adev, false);
4059
4060 /* PFP */
4061 fw_data = (const __le32 *)
4062 (adev->gfx.pfp_fw->data +
4063 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
4064 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
4065 WREG32(mmCP_PFP_UCODE_ADDR, 0);
4066 for (i = 0; i < fw_size; i++)
4067 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
4068 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
4069
4070 /* CE */
4071 fw_data = (const __le32 *)
4072 (adev->gfx.ce_fw->data +
4073 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
4074 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
4075 WREG32(mmCP_CE_UCODE_ADDR, 0);
4076 for (i = 0; i < fw_size; i++)
4077 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
4078 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
4079
4080 /* ME */
4081 fw_data = (const __le32 *)
4082 (adev->gfx.me_fw->data +
4083 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
4084 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
4085 WREG32(mmCP_ME_RAM_WADDR, 0);
4086 for (i = 0; i < fw_size; i++)
4087 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
4088 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
4089
4090 return 0;
4091}
4092
4093static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
4094{
4095 u32 count = 0;
4096 const struct cs_section_def *sect = NULL;
4097 const struct cs_extent_def *ext = NULL;
4098
4099 /* begin clear state */
4100 count += 2;
4101 /* context control state */
4102 count += 3;
4103
4104 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4105 for (ext = sect->section; ext->extent != NULL; ++ext) {
4106 if (sect->id == SECT_CONTEXT)
4107 count += 2 + ext->reg_count;
4108 else
4109 return 0;
4110 }
4111 }
4112 /* pa_sc_raster_config/pa_sc_raster_config1 */
4113 count += 4;
4114 /* end clear state */
4115 count += 2;
4116 /* clear state */
4117 count += 2;
4118
4119 return count;
4120}
4121
4122static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
4123{
4124 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
4125 const struct cs_section_def *sect = NULL;
4126 const struct cs_extent_def *ext = NULL;
4127 int r, i;
4128
4129 /* init the CP */
4130 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
4131 WREG32(mmCP_ENDIAN_SWAP, 0);
4132 WREG32(mmCP_DEVICE_ID, 1);
4133
4134 gfx_v8_0_cp_gfx_enable(adev, true);
4135
a27de35c 4136 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
aaa36a97
AD		 4137 if (r) {
4138 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
4139 return r;
4140 }
4141
4142 /* clear state buffer */
4143 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4144 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4145
4146 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4147 amdgpu_ring_write(ring, 0x80000000);
4148 amdgpu_ring_write(ring, 0x80000000);
4149
4150 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4151 for (ext = sect->section; ext->extent != NULL; ++ext) {
4152 if (sect->id == SECT_CONTEXT) {
4153 amdgpu_ring_write(ring,
4154 PACKET3(PACKET3_SET_CONTEXT_REG,
4155 ext->reg_count));
4156 amdgpu_ring_write(ring,
4157 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4158 for (i = 0; i < ext->reg_count; i++)
4159 amdgpu_ring_write(ring, ext->extent[i]);
4160 }
4161 }
4162 }
4163
4164 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4165 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4166 switch (adev->asic_type) {
4167 case CHIP_TONGA:
2cc0c0b5 4168 case CHIP_POLARIS10:
aaa36a97
AD		 4169 amdgpu_ring_write(ring, 0x16000012);
4170 amdgpu_ring_write(ring, 0x0000002A);
4171 break;
2cc0c0b5 4172 case CHIP_POLARIS11:
68182d90
FC		 4173 amdgpu_ring_write(ring, 0x16000012);
4174 amdgpu_ring_write(ring, 0x00000000);
4175 break;
fa676048
FC		 4176 case CHIP_FIJI:
4177 amdgpu_ring_write(ring, 0x3a00161a);
4178 amdgpu_ring_write(ring, 0x0000002e);
4179 break;
aaa36a97
AD		 4180 case CHIP_CARRIZO:
4181 amdgpu_ring_write(ring, 0x00000002);
4182 amdgpu_ring_write(ring, 0x00000000);
4183 break;
d1a7f7aa
KW		 4184 case CHIP_TOPAZ:
4185 amdgpu_ring_write(ring, adev->gfx.config.num_rbs == 1 ?
4186 0x00000000 : 0x00000002);
4187 amdgpu_ring_write(ring, 0x00000000);
4188 break;
e3c7656c
SL		 4189 case CHIP_STONEY:
4190 amdgpu_ring_write(ring, 0x00000000);
4191 amdgpu_ring_write(ring, 0x00000000);
4192 break;
aaa36a97
AD		 4193 default:
4194 BUG();
4195 }
4196
4197 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4198 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4199
4200 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4201 amdgpu_ring_write(ring, 0);
4202
4203 /* init the CE partitions */
4204 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4205 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4206 amdgpu_ring_write(ring, 0x8000);
4207 amdgpu_ring_write(ring, 0x8000);
4208
a27de35c 4209 amdgpu_ring_commit(ring);
aaa36a97
AD		 4210
4211 return 0;
4212}
4213
4214static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4215{
4216 struct amdgpu_ring *ring;
4217 u32 tmp;
4218 u32 rb_bufsz;
4219 u64 rb_addr, rptr_addr;
4220 int r;
4221
4222 /* Set the write pointer delay */
4223 WREG32(mmCP_RB_WPTR_DELAY, 0);
4224
4225 /* set the RB to use vmid 0 */
4226 WREG32(mmCP_RB_VMID, 0);
4227
4228 /* Set ring buffer size */
4229 ring = &adev->gfx.gfx_ring[0];
4230 rb_bufsz = order_base_2(ring->ring_size / 8);
4231 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4232 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4233 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4234 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4235#ifdef __BIG_ENDIAN
4236 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4237#endif
4238 WREG32(mmCP_RB0_CNTL, tmp);
4239
4240 /* Initialize the ring buffer's read and write pointers */
4241 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4242 ring->wptr = 0;
4243 WREG32(mmCP_RB0_WPTR, ring->wptr);
4244
4245 /* set the wb address wether it's enabled or not */
4246 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4247 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4248 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4249
4250 mdelay(1);
4251 WREG32(mmCP_RB0_CNTL, tmp);
4252
4253 rb_addr = ring->gpu_addr >> 8;
4254 WREG32(mmCP_RB0_BASE, rb_addr);
4255 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4256
4257 /* no gfx doorbells on iceland */
4258 if (adev->asic_type != CHIP_TOPAZ) {
4259 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4260 if (ring->use_doorbell) {
4261 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4262 DOORBELL_OFFSET, ring->doorbell_index);
68182d90
FC		 4263 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4264 DOORBELL_HIT, 0);
aaa36a97
AD		 4265 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4266 DOORBELL_EN, 1);
4267 } else {
4268 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4269 DOORBELL_EN, 0);
4270 }
4271 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4272
4273 if (adev->asic_type == CHIP_TONGA) {
4274 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4275 DOORBELL_RANGE_LOWER,
4276 AMDGPU_DOORBELL_GFX_RING0);
4277 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4278
4279 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4280 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4281 }
4282
4283 }
4284
4285 /* start the ring */
4286 gfx_v8_0_cp_gfx_start(adev);
4287 ring->ready = true;
4288 r = amdgpu_ring_test_ring(ring);
4289 if (r) {
4290 ring->ready = false;
4291 return r;
4292 }
4293
4294 return 0;
4295}
4296
4297static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4298{
4299 int i;
4300
4301 if (enable) {
4302 WREG32(mmCP_MEC_CNTL, 0);
4303 } else {
4304 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4305 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4306 adev->gfx.compute_ring[i].ready = false;
4307 }
4308 udelay(50);
4309}
4310
aaa36a97
AD		 4311static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
4312{
4313 const struct gfx_firmware_header_v1_0 *mec_hdr;
4314 const __le32 *fw_data;
4315 unsigned i, fw_size;
4316
4317 if (!adev->gfx.mec_fw)
4318 return -EINVAL;
4319
4320 gfx_v8_0_cp_compute_enable(adev, false);
4321
4322 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4323 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
aaa36a97
AD		 4324
4325 fw_data = (const __le32 *)
4326 (adev->gfx.mec_fw->data +
4327 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4328 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
4329
4330 /* MEC1 */
4331 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
4332 for (i = 0; i < fw_size; i++)
4333 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
4334 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
4335
4336 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
4337 if (adev->gfx.mec2_fw) {
4338 const struct gfx_firmware_header_v1_0 *mec2_hdr;
4339
4340 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4341 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
aaa36a97
AD		 4342
4343 fw_data = (const __le32 *)
4344 (adev->gfx.mec2_fw->data +
4345 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
4346 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
4347
4348 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
4349 for (i = 0; i < fw_size; i++)
4350 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
4351 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
4352 }
4353
4354 return 0;
4355}
4356
4357struct vi_mqd {
4358 uint32_t header; /* ordinal0 */
4359 uint32_t compute_dispatch_initiator; /* ordinal1 */
4360 uint32_t compute_dim_x; /* ordinal2 */
4361 uint32_t compute_dim_y; /* ordinal3 */
4362 uint32_t compute_dim_z; /* ordinal4 */
4363 uint32_t compute_start_x; /* ordinal5 */
4364 uint32_t compute_start_y; /* ordinal6 */
4365 uint32_t compute_start_z; /* ordinal7 */
4366 uint32_t compute_num_thread_x; /* ordinal8 */
4367 uint32_t compute_num_thread_y; /* ordinal9 */
4368 uint32_t compute_num_thread_z; /* ordinal10 */
4369 uint32_t compute_pipelinestat_enable; /* ordinal11 */
4370 uint32_t compute_perfcount_enable; /* ordinal12 */
4371 uint32_t compute_pgm_lo; /* ordinal13 */
4372 uint32_t compute_pgm_hi; /* ordinal14 */
4373 uint32_t compute_tba_lo; /* ordinal15 */
4374 uint32_t compute_tba_hi; /* ordinal16 */
4375 uint32_t compute_tma_lo; /* ordinal17 */
4376 uint32_t compute_tma_hi; /* ordinal18 */
4377 uint32_t compute_pgm_rsrc1; /* ordinal19 */
4378 uint32_t compute_pgm_rsrc2; /* ordinal20 */
4379 uint32_t compute_vmid; /* ordinal21 */
4380 uint32_t compute_resource_limits; /* ordinal22 */
4381 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
4382 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
4383 uint32_t compute_tmpring_size; /* ordinal25 */
4384 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
4385 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
4386 uint32_t compute_restart_x; /* ordinal28 */
4387 uint32_t compute_restart_y; /* ordinal29 */
4388 uint32_t compute_restart_z; /* ordinal30 */
4389 uint32_t compute_thread_trace_enable; /* ordinal31 */
4390 uint32_t compute_misc_reserved; /* ordinal32 */
4391 uint32_t compute_dispatch_id; /* ordinal33 */
4392 uint32_t compute_threadgroup_id; /* ordinal34 */
4393 uint32_t compute_relaunch; /* ordinal35 */
4394 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
4395 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
4396 uint32_t compute_wave_restore_control; /* ordinal38 */
4397 uint32_t reserved9; /* ordinal39 */
4398 uint32_t reserved10; /* ordinal40 */
4399 uint32_t reserved11; /* ordinal41 */
4400 uint32_t reserved12; /* ordinal42 */
4401 uint32_t reserved13; /* ordinal43 */
4402 uint32_t reserved14; /* ordinal44 */
4403 uint32_t reserved15; /* ordinal45 */
4404 uint32_t reserved16; /* ordinal46 */
4405 uint32_t reserved17; /* ordinal47 */
4406 uint32_t reserved18; /* ordinal48 */
4407 uint32_t reserved19; /* ordinal49 */
4408 uint32_t reserved20; /* ordinal50 */
4409 uint32_t reserved21; /* ordinal51 */
4410 uint32_t reserved22; /* ordinal52 */
4411 uint32_t reserved23; /* ordinal53 */
4412 uint32_t reserved24; /* ordinal54 */
4413 uint32_t reserved25; /* ordinal55 */
4414 uint32_t reserved26; /* ordinal56 */
4415 uint32_t reserved27; /* ordinal57 */
4416 uint32_t reserved28; /* ordinal58 */
4417 uint32_t reserved29; /* ordinal59 */
4418 uint32_t reserved30; /* ordinal60 */
4419 uint32_t reserved31; /* ordinal61 */
4420 uint32_t reserved32; /* ordinal62 */
4421 uint32_t reserved33; /* ordinal63 */
4422 uint32_t reserved34; /* ordinal64 */
4423 uint32_t compute_user_data_0; /* ordinal65 */
4424 uint32_t compute_user_data_1; /* ordinal66 */
4425 uint32_t compute_user_data_2; /* ordinal67 */
4426 uint32_t compute_user_data_3; /* ordinal68 */
4427 uint32_t compute_user_data_4; /* ordinal69 */
4428 uint32_t compute_user_data_5; /* ordinal70 */
4429 uint32_t compute_user_data_6; /* ordinal71 */
4430 uint32_t compute_user_data_7; /* ordinal72 */
4431 uint32_t compute_user_data_8; /* ordinal73 */
4432 uint32_t compute_user_data_9; /* ordinal74 */
4433 uint32_t compute_user_data_10; /* ordinal75 */
4434 uint32_t compute_user_data_11; /* ordinal76 */
4435 uint32_t compute_user_data_12; /* ordinal77 */
4436 uint32_t compute_user_data_13; /* ordinal78 */
4437 uint32_t compute_user_data_14; /* ordinal79 */
4438 uint32_t compute_user_data_15; /* ordinal80 */
4439 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
4440 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
4441 uint32_t reserved35; /* ordinal83 */
4442 uint32_t reserved36; /* ordinal84 */
4443 uint32_t reserved37; /* ordinal85 */
4444 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
4445 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
4446 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
4447 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
4448 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
4449 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
4450 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
4451 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
4452 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
4453 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
4454 uint32_t reserved38; /* ordinal96 */
4455 uint32_t reserved39; /* ordinal97 */
4456 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
4457 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
4458 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
4459 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
4460 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
4461 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
4462 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
4463 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
4464 uint32_t reserved40; /* ordinal106 */
4465 uint32_t reserved41; /* ordinal107 */
4466 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
4467 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
4468 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
4469 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
4470 uint32_t reserved42; /* ordinal112 */
4471 uint32_t reserved43; /* ordinal113 */
4472 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
4473 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
4474 uint32_t cp_packet_id_lo; /* ordinal116 */
4475 uint32_t cp_packet_id_hi; /* ordinal117 */
4476 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
4477 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
4478 uint32_t gds_save_base_addr_lo; /* ordinal120 */
4479 uint32_t gds_save_base_addr_hi; /* ordinal121 */
4480 uint32_t gds_save_mask_lo; /* ordinal122 */
4481 uint32_t gds_save_mask_hi; /* ordinal123 */
4482 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
4483 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
4484 uint32_t reserved44; /* ordinal126 */
4485 uint32_t reserved45; /* ordinal127 */
4486 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
4487 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
4488 uint32_t cp_hqd_active; /* ordinal130 */
4489 uint32_t cp_hqd_vmid; /* ordinal131 */
4490 uint32_t cp_hqd_persistent_state; /* ordinal132 */
4491 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
4492 uint32_t cp_hqd_queue_priority; /* ordinal134 */
4493 uint32_t cp_hqd_quantum; /* ordinal135 */
4494 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
4495 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
4496 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
4497 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
4498 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
4499 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
4500 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
4501 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
4502 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
4503 uint32_t cp_hqd_pq_control; /* ordinal145 */
4504 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
4505 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
4506 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
4507 uint32_t cp_hqd_ib_control; /* ordinal149 */
4508 uint32_t cp_hqd_iq_timer; /* ordinal150 */
4509 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
4510 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
4511 uint32_t cp_hqd_dma_offload; /* ordinal153 */
4512 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
4513 uint32_t cp_hqd_msg_type; /* ordinal155 */
4514 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
4515 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
4516 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
4517 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
4518 uint32_t cp_hqd_hq_status0; /* ordinal160 */
4519 uint32_t cp_hqd_hq_control0; /* ordinal161 */
4520 uint32_t cp_mqd_control; /* ordinal162 */
4521 uint32_t cp_hqd_hq_status1; /* ordinal163 */
4522 uint32_t cp_hqd_hq_control1; /* ordinal164 */
4523 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
4524 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
4525 uint32_t cp_hqd_eop_control; /* ordinal167 */
4526 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
4527 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
4528 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
4529 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
4530 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
4531 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
4532 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
4533 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
4534 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
4535 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
4536 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
4537 uint32_t cp_hqd_error; /* ordinal179 */
4538 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
4539 uint32_t cp_hqd_eop_dones; /* ordinal181 */
4540 uint32_t reserved46; /* ordinal182 */
4541 uint32_t reserved47; /* ordinal183 */
4542 uint32_t reserved48; /* ordinal184 */
4543 uint32_t reserved49; /* ordinal185 */
4544 uint32_t reserved50; /* ordinal186 */
4545 uint32_t reserved51; /* ordinal187 */
4546 uint32_t reserved52; /* ordinal188 */
4547 uint32_t reserved53; /* ordinal189 */
4548 uint32_t reserved54; /* ordinal190 */
4549 uint32_t reserved55; /* ordinal191 */
4550 uint32_t iqtimer_pkt_header; /* ordinal192 */
4551 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
4552 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
4553 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
4554 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
4555 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
4556 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
4557 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
4558 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
4559 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
4560 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
4561 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
4562 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
4563 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
4564 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
4565 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
4566 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
4567 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
4568 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
4569 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
4570 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
4571 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
4572 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
4573 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
4574 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
4575 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
4576 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
4577 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
4578 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
4579 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
4580 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
4581 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
4582 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
4583 uint32_t reserved56; /* ordinal225 */
4584 uint32_t reserved57; /* ordinal226 */
4585 uint32_t reserved58; /* ordinal227 */
4586 uint32_t set_resources_header; /* ordinal228 */
4587 uint32_t set_resources_dw1; /* ordinal229 */
4588 uint32_t set_resources_dw2; /* ordinal230 */
4589 uint32_t set_resources_dw3; /* ordinal231 */
4590 uint32_t set_resources_dw4; /* ordinal232 */
4591 uint32_t set_resources_dw5; /* ordinal233 */
4592 uint32_t set_resources_dw6; /* ordinal234 */
4593 uint32_t set_resources_dw7; /* ordinal235 */
4594 uint32_t reserved59; /* ordinal236 */
4595 uint32_t reserved60; /* ordinal237 */
4596 uint32_t reserved61; /* ordinal238 */
4597 uint32_t reserved62; /* ordinal239 */
4598 uint32_t reserved63; /* ordinal240 */
4599 uint32_t reserved64; /* ordinal241 */
4600 uint32_t reserved65; /* ordinal242 */
4601 uint32_t reserved66; /* ordinal243 */
4602 uint32_t reserved67; /* ordinal244 */
4603 uint32_t reserved68; /* ordinal245 */
4604 uint32_t reserved69; /* ordinal246 */
4605 uint32_t reserved70; /* ordinal247 */
4606 uint32_t reserved71; /* ordinal248 */
4607 uint32_t reserved72; /* ordinal249 */
4608 uint32_t reserved73; /* ordinal250 */
4609 uint32_t reserved74; /* ordinal251 */
4610 uint32_t reserved75; /* ordinal252 */
4611 uint32_t reserved76; /* ordinal253 */
4612 uint32_t reserved77; /* ordinal254 */
4613 uint32_t reserved78; /* ordinal255 */
4614
4615 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
4616};
4617
4618static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
4619{
4620 int i, r;
4621
4622 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4623 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4624
4625 if (ring->mqd_obj) {
4626 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4627 if (unlikely(r != 0))
4628 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
4629
4630 amdgpu_bo_unpin(ring->mqd_obj);
4631 amdgpu_bo_unreserve(ring->mqd_obj);
4632
4633 amdgpu_bo_unref(&ring->mqd_obj);
4634 ring->mqd_obj = NULL;
4635 }
4636 }
4637}
4638
4639static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
4640{
4641 int r, i, j;
4642 u32 tmp;
4643 bool use_doorbell = true;
4644 u64 hqd_gpu_addr;
4645 u64 mqd_gpu_addr;
4646 u64 eop_gpu_addr;
4647 u64 wb_gpu_addr;
4648 u32 *buf;
4649 struct vi_mqd *mqd;
4650
4651 /* init the pipes */
4652 mutex_lock(&adev->srbm_mutex);
4653 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
4654 int me = (i < 4) ? 1 : 2;
4655 int pipe = (i < 4) ? i : (i - 4);
4656
4657 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
4658 eop_gpu_addr >>= 8;
4659
4660 vi_srbm_select(adev, me, pipe, 0, 0);
4661
4662 /* write the EOP addr */
4663 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
4664 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
4665
4666 /* set the VMID assigned */
4667 WREG32(mmCP_HQD_VMID, 0);
4668
4669 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4670 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4671 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4672 (order_base_2(MEC_HPD_SIZE / 4) - 1));
4673 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
4674 }
4675 vi_srbm_select(adev, 0, 0, 0, 0);
4676 mutex_unlock(&adev->srbm_mutex);
4677
4678 /* init the queues. Just two for now. */
4679 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4680 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4681
4682 if (ring->mqd_obj == NULL) {
4683 r = amdgpu_bo_create(adev,
4684 sizeof(struct vi_mqd),
4685 PAGE_SIZE, true,
4686 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
72d7668b 4687 NULL, &ring->mqd_obj);
aaa36a97
AD		 4688 if (r) {
4689 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
4690 return r;
4691 }
4692 }
4693
4694 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4695 if (unlikely(r != 0)) {
4696 gfx_v8_0_cp_compute_fini(adev);
4697 return r;
4698 }
4699 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
4700 &mqd_gpu_addr);
4701 if (r) {
4702 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
4703 gfx_v8_0_cp_compute_fini(adev);
4704 return r;
4705 }
4706 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
4707 if (r) {
4708 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
4709 gfx_v8_0_cp_compute_fini(adev);
4710 return r;
4711 }
4712
4713 /* init the mqd struct */
4714 memset(buf, 0, sizeof(struct vi_mqd));
4715
4716 mqd = (struct vi_mqd *)buf;
4717 mqd->header = 0xC0310800;
4718 mqd->compute_pipelinestat_enable = 0x00000001;
4719 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4720 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4721 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4722 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4723 mqd->compute_misc_reserved = 0x00000003;
4724
4725 mutex_lock(&adev->srbm_mutex);
4726 vi_srbm_select(adev, ring->me,
4727 ring->pipe,
4728 ring->queue, 0);
4729
4730 /* disable wptr polling */
4731 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
4732 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
4733 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
4734
4735 mqd->cp_hqd_eop_base_addr_lo =
4736 RREG32(mmCP_HQD_EOP_BASE_ADDR);
4737 mqd->cp_hqd_eop_base_addr_hi =
4738 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
4739
4740 /* enable doorbell? */
4741 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4742 if (use_doorbell) {
4743 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4744 } else {
4745 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
4746 }
4747 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
4748 mqd->cp_hqd_pq_doorbell_control = tmp;
4749
4750 /* disable the queue if it's active */
4751 mqd->cp_hqd_dequeue_request = 0;
4752 mqd->cp_hqd_pq_rptr = 0;
4753 mqd->cp_hqd_pq_wptr= 0;
4754 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
4755 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
4756 for (j = 0; j < adev->usec_timeout; j++) {
4757 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
4758 break;
4759 udelay(1);
4760 }
4761 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
4762 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
4763 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
4764 }
4765
4766 /* set the pointer to the MQD */
4767 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
4768 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
4769 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
4770 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
4771
4772 /* set MQD vmid to 0 */
4773 tmp = RREG32(mmCP_MQD_CONTROL);
4774 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4775 WREG32(mmCP_MQD_CONTROL, tmp);
4776 mqd->cp_mqd_control = tmp;
4777
4778 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4779 hqd_gpu_addr = ring->gpu_addr >> 8;
4780 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4781 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4782 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
4783 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
4784
4785 /* set up the HQD, this is similar to CP_RB0_CNTL */
4786 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4787 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4788 (order_base_2(ring->ring_size / 4) - 1));
4789 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4790 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4791#ifdef __BIG_ENDIAN
4792 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4793#endif
4794 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4795 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4796 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4797 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4798 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
4799 mqd->cp_hqd_pq_control = tmp;
4800
4801 /* set the wb address wether it's enabled or not */
4802 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4803 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4804 mqd->cp_hqd_pq_rptr_report_addr_hi =
4805 upper_32_bits(wb_gpu_addr) & 0xffff;
4806 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
4807 mqd->cp_hqd_pq_rptr_report_addr_lo);
4808 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
4809 mqd->cp_hqd_pq_rptr_report_addr_hi);
4810
4811 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4812 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4813 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4814 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4815 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
4816 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
4817 mqd->cp_hqd_pq_wptr_poll_addr_hi);
4818
4819 /* enable the doorbell if requested */
4820 if (use_doorbell) {
bddf8026 4821 if ((adev->asic_type == CHIP_CARRIZO) ||
e3c7656c 4822 (adev->asic_type == CHIP_FIJI) ||
68182d90 4823 (adev->asic_type == CHIP_STONEY) ||
2cc0c0b5
FC		 4824 (adev->asic_type == CHIP_POLARIS11) ||
4825 (adev->asic_type == CHIP_POLARIS10)) {
aaa36a97
AD		 4826 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
4827 AMDGPU_DOORBELL_KIQ << 2);
4828 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
b8826b0c 4829 AMDGPU_DOORBELL_MEC_RING7 << 2);
aaa36a97
AD		 4830 }
4831 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4832 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4833 DOORBELL_OFFSET, ring->doorbell_index);
4834 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4835 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
4836 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
4837 mqd->cp_hqd_pq_doorbell_control = tmp;
4838
4839 } else {
4840 mqd->cp_hqd_pq_doorbell_control = 0;
4841 }
4842 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
4843 mqd->cp_hqd_pq_doorbell_control);
4844
845253e7
SJ		 4845 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4846 ring->wptr = 0;
4847 mqd->cp_hqd_pq_wptr = ring->wptr;
4848 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
4849 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4850
aaa36a97
AD		 4851 /* set the vmid for the queue */
4852 mqd->cp_hqd_vmid = 0;
4853 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
4854
4855 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4856 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4857 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
4858 mqd->cp_hqd_persistent_state = tmp;
68182d90 4859 if (adev->asic_type == CHIP_STONEY ||
2cc0c0b5
FC		 4860 adev->asic_type == CHIP_POLARIS11 ||
4861 adev->asic_type == CHIP_POLARIS10) {
3b55ddad
FC		 4862 tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
4863 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
4864 WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
4865 }
aaa36a97
AD		 4866
4867 /* activate the queue */
4868 mqd->cp_hqd_active = 1;
4869 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
4870
4871 vi_srbm_select(adev, 0, 0, 0, 0);
4872 mutex_unlock(&adev->srbm_mutex);
4873
4874 amdgpu_bo_kunmap(ring->mqd_obj);
4875 amdgpu_bo_unreserve(ring->mqd_obj);
4876 }
4877
4878 if (use_doorbell) {
4879 tmp = RREG32(mmCP_PQ_STATUS);
4880 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4881 WREG32(mmCP_PQ_STATUS, tmp);
4882 }
4883
6e9821b2 4884 gfx_v8_0_cp_compute_enable(adev, true);
aaa36a97
AD		 4885
4886 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4887 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4888
4889 ring->ready = true;
4890 r = amdgpu_ring_test_ring(ring);
4891 if (r)
4892 ring->ready = false;
4893 }
4894
4895 return 0;
4896}
4897
4898static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4899{
4900 int r;
4901
e3c7656c 4902 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 4903 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4904
e61710c5 4905 if (!adev->pp_enabled) {
ba5c2a87
RZ		 4906 if (!adev->firmware.smu_load) {
4907 /* legacy firmware loading */
4908 r = gfx_v8_0_cp_gfx_load_microcode(adev);
4909 if (r)
4910 return r;
aaa36a97 4911
ba5c2a87
RZ		 4912 r = gfx_v8_0_cp_compute_load_microcode(adev);
4913 if (r)
4914 return r;
4915 } else {
4916 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4917 AMDGPU_UCODE_ID_CP_CE);
4918 if (r)
4919 return -EINVAL;
4920
4921 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4922 AMDGPU_UCODE_ID_CP_PFP);
4923 if (r)
4924 return -EINVAL;
4925
4926 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4927 AMDGPU_UCODE_ID_CP_ME);
4928 if (r)
4929 return -EINVAL;
4930
951e0962
AD		 4931 if (adev->asic_type == CHIP_TOPAZ) {
4932 r = gfx_v8_0_cp_compute_load_microcode(adev);
4933 if (r)
4934 return r;
4935 } else {
4936 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4937 AMDGPU_UCODE_ID_CP_MEC1);
4938 if (r)
4939 return -EINVAL;
4940 }
ba5c2a87 4941 }
aaa36a97
AD		 4942 }
4943
4944 r = gfx_v8_0_cp_gfx_resume(adev);
4945 if (r)
4946 return r;
4947
4948 r = gfx_v8_0_cp_compute_resume(adev);
4949 if (r)
4950 return r;
4951
4952 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4953
4954 return 0;
4955}
4956
4957static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4958{
4959 gfx_v8_0_cp_gfx_enable(adev, enable);
4960 gfx_v8_0_cp_compute_enable(adev, enable);
4961}
4962
5fc3aeeb 4963static int gfx_v8_0_hw_init(void *handle)
aaa36a97
AD		 4964{
4965 int r;
5fc3aeeb 4966 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 4967
4968 gfx_v8_0_init_golden_registers(adev);
4969
4970 gfx_v8_0_gpu_init(adev);
4971
4972 r = gfx_v8_0_rlc_resume(adev);
4973 if (r)
4974 return r;
4975
4976 r = gfx_v8_0_cp_resume(adev);
4977 if (r)
4978 return r;
4979
4980 return r;
4981}
4982
5fc3aeeb 4983static int gfx_v8_0_hw_fini(void *handle)
aaa36a97 4984{
5fc3aeeb 4985 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4986
1d22a454
AD		 4987 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4988 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
aaa36a97
AD		 4989 gfx_v8_0_cp_enable(adev, false);
4990 gfx_v8_0_rlc_stop(adev);
4991 gfx_v8_0_cp_compute_fini(adev);
4992
62a86fc2
EH		 4993 amdgpu_set_powergating_state(adev,
4994 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE);
4995
aaa36a97
AD		 4996 return 0;
4997}
4998
5fc3aeeb 4999static int gfx_v8_0_suspend(void *handle)
aaa36a97 5000{
5fc3aeeb 5001 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5002
aaa36a97
AD		 5003 return gfx_v8_0_hw_fini(adev);
5004}
5005
5fc3aeeb 5006static int gfx_v8_0_resume(void *handle)
aaa36a97 5007{
5fc3aeeb 5008 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5009
aaa36a97
AD		 5010 return gfx_v8_0_hw_init(adev);
5011}
5012
5fc3aeeb 5013static bool gfx_v8_0_is_idle(void *handle)
aaa36a97 5014{
5fc3aeeb 5015 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5016
aaa36a97
AD		 5017 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
5018 return false;
5019 else
5020 return true;
5021}
5022
5fc3aeeb 5023static int gfx_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 5024{
5025 unsigned i;
5026 u32 tmp;
5fc3aeeb 5027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 5028
5029 for (i = 0; i < adev->usec_timeout; i++) {
5030 /* read MC_STATUS */
5031 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
5032
5033 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
5034 return 0;
5035 udelay(1);
5036 }
5037 return -ETIMEDOUT;
5038}
5039
5fc3aeeb 5040static int gfx_v8_0_soft_reset(void *handle)
aaa36a97
AD		 5041{
5042 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5043 u32 tmp;
5fc3aeeb 5044 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 5045
5046 /* GRBM_STATUS */
5047 tmp = RREG32(mmGRBM_STATUS);
5048 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
5049 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
5050 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
5051 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
5052 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
5053 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
5054 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5055 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
5056 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5057 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
5058 }
5059
5060 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
5061 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5062 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
5063 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5064 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
5065 }
5066
5067 /* GRBM_STATUS2 */
5068 tmp = RREG32(mmGRBM_STATUS2);
5069 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
5070 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5071 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5072
5073 /* SRBM_STATUS */
5074 tmp = RREG32(mmSRBM_STATUS);
5075 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
5076 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5077 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
5078
5079 if (grbm_soft_reset || srbm_soft_reset) {
aaa36a97
AD		 5080 /* stop the rlc */
5081 gfx_v8_0_rlc_stop(adev);
5082
5083 /* Disable GFX parsing/prefetching */
5084 gfx_v8_0_cp_gfx_enable(adev, false);
5085
5086 /* Disable MEC parsing/prefetching */
7776a693
AD		 5087 gfx_v8_0_cp_compute_enable(adev, false);
5088
5089 if (grbm_soft_reset || srbm_soft_reset) {
5090 tmp = RREG32(mmGMCON_DEBUG);
5091 tmp = REG_SET_FIELD(tmp,
5092 GMCON_DEBUG, GFX_STALL, 1);
5093 tmp = REG_SET_FIELD(tmp,
5094 GMCON_DEBUG, GFX_CLEAR, 1);
5095 WREG32(mmGMCON_DEBUG, tmp);
5096
5097 udelay(50);
5098 }
aaa36a97
AD		 5099
5100 if (grbm_soft_reset) {
5101 tmp = RREG32(mmGRBM_SOFT_RESET);
5102 tmp |= grbm_soft_reset;
5103 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5104 WREG32(mmGRBM_SOFT_RESET, tmp);
5105 tmp = RREG32(mmGRBM_SOFT_RESET);
5106
5107 udelay(50);
5108
5109 tmp &= ~grbm_soft_reset;
5110 WREG32(mmGRBM_SOFT_RESET, tmp);
5111 tmp = RREG32(mmGRBM_SOFT_RESET);
5112 }
5113
5114 if (srbm_soft_reset) {
5115 tmp = RREG32(mmSRBM_SOFT_RESET);
5116 tmp |= srbm_soft_reset;
5117 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5118 WREG32(mmSRBM_SOFT_RESET, tmp);
5119 tmp = RREG32(mmSRBM_SOFT_RESET);
5120
5121 udelay(50);
5122
5123 tmp &= ~srbm_soft_reset;
5124 WREG32(mmSRBM_SOFT_RESET, tmp);
5125 tmp = RREG32(mmSRBM_SOFT_RESET);
5126 }
7776a693
AD		 5127
5128 if (grbm_soft_reset || srbm_soft_reset) {
5129 tmp = RREG32(mmGMCON_DEBUG);
5130 tmp = REG_SET_FIELD(tmp,
5131 GMCON_DEBUG, GFX_STALL, 0);
5132 tmp = REG_SET_FIELD(tmp,
5133 GMCON_DEBUG, GFX_CLEAR, 0);
5134 WREG32(mmGMCON_DEBUG, tmp);
5135 }
5136
aaa36a97
AD		 5137 /* Wait a little for things to settle down */
5138 udelay(50);
aaa36a97
AD		 5139 }
5140 return 0;
5141}
5142
5143/**
5144 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5145 *
5146 * @adev: amdgpu_device pointer
5147 *
5148 * Fetches a GPU clock counter snapshot.
5149 * Returns the 64 bit clock counter snapshot.
5150 */
b95e31fd 5151static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
aaa36a97
AD		 5152{
5153 uint64_t clock;
5154
5155 mutex_lock(&adev->gfx.gpu_clock_mutex);
5156 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5157 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5158 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5159 mutex_unlock(&adev->gfx.gpu_clock_mutex);
5160 return clock;
5161}
5162
5163static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5164 uint32_t vmid,
5165 uint32_t gds_base, uint32_t gds_size,
5166 uint32_t gws_base, uint32_t gws_size,
5167 uint32_t oa_base, uint32_t oa_size)
5168{
5169 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
5170 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
5171
5172 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
5173 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
5174
5175 oa_base = oa_base >> AMDGPU_OA_SHIFT;
5176 oa_size = oa_size >> AMDGPU_OA_SHIFT;
5177
5178 /* GDS Base */
5179 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5180 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5181 WRITE_DATA_DST_SEL(0)));
5182 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5183 amdgpu_ring_write(ring, 0);
5184 amdgpu_ring_write(ring, gds_base);
5185
5186 /* GDS Size */
5187 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5188 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5189 WRITE_DATA_DST_SEL(0)));
5190 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5191 amdgpu_ring_write(ring, 0);
5192 amdgpu_ring_write(ring, gds_size);
5193
5194 /* GWS */
5195 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5196 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5197 WRITE_DATA_DST_SEL(0)));
5198 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5199 amdgpu_ring_write(ring, 0);
5200 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5201
5202 /* OA */
5203 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5204 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5205 WRITE_DATA_DST_SEL(0)));
5206 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5207 amdgpu_ring_write(ring, 0);
5208 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5209}
5210
b95e31fd
AD		 5211static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5212 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
05fb7291 5213 .select_se_sh = &gfx_v8_0_select_se_sh,
b95e31fd
AD		 5214};
5215
5fc3aeeb 5216static int gfx_v8_0_early_init(void *handle)
aaa36a97 5217{
5fc3aeeb 5218 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 5219
5220 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5221 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
b95e31fd 5222 adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
aaa36a97
AD		 5223 gfx_v8_0_set_ring_funcs(adev);
5224 gfx_v8_0_set_irq_funcs(adev);
5225 gfx_v8_0_set_gds_init(adev);
dbff57bc 5226 gfx_v8_0_set_rlc_funcs(adev);
aaa36a97
AD		 5227
5228 return 0;
5229}
5230
ccba7691
AD		 5231static int gfx_v8_0_late_init(void *handle)
5232{
5233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5234 int r;
5235
1d22a454
AD		 5236 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5237 if (r)
5238 return r;
5239
5240 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5241 if (r)
5242 return r;
5243
ccba7691
AD		 5244 /* requires IBs so do in late init after IB pool is initialized */
5245 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5246 if (r)
5247 return r;
5248
62a86fc2
EH		 5249 amdgpu_set_powergating_state(adev,
5250 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE);
5251
ccba7691
AD		 5252 return 0;
5253}
5254
c2546f55
AD		 5255static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5256 bool enable)
62a86fc2
EH		 5257{
5258 uint32_t data, temp;
5259
c2546f55
AD		 5260 if (adev->asic_type == CHIP_POLARIS11)
5261 /* Send msg to SMU via Powerplay */
5262 amdgpu_set_powergating_state(adev,
5263 AMD_IP_BLOCK_TYPE_SMC,
5264 enable ?
5265 AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
62a86fc2 5266
dad4acc8
TSD		 5267 temp = data = RREG32(mmRLC_PG_CNTL);
5268 /* Enable static MGPG */
5269 if (enable)
62a86fc2 5270 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
dad4acc8 5271 else
62a86fc2
EH		 5272 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
5273
dad4acc8
TSD		 5274 if (temp != data)
5275 WREG32(mmRLC_PG_CNTL, data);
62a86fc2
EH		 5276}
5277
c2546f55
AD		 5278static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5279 bool enable)
62a86fc2
EH		 5280{
5281 uint32_t data, temp;
5282
dad4acc8
TSD		 5283 temp = data = RREG32(mmRLC_PG_CNTL);
5284 /* Enable dynamic MGPG */
5285 if (enable)
62a86fc2 5286 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
dad4acc8 5287 else
62a86fc2
EH		 5288 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
5289
dad4acc8
TSD		 5290 if (temp != data)
5291 WREG32(mmRLC_PG_CNTL, data);
62a86fc2
EH		 5292}
5293
2cc0c0b5 5294static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
62a86fc2
EH		 5295 bool enable)
5296{
5297 uint32_t data, temp;
5298
dad4acc8
TSD		 5299 temp = data = RREG32(mmRLC_PG_CNTL);
5300 /* Enable quick PG */
5301 if (enable)
78f73bf0 5302 data |= RLC_PG_CNTL__QUICK_PG_ENABLE_MASK;
dad4acc8 5303 else
78f73bf0 5304 data &= ~RLC_PG_CNTL__QUICK_PG_ENABLE_MASK;
62a86fc2 5305
dad4acc8
TSD		 5306 if (temp != data)
5307 WREG32(mmRLC_PG_CNTL, data);
62a86fc2
EH		 5308}
5309
2c547165
AD		 5310static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
5311 bool enable)
5312{
5313 u32 data, orig;
5314
5315 orig = data = RREG32(mmRLC_PG_CNTL);
5316
5317 if (enable)
5318 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5319 else
5320 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5321
5322 if (orig != data)
5323 WREG32(mmRLC_PG_CNTL, data);
5324}
5325
5326static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
5327 bool enable)
5328{
5329 u32 data, orig;
5330
5331 orig = data = RREG32(mmRLC_PG_CNTL);
5332
5333 if (enable)
5334 data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
5335 else
5336 data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
5337
5338 if (orig != data)
5339 WREG32(mmRLC_PG_CNTL, data);
5340
5341 /* Read any GFX register to wake up GFX. */
5342 if (!enable)
5343 data = RREG32(mmDB_RENDER_CONTROL);
5344}
5345
5346static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
5347 bool enable)
5348{
5349 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
5350 cz_enable_gfx_cg_power_gating(adev, true);
5351 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
5352 cz_enable_gfx_pipeline_power_gating(adev, true);
5353 } else {
5354 cz_enable_gfx_cg_power_gating(adev, false);
5355 cz_enable_gfx_pipeline_power_gating(adev, false);
5356 }
5357}
5358
5fc3aeeb 5359static int gfx_v8_0_set_powergating_state(void *handle,
5360 enum amd_powergating_state state)
aaa36a97 5361{
62a86fc2 5362 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2c547165 5363 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
62a86fc2
EH		 5364
5365 if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5366 return 0;
5367
5368 switch (adev->asic_type) {
2c547165
AD		 5369 case CHIP_CARRIZO:
5370 case CHIP_STONEY:
5371 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
5372 cz_update_gfx_cg_power_gating(adev, enable);
5373
5374 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5375 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5376 else
5377 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5378
5379 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5380 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5381 else
5382 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5383 break;
2cc0c0b5 5384 case CHIP_POLARIS11:
7ba0eb6d
AD		 5385 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5386 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5387 else
5388 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5389
5390 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5391 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5392 else
5393 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5394
5395 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
5396 polaris11_enable_gfx_quick_mg_power_gating(adev, true);
62a86fc2 5397 else
7ba0eb6d 5398 polaris11_enable_gfx_quick_mg_power_gating(adev, false);
62a86fc2
EH		 5399 break;
5400 default:
5401 break;
5402 }
5403
aaa36a97
AD		 5404 return 0;
5405}
5406
79deaaf4 5407static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
14698b6c 5408 uint32_t reg_addr, uint32_t cmd)
6e378858
EH		 5409{
5410 uint32_t data;
5411
5412 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5413
5414 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5415 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5416
5417 data = RREG32(mmRLC_SERDES_WR_CTRL);
146f256f
AD		 5418 if (adev->asic_type == CHIP_STONEY)
5419 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
6e378858
EH		 5420 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5421 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5422 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5423 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5424 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5425 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5426 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
6e378858 5427 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
146f256f
AD		 5428 else
5429 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5430 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5431 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5432 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5433 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5434 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5435 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5436 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5437 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5438 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5439 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
6e378858 5440 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
146f256f
AD		 5441 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5442 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5443 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
6e378858
EH		 5444
5445 WREG32(mmRLC_SERDES_WR_CTRL, data);
5446}
5447
dbff57bc
AD		 5448#define MSG_ENTER_RLC_SAFE_MODE 1
5449#define MSG_EXIT_RLC_SAFE_MODE 0
5450
5451#define RLC_GPR_REG2__REQ_MASK 0x00000001
5452#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5453#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5454
5455static void cz_enter_rlc_safe_mode(struct amdgpu_device *adev)
5456{
5457 u32 data = 0;
5458 unsigned i;
5459
5460 data = RREG32(mmRLC_CNTL);
5461 if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
5462 return;
5463
5464 if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
5465 (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
5466 AMD_PG_SUPPORT_GFX_DMG))) {
5467 data |= RLC_GPR_REG2__REQ_MASK;
5468 data &= ~RLC_GPR_REG2__MESSAGE_MASK;
5469 data |= (MSG_ENTER_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
5470 WREG32(mmRLC_GPR_REG2, data);
5471
5472 for (i = 0; i < adev->usec_timeout; i++) {
5473 if ((RREG32(mmRLC_GPM_STAT) &
5474 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5475 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5476 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5477 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5478 break;
5479 udelay(1);
5480 }
5481
5482 for (i = 0; i < adev->usec_timeout; i++) {
5483 if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)
5484 break;
5485 udelay(1);
5486 }
5487 adev->gfx.rlc.in_safe_mode = true;
5488 }
5489}
5490
5491static void cz_exit_rlc_safe_mode(struct amdgpu_device *adev)
5492{
5493 u32 data;
5494 unsigned i;
5495
5496 data = RREG32(mmRLC_CNTL);
5497 if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
5498 return;
5499
5500 if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
5501 (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
5502 AMD_PG_SUPPORT_GFX_DMG))) {
5503 data |= RLC_GPR_REG2__REQ_MASK;
5504 data &= ~RLC_GPR_REG2__MESSAGE_MASK;
5505 data |= (MSG_EXIT_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
5506 WREG32(mmRLC_GPR_REG2, data);
5507 adev->gfx.rlc.in_safe_mode = false;
5508 }
5509
5510 for (i = 0; i < adev->usec_timeout; i++) {
5511 if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)
5512 break;
5513 udelay(1);
5514 }
5515}
5516
5517static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev)
5518{
5519 u32 data;
5520 unsigned i;
5521
5522 data = RREG32(mmRLC_CNTL);
5523 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
5524 return;
5525
5526 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
5527 data |= RLC_SAFE_MODE__CMD_MASK;
5528 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5529 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5530 WREG32(mmRLC_SAFE_MODE, data);
5531
5532 for (i = 0; i < adev->usec_timeout; i++) {
5533 if ((RREG32(mmRLC_GPM_STAT) &
5534 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5535 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5536 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5537 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5538 break;
5539 udelay(1);
5540 }
5541
5542 for (i = 0; i < adev->usec_timeout; i++) {
5543 if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)
5544 break;
5545 udelay(1);
5546 }
5547 adev->gfx.rlc.in_safe_mode = true;
5548 }
5549}
5550
5551static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev)
5552{
5553 u32 data = 0;
5554 unsigned i;
5555
5556 data = RREG32(mmRLC_CNTL);
5557 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
5558 return;
5559
5560 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
5561 if (adev->gfx.rlc.in_safe_mode) {
5562 data |= RLC_SAFE_MODE__CMD_MASK;
5563 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5564 WREG32(mmRLC_SAFE_MODE, data);
5565 adev->gfx.rlc.in_safe_mode = false;
5566 }
5567 }
5568
5569 for (i = 0; i < adev->usec_timeout; i++) {
5570 if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)
5571 break;
5572 udelay(1);
5573 }
5574}
5575
5576static void gfx_v8_0_nop_enter_rlc_safe_mode(struct amdgpu_device *adev)
5577{
5578 adev->gfx.rlc.in_safe_mode = true;
5579}
5580
5581static void gfx_v8_0_nop_exit_rlc_safe_mode(struct amdgpu_device *adev)
5582{
5583 adev->gfx.rlc.in_safe_mode = false;
5584}
5585
5586static const struct amdgpu_rlc_funcs cz_rlc_funcs = {
5587 .enter_safe_mode = cz_enter_rlc_safe_mode,
5588 .exit_safe_mode = cz_exit_rlc_safe_mode
5589};
5590
5591static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5592 .enter_safe_mode = iceland_enter_rlc_safe_mode,
5593 .exit_safe_mode = iceland_exit_rlc_safe_mode
5594};
5595
5596static const struct amdgpu_rlc_funcs gfx_v8_0_nop_rlc_funcs = {
5597 .enter_safe_mode = gfx_v8_0_nop_enter_rlc_safe_mode,
5598 .exit_safe_mode = gfx_v8_0_nop_exit_rlc_safe_mode
5599};
5600
5601static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5602 bool enable)
6e378858
EH		 5603{
5604 uint32_t temp, data;
5605
dbff57bc
AD		 5606 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5607
6e378858 5608 /* It is disabled by HW by default */
14698b6c
AD		 5609 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5610 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5611 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5612 /* 1 - RLC memory Light sleep */
5613 temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
5614 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5615 if (temp != data)
5616 WREG32(mmRLC_MEM_SLP_CNTL, data);
5617 }
6e378858 5618
14698b6c
AD		 5619 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5620 /* 2 - CP memory Light sleep */
5621 temp = data = RREG32(mmCP_MEM_SLP_CNTL);
5622 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5623 if (temp != data)
5624 WREG32(mmCP_MEM_SLP_CNTL, data);
5625 }
5626 }
6e378858
EH		 5627
5628 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5629 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
dbff57bc
AD		 5630 if (adev->flags & AMD_IS_APU)
5631 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5632 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5633 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5634 else
5635 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5636 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5637 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5638 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
6e378858
EH		 5639
5640 if (temp != data)
5641 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5642
5643 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5644 gfx_v8_0_wait_for_rlc_serdes(adev);
5645
5646 /* 5 - clear mgcg override */
79deaaf4 5647 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
6e378858 5648
14698b6c
AD		 5649 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5650 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5651 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5652 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5653 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5654 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5655 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5656 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5657 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5658 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5659 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5660 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5661 if (temp != data)
5662 WREG32(mmCGTS_SM_CTRL_REG, data);
5663 }
6e378858
EH		 5664 udelay(50);
5665
5666 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5667 gfx_v8_0_wait_for_rlc_serdes(adev);
5668 } else {
5669 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5670 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5671 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5672 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5673 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5674 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5675 if (temp != data)
5676 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5677
5678 /* 2 - disable MGLS in RLC */
5679 data = RREG32(mmRLC_MEM_SLP_CNTL);
5680 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5681 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5682 WREG32(mmRLC_MEM_SLP_CNTL, data);
5683 }
5684
5685 /* 3 - disable MGLS in CP */
5686 data = RREG32(mmCP_MEM_SLP_CNTL);
5687 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5688 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5689 WREG32(mmCP_MEM_SLP_CNTL, data);
5690 }
5691
5692 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5693 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5694 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5695 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5696 if (temp != data)
5697 WREG32(mmCGTS_SM_CTRL_REG, data);
5698
5699 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5700 gfx_v8_0_wait_for_rlc_serdes(adev);
5701
5702 /* 6 - set mgcg override */
79deaaf4 5703 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
6e378858
EH		 5704
5705 udelay(50);
5706
5707 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5708 gfx_v8_0_wait_for_rlc_serdes(adev);
5709 }
dbff57bc
AD		 5710
5711 adev->gfx.rlc.funcs->exit_safe_mode(adev);
6e378858
EH		 5712}
5713
dbff57bc
AD		 5714static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5715 bool enable)
6e378858
EH		 5716{
5717 uint32_t temp, temp1, data, data1;
5718
5719 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5720
dbff57bc
AD		 5721 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5722
14698b6c 5723 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
6e378858
EH		 5724 /* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
5725 * Cmp_busy/GFX_Idle interrupts
5726 */
5727 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5728
5729 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5730 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5731 if (temp1 != data1)
5732 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5733
5734 /* 2 wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5735 gfx_v8_0_wait_for_rlc_serdes(adev);
5736
5737 /* 3 - clear cgcg override */
79deaaf4 5738 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
6e378858
EH		 5739
5740 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5741 gfx_v8_0_wait_for_rlc_serdes(adev);
5742
5743 /* 4 - write cmd to set CGLS */
79deaaf4 5744 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
6e378858
EH		 5745
5746 /* 5 - enable cgcg */
5747 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5748
14698b6c
AD		 5749 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5750 /* enable cgls*/
5751 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
6e378858 5752
14698b6c
AD		 5753 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5754 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
6e378858 5755
14698b6c
AD		 5756 if (temp1 != data1)
5757 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5758 } else {
5759 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5760 }
6e378858
EH		 5761
5762 if (temp != data)
5763 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5764 } else {
5765 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5766 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5767
5768 /* TEST CGCG */
5769 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5770 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5771 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5772 if (temp1 != data1)
5773 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5774
5775 /* read gfx register to wake up cgcg */
5776 RREG32(mmCB_CGTT_SCLK_CTRL);
5777 RREG32(mmCB_CGTT_SCLK_CTRL);
5778 RREG32(mmCB_CGTT_SCLK_CTRL);
5779 RREG32(mmCB_CGTT_SCLK_CTRL);
5780
5781 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5782 gfx_v8_0_wait_for_rlc_serdes(adev);
5783
5784 /* write cmd to Set CGCG Overrride */
79deaaf4 5785 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
6e378858
EH		 5786
5787 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5788 gfx_v8_0_wait_for_rlc_serdes(adev);
5789
5790 /* write cmd to Clear CGLS */
79deaaf4 5791 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
6e378858
EH		 5792
5793 /* disable cgcg, cgls should be disabled too. */
5794 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
14698b6c 5795 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
6e378858
EH		 5796 if (temp != data)
5797 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5798 }
dbff57bc 5799
7894745a
TSD		 5800 gfx_v8_0_wait_for_rlc_serdes(adev);
5801
dbff57bc 5802 adev->gfx.rlc.funcs->exit_safe_mode(adev);
6e378858 5803}
dbff57bc
AD		 5804static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5805 bool enable)
6e378858
EH		 5806{
5807 if (enable) {
5808 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5809 * === MGCG + MGLS + TS(CG/LS) ===
5810 */
dbff57bc
AD		 5811 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5812 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
6e378858
EH		 5813 } else {
5814 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5815 * === CGCG + CGLS ===
5816 */
dbff57bc
AD		 5817 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5818 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
6e378858
EH		 5819 }
5820 return 0;
5821}
5822
5fc3aeeb 5823static int gfx_v8_0_set_clockgating_state(void *handle,
5824 enum amd_clockgating_state state)
aaa36a97 5825{
6e378858
EH		 5826 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5827
5828 switch (adev->asic_type) {
5829 case CHIP_FIJI:
dbff57bc
AD		 5830 case CHIP_CARRIZO:
5831 case CHIP_STONEY:
5832 gfx_v8_0_update_gfx_clock_gating(adev,
5833 state == AMD_CG_STATE_GATE ? true : false);
6e378858
EH		 5834 break;
5835 default:
5836 break;
5837 }
aaa36a97
AD		 5838 return 0;
5839}
5840
5841static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5842{
5843 u32 rptr;
5844
5845 rptr = ring->adev->wb.wb[ring->rptr_offs];
5846
5847 return rptr;
5848}
5849
5850static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5851{
5852 struct amdgpu_device *adev = ring->adev;
5853 u32 wptr;
5854
5855 if (ring->use_doorbell)
5856 /* XXX check if swapping is necessary on BE */
5857 wptr = ring->adev->wb.wb[ring->wptr_offs];
5858 else
5859 wptr = RREG32(mmCP_RB0_WPTR);
5860
5861 return wptr;
5862}
5863
5864static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5865{
5866 struct amdgpu_device *adev = ring->adev;
5867
5868 if (ring->use_doorbell) {
5869 /* XXX check if swapping is necessary on BE */
5870 adev->wb.wb[ring->wptr_offs] = ring->wptr;
5871 WDOORBELL32(ring->doorbell_index, ring->wptr);
5872 } else {
5873 WREG32(mmCP_RB0_WPTR, ring->wptr);
5874 (void)RREG32(mmCP_RB0_WPTR);
5875 }
5876}
5877
d2edb07b 5878static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD		 5879{
5880 u32 ref_and_mask, reg_mem_engine;
5881
5882 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
5883 switch (ring->me) {
5884 case 1:
5885 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
5886 break;
5887 case 2:
5888 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
5889 break;
5890 default:
5891 return;
5892 }
5893 reg_mem_engine = 0;
5894 } else {
5895 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
5896 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
5897 }
5898
5899 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5900 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
5901 WAIT_REG_MEM_FUNCTION(3) | /* == */
5902 reg_mem_engine));
5903 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
5904 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
5905 amdgpu_ring_write(ring, ref_and_mask);
5906 amdgpu_ring_write(ring, ref_and_mask);
5907 amdgpu_ring_write(ring, 0x20); /* poll interval */
5908}
5909
d35db561
CZ		 5910static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
5911{
5912 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5913 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5914 WRITE_DATA_DST_SEL(0) |
5915 WR_CONFIRM));
5916 amdgpu_ring_write(ring, mmHDP_DEBUG0);
5917 amdgpu_ring_write(ring, 0);
5918 amdgpu_ring_write(ring, 1);
5919
5920}
5921
93323131 5922static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
d88bf583
CK		 5923 struct amdgpu_ib *ib,
5924 unsigned vm_id, bool ctx_switch)
aaa36a97
AD		 5925{
5926 u32 header, control = 0;
5927 u32 next_rptr = ring->wptr + 5;
aa2bdb24 5928
f153d286 5929 if (ctx_switch)
aaa36a97
AD		 5930 next_rptr += 2;
5931
5932 next_rptr += 4;
5933 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5934 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
5935 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
5936 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
5937 amdgpu_ring_write(ring, next_rptr);
5938
aaa36a97 5939 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
f153d286 5940 if (ctx_switch) {
aaa36a97
AD		 5941 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5942 amdgpu_ring_write(ring, 0);
aaa36a97
AD		 5943 }
5944
de807f81 5945 if (ib->flags & AMDGPU_IB_FLAG_CE)
aaa36a97
AD		 5946 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
5947 else
5948 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5949
d88bf583 5950 control |= ib->length_dw | (vm_id << 24);
aaa36a97
AD		 5951
5952 amdgpu_ring_write(ring, header);
5953 amdgpu_ring_write(ring,
5954#ifdef __BIG_ENDIAN
5955 (2 << 0) |
5956#endif
5957 (ib->gpu_addr & 0xFFFFFFFC));
5958 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
5959 amdgpu_ring_write(ring, control);
5960}
5961
93323131 5962static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
d88bf583
CK		 5963 struct amdgpu_ib *ib,
5964 unsigned vm_id, bool ctx_switch)
93323131 5965{
5966 u32 header, control = 0;
5967 u32 next_rptr = ring->wptr + 5;
5968
5969 control |= INDIRECT_BUFFER_VALID;
5970
5971 next_rptr += 4;
5972 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5973 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
5974 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
5975 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
5976 amdgpu_ring_write(ring, next_rptr);
5977
5978 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5979
d88bf583 5980 control |= ib->length_dw | (vm_id << 24);
93323131 5981
5982 amdgpu_ring_write(ring, header);
5983 amdgpu_ring_write(ring,
5984#ifdef __BIG_ENDIAN
5985 (2 << 0) |
5986#endif
5987 (ib->gpu_addr & 0xFFFFFFFC));
5988 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
5989 amdgpu_ring_write(ring, control);
5990}
5991
aaa36a97 5992static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 5993 u64 seq, unsigned flags)
aaa36a97 5994{
890ee23f
CZ		 5995 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5996 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5997
aaa36a97
AD		 5998 /* EVENT_WRITE_EOP - flush caches, send int */
5999 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6000 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6001 EOP_TC_ACTION_EN |
f84e63f2 6002 EOP_TC_WB_ACTION_EN |
aaa36a97
AD		 6003 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6004 EVENT_INDEX(5)));
6005 amdgpu_ring_write(ring, addr & 0xfffffffc);
90bea0ab 6006 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 6007 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 6008 amdgpu_ring_write(ring, lower_32_bits(seq));
6009 amdgpu_ring_write(ring, upper_32_bits(seq));
22c01cc4 6010
aaa36a97
AD		 6011}
6012
b8c7b39e 6013static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
aaa36a97
AD		 6014{
6015 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
5907a0d8 6016 uint32_t seq = ring->fence_drv.sync_seq;
22c01cc4
AA		 6017 uint64_t addr = ring->fence_drv.gpu_addr;
6018
6019 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6020 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
9cac5373
CZ		 6021 WAIT_REG_MEM_FUNCTION(3) | /* equal */
6022 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
22c01cc4
AA		 6023 amdgpu_ring_write(ring, addr & 0xfffffffc);
6024 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
6025 amdgpu_ring_write(ring, seq);
6026 amdgpu_ring_write(ring, 0xffffffff);
6027 amdgpu_ring_write(ring, 4); /* poll interval */
aaa36a97 6028
5c3422b0 6029 if (usepfp) {
6030 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
6031 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6032 amdgpu_ring_write(ring, 0);
6033 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6034 amdgpu_ring_write(ring, 0);
6035 }
b8c7b39e
CK		 6036}
6037
6038static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6039 unsigned vm_id, uint64_t pd_addr)
6040{
6041 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
5c3422b0 6042
aaa36a97
AD		 6043 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6044 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
20a85ff8
CK		 6045 WRITE_DATA_DST_SEL(0)) |
6046 WR_CONFIRM);
aaa36a97
AD		 6047 if (vm_id < 8) {
6048 amdgpu_ring_write(ring,
6049 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
6050 } else {
6051 amdgpu_ring_write(ring,
6052 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
6053 }
6054 amdgpu_ring_write(ring, 0);
6055 amdgpu_ring_write(ring, pd_addr >> 12);
6056
aaa36a97
AD		 6057 /* bits 0-15 are the VM contexts0-15 */
6058 /* invalidate the cache */
6059 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6060 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6061 WRITE_DATA_DST_SEL(0)));
6062 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6063 amdgpu_ring_write(ring, 0);
6064 amdgpu_ring_write(ring, 1 << vm_id);
6065
6066 /* wait for the invalidate to complete */
6067 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6068 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6069 WAIT_REG_MEM_FUNCTION(0) | /* always */
6070 WAIT_REG_MEM_ENGINE(0))); /* me */
6071 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6072 amdgpu_ring_write(ring, 0);
6073 amdgpu_ring_write(ring, 0); /* ref */
6074 amdgpu_ring_write(ring, 0); /* mask */
6075 amdgpu_ring_write(ring, 0x20); /* poll interval */
6076
6077 /* compute doesn't have PFP */
6078 if (usepfp) {
6079 /* sync PFP to ME, otherwise we might get invalid PFP reads */
6080 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6081 amdgpu_ring_write(ring, 0x0);
5c3422b0 6082 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6083 amdgpu_ring_write(ring, 0);
6084 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6085 amdgpu_ring_write(ring, 0);
aaa36a97
AD		 6086 }
6087}
6088
aaa36a97
AD		 6089static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
6090{
6091 return ring->adev->wb.wb[ring->rptr_offs];
6092}
6093
6094static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6095{
6096 return ring->adev->wb.wb[ring->wptr_offs];
6097}
6098
6099static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6100{
6101 struct amdgpu_device *adev = ring->adev;
6102
6103 /* XXX check if swapping is necessary on BE */
6104 adev->wb.wb[ring->wptr_offs] = ring->wptr;
6105 WDOORBELL32(ring->doorbell_index, ring->wptr);
6106}
6107
6108static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6109 u64 addr, u64 seq,
890ee23f 6110 unsigned flags)
aaa36a97 6111{
890ee23f
CZ		 6112 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6113 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6114
aaa36a97
AD		 6115 /* RELEASE_MEM - flush caches, send int */
6116 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6117 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6118 EOP_TC_ACTION_EN |
a3d5aaa8 6119 EOP_TC_WB_ACTION_EN |
aaa36a97
AD		 6120 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6121 EVENT_INDEX(5)));
890ee23f 6122 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 6123 amdgpu_ring_write(ring, addr & 0xfffffffc);
6124 amdgpu_ring_write(ring, upper_32_bits(addr));
6125 amdgpu_ring_write(ring, lower_32_bits(seq));
6126 amdgpu_ring_write(ring, upper_32_bits(seq));
6127}
6128
6129static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6130 enum amdgpu_interrupt_state state)
6131{
6132 u32 cp_int_cntl;
6133
6134 switch (state) {
6135 case AMDGPU_IRQ_STATE_DISABLE:
6136 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6137 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6138 TIME_STAMP_INT_ENABLE, 0);
6139 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6140 break;
6141 case AMDGPU_IRQ_STATE_ENABLE:
6142 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6143 cp_int_cntl =
6144 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6145 TIME_STAMP_INT_ENABLE, 1);
6146 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6147 break;
6148 default:
6149 break;
6150 }
6151}
6152
6153static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6154 int me, int pipe,
6155 enum amdgpu_interrupt_state state)
6156{
6157 u32 mec_int_cntl, mec_int_cntl_reg;
6158
6159 /*
6160 * amdgpu controls only pipe 0 of MEC1. That's why this function only
6161 * handles the setting of interrupts for this specific pipe. All other
6162 * pipes' interrupts are set by amdkfd.
6163 */
6164
6165 if (me == 1) {
6166 switch (pipe) {
6167 case 0:
6168 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6169 break;
6170 default:
6171 DRM_DEBUG("invalid pipe %d\n", pipe);
6172 return;
6173 }
6174 } else {
6175 DRM_DEBUG("invalid me %d\n", me);
6176 return;
6177 }
6178
6179 switch (state) {
6180 case AMDGPU_IRQ_STATE_DISABLE:
6181 mec_int_cntl = RREG32(mec_int_cntl_reg);
6182 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
6183 TIME_STAMP_INT_ENABLE, 0);
6184 WREG32(mec_int_cntl_reg, mec_int_cntl);
6185 break;
6186 case AMDGPU_IRQ_STATE_ENABLE:
6187 mec_int_cntl = RREG32(mec_int_cntl_reg);
6188 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
6189 TIME_STAMP_INT_ENABLE, 1);
6190 WREG32(mec_int_cntl_reg, mec_int_cntl);
6191 break;
6192 default:
6193 break;
6194 }
6195}
6196
6197static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6198 struct amdgpu_irq_src *source,
6199 unsigned type,
6200 enum amdgpu_interrupt_state state)
6201{
6202 u32 cp_int_cntl;
6203
6204 switch (state) {
6205 case AMDGPU_IRQ_STATE_DISABLE:
6206 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6207 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6208 PRIV_REG_INT_ENABLE, 0);
6209 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6210 break;
6211 case AMDGPU_IRQ_STATE_ENABLE:
6212 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6213 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
04ab3b76 6214 PRIV_REG_INT_ENABLE, 1);
aaa36a97
AD		 6215 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6216 break;
6217 default:
6218 break;
6219 }
6220
6221 return 0;
6222}
6223
6224static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6225 struct amdgpu_irq_src *source,
6226 unsigned type,
6227 enum amdgpu_interrupt_state state)
6228{
6229 u32 cp_int_cntl;
6230
6231 switch (state) {
6232 case AMDGPU_IRQ_STATE_DISABLE:
6233 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6234 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6235 PRIV_INSTR_INT_ENABLE, 0);
6236 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6237 break;
6238 case AMDGPU_IRQ_STATE_ENABLE:
6239 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6240 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6241 PRIV_INSTR_INT_ENABLE, 1);
6242 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6243 break;
6244 default:
6245 break;
6246 }
6247
6248 return 0;
6249}
6250
6251static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6252 struct amdgpu_irq_src *src,
6253 unsigned type,
6254 enum amdgpu_interrupt_state state)
6255{
6256 switch (type) {
6257 case AMDGPU_CP_IRQ_GFX_EOP:
6258 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6259 break;
6260 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6261 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6262 break;
6263 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6264 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6265 break;
6266 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6267 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6268 break;
6269 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6270 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6271 break;
6272 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6273 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6274 break;
6275 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6276 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6277 break;
6278 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6279 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6280 break;
6281 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6282 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6283 break;
6284 default:
6285 break;
6286 }
6287 return 0;
6288}
6289
6290static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6291 struct amdgpu_irq_src *source,
6292 struct amdgpu_iv_entry *entry)
6293{
6294 int i;
6295 u8 me_id, pipe_id, queue_id;
6296 struct amdgpu_ring *ring;
6297
6298 DRM_DEBUG("IH: CP EOP\n");
6299 me_id = (entry->ring_id & 0x0c) >> 2;
6300 pipe_id = (entry->ring_id & 0x03) >> 0;
6301 queue_id = (entry->ring_id & 0x70) >> 4;
6302
6303 switch (me_id) {
6304 case 0:
6305 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6306 break;
6307 case 1:
6308 case 2:
6309 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6310 ring = &adev->gfx.compute_ring[i];
6311 /* Per-queue interrupt is supported for MEC starting from VI.
6312 * The interrupt can only be enabled/disabled per pipe instead of per queue.
6313 */
6314 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6315 amdgpu_fence_process(ring);
6316 }
6317 break;
6318 }
6319 return 0;
6320}
6321
6322static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6323 struct amdgpu_irq_src *source,
6324 struct amdgpu_iv_entry *entry)
6325{
6326 DRM_ERROR("Illegal register access in command stream\n");
6327 schedule_work(&adev->reset_work);
6328 return 0;
6329}
6330
6331static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6332 struct amdgpu_irq_src *source,
6333 struct amdgpu_iv_entry *entry)
6334{
6335 DRM_ERROR("Illegal instruction in command stream\n");
6336 schedule_work(&adev->reset_work);
6337 return 0;
6338}
6339
5fc3aeeb 6340const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
88a907d6 6341 .name = "gfx_v8_0",
aaa36a97 6342 .early_init = gfx_v8_0_early_init,
ccba7691 6343 .late_init = gfx_v8_0_late_init,
aaa36a97
AD		 6344 .sw_init = gfx_v8_0_sw_init,
6345 .sw_fini = gfx_v8_0_sw_fini,
6346 .hw_init = gfx_v8_0_hw_init,
6347 .hw_fini = gfx_v8_0_hw_fini,
6348 .suspend = gfx_v8_0_suspend,
6349 .resume = gfx_v8_0_resume,
6350 .is_idle = gfx_v8_0_is_idle,
6351 .wait_for_idle = gfx_v8_0_wait_for_idle,
6352 .soft_reset = gfx_v8_0_soft_reset,
aaa36a97
AD		 6353 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6354 .set_powergating_state = gfx_v8_0_set_powergating_state,
6355};
6356
6357static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6358 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
6359 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6360 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6361 .parse_cs = NULL,
93323131 6362 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
aaa36a97 6363 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
b8c7b39e 6364 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
aaa36a97
AD		 6365 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6366 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
d2edb07b 6367 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
d35db561 6368 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
aaa36a97
AD		 6369 .test_ring = gfx_v8_0_ring_test_ring,
6370 .test_ib = gfx_v8_0_ring_test_ib,
edff0e28 6371 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 6372 .pad_ib = amdgpu_ring_generic_pad_ib,
aaa36a97
AD		 6373};
6374
6375static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6376 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
6377 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6378 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6379 .parse_cs = NULL,
93323131 6380 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
aaa36a97 6381 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
b8c7b39e 6382 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
aaa36a97
AD		 6383 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6384 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
35074d2d 6385 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
d35db561 6386 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
aaa36a97
AD		 6387 .test_ring = gfx_v8_0_ring_test_ring,
6388 .test_ib = gfx_v8_0_ring_test_ib,
edff0e28 6389 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 6390 .pad_ib = amdgpu_ring_generic_pad_ib,
aaa36a97
AD		 6391};
6392
6393static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
6394{
6395 int i;
6396
6397 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6398 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
6399
6400 for (i = 0; i < adev->gfx.num_compute_rings; i++)
6401 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
6402}
6403
6404static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
6405 .set = gfx_v8_0_set_eop_interrupt_state,
6406 .process = gfx_v8_0_eop_irq,
6407};
6408
6409static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
6410 .set = gfx_v8_0_set_priv_reg_fault_state,
6411 .process = gfx_v8_0_priv_reg_irq,
6412};
6413
6414static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
6415 .set = gfx_v8_0_set_priv_inst_fault_state,
6416 .process = gfx_v8_0_priv_inst_irq,
6417};
6418
6419static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
6420{
6421 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6422 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
6423
6424 adev->gfx.priv_reg_irq.num_types = 1;
6425 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
6426
6427 adev->gfx.priv_inst_irq.num_types = 1;
6428 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
6429}
6430
dbff57bc
AD		 6431static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
6432{
6433 switch (adev->asic_type) {
6434 case CHIP_TOPAZ:
dbff57bc
AD		 6435 adev->gfx.rlc.funcs = &iceland_rlc_funcs;
6436 break;
6ab3886c 6437 case CHIP_STONEY:
dbff57bc
AD		 6438 case CHIP_CARRIZO:
6439 adev->gfx.rlc.funcs = &cz_rlc_funcs;
6440 break;
6441 default:
6442 adev->gfx.rlc.funcs = &gfx_v8_0_nop_rlc_funcs;
6443 break;
6444 }
6445}
6446
aaa36a97
AD		 6447static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
6448{
6449 /* init asci gds info */
6450 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
6451 adev->gds.gws.total_size = 64;
6452 adev->gds.oa.total_size = 16;
6453
6454 if (adev->gds.mem.total_size == 64 * 1024) {
6455 adev->gds.mem.gfx_partition_size = 4096;
6456 adev->gds.mem.cs_partition_size = 4096;
6457
6458 adev->gds.gws.gfx_partition_size = 4;
6459 adev->gds.gws.cs_partition_size = 4;
6460
6461 adev->gds.oa.gfx_partition_size = 4;
6462 adev->gds.oa.cs_partition_size = 1;
6463 } else {
6464 adev->gds.mem.gfx_partition_size = 1024;
6465 adev->gds.mem.cs_partition_size = 1024;
6466
6467 adev->gds.gws.gfx_partition_size = 16;
6468 adev->gds.gws.cs_partition_size = 16;
6469
6470 adev->gds.oa.gfx_partition_size = 4;
6471 adev->gds.oa.cs_partition_size = 4;
6472 }
6473}
6474
9de06de8
NH		 6475static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
6476 u32 bitmap)
6477{
6478 u32 data;
6479
6480 if (!bitmap)
6481 return;
6482
6483 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
6484 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
6485
6486 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
6487}
6488
8f8e00c1 6489static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
aaa36a97 6490{
8f8e00c1 6491 u32 data, mask;
aaa36a97 6492
8f8e00c1
AD		 6493 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
6494 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
aaa36a97 6495
8f8e00c1
AD		 6496 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
6497 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
aaa36a97 6498
6157bd7a 6499 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
aaa36a97 6500
8f8e00c1 6501 return (~data) & mask;
aaa36a97
AD		 6502}
6503
7dae69a2 6504static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
aaa36a97
AD		 6505{
6506 int i, j, k, counter, active_cu_number = 0;
6507 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7dae69a2 6508 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
9de06de8 6509 unsigned disable_masks[4 * 2];
aaa36a97 6510
6157bd7a
FC		 6511 memset(cu_info, 0, sizeof(*cu_info));
6512
9de06de8
NH		 6513 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
6514
aaa36a97
AD		 6515 mutex_lock(&adev->grbm_idx_mutex);
6516 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6517 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6518 mask = 1;
6519 ao_bitmap = 0;
6520 counter = 0;
8f8e00c1 6521 gfx_v8_0_select_se_sh(adev, i, j);
9de06de8
NH		 6522 if (i < 4 && j < 2)
6523 gfx_v8_0_set_user_cu_inactive_bitmap(
6524 adev, disable_masks[i * 2 + j]);
8f8e00c1 6525 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
aaa36a97
AD		 6526 cu_info->bitmap[i][j] = bitmap;
6527
8f8e00c1 6528 for (k = 0; k < 16; k ++) {
aaa36a97
AD		 6529 if (bitmap & mask) {
6530 if (counter < 2)
6531 ao_bitmap |= mask;
6532 counter ++;
6533 }
6534 mask <<= 1;
6535 }
6536 active_cu_number += counter;
6537 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
6538 }
6539 }
8f8e00c1
AD		 6540 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
6541 mutex_unlock(&adev->grbm_idx_mutex);
aaa36a97
AD		 6542
6543 cu_info->number = active_cu_number;
6544 cu_info->ao_cu_mask = ao_cu_mask;
aaa36a97 6545}
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