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drm/amdgpu: add ELM/BAF pci ids
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "vi.h"
28#include "vid.h"
29#include "amdgpu_ucode.h"
68182d90 30#include "amdgpu_atombios.h"
aaa36a97
AD		 31#include "clearstate_vi.h"
32
33#include "gmc/gmc_8_2_d.h"
34#include "gmc/gmc_8_2_sh_mask.h"
35
36#include "oss/oss_3_0_d.h"
37#include "oss/oss_3_0_sh_mask.h"
38
39#include "bif/bif_5_0_d.h"
40#include "bif/bif_5_0_sh_mask.h"
41
42#include "gca/gfx_8_0_d.h"
43#include "gca/gfx_8_0_enum.h"
44#include "gca/gfx_8_0_sh_mask.h"
45#include "gca/gfx_8_0_enum.h"
46
aaa36a97
AD		 47#include "dce/dce_10_0_d.h"
48#include "dce/dce_10_0_sh_mask.h"
49
50#define GFX8_NUM_GFX_RINGS 1
51#define GFX8_NUM_COMPUTE_RINGS 8
52
53#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
54#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
68182d90 55#define BAFFIN_GB_ADDR_CONFIG_GOLDEN 0x22011002
aaa36a97
AD		 56#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
57
58#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
59#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
60#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
61#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
62#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
63#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
64#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
65#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
66#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
67
6e378858
EH		 68#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
69#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
70#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
71#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
72#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
73#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
74
75/* BPM SERDES CMD */
76#define SET_BPM_SERDES_CMD 1
77#define CLE_BPM_SERDES_CMD 0
78
79/* BPM Register Address*/
80enum {
81 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
82 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
83 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
84 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
85 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
86 BPM_REG_FGCG_MAX
87};
88
2b6cd977
EH		 89#define RLC_FormatDirectRegListLength 14
90
c65444fe
JZ		 91MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
92MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
93MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
94MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
95MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
96MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
97
e3c7656c
SL		 98MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
99MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
100MODULE_FIRMWARE("amdgpu/stoney_me.bin");
101MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
102MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
103
c65444fe
JZ		 104MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
105MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
106MODULE_FIRMWARE("amdgpu/tonga_me.bin");
107MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
108MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
109MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
110
111MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
112MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
113MODULE_FIRMWARE("amdgpu/topaz_me.bin");
114MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
c65444fe 115MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
aaa36a97 116
af15a2d5
DZ		 117MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
118MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
119MODULE_FIRMWARE("amdgpu/fiji_me.bin");
120MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
121MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
122MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
123
68182d90
FC		 124MODULE_FIRMWARE("amdgpu/baffin_ce.bin");
125MODULE_FIRMWARE("amdgpu/baffin_pfp.bin");
126MODULE_FIRMWARE("amdgpu/baffin_me.bin");
127MODULE_FIRMWARE("amdgpu/baffin_mec.bin");
128MODULE_FIRMWARE("amdgpu/baffin_mec2.bin");
129MODULE_FIRMWARE("amdgpu/baffin_rlc.bin");
130
131MODULE_FIRMWARE("amdgpu/ellesmere_ce.bin");
132MODULE_FIRMWARE("amdgpu/ellesmere_pfp.bin");
133MODULE_FIRMWARE("amdgpu/ellesmere_me.bin");
134MODULE_FIRMWARE("amdgpu/ellesmere_mec.bin");
135MODULE_FIRMWARE("amdgpu/ellesmere_mec2.bin");
136MODULE_FIRMWARE("amdgpu/ellesmere_rlc.bin");
137
aaa36a97
AD		 138static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
139{
140 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
141 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
142 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
143 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
144 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
145 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
146 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
147 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
148 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
149 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
150 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
151 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
152 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
153 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
154 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
155 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
156};
157
158static const u32 golden_settings_tonga_a11[] =
159{
160 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
161 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
162 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
163 mmGB_GPU_ID, 0x0000000f, 0x00000000,
164 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
165 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
166 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 167 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 168 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
169 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 170 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 171 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
172 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
173 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
6a00a09e 174 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
aaa36a97
AD		 175};
176
177static const u32 tonga_golden_common_all[] =
178{
179 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
180 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
181 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
182 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
183 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
184 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
185 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
186 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
187};
188
189static const u32 tonga_mgcg_cgcg_init[] =
190{
191 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
192 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
193 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
194 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
195 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
196 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
197 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
198 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
199 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
200 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
201 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
202 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
203 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
204 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
205 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
206 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
207 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
208 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
209 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
210 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
211 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
212 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
213 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
214 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
215 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
216 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
217 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
218 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
219 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
220 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
221 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
222 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
223 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
224 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
225 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
226 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
227 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
228 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
229 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
230 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
231 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
232 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
233 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
234 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
235 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
236 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
237 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
238 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
239 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
240 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
241 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
242 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
243 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
244 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
245 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
246 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
247 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
248 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
249 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
250 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
251 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
252 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
253 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
254 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
255 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
256 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
257 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
258 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
259 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
260 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
261 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
262 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
263 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
264 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
265 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
266};
267
68182d90
FC		 268static const u32 golden_settings_baffin_a11[] =
269{
270 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
271 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
272 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
273 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
274 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
275 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
276 mmSQ_CONFIG, 0x07f80000, 0x07180000,
277 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
278 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
279 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
280 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
281 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
282};
283
284static const u32 baffin_golden_common_all[] =
285{
286 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
287 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
288 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
289 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
290 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
291 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
292 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
293 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
294};
295
296static const u32 golden_settings_ellesmere_a11[] =
297{
298 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
299 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
300 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
301 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
302 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
303 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
304 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
305 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
306 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
307 mmSQ_CONFIG, 0x07f80000, 0x07180000,
308 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
309 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
310 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
311 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
312};
313
314static const u32 ellesmere_golden_common_all[] =
315{
316 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
317 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
318 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
319 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
320 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
321 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
322 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
323 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
324};
325
af15a2d5
DZ		 326static const u32 fiji_golden_common_all[] =
327{
328 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
329 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
330 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
a7ca8ef9 331 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
af15a2d5
DZ		 332 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
333 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
334 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
a7ca8ef9
FC		 335 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
336 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
337 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
af15a2d5
DZ		 338};
339
340static const u32 golden_settings_fiji_a10[] =
341{
342 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
343 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
344 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
af15a2d5 345 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
a7ca8ef9
FC		 346 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
347 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
af15a2d5 348 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
a7ca8ef9
FC		 349 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
350 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
af15a2d5 351 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
a7ca8ef9 352 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
af15a2d5
DZ		 353};
354
355static const u32 fiji_mgcg_cgcg_init[] =
356{
a7ca8ef9 357 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
af15a2d5
DZ		 358 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
359 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
360 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
361 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
362 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
363 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
364 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
365 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
366 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
367 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
368 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
369 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
370 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
371 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
372 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
373 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
374 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
375 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
376 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
377 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
378 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
379 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
380 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
381 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
382 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
383 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
384 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
385 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
386 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
387 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
388 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
389 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
390 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
391 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
392};
393
aaa36a97
AD		 394static const u32 golden_settings_iceland_a11[] =
395{
396 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
397 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
398 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
399 mmGB_GPU_ID, 0x0000000f, 0x00000000,
400 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
401 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
402 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
403 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
6a00a09e 404 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 405 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
406 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 407 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 408 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
409 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
410 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
411};
412
413static const u32 iceland_golden_common_all[] =
414{
415 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
416 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
417 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
418 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
419 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
420 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
421 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
422 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
423};
424
425static const u32 iceland_mgcg_cgcg_init[] =
426{
427 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
428 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
429 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
430 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
431 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
432 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
433 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
434 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
435 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
436 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
437 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
438 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
439 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
440 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
441 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
443 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
444 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
445 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
446 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
447 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
448 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
449 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
450 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
452 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
453 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
454 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
455 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
456 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
457 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
458 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
459 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
460 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
461 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
462 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
463 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
464 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
465 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
466 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
467 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
468 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
469 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
470 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
471 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
472 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
473 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
474 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
475 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
476 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
477 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
478 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
479 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
480 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
481 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
482 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
483 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
484 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
485 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
486 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
487 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
488 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
489 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
490 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
491};
492
493static const u32 cz_golden_settings_a11[] =
494{
495 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
496 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
497 mmGB_GPU_ID, 0x0000000f, 0x00000000,
498 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
499 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 500 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97 501 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
6a00a09e 502 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 503 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
504 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
505};
506
507static const u32 cz_golden_common_all[] =
508{
509 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
510 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
511 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
512 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
513 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
514 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
515 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
516 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
517};
518
519static const u32 cz_mgcg_cgcg_init[] =
520{
521 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
522 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
523 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
524 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
525 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
526 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
527 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
528 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
529 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
530 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
531 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
532 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
533 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
534 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
535 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
536 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
537 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
538 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
539 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
540 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
541 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
542 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
543 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
544 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
545 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
546 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
547 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
548 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
549 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
550 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
551 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
552 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
553 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
554 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
555 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
556 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
557 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
558 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
559 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
560 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
561 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
562 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
563 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
564 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
565 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
566 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
567 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
568 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
569 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
570 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
571 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
572 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
573 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
574 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
575 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
576 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
577 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
578 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
579 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
580 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
581 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
582 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
583 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
584 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
585 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
586 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
587 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
588 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
589 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
590 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
591 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
592 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
593 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
594 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
595 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
596};
597
e3c7656c
SL		 598static const u32 stoney_golden_settings_a11[] =
599{
600 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
601 mmGB_GPU_ID, 0x0000000f, 0x00000000,
602 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
603 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
604 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
605 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
606 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
607 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
608 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
609 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
610};
611
612static const u32 stoney_golden_common_all[] =
613{
614 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
615 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
616 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
617 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
618 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
619 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
620 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
621 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
622};
623
624static const u32 stoney_mgcg_cgcg_init[] =
625{
626 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
627 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
628 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
629 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
630 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
631 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
632};
633
aaa36a97
AD		 634static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
635static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
636static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
dbff57bc 637static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
2b6cd977 638static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
aaa36a97
AD		 639
640static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
641{
642 switch (adev->asic_type) {
643 case CHIP_TOPAZ:
644 amdgpu_program_register_sequence(adev,
645 iceland_mgcg_cgcg_init,
646 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
647 amdgpu_program_register_sequence(adev,
648 golden_settings_iceland_a11,
649 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
650 amdgpu_program_register_sequence(adev,
651 iceland_golden_common_all,
652 (const u32)ARRAY_SIZE(iceland_golden_common_all));
653 break;
af15a2d5
DZ		 654 case CHIP_FIJI:
655 amdgpu_program_register_sequence(adev,
656 fiji_mgcg_cgcg_init,
657 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
658 amdgpu_program_register_sequence(adev,
659 golden_settings_fiji_a10,
660 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
661 amdgpu_program_register_sequence(adev,
662 fiji_golden_common_all,
663 (const u32)ARRAY_SIZE(fiji_golden_common_all));
664 break;
665
aaa36a97
AD		 666 case CHIP_TONGA:
667 amdgpu_program_register_sequence(adev,
668 tonga_mgcg_cgcg_init,
669 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
670 amdgpu_program_register_sequence(adev,
671 golden_settings_tonga_a11,
672 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
673 amdgpu_program_register_sequence(adev,
674 tonga_golden_common_all,
675 (const u32)ARRAY_SIZE(tonga_golden_common_all));
676 break;
68182d90
FC		 677 case CHIP_BAFFIN:
678 amdgpu_program_register_sequence(adev,
679 golden_settings_baffin_a11,
680 (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
681 amdgpu_program_register_sequence(adev,
682 baffin_golden_common_all,
683 (const u32)ARRAY_SIZE(baffin_golden_common_all));
684 break;
685 case CHIP_ELLESMERE:
686 amdgpu_program_register_sequence(adev,
687 golden_settings_ellesmere_a11,
688 (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
689 amdgpu_program_register_sequence(adev,
690 ellesmere_golden_common_all,
691 (const u32)ARRAY_SIZE(ellesmere_golden_common_all));
692 break;
aaa36a97
AD		 693 case CHIP_CARRIZO:
694 amdgpu_program_register_sequence(adev,
695 cz_mgcg_cgcg_init,
696 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
697 amdgpu_program_register_sequence(adev,
698 cz_golden_settings_a11,
699 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
700 amdgpu_program_register_sequence(adev,
701 cz_golden_common_all,
702 (const u32)ARRAY_SIZE(cz_golden_common_all));
703 break;
e3c7656c
SL		 704 case CHIP_STONEY:
705 amdgpu_program_register_sequence(adev,
706 stoney_mgcg_cgcg_init,
707 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
708 amdgpu_program_register_sequence(adev,
709 stoney_golden_settings_a11,
710 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
711 amdgpu_program_register_sequence(adev,
712 stoney_golden_common_all,
713 (const u32)ARRAY_SIZE(stoney_golden_common_all));
714 break;
aaa36a97
AD		 715 default:
716 break;
717 }
718}
719
720static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
721{
722 int i;
723
724 adev->gfx.scratch.num_reg = 7;
725 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
726 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
727 adev->gfx.scratch.free[i] = true;
728 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
729 }
730}
731
732static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
733{
734 struct amdgpu_device *adev = ring->adev;
735 uint32_t scratch;
736 uint32_t tmp = 0;
737 unsigned i;
738 int r;
739
740 r = amdgpu_gfx_scratch_get(adev, &scratch);
741 if (r) {
742 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
743 return r;
744 }
745 WREG32(scratch, 0xCAFEDEAD);
a27de35c 746 r = amdgpu_ring_alloc(ring, 3);
aaa36a97
AD		 747 if (r) {
748 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
749 ring->idx, r);
750 amdgpu_gfx_scratch_free(adev, scratch);
751 return r;
752 }
753 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
754 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
755 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 756 amdgpu_ring_commit(ring);
aaa36a97
AD		 757
758 for (i = 0; i < adev->usec_timeout; i++) {
759 tmp = RREG32(scratch);
760 if (tmp == 0xDEADBEEF)
761 break;
762 DRM_UDELAY(1);
763 }
764 if (i < adev->usec_timeout) {
765 DRM_INFO("ring test on %d succeeded in %d usecs\n",
766 ring->idx, i);
767 } else {
768 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
769 ring->idx, scratch, tmp);
770 r = -EINVAL;
771 }
772 amdgpu_gfx_scratch_free(adev, scratch);
773 return r;
774}
775
776static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
777{
778 struct amdgpu_device *adev = ring->adev;
779 struct amdgpu_ib ib;
1763552e 780 struct fence *f = NULL;
aaa36a97
AD		 781 uint32_t scratch;
782 uint32_t tmp = 0;
783 unsigned i;
784 int r;
785
786 r = amdgpu_gfx_scratch_get(adev, &scratch);
787 if (r) {
788 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
789 return r;
790 }
791 WREG32(scratch, 0xCAFEDEAD);
b203dd95 792 memset(&ib, 0, sizeof(ib));
b07c60c0 793 r = amdgpu_ib_get(adev, NULL, 256, &ib);
aaa36a97
AD		 794 if (r) {
795 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
42d13693 796 goto err1;
aaa36a97
AD		 797 }
798 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
799 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
800 ib.ptr[2] = 0xDEADBEEF;
801 ib.length_dw = 3;
42d13693 802
336d1f5e 803 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
42d13693
CZ		 804 if (r)
805 goto err2;
806
1763552e 807 r = fence_wait(f, false);
aaa36a97
AD		 808 if (r) {
809 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
42d13693 810 goto err2;
aaa36a97
AD		 811 }
812 for (i = 0; i < adev->usec_timeout; i++) {
813 tmp = RREG32(scratch);
814 if (tmp == 0xDEADBEEF)
815 break;
816 DRM_UDELAY(1);
817 }
818 if (i < adev->usec_timeout) {
819 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
42d13693
CZ		 820 ring->idx, i);
821 goto err2;
aaa36a97
AD		 822 } else {
823 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
824 scratch, tmp);
825 r = -EINVAL;
826 }
42d13693 827err2:
281b4223 828 fence_put(f);
cc55c45d 829 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 830 fence_put(f);
42d13693
CZ		 831err1:
832 amdgpu_gfx_scratch_free(adev, scratch);
aaa36a97
AD		 833 return r;
834}
835
836static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
837{
838 const char *chip_name;
839 char fw_name[30];
840 int err;
841 struct amdgpu_firmware_info *info = NULL;
842 const struct common_firmware_header *header = NULL;
595fd013 843 const struct gfx_firmware_header_v1_0 *cp_hdr;
2b6cd977
EH		 844 const struct rlc_firmware_header_v2_0 *rlc_hdr;
845 unsigned int *tmp = NULL, i;
aaa36a97
AD		 846
847 DRM_DEBUG("\n");
848
849 switch (adev->asic_type) {
850 case CHIP_TOPAZ:
851 chip_name = "topaz";
852 break;
853 case CHIP_TONGA:
854 chip_name = "tonga";
855 break;
856 case CHIP_CARRIZO:
857 chip_name = "carrizo";
858 break;
af15a2d5
DZ		 859 case CHIP_FIJI:
860 chip_name = "fiji";
861 break;
68182d90
FC		 862 case CHIP_BAFFIN:
863 chip_name = "baffin";
864 break;
865 case CHIP_ELLESMERE:
866 chip_name = "ellesmere";
867 break;
e3c7656c
SL		 868 case CHIP_STONEY:
869 chip_name = "stoney";
870 break;
aaa36a97
AD		 871 default:
872 BUG();
873 }
874
c65444fe 875 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
aaa36a97
AD		 876 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
877 if (err)
878 goto out;
879 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
880 if (err)
881 goto out;
595fd013
JZ		 882 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
883 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
884 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 885
c65444fe 886 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
aaa36a97
AD		 887 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
888 if (err)
889 goto out;
890 err = amdgpu_ucode_validate(adev->gfx.me_fw);
891 if (err)
892 goto out;
595fd013
JZ		 893 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
894 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
895 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 896
c65444fe 897 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
aaa36a97
AD		 898 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
899 if (err)
900 goto out;
901 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
902 if (err)
903 goto out;
595fd013
JZ		 904 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
905 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
906 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 907
c65444fe 908 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
aaa36a97
AD		 909 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
910 if (err)
911 goto out;
912 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
2b6cd977
EH		 913 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
914 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
915 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
916
917 adev->gfx.rlc.save_and_restore_offset =
918 le32_to_cpu(rlc_hdr->save_and_restore_offset);
919 adev->gfx.rlc.clear_state_descriptor_offset =
920 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
921 adev->gfx.rlc.avail_scratch_ram_locations =
922 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
923 adev->gfx.rlc.reg_restore_list_size =
924 le32_to_cpu(rlc_hdr->reg_restore_list_size);
925 adev->gfx.rlc.reg_list_format_start =
926 le32_to_cpu(rlc_hdr->reg_list_format_start);
927 adev->gfx.rlc.reg_list_format_separate_start =
928 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
929 adev->gfx.rlc.starting_offsets_start =
930 le32_to_cpu(rlc_hdr->starting_offsets_start);
931 adev->gfx.rlc.reg_list_format_size_bytes =
932 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
933 adev->gfx.rlc.reg_list_size_bytes =
934 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
935
936 adev->gfx.rlc.register_list_format =
937 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
938 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
939
940 if (!adev->gfx.rlc.register_list_format) {
941 err = -ENOMEM;
942 goto out;
943 }
944
945 tmp = (unsigned int *)((uint64_t)rlc_hdr +
946 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
947 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
948 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
949
950 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
951
952 tmp = (unsigned int *)((uint64_t)rlc_hdr +
953 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
954 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
955 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
aaa36a97 956
c65444fe 957 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
aaa36a97
AD		 958 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
959 if (err)
960 goto out;
961 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
962 if (err)
963 goto out;
595fd013
JZ		 964 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
965 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
966 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 967
97dde76a
AD		 968 if ((adev->asic_type != CHIP_STONEY) &&
969 (adev->asic_type != CHIP_TOPAZ)) {
e3c7656c
SL		 970 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
971 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
972 if (!err) {
973 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
974 if (err)
975 goto out;
976 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
977 adev->gfx.mec2_fw->data;
978 adev->gfx.mec2_fw_version =
979 le32_to_cpu(cp_hdr->header.ucode_version);
980 adev->gfx.mec2_feature_version =
981 le32_to_cpu(cp_hdr->ucode_feature_version);
982 } else {
983 err = 0;
984 adev->gfx.mec2_fw = NULL;
985 }
aaa36a97
AD		 986 }
987
988 if (adev->firmware.smu_load) {
989 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
990 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
991 info->fw = adev->gfx.pfp_fw;
992 header = (const struct common_firmware_header *)info->fw->data;
993 adev->firmware.fw_size +=
994 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
995
996 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
997 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
998 info->fw = adev->gfx.me_fw;
999 header = (const struct common_firmware_header *)info->fw->data;
1000 adev->firmware.fw_size +=
1001 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1002
1003 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1004 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1005 info->fw = adev->gfx.ce_fw;
1006 header = (const struct common_firmware_header *)info->fw->data;
1007 adev->firmware.fw_size +=
1008 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1009
1010 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1011 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1012 info->fw = adev->gfx.rlc_fw;
1013 header = (const struct common_firmware_header *)info->fw->data;
1014 adev->firmware.fw_size +=
1015 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1016
1017 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1018 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1019 info->fw = adev->gfx.mec_fw;
1020 header = (const struct common_firmware_header *)info->fw->data;
1021 adev->firmware.fw_size +=
1022 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1023
1024 if (adev->gfx.mec2_fw) {
1025 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1026 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1027 info->fw = adev->gfx.mec2_fw;
1028 header = (const struct common_firmware_header *)info->fw->data;
1029 adev->firmware.fw_size +=
1030 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1031 }
1032
1033 }
1034
1035out:
1036 if (err) {
1037 dev_err(adev->dev,
1038 "gfx8: Failed to load firmware \"%s\"\n",
1039 fw_name);
1040 release_firmware(adev->gfx.pfp_fw);
1041 adev->gfx.pfp_fw = NULL;
1042 release_firmware(adev->gfx.me_fw);
1043 adev->gfx.me_fw = NULL;
1044 release_firmware(adev->gfx.ce_fw);
1045 adev->gfx.ce_fw = NULL;
1046 release_firmware(adev->gfx.rlc_fw);
1047 adev->gfx.rlc_fw = NULL;
1048 release_firmware(adev->gfx.mec_fw);
1049 adev->gfx.mec_fw = NULL;
1050 release_firmware(adev->gfx.mec2_fw);
1051 adev->gfx.mec2_fw = NULL;
1052 }
1053 return err;
1054}
1055
2b6cd977
EH		 1056static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1057 volatile u32 *buffer)
1058{
1059 u32 count = 0, i;
1060 const struct cs_section_def *sect = NULL;
1061 const struct cs_extent_def *ext = NULL;
1062
1063 if (adev->gfx.rlc.cs_data == NULL)
1064 return;
1065 if (buffer == NULL)
1066 return;
1067
1068 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1069 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1070
1071 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1072 buffer[count++] = cpu_to_le32(0x80000000);
1073 buffer[count++] = cpu_to_le32(0x80000000);
1074
1075 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1076 for (ext = sect->section; ext->extent != NULL; ++ext) {
1077 if (sect->id == SECT_CONTEXT) {
1078 buffer[count++] =
1079 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1080 buffer[count++] = cpu_to_le32(ext->reg_index -
1081 PACKET3_SET_CONTEXT_REG_START);
1082 for (i = 0; i < ext->reg_count; i++)
1083 buffer[count++] = cpu_to_le32(ext->extent[i]);
1084 } else {
1085 return;
1086 }
1087 }
1088 }
1089
1090 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1091 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1092 PACKET3_SET_CONTEXT_REG_START);
1093 switch (adev->asic_type) {
1094 case CHIP_TONGA:
f4bfffdd 1095 case CHIP_ELLESMERE:
2b6cd977
EH		 1096 buffer[count++] = cpu_to_le32(0x16000012);
1097 buffer[count++] = cpu_to_le32(0x0000002A);
1098 break;
f4bfffdd
EH		 1099 case CHIP_BAFFIN:
1100 buffer[count++] = cpu_to_le32(0x16000012);
1101 buffer[count++] = cpu_to_le32(0x00000000);
1102 break;
2b6cd977
EH		 1103 case CHIP_FIJI:
1104 buffer[count++] = cpu_to_le32(0x3a00161a);
1105 buffer[count++] = cpu_to_le32(0x0000002e);
1106 break;
1107 case CHIP_TOPAZ:
1108 case CHIP_CARRIZO:
1109 buffer[count++] = cpu_to_le32(0x00000002);
1110 buffer[count++] = cpu_to_le32(0x00000000);
1111 break;
1112 case CHIP_STONEY:
1113 buffer[count++] = cpu_to_le32(0x00000000);
1114 buffer[count++] = cpu_to_le32(0x00000000);
1115 break;
1116 default:
1117 buffer[count++] = cpu_to_le32(0x00000000);
1118 buffer[count++] = cpu_to_le32(0x00000000);
1119 break;
1120 }
1121
1122 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1123 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1124
1125 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1126 buffer[count++] = cpu_to_le32(0);
1127}
1128
1129static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
1130{
1131 int r;
1132
1133 /* clear state block */
1134 if (adev->gfx.rlc.clear_state_obj) {
1135 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1136 if (unlikely(r != 0))
1137 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
1138 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1139 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1140
1141 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
1142 adev->gfx.rlc.clear_state_obj = NULL;
1143 }
1144}
1145
1146static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1147{
1148 volatile u32 *dst_ptr;
1149 u32 dws;
1150 const struct cs_section_def *cs_data;
1151 int r;
1152
1153 adev->gfx.rlc.cs_data = vi_cs_data;
1154
1155 cs_data = adev->gfx.rlc.cs_data;
1156
1157 if (cs_data) {
1158 /* clear state block */
1159 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev);
1160
1161 if (adev->gfx.rlc.clear_state_obj == NULL) {
1162 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
1163 AMDGPU_GEM_DOMAIN_VRAM,
1164 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1165 NULL, NULL,
1166 &adev->gfx.rlc.clear_state_obj);
1167 if (r) {
1168 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
1169 gfx_v8_0_rlc_fini(adev);
1170 return r;
1171 }
1172 }
1173 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1174 if (unlikely(r != 0)) {
1175 gfx_v8_0_rlc_fini(adev);
1176 return r;
1177 }
1178 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
1179 &adev->gfx.rlc.clear_state_gpu_addr);
1180 if (r) {
1181 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1182 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
1183 gfx_v8_0_rlc_fini(adev);
1184 return r;
1185 }
1186
1187 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
1188 if (r) {
1189 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
1190 gfx_v8_0_rlc_fini(adev);
1191 return r;
1192 }
1193 /* set up the cs buffer */
1194 dst_ptr = adev->gfx.rlc.cs_ptr;
1195 gfx_v8_0_get_csb_buffer(adev, dst_ptr);
1196 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1197 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1198 }
1199
1200 return 0;
1201}
1202
aaa36a97
AD		 1203static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1204{
1205 int r;
1206
1207 if (adev->gfx.mec.hpd_eop_obj) {
1208 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
1209 if (unlikely(r != 0))
1210 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
1211 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
1212 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1213
1214 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
1215 adev->gfx.mec.hpd_eop_obj = NULL;
1216 }
1217}
1218
1219#define MEC_HPD_SIZE 2048
1220
1221static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1222{
1223 int r;
1224 u32 *hpd;
1225
1226 /*
1227 * we assign only 1 pipe because all other pipes will
1228 * be handled by KFD
1229 */
1230 adev->gfx.mec.num_mec = 1;
1231 adev->gfx.mec.num_pipe = 1;
1232 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
1233
1234 if (adev->gfx.mec.hpd_eop_obj == NULL) {
1235 r = amdgpu_bo_create(adev,
1236 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
1237 PAGE_SIZE, true,
72d7668b 1238 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
aaa36a97
AD		 1239 &adev->gfx.mec.hpd_eop_obj);
1240 if (r) {
1241 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1242 return r;
1243 }
1244 }
1245
1246 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
1247 if (unlikely(r != 0)) {
1248 gfx_v8_0_mec_fini(adev);
1249 return r;
1250 }
1251 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
1252 &adev->gfx.mec.hpd_eop_gpu_addr);
1253 if (r) {
1254 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
1255 gfx_v8_0_mec_fini(adev);
1256 return r;
1257 }
1258 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
1259 if (r) {
1260 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
1261 gfx_v8_0_mec_fini(adev);
1262 return r;
1263 }
1264
1265 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
1266
1267 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1268 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1269
1270 return 0;
1271}
1272
ccba7691
AD		 1273static const u32 vgpr_init_compute_shader[] =
1274{
1275 0x7e000209, 0x7e020208,
1276 0x7e040207, 0x7e060206,
1277 0x7e080205, 0x7e0a0204,
1278 0x7e0c0203, 0x7e0e0202,
1279 0x7e100201, 0x7e120200,
1280 0x7e140209, 0x7e160208,
1281 0x7e180207, 0x7e1a0206,
1282 0x7e1c0205, 0x7e1e0204,
1283 0x7e200203, 0x7e220202,
1284 0x7e240201, 0x7e260200,
1285 0x7e280209, 0x7e2a0208,
1286 0x7e2c0207, 0x7e2e0206,
1287 0x7e300205, 0x7e320204,
1288 0x7e340203, 0x7e360202,
1289 0x7e380201, 0x7e3a0200,
1290 0x7e3c0209, 0x7e3e0208,
1291 0x7e400207, 0x7e420206,
1292 0x7e440205, 0x7e460204,
1293 0x7e480203, 0x7e4a0202,
1294 0x7e4c0201, 0x7e4e0200,
1295 0x7e500209, 0x7e520208,
1296 0x7e540207, 0x7e560206,
1297 0x7e580205, 0x7e5a0204,
1298 0x7e5c0203, 0x7e5e0202,
1299 0x7e600201, 0x7e620200,
1300 0x7e640209, 0x7e660208,
1301 0x7e680207, 0x7e6a0206,
1302 0x7e6c0205, 0x7e6e0204,
1303 0x7e700203, 0x7e720202,
1304 0x7e740201, 0x7e760200,
1305 0x7e780209, 0x7e7a0208,
1306 0x7e7c0207, 0x7e7e0206,
1307 0xbf8a0000, 0xbf810000,
1308};
1309
1310static const u32 sgpr_init_compute_shader[] =
1311{
1312 0xbe8a0100, 0xbe8c0102,
1313 0xbe8e0104, 0xbe900106,
1314 0xbe920108, 0xbe940100,
1315 0xbe960102, 0xbe980104,
1316 0xbe9a0106, 0xbe9c0108,
1317 0xbe9e0100, 0xbea00102,
1318 0xbea20104, 0xbea40106,
1319 0xbea60108, 0xbea80100,
1320 0xbeaa0102, 0xbeac0104,
1321 0xbeae0106, 0xbeb00108,
1322 0xbeb20100, 0xbeb40102,
1323 0xbeb60104, 0xbeb80106,
1324 0xbeba0108, 0xbebc0100,
1325 0xbebe0102, 0xbec00104,
1326 0xbec20106, 0xbec40108,
1327 0xbec60100, 0xbec80102,
1328 0xbee60004, 0xbee70005,
1329 0xbeea0006, 0xbeeb0007,
1330 0xbee80008, 0xbee90009,
1331 0xbefc0000, 0xbf8a0000,
1332 0xbf810000, 0x00000000,
1333};
1334
1335static const u32 vgpr_init_regs[] =
1336{
1337 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1338 mmCOMPUTE_RESOURCE_LIMITS, 0,
1339 mmCOMPUTE_NUM_THREAD_X, 256*4,
1340 mmCOMPUTE_NUM_THREAD_Y, 1,
1341 mmCOMPUTE_NUM_THREAD_Z, 1,
1342 mmCOMPUTE_PGM_RSRC2, 20,
1343 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1344 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1345 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1346 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1347 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1348 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1349 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1350 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1351 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1352 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1353};
1354
1355static const u32 sgpr1_init_regs[] =
1356{
1357 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1358 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1359 mmCOMPUTE_NUM_THREAD_X, 256*5,
1360 mmCOMPUTE_NUM_THREAD_Y, 1,
1361 mmCOMPUTE_NUM_THREAD_Z, 1,
1362 mmCOMPUTE_PGM_RSRC2, 20,
1363 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1364 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1365 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1366 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1367 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1368 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1369 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1370 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1371 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1372 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1373};
1374
1375static const u32 sgpr2_init_regs[] =
1376{
1377 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1378 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1379 mmCOMPUTE_NUM_THREAD_X, 256*5,
1380 mmCOMPUTE_NUM_THREAD_Y, 1,
1381 mmCOMPUTE_NUM_THREAD_Z, 1,
1382 mmCOMPUTE_PGM_RSRC2, 20,
1383 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1384 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1385 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1386 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1387 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1388 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1389 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1390 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1391 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1392 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1393};
1394
1395static const u32 sec_ded_counter_registers[] =
1396{
1397 mmCPC_EDC_ATC_CNT,
1398 mmCPC_EDC_SCRATCH_CNT,
1399 mmCPC_EDC_UCODE_CNT,
1400 mmCPF_EDC_ATC_CNT,
1401 mmCPF_EDC_ROQ_CNT,
1402 mmCPF_EDC_TAG_CNT,
1403 mmCPG_EDC_ATC_CNT,
1404 mmCPG_EDC_DMA_CNT,
1405 mmCPG_EDC_TAG_CNT,
1406 mmDC_EDC_CSINVOC_CNT,
1407 mmDC_EDC_RESTORE_CNT,
1408 mmDC_EDC_STATE_CNT,
1409 mmGDS_EDC_CNT,
1410 mmGDS_EDC_GRBM_CNT,
1411 mmGDS_EDC_OA_DED,
1412 mmSPI_EDC_CNT,
1413 mmSQC_ATC_EDC_GATCL1_CNT,
1414 mmSQC_EDC_CNT,
1415 mmSQ_EDC_DED_CNT,
1416 mmSQ_EDC_INFO,
1417 mmSQ_EDC_SEC_CNT,
1418 mmTCC_EDC_CNT,
1419 mmTCP_ATC_EDC_GATCL1_CNT,
1420 mmTCP_EDC_CNT,
1421 mmTD_EDC_CNT
1422};
1423
1424static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1425{
1426 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1427 struct amdgpu_ib ib;
1428 struct fence *f = NULL;
1429 int r, i;
1430 u32 tmp;
1431 unsigned total_size, vgpr_offset, sgpr_offset;
1432 u64 gpu_addr;
1433
1434 /* only supported on CZ */
1435 if (adev->asic_type != CHIP_CARRIZO)
1436 return 0;
1437
1438 /* bail if the compute ring is not ready */
1439 if (!ring->ready)
1440 return 0;
1441
1442 tmp = RREG32(mmGB_EDC_MODE);
1443 WREG32(mmGB_EDC_MODE, 0);
1444
1445 total_size =
1446 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1447 total_size +=
1448 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1449 total_size +=
1450 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1451 total_size = ALIGN(total_size, 256);
1452 vgpr_offset = total_size;
1453 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1454 sgpr_offset = total_size;
1455 total_size += sizeof(sgpr_init_compute_shader);
1456
1457 /* allocate an indirect buffer to put the commands in */
1458 memset(&ib, 0, sizeof(ib));
b07c60c0 1459 r = amdgpu_ib_get(adev, NULL, total_size, &ib);
ccba7691
AD		 1460 if (r) {
1461 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1462 return r;
1463 }
1464
1465 /* load the compute shaders */
1466 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1467 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1468
1469 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1470 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1471
1472 /* init the ib length to 0 */
1473 ib.length_dw = 0;
1474
1475 /* VGPR */
1476 /* write the register state for the compute dispatch */
1477 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1478 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1479 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1480 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1481 }
1482 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1483 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1484 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1485 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1486 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1487 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1488
1489 /* write dispatch packet */
1490 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1491 ib.ptr[ib.length_dw++] = 8; /* x */
1492 ib.ptr[ib.length_dw++] = 1; /* y */
1493 ib.ptr[ib.length_dw++] = 1; /* z */
1494 ib.ptr[ib.length_dw++] =
1495 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1496
1497 /* write CS partial flush packet */
1498 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1499 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1500
1501 /* SGPR1 */
1502 /* write the register state for the compute dispatch */
1503 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1504 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1505 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1506 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1507 }
1508 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1509 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1510 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1511 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1512 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1513 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1514
1515 /* write dispatch packet */
1516 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1517 ib.ptr[ib.length_dw++] = 8; /* x */
1518 ib.ptr[ib.length_dw++] = 1; /* y */
1519 ib.ptr[ib.length_dw++] = 1; /* z */
1520 ib.ptr[ib.length_dw++] =
1521 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1522
1523 /* write CS partial flush packet */
1524 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1525 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1526
1527 /* SGPR2 */
1528 /* write the register state for the compute dispatch */
1529 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1530 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1531 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1532 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1533 }
1534 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1535 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1536 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1537 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1538 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1539 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1540
1541 /* write dispatch packet */
1542 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1543 ib.ptr[ib.length_dw++] = 8; /* x */
1544 ib.ptr[ib.length_dw++] = 1; /* y */
1545 ib.ptr[ib.length_dw++] = 1; /* z */
1546 ib.ptr[ib.length_dw++] =
1547 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1548
1549 /* write CS partial flush packet */
1550 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1551 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1552
1553 /* shedule the ib on the ring */
336d1f5e 1554 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
ccba7691
AD		 1555 if (r) {
1556 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1557 goto fail;
1558 }
1559
1560 /* wait for the GPU to finish processing the IB */
1561 r = fence_wait(f, false);
1562 if (r) {
1563 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1564 goto fail;
1565 }
1566
1567 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1568 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1569 WREG32(mmGB_EDC_MODE, tmp);
1570
1571 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1572 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1573 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1574
1575
1576 /* read back registers to clear the counters */
1577 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1578 RREG32(sec_ded_counter_registers[i]);
1579
1580fail:
1581 fence_put(f);
cc55c45d 1582 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 1583 fence_put(f);
ccba7691
AD		 1584
1585 return r;
1586}
1587
68182d90 1588static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
0bde3a95
AD		 1589{
1590 u32 gb_addr_config;
1591 u32 mc_shared_chmap, mc_arb_ramcfg;
1592 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1593 u32 tmp;
68182d90 1594 int ret;
0bde3a95
AD		 1595
1596 switch (adev->asic_type) {
1597 case CHIP_TOPAZ:
1598 adev->gfx.config.max_shader_engines = 1;
1599 adev->gfx.config.max_tile_pipes = 2;
1600 adev->gfx.config.max_cu_per_sh = 6;
1601 adev->gfx.config.max_sh_per_se = 1;
1602 adev->gfx.config.max_backends_per_se = 2;
1603 adev->gfx.config.max_texture_channel_caches = 2;
1604 adev->gfx.config.max_gprs = 256;
1605 adev->gfx.config.max_gs_threads = 32;
1606 adev->gfx.config.max_hw_contexts = 8;
1607
1608 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1609 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1610 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1611 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1612 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1613 break;
1614 case CHIP_FIJI:
1615 adev->gfx.config.max_shader_engines = 4;
1616 adev->gfx.config.max_tile_pipes = 16;
1617 adev->gfx.config.max_cu_per_sh = 16;
1618 adev->gfx.config.max_sh_per_se = 1;
1619 adev->gfx.config.max_backends_per_se = 4;
5f2e816b 1620 adev->gfx.config.max_texture_channel_caches = 16;
0bde3a95
AD		 1621 adev->gfx.config.max_gprs = 256;
1622 adev->gfx.config.max_gs_threads = 32;
1623 adev->gfx.config.max_hw_contexts = 8;
1624
68182d90
FC		 1625 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1626 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1627 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1628 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1629 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1630 break;
1631 case CHIP_BAFFIN:
1632 ret = amdgpu_atombios_get_gfx_info(adev);
1633 if (ret)
1634 return ret;
1635 adev->gfx.config.max_gprs = 256;
1636 adev->gfx.config.max_gs_threads = 32;
1637 adev->gfx.config.max_hw_contexts = 8;
1638
1639 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1640 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1641 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1642 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1643 gb_addr_config = BAFFIN_GB_ADDR_CONFIG_GOLDEN;
1644 break;
1645 case CHIP_ELLESMERE:
1646 ret = amdgpu_atombios_get_gfx_info(adev);
1647 if (ret)
1648 return ret;
1649 adev->gfx.config.max_gprs = 256;
1650 adev->gfx.config.max_gs_threads = 32;
1651 adev->gfx.config.max_hw_contexts = 8;
1652
0bde3a95
AD		 1653 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1654 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1655 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1656 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1657 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1658 break;
1659 case CHIP_TONGA:
1660 adev->gfx.config.max_shader_engines = 4;
1661 adev->gfx.config.max_tile_pipes = 8;
1662 adev->gfx.config.max_cu_per_sh = 8;
1663 adev->gfx.config.max_sh_per_se = 1;
1664 adev->gfx.config.max_backends_per_se = 2;
1665 adev->gfx.config.max_texture_channel_caches = 8;
1666 adev->gfx.config.max_gprs = 256;
1667 adev->gfx.config.max_gs_threads = 32;
1668 adev->gfx.config.max_hw_contexts = 8;
1669
1670 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1671 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1672 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1673 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1674 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1675 break;
1676 case CHIP_CARRIZO:
1677 adev->gfx.config.max_shader_engines = 1;
1678 adev->gfx.config.max_tile_pipes = 2;
1679 adev->gfx.config.max_sh_per_se = 1;
1680 adev->gfx.config.max_backends_per_se = 2;
1681
1682 switch (adev->pdev->revision) {
1683 case 0xc4:
1684 case 0x84:
1685 case 0xc8:
1686 case 0xcc:
b8b339ea
AD		 1687 case 0xe1:
1688 case 0xe3:
0bde3a95
AD		 1689 /* B10 */
1690 adev->gfx.config.max_cu_per_sh = 8;
1691 break;
1692 case 0xc5:
1693 case 0x81:
1694 case 0x85:
1695 case 0xc9:
1696 case 0xcd:
b8b339ea
AD		 1697 case 0xe2:
1698 case 0xe4:
0bde3a95
AD		 1699 /* B8 */
1700 adev->gfx.config.max_cu_per_sh = 6;
1701 break;
1702 case 0xc6:
1703 case 0xca:
1704 case 0xce:
b8b339ea 1705 case 0x88:
0bde3a95
AD		 1706 /* B6 */
1707 adev->gfx.config.max_cu_per_sh = 6;
1708 break;
1709 case 0xc7:
1710 case 0x87:
1711 case 0xcb:
b8b339ea
AD		 1712 case 0xe5:
1713 case 0x89:
0bde3a95
AD		 1714 default:
1715 /* B4 */
1716 adev->gfx.config.max_cu_per_sh = 4;
1717 break;
1718 }
1719
1720 adev->gfx.config.max_texture_channel_caches = 2;
1721 adev->gfx.config.max_gprs = 256;
1722 adev->gfx.config.max_gs_threads = 32;
1723 adev->gfx.config.max_hw_contexts = 8;
1724
e3c7656c
SL		 1725 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1726 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1727 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1728 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1729 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1730 break;
1731 case CHIP_STONEY:
1732 adev->gfx.config.max_shader_engines = 1;
1733 adev->gfx.config.max_tile_pipes = 2;
1734 adev->gfx.config.max_sh_per_se = 1;
1735 adev->gfx.config.max_backends_per_se = 1;
1736
1737 switch (adev->pdev->revision) {
1738 case 0xc0:
1739 case 0xc1:
1740 case 0xc2:
1741 case 0xc4:
1742 case 0xc8:
1743 case 0xc9:
1744 adev->gfx.config.max_cu_per_sh = 3;
1745 break;
1746 case 0xd0:
1747 case 0xd1:
1748 case 0xd2:
1749 default:
1750 adev->gfx.config.max_cu_per_sh = 2;
1751 break;
1752 }
1753
1754 adev->gfx.config.max_texture_channel_caches = 2;
1755 adev->gfx.config.max_gprs = 256;
1756 adev->gfx.config.max_gs_threads = 16;
1757 adev->gfx.config.max_hw_contexts = 8;
1758
0bde3a95
AD		 1759 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1760 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1761 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1762 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1763 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1764 break;
1765 default:
1766 adev->gfx.config.max_shader_engines = 2;
1767 adev->gfx.config.max_tile_pipes = 4;
1768 adev->gfx.config.max_cu_per_sh = 2;
1769 adev->gfx.config.max_sh_per_se = 1;
1770 adev->gfx.config.max_backends_per_se = 2;
1771 adev->gfx.config.max_texture_channel_caches = 4;
1772 adev->gfx.config.max_gprs = 256;
1773 adev->gfx.config.max_gs_threads = 32;
1774 adev->gfx.config.max_hw_contexts = 8;
1775
1776 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1777 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1778 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1779 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1780 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1781 break;
1782 }
1783
1784 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1785 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1786 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1787
1788 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1789 adev->gfx.config.mem_max_burst_length_bytes = 256;
1790 if (adev->flags & AMD_IS_APU) {
1791 /* Get memory bank mapping mode. */
1792 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1793 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1794 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1795
1796 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1797 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1798 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1799
1800 /* Validate settings in case only one DIMM installed. */
1801 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1802 dimm00_addr_map = 0;
1803 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1804 dimm01_addr_map = 0;
1805 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1806 dimm10_addr_map = 0;
1807 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1808 dimm11_addr_map = 0;
1809
1810 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1811 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1812 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1813 adev->gfx.config.mem_row_size_in_kb = 2;
1814 else
1815 adev->gfx.config.mem_row_size_in_kb = 1;
1816 } else {
1817 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1818 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1819 if (adev->gfx.config.mem_row_size_in_kb > 4)
1820 adev->gfx.config.mem_row_size_in_kb = 4;
1821 }
1822
1823 adev->gfx.config.shader_engine_tile_size = 32;
1824 adev->gfx.config.num_gpus = 1;
1825 adev->gfx.config.multi_gpu_tile_size = 64;
1826
1827 /* fix up row size */
1828 switch (adev->gfx.config.mem_row_size_in_kb) {
1829 case 1:
1830 default:
1831 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1832 break;
1833 case 2:
1834 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1835 break;
1836 case 4:
1837 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1838 break;
1839 }
1840 adev->gfx.config.gb_addr_config = gb_addr_config;
68182d90
FC		 1841
1842 return 0;
0bde3a95
AD		 1843}
1844
5fc3aeeb 1845static int gfx_v8_0_sw_init(void *handle)
aaa36a97
AD		 1846{
1847 int i, r;
1848 struct amdgpu_ring *ring;
5fc3aeeb 1849 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1850
1851 /* EOP Event */
1852 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
1853 if (r)
1854 return r;
1855
1856 /* Privileged reg */
1857 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
1858 if (r)
1859 return r;
1860
1861 /* Privileged inst */
1862 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
1863 if (r)
1864 return r;
1865
1866 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1867
1868 gfx_v8_0_scratch_init(adev);
1869
1870 r = gfx_v8_0_init_microcode(adev);
1871 if (r) {
1872 DRM_ERROR("Failed to load gfx firmware!\n");
1873 return r;
1874 }
1875
2b6cd977
EH		 1876 r = gfx_v8_0_rlc_init(adev);
1877 if (r) {
1878 DRM_ERROR("Failed to init rlc BOs!\n");
1879 return r;
1880 }
1881
aaa36a97
AD		 1882 r = gfx_v8_0_mec_init(adev);
1883 if (r) {
1884 DRM_ERROR("Failed to init MEC BOs!\n");
1885 return r;
1886 }
1887
aaa36a97
AD		 1888 /* set up the gfx ring */
1889 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1890 ring = &adev->gfx.gfx_ring[i];
1891 ring->ring_obj = NULL;
1892 sprintf(ring->name, "gfx");
1893 /* no gfx doorbells on iceland */
1894 if (adev->asic_type != CHIP_TOPAZ) {
1895 ring->use_doorbell = true;
1896 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
1897 }
1898
2800de2e 1899 r = amdgpu_ring_init(adev, ring, 1024,
aaa36a97
AD		 1900 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1901 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
1902 AMDGPU_RING_TYPE_GFX);
1903 if (r)
1904 return r;
1905 }
1906
1907 /* set up the compute queues */
1908 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1909 unsigned irq_type;
1910
1911 /* max 32 queues per MEC */
1912 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1913 DRM_ERROR("Too many (%d) compute rings!\n", i);
1914 break;
1915 }
1916 ring = &adev->gfx.compute_ring[i];
1917 ring->ring_obj = NULL;
1918 ring->use_doorbell = true;
1919 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
1920 ring->me = 1; /* first MEC */
1921 ring->pipe = i / 8;
1922 ring->queue = i % 8;
771c8ec1 1923 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
aaa36a97
AD		 1924 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1925 /* type-2 packets are deprecated on MEC, use type-3 instead */
2800de2e 1926 r = amdgpu_ring_init(adev, ring, 1024,
aaa36a97
AD		 1927 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1928 &adev->gfx.eop_irq, irq_type,
1929 AMDGPU_RING_TYPE_COMPUTE);
1930 if (r)
1931 return r;
1932 }
1933
1934 /* reserve GDS, GWS and OA resource for gfx */
1935 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
1936 PAGE_SIZE, true,
72d7668b 1937 AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
aaa36a97
AD		 1938 NULL, &adev->gds.gds_gfx_bo);
1939 if (r)
1940 return r;
1941
1942 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1943 PAGE_SIZE, true,
72d7668b 1944 AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
aaa36a97
AD		 1945 NULL, &adev->gds.gws_gfx_bo);
1946 if (r)
1947 return r;
1948
1949 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1950 PAGE_SIZE, true,
72d7668b 1951 AMDGPU_GEM_DOMAIN_OA, 0, NULL,
aaa36a97
AD		 1952 NULL, &adev->gds.oa_gfx_bo);
1953 if (r)
1954 return r;
1955
a101a899
KW		 1956 adev->gfx.ce_ram_size = 0x8000;
1957
68182d90
FC		 1958 r = gfx_v8_0_gpu_early_init(adev);
1959 if (r)
1960 return r;
0bde3a95 1961
aaa36a97
AD		 1962 return 0;
1963}
1964
5fc3aeeb 1965static int gfx_v8_0_sw_fini(void *handle)
aaa36a97
AD		 1966{
1967 int i;
5fc3aeeb 1968 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1969
1970 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1971 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1972 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1973
1974 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1975 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1976 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1977 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1978
aaa36a97
AD		 1979 gfx_v8_0_mec_fini(adev);
1980
2b6cd977
EH		 1981 gfx_v8_0_rlc_fini(adev);
1982
1983 kfree(adev->gfx.rlc.register_list_format);
1984
aaa36a97
AD		 1985 return 0;
1986}
1987
1988static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1989{
90bea0ab 1990 uint32_t *modearray, *mod2array;
eb64526f
TSD		 1991 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1992 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
90bea0ab 1993 u32 reg_offset;
aaa36a97 1994
90bea0ab
TSD		 1995 modearray = adev->gfx.config.tile_mode_array;
1996 mod2array = adev->gfx.config.macrotile_mode_array;
1997
1998 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1999 modearray[reg_offset] = 0;
2000
2001 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2002 mod2array[reg_offset] = 0;
aaa36a97
AD		 2003
2004 switch (adev->asic_type) {
2005 case CHIP_TOPAZ:
90bea0ab
TSD		 2006 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2007 PIPE_CONFIG(ADDR_SURF_P2) |
2008 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2009 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2010 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2011 PIPE_CONFIG(ADDR_SURF_P2) |
2012 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2013 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2014 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2015 PIPE_CONFIG(ADDR_SURF_P2) |
2016 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2017 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2018 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2019 PIPE_CONFIG(ADDR_SURF_P2) |
2020 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2021 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2022 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2023 PIPE_CONFIG(ADDR_SURF_P2) |
2024 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2025 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2026 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2027 PIPE_CONFIG(ADDR_SURF_P2) |
2028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2029 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2030 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2031 PIPE_CONFIG(ADDR_SURF_P2) |
2032 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2033 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2034 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2035 PIPE_CONFIG(ADDR_SURF_P2));
2036 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2037 PIPE_CONFIG(ADDR_SURF_P2) |
2038 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2039 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2040 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2041 PIPE_CONFIG(ADDR_SURF_P2) |
2042 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2043 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2044 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2045 PIPE_CONFIG(ADDR_SURF_P2) |
2046 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2047 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2048 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2049 PIPE_CONFIG(ADDR_SURF_P2) |
2050 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2051 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2052 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2053 PIPE_CONFIG(ADDR_SURF_P2) |
2054 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2055 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2056 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2057 PIPE_CONFIG(ADDR_SURF_P2) |
2058 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2059 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2060 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2061 PIPE_CONFIG(ADDR_SURF_P2) |
2062 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2063 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2064 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2065 PIPE_CONFIG(ADDR_SURF_P2) |
2066 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2067 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2068 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2069 PIPE_CONFIG(ADDR_SURF_P2) |
2070 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2071 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2072 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2073 PIPE_CONFIG(ADDR_SURF_P2) |
2074 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2075 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2076 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2077 PIPE_CONFIG(ADDR_SURF_P2) |
2078 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2079 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2080 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2081 PIPE_CONFIG(ADDR_SURF_P2) |
2082 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2083 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2084 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2085 PIPE_CONFIG(ADDR_SURF_P2) |
2086 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2087 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2088 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2089 PIPE_CONFIG(ADDR_SURF_P2) |
2090 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2091 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2092 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2093 PIPE_CONFIG(ADDR_SURF_P2) |
2094 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2095 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2096 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2097 PIPE_CONFIG(ADDR_SURF_P2) |
2098 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2099 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2100 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2101 PIPE_CONFIG(ADDR_SURF_P2) |
2102 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2103 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2104 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2105 PIPE_CONFIG(ADDR_SURF_P2) |
2106 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2107 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2108
2109 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2110 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2111 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2112 NUM_BANKS(ADDR_SURF_8_BANK));
2113 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2114 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2115 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2116 NUM_BANKS(ADDR_SURF_8_BANK));
2117 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2118 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2119 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2120 NUM_BANKS(ADDR_SURF_8_BANK));
2121 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2122 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2123 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2124 NUM_BANKS(ADDR_SURF_8_BANK));
2125 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2128 NUM_BANKS(ADDR_SURF_8_BANK));
2129 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2130 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2131 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2132 NUM_BANKS(ADDR_SURF_8_BANK));
2133 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2134 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2135 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2136 NUM_BANKS(ADDR_SURF_8_BANK));
2137 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2138 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2140 NUM_BANKS(ADDR_SURF_16_BANK));
2141 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2142 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2143 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2144 NUM_BANKS(ADDR_SURF_16_BANK));
2145 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2146 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2147 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2148 NUM_BANKS(ADDR_SURF_16_BANK));
2149 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2150 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2151 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2152 NUM_BANKS(ADDR_SURF_16_BANK));
2153 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2154 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2155 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2156 NUM_BANKS(ADDR_SURF_16_BANK));
2157 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2158 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2160 NUM_BANKS(ADDR_SURF_16_BANK));
2161 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2164 NUM_BANKS(ADDR_SURF_8_BANK));
2165
2166 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2167 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2168 reg_offset != 23)
2169 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2170
2171 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2172 if (reg_offset != 7)
2173 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2174
8cdacf44 2175 break;
af15a2d5 2176 case CHIP_FIJI:
90bea0ab
TSD		 2177 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2178 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2179 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2180 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2181 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2182 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2183 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2184 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2185 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2186 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2187 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2188 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2189 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2190 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2191 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2192 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2193 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2194 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2195 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2196 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2197 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2198 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2199 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2200 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2201 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2202 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2203 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2204 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2205 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2206 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2207 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2208 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2209 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2210 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2211 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2212 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2213 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2214 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2215 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2216 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2217 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2218 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2219 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2220 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2221 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2222 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2223 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2224 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2225 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2226 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2227 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2228 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2229 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2230 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2231 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2232 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2233 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2234 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2235 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2236 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2237 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2238 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2239 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2240 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2241 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2242 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2243 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2244 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2245 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2246 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2247 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2248 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2249 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2250 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2251 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2252 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2253 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2254 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2255 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2256 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2257 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2258 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2259 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2260 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2261 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2262 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2263 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2264 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2265 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2266 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2267 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2268 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2269 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2270 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2271 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2272 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2273 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2274 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2275 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2276 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2277 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2278 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2279 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2281 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2283 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2284 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2285 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2287 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2289 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2291 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2292 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2293 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2294 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2295 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2296 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2297 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2299
2300 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2301 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2302 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2303 NUM_BANKS(ADDR_SURF_8_BANK));
2304 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2305 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2306 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2307 NUM_BANKS(ADDR_SURF_8_BANK));
2308 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2309 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2310 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2311 NUM_BANKS(ADDR_SURF_8_BANK));
2312 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2313 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2314 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2315 NUM_BANKS(ADDR_SURF_8_BANK));
2316 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2317 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2318 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2319 NUM_BANKS(ADDR_SURF_8_BANK));
2320 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2321 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2322 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2323 NUM_BANKS(ADDR_SURF_8_BANK));
2324 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2325 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2326 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2327 NUM_BANKS(ADDR_SURF_8_BANK));
2328 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2329 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2330 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2331 NUM_BANKS(ADDR_SURF_8_BANK));
2332 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2333 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2334 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2335 NUM_BANKS(ADDR_SURF_8_BANK));
2336 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2337 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2338 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2339 NUM_BANKS(ADDR_SURF_8_BANK));
2340 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2341 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2342 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2343 NUM_BANKS(ADDR_SURF_8_BANK));
2344 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2345 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2346 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2347 NUM_BANKS(ADDR_SURF_8_BANK));
2348 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2349 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2350 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2351 NUM_BANKS(ADDR_SURF_8_BANK));
2352 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2353 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2354 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2355 NUM_BANKS(ADDR_SURF_4_BANK));
2356
2357 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2358 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2359
2360 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2361 if (reg_offset != 7)
2362 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2363
5f2e816b 2364 break;
aaa36a97 2365 case CHIP_TONGA:
90bea0ab
TSD		 2366 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2367 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2368 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2369 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2370 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2371 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2372 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2373 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2374 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2375 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2376 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2377 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2378 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2379 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2380 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2381 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2382 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2383 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2384 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2385 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2386 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2387 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2388 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2389 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2390 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2391 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2392 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2393 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2394 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2395 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2396 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2397 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2398 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2399 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2400 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2401 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2402 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2404 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2405 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2406 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2407 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2408 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2409 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2410 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2411 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2412 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2413 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2414 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2416 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2417 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2418 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2420 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2421 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2422 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2423 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2424 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2425 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2426 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2428 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2429 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2430 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2431 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2432 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2433 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2434 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2435 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2436 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2437 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2438 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2439 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2440 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2441 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2442 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2443 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2444 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2445 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2446 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2447 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2448 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2449 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2450 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2451 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2452 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2453 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2454 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2455 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2456 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2457 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2458 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2459 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2460 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2461 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2462 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2463 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2464 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2465 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2466 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2467 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2468 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2469 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2470 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2471 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2472 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2473 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2474 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2476 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2477 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2478 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2479 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2480 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2481 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2482 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2483 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2484 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2485 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2486 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2488
2489 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2490 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2491 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2492 NUM_BANKS(ADDR_SURF_16_BANK));
2493 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2496 NUM_BANKS(ADDR_SURF_16_BANK));
2497 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2500 NUM_BANKS(ADDR_SURF_16_BANK));
2501 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2504 NUM_BANKS(ADDR_SURF_16_BANK));
2505 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2508 NUM_BANKS(ADDR_SURF_16_BANK));
2509 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2512 NUM_BANKS(ADDR_SURF_16_BANK));
2513 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2516 NUM_BANKS(ADDR_SURF_16_BANK));
2517 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2520 NUM_BANKS(ADDR_SURF_16_BANK));
2521 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2524 NUM_BANKS(ADDR_SURF_16_BANK));
2525 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2528 NUM_BANKS(ADDR_SURF_16_BANK));
2529 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2532 NUM_BANKS(ADDR_SURF_16_BANK));
2533 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2536 NUM_BANKS(ADDR_SURF_8_BANK));
2537 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2540 NUM_BANKS(ADDR_SURF_4_BANK));
2541 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2544 NUM_BANKS(ADDR_SURF_4_BANK));
2545
2546 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2547 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2548
2549 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2550 if (reg_offset != 7)
2551 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2552
68182d90
FC		 2553 break;
2554 case CHIP_BAFFIN:
2555 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2556 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2557 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2558 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2559 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2560 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2562 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2563 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2564 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2565 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2566 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2567 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2568 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2569 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2570 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2571 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2572 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2573 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2574 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2575 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2576 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2577 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2578 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2579 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2580 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2581 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2582 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2583 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2584 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2585 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2586 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2587 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2588 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2589 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2590 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2591 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2593 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2594 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2595 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2596 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2597 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2598 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2599 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2600 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2601 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2602 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2603 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2604 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2605 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2606 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2607 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2608 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2609 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2610 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2611 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2612 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2613 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2614 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2615 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2616 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2617 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2618 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2619 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2620 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2621 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2622 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2623 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2624 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2625 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2626 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2627 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2628 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2629 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2630 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2631 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2632 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2633 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2634 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2635 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2636 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2637 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2638 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2639 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2640 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2641 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2642 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2643 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2644 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2645 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2646 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2647 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2648 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2649 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2650 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2651 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2652 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2653 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2654 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2655 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2656 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2657 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2658 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2659 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2660 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2661 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2662 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2663 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2664 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2665 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2666 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2667 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2668 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2669 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2670 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2671 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2672 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2673 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2674 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2675 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2676 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2677
2678 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2681 NUM_BANKS(ADDR_SURF_16_BANK));
2682
2683 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2684 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2685 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2686 NUM_BANKS(ADDR_SURF_16_BANK));
2687
2688 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2689 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2690 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2691 NUM_BANKS(ADDR_SURF_16_BANK));
2692
2693 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2696 NUM_BANKS(ADDR_SURF_16_BANK));
2697
2698 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2699 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2700 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2701 NUM_BANKS(ADDR_SURF_16_BANK));
2702
2703 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2704 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2705 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2706 NUM_BANKS(ADDR_SURF_16_BANK));
2707
2708 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2709 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2710 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2711 NUM_BANKS(ADDR_SURF_16_BANK));
2712
2713 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2714 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2715 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2716 NUM_BANKS(ADDR_SURF_16_BANK));
2717
2718 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2721 NUM_BANKS(ADDR_SURF_16_BANK));
2722
2723 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2724 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2725 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2726 NUM_BANKS(ADDR_SURF_16_BANK));
2727
2728 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2729 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2730 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2731 NUM_BANKS(ADDR_SURF_16_BANK));
2732
2733 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2734 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2735 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2736 NUM_BANKS(ADDR_SURF_16_BANK));
2737
2738 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2739 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2740 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2741 NUM_BANKS(ADDR_SURF_8_BANK));
2742
2743 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2744 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2745 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2746 NUM_BANKS(ADDR_SURF_4_BANK));
2747
2748 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2749 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2750
2751 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2752 if (reg_offset != 7)
2753 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2754
2755 break;
2756 case CHIP_ELLESMERE:
2757 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2758 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2759 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2760 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2761 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2762 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2763 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2764 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2765 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2766 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2767 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2768 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2769 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2770 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2771 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2772 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2773 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2774 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2775 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2776 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2777 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2778 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2779 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2780 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2781 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2782 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2783 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2784 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2785 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2786 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2787 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2788 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2789 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2790 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2791 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2792 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2793 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2794 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2795 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2796 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2797 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2798 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2799 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2800 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2801 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2802 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2803 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2804 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2805 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2806 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2807 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2808 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2809 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2810 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2811 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2812 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2813 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2814 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2815 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2816 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2817 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2818 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2819 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2820 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2821 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2822 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2823 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2824 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2825 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2826 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2827 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2828 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2829 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2830 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2831 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2832 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2833 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2834 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2835 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2836 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2837 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2838 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2839 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2840 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2841 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2842 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2843 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2844 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2845 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2846 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2847 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2848 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2849 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2850 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2851 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2852 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2853 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2854 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2855 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2856 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2857 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2858 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2859 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2860 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2861 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2862 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2863 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2864 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2865 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2866 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2867 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2868 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2869 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2870 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2871 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2872 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2873 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2874 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2875 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2876 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2877 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2878 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2879
2880 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2881 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2882 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2883 NUM_BANKS(ADDR_SURF_16_BANK));
2884
2885 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2886 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2887 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2888 NUM_BANKS(ADDR_SURF_16_BANK));
2889
2890 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2891 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2892 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2893 NUM_BANKS(ADDR_SURF_16_BANK));
2894
2895 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2896 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2897 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2898 NUM_BANKS(ADDR_SURF_16_BANK));
2899
2900 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2901 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2902 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2903 NUM_BANKS(ADDR_SURF_16_BANK));
2904
2905 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2906 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2907 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2908 NUM_BANKS(ADDR_SURF_16_BANK));
2909
2910 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2911 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2912 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2913 NUM_BANKS(ADDR_SURF_16_BANK));
2914
2915 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2916 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2917 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2918 NUM_BANKS(ADDR_SURF_16_BANK));
2919
2920 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2921 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2922 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2923 NUM_BANKS(ADDR_SURF_16_BANK));
2924
2925 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2926 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2927 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2928 NUM_BANKS(ADDR_SURF_16_BANK));
2929
2930 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2933 NUM_BANKS(ADDR_SURF_16_BANK));
2934
2935 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2936 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2937 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2938 NUM_BANKS(ADDR_SURF_8_BANK));
2939
2940 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2941 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2942 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2943 NUM_BANKS(ADDR_SURF_4_BANK));
2944
2945 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2946 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2947 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2948 NUM_BANKS(ADDR_SURF_4_BANK));
2949
2950 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2951 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2952
2953 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2954 if (reg_offset != 7)
2955 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2956
aaa36a97 2957 break;
e3c7656c 2958 case CHIP_STONEY:
90bea0ab
TSD		 2959 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2960 PIPE_CONFIG(ADDR_SURF_P2) |
2961 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2962 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2963 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2964 PIPE_CONFIG(ADDR_SURF_P2) |
2965 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2966 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2967 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2968 PIPE_CONFIG(ADDR_SURF_P2) |
2969 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2970 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2971 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2972 PIPE_CONFIG(ADDR_SURF_P2) |
2973 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2974 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2975 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2976 PIPE_CONFIG(ADDR_SURF_P2) |
2977 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2978 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2979 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2980 PIPE_CONFIG(ADDR_SURF_P2) |
2981 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2982 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2983 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2984 PIPE_CONFIG(ADDR_SURF_P2) |
2985 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2986 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2987 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2988 PIPE_CONFIG(ADDR_SURF_P2));
2989 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2990 PIPE_CONFIG(ADDR_SURF_P2) |
2991 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2992 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2993 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2994 PIPE_CONFIG(ADDR_SURF_P2) |
2995 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2996 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2997 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2998 PIPE_CONFIG(ADDR_SURF_P2) |
2999 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3000 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3001 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3002 PIPE_CONFIG(ADDR_SURF_P2) |
3003 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3004 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3005 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3006 PIPE_CONFIG(ADDR_SURF_P2) |
3007 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3008 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3009 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3010 PIPE_CONFIG(ADDR_SURF_P2) |
3011 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3012 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3013 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3014 PIPE_CONFIG(ADDR_SURF_P2) |
3015 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3016 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3017 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3018 PIPE_CONFIG(ADDR_SURF_P2) |
3019 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3020 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3021 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3022 PIPE_CONFIG(ADDR_SURF_P2) |
3023 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3024 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3025 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3026 PIPE_CONFIG(ADDR_SURF_P2) |
3027 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3028 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3029 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3030 PIPE_CONFIG(ADDR_SURF_P2) |
3031 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3032 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3033 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3034 PIPE_CONFIG(ADDR_SURF_P2) |
3035 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3036 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3037 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3038 PIPE_CONFIG(ADDR_SURF_P2) |
3039 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3040 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3041 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3042 PIPE_CONFIG(ADDR_SURF_P2) |
3043 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3044 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3045 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3046 PIPE_CONFIG(ADDR_SURF_P2) |
3047 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3048 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3049 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3050 PIPE_CONFIG(ADDR_SURF_P2) |
3051 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3052 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3053 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3054 PIPE_CONFIG(ADDR_SURF_P2) |
3055 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3056 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3057 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3058 PIPE_CONFIG(ADDR_SURF_P2) |
3059 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3060 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3061
3062 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3065 NUM_BANKS(ADDR_SURF_8_BANK));
3066 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3067 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3068 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3069 NUM_BANKS(ADDR_SURF_8_BANK));
3070 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3073 NUM_BANKS(ADDR_SURF_8_BANK));
3074 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3075 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3076 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3077 NUM_BANKS(ADDR_SURF_8_BANK));
3078 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3079 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3080 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3081 NUM_BANKS(ADDR_SURF_8_BANK));
3082 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3083 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3084 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3085 NUM_BANKS(ADDR_SURF_8_BANK));
3086 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3087 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3088 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3089 NUM_BANKS(ADDR_SURF_8_BANK));
3090 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3093 NUM_BANKS(ADDR_SURF_16_BANK));
3094 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3095 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3096 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3097 NUM_BANKS(ADDR_SURF_16_BANK));
3098 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3101 NUM_BANKS(ADDR_SURF_16_BANK));
3102 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3103 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3104 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3105 NUM_BANKS(ADDR_SURF_16_BANK));
3106 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3107 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3108 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3109 NUM_BANKS(ADDR_SURF_16_BANK));
3110 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3113 NUM_BANKS(ADDR_SURF_16_BANK));
3114 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3115 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3116 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3117 NUM_BANKS(ADDR_SURF_8_BANK));
3118
3119 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3120 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3121 reg_offset != 23)
3122 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3123
3124 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3125 if (reg_offset != 7)
3126 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3127
e3c7656c 3128 break;
aaa36a97 3129 default:
90bea0ab
TSD		 3130 dev_warn(adev->dev,
3131 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3132 adev->asic_type);
3133
3134 case CHIP_CARRIZO:
3135 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3136 PIPE_CONFIG(ADDR_SURF_P2) |
3137 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3138 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3139 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3140 PIPE_CONFIG(ADDR_SURF_P2) |
3141 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3142 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3143 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3144 PIPE_CONFIG(ADDR_SURF_P2) |
3145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3146 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3147 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3148 PIPE_CONFIG(ADDR_SURF_P2) |
3149 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3150 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3151 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3152 PIPE_CONFIG(ADDR_SURF_P2) |
3153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3154 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3155 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3156 PIPE_CONFIG(ADDR_SURF_P2) |
3157 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3158 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3159 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3160 PIPE_CONFIG(ADDR_SURF_P2) |
3161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3162 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3163 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3164 PIPE_CONFIG(ADDR_SURF_P2));
3165 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3166 PIPE_CONFIG(ADDR_SURF_P2) |
3167 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3168 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3169 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3170 PIPE_CONFIG(ADDR_SURF_P2) |
3171 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3172 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3173 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3174 PIPE_CONFIG(ADDR_SURF_P2) |
3175 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3176 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3177 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3178 PIPE_CONFIG(ADDR_SURF_P2) |
3179 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3180 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3181 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3182 PIPE_CONFIG(ADDR_SURF_P2) |
3183 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3184 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3185 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3186 PIPE_CONFIG(ADDR_SURF_P2) |
3187 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3188 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3189 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3190 PIPE_CONFIG(ADDR_SURF_P2) |
3191 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3192 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3193 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3194 PIPE_CONFIG(ADDR_SURF_P2) |
3195 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3196 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3197 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3198 PIPE_CONFIG(ADDR_SURF_P2) |
3199 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3200 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3201 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3202 PIPE_CONFIG(ADDR_SURF_P2) |
3203 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3204 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3205 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3206 PIPE_CONFIG(ADDR_SURF_P2) |
3207 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3208 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3209 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3210 PIPE_CONFIG(ADDR_SURF_P2) |
3211 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3212 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3213 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3214 PIPE_CONFIG(ADDR_SURF_P2) |
3215 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3216 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3217 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3218 PIPE_CONFIG(ADDR_SURF_P2) |
3219 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3220 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3221 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3222 PIPE_CONFIG(ADDR_SURF_P2) |
3223 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3224 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3225 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3226 PIPE_CONFIG(ADDR_SURF_P2) |
3227 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3228 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3229 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3230 PIPE_CONFIG(ADDR_SURF_P2) |
3231 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3232 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3233 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3234 PIPE_CONFIG(ADDR_SURF_P2) |
3235 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3236 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3237
3238 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3239 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3240 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3241 NUM_BANKS(ADDR_SURF_8_BANK));
3242 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3243 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3244 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3245 NUM_BANKS(ADDR_SURF_8_BANK));
3246 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3247 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3248 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3249 NUM_BANKS(ADDR_SURF_8_BANK));
3250 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3253 NUM_BANKS(ADDR_SURF_8_BANK));
3254 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3255 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3256 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3257 NUM_BANKS(ADDR_SURF_8_BANK));
3258 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3259 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3260 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3261 NUM_BANKS(ADDR_SURF_8_BANK));
3262 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3265 NUM_BANKS(ADDR_SURF_8_BANK));
3266 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3268 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3269 NUM_BANKS(ADDR_SURF_16_BANK));
3270 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3273 NUM_BANKS(ADDR_SURF_16_BANK));
3274 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3275 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3276 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3277 NUM_BANKS(ADDR_SURF_16_BANK));
3278 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3281 NUM_BANKS(ADDR_SURF_16_BANK));
3282 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3283 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3284 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3285 NUM_BANKS(ADDR_SURF_16_BANK));
3286 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3289 NUM_BANKS(ADDR_SURF_16_BANK));
3290 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3291 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3292 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3293 NUM_BANKS(ADDR_SURF_8_BANK));
3294
3295 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3296 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3297 reg_offset != 23)
3298 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3299
3300 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3301 if (reg_offset != 7)
3302 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3303
3304 break;
aaa36a97
AD		 3305 }
3306}
3307
aaa36a97
AD		 3308void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
3309{
3310 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3311
3312 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
3313 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3314 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3315 } else if (se_num == 0xffffffff) {
3316 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3317 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3318 } else if (sh_num == 0xffffffff) {
3319 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3320 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3321 } else {
3322 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3323 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3324 }
3325 WREG32(mmGRBM_GFX_INDEX, data);
3326}
3327
8f8e00c1
AD		 3328static u32 gfx_v8_0_create_bitmask(u32 bit_width)
3329{
3330 return (u32)((1ULL << bit_width) - 1);
3331}
3332
3333static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
aaa36a97
AD		 3334{
3335 u32 data, mask;
3336
3337 data = RREG32(mmCC_RB_BACKEND_DISABLE);
aaa36a97
AD		 3338 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3339
8f8e00c1 3340 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
aaa36a97
AD		 3341 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
3342
8f8e00c1
AD		 3343 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
3344 adev->gfx.config.max_sh_per_se);
aaa36a97 3345
8f8e00c1 3346 return (~data) & mask;
aaa36a97
AD		 3347}
3348
8f8e00c1 3349static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
aaa36a97
AD		 3350{
3351 int i, j;
aac1e3ca 3352 u32 data;
8f8e00c1 3353 u32 active_rbs = 0;
6157bd7a
FC		 3354 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3355 adev->gfx.config.max_sh_per_se;
aaa36a97
AD		 3356
3357 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 3358 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3359 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
aaa36a97 3360 gfx_v8_0_select_se_sh(adev, i, j);
8f8e00c1
AD		 3361 data = gfx_v8_0_get_rb_active_bitmap(adev);
3362 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
6157bd7a 3363 rb_bitmap_width_per_sh);
aaa36a97
AD		 3364 }
3365 }
3366 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3367 mutex_unlock(&adev->grbm_idx_mutex);
3368
8f8e00c1 3369 adev->gfx.config.backend_enable_mask = active_rbs;
aac1e3ca 3370 adev->gfx.config.num_rbs = hweight32(active_rbs);
aaa36a97
AD		 3371}
3372
cd06bf68 3373/**
35c7a952 3374 * gfx_v8_0_init_compute_vmid - gart enable
cd06bf68
BG		 3375 *
3376 * @rdev: amdgpu_device pointer
3377 *
3378 * Initialize compute vmid sh_mem registers
3379 *
3380 */
3381#define DEFAULT_SH_MEM_BASES (0x6000)
3382#define FIRST_COMPUTE_VMID (8)
3383#define LAST_COMPUTE_VMID (16)
35c7a952 3384static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
cd06bf68
BG		 3385{
3386 int i;
3387 uint32_t sh_mem_config;
3388 uint32_t sh_mem_bases;
3389
3390 /*
3391 * Configure apertures:
3392 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3393 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3394 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3395 */
3396 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3397
3398 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3399 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3400 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3401 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3402 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3403 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3404
3405 mutex_lock(&adev->srbm_mutex);
3406 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
3407 vi_srbm_select(adev, 0, 0, 0, i);
3408 /* CP and shaders */
3409 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3410 WREG32(mmSH_MEM_APE1_BASE, 1);
3411 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3412 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3413 }
3414 vi_srbm_select(adev, 0, 0, 0, 0);
3415 mutex_unlock(&adev->srbm_mutex);
3416}
3417
aaa36a97
AD		 3418static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
3419{
aaa36a97
AD		 3420 u32 tmp;
3421 int i;
3422
aaa36a97
AD		 3423 tmp = RREG32(mmGRBM_CNTL);
3424 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
3425 WREG32(mmGRBM_CNTL, tmp);
3426
0bde3a95
AD		 3427 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3428 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3429 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
aaa36a97
AD		 3430
3431 gfx_v8_0_tiling_mode_table_init(adev);
3432
8f8e00c1 3433 gfx_v8_0_setup_rb(adev);
aaa36a97
AD		 3434
3435 /* XXX SH_MEM regs */
3436 /* where to put LDS, scratch, GPUVM in FSA64 space */
3437 mutex_lock(&adev->srbm_mutex);
3438 for (i = 0; i < 16; i++) {
3439 vi_srbm_select(adev, 0, 0, 0, i);
3440 /* CP and shaders */
3441 if (i == 0) {
3442 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3443 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
0bde3a95 3444 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165 3445 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 3446 WREG32(mmSH_MEM_CONFIG, tmp);
3447 } else {
3448 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3449 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
0bde3a95 3450 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165 3451 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 3452 WREG32(mmSH_MEM_CONFIG, tmp);
3453 }
3454
3455 WREG32(mmSH_MEM_APE1_BASE, 1);
3456 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3457 WREG32(mmSH_MEM_BASES, 0);
3458 }
3459 vi_srbm_select(adev, 0, 0, 0, 0);
3460 mutex_unlock(&adev->srbm_mutex);
3461
35c7a952 3462 gfx_v8_0_init_compute_vmid(adev);
cd06bf68 3463
aaa36a97
AD		 3464 mutex_lock(&adev->grbm_idx_mutex);
3465 /*
3466 * making sure that the following register writes will be broadcasted
3467 * to all the shaders
3468 */
3469 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3470
3471 WREG32(mmPA_SC_FIFO_SIZE,
3472 (adev->gfx.config.sc_prim_fifo_size_frontend <<
3473 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3474 (adev->gfx.config.sc_prim_fifo_size_backend <<
3475 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3476 (adev->gfx.config.sc_hiz_tile_fifo_size <<
3477 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3478 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3479 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3480 mutex_unlock(&adev->grbm_idx_mutex);
3481
3482}
3483
3484static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3485{
3486 u32 i, j, k;
3487 u32 mask;
3488
3489 mutex_lock(&adev->grbm_idx_mutex);
3490 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3491 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3492 gfx_v8_0_select_se_sh(adev, i, j);
3493 for (k = 0; k < adev->usec_timeout; k++) {
3494 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3495 break;
3496 udelay(1);
3497 }
3498 }
3499 }
3500 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3501 mutex_unlock(&adev->grbm_idx_mutex);
3502
3503 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3504 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3505 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3506 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3507 for (k = 0; k < adev->usec_timeout; k++) {
3508 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3509 break;
3510 udelay(1);
3511 }
3512}
3513
3514static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3515 bool enable)
3516{
3517 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3518
0d07db7e
TSD		 3519 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3520 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3521 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3522 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3523
aaa36a97
AD		 3524 WREG32(mmCP_INT_CNTL_RING0, tmp);
3525}
3526
2b6cd977
EH		 3527static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3528{
3529 /* csib */
3530 WREG32(mmRLC_CSIB_ADDR_HI,
3531 adev->gfx.rlc.clear_state_gpu_addr >> 32);
3532 WREG32(mmRLC_CSIB_ADDR_LO,
3533 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3534 WREG32(mmRLC_CSIB_LENGTH,
3535 adev->gfx.rlc.clear_state_size);
3536}
3537
3538static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3539 int ind_offset,
3540 int list_size,
3541 int *unique_indices,
3542 int *indices_count,
3543 int max_indices,
3544 int *ind_start_offsets,
3545 int *offset_count,
3546 int max_offset)
3547{
3548 int indices;
3549 bool new_entry = true;
3550
3551 for (; ind_offset < list_size; ind_offset++) {
3552
3553 if (new_entry) {
3554 new_entry = false;
3555 ind_start_offsets[*offset_count] = ind_offset;
3556 *offset_count = *offset_count + 1;
3557 BUG_ON(*offset_count >= max_offset);
3558 }
3559
3560 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3561 new_entry = true;
3562 continue;
3563 }
3564
3565 ind_offset += 2;
3566
3567 /* look for the matching indice */
3568 for (indices = 0;
3569 indices < *indices_count;
3570 indices++) {
3571 if (unique_indices[indices] ==
3572 register_list_format[ind_offset])
3573 break;
3574 }
3575
3576 if (indices >= *indices_count) {
3577 unique_indices[*indices_count] =
3578 register_list_format[ind_offset];
3579 indices = *indices_count;
3580 *indices_count = *indices_count + 1;
3581 BUG_ON(*indices_count >= max_indices);
3582 }
3583
3584 register_list_format[ind_offset] = indices;
3585 }
3586}
3587
3588static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3589{
3590 int i, temp, data;
3591 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3592 int indices_count = 0;
3593 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3594 int offset_count = 0;
3595
3596 int list_size;
3597 unsigned int *register_list_format =
3598 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3599 if (register_list_format == NULL)
3600 return -ENOMEM;
3601 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
3602 adev->gfx.rlc.reg_list_format_size_bytes);
3603
3604 gfx_v8_0_parse_ind_reg_list(register_list_format,
3605 RLC_FormatDirectRegListLength,
3606 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3607 unique_indices,
3608 &indices_count,
3609 sizeof(unique_indices) / sizeof(int),
3610 indirect_start_offsets,
3611 &offset_count,
3612 sizeof(indirect_start_offsets)/sizeof(int));
3613
3614 /* save and restore list */
3615 temp = RREG32(mmRLC_SRM_CNTL);
3616 temp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
3617 WREG32(mmRLC_SRM_CNTL, temp);
3618
3619 WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3620 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3621 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
3622
3623 /* indirect list */
3624 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
3625 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
3626 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3627
3628 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
3629 list_size = list_size >> 1;
3630 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
3631 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
3632
3633 /* starting offsets starts */
3634 WREG32(mmRLC_GPM_SCRATCH_ADDR,
3635 adev->gfx.rlc.starting_offsets_start);
3636 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
3637 WREG32(mmRLC_GPM_SCRATCH_DATA,
3638 indirect_start_offsets[i]);
3639
3640 /* unique indices */
3641 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
3642 data = mmRLC_SRM_INDEX_CNTL_DATA_0;
3643 for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
3644 amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
3645 amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
3646 }
3647 kfree(register_list_format);
3648
3649 return 0;
3650}
3651
3652static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
3653{
3654 uint32_t data;
3655
3656 data = RREG32(mmRLC_SRM_CNTL);
3657 data |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
3658 WREG32(mmRLC_SRM_CNTL, data);
3659}
3660
f4bfffdd
EH		 3661static void baffin_init_power_gating(struct amdgpu_device *adev)
3662{
3663 uint32_t data;
3664
3665 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3666 AMD_PG_SUPPORT_GFX_SMG |
3667 AMD_PG_SUPPORT_GFX_DMG)) {
3668 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3669 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3670 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3671 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3672
3673 data = 0;
3674 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
3675 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
3676 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
3677 data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
3678 WREG32(mmRLC_PG_DELAY, data);
3679
3680 data = RREG32(mmRLC_PG_DELAY_2);
3681 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
3682 data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
3683 WREG32(mmRLC_PG_DELAY_2, data);
3684
3685 data = RREG32(mmRLC_AUTO_PG_CTRL);
3686 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3687 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3688 WREG32(mmRLC_AUTO_PG_CTRL, data);
3689 }
3690}
3691
2b6cd977
EH		 3692static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
3693{
3694 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3695 AMD_PG_SUPPORT_GFX_SMG |
3696 AMD_PG_SUPPORT_GFX_DMG |
3697 AMD_PG_SUPPORT_CP |
3698 AMD_PG_SUPPORT_GDS |
3699 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3700 gfx_v8_0_init_csb(adev);
3701 gfx_v8_0_init_save_restore_list(adev);
3702 gfx_v8_0_enable_save_restore_machine(adev);
f4bfffdd
EH		 3703
3704 if (adev->asic_type == CHIP_BAFFIN)
3705 baffin_init_power_gating(adev);
2b6cd977
EH		 3706 }
3707}
3708
aaa36a97
AD		 3709void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
3710{
3711 u32 tmp = RREG32(mmRLC_CNTL);
3712
3713 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
3714 WREG32(mmRLC_CNTL, tmp);
3715
3716 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3717
3718 gfx_v8_0_wait_for_rlc_serdes(adev);
3719}
3720
3721static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
3722{
3723 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3724
3725 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3726 WREG32(mmGRBM_SOFT_RESET, tmp);
3727 udelay(50);
3728 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
3729 WREG32(mmGRBM_SOFT_RESET, tmp);
3730 udelay(50);
3731}
3732
3733static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
3734{
3735 u32 tmp = RREG32(mmRLC_CNTL);
3736
3737 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
3738 WREG32(mmRLC_CNTL, tmp);
3739
3740 /* carrizo do enable cp interrupt after cp inited */
e3c7656c 3741 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 3742 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3743
3744 udelay(50);
3745}
3746
3747static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
3748{
3749 const struct rlc_firmware_header_v2_0 *hdr;
3750 const __le32 *fw_data;
3751 unsigned i, fw_size;
3752
3753 if (!adev->gfx.rlc_fw)
3754 return -EINVAL;
3755
3756 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3757 amdgpu_ucode_print_rlc_hdr(&hdr->header);
aaa36a97
AD		 3758
3759 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
3760 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3761 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3762
3763 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3764 for (i = 0; i < fw_size; i++)
3765 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3766 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3767
3768 return 0;
3769}
3770
3771static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
3772{
3773 int r;
3774
3775 gfx_v8_0_rlc_stop(adev);
3776
3777 /* disable CG */
3778 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
68182d90
FC		 3779 if (adev->asic_type == CHIP_BAFFIN ||
3780 adev->asic_type == CHIP_ELLESMERE)
3781 WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0);
aaa36a97
AD		 3782
3783 /* disable PG */
3784 WREG32(mmRLC_PG_CNTL, 0);
3785
3786 gfx_v8_0_rlc_reset(adev);
3787
2b6cd977
EH		 3788 gfx_v8_0_init_pg(adev);
3789
e61710c5 3790 if (!adev->pp_enabled) {
ba5c2a87
RZ		 3791 if (!adev->firmware.smu_load) {
3792 /* legacy rlc firmware loading */
3793 r = gfx_v8_0_rlc_load_microcode(adev);
3794 if (r)
3795 return r;
3796 } else {
3797 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3798 AMDGPU_UCODE_ID_RLC_G);
3799 if (r)
3800 return -EINVAL;
3801 }
aaa36a97
AD		 3802 }
3803
3804 gfx_v8_0_rlc_start(adev);
3805
3806 return 0;
3807}
3808
3809static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
3810{
3811 int i;
3812 u32 tmp = RREG32(mmCP_ME_CNTL);
3813
3814 if (enable) {
3815 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
3816 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
3817 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
3818 } else {
3819 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
3820 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
3821 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
3822 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3823 adev->gfx.gfx_ring[i].ready = false;
3824 }
3825 WREG32(mmCP_ME_CNTL, tmp);
3826 udelay(50);
3827}
3828
3829static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3830{
3831 const struct gfx_firmware_header_v1_0 *pfp_hdr;
3832 const struct gfx_firmware_header_v1_0 *ce_hdr;
3833 const struct gfx_firmware_header_v1_0 *me_hdr;
3834 const __le32 *fw_data;
3835 unsigned i, fw_size;
3836
3837 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
3838 return -EINVAL;
3839
3840 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
3841 adev->gfx.pfp_fw->data;
3842 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
3843 adev->gfx.ce_fw->data;
3844 me_hdr = (const struct gfx_firmware_header_v1_0 *)
3845 adev->gfx.me_fw->data;
3846
3847 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
3848 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
3849 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
aaa36a97
AD		 3850
3851 gfx_v8_0_cp_gfx_enable(adev, false);
3852
3853 /* PFP */
3854 fw_data = (const __le32 *)
3855 (adev->gfx.pfp_fw->data +
3856 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3857 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3858 WREG32(mmCP_PFP_UCODE_ADDR, 0);
3859 for (i = 0; i < fw_size; i++)
3860 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3861 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
3862
3863 /* CE */
3864 fw_data = (const __le32 *)
3865 (adev->gfx.ce_fw->data +
3866 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3867 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3868 WREG32(mmCP_CE_UCODE_ADDR, 0);
3869 for (i = 0; i < fw_size; i++)
3870 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3871 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
3872
3873 /* ME */
3874 fw_data = (const __le32 *)
3875 (adev->gfx.me_fw->data +
3876 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3877 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3878 WREG32(mmCP_ME_RAM_WADDR, 0);
3879 for (i = 0; i < fw_size; i++)
3880 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3881 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
3882
3883 return 0;
3884}
3885
3886static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
3887{
3888 u32 count = 0;
3889 const struct cs_section_def *sect = NULL;
3890 const struct cs_extent_def *ext = NULL;
3891
3892 /* begin clear state */
3893 count += 2;
3894 /* context control state */
3895 count += 3;
3896
3897 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
3898 for (ext = sect->section; ext->extent != NULL; ++ext) {
3899 if (sect->id == SECT_CONTEXT)
3900 count += 2 + ext->reg_count;
3901 else
3902 return 0;
3903 }
3904 }
3905 /* pa_sc_raster_config/pa_sc_raster_config1 */
3906 count += 4;
3907 /* end clear state */
3908 count += 2;
3909 /* clear state */
3910 count += 2;
3911
3912 return count;
3913}
3914
3915static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
3916{
3917 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
3918 const struct cs_section_def *sect = NULL;
3919 const struct cs_extent_def *ext = NULL;
3920 int r, i;
3921
3922 /* init the CP */
3923 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
3924 WREG32(mmCP_ENDIAN_SWAP, 0);
3925 WREG32(mmCP_DEVICE_ID, 1);
3926
3927 gfx_v8_0_cp_gfx_enable(adev, true);
3928
a27de35c 3929 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
aaa36a97
AD		 3930 if (r) {
3931 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3932 return r;
3933 }
3934
3935 /* clear state buffer */
3936 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3937 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3938
3939 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3940 amdgpu_ring_write(ring, 0x80000000);
3941 amdgpu_ring_write(ring, 0x80000000);
3942
3943 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
3944 for (ext = sect->section; ext->extent != NULL; ++ext) {
3945 if (sect->id == SECT_CONTEXT) {
3946 amdgpu_ring_write(ring,
3947 PACKET3(PACKET3_SET_CONTEXT_REG,
3948 ext->reg_count));
3949 amdgpu_ring_write(ring,
3950 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3951 for (i = 0; i < ext->reg_count; i++)
3952 amdgpu_ring_write(ring, ext->extent[i]);
3953 }
3954 }
3955 }
3956
3957 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3958 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
3959 switch (adev->asic_type) {
3960 case CHIP_TONGA:
68182d90 3961 case CHIP_ELLESMERE:
aaa36a97
AD		 3962 amdgpu_ring_write(ring, 0x16000012);
3963 amdgpu_ring_write(ring, 0x0000002A);
3964 break;
68182d90
FC		 3965 case CHIP_BAFFIN:
3966 amdgpu_ring_write(ring, 0x16000012);
3967 amdgpu_ring_write(ring, 0x00000000);
3968 break;
fa676048
FC		 3969 case CHIP_FIJI:
3970 amdgpu_ring_write(ring, 0x3a00161a);
3971 amdgpu_ring_write(ring, 0x0000002e);
3972 break;
aaa36a97
AD		 3973 case CHIP_TOPAZ:
3974 case CHIP_CARRIZO:
3975 amdgpu_ring_write(ring, 0x00000002);
3976 amdgpu_ring_write(ring, 0x00000000);
3977 break;
e3c7656c
SL		 3978 case CHIP_STONEY:
3979 amdgpu_ring_write(ring, 0x00000000);
3980 amdgpu_ring_write(ring, 0x00000000);
3981 break;
aaa36a97
AD		 3982 default:
3983 BUG();
3984 }
3985
3986 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3987 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3988
3989 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3990 amdgpu_ring_write(ring, 0);
3991
3992 /* init the CE partitions */
3993 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3994 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3995 amdgpu_ring_write(ring, 0x8000);
3996 amdgpu_ring_write(ring, 0x8000);
3997
a27de35c 3998 amdgpu_ring_commit(ring);
aaa36a97
AD		 3999
4000 return 0;
4001}
4002
4003static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4004{
4005 struct amdgpu_ring *ring;
4006 u32 tmp;
4007 u32 rb_bufsz;
4008 u64 rb_addr, rptr_addr;
4009 int r;
4010
4011 /* Set the write pointer delay */
4012 WREG32(mmCP_RB_WPTR_DELAY, 0);
4013
4014 /* set the RB to use vmid 0 */
4015 WREG32(mmCP_RB_VMID, 0);
4016
4017 /* Set ring buffer size */
4018 ring = &adev->gfx.gfx_ring[0];
4019 rb_bufsz = order_base_2(ring->ring_size / 8);
4020 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4021 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4022 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4023 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4024#ifdef __BIG_ENDIAN
4025 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4026#endif
4027 WREG32(mmCP_RB0_CNTL, tmp);
4028
4029 /* Initialize the ring buffer's read and write pointers */
4030 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4031 ring->wptr = 0;
4032 WREG32(mmCP_RB0_WPTR, ring->wptr);
4033
4034 /* set the wb address wether it's enabled or not */
4035 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4036 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4037 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4038
4039 mdelay(1);
4040 WREG32(mmCP_RB0_CNTL, tmp);
4041
4042 rb_addr = ring->gpu_addr >> 8;
4043 WREG32(mmCP_RB0_BASE, rb_addr);
4044 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4045
4046 /* no gfx doorbells on iceland */
4047 if (adev->asic_type != CHIP_TOPAZ) {
4048 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4049 if (ring->use_doorbell) {
4050 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4051 DOORBELL_OFFSET, ring->doorbell_index);
68182d90
FC		 4052 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4053 DOORBELL_HIT, 0);
aaa36a97
AD		 4054 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4055 DOORBELL_EN, 1);
4056 } else {
4057 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4058 DOORBELL_EN, 0);
4059 }
4060 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4061
4062 if (adev->asic_type == CHIP_TONGA) {
4063 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4064 DOORBELL_RANGE_LOWER,
4065 AMDGPU_DOORBELL_GFX_RING0);
4066 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4067
4068 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4069 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4070 }
4071
4072 }
4073
4074 /* start the ring */
4075 gfx_v8_0_cp_gfx_start(adev);
4076 ring->ready = true;
4077 r = amdgpu_ring_test_ring(ring);
4078 if (r) {
4079 ring->ready = false;
4080 return r;
4081 }
4082
4083 return 0;
4084}
4085
4086static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4087{
4088 int i;
4089
4090 if (enable) {
4091 WREG32(mmCP_MEC_CNTL, 0);
4092 } else {
4093 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4094 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4095 adev->gfx.compute_ring[i].ready = false;
4096 }
4097 udelay(50);
4098}
4099
aaa36a97
AD		 4100static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
4101{
4102 const struct gfx_firmware_header_v1_0 *mec_hdr;
4103 const __le32 *fw_data;
4104 unsigned i, fw_size;
4105
4106 if (!adev->gfx.mec_fw)
4107 return -EINVAL;
4108
4109 gfx_v8_0_cp_compute_enable(adev, false);
4110
4111 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4112 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
aaa36a97
AD		 4113
4114 fw_data = (const __le32 *)
4115 (adev->gfx.mec_fw->data +
4116 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4117 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
4118
4119 /* MEC1 */
4120 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
4121 for (i = 0; i < fw_size; i++)
4122 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
4123 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
4124
4125 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
4126 if (adev->gfx.mec2_fw) {
4127 const struct gfx_firmware_header_v1_0 *mec2_hdr;
4128
4129 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4130 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
aaa36a97
AD		 4131
4132 fw_data = (const __le32 *)
4133 (adev->gfx.mec2_fw->data +
4134 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
4135 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
4136
4137 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
4138 for (i = 0; i < fw_size; i++)
4139 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
4140 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
4141 }
4142
4143 return 0;
4144}
4145
4146struct vi_mqd {
4147 uint32_t header; /* ordinal0 */
4148 uint32_t compute_dispatch_initiator; /* ordinal1 */
4149 uint32_t compute_dim_x; /* ordinal2 */
4150 uint32_t compute_dim_y; /* ordinal3 */
4151 uint32_t compute_dim_z; /* ordinal4 */
4152 uint32_t compute_start_x; /* ordinal5 */
4153 uint32_t compute_start_y; /* ordinal6 */
4154 uint32_t compute_start_z; /* ordinal7 */
4155 uint32_t compute_num_thread_x; /* ordinal8 */
4156 uint32_t compute_num_thread_y; /* ordinal9 */
4157 uint32_t compute_num_thread_z; /* ordinal10 */
4158 uint32_t compute_pipelinestat_enable; /* ordinal11 */
4159 uint32_t compute_perfcount_enable; /* ordinal12 */
4160 uint32_t compute_pgm_lo; /* ordinal13 */
4161 uint32_t compute_pgm_hi; /* ordinal14 */
4162 uint32_t compute_tba_lo; /* ordinal15 */
4163 uint32_t compute_tba_hi; /* ordinal16 */
4164 uint32_t compute_tma_lo; /* ordinal17 */
4165 uint32_t compute_tma_hi; /* ordinal18 */
4166 uint32_t compute_pgm_rsrc1; /* ordinal19 */
4167 uint32_t compute_pgm_rsrc2; /* ordinal20 */
4168 uint32_t compute_vmid; /* ordinal21 */
4169 uint32_t compute_resource_limits; /* ordinal22 */
4170 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
4171 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
4172 uint32_t compute_tmpring_size; /* ordinal25 */
4173 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
4174 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
4175 uint32_t compute_restart_x; /* ordinal28 */
4176 uint32_t compute_restart_y; /* ordinal29 */
4177 uint32_t compute_restart_z; /* ordinal30 */
4178 uint32_t compute_thread_trace_enable; /* ordinal31 */
4179 uint32_t compute_misc_reserved; /* ordinal32 */
4180 uint32_t compute_dispatch_id; /* ordinal33 */
4181 uint32_t compute_threadgroup_id; /* ordinal34 */
4182 uint32_t compute_relaunch; /* ordinal35 */
4183 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
4184 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
4185 uint32_t compute_wave_restore_control; /* ordinal38 */
4186 uint32_t reserved9; /* ordinal39 */
4187 uint32_t reserved10; /* ordinal40 */
4188 uint32_t reserved11; /* ordinal41 */
4189 uint32_t reserved12; /* ordinal42 */
4190 uint32_t reserved13; /* ordinal43 */
4191 uint32_t reserved14; /* ordinal44 */
4192 uint32_t reserved15; /* ordinal45 */
4193 uint32_t reserved16; /* ordinal46 */
4194 uint32_t reserved17; /* ordinal47 */
4195 uint32_t reserved18; /* ordinal48 */
4196 uint32_t reserved19; /* ordinal49 */
4197 uint32_t reserved20; /* ordinal50 */
4198 uint32_t reserved21; /* ordinal51 */
4199 uint32_t reserved22; /* ordinal52 */
4200 uint32_t reserved23; /* ordinal53 */
4201 uint32_t reserved24; /* ordinal54 */
4202 uint32_t reserved25; /* ordinal55 */
4203 uint32_t reserved26; /* ordinal56 */
4204 uint32_t reserved27; /* ordinal57 */
4205 uint32_t reserved28; /* ordinal58 */
4206 uint32_t reserved29; /* ordinal59 */
4207 uint32_t reserved30; /* ordinal60 */
4208 uint32_t reserved31; /* ordinal61 */
4209 uint32_t reserved32; /* ordinal62 */
4210 uint32_t reserved33; /* ordinal63 */
4211 uint32_t reserved34; /* ordinal64 */
4212 uint32_t compute_user_data_0; /* ordinal65 */
4213 uint32_t compute_user_data_1; /* ordinal66 */
4214 uint32_t compute_user_data_2; /* ordinal67 */
4215 uint32_t compute_user_data_3; /* ordinal68 */
4216 uint32_t compute_user_data_4; /* ordinal69 */
4217 uint32_t compute_user_data_5; /* ordinal70 */
4218 uint32_t compute_user_data_6; /* ordinal71 */
4219 uint32_t compute_user_data_7; /* ordinal72 */
4220 uint32_t compute_user_data_8; /* ordinal73 */
4221 uint32_t compute_user_data_9; /* ordinal74 */
4222 uint32_t compute_user_data_10; /* ordinal75 */
4223 uint32_t compute_user_data_11; /* ordinal76 */
4224 uint32_t compute_user_data_12; /* ordinal77 */
4225 uint32_t compute_user_data_13; /* ordinal78 */
4226 uint32_t compute_user_data_14; /* ordinal79 */
4227 uint32_t compute_user_data_15; /* ordinal80 */
4228 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
4229 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
4230 uint32_t reserved35; /* ordinal83 */
4231 uint32_t reserved36; /* ordinal84 */
4232 uint32_t reserved37; /* ordinal85 */
4233 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
4234 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
4235 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
4236 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
4237 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
4238 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
4239 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
4240 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
4241 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
4242 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
4243 uint32_t reserved38; /* ordinal96 */
4244 uint32_t reserved39; /* ordinal97 */
4245 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
4246 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
4247 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
4248 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
4249 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
4250 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
4251 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
4252 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
4253 uint32_t reserved40; /* ordinal106 */
4254 uint32_t reserved41; /* ordinal107 */
4255 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
4256 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
4257 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
4258 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
4259 uint32_t reserved42; /* ordinal112 */
4260 uint32_t reserved43; /* ordinal113 */
4261 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
4262 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
4263 uint32_t cp_packet_id_lo; /* ordinal116 */
4264 uint32_t cp_packet_id_hi; /* ordinal117 */
4265 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
4266 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
4267 uint32_t gds_save_base_addr_lo; /* ordinal120 */
4268 uint32_t gds_save_base_addr_hi; /* ordinal121 */
4269 uint32_t gds_save_mask_lo; /* ordinal122 */
4270 uint32_t gds_save_mask_hi; /* ordinal123 */
4271 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
4272 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
4273 uint32_t reserved44; /* ordinal126 */
4274 uint32_t reserved45; /* ordinal127 */
4275 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
4276 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
4277 uint32_t cp_hqd_active; /* ordinal130 */
4278 uint32_t cp_hqd_vmid; /* ordinal131 */
4279 uint32_t cp_hqd_persistent_state; /* ordinal132 */
4280 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
4281 uint32_t cp_hqd_queue_priority; /* ordinal134 */
4282 uint32_t cp_hqd_quantum; /* ordinal135 */
4283 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
4284 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
4285 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
4286 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
4287 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
4288 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
4289 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
4290 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
4291 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
4292 uint32_t cp_hqd_pq_control; /* ordinal145 */
4293 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
4294 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
4295 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
4296 uint32_t cp_hqd_ib_control; /* ordinal149 */
4297 uint32_t cp_hqd_iq_timer; /* ordinal150 */
4298 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
4299 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
4300 uint32_t cp_hqd_dma_offload; /* ordinal153 */
4301 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
4302 uint32_t cp_hqd_msg_type; /* ordinal155 */
4303 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
4304 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
4305 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
4306 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
4307 uint32_t cp_hqd_hq_status0; /* ordinal160 */
4308 uint32_t cp_hqd_hq_control0; /* ordinal161 */
4309 uint32_t cp_mqd_control; /* ordinal162 */
4310 uint32_t cp_hqd_hq_status1; /* ordinal163 */
4311 uint32_t cp_hqd_hq_control1; /* ordinal164 */
4312 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
4313 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
4314 uint32_t cp_hqd_eop_control; /* ordinal167 */
4315 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
4316 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
4317 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
4318 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
4319 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
4320 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
4321 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
4322 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
4323 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
4324 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
4325 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
4326 uint32_t cp_hqd_error; /* ordinal179 */
4327 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
4328 uint32_t cp_hqd_eop_dones; /* ordinal181 */
4329 uint32_t reserved46; /* ordinal182 */
4330 uint32_t reserved47; /* ordinal183 */
4331 uint32_t reserved48; /* ordinal184 */
4332 uint32_t reserved49; /* ordinal185 */
4333 uint32_t reserved50; /* ordinal186 */
4334 uint32_t reserved51; /* ordinal187 */
4335 uint32_t reserved52; /* ordinal188 */
4336 uint32_t reserved53; /* ordinal189 */
4337 uint32_t reserved54; /* ordinal190 */
4338 uint32_t reserved55; /* ordinal191 */
4339 uint32_t iqtimer_pkt_header; /* ordinal192 */
4340 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
4341 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
4342 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
4343 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
4344 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
4345 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
4346 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
4347 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
4348 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
4349 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
4350 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
4351 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
4352 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
4353 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
4354 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
4355 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
4356 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
4357 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
4358 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
4359 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
4360 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
4361 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
4362 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
4363 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
4364 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
4365 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
4366 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
4367 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
4368 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
4369 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
4370 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
4371 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
4372 uint32_t reserved56; /* ordinal225 */
4373 uint32_t reserved57; /* ordinal226 */
4374 uint32_t reserved58; /* ordinal227 */
4375 uint32_t set_resources_header; /* ordinal228 */
4376 uint32_t set_resources_dw1; /* ordinal229 */
4377 uint32_t set_resources_dw2; /* ordinal230 */
4378 uint32_t set_resources_dw3; /* ordinal231 */
4379 uint32_t set_resources_dw4; /* ordinal232 */
4380 uint32_t set_resources_dw5; /* ordinal233 */
4381 uint32_t set_resources_dw6; /* ordinal234 */
4382 uint32_t set_resources_dw7; /* ordinal235 */
4383 uint32_t reserved59; /* ordinal236 */
4384 uint32_t reserved60; /* ordinal237 */
4385 uint32_t reserved61; /* ordinal238 */
4386 uint32_t reserved62; /* ordinal239 */
4387 uint32_t reserved63; /* ordinal240 */
4388 uint32_t reserved64; /* ordinal241 */
4389 uint32_t reserved65; /* ordinal242 */
4390 uint32_t reserved66; /* ordinal243 */
4391 uint32_t reserved67; /* ordinal244 */
4392 uint32_t reserved68; /* ordinal245 */
4393 uint32_t reserved69; /* ordinal246 */
4394 uint32_t reserved70; /* ordinal247 */
4395 uint32_t reserved71; /* ordinal248 */
4396 uint32_t reserved72; /* ordinal249 */
4397 uint32_t reserved73; /* ordinal250 */
4398 uint32_t reserved74; /* ordinal251 */
4399 uint32_t reserved75; /* ordinal252 */
4400 uint32_t reserved76; /* ordinal253 */
4401 uint32_t reserved77; /* ordinal254 */
4402 uint32_t reserved78; /* ordinal255 */
4403
4404 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
4405};
4406
4407static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
4408{
4409 int i, r;
4410
4411 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4412 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4413
4414 if (ring->mqd_obj) {
4415 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4416 if (unlikely(r != 0))
4417 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
4418
4419 amdgpu_bo_unpin(ring->mqd_obj);
4420 amdgpu_bo_unreserve(ring->mqd_obj);
4421
4422 amdgpu_bo_unref(&ring->mqd_obj);
4423 ring->mqd_obj = NULL;
4424 }
4425 }
4426}
4427
4428static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
4429{
4430 int r, i, j;
4431 u32 tmp;
4432 bool use_doorbell = true;
4433 u64 hqd_gpu_addr;
4434 u64 mqd_gpu_addr;
4435 u64 eop_gpu_addr;
4436 u64 wb_gpu_addr;
4437 u32 *buf;
4438 struct vi_mqd *mqd;
4439
4440 /* init the pipes */
4441 mutex_lock(&adev->srbm_mutex);
4442 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
4443 int me = (i < 4) ? 1 : 2;
4444 int pipe = (i < 4) ? i : (i - 4);
4445
4446 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
4447 eop_gpu_addr >>= 8;
4448
4449 vi_srbm_select(adev, me, pipe, 0, 0);
4450
4451 /* write the EOP addr */
4452 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
4453 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
4454
4455 /* set the VMID assigned */
4456 WREG32(mmCP_HQD_VMID, 0);
4457
4458 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4459 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4460 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4461 (order_base_2(MEC_HPD_SIZE / 4) - 1));
4462 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
4463 }
4464 vi_srbm_select(adev, 0, 0, 0, 0);
4465 mutex_unlock(&adev->srbm_mutex);
4466
4467 /* init the queues. Just two for now. */
4468 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4469 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4470
4471 if (ring->mqd_obj == NULL) {
4472 r = amdgpu_bo_create(adev,
4473 sizeof(struct vi_mqd),
4474 PAGE_SIZE, true,
4475 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
72d7668b 4476 NULL, &ring->mqd_obj);
aaa36a97
AD		 4477 if (r) {
4478 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
4479 return r;
4480 }
4481 }
4482
4483 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4484 if (unlikely(r != 0)) {
4485 gfx_v8_0_cp_compute_fini(adev);
4486 return r;
4487 }
4488 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
4489 &mqd_gpu_addr);
4490 if (r) {
4491 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
4492 gfx_v8_0_cp_compute_fini(adev);
4493 return r;
4494 }
4495 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
4496 if (r) {
4497 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
4498 gfx_v8_0_cp_compute_fini(adev);
4499 return r;
4500 }
4501
4502 /* init the mqd struct */
4503 memset(buf, 0, sizeof(struct vi_mqd));
4504
4505 mqd = (struct vi_mqd *)buf;
4506 mqd->header = 0xC0310800;
4507 mqd->compute_pipelinestat_enable = 0x00000001;
4508 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4509 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4510 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4511 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4512 mqd->compute_misc_reserved = 0x00000003;
4513
4514 mutex_lock(&adev->srbm_mutex);
4515 vi_srbm_select(adev, ring->me,
4516 ring->pipe,
4517 ring->queue, 0);
4518
4519 /* disable wptr polling */
4520 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
4521 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
4522 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
4523
4524 mqd->cp_hqd_eop_base_addr_lo =
4525 RREG32(mmCP_HQD_EOP_BASE_ADDR);
4526 mqd->cp_hqd_eop_base_addr_hi =
4527 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
4528
4529 /* enable doorbell? */
4530 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4531 if (use_doorbell) {
4532 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4533 } else {
4534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
4535 }
4536 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
4537 mqd->cp_hqd_pq_doorbell_control = tmp;
4538
4539 /* disable the queue if it's active */
4540 mqd->cp_hqd_dequeue_request = 0;
4541 mqd->cp_hqd_pq_rptr = 0;
4542 mqd->cp_hqd_pq_wptr= 0;
4543 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
4544 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
4545 for (j = 0; j < adev->usec_timeout; j++) {
4546 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
4547 break;
4548 udelay(1);
4549 }
4550 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
4551 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
4552 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
4553 }
4554
4555 /* set the pointer to the MQD */
4556 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
4557 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
4558 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
4559 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
4560
4561 /* set MQD vmid to 0 */
4562 tmp = RREG32(mmCP_MQD_CONTROL);
4563 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4564 WREG32(mmCP_MQD_CONTROL, tmp);
4565 mqd->cp_mqd_control = tmp;
4566
4567 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4568 hqd_gpu_addr = ring->gpu_addr >> 8;
4569 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4570 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4571 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
4572 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
4573
4574 /* set up the HQD, this is similar to CP_RB0_CNTL */
4575 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4576 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4577 (order_base_2(ring->ring_size / 4) - 1));
4578 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4579 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4580#ifdef __BIG_ENDIAN
4581 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4582#endif
4583 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4584 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4585 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4586 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4587 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
4588 mqd->cp_hqd_pq_control = tmp;
4589
4590 /* set the wb address wether it's enabled or not */
4591 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4592 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4593 mqd->cp_hqd_pq_rptr_report_addr_hi =
4594 upper_32_bits(wb_gpu_addr) & 0xffff;
4595 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
4596 mqd->cp_hqd_pq_rptr_report_addr_lo);
4597 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
4598 mqd->cp_hqd_pq_rptr_report_addr_hi);
4599
4600 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4601 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4602 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4603 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4604 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
4605 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
4606 mqd->cp_hqd_pq_wptr_poll_addr_hi);
4607
4608 /* enable the doorbell if requested */
4609 if (use_doorbell) {
bddf8026 4610 if ((adev->asic_type == CHIP_CARRIZO) ||
e3c7656c 4611 (adev->asic_type == CHIP_FIJI) ||
68182d90
FC		 4612 (adev->asic_type == CHIP_STONEY) ||
4613 (adev->asic_type == CHIP_BAFFIN) ||
4614 (adev->asic_type == CHIP_ELLESMERE)) {
aaa36a97
AD		 4615 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
4616 AMDGPU_DOORBELL_KIQ << 2);
4617 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
b8826b0c 4618 AMDGPU_DOORBELL_MEC_RING7 << 2);
aaa36a97
AD		 4619 }
4620 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4621 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4622 DOORBELL_OFFSET, ring->doorbell_index);
4623 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4624 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
4625 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
4626 mqd->cp_hqd_pq_doorbell_control = tmp;
4627
4628 } else {
4629 mqd->cp_hqd_pq_doorbell_control = 0;
4630 }
4631 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
4632 mqd->cp_hqd_pq_doorbell_control);
4633
845253e7
SJ		 4634 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4635 ring->wptr = 0;
4636 mqd->cp_hqd_pq_wptr = ring->wptr;
4637 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
4638 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4639
aaa36a97
AD		 4640 /* set the vmid for the queue */
4641 mqd->cp_hqd_vmid = 0;
4642 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
4643
4644 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4645 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4646 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
4647 mqd->cp_hqd_persistent_state = tmp;
68182d90
FC		 4648 if (adev->asic_type == CHIP_STONEY ||
4649 adev->asic_type == CHIP_BAFFIN ||
4650 adev->asic_type == CHIP_ELLESMERE) {
3b55ddad
FC		 4651 tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
4652 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
4653 WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
4654 }
aaa36a97
AD		 4655
4656 /* activate the queue */
4657 mqd->cp_hqd_active = 1;
4658 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
4659
4660 vi_srbm_select(adev, 0, 0, 0, 0);
4661 mutex_unlock(&adev->srbm_mutex);
4662
4663 amdgpu_bo_kunmap(ring->mqd_obj);
4664 amdgpu_bo_unreserve(ring->mqd_obj);
4665 }
4666
4667 if (use_doorbell) {
4668 tmp = RREG32(mmCP_PQ_STATUS);
4669 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4670 WREG32(mmCP_PQ_STATUS, tmp);
4671 }
4672
6e9821b2 4673 gfx_v8_0_cp_compute_enable(adev, true);
aaa36a97
AD		 4674
4675 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4676 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4677
4678 ring->ready = true;
4679 r = amdgpu_ring_test_ring(ring);
4680 if (r)
4681 ring->ready = false;
4682 }
4683
4684 return 0;
4685}
4686
4687static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4688{
4689 int r;
4690
e3c7656c 4691 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 4692 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4693
e61710c5 4694 if (!adev->pp_enabled) {
ba5c2a87
RZ		 4695 if (!adev->firmware.smu_load) {
4696 /* legacy firmware loading */
4697 r = gfx_v8_0_cp_gfx_load_microcode(adev);
4698 if (r)
4699 return r;
aaa36a97 4700
ba5c2a87
RZ		 4701 r = gfx_v8_0_cp_compute_load_microcode(adev);
4702 if (r)
4703 return r;
4704 } else {
4705 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4706 AMDGPU_UCODE_ID_CP_CE);
4707 if (r)
4708 return -EINVAL;
4709
4710 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4711 AMDGPU_UCODE_ID_CP_PFP);
4712 if (r)
4713 return -EINVAL;
4714
4715 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4716 AMDGPU_UCODE_ID_CP_ME);
4717 if (r)
4718 return -EINVAL;
4719
951e0962
AD		 4720 if (adev->asic_type == CHIP_TOPAZ) {
4721 r = gfx_v8_0_cp_compute_load_microcode(adev);
4722 if (r)
4723 return r;
4724 } else {
4725 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4726 AMDGPU_UCODE_ID_CP_MEC1);
4727 if (r)
4728 return -EINVAL;
4729 }
ba5c2a87 4730 }
aaa36a97
AD		 4731 }
4732
4733 r = gfx_v8_0_cp_gfx_resume(adev);
4734 if (r)
4735 return r;
4736
4737 r = gfx_v8_0_cp_compute_resume(adev);
4738 if (r)
4739 return r;
4740
4741 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4742
4743 return 0;
4744}
4745
4746static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4747{
4748 gfx_v8_0_cp_gfx_enable(adev, enable);
4749 gfx_v8_0_cp_compute_enable(adev, enable);
4750}
4751
5fc3aeeb 4752static int gfx_v8_0_hw_init(void *handle)
aaa36a97
AD		 4753{
4754 int r;
5fc3aeeb 4755 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 4756
4757 gfx_v8_0_init_golden_registers(adev);
4758
4759 gfx_v8_0_gpu_init(adev);
4760
4761 r = gfx_v8_0_rlc_resume(adev);
4762 if (r)
4763 return r;
4764
4765 r = gfx_v8_0_cp_resume(adev);
4766 if (r)
4767 return r;
4768
4769 return r;
4770}
4771
5fc3aeeb 4772static int gfx_v8_0_hw_fini(void *handle)
aaa36a97 4773{
5fc3aeeb 4774 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4775
1d22a454
AD		 4776 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4777 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
aaa36a97
AD		 4778 gfx_v8_0_cp_enable(adev, false);
4779 gfx_v8_0_rlc_stop(adev);
4780 gfx_v8_0_cp_compute_fini(adev);
4781
62a86fc2
EH		 4782 amdgpu_set_powergating_state(adev,
4783 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE);
4784
aaa36a97
AD		 4785 return 0;
4786}
4787
5fc3aeeb 4788static int gfx_v8_0_suspend(void *handle)
aaa36a97 4789{
5fc3aeeb 4790 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4791
aaa36a97
AD		 4792 return gfx_v8_0_hw_fini(adev);
4793}
4794
5fc3aeeb 4795static int gfx_v8_0_resume(void *handle)
aaa36a97 4796{
5fc3aeeb 4797 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4798
aaa36a97
AD		 4799 return gfx_v8_0_hw_init(adev);
4800}
4801
5fc3aeeb 4802static bool gfx_v8_0_is_idle(void *handle)
aaa36a97 4803{
5fc3aeeb 4804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4805
aaa36a97
AD		 4806 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
4807 return false;
4808 else
4809 return true;
4810}
4811
5fc3aeeb 4812static int gfx_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 4813{
4814 unsigned i;
4815 u32 tmp;
5fc3aeeb 4816 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 4817
4818 for (i = 0; i < adev->usec_timeout; i++) {
4819 /* read MC_STATUS */
4820 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4821
4822 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
4823 return 0;
4824 udelay(1);
4825 }
4826 return -ETIMEDOUT;
4827}
4828
5fc3aeeb 4829static void gfx_v8_0_print_status(void *handle)
aaa36a97
AD		 4830{
4831 int i;
5fc3aeeb 4832 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 4833
4834 dev_info(adev->dev, "GFX 8.x registers\n");
4835 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
4836 RREG32(mmGRBM_STATUS));
4837 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
4838 RREG32(mmGRBM_STATUS2));
4839 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
4840 RREG32(mmGRBM_STATUS_SE0));
4841 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
4842 RREG32(mmGRBM_STATUS_SE1));
4843 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
4844 RREG32(mmGRBM_STATUS_SE2));
4845 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
4846 RREG32(mmGRBM_STATUS_SE3));
4847 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
4848 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
4849 RREG32(mmCP_STALLED_STAT1));
4850 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
4851 RREG32(mmCP_STALLED_STAT2));
4852 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
4853 RREG32(mmCP_STALLED_STAT3));
4854 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
4855 RREG32(mmCP_CPF_BUSY_STAT));
4856 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
4857 RREG32(mmCP_CPF_STALLED_STAT1));
4858 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
4859 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
4860 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
4861 RREG32(mmCP_CPC_STALLED_STAT1));
4862 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
4863
4864 for (i = 0; i < 32; i++) {
4865 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
4866 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
4867 }
4868 for (i = 0; i < 16; i++) {
4869 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
4870 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
4871 }
4872 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4873 dev_info(adev->dev, " se: %d\n", i);
4874 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
4875 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
4876 RREG32(mmPA_SC_RASTER_CONFIG));
4877 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
4878 RREG32(mmPA_SC_RASTER_CONFIG_1));
4879 }
4880 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4881
4882 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
4883 RREG32(mmGB_ADDR_CONFIG));
4884 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
4885 RREG32(mmHDP_ADDR_CONFIG));
4886 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
4887 RREG32(mmDMIF_ADDR_CALC));
aaa36a97
AD		 4888
4889 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
4890 RREG32(mmCP_MEQ_THRESHOLDS));
4891 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
4892 RREG32(mmSX_DEBUG_1));
4893 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
4894 RREG32(mmTA_CNTL_AUX));
4895 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
4896 RREG32(mmSPI_CONFIG_CNTL));
4897 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
4898 RREG32(mmSQ_CONFIG));
4899 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
4900 RREG32(mmDB_DEBUG));
4901 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
4902 RREG32(mmDB_DEBUG2));
4903 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
4904 RREG32(mmDB_DEBUG3));
4905 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
4906 RREG32(mmCB_HW_CONTROL));
4907 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
4908 RREG32(mmSPI_CONFIG_CNTL_1));
4909 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
4910 RREG32(mmPA_SC_FIFO_SIZE));
4911 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
4912 RREG32(mmVGT_NUM_INSTANCES));
4913 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
4914 RREG32(mmCP_PERFMON_CNTL));
4915 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
4916 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
4917 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
4918 RREG32(mmVGT_CACHE_INVALIDATION));
4919 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
4920 RREG32(mmVGT_GS_VERTEX_REUSE));
4921 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
4922 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
4923 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
4924 RREG32(mmPA_CL_ENHANCE));
4925 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
4926 RREG32(mmPA_SC_ENHANCE));
4927
4928 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
4929 RREG32(mmCP_ME_CNTL));
4930 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
4931 RREG32(mmCP_MAX_CONTEXT));
4932 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
4933 RREG32(mmCP_ENDIAN_SWAP));
4934 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
4935 RREG32(mmCP_DEVICE_ID));
4936
4937 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
4938 RREG32(mmCP_SEM_WAIT_TIMER));
4939
4940 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
4941 RREG32(mmCP_RB_WPTR_DELAY));
4942 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
4943 RREG32(mmCP_RB_VMID));
4944 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4945 RREG32(mmCP_RB0_CNTL));
4946 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
4947 RREG32(mmCP_RB0_WPTR));
4948 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
4949 RREG32(mmCP_RB0_RPTR_ADDR));
4950 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
4951 RREG32(mmCP_RB0_RPTR_ADDR_HI));
4952 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4953 RREG32(mmCP_RB0_CNTL));
4954 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
4955 RREG32(mmCP_RB0_BASE));
4956 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
4957 RREG32(mmCP_RB0_BASE_HI));
4958 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
4959 RREG32(mmCP_MEC_CNTL));
4960 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
4961 RREG32(mmCP_CPF_DEBUG));
4962
4963 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
4964 RREG32(mmSCRATCH_ADDR));
4965 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
4966 RREG32(mmSCRATCH_UMSK));
4967
4968 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
4969 RREG32(mmCP_INT_CNTL_RING0));
4970 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4971 RREG32(mmRLC_LB_CNTL));
4972 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
4973 RREG32(mmRLC_CNTL));
4974 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
4975 RREG32(mmRLC_CGCG_CGLS_CTRL));
4976 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
4977 RREG32(mmRLC_LB_CNTR_INIT));
4978 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
4979 RREG32(mmRLC_LB_CNTR_MAX));
4980 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
4981 RREG32(mmRLC_LB_INIT_CU_MASK));
4982 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
4983 RREG32(mmRLC_LB_PARAMS));
4984 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4985 RREG32(mmRLC_LB_CNTL));
4986 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
4987 RREG32(mmRLC_MC_CNTL));
4988 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
4989 RREG32(mmRLC_UCODE_CNTL));
4990
4991 mutex_lock(&adev->srbm_mutex);
4992 for (i = 0; i < 16; i++) {
4993 vi_srbm_select(adev, 0, 0, 0, i);
4994 dev_info(adev->dev, " VM %d:\n", i);
4995 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
4996 RREG32(mmSH_MEM_CONFIG));
4997 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
4998 RREG32(mmSH_MEM_APE1_BASE));
4999 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
5000 RREG32(mmSH_MEM_APE1_LIMIT));
5001 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
5002 RREG32(mmSH_MEM_BASES));
5003 }
5004 vi_srbm_select(adev, 0, 0, 0, 0);
5005 mutex_unlock(&adev->srbm_mutex);
5006}
5007
5fc3aeeb 5008static int gfx_v8_0_soft_reset(void *handle)
aaa36a97
AD		 5009{
5010 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5011 u32 tmp;
5fc3aeeb 5012 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 5013
5014 /* GRBM_STATUS */
5015 tmp = RREG32(mmGRBM_STATUS);
5016 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
5017 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
5018 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
5019 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
5020 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
5021 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
5022 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5023 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
5024 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5025 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
5026 }
5027
5028 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
5029 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5030 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
5031 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5032 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
5033 }
5034
5035 /* GRBM_STATUS2 */
5036 tmp = RREG32(mmGRBM_STATUS2);
5037 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
5038 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
5039 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5040
5041 /* SRBM_STATUS */
5042 tmp = RREG32(mmSRBM_STATUS);
5043 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
5044 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5045 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
5046
5047 if (grbm_soft_reset || srbm_soft_reset) {
5fc3aeeb 5048 gfx_v8_0_print_status((void *)adev);
aaa36a97
AD		 5049 /* stop the rlc */
5050 gfx_v8_0_rlc_stop(adev);
5051
5052 /* Disable GFX parsing/prefetching */
5053 gfx_v8_0_cp_gfx_enable(adev, false);
5054
5055 /* Disable MEC parsing/prefetching */
7776a693
AD		 5056 gfx_v8_0_cp_compute_enable(adev, false);
5057
5058 if (grbm_soft_reset || srbm_soft_reset) {
5059 tmp = RREG32(mmGMCON_DEBUG);
5060 tmp = REG_SET_FIELD(tmp,
5061 GMCON_DEBUG, GFX_STALL, 1);
5062 tmp = REG_SET_FIELD(tmp,
5063 GMCON_DEBUG, GFX_CLEAR, 1);
5064 WREG32(mmGMCON_DEBUG, tmp);
5065
5066 udelay(50);
5067 }
aaa36a97
AD		 5068
5069 if (grbm_soft_reset) {
5070 tmp = RREG32(mmGRBM_SOFT_RESET);
5071 tmp |= grbm_soft_reset;
5072 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5073 WREG32(mmGRBM_SOFT_RESET, tmp);
5074 tmp = RREG32(mmGRBM_SOFT_RESET);
5075
5076 udelay(50);
5077
5078 tmp &= ~grbm_soft_reset;
5079 WREG32(mmGRBM_SOFT_RESET, tmp);
5080 tmp = RREG32(mmGRBM_SOFT_RESET);
5081 }
5082
5083 if (srbm_soft_reset) {
5084 tmp = RREG32(mmSRBM_SOFT_RESET);
5085 tmp |= srbm_soft_reset;
5086 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5087 WREG32(mmSRBM_SOFT_RESET, tmp);
5088 tmp = RREG32(mmSRBM_SOFT_RESET);
5089
5090 udelay(50);
5091
5092 tmp &= ~srbm_soft_reset;
5093 WREG32(mmSRBM_SOFT_RESET, tmp);
5094 tmp = RREG32(mmSRBM_SOFT_RESET);
5095 }
7776a693
AD		 5096
5097 if (grbm_soft_reset || srbm_soft_reset) {
5098 tmp = RREG32(mmGMCON_DEBUG);
5099 tmp = REG_SET_FIELD(tmp,
5100 GMCON_DEBUG, GFX_STALL, 0);
5101 tmp = REG_SET_FIELD(tmp,
5102 GMCON_DEBUG, GFX_CLEAR, 0);
5103 WREG32(mmGMCON_DEBUG, tmp);
5104 }
5105
aaa36a97
AD		 5106 /* Wait a little for things to settle down */
5107 udelay(50);
5fc3aeeb 5108 gfx_v8_0_print_status((void *)adev);
aaa36a97
AD		 5109 }
5110 return 0;
5111}
5112
5113/**
5114 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5115 *
5116 * @adev: amdgpu_device pointer
5117 *
5118 * Fetches a GPU clock counter snapshot.
5119 * Returns the 64 bit clock counter snapshot.
5120 */
5121uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
5122{
5123 uint64_t clock;
5124
5125 mutex_lock(&adev->gfx.gpu_clock_mutex);
5126 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5127 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5128 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5129 mutex_unlock(&adev->gfx.gpu_clock_mutex);
5130 return clock;
5131}
5132
5133static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5134 uint32_t vmid,
5135 uint32_t gds_base, uint32_t gds_size,
5136 uint32_t gws_base, uint32_t gws_size,
5137 uint32_t oa_base, uint32_t oa_size)
5138{
5139 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
5140 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
5141
5142 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
5143 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
5144
5145 oa_base = oa_base >> AMDGPU_OA_SHIFT;
5146 oa_size = oa_size >> AMDGPU_OA_SHIFT;
5147
5148 /* GDS Base */
5149 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5150 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5151 WRITE_DATA_DST_SEL(0)));
5152 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5153 amdgpu_ring_write(ring, 0);
5154 amdgpu_ring_write(ring, gds_base);
5155
5156 /* GDS Size */
5157 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5158 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5159 WRITE_DATA_DST_SEL(0)));
5160 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5161 amdgpu_ring_write(ring, 0);
5162 amdgpu_ring_write(ring, gds_size);
5163
5164 /* GWS */
5165 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5166 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5167 WRITE_DATA_DST_SEL(0)));
5168 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5169 amdgpu_ring_write(ring, 0);
5170 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5171
5172 /* OA */
5173 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5174 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5175 WRITE_DATA_DST_SEL(0)));
5176 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5177 amdgpu_ring_write(ring, 0);
5178 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5179}
5180
5fc3aeeb 5181static int gfx_v8_0_early_init(void *handle)
aaa36a97 5182{
5fc3aeeb 5183 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 5184
5185 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5186 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
5187 gfx_v8_0_set_ring_funcs(adev);
5188 gfx_v8_0_set_irq_funcs(adev);
5189 gfx_v8_0_set_gds_init(adev);
dbff57bc 5190 gfx_v8_0_set_rlc_funcs(adev);
aaa36a97
AD		 5191
5192 return 0;
5193}
5194
ccba7691
AD		 5195static int gfx_v8_0_late_init(void *handle)
5196{
5197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5198 int r;
5199
1d22a454
AD		 5200 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5201 if (r)
5202 return r;
5203
5204 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5205 if (r)
5206 return r;
5207
ccba7691
AD		 5208 /* requires IBs so do in late init after IB pool is initialized */
5209 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5210 if (r)
5211 return r;
5212
62a86fc2
EH		 5213 amdgpu_set_powergating_state(adev,
5214 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE);
5215
ccba7691
AD		 5216 return 0;
5217}
5218
62a86fc2
EH		 5219static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5220 bool enable)
5221{
5222 uint32_t data, temp;
5223
5224 /* Send msg to SMU via Powerplay */
5225 amdgpu_set_powergating_state(adev,
5226 AMD_IP_BLOCK_TYPE_SMC,
5227 enable ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
5228
5229 if (enable) {
5230 /* Enable static MGPG */
5231 temp = data = RREG32(mmRLC_PG_CNTL);
5232 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
5233
5234 if (temp != data)
5235 WREG32(mmRLC_PG_CNTL, data);
5236 } else {
5237 temp = data = RREG32(mmRLC_PG_CNTL);
5238 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
5239
5240 if (temp != data)
5241 WREG32(mmRLC_PG_CNTL, data);
5242 }
5243}
5244
5245static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5246 bool enable)
5247{
5248 uint32_t data, temp;
5249
5250 if (enable) {
5251 /* Enable dynamic MGPG */
5252 temp = data = RREG32(mmRLC_PG_CNTL);
5253 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
5254
5255 if (temp != data)
5256 WREG32(mmRLC_PG_CNTL, data);
5257 } else {
5258 temp = data = RREG32(mmRLC_PG_CNTL);
5259 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
5260
5261 if (temp != data)
5262 WREG32(mmRLC_PG_CNTL, data);
5263 }
5264}
5265
5266static void baffin_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
5267 bool enable)
5268{
5269 uint32_t data, temp;
5270
5271 if (enable) {
5272 /* Enable quick PG */
5273 temp = data = RREG32(mmRLC_PG_CNTL);
5274 data |= 0x100000;
5275
5276 if (temp != data)
5277 WREG32(mmRLC_PG_CNTL, data);
5278 } else {
5279 temp = data = RREG32(mmRLC_PG_CNTL);
5280 data &= ~0x100000;
5281
5282 if (temp != data)
5283 WREG32(mmRLC_PG_CNTL, data);
5284 }
5285}
5286
5fc3aeeb 5287static int gfx_v8_0_set_powergating_state(void *handle,
5288 enum amd_powergating_state state)
aaa36a97 5289{
62a86fc2
EH		 5290 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5291
5292 if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5293 return 0;
5294
5295 switch (adev->asic_type) {
5296 case CHIP_BAFFIN:
5297 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG)
5298 baffin_enable_gfx_static_mg_power_gating(adev,
5299 state == AMD_PG_STATE_GATE ? true : false);
5300 else if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG)
5301 baffin_enable_gfx_dynamic_mg_power_gating(adev,
5302 state == AMD_PG_STATE_GATE ? true : false);
5303 else
5304 baffin_enable_gfx_quick_mg_power_gating(adev,
5305 state == AMD_PG_STATE_GATE ? true : false);
5306 break;
5307 default:
5308 break;
5309 }
5310
aaa36a97
AD		 5311 return 0;
5312}
5313
79deaaf4 5314static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
14698b6c 5315 uint32_t reg_addr, uint32_t cmd)
6e378858
EH		 5316{
5317 uint32_t data;
5318
5319 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5320
5321 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5322 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5323
5324 data = RREG32(mmRLC_SERDES_WR_CTRL);
146f256f
AD		 5325 if (adev->asic_type == CHIP_STONEY)
5326 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
6e378858
EH		 5327 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5328 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5329 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5330 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5331 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5332 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5333 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
6e378858 5334 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
146f256f
AD		 5335 else
5336 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5337 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5338 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5339 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5340 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5341 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5342 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5343 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5344 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5345 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5346 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
6e378858 5347 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
146f256f
AD		 5348 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5349 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5350 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
6e378858
EH		 5351
5352 WREG32(mmRLC_SERDES_WR_CTRL, data);
5353}
5354
dbff57bc
AD		 5355#define MSG_ENTER_RLC_SAFE_MODE 1
5356#define MSG_EXIT_RLC_SAFE_MODE 0
5357
5358#define RLC_GPR_REG2__REQ_MASK 0x00000001
5359#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5360#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5361
5362static void cz_enter_rlc_safe_mode(struct amdgpu_device *adev)
5363{
5364 u32 data = 0;
5365 unsigned i;
5366
5367 data = RREG32(mmRLC_CNTL);
5368 if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
5369 return;
5370
5371 if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
5372 (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
5373 AMD_PG_SUPPORT_GFX_DMG))) {
5374 data |= RLC_GPR_REG2__REQ_MASK;
5375 data &= ~RLC_GPR_REG2__MESSAGE_MASK;
5376 data |= (MSG_ENTER_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
5377 WREG32(mmRLC_GPR_REG2, data);
5378
5379 for (i = 0; i < adev->usec_timeout; i++) {
5380 if ((RREG32(mmRLC_GPM_STAT) &
5381 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5382 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5383 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5384 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5385 break;
5386 udelay(1);
5387 }
5388
5389 for (i = 0; i < adev->usec_timeout; i++) {
5390 if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)
5391 break;
5392 udelay(1);
5393 }
5394 adev->gfx.rlc.in_safe_mode = true;
5395 }
5396}
5397
5398static void cz_exit_rlc_safe_mode(struct amdgpu_device *adev)
5399{
5400 u32 data;
5401 unsigned i;
5402
5403 data = RREG32(mmRLC_CNTL);
5404 if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
5405 return;
5406
5407 if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
5408 (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
5409 AMD_PG_SUPPORT_GFX_DMG))) {
5410 data |= RLC_GPR_REG2__REQ_MASK;
5411 data &= ~RLC_GPR_REG2__MESSAGE_MASK;
5412 data |= (MSG_EXIT_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
5413 WREG32(mmRLC_GPR_REG2, data);
5414 adev->gfx.rlc.in_safe_mode = false;
5415 }
5416
5417 for (i = 0; i < adev->usec_timeout; i++) {
5418 if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)
5419 break;
5420 udelay(1);
5421 }
5422}
5423
5424static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev)
5425{
5426 u32 data;
5427 unsigned i;
5428
5429 data = RREG32(mmRLC_CNTL);
5430 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
5431 return;
5432
5433 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
5434 data |= RLC_SAFE_MODE__CMD_MASK;
5435 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5436 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5437 WREG32(mmRLC_SAFE_MODE, data);
5438
5439 for (i = 0; i < adev->usec_timeout; i++) {
5440 if ((RREG32(mmRLC_GPM_STAT) &
5441 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5442 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5443 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5444 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5445 break;
5446 udelay(1);
5447 }
5448
5449 for (i = 0; i < adev->usec_timeout; i++) {
5450 if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)
5451 break;
5452 udelay(1);
5453 }
5454 adev->gfx.rlc.in_safe_mode = true;
5455 }
5456}
5457
5458static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev)
5459{
5460 u32 data = 0;
5461 unsigned i;
5462
5463 data = RREG32(mmRLC_CNTL);
5464 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
5465 return;
5466
5467 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
5468 if (adev->gfx.rlc.in_safe_mode) {
5469 data |= RLC_SAFE_MODE__CMD_MASK;
5470 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5471 WREG32(mmRLC_SAFE_MODE, data);
5472 adev->gfx.rlc.in_safe_mode = false;
5473 }
5474 }
5475
5476 for (i = 0; i < adev->usec_timeout; i++) {
5477 if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)
5478 break;
5479 udelay(1);
5480 }
5481}
5482
5483static void gfx_v8_0_nop_enter_rlc_safe_mode(struct amdgpu_device *adev)
5484{
5485 adev->gfx.rlc.in_safe_mode = true;
5486}
5487
5488static void gfx_v8_0_nop_exit_rlc_safe_mode(struct amdgpu_device *adev)
5489{
5490 adev->gfx.rlc.in_safe_mode = false;
5491}
5492
5493static const struct amdgpu_rlc_funcs cz_rlc_funcs = {
5494 .enter_safe_mode = cz_enter_rlc_safe_mode,
5495 .exit_safe_mode = cz_exit_rlc_safe_mode
5496};
5497
5498static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5499 .enter_safe_mode = iceland_enter_rlc_safe_mode,
5500 .exit_safe_mode = iceland_exit_rlc_safe_mode
5501};
5502
5503static const struct amdgpu_rlc_funcs gfx_v8_0_nop_rlc_funcs = {
5504 .enter_safe_mode = gfx_v8_0_nop_enter_rlc_safe_mode,
5505 .exit_safe_mode = gfx_v8_0_nop_exit_rlc_safe_mode
5506};
5507
5508static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5509 bool enable)
6e378858
EH		 5510{
5511 uint32_t temp, data;
5512
dbff57bc
AD		 5513 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5514
6e378858 5515 /* It is disabled by HW by default */
14698b6c
AD		 5516 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5517 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5518 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5519 /* 1 - RLC memory Light sleep */
5520 temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
5521 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5522 if (temp != data)
5523 WREG32(mmRLC_MEM_SLP_CNTL, data);
5524 }
6e378858 5525
14698b6c
AD		 5526 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5527 /* 2 - CP memory Light sleep */
5528 temp = data = RREG32(mmCP_MEM_SLP_CNTL);
5529 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5530 if (temp != data)
5531 WREG32(mmCP_MEM_SLP_CNTL, data);
5532 }
5533 }
6e378858
EH		 5534
5535 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5536 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
dbff57bc
AD		 5537 if (adev->flags & AMD_IS_APU)
5538 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5539 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5540 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5541 else
5542 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5543 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5544 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5545 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
6e378858
EH		 5546
5547 if (temp != data)
5548 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5549
5550 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5551 gfx_v8_0_wait_for_rlc_serdes(adev);
5552
5553 /* 5 - clear mgcg override */
79deaaf4 5554 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
6e378858 5555
14698b6c
AD		 5556 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5557 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5558 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5559 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5560 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5561 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5562 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5563 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5564 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5565 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5566 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5567 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5568 if (temp != data)
5569 WREG32(mmCGTS_SM_CTRL_REG, data);
5570 }
6e378858
EH		 5571 udelay(50);
5572
5573 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5574 gfx_v8_0_wait_for_rlc_serdes(adev);
5575 } else {
5576 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5577 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5578 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5579 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5580 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5581 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5582 if (temp != data)
5583 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5584
5585 /* 2 - disable MGLS in RLC */
5586 data = RREG32(mmRLC_MEM_SLP_CNTL);
5587 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5588 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5589 WREG32(mmRLC_MEM_SLP_CNTL, data);
5590 }
5591
5592 /* 3 - disable MGLS in CP */
5593 data = RREG32(mmCP_MEM_SLP_CNTL);
5594 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5595 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5596 WREG32(mmCP_MEM_SLP_CNTL, data);
5597 }
5598
5599 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5600 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5601 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5602 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5603 if (temp != data)
5604 WREG32(mmCGTS_SM_CTRL_REG, data);
5605
5606 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5607 gfx_v8_0_wait_for_rlc_serdes(adev);
5608
5609 /* 6 - set mgcg override */
79deaaf4 5610 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
6e378858
EH		 5611
5612 udelay(50);
5613
5614 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5615 gfx_v8_0_wait_for_rlc_serdes(adev);
5616 }
dbff57bc
AD		 5617
5618 adev->gfx.rlc.funcs->exit_safe_mode(adev);
6e378858
EH		 5619}
5620
dbff57bc
AD		 5621static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5622 bool enable)
6e378858
EH		 5623{
5624 uint32_t temp, temp1, data, data1;
5625
5626 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5627
dbff57bc
AD		 5628 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5629
14698b6c 5630 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
6e378858
EH		 5631 /* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
5632 * Cmp_busy/GFX_Idle interrupts
5633 */
5634 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5635
5636 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5637 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5638 if (temp1 != data1)
5639 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5640
5641 /* 2 wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5642 gfx_v8_0_wait_for_rlc_serdes(adev);
5643
5644 /* 3 - clear cgcg override */
79deaaf4 5645 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
6e378858
EH		 5646
5647 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5648 gfx_v8_0_wait_for_rlc_serdes(adev);
5649
5650 /* 4 - write cmd to set CGLS */
79deaaf4 5651 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
6e378858
EH		 5652
5653 /* 5 - enable cgcg */
5654 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5655
14698b6c
AD		 5656 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5657 /* enable cgls*/
5658 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
6e378858 5659
14698b6c
AD		 5660 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5661 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
6e378858 5662
14698b6c
AD		 5663 if (temp1 != data1)
5664 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5665 } else {
5666 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5667 }
6e378858
EH		 5668
5669 if (temp != data)
5670 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5671 } else {
5672 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5673 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5674
5675 /* TEST CGCG */
5676 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5677 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5678 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5679 if (temp1 != data1)
5680 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5681
5682 /* read gfx register to wake up cgcg */
5683 RREG32(mmCB_CGTT_SCLK_CTRL);
5684 RREG32(mmCB_CGTT_SCLK_CTRL);
5685 RREG32(mmCB_CGTT_SCLK_CTRL);
5686 RREG32(mmCB_CGTT_SCLK_CTRL);
5687
5688 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5689 gfx_v8_0_wait_for_rlc_serdes(adev);
5690
5691 /* write cmd to Set CGCG Overrride */
79deaaf4 5692 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
6e378858
EH		 5693
5694 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5695 gfx_v8_0_wait_for_rlc_serdes(adev);
5696
5697 /* write cmd to Clear CGLS */
79deaaf4 5698 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
6e378858
EH		 5699
5700 /* disable cgcg, cgls should be disabled too. */
5701 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
14698b6c 5702 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
6e378858
EH		 5703 if (temp != data)
5704 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5705 }
dbff57bc
AD		 5706
5707 adev->gfx.rlc.funcs->exit_safe_mode(adev);
6e378858 5708}
dbff57bc
AD		 5709static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5710 bool enable)
6e378858
EH		 5711{
5712 if (enable) {
5713 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5714 * === MGCG + MGLS + TS(CG/LS) ===
5715 */
dbff57bc
AD		 5716 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5717 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
6e378858
EH		 5718 } else {
5719 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5720 * === CGCG + CGLS ===
5721 */
dbff57bc
AD		 5722 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5723 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
6e378858
EH		 5724 }
5725 return 0;
5726}
5727
5fc3aeeb 5728static int gfx_v8_0_set_clockgating_state(void *handle,
5729 enum amd_clockgating_state state)
aaa36a97 5730{
6e378858
EH		 5731 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5732
5733 switch (adev->asic_type) {
5734 case CHIP_FIJI:
dbff57bc
AD		 5735 case CHIP_CARRIZO:
5736 case CHIP_STONEY:
5737 gfx_v8_0_update_gfx_clock_gating(adev,
5738 state == AMD_CG_STATE_GATE ? true : false);
6e378858
EH		 5739 break;
5740 default:
5741 break;
5742 }
aaa36a97
AD		 5743 return 0;
5744}
5745
5746static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5747{
5748 u32 rptr;
5749
5750 rptr = ring->adev->wb.wb[ring->rptr_offs];
5751
5752 return rptr;
5753}
5754
5755static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5756{
5757 struct amdgpu_device *adev = ring->adev;
5758 u32 wptr;
5759
5760 if (ring->use_doorbell)
5761 /* XXX check if swapping is necessary on BE */
5762 wptr = ring->adev->wb.wb[ring->wptr_offs];
5763 else
5764 wptr = RREG32(mmCP_RB0_WPTR);
5765
5766 return wptr;
5767}
5768
5769static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5770{
5771 struct amdgpu_device *adev = ring->adev;
5772
5773 if (ring->use_doorbell) {
5774 /* XXX check if swapping is necessary on BE */
5775 adev->wb.wb[ring->wptr_offs] = ring->wptr;
5776 WDOORBELL32(ring->doorbell_index, ring->wptr);
5777 } else {
5778 WREG32(mmCP_RB0_WPTR, ring->wptr);
5779 (void)RREG32(mmCP_RB0_WPTR);
5780 }
5781}
5782
d2edb07b 5783static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD		 5784{
5785 u32 ref_and_mask, reg_mem_engine;
5786
5787 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
5788 switch (ring->me) {
5789 case 1:
5790 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
5791 break;
5792 case 2:
5793 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
5794 break;
5795 default:
5796 return;
5797 }
5798 reg_mem_engine = 0;
5799 } else {
5800 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
5801 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
5802 }
5803
5804 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5805 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
5806 WAIT_REG_MEM_FUNCTION(3) | /* == */
5807 reg_mem_engine));
5808 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
5809 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
5810 amdgpu_ring_write(ring, ref_and_mask);
5811 amdgpu_ring_write(ring, ref_and_mask);
5812 amdgpu_ring_write(ring, 0x20); /* poll interval */
5813}
5814
d35db561
CZ		 5815static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
5816{
5817 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5818 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5819 WRITE_DATA_DST_SEL(0) |
5820 WR_CONFIRM));
5821 amdgpu_ring_write(ring, mmHDP_DEBUG0);
5822 amdgpu_ring_write(ring, 0);
5823 amdgpu_ring_write(ring, 1);
5824
5825}
5826
93323131 5827static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
aaa36a97
AD		 5828 struct amdgpu_ib *ib)
5829{
3cb485f3 5830 bool need_ctx_switch = ring->current_ctx != ib->ctx;
aaa36a97
AD		 5831 u32 header, control = 0;
5832 u32 next_rptr = ring->wptr + 5;
aa2bdb24
JZ		 5833
5834 /* drop the CE preamble IB for the same context */
93323131 5835 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
aa2bdb24
JZ		 5836 return;
5837
93323131 5838 if (need_ctx_switch)
aaa36a97
AD		 5839 next_rptr += 2;
5840
5841 next_rptr += 4;
5842 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5843 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
5844 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
5845 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
5846 amdgpu_ring_write(ring, next_rptr);
5847
aaa36a97 5848 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
93323131 5849 if (need_ctx_switch) {
aaa36a97
AD		 5850 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5851 amdgpu_ring_write(ring, 0);
aaa36a97
AD		 5852 }
5853
de807f81 5854 if (ib->flags & AMDGPU_IB_FLAG_CE)
aaa36a97
AD		 5855 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
5856 else
5857 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5858
4ff37a83 5859 control |= ib->length_dw | (ib->vm_id << 24);
aaa36a97
AD		 5860
5861 amdgpu_ring_write(ring, header);
5862 amdgpu_ring_write(ring,
5863#ifdef __BIG_ENDIAN
5864 (2 << 0) |
5865#endif
5866 (ib->gpu_addr & 0xFFFFFFFC));
5867 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
5868 amdgpu_ring_write(ring, control);
5869}
5870
93323131 5871static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5872 struct amdgpu_ib *ib)
5873{
5874 u32 header, control = 0;
5875 u32 next_rptr = ring->wptr + 5;
5876
5877 control |= INDIRECT_BUFFER_VALID;
5878
5879 next_rptr += 4;
5880 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5881 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
5882 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
5883 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
5884 amdgpu_ring_write(ring, next_rptr);
5885
5886 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5887
4ff37a83 5888 control |= ib->length_dw | (ib->vm_id << 24);
93323131 5889
5890 amdgpu_ring_write(ring, header);
5891 amdgpu_ring_write(ring,
5892#ifdef __BIG_ENDIAN
5893 (2 << 0) |
5894#endif
5895 (ib->gpu_addr & 0xFFFFFFFC));
5896 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
5897 amdgpu_ring_write(ring, control);
5898}
5899
aaa36a97 5900static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 5901 u64 seq, unsigned flags)
aaa36a97 5902{
890ee23f
CZ		 5903 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5904 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5905
aaa36a97
AD		 5906 /* EVENT_WRITE_EOP - flush caches, send int */
5907 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
5908 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
5909 EOP_TC_ACTION_EN |
5910 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5911 EVENT_INDEX(5)));
5912 amdgpu_ring_write(ring, addr & 0xfffffffc);
90bea0ab 5913 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 5914 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 5915 amdgpu_ring_write(ring, lower_32_bits(seq));
5916 amdgpu_ring_write(ring, upper_32_bits(seq));
22c01cc4 5917
aaa36a97
AD		 5918}
5919
b8c7b39e 5920static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
aaa36a97
AD		 5921{
5922 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
5907a0d8 5923 uint32_t seq = ring->fence_drv.sync_seq;
22c01cc4
AA		 5924 uint64_t addr = ring->fence_drv.gpu_addr;
5925
5926 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5927 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
9cac5373
CZ		 5928 WAIT_REG_MEM_FUNCTION(3) | /* equal */
5929 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
22c01cc4
AA		 5930 amdgpu_ring_write(ring, addr & 0xfffffffc);
5931 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
5932 amdgpu_ring_write(ring, seq);
5933 amdgpu_ring_write(ring, 0xffffffff);
5934 amdgpu_ring_write(ring, 4); /* poll interval */
aaa36a97 5935
5c3422b0 5936 if (usepfp) {
5937 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
5938 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5939 amdgpu_ring_write(ring, 0);
5940 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5941 amdgpu_ring_write(ring, 0);
5942 }
b8c7b39e
CK		 5943}
5944
5945static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5946 unsigned vm_id, uint64_t pd_addr)
5947{
5948 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
5c3422b0 5949
aaa36a97
AD		 5950 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5951 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
20a85ff8
CK		 5952 WRITE_DATA_DST_SEL(0)) |
5953 WR_CONFIRM);
aaa36a97
AD		 5954 if (vm_id < 8) {
5955 amdgpu_ring_write(ring,
5956 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
5957 } else {
5958 amdgpu_ring_write(ring,
5959 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
5960 }
5961 amdgpu_ring_write(ring, 0);
5962 amdgpu_ring_write(ring, pd_addr >> 12);
5963
aaa36a97
AD		 5964 /* bits 0-15 are the VM contexts0-15 */
5965 /* invalidate the cache */
5966 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5967 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5968 WRITE_DATA_DST_SEL(0)));
5969 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
5970 amdgpu_ring_write(ring, 0);
5971 amdgpu_ring_write(ring, 1 << vm_id);
5972
5973 /* wait for the invalidate to complete */
5974 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5975 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
5976 WAIT_REG_MEM_FUNCTION(0) | /* always */
5977 WAIT_REG_MEM_ENGINE(0))); /* me */
5978 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
5979 amdgpu_ring_write(ring, 0);
5980 amdgpu_ring_write(ring, 0); /* ref */
5981 amdgpu_ring_write(ring, 0); /* mask */
5982 amdgpu_ring_write(ring, 0x20); /* poll interval */
5983
5984 /* compute doesn't have PFP */
5985 if (usepfp) {
5986 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5987 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5988 amdgpu_ring_write(ring, 0x0);
5c3422b0 5989 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5990 amdgpu_ring_write(ring, 0);
5991 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5992 amdgpu_ring_write(ring, 0);
aaa36a97
AD		 5993 }
5994}
5995
aaa36a97
AD		 5996static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5997{
5998 return ring->adev->wb.wb[ring->rptr_offs];
5999}
6000
6001static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6002{
6003 return ring->adev->wb.wb[ring->wptr_offs];
6004}
6005
6006static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6007{
6008 struct amdgpu_device *adev = ring->adev;
6009
6010 /* XXX check if swapping is necessary on BE */
6011 adev->wb.wb[ring->wptr_offs] = ring->wptr;
6012 WDOORBELL32(ring->doorbell_index, ring->wptr);
6013}
6014
6015static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6016 u64 addr, u64 seq,
890ee23f 6017 unsigned flags)
aaa36a97 6018{
890ee23f
CZ		 6019 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6020 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6021
aaa36a97
AD		 6022 /* RELEASE_MEM - flush caches, send int */
6023 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6024 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6025 EOP_TC_ACTION_EN |
a3d5aaa8 6026 EOP_TC_WB_ACTION_EN |
aaa36a97
AD		 6027 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6028 EVENT_INDEX(5)));
890ee23f 6029 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 6030 amdgpu_ring_write(ring, addr & 0xfffffffc);
6031 amdgpu_ring_write(ring, upper_32_bits(addr));
6032 amdgpu_ring_write(ring, lower_32_bits(seq));
6033 amdgpu_ring_write(ring, upper_32_bits(seq));
6034}
6035
6036static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6037 enum amdgpu_interrupt_state state)
6038{
6039 u32 cp_int_cntl;
6040
6041 switch (state) {
6042 case AMDGPU_IRQ_STATE_DISABLE:
6043 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6044 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6045 TIME_STAMP_INT_ENABLE, 0);
6046 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6047 break;
6048 case AMDGPU_IRQ_STATE_ENABLE:
6049 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6050 cp_int_cntl =
6051 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6052 TIME_STAMP_INT_ENABLE, 1);
6053 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6054 break;
6055 default:
6056 break;
6057 }
6058}
6059
6060static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6061 int me, int pipe,
6062 enum amdgpu_interrupt_state state)
6063{
6064 u32 mec_int_cntl, mec_int_cntl_reg;
6065
6066 /*
6067 * amdgpu controls only pipe 0 of MEC1. That's why this function only
6068 * handles the setting of interrupts for this specific pipe. All other
6069 * pipes' interrupts are set by amdkfd.
6070 */
6071
6072 if (me == 1) {
6073 switch (pipe) {
6074 case 0:
6075 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6076 break;
6077 default:
6078 DRM_DEBUG("invalid pipe %d\n", pipe);
6079 return;
6080 }
6081 } else {
6082 DRM_DEBUG("invalid me %d\n", me);
6083 return;
6084 }
6085
6086 switch (state) {
6087 case AMDGPU_IRQ_STATE_DISABLE:
6088 mec_int_cntl = RREG32(mec_int_cntl_reg);
6089 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
6090 TIME_STAMP_INT_ENABLE, 0);
6091 WREG32(mec_int_cntl_reg, mec_int_cntl);
6092 break;
6093 case AMDGPU_IRQ_STATE_ENABLE:
6094 mec_int_cntl = RREG32(mec_int_cntl_reg);
6095 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
6096 TIME_STAMP_INT_ENABLE, 1);
6097 WREG32(mec_int_cntl_reg, mec_int_cntl);
6098 break;
6099 default:
6100 break;
6101 }
6102}
6103
6104static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6105 struct amdgpu_irq_src *source,
6106 unsigned type,
6107 enum amdgpu_interrupt_state state)
6108{
6109 u32 cp_int_cntl;
6110
6111 switch (state) {
6112 case AMDGPU_IRQ_STATE_DISABLE:
6113 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6114 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6115 PRIV_REG_INT_ENABLE, 0);
6116 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6117 break;
6118 case AMDGPU_IRQ_STATE_ENABLE:
6119 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6120 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
04ab3b76 6121 PRIV_REG_INT_ENABLE, 1);
aaa36a97
AD		 6122 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6123 break;
6124 default:
6125 break;
6126 }
6127
6128 return 0;
6129}
6130
6131static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6132 struct amdgpu_irq_src *source,
6133 unsigned type,
6134 enum amdgpu_interrupt_state state)
6135{
6136 u32 cp_int_cntl;
6137
6138 switch (state) {
6139 case AMDGPU_IRQ_STATE_DISABLE:
6140 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6141 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6142 PRIV_INSTR_INT_ENABLE, 0);
6143 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6144 break;
6145 case AMDGPU_IRQ_STATE_ENABLE:
6146 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
6147 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
6148 PRIV_INSTR_INT_ENABLE, 1);
6149 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
6150 break;
6151 default:
6152 break;
6153 }
6154
6155 return 0;
6156}
6157
6158static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6159 struct amdgpu_irq_src *src,
6160 unsigned type,
6161 enum amdgpu_interrupt_state state)
6162{
6163 switch (type) {
6164 case AMDGPU_CP_IRQ_GFX_EOP:
6165 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6166 break;
6167 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6168 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6169 break;
6170 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6171 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6172 break;
6173 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6174 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6175 break;
6176 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6177 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6178 break;
6179 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6180 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6181 break;
6182 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6183 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6184 break;
6185 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6186 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6187 break;
6188 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6189 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6190 break;
6191 default:
6192 break;
6193 }
6194 return 0;
6195}
6196
6197static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6198 struct amdgpu_irq_src *source,
6199 struct amdgpu_iv_entry *entry)
6200{
6201 int i;
6202 u8 me_id, pipe_id, queue_id;
6203 struct amdgpu_ring *ring;
6204
6205 DRM_DEBUG("IH: CP EOP\n");
6206 me_id = (entry->ring_id & 0x0c) >> 2;
6207 pipe_id = (entry->ring_id & 0x03) >> 0;
6208 queue_id = (entry->ring_id & 0x70) >> 4;
6209
6210 switch (me_id) {
6211 case 0:
6212 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6213 break;
6214 case 1:
6215 case 2:
6216 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6217 ring = &adev->gfx.compute_ring[i];
6218 /* Per-queue interrupt is supported for MEC starting from VI.
6219 * The interrupt can only be enabled/disabled per pipe instead of per queue.
6220 */
6221 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6222 amdgpu_fence_process(ring);
6223 }
6224 break;
6225 }
6226 return 0;
6227}
6228
6229static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6230 struct amdgpu_irq_src *source,
6231 struct amdgpu_iv_entry *entry)
6232{
6233 DRM_ERROR("Illegal register access in command stream\n");
6234 schedule_work(&adev->reset_work);
6235 return 0;
6236}
6237
6238static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6239 struct amdgpu_irq_src *source,
6240 struct amdgpu_iv_entry *entry)
6241{
6242 DRM_ERROR("Illegal instruction in command stream\n");
6243 schedule_work(&adev->reset_work);
6244 return 0;
6245}
6246
5fc3aeeb 6247const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
aaa36a97 6248 .early_init = gfx_v8_0_early_init,
ccba7691 6249 .late_init = gfx_v8_0_late_init,
aaa36a97
AD		 6250 .sw_init = gfx_v8_0_sw_init,
6251 .sw_fini = gfx_v8_0_sw_fini,
6252 .hw_init = gfx_v8_0_hw_init,
6253 .hw_fini = gfx_v8_0_hw_fini,
6254 .suspend = gfx_v8_0_suspend,
6255 .resume = gfx_v8_0_resume,
6256 .is_idle = gfx_v8_0_is_idle,
6257 .wait_for_idle = gfx_v8_0_wait_for_idle,
6258 .soft_reset = gfx_v8_0_soft_reset,
6259 .print_status = gfx_v8_0_print_status,
6260 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6261 .set_powergating_state = gfx_v8_0_set_powergating_state,
6262};
6263
6264static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6265 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
6266 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6267 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6268 .parse_cs = NULL,
93323131 6269 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
aaa36a97 6270 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
b8c7b39e 6271 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
aaa36a97
AD		 6272 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6273 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
d2edb07b 6274 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
d35db561 6275 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
aaa36a97
AD		 6276 .test_ring = gfx_v8_0_ring_test_ring,
6277 .test_ib = gfx_v8_0_ring_test_ib,
edff0e28 6278 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 6279 .pad_ib = amdgpu_ring_generic_pad_ib,
aaa36a97
AD		 6280};
6281
6282static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6283 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
6284 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6285 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6286 .parse_cs = NULL,
93323131 6287 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
aaa36a97 6288 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
b8c7b39e 6289 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
aaa36a97
AD		 6290 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6291 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
35074d2d 6292 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
d35db561 6293 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
aaa36a97
AD		 6294 .test_ring = gfx_v8_0_ring_test_ring,
6295 .test_ib = gfx_v8_0_ring_test_ib,
edff0e28 6296 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 6297 .pad_ib = amdgpu_ring_generic_pad_ib,
aaa36a97
AD		 6298};
6299
6300static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
6301{
6302 int i;
6303
6304 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6305 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
6306
6307 for (i = 0; i < adev->gfx.num_compute_rings; i++)
6308 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
6309}
6310
6311static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
6312 .set = gfx_v8_0_set_eop_interrupt_state,
6313 .process = gfx_v8_0_eop_irq,
6314};
6315
6316static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
6317 .set = gfx_v8_0_set_priv_reg_fault_state,
6318 .process = gfx_v8_0_priv_reg_irq,
6319};
6320
6321static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
6322 .set = gfx_v8_0_set_priv_inst_fault_state,
6323 .process = gfx_v8_0_priv_inst_irq,
6324};
6325
6326static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
6327{
6328 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6329 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
6330
6331 adev->gfx.priv_reg_irq.num_types = 1;
6332 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
6333
6334 adev->gfx.priv_inst_irq.num_types = 1;
6335 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
6336}
6337
dbff57bc
AD		 6338static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
6339{
6340 switch (adev->asic_type) {
6341 case CHIP_TOPAZ:
6342 case CHIP_STONEY:
6343 adev->gfx.rlc.funcs = &iceland_rlc_funcs;
6344 break;
6345 case CHIP_CARRIZO:
6346 adev->gfx.rlc.funcs = &cz_rlc_funcs;
6347 break;
6348 default:
6349 adev->gfx.rlc.funcs = &gfx_v8_0_nop_rlc_funcs;
6350 break;
6351 }
6352}
6353
aaa36a97
AD		 6354static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
6355{
6356 /* init asci gds info */
6357 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
6358 adev->gds.gws.total_size = 64;
6359 adev->gds.oa.total_size = 16;
6360
6361 if (adev->gds.mem.total_size == 64 * 1024) {
6362 adev->gds.mem.gfx_partition_size = 4096;
6363 adev->gds.mem.cs_partition_size = 4096;
6364
6365 adev->gds.gws.gfx_partition_size = 4;
6366 adev->gds.gws.cs_partition_size = 4;
6367
6368 adev->gds.oa.gfx_partition_size = 4;
6369 adev->gds.oa.cs_partition_size = 1;
6370 } else {
6371 adev->gds.mem.gfx_partition_size = 1024;
6372 adev->gds.mem.cs_partition_size = 1024;
6373
6374 adev->gds.gws.gfx_partition_size = 16;
6375 adev->gds.gws.cs_partition_size = 16;
6376
6377 adev->gds.oa.gfx_partition_size = 4;
6378 adev->gds.oa.cs_partition_size = 4;
6379 }
6380}
6381
8f8e00c1 6382static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
aaa36a97 6383{
8f8e00c1 6384 u32 data, mask;
aaa36a97 6385
8f8e00c1
AD		 6386 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
6387 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
aaa36a97 6388
8f8e00c1
AD		 6389 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
6390 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
aaa36a97 6391
6157bd7a 6392 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
aaa36a97 6393
8f8e00c1 6394 return (~data) & mask;
aaa36a97
AD		 6395}
6396
6397int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
8f8e00c1 6398 struct amdgpu_cu_info *cu_info)
aaa36a97
AD		 6399{
6400 int i, j, k, counter, active_cu_number = 0;
6401 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
6402
6403 if (!adev || !cu_info)
6404 return -EINVAL;
6405
6157bd7a
FC		 6406 memset(cu_info, 0, sizeof(*cu_info));
6407
aaa36a97
AD		 6408 mutex_lock(&adev->grbm_idx_mutex);
6409 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6410 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6411 mask = 1;
6412 ao_bitmap = 0;
6413 counter = 0;
8f8e00c1
AD		 6414 gfx_v8_0_select_se_sh(adev, i, j);
6415 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
aaa36a97
AD		 6416 cu_info->bitmap[i][j] = bitmap;
6417
8f8e00c1 6418 for (k = 0; k < 16; k ++) {
aaa36a97
AD		 6419 if (bitmap & mask) {
6420 if (counter < 2)
6421 ao_bitmap |= mask;
6422 counter ++;
6423 }
6424 mask <<= 1;
6425 }
6426 active_cu_number += counter;
6427 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
6428 }
6429 }
8f8e00c1
AD		 6430 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
6431 mutex_unlock(&adev->grbm_idx_mutex);
aaa36a97
AD		 6432
6433 cu_info->number = active_cu_number;
6434 cu_info->ao_cu_mask = ao_cu_mask;
8f8e00c1 6435
aaa36a97
AD		 6436 return 0;
6437}
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