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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
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aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "vi.h"
aeab2032 28#include "vi_structs.h"
aaa36a97
AD		 29#include "vid.h"
30#include "amdgpu_ucode.h"
68182d90 31#include "amdgpu_atombios.h"
eeade25a 32#include "atombios_i2c.h"
aaa36a97
AD		 33#include "clearstate_vi.h"
34
35#include "gmc/gmc_8_2_d.h"
36#include "gmc/gmc_8_2_sh_mask.h"
37
38#include "oss/oss_3_0_d.h"
39#include "oss/oss_3_0_sh_mask.h"
40
41#include "bif/bif_5_0_d.h"
42#include "bif/bif_5_0_sh_mask.h"
43
44#include "gca/gfx_8_0_d.h"
45#include "gca/gfx_8_0_enum.h"
46#include "gca/gfx_8_0_sh_mask.h"
47#include "gca/gfx_8_0_enum.h"
48
aaa36a97
AD		 49#include "dce/dce_10_0_d.h"
50#include "dce/dce_10_0_sh_mask.h"
51
d9d533c1
KW		 52#include "smu/smu_7_1_3_d.h"
53
aaa36a97
AD		 54#define GFX8_NUM_GFX_RINGS 1
55#define GFX8_NUM_COMPUTE_RINGS 8
56
57#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
58#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
2cc0c0b5 59#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
aaa36a97
AD		 60#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
61
62#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
63#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
64#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
65#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
66#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
67#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
68#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
69#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
70#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
71
6e378858
EH		 72#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
73#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
74#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
75#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
76#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
77#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
78
79/* BPM SERDES CMD */
80#define SET_BPM_SERDES_CMD 1
81#define CLE_BPM_SERDES_CMD 0
82
83/* BPM Register Address*/
84enum {
85 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
86 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
87 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
88 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
89 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
90 BPM_REG_FGCG_MAX
91};
92
2b6cd977
EH		 93#define RLC_FormatDirectRegListLength 14
94
c65444fe
JZ		 95MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
96MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
97MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
98MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
99MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
100MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
101
e3c7656c
SL		 102MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
103MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
104MODULE_FIRMWARE("amdgpu/stoney_me.bin");
105MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
106MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
107
c65444fe
JZ		 108MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
109MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
110MODULE_FIRMWARE("amdgpu/tonga_me.bin");
111MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
112MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
113MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
114
115MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
116MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
117MODULE_FIRMWARE("amdgpu/topaz_me.bin");
118MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
c65444fe 119MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
aaa36a97 120
af15a2d5
DZ		 121MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
122MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
123MODULE_FIRMWARE("amdgpu/fiji_me.bin");
124MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
125MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
126MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
127
2cc0c0b5
FC		 128MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
129MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
130MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
131MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
132MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
133MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
68182d90 134
2cc0c0b5
FC		 135MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
136MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
137MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
138MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
139MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
140MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
68182d90 141
aaa36a97
AD		 142static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
143{
144 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
145 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
146 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
147 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
148 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
149 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
150 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
151 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
152 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
153 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
154 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
155 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
156 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
157 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
158 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
159 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
160};
161
162static const u32 golden_settings_tonga_a11[] =
163{
164 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
165 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
166 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
167 mmGB_GPU_ID, 0x0000000f, 0x00000000,
168 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
169 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
170 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 171 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 172 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
173 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 174 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 175 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
176 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
177 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
6a00a09e 178 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
aaa36a97
AD		 179};
180
181static const u32 tonga_golden_common_all[] =
182{
183 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
184 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
185 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
186 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
187 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
188 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
189 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
190 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
191};
192
193static const u32 tonga_mgcg_cgcg_init[] =
194{
195 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
196 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
197 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
198 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
199 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
200 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
201 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
202 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
203 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
204 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
205 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
206 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
207 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
208 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
209 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
210 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
211 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
212 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
213 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
214 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
215 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
216 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
217 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
218 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
219 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
220 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
221 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
222 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
223 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
224 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
225 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
226 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
227 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
228 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
229 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
230 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
231 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
232 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
233 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
234 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
235 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
236 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
237 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
238 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
239 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
240 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
241 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
242 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
243 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
244 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
245 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
246 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
247 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
248 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
249 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
250 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
251 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
252 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
253 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
254 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
255 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
256 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
257 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
258 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
259 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
260 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
261 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
262 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
263 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
264 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
265 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
266 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
267 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
268 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
269 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
270};
271
2cc0c0b5 272static const u32 golden_settings_polaris11_a11[] =
68182d90 273{
9761bc53
HR		 274 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
275 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
68182d90
FC		 276 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
277 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
278 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
279 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
b9934878
FC		 280 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
281 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
68182d90
FC		 282 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
283 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
9761bc53 284 mmSQ_CONFIG, 0x07f80000, 0x01180000,
68182d90
FC		 285 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
286 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
287 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
288 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
289 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
795c2109 290 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
68182d90
FC		 291};
292
2cc0c0b5 293static const u32 polaris11_golden_common_all[] =
68182d90
FC		 294{
295 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
68182d90
FC		 296 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
297 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
298 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
299 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
300 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
301};
302
2cc0c0b5 303static const u32 golden_settings_polaris10_a11[] =
68182d90
FC		 304{
305 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
a5a5e308
HR		 306 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
307 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
68182d90
FC		 308 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
309 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
310 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
311 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
312 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
313 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
314 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
315 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
316 mmSQ_CONFIG, 0x07f80000, 0x07180000,
317 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
318 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
319 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
320 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
795c2109 321 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
68182d90
FC		 322};
323
2cc0c0b5 324static const u32 polaris10_golden_common_all[] =
68182d90
FC		 325{
326 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
327 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
328 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
329 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
330 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
331 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
332 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
333 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
334};
335
af15a2d5
DZ		 336static const u32 fiji_golden_common_all[] =
337{
338 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
339 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
340 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
a7ca8ef9 341 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
af15a2d5
DZ		 342 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
343 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
344 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
a7ca8ef9
FC		 345 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
346 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
347 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
af15a2d5
DZ		 348};
349
350static const u32 golden_settings_fiji_a10[] =
351{
352 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
353 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
354 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
af15a2d5 355 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
a7ca8ef9
FC		 356 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
357 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
af15a2d5 358 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
a7ca8ef9
FC		 359 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
360 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
af15a2d5 361 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
a7ca8ef9 362 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
af15a2d5
DZ		 363};
364
365static const u32 fiji_mgcg_cgcg_init[] =
366{
a7ca8ef9 367 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
af15a2d5
DZ		 368 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
369 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
370 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
371 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
372 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
373 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
374 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
375 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
376 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
377 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
378 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
379 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
380 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
381 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
382 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
383 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
384 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
385 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
386 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
387 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
388 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
389 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
390 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
391 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
392 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
393 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
394 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
395 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
396 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
397 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
398 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
399 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
400 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
401 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
402};
403
aaa36a97
AD		 404static const u32 golden_settings_iceland_a11[] =
405{
406 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
407 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
408 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
409 mmGB_GPU_ID, 0x0000000f, 0x00000000,
410 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
411 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
412 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
413 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
fe85f07f 414 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
6a00a09e 415 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 416 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
417 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 418 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 419 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
420 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
421 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
422};
423
424static const u32 iceland_golden_common_all[] =
425{
426 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
427 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
428 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
429 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
430 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
431 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
432 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
433 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
434};
435
436static const u32 iceland_mgcg_cgcg_init[] =
437{
438 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
439 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
440 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
441 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
443 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
444 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
445 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
446 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
447 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
449 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
452 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
453 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
454 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
455 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
456 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
457 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
458 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
459 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
460 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
461 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
462 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
463 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
464 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
465 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
466 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
467 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
468 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
469 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
470 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
471 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
472 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
473 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
474 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
475 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
476 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
477 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
478 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
479 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
480 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
481 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
482 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
483 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
484 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
485 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
486 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
487 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
488 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
489 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
490 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
491 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
492 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
493 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
494 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
495 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
496 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
497 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
498 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
499 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
500 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
501 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
502};
503
504static const u32 cz_golden_settings_a11[] =
505{
506 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
507 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
508 mmGB_GPU_ID, 0x0000000f, 0x00000000,
509 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
510 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
3a494b58 511 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
6a00a09e 512 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97 513 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
3a494b58 514 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 515 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 516 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
517 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
518};
519
520static const u32 cz_golden_common_all[] =
521{
522 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
523 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
524 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
525 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
526 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
527 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
528 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
529 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
530};
531
532static const u32 cz_mgcg_cgcg_init[] =
533{
534 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
535 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
536 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
537 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
538 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
539 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
540 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
541 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
542 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
543 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
544 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
545 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
546 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
547 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
548 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
549 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
550 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
551 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
552 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
553 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
554 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
555 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
556 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
557 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
558 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
559 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
560 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
561 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
562 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
563 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
564 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
565 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
566 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
567 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
568 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
569 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
570 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
571 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
572 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
573 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
574 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
575 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
576 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
577 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
578 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
579 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
580 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
581 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
582 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
583 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
584 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
585 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
586 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
587 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
588 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
589 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
590 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
591 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
592 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
593 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
594 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
595 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
596 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
597 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
598 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
599 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
600 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
601 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
602 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
603 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
604 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
605 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
606 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
607 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
608 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
609};
610
e3c7656c
SL		 611static const u32 stoney_golden_settings_a11[] =
612{
613 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
614 mmGB_GPU_ID, 0x0000000f, 0x00000000,
615 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
616 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
617 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
618 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
edf600da 619 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
e3c7656c
SL		 620 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
621 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
622 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
623};
624
625static const u32 stoney_golden_common_all[] =
626{
627 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
628 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
629 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
630 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
631 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
632 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
633 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
634 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
635};
636
637static const u32 stoney_mgcg_cgcg_init[] =
638{
639 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
640 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
641 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
642 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
643 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
e3c7656c
SL		 644};
645
aaa36a97
AD		 646static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
647static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
648static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
dbff57bc 649static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
2b6cd977 650static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
7dae69a2 651static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
aaa36a97
AD		 652
653static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
654{
655 switch (adev->asic_type) {
656 case CHIP_TOPAZ:
657 amdgpu_program_register_sequence(adev,
658 iceland_mgcg_cgcg_init,
659 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
660 amdgpu_program_register_sequence(adev,
661 golden_settings_iceland_a11,
662 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
663 amdgpu_program_register_sequence(adev,
664 iceland_golden_common_all,
665 (const u32)ARRAY_SIZE(iceland_golden_common_all));
666 break;
af15a2d5
DZ		 667 case CHIP_FIJI:
668 amdgpu_program_register_sequence(adev,
669 fiji_mgcg_cgcg_init,
670 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
671 amdgpu_program_register_sequence(adev,
672 golden_settings_fiji_a10,
673 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
674 amdgpu_program_register_sequence(adev,
675 fiji_golden_common_all,
676 (const u32)ARRAY_SIZE(fiji_golden_common_all));
677 break;
678
aaa36a97
AD		 679 case CHIP_TONGA:
680 amdgpu_program_register_sequence(adev,
681 tonga_mgcg_cgcg_init,
682 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
683 amdgpu_program_register_sequence(adev,
684 golden_settings_tonga_a11,
685 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
686 amdgpu_program_register_sequence(adev,
687 tonga_golden_common_all,
688 (const u32)ARRAY_SIZE(tonga_golden_common_all));
689 break;
2cc0c0b5 690 case CHIP_POLARIS11:
68182d90 691 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 692 golden_settings_polaris11_a11,
693 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
68182d90 694 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 695 polaris11_golden_common_all,
696 (const u32)ARRAY_SIZE(polaris11_golden_common_all));
68182d90 697 break;
2cc0c0b5 698 case CHIP_POLARIS10:
68182d90 699 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 700 golden_settings_polaris10_a11,
701 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
68182d90 702 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 703 polaris10_golden_common_all,
704 (const u32)ARRAY_SIZE(polaris10_golden_common_all));
d9d533c1 705 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
5765a36d
RZ		 706 if (adev->pdev->revision == 0xc7 &&
707 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
708 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
709 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) {
eeade25a
KW		 710 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
711 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
712 }
68182d90 713 break;
aaa36a97
AD		 714 case CHIP_CARRIZO:
715 amdgpu_program_register_sequence(adev,
716 cz_mgcg_cgcg_init,
717 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
718 amdgpu_program_register_sequence(adev,
719 cz_golden_settings_a11,
720 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
721 amdgpu_program_register_sequence(adev,
722 cz_golden_common_all,
723 (const u32)ARRAY_SIZE(cz_golden_common_all));
724 break;
e3c7656c
SL		 725 case CHIP_STONEY:
726 amdgpu_program_register_sequence(adev,
727 stoney_mgcg_cgcg_init,
728 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
729 amdgpu_program_register_sequence(adev,
730 stoney_golden_settings_a11,
731 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
732 amdgpu_program_register_sequence(adev,
733 stoney_golden_common_all,
734 (const u32)ARRAY_SIZE(stoney_golden_common_all));
735 break;
aaa36a97
AD		 736 default:
737 break;
738 }
739}
740
741static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
742{
743 int i;
744
745 adev->gfx.scratch.num_reg = 7;
746 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
747 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
748 adev->gfx.scratch.free[i] = true;
749 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
750 }
751}
752
753static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
754{
755 struct amdgpu_device *adev = ring->adev;
756 uint32_t scratch;
757 uint32_t tmp = 0;
758 unsigned i;
759 int r;
760
761 r = amdgpu_gfx_scratch_get(adev, &scratch);
762 if (r) {
763 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
764 return r;
765 }
766 WREG32(scratch, 0xCAFEDEAD);
a27de35c 767 r = amdgpu_ring_alloc(ring, 3);
aaa36a97
AD		 768 if (r) {
769 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
770 ring->idx, r);
771 amdgpu_gfx_scratch_free(adev, scratch);
772 return r;
773 }
774 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
775 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
776 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 777 amdgpu_ring_commit(ring);
aaa36a97
AD		 778
779 for (i = 0; i < adev->usec_timeout; i++) {
780 tmp = RREG32(scratch);
781 if (tmp == 0xDEADBEEF)
782 break;
783 DRM_UDELAY(1);
784 }
785 if (i < adev->usec_timeout) {
786 DRM_INFO("ring test on %d succeeded in %d usecs\n",
787 ring->idx, i);
788 } else {
789 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
790 ring->idx, scratch, tmp);
791 r = -EINVAL;
792 }
793 amdgpu_gfx_scratch_free(adev, scratch);
794 return r;
795}
796
bbec97aa 797static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
aaa36a97
AD		 798{
799 struct amdgpu_device *adev = ring->adev;
800 struct amdgpu_ib ib;
f54d1867 801 struct dma_fence *f = NULL;
aaa36a97
AD		 802 uint32_t scratch;
803 uint32_t tmp = 0;
bbec97aa 804 long r;
aaa36a97
AD		 805
806 r = amdgpu_gfx_scratch_get(adev, &scratch);
807 if (r) {
bbec97aa 808 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
aaa36a97
AD		 809 return r;
810 }
811 WREG32(scratch, 0xCAFEDEAD);
b203dd95 812 memset(&ib, 0, sizeof(ib));
b07c60c0 813 r = amdgpu_ib_get(adev, NULL, 256, &ib);
aaa36a97 814 if (r) {
bbec97aa 815 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
42d13693 816 goto err1;
aaa36a97
AD		 817 }
818 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
819 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
820 ib.ptr[2] = 0xDEADBEEF;
821 ib.length_dw = 3;
42d13693 822
c5637837 823 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
42d13693
CZ		 824 if (r)
825 goto err2;
826
f54d1867 827 r = dma_fence_wait_timeout(f, false, timeout);
bbec97aa
CK		 828 if (r == 0) {
829 DRM_ERROR("amdgpu: IB test timed out.\n");
830 r = -ETIMEDOUT;
831 goto err2;
832 } else if (r < 0) {
833 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
42d13693 834 goto err2;
aaa36a97 835 }
6d44565d
CK		 836 tmp = RREG32(scratch);
837 if (tmp == 0xDEADBEEF) {
838 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
bbec97aa 839 r = 0;
aaa36a97
AD		 840 } else {
841 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
842 scratch, tmp);
843 r = -EINVAL;
844 }
42d13693 845err2:
cc55c45d 846 amdgpu_ib_free(adev, &ib, NULL);
f54d1867 847 dma_fence_put(f);
42d13693
CZ		 848err1:
849 amdgpu_gfx_scratch_free(adev, scratch);
aaa36a97
AD		 850 return r;
851}
852
13331ac3
ML		 853
854static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) {
855 release_firmware(adev->gfx.pfp_fw);
856 adev->gfx.pfp_fw = NULL;
857 release_firmware(adev->gfx.me_fw);
858 adev->gfx.me_fw = NULL;
859 release_firmware(adev->gfx.ce_fw);
860 adev->gfx.ce_fw = NULL;
861 release_firmware(adev->gfx.rlc_fw);
862 adev->gfx.rlc_fw = NULL;
863 release_firmware(adev->gfx.mec_fw);
864 adev->gfx.mec_fw = NULL;
865 if ((adev->asic_type != CHIP_STONEY) &&
866 (adev->asic_type != CHIP_TOPAZ))
867 release_firmware(adev->gfx.mec2_fw);
868 adev->gfx.mec2_fw = NULL;
869
870 kfree(adev->gfx.rlc.register_list_format);
871}
872
aaa36a97
AD		 873static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
874{
875 const char *chip_name;
876 char fw_name[30];
877 int err;
878 struct amdgpu_firmware_info *info = NULL;
879 const struct common_firmware_header *header = NULL;
595fd013 880 const struct gfx_firmware_header_v1_0 *cp_hdr;
2b6cd977
EH		 881 const struct rlc_firmware_header_v2_0 *rlc_hdr;
882 unsigned int *tmp = NULL, i;
aaa36a97
AD		 883
884 DRM_DEBUG("\n");
885
886 switch (adev->asic_type) {
887 case CHIP_TOPAZ:
888 chip_name = "topaz";
889 break;
890 case CHIP_TONGA:
891 chip_name = "tonga";
892 break;
893 case CHIP_CARRIZO:
894 chip_name = "carrizo";
895 break;
af15a2d5
DZ		 896 case CHIP_FIJI:
897 chip_name = "fiji";
898 break;
2cc0c0b5
FC		 899 case CHIP_POLARIS11:
900 chip_name = "polaris11";
68182d90 901 break;
2cc0c0b5
FC		 902 case CHIP_POLARIS10:
903 chip_name = "polaris10";
68182d90 904 break;
e3c7656c
SL		 905 case CHIP_STONEY:
906 chip_name = "stoney";
907 break;
aaa36a97
AD		 908 default:
909 BUG();
910 }
911
c65444fe 912 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
aaa36a97
AD		 913 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
914 if (err)
915 goto out;
916 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
917 if (err)
918 goto out;
595fd013
JZ		 919 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
920 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
921 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 922
c65444fe 923 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
aaa36a97
AD		 924 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
925 if (err)
926 goto out;
927 err = amdgpu_ucode_validate(adev->gfx.me_fw);
928 if (err)
929 goto out;
595fd013
JZ		 930 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
931 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
932 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 933
c65444fe 934 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
aaa36a97
AD		 935 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
936 if (err)
937 goto out;
938 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
939 if (err)
940 goto out;
595fd013
JZ		 941 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
942 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
943 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 944
c65444fe 945 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
aaa36a97
AD		 946 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
947 if (err)
948 goto out;
949 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
2b6cd977
EH		 950 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
951 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
952 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
953
954 adev->gfx.rlc.save_and_restore_offset =
955 le32_to_cpu(rlc_hdr->save_and_restore_offset);
956 adev->gfx.rlc.clear_state_descriptor_offset =
957 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
958 adev->gfx.rlc.avail_scratch_ram_locations =
959 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
960 adev->gfx.rlc.reg_restore_list_size =
961 le32_to_cpu(rlc_hdr->reg_restore_list_size);
962 adev->gfx.rlc.reg_list_format_start =
963 le32_to_cpu(rlc_hdr->reg_list_format_start);
964 adev->gfx.rlc.reg_list_format_separate_start =
965 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
966 adev->gfx.rlc.starting_offsets_start =
967 le32_to_cpu(rlc_hdr->starting_offsets_start);
968 adev->gfx.rlc.reg_list_format_size_bytes =
969 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
970 adev->gfx.rlc.reg_list_size_bytes =
971 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
972
973 adev->gfx.rlc.register_list_format =
974 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
975 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
976
977 if (!adev->gfx.rlc.register_list_format) {
978 err = -ENOMEM;
979 goto out;
980 }
981
ae17c999 982 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
2b6cd977
EH		 983 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
984 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
985 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
986
987 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
988
ae17c999 989 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
2b6cd977
EH		 990 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
991 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
992 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
aaa36a97 993
c65444fe 994 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
aaa36a97
AD		 995 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
996 if (err)
997 goto out;
998 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
999 if (err)
1000 goto out;
595fd013
JZ		 1001 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1002 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1003 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 1004
97dde76a
AD		 1005 if ((adev->asic_type != CHIP_STONEY) &&
1006 (adev->asic_type != CHIP_TOPAZ)) {
e3c7656c
SL		 1007 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1008 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1009 if (!err) {
1010 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1011 if (err)
1012 goto out;
1013 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1014 adev->gfx.mec2_fw->data;
1015 adev->gfx.mec2_fw_version =
1016 le32_to_cpu(cp_hdr->header.ucode_version);
1017 adev->gfx.mec2_feature_version =
1018 le32_to_cpu(cp_hdr->ucode_feature_version);
1019 } else {
1020 err = 0;
1021 adev->gfx.mec2_fw = NULL;
1022 }
aaa36a97
AD		 1023 }
1024
1025 if (adev->firmware.smu_load) {
1026 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1027 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1028 info->fw = adev->gfx.pfp_fw;
1029 header = (const struct common_firmware_header *)info->fw->data;
1030 adev->firmware.fw_size +=
1031 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1032
1033 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1034 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1035 info->fw = adev->gfx.me_fw;
1036 header = (const struct common_firmware_header *)info->fw->data;
1037 adev->firmware.fw_size +=
1038 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1039
1040 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1041 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1042 info->fw = adev->gfx.ce_fw;
1043 header = (const struct common_firmware_header *)info->fw->data;
1044 adev->firmware.fw_size +=
1045 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1046
1047 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1048 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1049 info->fw = adev->gfx.rlc_fw;
1050 header = (const struct common_firmware_header *)info->fw->data;
1051 adev->firmware.fw_size +=
1052 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1053
1054 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1055 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1056 info->fw = adev->gfx.mec_fw;
1057 header = (const struct common_firmware_header *)info->fw->data;
1058 adev->firmware.fw_size +=
1059 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1060
4c2b2453
ML		 1061 /* we need account JT in */
1062 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1063 adev->firmware.fw_size +=
1064 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1065
bed5712e
ML		 1066 if (amdgpu_sriov_vf(adev)) {
1067 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1068 info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1069 info->fw = adev->gfx.mec_fw;
1070 adev->firmware.fw_size +=
1071 ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1072 }
1073
aaa36a97
AD		 1074 if (adev->gfx.mec2_fw) {
1075 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1076 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1077 info->fw = adev->gfx.mec2_fw;
1078 header = (const struct common_firmware_header *)info->fw->data;
1079 adev->firmware.fw_size +=
1080 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1081 }
1082
1083 }
1084
1085out:
1086 if (err) {
1087 dev_err(adev->dev,
1088 "gfx8: Failed to load firmware \"%s\"\n",
1089 fw_name);
1090 release_firmware(adev->gfx.pfp_fw);
1091 adev->gfx.pfp_fw = NULL;
1092 release_firmware(adev->gfx.me_fw);
1093 adev->gfx.me_fw = NULL;
1094 release_firmware(adev->gfx.ce_fw);
1095 adev->gfx.ce_fw = NULL;
1096 release_firmware(adev->gfx.rlc_fw);
1097 adev->gfx.rlc_fw = NULL;
1098 release_firmware(adev->gfx.mec_fw);
1099 adev->gfx.mec_fw = NULL;
1100 release_firmware(adev->gfx.mec2_fw);
1101 adev->gfx.mec2_fw = NULL;
1102 }
1103 return err;
1104}
1105
2b6cd977
EH		 1106static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1107 volatile u32 *buffer)
1108{
1109 u32 count = 0, i;
1110 const struct cs_section_def *sect = NULL;
1111 const struct cs_extent_def *ext = NULL;
1112
1113 if (adev->gfx.rlc.cs_data == NULL)
1114 return;
1115 if (buffer == NULL)
1116 return;
1117
1118 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1119 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1120
1121 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1122 buffer[count++] = cpu_to_le32(0x80000000);
1123 buffer[count++] = cpu_to_le32(0x80000000);
1124
1125 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1126 for (ext = sect->section; ext->extent != NULL; ++ext) {
1127 if (sect->id == SECT_CONTEXT) {
1128 buffer[count++] =
1129 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1130 buffer[count++] = cpu_to_le32(ext->reg_index -
1131 PACKET3_SET_CONTEXT_REG_START);
1132 for (i = 0; i < ext->reg_count; i++)
1133 buffer[count++] = cpu_to_le32(ext->extent[i]);
1134 } else {
1135 return;
1136 }
1137 }
1138 }
1139
1140 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1141 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1142 PACKET3_SET_CONTEXT_REG_START);
34817db6
AD		 1143 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1144 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
2b6cd977
EH		 1145
1146 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1147 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1148
1149 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1150 buffer[count++] = cpu_to_le32(0);
1151}
1152
fb16007b
AD		 1153static void cz_init_cp_jump_table(struct amdgpu_device *adev)
1154{
1155 const __le32 *fw_data;
1156 volatile u32 *dst_ptr;
1157 int me, i, max_me = 4;
1158 u32 bo_offset = 0;
1159 u32 table_offset, table_size;
1160
1161 if (adev->asic_type == CHIP_CARRIZO)
1162 max_me = 5;
1163
1164 /* write the cp table buffer */
1165 dst_ptr = adev->gfx.rlc.cp_table_ptr;
1166 for (me = 0; me < max_me; me++) {
1167 if (me == 0) {
1168 const struct gfx_firmware_header_v1_0 *hdr =
1169 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1170 fw_data = (const __le32 *)
1171 (adev->gfx.ce_fw->data +
1172 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1173 table_offset = le32_to_cpu(hdr->jt_offset);
1174 table_size = le32_to_cpu(hdr->jt_size);
1175 } else if (me == 1) {
1176 const struct gfx_firmware_header_v1_0 *hdr =
1177 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1178 fw_data = (const __le32 *)
1179 (adev->gfx.pfp_fw->data +
1180 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1181 table_offset = le32_to_cpu(hdr->jt_offset);
1182 table_size = le32_to_cpu(hdr->jt_size);
1183 } else if (me == 2) {
1184 const struct gfx_firmware_header_v1_0 *hdr =
1185 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1186 fw_data = (const __le32 *)
1187 (adev->gfx.me_fw->data +
1188 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1189 table_offset = le32_to_cpu(hdr->jt_offset);
1190 table_size = le32_to_cpu(hdr->jt_size);
1191 } else if (me == 3) {
1192 const struct gfx_firmware_header_v1_0 *hdr =
1193 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1194 fw_data = (const __le32 *)
1195 (adev->gfx.mec_fw->data +
1196 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1197 table_offset = le32_to_cpu(hdr->jt_offset);
1198 table_size = le32_to_cpu(hdr->jt_size);
1199 } else if (me == 4) {
1200 const struct gfx_firmware_header_v1_0 *hdr =
1201 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
1202 fw_data = (const __le32 *)
1203 (adev->gfx.mec2_fw->data +
1204 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1205 table_offset = le32_to_cpu(hdr->jt_offset);
1206 table_size = le32_to_cpu(hdr->jt_size);
1207 }
1208
1209 for (i = 0; i < table_size; i ++) {
1210 dst_ptr[bo_offset + i] =
1211 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
1212 }
1213
1214 bo_offset += table_size;
1215 }
1216}
1217
2b6cd977
EH		 1218static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
1219{
1220 int r;
1221
1222 /* clear state block */
1223 if (adev->gfx.rlc.clear_state_obj) {
1224 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1225 if (unlikely(r != 0))
62d2ce4b 1226 dev_warn(adev->dev, "(%d) reserve RLC cbs bo failed\n", r);
2b6cd977
EH		 1227 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1228 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2b6cd977
EH		 1229 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
1230 adev->gfx.rlc.clear_state_obj = NULL;
1231 }
fb16007b
AD		 1232
1233 /* jump table block */
1234 if (adev->gfx.rlc.cp_table_obj) {
1235 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
1236 if (unlikely(r != 0))
1237 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
1238 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
1239 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
fb16007b
AD		 1240 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
1241 adev->gfx.rlc.cp_table_obj = NULL;
1242 }
2b6cd977
EH		 1243}
1244
1245static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1246{
1247 volatile u32 *dst_ptr;
1248 u32 dws;
1249 const struct cs_section_def *cs_data;
1250 int r;
1251
1252 adev->gfx.rlc.cs_data = vi_cs_data;
1253
1254 cs_data = adev->gfx.rlc.cs_data;
1255
1256 if (cs_data) {
1257 /* clear state block */
1258 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev);
1259
1260 if (adev->gfx.rlc.clear_state_obj == NULL) {
1261 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
1262 AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5
CK		 1263 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1264 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
2b6cd977
EH		 1265 NULL, NULL,
1266 &adev->gfx.rlc.clear_state_obj);
1267 if (r) {
1268 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
1269 gfx_v8_0_rlc_fini(adev);
1270 return r;
1271 }
1272 }
1273 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1274 if (unlikely(r != 0)) {
1275 gfx_v8_0_rlc_fini(adev);
1276 return r;
1277 }
1278 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
1279 &adev->gfx.rlc.clear_state_gpu_addr);
1280 if (r) {
1281 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
62d2ce4b 1282 dev_warn(adev->dev, "(%d) pin RLC cbs bo failed\n", r);
2b6cd977
EH		 1283 gfx_v8_0_rlc_fini(adev);
1284 return r;
1285 }
1286
1287 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
1288 if (r) {
62d2ce4b 1289 dev_warn(adev->dev, "(%d) map RLC cbs bo failed\n", r);
2b6cd977
EH		 1290 gfx_v8_0_rlc_fini(adev);
1291 return r;
1292 }
1293 /* set up the cs buffer */
1294 dst_ptr = adev->gfx.rlc.cs_ptr;
1295 gfx_v8_0_get_csb_buffer(adev, dst_ptr);
1296 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1297 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1298 }
1299
fb16007b
AD		 1300 if ((adev->asic_type == CHIP_CARRIZO) ||
1301 (adev->asic_type == CHIP_STONEY)) {
07cf1a0b 1302 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
fb16007b
AD		 1303 if (adev->gfx.rlc.cp_table_obj == NULL) {
1304 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
1305 AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5
CK		 1306 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1307 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
fb16007b
AD		 1308 NULL, NULL,
1309 &adev->gfx.rlc.cp_table_obj);
1310 if (r) {
1311 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
1312 return r;
1313 }
1314 }
1315
1316 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
1317 if (unlikely(r != 0)) {
1318 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
1319 return r;
1320 }
1321 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
1322 &adev->gfx.rlc.cp_table_gpu_addr);
1323 if (r) {
1324 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
62d2ce4b 1325 dev_warn(adev->dev, "(%d) pin RLC cp table bo failed\n", r);
fb16007b
AD		 1326 return r;
1327 }
1328 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
1329 if (r) {
1330 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
1331 return r;
1332 }
1333
1334 cz_init_cp_jump_table(adev);
1335
1336 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
1337 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
fb16007b
AD		 1338 }
1339
2b6cd977
EH		 1340 return 0;
1341}
1342
aaa36a97
AD		 1343static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1344{
1345 int r;
1346
1347 if (adev->gfx.mec.hpd_eop_obj) {
1348 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
1349 if (unlikely(r != 0))
1350 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
1351 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
1352 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
aaa36a97
AD		 1353 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
1354 adev->gfx.mec.hpd_eop_obj = NULL;
1355 }
1356}
1357
1358#define MEC_HPD_SIZE 2048
1359
1360static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1361{
1362 int r;
1363 u32 *hpd;
1364
1365 /*
1366 * we assign only 1 pipe because all other pipes will
1367 * be handled by KFD
1368 */
1369 adev->gfx.mec.num_mec = 1;
1370 adev->gfx.mec.num_pipe = 1;
1371 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
1372
1373 if (adev->gfx.mec.hpd_eop_obj == NULL) {
1374 r = amdgpu_bo_create(adev,
ad3b9614 1375 adev->gfx.mec.num_queue * MEC_HPD_SIZE,
aaa36a97 1376 PAGE_SIZE, true,
72d7668b 1377 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
aaa36a97
AD		 1378 &adev->gfx.mec.hpd_eop_obj);
1379 if (r) {
1380 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1381 return r;
1382 }
1383 }
1384
1385 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
1386 if (unlikely(r != 0)) {
1387 gfx_v8_0_mec_fini(adev);
1388 return r;
1389 }
1390 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
1391 &adev->gfx.mec.hpd_eop_gpu_addr);
1392 if (r) {
1393 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
1394 gfx_v8_0_mec_fini(adev);
1395 return r;
1396 }
1397 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
1398 if (r) {
1399 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
1400 gfx_v8_0_mec_fini(adev);
1401 return r;
1402 }
1403
ad3b9614 1404 memset(hpd, 0, adev->gfx.mec.num_queue * MEC_HPD_SIZE);
aaa36a97
AD		 1405
1406 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1407 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1408
1409 return 0;
1410}
1411
ccba7691
AD		 1412static const u32 vgpr_init_compute_shader[] =
1413{
1414 0x7e000209, 0x7e020208,
1415 0x7e040207, 0x7e060206,
1416 0x7e080205, 0x7e0a0204,
1417 0x7e0c0203, 0x7e0e0202,
1418 0x7e100201, 0x7e120200,
1419 0x7e140209, 0x7e160208,
1420 0x7e180207, 0x7e1a0206,
1421 0x7e1c0205, 0x7e1e0204,
1422 0x7e200203, 0x7e220202,
1423 0x7e240201, 0x7e260200,
1424 0x7e280209, 0x7e2a0208,
1425 0x7e2c0207, 0x7e2e0206,
1426 0x7e300205, 0x7e320204,
1427 0x7e340203, 0x7e360202,
1428 0x7e380201, 0x7e3a0200,
1429 0x7e3c0209, 0x7e3e0208,
1430 0x7e400207, 0x7e420206,
1431 0x7e440205, 0x7e460204,
1432 0x7e480203, 0x7e4a0202,
1433 0x7e4c0201, 0x7e4e0200,
1434 0x7e500209, 0x7e520208,
1435 0x7e540207, 0x7e560206,
1436 0x7e580205, 0x7e5a0204,
1437 0x7e5c0203, 0x7e5e0202,
1438 0x7e600201, 0x7e620200,
1439 0x7e640209, 0x7e660208,
1440 0x7e680207, 0x7e6a0206,
1441 0x7e6c0205, 0x7e6e0204,
1442 0x7e700203, 0x7e720202,
1443 0x7e740201, 0x7e760200,
1444 0x7e780209, 0x7e7a0208,
1445 0x7e7c0207, 0x7e7e0206,
1446 0xbf8a0000, 0xbf810000,
1447};
1448
1449static const u32 sgpr_init_compute_shader[] =
1450{
1451 0xbe8a0100, 0xbe8c0102,
1452 0xbe8e0104, 0xbe900106,
1453 0xbe920108, 0xbe940100,
1454 0xbe960102, 0xbe980104,
1455 0xbe9a0106, 0xbe9c0108,
1456 0xbe9e0100, 0xbea00102,
1457 0xbea20104, 0xbea40106,
1458 0xbea60108, 0xbea80100,
1459 0xbeaa0102, 0xbeac0104,
1460 0xbeae0106, 0xbeb00108,
1461 0xbeb20100, 0xbeb40102,
1462 0xbeb60104, 0xbeb80106,
1463 0xbeba0108, 0xbebc0100,
1464 0xbebe0102, 0xbec00104,
1465 0xbec20106, 0xbec40108,
1466 0xbec60100, 0xbec80102,
1467 0xbee60004, 0xbee70005,
1468 0xbeea0006, 0xbeeb0007,
1469 0xbee80008, 0xbee90009,
1470 0xbefc0000, 0xbf8a0000,
1471 0xbf810000, 0x00000000,
1472};
1473
1474static const u32 vgpr_init_regs[] =
1475{
1476 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1477 mmCOMPUTE_RESOURCE_LIMITS, 0,
1478 mmCOMPUTE_NUM_THREAD_X, 256*4,
1479 mmCOMPUTE_NUM_THREAD_Y, 1,
1480 mmCOMPUTE_NUM_THREAD_Z, 1,
1481 mmCOMPUTE_PGM_RSRC2, 20,
1482 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1483 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1484 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1485 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1486 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1487 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1488 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1489 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1490 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1491 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1492};
1493
1494static const u32 sgpr1_init_regs[] =
1495{
1496 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1497 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1498 mmCOMPUTE_NUM_THREAD_X, 256*5,
1499 mmCOMPUTE_NUM_THREAD_Y, 1,
1500 mmCOMPUTE_NUM_THREAD_Z, 1,
1501 mmCOMPUTE_PGM_RSRC2, 20,
1502 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1503 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1504 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1505 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1506 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1507 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1508 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1509 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1510 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1511 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1512};
1513
1514static const u32 sgpr2_init_regs[] =
1515{
1516 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1517 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1518 mmCOMPUTE_NUM_THREAD_X, 256*5,
1519 mmCOMPUTE_NUM_THREAD_Y, 1,
1520 mmCOMPUTE_NUM_THREAD_Z, 1,
1521 mmCOMPUTE_PGM_RSRC2, 20,
1522 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1523 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1524 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1525 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1526 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1527 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1528 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1529 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1530 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1531 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1532};
1533
1534static const u32 sec_ded_counter_registers[] =
1535{
1536 mmCPC_EDC_ATC_CNT,
1537 mmCPC_EDC_SCRATCH_CNT,
1538 mmCPC_EDC_UCODE_CNT,
1539 mmCPF_EDC_ATC_CNT,
1540 mmCPF_EDC_ROQ_CNT,
1541 mmCPF_EDC_TAG_CNT,
1542 mmCPG_EDC_ATC_CNT,
1543 mmCPG_EDC_DMA_CNT,
1544 mmCPG_EDC_TAG_CNT,
1545 mmDC_EDC_CSINVOC_CNT,
1546 mmDC_EDC_RESTORE_CNT,
1547 mmDC_EDC_STATE_CNT,
1548 mmGDS_EDC_CNT,
1549 mmGDS_EDC_GRBM_CNT,
1550 mmGDS_EDC_OA_DED,
1551 mmSPI_EDC_CNT,
1552 mmSQC_ATC_EDC_GATCL1_CNT,
1553 mmSQC_EDC_CNT,
1554 mmSQ_EDC_DED_CNT,
1555 mmSQ_EDC_INFO,
1556 mmSQ_EDC_SEC_CNT,
1557 mmTCC_EDC_CNT,
1558 mmTCP_ATC_EDC_GATCL1_CNT,
1559 mmTCP_EDC_CNT,
1560 mmTD_EDC_CNT
1561};
1562
1563static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1564{
1565 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1566 struct amdgpu_ib ib;
f54d1867 1567 struct dma_fence *f = NULL;
ccba7691
AD		 1568 int r, i;
1569 u32 tmp;
1570 unsigned total_size, vgpr_offset, sgpr_offset;
1571 u64 gpu_addr;
1572
1573 /* only supported on CZ */
1574 if (adev->asic_type != CHIP_CARRIZO)
1575 return 0;
1576
1577 /* bail if the compute ring is not ready */
1578 if (!ring->ready)
1579 return 0;
1580
1581 tmp = RREG32(mmGB_EDC_MODE);
1582 WREG32(mmGB_EDC_MODE, 0);
1583
1584 total_size =
1585 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1586 total_size +=
1587 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1588 total_size +=
1589 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1590 total_size = ALIGN(total_size, 256);
1591 vgpr_offset = total_size;
1592 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1593 sgpr_offset = total_size;
1594 total_size += sizeof(sgpr_init_compute_shader);
1595
1596 /* allocate an indirect buffer to put the commands in */
1597 memset(&ib, 0, sizeof(ib));
b07c60c0 1598 r = amdgpu_ib_get(adev, NULL, total_size, &ib);
ccba7691
AD		 1599 if (r) {
1600 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1601 return r;
1602 }
1603
1604 /* load the compute shaders */
1605 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1606 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1607
1608 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1609 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1610
1611 /* init the ib length to 0 */
1612 ib.length_dw = 0;
1613
1614 /* VGPR */
1615 /* write the register state for the compute dispatch */
1616 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1617 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1618 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1619 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1620 }
1621 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1622 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1623 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1624 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1625 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1626 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1627
1628 /* write dispatch packet */
1629 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1630 ib.ptr[ib.length_dw++] = 8; /* x */
1631 ib.ptr[ib.length_dw++] = 1; /* y */
1632 ib.ptr[ib.length_dw++] = 1; /* z */
1633 ib.ptr[ib.length_dw++] =
1634 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1635
1636 /* write CS partial flush packet */
1637 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1638 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1639
1640 /* SGPR1 */
1641 /* write the register state for the compute dispatch */
1642 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1643 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1644 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1645 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1646 }
1647 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1648 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1649 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1650 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1651 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1652 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1653
1654 /* write dispatch packet */
1655 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1656 ib.ptr[ib.length_dw++] = 8; /* x */
1657 ib.ptr[ib.length_dw++] = 1; /* y */
1658 ib.ptr[ib.length_dw++] = 1; /* z */
1659 ib.ptr[ib.length_dw++] =
1660 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1661
1662 /* write CS partial flush packet */
1663 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1664 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1665
1666 /* SGPR2 */
1667 /* write the register state for the compute dispatch */
1668 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1669 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1670 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1671 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1672 }
1673 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1674 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1675 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1676 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1677 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1678 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1679
1680 /* write dispatch packet */
1681 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1682 ib.ptr[ib.length_dw++] = 8; /* x */
1683 ib.ptr[ib.length_dw++] = 1; /* y */
1684 ib.ptr[ib.length_dw++] = 1; /* z */
1685 ib.ptr[ib.length_dw++] =
1686 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1687
1688 /* write CS partial flush packet */
1689 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1690 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1691
1692 /* shedule the ib on the ring */
c5637837 1693 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
ccba7691
AD		 1694 if (r) {
1695 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1696 goto fail;
1697 }
1698
1699 /* wait for the GPU to finish processing the IB */
f54d1867 1700 r = dma_fence_wait(f, false);
ccba7691
AD		 1701 if (r) {
1702 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1703 goto fail;
1704 }
1705
1706 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1707 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1708 WREG32(mmGB_EDC_MODE, tmp);
1709
1710 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1711 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1712 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1713
1714
1715 /* read back registers to clear the counters */
1716 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1717 RREG32(sec_ded_counter_registers[i]);
1718
1719fail:
cc55c45d 1720 amdgpu_ib_free(adev, &ib, NULL);
f54d1867 1721 dma_fence_put(f);
ccba7691
AD		 1722
1723 return r;
1724}
1725
68182d90 1726static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
0bde3a95
AD		 1727{
1728 u32 gb_addr_config;
1729 u32 mc_shared_chmap, mc_arb_ramcfg;
1730 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1731 u32 tmp;
68182d90 1732 int ret;
0bde3a95
AD		 1733
1734 switch (adev->asic_type) {
1735 case CHIP_TOPAZ:
1736 adev->gfx.config.max_shader_engines = 1;
1737 adev->gfx.config.max_tile_pipes = 2;
1738 adev->gfx.config.max_cu_per_sh = 6;
1739 adev->gfx.config.max_sh_per_se = 1;
1740 adev->gfx.config.max_backends_per_se = 2;
1741 adev->gfx.config.max_texture_channel_caches = 2;
1742 adev->gfx.config.max_gprs = 256;
1743 adev->gfx.config.max_gs_threads = 32;
1744 adev->gfx.config.max_hw_contexts = 8;
1745
1746 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1747 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1748 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1749 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1750 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1751 break;
1752 case CHIP_FIJI:
1753 adev->gfx.config.max_shader_engines = 4;
1754 adev->gfx.config.max_tile_pipes = 16;
1755 adev->gfx.config.max_cu_per_sh = 16;
1756 adev->gfx.config.max_sh_per_se = 1;
1757 adev->gfx.config.max_backends_per_se = 4;
5f2e816b 1758 adev->gfx.config.max_texture_channel_caches = 16;
0bde3a95
AD		 1759 adev->gfx.config.max_gprs = 256;
1760 adev->gfx.config.max_gs_threads = 32;
1761 adev->gfx.config.max_hw_contexts = 8;
1762
68182d90
FC		 1763 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1764 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1765 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1766 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1767 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1768 break;
2cc0c0b5 1769 case CHIP_POLARIS11:
68182d90
FC		 1770 ret = amdgpu_atombios_get_gfx_info(adev);
1771 if (ret)
1772 return ret;
1773 adev->gfx.config.max_gprs = 256;
1774 adev->gfx.config.max_gs_threads = 32;
1775 adev->gfx.config.max_hw_contexts = 8;
1776
1777 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1778 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1779 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1780 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2cc0c0b5 1781 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
68182d90 1782 break;
2cc0c0b5 1783 case CHIP_POLARIS10:
68182d90
FC		 1784 ret = amdgpu_atombios_get_gfx_info(adev);
1785 if (ret)
1786 return ret;
1787 adev->gfx.config.max_gprs = 256;
1788 adev->gfx.config.max_gs_threads = 32;
1789 adev->gfx.config.max_hw_contexts = 8;
1790
0bde3a95
AD		 1791 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1792 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1793 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1794 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1795 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1796 break;
1797 case CHIP_TONGA:
1798 adev->gfx.config.max_shader_engines = 4;
1799 adev->gfx.config.max_tile_pipes = 8;
1800 adev->gfx.config.max_cu_per_sh = 8;
1801 adev->gfx.config.max_sh_per_se = 1;
1802 adev->gfx.config.max_backends_per_se = 2;
1803 adev->gfx.config.max_texture_channel_caches = 8;
1804 adev->gfx.config.max_gprs = 256;
1805 adev->gfx.config.max_gs_threads = 32;
1806 adev->gfx.config.max_hw_contexts = 8;
1807
1808 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1809 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1810 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1811 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1812 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1813 break;
1814 case CHIP_CARRIZO:
1815 adev->gfx.config.max_shader_engines = 1;
1816 adev->gfx.config.max_tile_pipes = 2;
1817 adev->gfx.config.max_sh_per_se = 1;
1818 adev->gfx.config.max_backends_per_se = 2;
1819
1820 switch (adev->pdev->revision) {
1821 case 0xc4:
1822 case 0x84:
1823 case 0xc8:
1824 case 0xcc:
b8b339ea
AD		 1825 case 0xe1:
1826 case 0xe3:
0bde3a95
AD		 1827 /* B10 */
1828 adev->gfx.config.max_cu_per_sh = 8;
1829 break;
1830 case 0xc5:
1831 case 0x81:
1832 case 0x85:
1833 case 0xc9:
1834 case 0xcd:
b8b339ea
AD		 1835 case 0xe2:
1836 case 0xe4:
0bde3a95
AD		 1837 /* B8 */
1838 adev->gfx.config.max_cu_per_sh = 6;
1839 break;
1840 case 0xc6:
1841 case 0xca:
1842 case 0xce:
b8b339ea 1843 case 0x88:
0bde3a95
AD		 1844 /* B6 */
1845 adev->gfx.config.max_cu_per_sh = 6;
1846 break;
1847 case 0xc7:
1848 case 0x87:
1849 case 0xcb:
b8b339ea
AD		 1850 case 0xe5:
1851 case 0x89:
0bde3a95
AD		 1852 default:
1853 /* B4 */
1854 adev->gfx.config.max_cu_per_sh = 4;
1855 break;
1856 }
1857
1858 adev->gfx.config.max_texture_channel_caches = 2;
1859 adev->gfx.config.max_gprs = 256;
1860 adev->gfx.config.max_gs_threads = 32;
1861 adev->gfx.config.max_hw_contexts = 8;
1862
e3c7656c
SL		 1863 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1864 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1865 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1866 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1867 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1868 break;
1869 case CHIP_STONEY:
1870 adev->gfx.config.max_shader_engines = 1;
1871 adev->gfx.config.max_tile_pipes = 2;
1872 adev->gfx.config.max_sh_per_se = 1;
1873 adev->gfx.config.max_backends_per_se = 1;
1874
1875 switch (adev->pdev->revision) {
1876 case 0xc0:
1877 case 0xc1:
1878 case 0xc2:
1879 case 0xc4:
1880 case 0xc8:
1881 case 0xc9:
1882 adev->gfx.config.max_cu_per_sh = 3;
1883 break;
1884 case 0xd0:
1885 case 0xd1:
1886 case 0xd2:
1887 default:
1888 adev->gfx.config.max_cu_per_sh = 2;
1889 break;
1890 }
1891
1892 adev->gfx.config.max_texture_channel_caches = 2;
1893 adev->gfx.config.max_gprs = 256;
1894 adev->gfx.config.max_gs_threads = 16;
1895 adev->gfx.config.max_hw_contexts = 8;
1896
0bde3a95
AD		 1897 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1898 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1899 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1900 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1901 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1902 break;
1903 default:
1904 adev->gfx.config.max_shader_engines = 2;
1905 adev->gfx.config.max_tile_pipes = 4;
1906 adev->gfx.config.max_cu_per_sh = 2;
1907 adev->gfx.config.max_sh_per_se = 1;
1908 adev->gfx.config.max_backends_per_se = 2;
1909 adev->gfx.config.max_texture_channel_caches = 4;
1910 adev->gfx.config.max_gprs = 256;
1911 adev->gfx.config.max_gs_threads = 32;
1912 adev->gfx.config.max_hw_contexts = 8;
1913
1914 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1915 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1916 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1917 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1918 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1919 break;
1920 }
1921
1922 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1923 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1924 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1925
1926 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1927 adev->gfx.config.mem_max_burst_length_bytes = 256;
1928 if (adev->flags & AMD_IS_APU) {
1929 /* Get memory bank mapping mode. */
1930 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1931 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1932 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1933
1934 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1935 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1936 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1937
1938 /* Validate settings in case only one DIMM installed. */
1939 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1940 dimm00_addr_map = 0;
1941 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1942 dimm01_addr_map = 0;
1943 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1944 dimm10_addr_map = 0;
1945 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1946 dimm11_addr_map = 0;
1947
1948 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1949 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1950 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1951 adev->gfx.config.mem_row_size_in_kb = 2;
1952 else
1953 adev->gfx.config.mem_row_size_in_kb = 1;
1954 } else {
1955 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1956 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1957 if (adev->gfx.config.mem_row_size_in_kb > 4)
1958 adev->gfx.config.mem_row_size_in_kb = 4;
1959 }
1960
1961 adev->gfx.config.shader_engine_tile_size = 32;
1962 adev->gfx.config.num_gpus = 1;
1963 adev->gfx.config.multi_gpu_tile_size = 64;
1964
1965 /* fix up row size */
1966 switch (adev->gfx.config.mem_row_size_in_kb) {
1967 case 1:
1968 default:
1969 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1970 break;
1971 case 2:
1972 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1973 break;
1974 case 4:
1975 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1976 break;
1977 }
1978 adev->gfx.config.gb_addr_config = gb_addr_config;
68182d90
FC		 1979
1980 return 0;
0bde3a95
AD		 1981}
1982
5fc3aeeb 1983static int gfx_v8_0_sw_init(void *handle)
aaa36a97
AD		 1984{
1985 int i, r;
1986 struct amdgpu_ring *ring;
5fc3aeeb 1987 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1988
1989 /* EOP Event */
1990 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
1991 if (r)
1992 return r;
1993
1994 /* Privileged reg */
1995 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
1996 if (r)
1997 return r;
1998
1999 /* Privileged inst */
2000 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
2001 if (r)
2002 return r;
2003
2004 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
2005
2006 gfx_v8_0_scratch_init(adev);
2007
2008 r = gfx_v8_0_init_microcode(adev);
2009 if (r) {
2010 DRM_ERROR("Failed to load gfx firmware!\n");
2011 return r;
2012 }
2013
2b6cd977
EH		 2014 r = gfx_v8_0_rlc_init(adev);
2015 if (r) {
2016 DRM_ERROR("Failed to init rlc BOs!\n");
2017 return r;
2018 }
2019
aaa36a97
AD		 2020 r = gfx_v8_0_mec_init(adev);
2021 if (r) {
2022 DRM_ERROR("Failed to init MEC BOs!\n");
2023 return r;
2024 }
2025
aaa36a97
AD		 2026 /* set up the gfx ring */
2027 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2028 ring = &adev->gfx.gfx_ring[i];
2029 ring->ring_obj = NULL;
2030 sprintf(ring->name, "gfx");
2031 /* no gfx doorbells on iceland */
2032 if (adev->asic_type != CHIP_TOPAZ) {
2033 ring->use_doorbell = true;
2034 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
2035 }
2036
79887142
CK		 2037 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2038 AMDGPU_CP_IRQ_GFX_EOP);
aaa36a97
AD		 2039 if (r)
2040 return r;
2041 }
2042
2043 /* set up the compute queues */
2044 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2045 unsigned irq_type;
2046
2047 /* max 32 queues per MEC */
2048 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
2049 DRM_ERROR("Too many (%d) compute rings!\n", i);
2050 break;
2051 }
2052 ring = &adev->gfx.compute_ring[i];
2053 ring->ring_obj = NULL;
2054 ring->use_doorbell = true;
2055 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
2056 ring->me = 1; /* first MEC */
2057 ring->pipe = i / 8;
2058 ring->queue = i % 8;
771c8ec1 2059 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
aaa36a97
AD		 2060 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2061 /* type-2 packets are deprecated on MEC, use type-3 instead */
79887142
CK		 2062 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2063 irq_type);
aaa36a97
AD		 2064 if (r)
2065 return r;
2066 }
2067
2068 /* reserve GDS, GWS and OA resource for gfx */
78bbbd9c
CK		 2069 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
2070 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
2071 &adev->gds.gds_gfx_bo, NULL, NULL);
aaa36a97
AD		 2072 if (r)
2073 return r;
2074
78bbbd9c
CK		 2075 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
2076 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
2077 &adev->gds.gws_gfx_bo, NULL, NULL);
aaa36a97
AD		 2078 if (r)
2079 return r;
2080
78bbbd9c
CK		 2081 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
2082 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
2083 &adev->gds.oa_gfx_bo, NULL, NULL);
aaa36a97
AD		 2084 if (r)
2085 return r;
2086
a101a899
KW		 2087 adev->gfx.ce_ram_size = 0x8000;
2088
68182d90
FC		 2089 r = gfx_v8_0_gpu_early_init(adev);
2090 if (r)
2091 return r;
0bde3a95 2092
aaa36a97
AD		 2093 return 0;
2094}
2095
5fc3aeeb 2096static int gfx_v8_0_sw_fini(void *handle)
aaa36a97
AD		 2097{
2098 int i;
5fc3aeeb 2099 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 2100
8640faed
JZ		 2101 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
2102 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
2103 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
aaa36a97
AD		 2104
2105 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2106 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2107 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2108 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2109
aaa36a97 2110 gfx_v8_0_mec_fini(adev);
2b6cd977 2111 gfx_v8_0_rlc_fini(adev);
13331ac3 2112 gfx_v8_0_free_microcode(adev);
2b6cd977 2113
aaa36a97
AD		 2114 return 0;
2115}
2116
2117static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2118{
90bea0ab 2119 uint32_t *modearray, *mod2array;
eb64526f
TSD		 2120 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2121 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
90bea0ab 2122 u32 reg_offset;
aaa36a97 2123
90bea0ab
TSD		 2124 modearray = adev->gfx.config.tile_mode_array;
2125 mod2array = adev->gfx.config.macrotile_mode_array;
2126
2127 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2128 modearray[reg_offset] = 0;
2129
2130 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2131 mod2array[reg_offset] = 0;
aaa36a97
AD		 2132
2133 switch (adev->asic_type) {
2134 case CHIP_TOPAZ:
90bea0ab
TSD		 2135 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2136 PIPE_CONFIG(ADDR_SURF_P2) |
2137 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2138 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2139 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2140 PIPE_CONFIG(ADDR_SURF_P2) |
2141 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2142 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2143 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2144 PIPE_CONFIG(ADDR_SURF_P2) |
2145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2146 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2147 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2148 PIPE_CONFIG(ADDR_SURF_P2) |
2149 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2150 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2151 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2152 PIPE_CONFIG(ADDR_SURF_P2) |
2153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2154 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2155 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2156 PIPE_CONFIG(ADDR_SURF_P2) |
2157 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2158 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2159 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2160 PIPE_CONFIG(ADDR_SURF_P2) |
2161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2162 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2163 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2164 PIPE_CONFIG(ADDR_SURF_P2));
2165 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2166 PIPE_CONFIG(ADDR_SURF_P2) |
2167 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2168 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2169 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2170 PIPE_CONFIG(ADDR_SURF_P2) |
2171 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2172 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2173 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2174 PIPE_CONFIG(ADDR_SURF_P2) |
2175 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2176 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2177 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2178 PIPE_CONFIG(ADDR_SURF_P2) |
2179 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2180 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2181 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2182 PIPE_CONFIG(ADDR_SURF_P2) |
2183 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2184 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2185 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2186 PIPE_CONFIG(ADDR_SURF_P2) |
2187 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2188 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2189 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2190 PIPE_CONFIG(ADDR_SURF_P2) |
2191 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2192 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2193 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2194 PIPE_CONFIG(ADDR_SURF_P2) |
2195 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2196 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2197 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2198 PIPE_CONFIG(ADDR_SURF_P2) |
2199 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2200 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2201 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2202 PIPE_CONFIG(ADDR_SURF_P2) |
2203 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2204 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2205 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2206 PIPE_CONFIG(ADDR_SURF_P2) |
2207 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2208 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2209 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2210 PIPE_CONFIG(ADDR_SURF_P2) |
2211 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2212 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2213 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2214 PIPE_CONFIG(ADDR_SURF_P2) |
2215 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2216 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2217 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2218 PIPE_CONFIG(ADDR_SURF_P2) |
2219 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2220 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2221 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2222 PIPE_CONFIG(ADDR_SURF_P2) |
2223 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2224 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2225 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2226 PIPE_CONFIG(ADDR_SURF_P2) |
2227 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2228 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2229 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2230 PIPE_CONFIG(ADDR_SURF_P2) |
2231 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2232 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2233 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2234 PIPE_CONFIG(ADDR_SURF_P2) |
2235 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2236 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2237
2238 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2239 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2240 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2241 NUM_BANKS(ADDR_SURF_8_BANK));
2242 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2243 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2244 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2245 NUM_BANKS(ADDR_SURF_8_BANK));
2246 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2247 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2248 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2249 NUM_BANKS(ADDR_SURF_8_BANK));
2250 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2253 NUM_BANKS(ADDR_SURF_8_BANK));
2254 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2255 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2256 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2257 NUM_BANKS(ADDR_SURF_8_BANK));
2258 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2259 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2260 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2261 NUM_BANKS(ADDR_SURF_8_BANK));
2262 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2265 NUM_BANKS(ADDR_SURF_8_BANK));
2266 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2268 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2269 NUM_BANKS(ADDR_SURF_16_BANK));
2270 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2273 NUM_BANKS(ADDR_SURF_16_BANK));
2274 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2275 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2276 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2277 NUM_BANKS(ADDR_SURF_16_BANK));
2278 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2281 NUM_BANKS(ADDR_SURF_16_BANK));
2282 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2283 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2284 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2285 NUM_BANKS(ADDR_SURF_16_BANK));
2286 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2289 NUM_BANKS(ADDR_SURF_16_BANK));
2290 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2291 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2292 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2293 NUM_BANKS(ADDR_SURF_8_BANK));
2294
2295 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2296 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2297 reg_offset != 23)
2298 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2299
2300 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2301 if (reg_offset != 7)
2302 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2303
8cdacf44 2304 break;
af15a2d5 2305 case CHIP_FIJI:
90bea0ab
TSD		 2306 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2307 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2308 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2309 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2310 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2312 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2313 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2314 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2316 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2317 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2318 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2320 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2321 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2322 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2324 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2325 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2326 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2328 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2329 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2330 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2332 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2333 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2334 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2335 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2336 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2337 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2338 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2339 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2340 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2341 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2342 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2343 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2344 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2345 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2346 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2347 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2348 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2349 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2350 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2351 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2352 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2353 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2354 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2355 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2356 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2357 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2358 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2359 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2360 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2361 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2362 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2363 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2364 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2365 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2366 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2367 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2368 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2369 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2370 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2371 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2372 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2373 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2374 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2375 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2376 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2377 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2378 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2379 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2380 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2381 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2382 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2383 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2384 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2385 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2386 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2387 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2388 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2389 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2390 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2391 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2392 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2393 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2394 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2395 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2396 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2397 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2398 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2399 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2400 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2401 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2402 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2404 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2405 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2406 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2407 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2408 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2409 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2410 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2411 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2412 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2413 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2414 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2416 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2417 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2418 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2420 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2421 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2422 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2423 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2424 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2425 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2426 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2428
2429 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2432 NUM_BANKS(ADDR_SURF_8_BANK));
2433 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2435 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2436 NUM_BANKS(ADDR_SURF_8_BANK));
2437 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2440 NUM_BANKS(ADDR_SURF_8_BANK));
2441 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2442 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2443 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2444 NUM_BANKS(ADDR_SURF_8_BANK));
2445 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2448 NUM_BANKS(ADDR_SURF_8_BANK));
2449 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2452 NUM_BANKS(ADDR_SURF_8_BANK));
2453 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2456 NUM_BANKS(ADDR_SURF_8_BANK));
2457 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2459 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2460 NUM_BANKS(ADDR_SURF_8_BANK));
2461 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2464 NUM_BANKS(ADDR_SURF_8_BANK));
2465 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2468 NUM_BANKS(ADDR_SURF_8_BANK));
2469 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2471 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2472 NUM_BANKS(ADDR_SURF_8_BANK));
2473 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2476 NUM_BANKS(ADDR_SURF_8_BANK));
2477 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2480 NUM_BANKS(ADDR_SURF_8_BANK));
2481 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2484 NUM_BANKS(ADDR_SURF_4_BANK));
2485
2486 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2487 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2488
2489 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2490 if (reg_offset != 7)
2491 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2492
5f2e816b 2493 break;
aaa36a97 2494 case CHIP_TONGA:
90bea0ab
TSD		 2495 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2496 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2497 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2498 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2499 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2500 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2502 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2503 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2504 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2506 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2507 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2508 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2510 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2511 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2512 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2514 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2515 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2516 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2518 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2519 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2520 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2523 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2524 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2526 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2527 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2528 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2529 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2530 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2531 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2532 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2533 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2534 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2535 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2536 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2537 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2538 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2539 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2540 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2541 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2542 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2543 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2544 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2545 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2546 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2547 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2548 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2549 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2550 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2551 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2552 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2553 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2554 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2555 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2556 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2557 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2558 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2559 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2560 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2561 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2562 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2563 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2564 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2565 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2566 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2567 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2568 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2569 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2570 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2571 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2572 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2573 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2574 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2575 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2576 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2577 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2578 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2579 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2580 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2581 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2582 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2583 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2584 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2585 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2586 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2587 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2588 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2589 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2590 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2591 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2593 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2594 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2595 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2596 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2597 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2598 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2599 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2600 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2601 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2602 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2603 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2604 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2605 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2606 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2607 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2608 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2609 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2610 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2611 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2612 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2613 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2614 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2615 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2616 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2617
2618 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2621 NUM_BANKS(ADDR_SURF_16_BANK));
2622 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2623 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2624 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2625 NUM_BANKS(ADDR_SURF_16_BANK));
2626 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2629 NUM_BANKS(ADDR_SURF_16_BANK));
2630 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2631 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2632 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2633 NUM_BANKS(ADDR_SURF_16_BANK));
2634 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2637 NUM_BANKS(ADDR_SURF_16_BANK));
2638 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2640 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2641 NUM_BANKS(ADDR_SURF_16_BANK));
2642 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2643 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2644 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2645 NUM_BANKS(ADDR_SURF_16_BANK));
2646 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2649 NUM_BANKS(ADDR_SURF_16_BANK));
2650 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2653 NUM_BANKS(ADDR_SURF_16_BANK));
2654 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2657 NUM_BANKS(ADDR_SURF_16_BANK));
2658 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2659 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2660 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2661 NUM_BANKS(ADDR_SURF_16_BANK));
2662 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2665 NUM_BANKS(ADDR_SURF_8_BANK));
2666 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2667 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2668 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2669 NUM_BANKS(ADDR_SURF_4_BANK));
2670 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2673 NUM_BANKS(ADDR_SURF_4_BANK));
2674
2675 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2676 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2677
2678 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2679 if (reg_offset != 7)
2680 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2681
68182d90 2682 break;
2cc0c0b5 2683 case CHIP_POLARIS11:
68182d90
FC		 2684 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2685 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2686 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2687 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2688 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2689 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2690 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2691 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2692 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2693 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2694 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2695 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2696 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2697 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2698 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2699 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2700 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2701 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2702 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2703 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2704 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2705 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2706 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2707 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2708 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2709 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2710 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2711 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2712 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2713 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2715 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2716 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2717 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2718 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2719 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2720 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2721 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2722 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2723 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2724 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2725 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2726 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2727 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2728 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2729 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2730 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2731 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2732 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2733 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2734 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2735 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2736 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2737 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2738 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2739 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2740 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2741 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2742 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2743 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2744 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2745 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2746 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2747 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2748 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2749 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2750 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2751 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2752 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2753 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2754 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2755 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2756 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2757 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2758 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2759 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2760 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2761 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2762 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2763 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2764 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2765 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2766 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2767 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2768 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2769 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2770 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2771 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2772 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2773 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2774 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2775 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2776 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2777 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2778 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2779 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2780 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2781 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2782 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2783 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2784 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2785 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2786 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2787 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2788 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2789 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2790 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2791 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2792 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2793 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2794 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2795 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2796 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2797 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2798 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2799 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2800 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2801 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2802 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2803 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2804 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2805 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2806
2807 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2808 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2809 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2810 NUM_BANKS(ADDR_SURF_16_BANK));
2811
2812 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2813 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2814 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2815 NUM_BANKS(ADDR_SURF_16_BANK));
2816
2817 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2820 NUM_BANKS(ADDR_SURF_16_BANK));
2821
2822 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2825 NUM_BANKS(ADDR_SURF_16_BANK));
2826
2827 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2828 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2829 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2830 NUM_BANKS(ADDR_SURF_16_BANK));
2831
2832 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2835 NUM_BANKS(ADDR_SURF_16_BANK));
2836
2837 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2838 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2839 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2840 NUM_BANKS(ADDR_SURF_16_BANK));
2841
2842 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2843 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2844 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2845 NUM_BANKS(ADDR_SURF_16_BANK));
2846
2847 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2850 NUM_BANKS(ADDR_SURF_16_BANK));
2851
2852 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2853 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2854 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2855 NUM_BANKS(ADDR_SURF_16_BANK));
2856
2857 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2858 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2859 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2860 NUM_BANKS(ADDR_SURF_16_BANK));
2861
2862 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2863 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2864 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2865 NUM_BANKS(ADDR_SURF_16_BANK));
2866
2867 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2868 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2869 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2870 NUM_BANKS(ADDR_SURF_8_BANK));
2871
2872 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2873 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2874 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2875 NUM_BANKS(ADDR_SURF_4_BANK));
2876
2877 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2878 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2879
2880 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2881 if (reg_offset != 7)
2882 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2883
2884 break;
2cc0c0b5 2885 case CHIP_POLARIS10:
68182d90
FC		 2886 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2887 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2888 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2889 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2890 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2891 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2892 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2893 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2894 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2895 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2896 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2897 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2898 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2899 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2900 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2901 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2902 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2903 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2904 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2905 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2906 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2907 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2908 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2909 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2910 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2911 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2912 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2913 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2914 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2915 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2916 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2917 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2918 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2919 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2920 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2921 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2922 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2923 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2924 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2925 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2926 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2927 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2928 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2929 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2930 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2931 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2932 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2933 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2934 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2935 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2936 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2937 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2938 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2939 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2940 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2941 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2942 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2943 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2944 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2945 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2946 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2947 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2948 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2949 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2950 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2951 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2952 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2953 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2954 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2955 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2956 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2957 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2958 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2959 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2960 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2961 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2962 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2963 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2964 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2965 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2966 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2967 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2968 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2969 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2970 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2971 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2972 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2973 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2974 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2975 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2976 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2977 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2978 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2979 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2980 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2981 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2982 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2983 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2984 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2985 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2986 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2987 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2988 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2989 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2990 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2991 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2992 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2993 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2994 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2995 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2996 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2997 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2998 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2999 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3000 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3001 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3002 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3003 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3004 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3005 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
3006 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3007 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3008
3009 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3010 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3011 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3012 NUM_BANKS(ADDR_SURF_16_BANK));
3013
3014 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3015 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3016 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3017 NUM_BANKS(ADDR_SURF_16_BANK));
3018
3019 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3020 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3021 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3022 NUM_BANKS(ADDR_SURF_16_BANK));
3023
3024 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3025 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3026 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3027 NUM_BANKS(ADDR_SURF_16_BANK));
3028
3029 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3032 NUM_BANKS(ADDR_SURF_16_BANK));
3033
3034 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3035 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3036 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3037 NUM_BANKS(ADDR_SURF_16_BANK));
3038
3039 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3040 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3041 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3042 NUM_BANKS(ADDR_SURF_16_BANK));
3043
3044 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3045 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3046 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3047 NUM_BANKS(ADDR_SURF_16_BANK));
3048
3049 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3050 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3051 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3052 NUM_BANKS(ADDR_SURF_16_BANK));
3053
3054 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3055 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3056 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3057 NUM_BANKS(ADDR_SURF_16_BANK));
3058
3059 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3060 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3061 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3062 NUM_BANKS(ADDR_SURF_16_BANK));
3063
3064 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3065 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3066 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3067 NUM_BANKS(ADDR_SURF_8_BANK));
3068
3069 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3070 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3071 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3072 NUM_BANKS(ADDR_SURF_4_BANK));
3073
3074 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3075 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3076 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3077 NUM_BANKS(ADDR_SURF_4_BANK));
3078
3079 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3080 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3081
3082 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3083 if (reg_offset != 7)
3084 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3085
aaa36a97 3086 break;
e3c7656c 3087 case CHIP_STONEY:
90bea0ab
TSD		 3088 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3089 PIPE_CONFIG(ADDR_SURF_P2) |
3090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3091 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3092 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3093 PIPE_CONFIG(ADDR_SURF_P2) |
3094 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3095 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3096 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3097 PIPE_CONFIG(ADDR_SURF_P2) |
3098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3099 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3100 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3101 PIPE_CONFIG(ADDR_SURF_P2) |
3102 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3103 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3104 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3105 PIPE_CONFIG(ADDR_SURF_P2) |
3106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3107 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3108 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3109 PIPE_CONFIG(ADDR_SURF_P2) |
3110 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3111 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3112 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3113 PIPE_CONFIG(ADDR_SURF_P2) |
3114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3115 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3116 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3117 PIPE_CONFIG(ADDR_SURF_P2));
3118 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3119 PIPE_CONFIG(ADDR_SURF_P2) |
3120 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3122 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3123 PIPE_CONFIG(ADDR_SURF_P2) |
3124 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3126 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3127 PIPE_CONFIG(ADDR_SURF_P2) |
3128 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3130 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3131 PIPE_CONFIG(ADDR_SURF_P2) |
3132 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3134 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3135 PIPE_CONFIG(ADDR_SURF_P2) |
3136 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3138 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3139 PIPE_CONFIG(ADDR_SURF_P2) |
3140 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3141 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3142 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3143 PIPE_CONFIG(ADDR_SURF_P2) |
3144 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3145 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3146 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3147 PIPE_CONFIG(ADDR_SURF_P2) |
3148 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3150 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3151 PIPE_CONFIG(ADDR_SURF_P2) |
3152 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3154 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3155 PIPE_CONFIG(ADDR_SURF_P2) |
3156 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3157 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3158 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3159 PIPE_CONFIG(ADDR_SURF_P2) |
3160 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3161 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3162 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3163 PIPE_CONFIG(ADDR_SURF_P2) |
3164 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3165 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3166 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3167 PIPE_CONFIG(ADDR_SURF_P2) |
3168 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3169 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3170 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3171 PIPE_CONFIG(ADDR_SURF_P2) |
3172 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3173 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3174 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3175 PIPE_CONFIG(ADDR_SURF_P2) |
3176 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3177 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3178 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3179 PIPE_CONFIG(ADDR_SURF_P2) |
3180 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3181 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3182 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3183 PIPE_CONFIG(ADDR_SURF_P2) |
3184 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3185 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3186 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3187 PIPE_CONFIG(ADDR_SURF_P2) |
3188 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3189 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3190
3191 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3192 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3193 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3194 NUM_BANKS(ADDR_SURF_8_BANK));
3195 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3198 NUM_BANKS(ADDR_SURF_8_BANK));
3199 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3202 NUM_BANKS(ADDR_SURF_8_BANK));
3203 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3206 NUM_BANKS(ADDR_SURF_8_BANK));
3207 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3210 NUM_BANKS(ADDR_SURF_8_BANK));
3211 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3214 NUM_BANKS(ADDR_SURF_8_BANK));
3215 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3216 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3217 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3218 NUM_BANKS(ADDR_SURF_8_BANK));
3219 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3222 NUM_BANKS(ADDR_SURF_16_BANK));
3223 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3224 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3225 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3226 NUM_BANKS(ADDR_SURF_16_BANK));
3227 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3230 NUM_BANKS(ADDR_SURF_16_BANK));
3231 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3232 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3233 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3234 NUM_BANKS(ADDR_SURF_16_BANK));
3235 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3236 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3237 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3238 NUM_BANKS(ADDR_SURF_16_BANK));
3239 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3242 NUM_BANKS(ADDR_SURF_16_BANK));
3243 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3244 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3245 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3246 NUM_BANKS(ADDR_SURF_8_BANK));
3247
3248 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3249 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3250 reg_offset != 23)
3251 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3252
3253 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3254 if (reg_offset != 7)
3255 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3256
e3c7656c 3257 break;
aaa36a97 3258 default:
90bea0ab
TSD		 3259 dev_warn(adev->dev,
3260 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3261 adev->asic_type);
3262
3263 case CHIP_CARRIZO:
3264 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3265 PIPE_CONFIG(ADDR_SURF_P2) |
3266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3267 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3268 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3269 PIPE_CONFIG(ADDR_SURF_P2) |
3270 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3271 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3272 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3273 PIPE_CONFIG(ADDR_SURF_P2) |
3274 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3275 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3276 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3277 PIPE_CONFIG(ADDR_SURF_P2) |
3278 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3279 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3280 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3281 PIPE_CONFIG(ADDR_SURF_P2) |
3282 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3283 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3284 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3285 PIPE_CONFIG(ADDR_SURF_P2) |
3286 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3287 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3288 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3289 PIPE_CONFIG(ADDR_SURF_P2) |
3290 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3291 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3292 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3293 PIPE_CONFIG(ADDR_SURF_P2));
3294 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3295 PIPE_CONFIG(ADDR_SURF_P2) |
3296 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3298 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3299 PIPE_CONFIG(ADDR_SURF_P2) |
3300 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3302 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3303 PIPE_CONFIG(ADDR_SURF_P2) |
3304 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3306 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3307 PIPE_CONFIG(ADDR_SURF_P2) |
3308 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3310 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3311 PIPE_CONFIG(ADDR_SURF_P2) |
3312 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3314 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3315 PIPE_CONFIG(ADDR_SURF_P2) |
3316 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3318 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3319 PIPE_CONFIG(ADDR_SURF_P2) |
3320 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3322 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3323 PIPE_CONFIG(ADDR_SURF_P2) |
3324 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3325 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3326 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3327 PIPE_CONFIG(ADDR_SURF_P2) |
3328 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3330 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3331 PIPE_CONFIG(ADDR_SURF_P2) |
3332 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3334 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3335 PIPE_CONFIG(ADDR_SURF_P2) |
3336 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3338 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3339 PIPE_CONFIG(ADDR_SURF_P2) |
3340 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3341 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3342 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3343 PIPE_CONFIG(ADDR_SURF_P2) |
3344 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3345 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3346 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3347 PIPE_CONFIG(ADDR_SURF_P2) |
3348 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3349 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3350 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3351 PIPE_CONFIG(ADDR_SURF_P2) |
3352 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3353 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3354 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3355 PIPE_CONFIG(ADDR_SURF_P2) |
3356 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3357 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3358 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3359 PIPE_CONFIG(ADDR_SURF_P2) |
3360 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3361 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3362 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3363 PIPE_CONFIG(ADDR_SURF_P2) |
3364 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3365 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3366
3367 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3370 NUM_BANKS(ADDR_SURF_8_BANK));
3371 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3374 NUM_BANKS(ADDR_SURF_8_BANK));
3375 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3378 NUM_BANKS(ADDR_SURF_8_BANK));
3379 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3382 NUM_BANKS(ADDR_SURF_8_BANK));
3383 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3386 NUM_BANKS(ADDR_SURF_8_BANK));
3387 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3390 NUM_BANKS(ADDR_SURF_8_BANK));
3391 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3394 NUM_BANKS(ADDR_SURF_8_BANK));
3395 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3396 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3397 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3398 NUM_BANKS(ADDR_SURF_16_BANK));
3399 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3400 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3401 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3402 NUM_BANKS(ADDR_SURF_16_BANK));
3403 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3404 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3405 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3406 NUM_BANKS(ADDR_SURF_16_BANK));
3407 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3408 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3409 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3410 NUM_BANKS(ADDR_SURF_16_BANK));
3411 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3412 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3413 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3414 NUM_BANKS(ADDR_SURF_16_BANK));
3415 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3416 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3417 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3418 NUM_BANKS(ADDR_SURF_16_BANK));
3419 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3420 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3421 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3422 NUM_BANKS(ADDR_SURF_8_BANK));
3423
3424 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3425 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3426 reg_offset != 23)
3427 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3428
3429 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3430 if (reg_offset != 7)
3431 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3432
3433 break;
aaa36a97
AD		 3434 }
3435}
3436
05fb7291 3437static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
9559ef5b 3438 u32 se_num, u32 sh_num, u32 instance)
aaa36a97 3439{
9559ef5b
TSD		 3440 u32 data;
3441
3442 if (instance == 0xffffffff)
3443 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3444 else
3445 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
aaa36a97 3446
5003f278 3447 if (se_num == 0xffffffff)
aaa36a97 3448 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
5003f278 3449 else
aaa36a97 3450 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
5003f278
TSD		 3451
3452 if (sh_num == 0xffffffff)
3453 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3454 else
aaa36a97 3455 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
5003f278 3456
aaa36a97
AD		 3457 WREG32(mmGRBM_GFX_INDEX, data);
3458}
3459
8f8e00c1
AD		 3460static u32 gfx_v8_0_create_bitmask(u32 bit_width)
3461{
3462 return (u32)((1ULL << bit_width) - 1);
3463}
3464
3465static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
aaa36a97
AD		 3466{
3467 u32 data, mask;
3468
5003f278
TSD		 3469 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
3470 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
aaa36a97 3471
5003f278 3472 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
aaa36a97 3473
8f8e00c1
AD		 3474 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
3475 adev->gfx.config.max_sh_per_se);
aaa36a97 3476
8f8e00c1 3477 return (~data) & mask;
aaa36a97
AD		 3478}
3479
167ac573
HR		 3480static void
3481gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
3482{
3483 switch (adev->asic_type) {
3484 case CHIP_FIJI:
3485 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
3486 RB_XSEL2(1) | PKR_MAP(2) |
3487 PKR_XSEL(1) | PKR_YSEL(1) |
3488 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
3489 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
3490 SE_PAIR_YSEL(2);
3491 break;
3492 case CHIP_TONGA:
3493 case CHIP_POLARIS10:
3494 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3495 SE_XSEL(1) | SE_YSEL(1);
3496 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
3497 SE_PAIR_YSEL(2);
3498 break;
3499 case CHIP_TOPAZ:
3500 case CHIP_CARRIZO:
3501 *rconf |= RB_MAP_PKR0(2);
3502 *rconf1 |= 0x0;
3503 break;
3504 case CHIP_POLARIS11:
3505 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3506 SE_XSEL(1) | SE_YSEL(1);
3507 *rconf1 |= 0x0;
3508 break;
3509 case CHIP_STONEY:
3510 *rconf |= 0x0;
3511 *rconf1 |= 0x0;
3512 break;
3513 default:
3514 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
3515 break;
3516 }
3517}
3518
3519static void
3520gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
3521 u32 raster_config, u32 raster_config_1,
3522 unsigned rb_mask, unsigned num_rb)
3523{
3524 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
3525 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
3526 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
3527 unsigned rb_per_se = num_rb / num_se;
3528 unsigned se_mask[4];
3529 unsigned se;
3530
3531 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3532 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3533 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3534 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3535
3536 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
3537 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
3538 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
3539
3540 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3541 (!se_mask[2] && !se_mask[3]))) {
3542 raster_config_1 &= ~SE_PAIR_MAP_MASK;
3543
3544 if (!se_mask[0] && !se_mask[1]) {
3545 raster_config_1 |=
3546 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
3547 } else {
3548 raster_config_1 |=
3549 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
3550 }
3551 }
3552
3553 for (se = 0; se < num_se; se++) {
3554 unsigned raster_config_se = raster_config;
3555 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3556 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3557 int idx = (se / 2) * 2;
3558
3559 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3560 raster_config_se &= ~SE_MAP_MASK;
3561
3562 if (!se_mask[idx]) {
3563 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
3564 } else {
3565 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
3566 }
3567 }
3568
3569 pkr0_mask &= rb_mask;
3570 pkr1_mask &= rb_mask;
3571 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3572 raster_config_se &= ~PKR_MAP_MASK;
3573
3574 if (!pkr0_mask) {
3575 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
3576 } else {
3577 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
3578 }
3579 }
3580
3581 if (rb_per_se >= 2) {
3582 unsigned rb0_mask = 1 << (se * rb_per_se);
3583 unsigned rb1_mask = rb0_mask << 1;
3584
3585 rb0_mask &= rb_mask;
3586 rb1_mask &= rb_mask;
3587 if (!rb0_mask || !rb1_mask) {
3588 raster_config_se &= ~RB_MAP_PKR0_MASK;
3589
3590 if (!rb0_mask) {
3591 raster_config_se |=
3592 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
3593 } else {
3594 raster_config_se |=
3595 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
3596 }
3597 }
3598
3599 if (rb_per_se > 2) {
3600 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3601 rb1_mask = rb0_mask << 1;
3602 rb0_mask &= rb_mask;
3603 rb1_mask &= rb_mask;
3604 if (!rb0_mask || !rb1_mask) {
3605 raster_config_se &= ~RB_MAP_PKR1_MASK;
3606
3607 if (!rb0_mask) {
3608 raster_config_se |=
3609 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
3610 } else {
3611 raster_config_se |=
3612 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
3613 }
3614 }
3615 }
3616 }
3617
3618 /* GRBM_GFX_INDEX has a different offset on VI */
3619 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
3620 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
3621 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3622 }
3623
3624 /* GRBM_GFX_INDEX has a different offset on VI */
3625 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3626}
3627
8f8e00c1 3628static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
aaa36a97
AD		 3629{
3630 int i, j;
aac1e3ca 3631 u32 data;
167ac573 3632 u32 raster_config = 0, raster_config_1 = 0;
8f8e00c1 3633 u32 active_rbs = 0;
6157bd7a
FC		 3634 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3635 adev->gfx.config.max_sh_per_se;
167ac573 3636 unsigned num_rb_pipes;
aaa36a97
AD		 3637
3638 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 3639 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3640 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9559ef5b 3641 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
8f8e00c1
AD		 3642 data = gfx_v8_0_get_rb_active_bitmap(adev);
3643 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
6157bd7a 3644 rb_bitmap_width_per_sh);
aaa36a97
AD		 3645 }
3646 }
9559ef5b 3647 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
aaa36a97 3648
8f8e00c1 3649 adev->gfx.config.backend_enable_mask = active_rbs;
aac1e3ca 3650 adev->gfx.config.num_rbs = hweight32(active_rbs);
167ac573
HR		 3651
3652 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
3653 adev->gfx.config.max_shader_engines, 16);
3654
3655 gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
3656
3657 if (!adev->gfx.config.backend_enable_mask ||
3658 adev->gfx.config.num_rbs >= num_rb_pipes) {
3659 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
3660 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3661 } else {
3662 gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
3663 adev->gfx.config.backend_enable_mask,
3664 num_rb_pipes);
3665 }
3666
392f0c77
AD		 3667 /* cache the values for userspace */
3668 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3669 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3670 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3671 adev->gfx.config.rb_config[i][j].rb_backend_disable =
3672 RREG32(mmCC_RB_BACKEND_DISABLE);
3673 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
3674 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3675 adev->gfx.config.rb_config[i][j].raster_config =
3676 RREG32(mmPA_SC_RASTER_CONFIG);
3677 adev->gfx.config.rb_config[i][j].raster_config_1 =
3678 RREG32(mmPA_SC_RASTER_CONFIG_1);
3679 }
3680 }
3681 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
167ac573 3682 mutex_unlock(&adev->grbm_idx_mutex);
aaa36a97
AD		 3683}
3684
cd06bf68 3685/**
35c7a952 3686 * gfx_v8_0_init_compute_vmid - gart enable
cd06bf68
BG		 3687 *
3688 * @rdev: amdgpu_device pointer
3689 *
3690 * Initialize compute vmid sh_mem registers
3691 *
3692 */
3693#define DEFAULT_SH_MEM_BASES (0x6000)
3694#define FIRST_COMPUTE_VMID (8)
3695#define LAST_COMPUTE_VMID (16)
35c7a952 3696static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
cd06bf68
BG		 3697{
3698 int i;
3699 uint32_t sh_mem_config;
3700 uint32_t sh_mem_bases;
3701
3702 /*
3703 * Configure apertures:
3704 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3705 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3706 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3707 */
3708 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3709
3710 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3711 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3712 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3713 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3714 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3715 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3716
3717 mutex_lock(&adev->srbm_mutex);
3718 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
3719 vi_srbm_select(adev, 0, 0, 0, i);
3720 /* CP and shaders */
3721 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3722 WREG32(mmSH_MEM_APE1_BASE, 1);
3723 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3724 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3725 }
3726 vi_srbm_select(adev, 0, 0, 0, 0);
3727 mutex_unlock(&adev->srbm_mutex);
3728}
3729
aaa36a97
AD		 3730static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
3731{
aaa36a97
AD		 3732 u32 tmp;
3733 int i;
3734
61cb8cef 3735 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
0bde3a95
AD		 3736 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3737 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3738 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
aaa36a97
AD		 3739
3740 gfx_v8_0_tiling_mode_table_init(adev);
8f8e00c1 3741 gfx_v8_0_setup_rb(adev);
7dae69a2 3742 gfx_v8_0_get_cu_info(adev);
aaa36a97
AD		 3743
3744 /* XXX SH_MEM regs */
3745 /* where to put LDS, scratch, GPUVM in FSA64 space */
3746 mutex_lock(&adev->srbm_mutex);
3747 for (i = 0; i < 16; i++) {
3748 vi_srbm_select(adev, 0, 0, 0, i);
3749 /* CP and shaders */
3750 if (i == 0) {
3751 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3752 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
0bde3a95 3753 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165 3754 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 3755 WREG32(mmSH_MEM_CONFIG, tmp);
3756 } else {
3757 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3758 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
0bde3a95 3759 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165 3760 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 3761 WREG32(mmSH_MEM_CONFIG, tmp);
3762 }
3763
3764 WREG32(mmSH_MEM_APE1_BASE, 1);
3765 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3766 WREG32(mmSH_MEM_BASES, 0);
3767 }
3768 vi_srbm_select(adev, 0, 0, 0, 0);
3769 mutex_unlock(&adev->srbm_mutex);
3770
35c7a952 3771 gfx_v8_0_init_compute_vmid(adev);
cd06bf68 3772
aaa36a97
AD		 3773 mutex_lock(&adev->grbm_idx_mutex);
3774 /*
3775 * making sure that the following register writes will be broadcasted
3776 * to all the shaders
3777 */
9559ef5b 3778 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
aaa36a97
AD		 3779
3780 WREG32(mmPA_SC_FIFO_SIZE,
3781 (adev->gfx.config.sc_prim_fifo_size_frontend <<
3782 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3783 (adev->gfx.config.sc_prim_fifo_size_backend <<
3784 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3785 (adev->gfx.config.sc_hiz_tile_fifo_size <<
3786 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3787 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3788 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3789 mutex_unlock(&adev->grbm_idx_mutex);
3790
3791}
3792
3793static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3794{
3795 u32 i, j, k;
3796 u32 mask;
3797
3798 mutex_lock(&adev->grbm_idx_mutex);
3799 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3800 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9559ef5b 3801 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
aaa36a97
AD		 3802 for (k = 0; k < adev->usec_timeout; k++) {
3803 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3804 break;
3805 udelay(1);
3806 }
3807 }
3808 }
9559ef5b 3809 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
aaa36a97
AD		 3810 mutex_unlock(&adev->grbm_idx_mutex);
3811
3812 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3813 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3814 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3815 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3816 for (k = 0; k < adev->usec_timeout; k++) {
3817 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3818 break;
3819 udelay(1);
3820 }
3821}
3822
3823static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3824 bool enable)
3825{
3826 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3827
0d07db7e
TSD		 3828 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3829 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3830 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3831 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3832
aaa36a97
AD		 3833 WREG32(mmCP_INT_CNTL_RING0, tmp);
3834}
3835
2b6cd977
EH		 3836static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3837{
3838 /* csib */
3839 WREG32(mmRLC_CSIB_ADDR_HI,
3840 adev->gfx.rlc.clear_state_gpu_addr >> 32);
3841 WREG32(mmRLC_CSIB_ADDR_LO,
3842 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3843 WREG32(mmRLC_CSIB_LENGTH,
3844 adev->gfx.rlc.clear_state_size);
3845}
3846
3847static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3848 int ind_offset,
3849 int list_size,
3850 int *unique_indices,
3851 int *indices_count,
3852 int max_indices,
3853 int *ind_start_offsets,
3854 int *offset_count,
3855 int max_offset)
3856{
3857 int indices;
3858 bool new_entry = true;
3859
3860 for (; ind_offset < list_size; ind_offset++) {
3861
3862 if (new_entry) {
3863 new_entry = false;
3864 ind_start_offsets[*offset_count] = ind_offset;
3865 *offset_count = *offset_count + 1;
3866 BUG_ON(*offset_count >= max_offset);
3867 }
3868
3869 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3870 new_entry = true;
3871 continue;
3872 }
3873
3874 ind_offset += 2;
3875
3876 /* look for the matching indice */
3877 for (indices = 0;
3878 indices < *indices_count;
3879 indices++) {
3880 if (unique_indices[indices] ==
3881 register_list_format[ind_offset])
3882 break;
3883 }
3884
3885 if (indices >= *indices_count) {
3886 unique_indices[*indices_count] =
3887 register_list_format[ind_offset];
3888 indices = *indices_count;
3889 *indices_count = *indices_count + 1;
3890 BUG_ON(*indices_count >= max_indices);
3891 }
3892
3893 register_list_format[ind_offset] = indices;
3894 }
3895}
3896
3897static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3898{
3899 int i, temp, data;
3900 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3901 int indices_count = 0;
3902 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3903 int offset_count = 0;
3904
3905 int list_size;
3906 unsigned int *register_list_format =
3907 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3f12325a 3908 if (!register_list_format)
2b6cd977
EH		 3909 return -ENOMEM;
3910 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
3911 adev->gfx.rlc.reg_list_format_size_bytes);
3912
3913 gfx_v8_0_parse_ind_reg_list(register_list_format,
3914 RLC_FormatDirectRegListLength,
3915 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3916 unique_indices,
3917 &indices_count,
3918 sizeof(unique_indices) / sizeof(int),
3919 indirect_start_offsets,
3920 &offset_count,
3921 sizeof(indirect_start_offsets)/sizeof(int));
3922
3923 /* save and restore list */
61cb8cef 3924 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
2b6cd977
EH		 3925
3926 WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3927 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3928 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
3929
3930 /* indirect list */
3931 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
3932 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
3933 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3934
3935 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
3936 list_size = list_size >> 1;
3937 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
3938 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
3939
3940 /* starting offsets starts */
3941 WREG32(mmRLC_GPM_SCRATCH_ADDR,
3942 adev->gfx.rlc.starting_offsets_start);
3943 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
3944 WREG32(mmRLC_GPM_SCRATCH_DATA,
3945 indirect_start_offsets[i]);
3946
3947 /* unique indices */
3948 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
3949 data = mmRLC_SRM_INDEX_CNTL_DATA_0;
3950 for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
3951 amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
3952 amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
3953 }
3954 kfree(register_list_format);
3955
3956 return 0;
3957}
3958
3959static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
3960{
61cb8cef 3961 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
2b6cd977
EH		 3962}
3963
fb16007b 3964static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
f4bfffdd
EH		 3965{
3966 uint32_t data;
3967
3968 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
fb16007b
AD		 3969 AMD_PG_SUPPORT_GFX_SMG |
3970 AMD_PG_SUPPORT_GFX_DMG)) {
61cb8cef 3971 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
f4bfffdd 3972
61cb8cef
TSD		 3973 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
3974 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
3975 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
3976 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
3977 WREG32(mmRLC_PG_DELAY, data);
f4bfffdd 3978
61cb8cef
TSD		 3979 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
3980 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
f4bfffdd
EH		 3981 }
3982}
3983
2c547165
AD		 3984static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
3985 bool enable)
3986{
61cb8cef 3987 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
2c547165
AD		 3988}
3989
3990static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
3991 bool enable)
3992{
61cb8cef 3993 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
2c547165
AD		 3994}
3995
3996static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
3997{
61cb8cef 3998 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0);
2c547165
AD		 3999}
4000
2b6cd977
EH		 4001static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
4002{
4003 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4004 AMD_PG_SUPPORT_GFX_SMG |
4005 AMD_PG_SUPPORT_GFX_DMG |
4006 AMD_PG_SUPPORT_CP |
4007 AMD_PG_SUPPORT_GDS |
4008 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4009 gfx_v8_0_init_csb(adev);
4010 gfx_v8_0_init_save_restore_list(adev);
4011 gfx_v8_0_enable_save_restore_machine(adev);
f4bfffdd 4012
fb16007b
AD		 4013 if ((adev->asic_type == CHIP_CARRIZO) ||
4014 (adev->asic_type == CHIP_STONEY)) {
4015 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4016 gfx_v8_0_init_power_gating(adev);
4017 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2c547165
AD		 4018 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
4019 cz_enable_sck_slow_down_on_power_up(adev, true);
4020 cz_enable_sck_slow_down_on_power_down(adev, true);
4021 } else {
4022 cz_enable_sck_slow_down_on_power_up(adev, false);
4023 cz_enable_sck_slow_down_on_power_down(adev, false);
4024 }
4025 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
4026 cz_enable_cp_power_gating(adev, true);
4027 else
4028 cz_enable_cp_power_gating(adev, false);
fb16007b
AD		 4029 } else if (adev->asic_type == CHIP_POLARIS11) {
4030 gfx_v8_0_init_power_gating(adev);
4031 }
2b6cd977
EH		 4032 }
4033}
4034
761c2e82 4035static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
aaa36a97 4036{
61cb8cef 4037 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
aaa36a97
AD		 4038
4039 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
aaa36a97
AD		 4040 gfx_v8_0_wait_for_rlc_serdes(adev);
4041}
4042
4043static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
4044{
61cb8cef 4045 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
aaa36a97 4046 udelay(50);
61cb8cef
TSD		 4047
4048 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
aaa36a97
AD		 4049 udelay(50);
4050}
4051
4052static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
4053{
61cb8cef 4054 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
aaa36a97
AD		 4055
4056 /* carrizo do enable cp interrupt after cp inited */
e3c7656c 4057 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 4058 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4059
4060 udelay(50);
4061}
4062
4063static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
4064{
4065 const struct rlc_firmware_header_v2_0 *hdr;
4066 const __le32 *fw_data;
4067 unsigned i, fw_size;
4068
4069 if (!adev->gfx.rlc_fw)
4070 return -EINVAL;
4071
4072 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4073 amdgpu_ucode_print_rlc_hdr(&hdr->header);
aaa36a97
AD		 4074
4075 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4076 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4077 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4078
4079 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
4080 for (i = 0; i < fw_size; i++)
4081 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
4082 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4083
4084 return 0;
4085}
4086
4087static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
4088{
4089 int r;
6ae81452 4090 u32 tmp;
aaa36a97
AD		 4091
4092 gfx_v8_0_rlc_stop(adev);
4093
4094 /* disable CG */
6ae81452
AD		 4095 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL);
4096 tmp &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
4097 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4098 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
2cc0c0b5 4099 if (adev->asic_type == CHIP_POLARIS11 ||
6ae81452
AD		 4100 adev->asic_type == CHIP_POLARIS10) {
4101 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);
4102 tmp &= ~0x3;
4103 WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);
4104 }
aaa36a97
AD		 4105
4106 /* disable PG */
4107 WREG32(mmRLC_PG_CNTL, 0);
4108
4109 gfx_v8_0_rlc_reset(adev);
2b6cd977
EH		 4110 gfx_v8_0_init_pg(adev);
4111
e61710c5 4112 if (!adev->pp_enabled) {
ba5c2a87
RZ		 4113 if (!adev->firmware.smu_load) {
4114 /* legacy rlc firmware loading */
4115 r = gfx_v8_0_rlc_load_microcode(adev);
4116 if (r)
4117 return r;
4118 } else {
4119 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4120 AMDGPU_UCODE_ID_RLC_G);
4121 if (r)
4122 return -EINVAL;
4123 }
aaa36a97
AD		 4124 }
4125
4126 gfx_v8_0_rlc_start(adev);
4127
4128 return 0;
4129}
4130
4131static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
4132{
4133 int i;
4134 u32 tmp = RREG32(mmCP_ME_CNTL);
4135
4136 if (enable) {
4137 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4138 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4139 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4140 } else {
4141 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4142 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4143 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
4144 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4145 adev->gfx.gfx_ring[i].ready = false;
4146 }
4147 WREG32(mmCP_ME_CNTL, tmp);
4148 udelay(50);
4149}
4150
4151static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
4152{
4153 const struct gfx_firmware_header_v1_0 *pfp_hdr;
4154 const struct gfx_firmware_header_v1_0 *ce_hdr;
4155 const struct gfx_firmware_header_v1_0 *me_hdr;
4156 const __le32 *fw_data;
4157 unsigned i, fw_size;
4158
4159 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
4160 return -EINVAL;
4161
4162 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
4163 adev->gfx.pfp_fw->data;
4164 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
4165 adev->gfx.ce_fw->data;
4166 me_hdr = (const struct gfx_firmware_header_v1_0 *)
4167 adev->gfx.me_fw->data;
4168
4169 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
4170 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
4171 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
aaa36a97
AD		 4172
4173 gfx_v8_0_cp_gfx_enable(adev, false);
4174
4175 /* PFP */
4176 fw_data = (const __le32 *)
4177 (adev->gfx.pfp_fw->data +
4178 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
4179 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
4180 WREG32(mmCP_PFP_UCODE_ADDR, 0);
4181 for (i = 0; i < fw_size; i++)
4182 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
4183 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
4184
4185 /* CE */
4186 fw_data = (const __le32 *)
4187 (adev->gfx.ce_fw->data +
4188 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
4189 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
4190 WREG32(mmCP_CE_UCODE_ADDR, 0);
4191 for (i = 0; i < fw_size; i++)
4192 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
4193 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
4194
4195 /* ME */
4196 fw_data = (const __le32 *)
4197 (adev->gfx.me_fw->data +
4198 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
4199 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
4200 WREG32(mmCP_ME_RAM_WADDR, 0);
4201 for (i = 0; i < fw_size; i++)
4202 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
4203 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
4204
4205 return 0;
4206}
4207
4208static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
4209{
4210 u32 count = 0;
4211 const struct cs_section_def *sect = NULL;
4212 const struct cs_extent_def *ext = NULL;
4213
4214 /* begin clear state */
4215 count += 2;
4216 /* context control state */
4217 count += 3;
4218
4219 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4220 for (ext = sect->section; ext->extent != NULL; ++ext) {
4221 if (sect->id == SECT_CONTEXT)
4222 count += 2 + ext->reg_count;
4223 else
4224 return 0;
4225 }
4226 }
4227 /* pa_sc_raster_config/pa_sc_raster_config1 */
4228 count += 4;
4229 /* end clear state */
4230 count += 2;
4231 /* clear state */
4232 count += 2;
4233
4234 return count;
4235}
4236
4237static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
4238{
4239 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
4240 const struct cs_section_def *sect = NULL;
4241 const struct cs_extent_def *ext = NULL;
4242 int r, i;
4243
4244 /* init the CP */
4245 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
4246 WREG32(mmCP_ENDIAN_SWAP, 0);
4247 WREG32(mmCP_DEVICE_ID, 1);
4248
4249 gfx_v8_0_cp_gfx_enable(adev, true);
4250
a27de35c 4251 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
aaa36a97
AD		 4252 if (r) {
4253 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
4254 return r;
4255 }
4256
4257 /* clear state buffer */
4258 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4259 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4260
4261 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4262 amdgpu_ring_write(ring, 0x80000000);
4263 amdgpu_ring_write(ring, 0x80000000);
4264
4265 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4266 for (ext = sect->section; ext->extent != NULL; ++ext) {
4267 if (sect->id == SECT_CONTEXT) {
4268 amdgpu_ring_write(ring,
4269 PACKET3(PACKET3_SET_CONTEXT_REG,
4270 ext->reg_count));
4271 amdgpu_ring_write(ring,
4272 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4273 for (i = 0; i < ext->reg_count; i++)
4274 amdgpu_ring_write(ring, ext->extent[i]);
4275 }
4276 }
4277 }
4278
4279 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4280 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4281 switch (adev->asic_type) {
4282 case CHIP_TONGA:
2cc0c0b5 4283 case CHIP_POLARIS10:
aaa36a97
AD		 4284 amdgpu_ring_write(ring, 0x16000012);
4285 amdgpu_ring_write(ring, 0x0000002A);
4286 break;
2cc0c0b5 4287 case CHIP_POLARIS11:
68182d90
FC		 4288 amdgpu_ring_write(ring, 0x16000012);
4289 amdgpu_ring_write(ring, 0x00000000);
4290 break;
fa676048
FC		 4291 case CHIP_FIJI:
4292 amdgpu_ring_write(ring, 0x3a00161a);
4293 amdgpu_ring_write(ring, 0x0000002e);
4294 break;
aaa36a97
AD		 4295 case CHIP_CARRIZO:
4296 amdgpu_ring_write(ring, 0x00000002);
4297 amdgpu_ring_write(ring, 0x00000000);
4298 break;
d1a7f7aa
KW		 4299 case CHIP_TOPAZ:
4300 amdgpu_ring_write(ring, adev->gfx.config.num_rbs == 1 ?
4301 0x00000000 : 0x00000002);
4302 amdgpu_ring_write(ring, 0x00000000);
4303 break;
e3c7656c
SL		 4304 case CHIP_STONEY:
4305 amdgpu_ring_write(ring, 0x00000000);
4306 amdgpu_ring_write(ring, 0x00000000);
4307 break;
aaa36a97
AD		 4308 default:
4309 BUG();
4310 }
4311
4312 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4313 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4314
4315 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4316 amdgpu_ring_write(ring, 0);
4317
4318 /* init the CE partitions */
4319 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4320 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4321 amdgpu_ring_write(ring, 0x8000);
4322 amdgpu_ring_write(ring, 0x8000);
4323
a27de35c 4324 amdgpu_ring_commit(ring);
aaa36a97
AD		 4325
4326 return 0;
4327}
4328
4329static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4330{
4331 struct amdgpu_ring *ring;
4332 u32 tmp;
4333 u32 rb_bufsz;
42e8cb50 4334 u64 rb_addr, rptr_addr, wptr_gpu_addr;
aaa36a97
AD		 4335 int r;
4336
4337 /* Set the write pointer delay */
4338 WREG32(mmCP_RB_WPTR_DELAY, 0);
4339
4340 /* set the RB to use vmid 0 */
4341 WREG32(mmCP_RB_VMID, 0);
4342
4343 /* Set ring buffer size */
4344 ring = &adev->gfx.gfx_ring[0];
4345 rb_bufsz = order_base_2(ring->ring_size / 8);
4346 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4347 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4348 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4349 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4350#ifdef __BIG_ENDIAN
4351 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4352#endif
4353 WREG32(mmCP_RB0_CNTL, tmp);
4354
4355 /* Initialize the ring buffer's read and write pointers */
4356 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4357 ring->wptr = 0;
4358 WREG32(mmCP_RB0_WPTR, ring->wptr);
4359
4360 /* set the wb address wether it's enabled or not */
4361 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4362 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4363 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4364
42e8cb50
FM		 4365 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4366 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
4367 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
aaa36a97
AD		 4368 mdelay(1);
4369 WREG32(mmCP_RB0_CNTL, tmp);
4370
4371 rb_addr = ring->gpu_addr >> 8;
4372 WREG32(mmCP_RB0_BASE, rb_addr);
4373 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4374
4375 /* no gfx doorbells on iceland */
4376 if (adev->asic_type != CHIP_TOPAZ) {
4377 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4378 if (ring->use_doorbell) {
4379 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4380 DOORBELL_OFFSET, ring->doorbell_index);
68182d90
FC		 4381 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4382 DOORBELL_HIT, 0);
aaa36a97
AD		 4383 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4384 DOORBELL_EN, 1);
4385 } else {
4386 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4387 DOORBELL_EN, 0);
4388 }
4389 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4390
4391 if (adev->asic_type == CHIP_TONGA) {
4392 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4393 DOORBELL_RANGE_LOWER,
4394 AMDGPU_DOORBELL_GFX_RING0);
4395 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4396
4397 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4398 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4399 }
4400
4401 }
4402
4403 /* start the ring */
4404 gfx_v8_0_cp_gfx_start(adev);
4405 ring->ready = true;
4406 r = amdgpu_ring_test_ring(ring);
5003f278 4407 if (r)
aaa36a97 4408 ring->ready = false;
aaa36a97 4409
5003f278 4410 return r;
aaa36a97
AD		 4411}
4412
4413static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4414{
4415 int i;
4416
4417 if (enable) {
4418 WREG32(mmCP_MEC_CNTL, 0);
4419 } else {
4420 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4421 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4422 adev->gfx.compute_ring[i].ready = false;
4423 }
4424 udelay(50);
4425}
4426
aaa36a97
AD		 4427static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
4428{
4429 const struct gfx_firmware_header_v1_0 *mec_hdr;
4430 const __le32 *fw_data;
4431 unsigned i, fw_size;
4432
4433 if (!adev->gfx.mec_fw)
4434 return -EINVAL;
4435
4436 gfx_v8_0_cp_compute_enable(adev, false);
4437
4438 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4439 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
aaa36a97
AD		 4440
4441 fw_data = (const __le32 *)
4442 (adev->gfx.mec_fw->data +
4443 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4444 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
4445
4446 /* MEC1 */
4447 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
4448 for (i = 0; i < fw_size; i++)
4449 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
4450 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
4451
4452 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
4453 if (adev->gfx.mec2_fw) {
4454 const struct gfx_firmware_header_v1_0 *mec2_hdr;
4455
4456 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4457 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
aaa36a97
AD		 4458
4459 fw_data = (const __le32 *)
4460 (adev->gfx.mec2_fw->data +
4461 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
4462 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
4463
4464 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
4465 for (i = 0; i < fw_size; i++)
4466 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
4467 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
4468 }
4469
4470 return 0;
4471}
4472
aaa36a97
AD		 4473static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
4474{
4475 int i, r;
4476
4477 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4478 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4479
4480 if (ring->mqd_obj) {
4481 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4482 if (unlikely(r != 0))
4483 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
4484
4485 amdgpu_bo_unpin(ring->mqd_obj);
4486 amdgpu_bo_unreserve(ring->mqd_obj);
4487
4488 amdgpu_bo_unref(&ring->mqd_obj);
4489 ring->mqd_obj = NULL;
4490 }
4491 }
4492}
4493
4494static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
4495{
4496 int r, i, j;
4497 u32 tmp;
4498 bool use_doorbell = true;
4499 u64 hqd_gpu_addr;
4500 u64 mqd_gpu_addr;
4501 u64 eop_gpu_addr;
4502 u64 wb_gpu_addr;
4503 u32 *buf;
4504 struct vi_mqd *mqd;
4505
ad3b9614 4506 /* init the queues. */
aaa36a97
AD		 4507 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4508 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4509
4510 if (ring->mqd_obj == NULL) {
4511 r = amdgpu_bo_create(adev,
4512 sizeof(struct vi_mqd),
4513 PAGE_SIZE, true,
4514 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
72d7668b 4515 NULL, &ring->mqd_obj);
aaa36a97
AD		 4516 if (r) {
4517 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
4518 return r;
4519 }
4520 }
4521
4522 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4523 if (unlikely(r != 0)) {
4524 gfx_v8_0_cp_compute_fini(adev);
4525 return r;
4526 }
4527 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
4528 &mqd_gpu_addr);
4529 if (r) {
4530 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
4531 gfx_v8_0_cp_compute_fini(adev);
4532 return r;
4533 }
4534 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
4535 if (r) {
4536 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
4537 gfx_v8_0_cp_compute_fini(adev);
4538 return r;
4539 }
4540
4541 /* init the mqd struct */
4542 memset(buf, 0, sizeof(struct vi_mqd));
4543
4544 mqd = (struct vi_mqd *)buf;
4545 mqd->header = 0xC0310800;
4546 mqd->compute_pipelinestat_enable = 0x00000001;
4547 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4548 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4549 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4550 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4551 mqd->compute_misc_reserved = 0x00000003;
4552
4553 mutex_lock(&adev->srbm_mutex);
4554 vi_srbm_select(adev, ring->me,
4555 ring->pipe,
4556 ring->queue, 0);
4557
ad3b9614
AD		 4558 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
4559 eop_gpu_addr >>= 8;
4560
4561 /* write the EOP addr */
4562 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
4563 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
4564
4565 /* set the VMID assigned */
4566 WREG32(mmCP_HQD_VMID, 0);
4567
4568 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4569 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4570 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4571 (order_base_2(MEC_HPD_SIZE / 4) - 1));
4572 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
4573
aaa36a97
AD		 4574 /* disable wptr polling */
4575 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
4576 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
4577 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
4578
4579 mqd->cp_hqd_eop_base_addr_lo =
4580 RREG32(mmCP_HQD_EOP_BASE_ADDR);
4581 mqd->cp_hqd_eop_base_addr_hi =
4582 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
4583
4584 /* enable doorbell? */
4585 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4586 if (use_doorbell) {
4587 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4588 } else {
4589 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
4590 }
4591 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
4592 mqd->cp_hqd_pq_doorbell_control = tmp;
4593
4594 /* disable the queue if it's active */
4595 mqd->cp_hqd_dequeue_request = 0;
4596 mqd->cp_hqd_pq_rptr = 0;
4597 mqd->cp_hqd_pq_wptr= 0;
4598 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
4599 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
4600 for (j = 0; j < adev->usec_timeout; j++) {
4601 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
4602 break;
4603 udelay(1);
4604 }
4605 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
4606 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
4607 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
4608 }
4609
4610 /* set the pointer to the MQD */
4611 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
4612 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
4613 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
4614 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
4615
4616 /* set MQD vmid to 0 */
4617 tmp = RREG32(mmCP_MQD_CONTROL);
4618 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4619 WREG32(mmCP_MQD_CONTROL, tmp);
4620 mqd->cp_mqd_control = tmp;
4621
4622 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4623 hqd_gpu_addr = ring->gpu_addr >> 8;
4624 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4625 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4626 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
4627 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
4628
4629 /* set up the HQD, this is similar to CP_RB0_CNTL */
4630 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4631 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4632 (order_base_2(ring->ring_size / 4) - 1));
4633 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4634 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4635#ifdef __BIG_ENDIAN
4636 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4637#endif
4638 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4639 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4640 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4641 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4642 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
4643 mqd->cp_hqd_pq_control = tmp;
4644
4645 /* set the wb address wether it's enabled or not */
4646 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4647 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4648 mqd->cp_hqd_pq_rptr_report_addr_hi =
4649 upper_32_bits(wb_gpu_addr) & 0xffff;
4650 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
4651 mqd->cp_hqd_pq_rptr_report_addr_lo);
4652 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
4653 mqd->cp_hqd_pq_rptr_report_addr_hi);
4654
4655 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4656 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
aeab2032 4657 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
aaa36a97 4658 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
aeab2032 4659 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo);
aaa36a97
AD		 4660 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
4661 mqd->cp_hqd_pq_wptr_poll_addr_hi);
4662
4663 /* enable the doorbell if requested */
4664 if (use_doorbell) {
bddf8026 4665 if ((adev->asic_type == CHIP_CARRIZO) ||
e3c7656c 4666 (adev->asic_type == CHIP_FIJI) ||
68182d90 4667 (adev->asic_type == CHIP_STONEY) ||
2cc0c0b5
FC		 4668 (adev->asic_type == CHIP_POLARIS11) ||
4669 (adev->asic_type == CHIP_POLARIS10)) {
aaa36a97
AD		 4670 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
4671 AMDGPU_DOORBELL_KIQ << 2);
4672 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
b8826b0c 4673 AMDGPU_DOORBELL_MEC_RING7 << 2);
aaa36a97
AD		 4674 }
4675 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4676 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4677 DOORBELL_OFFSET, ring->doorbell_index);
4678 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4679 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
4680 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
4681 mqd->cp_hqd_pq_doorbell_control = tmp;
4682
4683 } else {
4684 mqd->cp_hqd_pq_doorbell_control = 0;
4685 }
4686 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
4687 mqd->cp_hqd_pq_doorbell_control);
4688
845253e7
SJ		 4689 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4690 ring->wptr = 0;
4691 mqd->cp_hqd_pq_wptr = ring->wptr;
4692 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
4693 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4694
aaa36a97
AD		 4695 /* set the vmid for the queue */
4696 mqd->cp_hqd_vmid = 0;
4697 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
4698
4699 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4700 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4701 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
4702 mqd->cp_hqd_persistent_state = tmp;
68182d90 4703 if (adev->asic_type == CHIP_STONEY ||
2cc0c0b5
FC		 4704 adev->asic_type == CHIP_POLARIS11 ||
4705 adev->asic_type == CHIP_POLARIS10) {
3b55ddad
FC		 4706 tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
4707 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
4708 WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
4709 }
aaa36a97
AD		 4710
4711 /* activate the queue */
4712 mqd->cp_hqd_active = 1;
4713 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
4714
4715 vi_srbm_select(adev, 0, 0, 0, 0);
4716 mutex_unlock(&adev->srbm_mutex);
4717
4718 amdgpu_bo_kunmap(ring->mqd_obj);
4719 amdgpu_bo_unreserve(ring->mqd_obj);
4720 }
4721
4722 if (use_doorbell) {
4723 tmp = RREG32(mmCP_PQ_STATUS);
4724 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4725 WREG32(mmCP_PQ_STATUS, tmp);
4726 }
4727
6e9821b2 4728 gfx_v8_0_cp_compute_enable(adev, true);
aaa36a97
AD		 4729
4730 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4731 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4732
4733 ring->ready = true;
4734 r = amdgpu_ring_test_ring(ring);
4735 if (r)
4736 ring->ready = false;
4737 }
4738
4739 return 0;
4740}
4741
4742static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4743{
4744 int r;
4745
e3c7656c 4746 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 4747 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4748
e61710c5 4749 if (!adev->pp_enabled) {
ba5c2a87
RZ		 4750 if (!adev->firmware.smu_load) {
4751 /* legacy firmware loading */
4752 r = gfx_v8_0_cp_gfx_load_microcode(adev);
4753 if (r)
4754 return r;
aaa36a97 4755
ba5c2a87
RZ		 4756 r = gfx_v8_0_cp_compute_load_microcode(adev);
4757 if (r)
4758 return r;
4759 } else {
4760 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4761 AMDGPU_UCODE_ID_CP_CE);
4762 if (r)
4763 return -EINVAL;
4764
4765 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4766 AMDGPU_UCODE_ID_CP_PFP);
4767 if (r)
4768 return -EINVAL;
4769
4770 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4771 AMDGPU_UCODE_ID_CP_ME);
4772 if (r)
4773 return -EINVAL;
4774
951e0962
AD		 4775 if (adev->asic_type == CHIP_TOPAZ) {
4776 r = gfx_v8_0_cp_compute_load_microcode(adev);
4777 if (r)
4778 return r;
4779 } else {
4780 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4781 AMDGPU_UCODE_ID_CP_MEC1);
4782 if (r)
4783 return -EINVAL;
4784 }
ba5c2a87 4785 }
aaa36a97
AD		 4786 }
4787
4788 r = gfx_v8_0_cp_gfx_resume(adev);
4789 if (r)
4790 return r;
4791
4792 r = gfx_v8_0_cp_compute_resume(adev);
4793 if (r)
4794 return r;
4795
4796 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4797
4798 return 0;
4799}
4800
4801static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4802{
4803 gfx_v8_0_cp_gfx_enable(adev, enable);
4804 gfx_v8_0_cp_compute_enable(adev, enable);
4805}
4806
5fc3aeeb 4807static int gfx_v8_0_hw_init(void *handle)
aaa36a97
AD		 4808{
4809 int r;
5fc3aeeb 4810 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 4811
4812 gfx_v8_0_init_golden_registers(adev);
aaa36a97
AD		 4813 gfx_v8_0_gpu_init(adev);
4814
4815 r = gfx_v8_0_rlc_resume(adev);
4816 if (r)
4817 return r;
4818
4819 r = gfx_v8_0_cp_resume(adev);
aaa36a97
AD		 4820
4821 return r;
4822}
4823
5fc3aeeb 4824static int gfx_v8_0_hw_fini(void *handle)
aaa36a97 4825{
5fc3aeeb 4826 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4827
1d22a454
AD		 4828 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4829 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
aaa36a97
AD		 4830 gfx_v8_0_cp_enable(adev, false);
4831 gfx_v8_0_rlc_stop(adev);
4832 gfx_v8_0_cp_compute_fini(adev);
4833
62a86fc2
EH		 4834 amdgpu_set_powergating_state(adev,
4835 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE);
4836
aaa36a97
AD		 4837 return 0;
4838}
4839
5fc3aeeb 4840static int gfx_v8_0_suspend(void *handle)
aaa36a97 4841{
5fc3aeeb 4842 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4843
aaa36a97
AD		 4844 return gfx_v8_0_hw_fini(adev);
4845}
4846
5fc3aeeb 4847static int gfx_v8_0_resume(void *handle)
aaa36a97 4848{
5fc3aeeb 4849 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4850
aaa36a97
AD		 4851 return gfx_v8_0_hw_init(adev);
4852}
4853
5fc3aeeb 4854static bool gfx_v8_0_is_idle(void *handle)
aaa36a97 4855{
5fc3aeeb 4856 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4857
aaa36a97
AD		 4858 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
4859 return false;
4860 else
4861 return true;
4862}
4863
5fc3aeeb 4864static int gfx_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 4865{
4866 unsigned i;
5fc3aeeb 4867 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 4868
4869 for (i = 0; i < adev->usec_timeout; i++) {
5003f278 4870 if (gfx_v8_0_is_idle(handle))
aaa36a97 4871 return 0;
5003f278 4872
aaa36a97
AD		 4873 udelay(1);
4874 }
4875 return -ETIMEDOUT;
4876}
4877
da146d3b 4878static bool gfx_v8_0_check_soft_reset(void *handle)
aaa36a97 4879{
3d7c6384 4880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 4881 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4882 u32 tmp;
4883
4884 /* GRBM_STATUS */
4885 tmp = RREG32(mmGRBM_STATUS);
4886 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4887 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4888 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4889 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4890 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3d7c6384
CZ		 4891 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK |
4892 GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
aaa36a97
AD		 4893 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4894 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4895 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4896 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
aaa36a97
AD		 4897 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4898 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4899 }
4900
4901 /* GRBM_STATUS2 */
4902 tmp = RREG32(mmGRBM_STATUS2);
4903 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4904 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4905 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4906
3d7c6384
CZ		 4907 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
4908 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
4909 REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
4910 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4911 SOFT_RESET_CPF, 1);
4912 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4913 SOFT_RESET_CPC, 1);
4914 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4915 SOFT_RESET_CPG, 1);
4916 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
4917 SOFT_RESET_GRBM, 1);
4918 }
4919
aaa36a97
AD		 4920 /* SRBM_STATUS */
4921 tmp = RREG32(mmSRBM_STATUS);
4922 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4923 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4924 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3d7c6384
CZ		 4925 if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
4926 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4927 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
aaa36a97
AD		 4928
4929 if (grbm_soft_reset || srbm_soft_reset) {
3d7c6384
CZ		 4930 adev->gfx.grbm_soft_reset = grbm_soft_reset;
4931 adev->gfx.srbm_soft_reset = srbm_soft_reset;
da146d3b 4932 return true;
3d7c6384 4933 } else {
3d7c6384
CZ		 4934 adev->gfx.grbm_soft_reset = 0;
4935 adev->gfx.srbm_soft_reset = 0;
da146d3b 4936 return false;
3d7c6384 4937 }
3d7c6384 4938}
aaa36a97 4939
1057f20c
CZ		 4940static void gfx_v8_0_inactive_hqd(struct amdgpu_device *adev,
4941 struct amdgpu_ring *ring)
4942{
4943 int i;
4944
4945 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4946 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
4947 u32 tmp;
4948 tmp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
4949 tmp = REG_SET_FIELD(tmp, CP_HQD_DEQUEUE_REQUEST,
4950 DEQUEUE_REQ, 2);
4951 WREG32(mmCP_HQD_DEQUEUE_REQUEST, tmp);
4952 for (i = 0; i < adev->usec_timeout; i++) {
4953 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
4954 break;
4955 udelay(1);
4956 }
4957 }
4958}
4959
4960static int gfx_v8_0_pre_soft_reset(void *handle)
4961{
4962 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4963 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4964
da146d3b
AD		 4965 if ((!adev->gfx.grbm_soft_reset) &&
4966 (!adev->gfx.srbm_soft_reset))
1057f20c
CZ		 4967 return 0;
4968
4969 grbm_soft_reset = adev->gfx.grbm_soft_reset;
4970 srbm_soft_reset = adev->gfx.srbm_soft_reset;
4971
4972 /* stop the rlc */
4973 gfx_v8_0_rlc_stop(adev);
4974
4975 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
4976 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
aaa36a97
AD		 4977 /* Disable GFX parsing/prefetching */
4978 gfx_v8_0_cp_gfx_enable(adev, false);
4979
1057f20c
CZ		 4980 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
4981 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
4982 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
4983 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
4984 int i;
4985
4986 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4987 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4988
4989 gfx_v8_0_inactive_hqd(adev, ring);
4990 }
aaa36a97 4991 /* Disable MEC parsing/prefetching */
7776a693 4992 gfx_v8_0_cp_compute_enable(adev, false);
1057f20c 4993 }
7776a693 4994
1057f20c
CZ		 4995 return 0;
4996}
7776a693 4997
3d7c6384
CZ		 4998static int gfx_v8_0_soft_reset(void *handle)
4999{
5000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5001 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5002 u32 tmp;
aaa36a97 5003
da146d3b
AD		 5004 if ((!adev->gfx.grbm_soft_reset) &&
5005 (!adev->gfx.srbm_soft_reset))
3d7c6384 5006 return 0;
aaa36a97 5007
3d7c6384
CZ		 5008 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5009 srbm_soft_reset = adev->gfx.srbm_soft_reset;
aaa36a97 5010
3d7c6384
CZ		 5011 if (grbm_soft_reset || srbm_soft_reset) {
5012 tmp = RREG32(mmGMCON_DEBUG);
5013 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
5014 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
5015 WREG32(mmGMCON_DEBUG, tmp);
5016 udelay(50);
5017 }
aaa36a97 5018
3d7c6384
CZ		 5019 if (grbm_soft_reset) {
5020 tmp = RREG32(mmGRBM_SOFT_RESET);
5021 tmp |= grbm_soft_reset;
5022 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5023 WREG32(mmGRBM_SOFT_RESET, tmp);
5024 tmp = RREG32(mmGRBM_SOFT_RESET);
aaa36a97 5025
3d7c6384 5026 udelay(50);
aaa36a97 5027
3d7c6384
CZ		 5028 tmp &= ~grbm_soft_reset;
5029 WREG32(mmGRBM_SOFT_RESET, tmp);
5030 tmp = RREG32(mmGRBM_SOFT_RESET);
5031 }
7776a693 5032
3d7c6384
CZ		 5033 if (srbm_soft_reset) {
5034 tmp = RREG32(mmSRBM_SOFT_RESET);
5035 tmp |= srbm_soft_reset;
5036 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5037 WREG32(mmSRBM_SOFT_RESET, tmp);
5038 tmp = RREG32(mmSRBM_SOFT_RESET);
7776a693 5039
aaa36a97 5040 udelay(50);
7776a693 5041
3d7c6384
CZ		 5042 tmp &= ~srbm_soft_reset;
5043 WREG32(mmSRBM_SOFT_RESET, tmp);
5044 tmp = RREG32(mmSRBM_SOFT_RESET);
aaa36a97 5045 }
7776a693 5046
3d7c6384
CZ		 5047 if (grbm_soft_reset || srbm_soft_reset) {
5048 tmp = RREG32(mmGMCON_DEBUG);
5049 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
5050 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
5051 WREG32(mmGMCON_DEBUG, tmp);
aaa36a97 5052 }
3d7c6384
CZ		 5053
5054 /* Wait a little for things to settle down */
5055 udelay(50);
5056
aaa36a97
AD		 5057 return 0;
5058}
5059
e4ae0fc3
CZ		 5060static void gfx_v8_0_init_hqd(struct amdgpu_device *adev,
5061 struct amdgpu_ring *ring)
5062{
5063 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5064 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
5065 WREG32(mmCP_HQD_PQ_RPTR, 0);
5066 WREG32(mmCP_HQD_PQ_WPTR, 0);
5067 vi_srbm_select(adev, 0, 0, 0, 0);
5068}
5069
5070static int gfx_v8_0_post_soft_reset(void *handle)
5071{
5072 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5073 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5074
da146d3b
AD		 5075 if ((!adev->gfx.grbm_soft_reset) &&
5076 (!adev->gfx.srbm_soft_reset))
e4ae0fc3
CZ		 5077 return 0;
5078
5079 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5080 srbm_soft_reset = adev->gfx.srbm_soft_reset;
5081
5082 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5083 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5084 gfx_v8_0_cp_gfx_resume(adev);
5085
5086 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5087 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5088 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5089 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5090 int i;
5091
5092 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5093 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5094
5095 gfx_v8_0_init_hqd(adev, ring);
5096 }
5097 gfx_v8_0_cp_compute_resume(adev);
5098 }
5099 gfx_v8_0_rlc_start(adev);
5100
aaa36a97
AD		 5101 return 0;
5102}
5103
5104/**
5105 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5106 *
5107 * @adev: amdgpu_device pointer
5108 *
5109 * Fetches a GPU clock counter snapshot.
5110 * Returns the 64 bit clock counter snapshot.
5111 */
b95e31fd 5112static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
aaa36a97
AD		 5113{
5114 uint64_t clock;
5115
5116 mutex_lock(&adev->gfx.gpu_clock_mutex);
5117 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5118 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5119 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5120 mutex_unlock(&adev->gfx.gpu_clock_mutex);
5121 return clock;
5122}
5123
5124static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5125 uint32_t vmid,
5126 uint32_t gds_base, uint32_t gds_size,
5127 uint32_t gws_base, uint32_t gws_size,
5128 uint32_t oa_base, uint32_t oa_size)
5129{
5130 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
5131 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
5132
5133 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
5134 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
5135
5136 oa_base = oa_base >> AMDGPU_OA_SHIFT;
5137 oa_size = oa_size >> AMDGPU_OA_SHIFT;
5138
5139 /* GDS Base */
5140 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5141 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5142 WRITE_DATA_DST_SEL(0)));
5143 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5144 amdgpu_ring_write(ring, 0);
5145 amdgpu_ring_write(ring, gds_base);
5146
5147 /* GDS Size */
5148 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5149 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5150 WRITE_DATA_DST_SEL(0)));
5151 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5152 amdgpu_ring_write(ring, 0);
5153 amdgpu_ring_write(ring, gds_size);
5154
5155 /* GWS */
5156 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5157 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5158 WRITE_DATA_DST_SEL(0)));
5159 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5160 amdgpu_ring_write(ring, 0);
5161 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5162
5163 /* OA */
5164 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5165 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5166 WRITE_DATA_DST_SEL(0)));
5167 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5168 amdgpu_ring_write(ring, 0);
5169 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5170}
5171
472259f0
TSD		 5172static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5173{
bc24fbe9
TSD		 5174 WREG32(mmSQ_IND_INDEX,
5175 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5176 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5177 (address << SQ_IND_INDEX__INDEX__SHIFT) |
5178 (SQ_IND_INDEX__FORCE_READ_MASK));
472259f0
TSD		 5179 return RREG32(mmSQ_IND_DATA);
5180}
5181
5182static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5183{
5184 /* type 0 wave data */
5185 dst[(*no_fields)++] = 0;
5186 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
5187 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
5188 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
5189 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
5190 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
5191 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
5192 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
5193 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
5194 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
5195 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
5196 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
5197 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
74f3ce31
TSD		 5198 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
5199 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
5200 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
5201 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
5202 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
5203 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
472259f0
TSD		 5204}
5205
5206
b95e31fd
AD		 5207static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5208 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
05fb7291 5209 .select_se_sh = &gfx_v8_0_select_se_sh,
472259f0 5210 .read_wave_data = &gfx_v8_0_read_wave_data,
b95e31fd
AD		 5211};
5212
5fc3aeeb 5213static int gfx_v8_0_early_init(void *handle)
aaa36a97 5214{
5fc3aeeb 5215 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 5216
5217 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5218 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
b95e31fd 5219 adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
aaa36a97
AD		 5220 gfx_v8_0_set_ring_funcs(adev);
5221 gfx_v8_0_set_irq_funcs(adev);
5222 gfx_v8_0_set_gds_init(adev);
dbff57bc 5223 gfx_v8_0_set_rlc_funcs(adev);
aaa36a97
AD		 5224
5225 return 0;
5226}
5227
ccba7691
AD		 5228static int gfx_v8_0_late_init(void *handle)
5229{
5230 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5231 int r;
5232
1d22a454
AD		 5233 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5234 if (r)
5235 return r;
5236
5237 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5238 if (r)
5239 return r;
5240
ccba7691
AD		 5241 /* requires IBs so do in late init after IB pool is initialized */
5242 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5243 if (r)
5244 return r;
5245
62a86fc2
EH		 5246 amdgpu_set_powergating_state(adev,
5247 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE);
5248
ccba7691
AD		 5249 return 0;
5250}
5251
c2546f55
AD		 5252static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5253 bool enable)
62a86fc2 5254{
c2546f55
AD		 5255 if (adev->asic_type == CHIP_POLARIS11)
5256 /* Send msg to SMU via Powerplay */
5257 amdgpu_set_powergating_state(adev,
5258 AMD_IP_BLOCK_TYPE_SMC,
5259 enable ?
5260 AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
62a86fc2 5261
61cb8cef 5262 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
62a86fc2
EH		 5263}
5264
c2546f55
AD		 5265static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5266 bool enable)
62a86fc2 5267{
61cb8cef 5268 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
62a86fc2
EH		 5269}
5270
2cc0c0b5 5271static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
62a86fc2
EH		 5272 bool enable)
5273{
61cb8cef 5274 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
62a86fc2
EH		 5275}
5276
2c547165
AD		 5277static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
5278 bool enable)
5279{
61cb8cef 5280 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
2c547165
AD		 5281}
5282
5283static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
5284 bool enable)
5285{
61cb8cef 5286 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
2c547165
AD		 5287
5288 /* Read any GFX register to wake up GFX. */
5289 if (!enable)
61cb8cef 5290 RREG32(mmDB_RENDER_CONTROL);
2c547165
AD		 5291}
5292
5293static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
5294 bool enable)
5295{
5296 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
5297 cz_enable_gfx_cg_power_gating(adev, true);
5298 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
5299 cz_enable_gfx_pipeline_power_gating(adev, true);
5300 } else {
5301 cz_enable_gfx_cg_power_gating(adev, false);
5302 cz_enable_gfx_pipeline_power_gating(adev, false);
5303 }
5304}
5305
5fc3aeeb 5306static int gfx_v8_0_set_powergating_state(void *handle,
5307 enum amd_powergating_state state)
aaa36a97 5308{
62a86fc2 5309 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2c547165 5310 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
62a86fc2
EH		 5311
5312 if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5313 return 0;
5314
5315 switch (adev->asic_type) {
2c547165
AD		 5316 case CHIP_CARRIZO:
5317 case CHIP_STONEY:
5318 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
5319 cz_update_gfx_cg_power_gating(adev, enable);
5320
5321 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5322 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5323 else
5324 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5325
5326 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5327 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5328 else
5329 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5330 break;
2cc0c0b5 5331 case CHIP_POLARIS11:
7ba0eb6d
AD		 5332 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5333 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5334 else
5335 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5336
5337 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5338 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5339 else
5340 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5341
5342 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
5343 polaris11_enable_gfx_quick_mg_power_gating(adev, true);
62a86fc2 5344 else
7ba0eb6d 5345 polaris11_enable_gfx_quick_mg_power_gating(adev, false);
62a86fc2
EH		 5346 break;
5347 default:
5348 break;
5349 }
5350
aaa36a97
AD		 5351 return 0;
5352}
5353
79deaaf4 5354static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
14698b6c 5355 uint32_t reg_addr, uint32_t cmd)
6e378858
EH		 5356{
5357 uint32_t data;
5358
9559ef5b 5359 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6e378858
EH		 5360
5361 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5362 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5363
5364 data = RREG32(mmRLC_SERDES_WR_CTRL);
146f256f 5365 if (adev->asic_type == CHIP_STONEY)
62d2ce4b
TSD		 5366 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5367 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5368 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5369 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5370 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5371 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5372 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5373 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5374 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
146f256f
AD		 5375 else
5376 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5377 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5378 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5379 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5380 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5381 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5382 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5383 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5384 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5385 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5386 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
6e378858 5387 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
146f256f
AD		 5388 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5389 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5390 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
6e378858
EH		 5391
5392 WREG32(mmRLC_SERDES_WR_CTRL, data);
5393}
5394
dbff57bc
AD		 5395#define MSG_ENTER_RLC_SAFE_MODE 1
5396#define MSG_EXIT_RLC_SAFE_MODE 0
61cb8cef
TSD		 5397#define RLC_GPR_REG2__REQ_MASK 0x00000001
5398#define RLC_GPR_REG2__REQ__SHIFT 0
5399#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5400#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
dbff57bc
AD		 5401
5402static void cz_enter_rlc_safe_mode(struct amdgpu_device *adev)
5403{
5404 u32 data = 0;
5405 unsigned i;
5406
5407 data = RREG32(mmRLC_CNTL);
5408 if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
5409 return;
5410
5411 if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
5412 (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
5413 AMD_PG_SUPPORT_GFX_DMG))) {
5414 data |= RLC_GPR_REG2__REQ_MASK;
5415 data &= ~RLC_GPR_REG2__MESSAGE_MASK;
5416 data |= (MSG_ENTER_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
5417 WREG32(mmRLC_GPR_REG2, data);
5418
5419 for (i = 0; i < adev->usec_timeout; i++) {
5420 if ((RREG32(mmRLC_GPM_STAT) &
5421 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5422 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5423 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5424 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5425 break;
5426 udelay(1);
5427 }
5428
5429 for (i = 0; i < adev->usec_timeout; i++) {
61cb8cef 5430 if (!REG_GET_FIELD(RREG32(mmRLC_GPR_REG2), RLC_GPR_REG2, REQ))
dbff57bc
AD		 5431 break;
5432 udelay(1);
5433 }
5434 adev->gfx.rlc.in_safe_mode = true;
5435 }
5436}
5437
5438static void cz_exit_rlc_safe_mode(struct amdgpu_device *adev)
5439{
5440 u32 data;
5441 unsigned i;
5442
5443 data = RREG32(mmRLC_CNTL);
5444 if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
5445 return;
5446
5447 if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
5448 (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
5449 AMD_PG_SUPPORT_GFX_DMG))) {
5450 data |= RLC_GPR_REG2__REQ_MASK;
5451 data &= ~RLC_GPR_REG2__MESSAGE_MASK;
5452 data |= (MSG_EXIT_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
5453 WREG32(mmRLC_GPR_REG2, data);
5454 adev->gfx.rlc.in_safe_mode = false;
5455 }
5456
5457 for (i = 0; i < adev->usec_timeout; i++) {
61cb8cef 5458 if (!REG_GET_FIELD(RREG32(mmRLC_GPR_REG2), RLC_GPR_REG2, REQ))
dbff57bc
AD		 5459 break;
5460 udelay(1);
5461 }
5462}
5463
5464static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev)
5465{
5466 u32 data;
5467 unsigned i;
5468
5469 data = RREG32(mmRLC_CNTL);
5470 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
5471 return;
5472
5473 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
5474 data |= RLC_SAFE_MODE__CMD_MASK;
5475 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5476 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5477 WREG32(mmRLC_SAFE_MODE, data);
5478
5479 for (i = 0; i < adev->usec_timeout; i++) {
5480 if ((RREG32(mmRLC_GPM_STAT) &
5481 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5482 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5483 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5484 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5485 break;
5486 udelay(1);
5487 }
5488
5489 for (i = 0; i < adev->usec_timeout; i++) {
61cb8cef 5490 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
dbff57bc
AD		 5491 break;
5492 udelay(1);
5493 }
5494 adev->gfx.rlc.in_safe_mode = true;
5495 }
5496}
5497
5498static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev)
5499{
5500 u32 data = 0;
5501 unsigned i;
5502
5503 data = RREG32(mmRLC_CNTL);
5504 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
5505 return;
5506
5507 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
5508 if (adev->gfx.rlc.in_safe_mode) {
5509 data |= RLC_SAFE_MODE__CMD_MASK;
5510 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5511 WREG32(mmRLC_SAFE_MODE, data);
5512 adev->gfx.rlc.in_safe_mode = false;
5513 }
5514 }
5515
5516 for (i = 0; i < adev->usec_timeout; i++) {
61cb8cef 5517 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
dbff57bc
AD		 5518 break;
5519 udelay(1);
5520 }
5521}
5522
5523static void gfx_v8_0_nop_enter_rlc_safe_mode(struct amdgpu_device *adev)
5524{
5525 adev->gfx.rlc.in_safe_mode = true;
5526}
5527
5528static void gfx_v8_0_nop_exit_rlc_safe_mode(struct amdgpu_device *adev)
5529{
5530 adev->gfx.rlc.in_safe_mode = false;
5531}
5532
5533static const struct amdgpu_rlc_funcs cz_rlc_funcs = {
5534 .enter_safe_mode = cz_enter_rlc_safe_mode,
5535 .exit_safe_mode = cz_exit_rlc_safe_mode
5536};
5537
5538static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5539 .enter_safe_mode = iceland_enter_rlc_safe_mode,
5540 .exit_safe_mode = iceland_exit_rlc_safe_mode
5541};
5542
5543static const struct amdgpu_rlc_funcs gfx_v8_0_nop_rlc_funcs = {
5544 .enter_safe_mode = gfx_v8_0_nop_enter_rlc_safe_mode,
5545 .exit_safe_mode = gfx_v8_0_nop_exit_rlc_safe_mode
5546};
5547
5548static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5549 bool enable)
6e378858
EH		 5550{
5551 uint32_t temp, data;
5552
dbff57bc
AD		 5553 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5554
6e378858 5555 /* It is disabled by HW by default */
14698b6c
AD		 5556 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5557 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
61cb8cef 5558 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS)
14698b6c 5559 /* 1 - RLC memory Light sleep */
61cb8cef 5560 WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);
6e378858 5561
61cb8cef
TSD		 5562 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS)
5563 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);
14698b6c 5564 }
6e378858
EH		 5565
5566 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5567 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
dbff57bc
AD		 5568 if (adev->flags & AMD_IS_APU)
5569 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5570 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5571 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5572 else
5573 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5574 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5575 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5576 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
6e378858
EH		 5577
5578 if (temp != data)
5579 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5580
5581 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5582 gfx_v8_0_wait_for_rlc_serdes(adev);
5583
5584 /* 5 - clear mgcg override */
79deaaf4 5585 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
6e378858 5586
14698b6c
AD		 5587 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5588 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5589 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5590 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5591 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5592 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5593 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5594 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5595 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5596 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5597 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5598 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5599 if (temp != data)
5600 WREG32(mmCGTS_SM_CTRL_REG, data);
5601 }
6e378858
EH		 5602 udelay(50);
5603
5604 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5605 gfx_v8_0_wait_for_rlc_serdes(adev);
5606 } else {
5607 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5608 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5609 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5610 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5611 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5612 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5613 if (temp != data)
5614 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5615
5616 /* 2 - disable MGLS in RLC */
5617 data = RREG32(mmRLC_MEM_SLP_CNTL);
5618 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5619 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5620 WREG32(mmRLC_MEM_SLP_CNTL, data);
5621 }
5622
5623 /* 3 - disable MGLS in CP */
5624 data = RREG32(mmCP_MEM_SLP_CNTL);
5625 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5626 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5627 WREG32(mmCP_MEM_SLP_CNTL, data);
5628 }
5629
5630 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5631 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5632 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5633 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5634 if (temp != data)
5635 WREG32(mmCGTS_SM_CTRL_REG, data);
5636
5637 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5638 gfx_v8_0_wait_for_rlc_serdes(adev);
5639
5640 /* 6 - set mgcg override */
79deaaf4 5641 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
6e378858
EH		 5642
5643 udelay(50);
5644
5645 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5646 gfx_v8_0_wait_for_rlc_serdes(adev);
5647 }
dbff57bc
AD		 5648
5649 adev->gfx.rlc.funcs->exit_safe_mode(adev);
6e378858
EH		 5650}
5651
dbff57bc
AD		 5652static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5653 bool enable)
6e378858
EH		 5654{
5655 uint32_t temp, temp1, data, data1;
5656
5657 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5658
dbff57bc
AD		 5659 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5660
14698b6c 5661 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
6e378858
EH		 5662 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5663 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5664 if (temp1 != data1)
5665 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5666
dd31ae9a 5667 /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
6e378858
EH		 5668 gfx_v8_0_wait_for_rlc_serdes(adev);
5669
dd31ae9a 5670 /* 2 - clear cgcg override */
79deaaf4 5671 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
6e378858
EH		 5672
5673 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5674 gfx_v8_0_wait_for_rlc_serdes(adev);
5675
dd31ae9a 5676 /* 3 - write cmd to set CGLS */
79deaaf4 5677 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
6e378858 5678
dd31ae9a 5679 /* 4 - enable cgcg */
6e378858
EH		 5680 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5681
14698b6c
AD		 5682 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5683 /* enable cgls*/
5684 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
6e378858 5685
14698b6c
AD		 5686 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5687 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
6e378858 5688
14698b6c
AD		 5689 if (temp1 != data1)
5690 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5691 } else {
5692 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5693 }
6e378858
EH		 5694
5695 if (temp != data)
5696 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
dd31ae9a
AN		 5697
5698 /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
5699 * Cmp_busy/GFX_Idle interrupts
5700 */
5701 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
6e378858
EH		 5702 } else {
5703 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5704 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5705
5706 /* TEST CGCG */
5707 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5708 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5709 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5710 if (temp1 != data1)
5711 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5712
5713 /* read gfx register to wake up cgcg */
5714 RREG32(mmCB_CGTT_SCLK_CTRL);
5715 RREG32(mmCB_CGTT_SCLK_CTRL);
5716 RREG32(mmCB_CGTT_SCLK_CTRL);
5717 RREG32(mmCB_CGTT_SCLK_CTRL);
5718
5719 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5720 gfx_v8_0_wait_for_rlc_serdes(adev);
5721
5722 /* write cmd to Set CGCG Overrride */
79deaaf4 5723 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
6e378858
EH		 5724
5725 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5726 gfx_v8_0_wait_for_rlc_serdes(adev);
5727
5728 /* write cmd to Clear CGLS */
79deaaf4 5729 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
6e378858
EH		 5730
5731 /* disable cgcg, cgls should be disabled too. */
5732 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
14698b6c 5733 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
6e378858
EH		 5734 if (temp != data)
5735 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5736 }
dbff57bc 5737
7894745a
TSD		 5738 gfx_v8_0_wait_for_rlc_serdes(adev);
5739
dbff57bc 5740 adev->gfx.rlc.funcs->exit_safe_mode(adev);
6e378858 5741}
dbff57bc
AD		 5742static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5743 bool enable)
6e378858
EH		 5744{
5745 if (enable) {
5746 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5747 * === MGCG + MGLS + TS(CG/LS) ===
5748 */
dbff57bc
AD		 5749 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5750 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
6e378858
EH		 5751 } else {
5752 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5753 * === CGCG + CGLS ===
5754 */
dbff57bc
AD		 5755 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5756 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
6e378858
EH		 5757 }
5758 return 0;
5759}
5760
a8ca3413
RZ		 5761static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5762 enum amd_clockgating_state state)
5763{
5764 uint32_t msg_id, pp_state;
5765 void *pp_handle = adev->powerplay.pp_handle;
5766
5767 if (state == AMD_CG_STATE_UNGATE)
5768 pp_state = 0;
5769 else
5770 pp_state = PP_STATE_CG | PP_STATE_LS;
5771
5772 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5773 PP_BLOCK_GFX_CG,
5774 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5775 pp_state);
5776 amd_set_clockgating_by_smu(pp_handle, msg_id);
5777
5778 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5779 PP_BLOCK_GFX_MG,
5780 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5781 pp_state);
5782 amd_set_clockgating_by_smu(pp_handle, msg_id);
5783
5784 return 0;
5785}
5786
5787static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
5788 enum amd_clockgating_state state)
5789{
5790 uint32_t msg_id, pp_state;
5791 void *pp_handle = adev->powerplay.pp_handle;
5792
5793 if (state == AMD_CG_STATE_UNGATE)
5794 pp_state = 0;
5795 else
5796 pp_state = PP_STATE_CG | PP_STATE_LS;
5797
5798 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5799 PP_BLOCK_GFX_CG,
5800 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5801 pp_state);
5802 amd_set_clockgating_by_smu(pp_handle, msg_id);
5803
5804 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5805 PP_BLOCK_GFX_3D,
5806 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5807 pp_state);
5808 amd_set_clockgating_by_smu(pp_handle, msg_id);
5809
5810 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5811 PP_BLOCK_GFX_MG,
5812 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5813 pp_state);
5814 amd_set_clockgating_by_smu(pp_handle, msg_id);
5815
5816 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5817 PP_BLOCK_GFX_RLC,
5818 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5819 pp_state);
5820 amd_set_clockgating_by_smu(pp_handle, msg_id);
5821
5822 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5823 PP_BLOCK_GFX_CP,
5824 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
5825 pp_state);
5826 amd_set_clockgating_by_smu(pp_handle, msg_id);
5827
5828 return 0;
5829}
5830
5fc3aeeb 5831static int gfx_v8_0_set_clockgating_state(void *handle,
5832 enum amd_clockgating_state state)
aaa36a97 5833{
6e378858
EH		 5834 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5835
5836 switch (adev->asic_type) {
5837 case CHIP_FIJI:
dbff57bc
AD		 5838 case CHIP_CARRIZO:
5839 case CHIP_STONEY:
5840 gfx_v8_0_update_gfx_clock_gating(adev,
5841 state == AMD_CG_STATE_GATE ? true : false);
6e378858 5842 break;
a8ca3413
RZ		 5843 case CHIP_TONGA:
5844 gfx_v8_0_tonga_update_gfx_clock_gating(adev, state);
5845 break;
5846 case CHIP_POLARIS10:
5847 case CHIP_POLARIS11:
5848 gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
5849 break;
6e378858
EH		 5850 default:
5851 break;
5852 }
aaa36a97
AD		 5853 return 0;
5854}
5855
e7706b42 5856static u32 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
aaa36a97 5857{
5003f278 5858 return ring->adev->wb.wb[ring->rptr_offs];
aaa36a97
AD		 5859}
5860
5861static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5862{
5863 struct amdgpu_device *adev = ring->adev;
aaa36a97
AD		 5864
5865 if (ring->use_doorbell)
5866 /* XXX check if swapping is necessary on BE */
5003f278 5867 return ring->adev->wb.wb[ring->wptr_offs];
aaa36a97 5868 else
5003f278 5869 return RREG32(mmCP_RB0_WPTR);
aaa36a97
AD		 5870}
5871
5872static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5873{
5874 struct amdgpu_device *adev = ring->adev;
5875
5876 if (ring->use_doorbell) {
5877 /* XXX check if swapping is necessary on BE */
5878 adev->wb.wb[ring->wptr_offs] = ring->wptr;
5879 WDOORBELL32(ring->doorbell_index, ring->wptr);
5880 } else {
5881 WREG32(mmCP_RB0_WPTR, ring->wptr);
5882 (void)RREG32(mmCP_RB0_WPTR);
5883 }
5884}
5885
d2edb07b 5886static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD		 5887{
5888 u32 ref_and_mask, reg_mem_engine;
5889
21cd942e 5890 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
aaa36a97
AD		 5891 switch (ring->me) {
5892 case 1:
5893 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
5894 break;
5895 case 2:
5896 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
5897 break;
5898 default:
5899 return;
5900 }
5901 reg_mem_engine = 0;
5902 } else {
5903 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
5904 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
5905 }
5906
5907 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5908 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
5909 WAIT_REG_MEM_FUNCTION(3) | /* == */
5910 reg_mem_engine));
5911 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
5912 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
5913 amdgpu_ring_write(ring, ref_and_mask);
5914 amdgpu_ring_write(ring, ref_and_mask);
5915 amdgpu_ring_write(ring, 0x20); /* poll interval */
5916}
5917
45682886
ML		 5918static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
5919{
5920 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
5921 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
5922 EVENT_INDEX(4));
5923
5924 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
5925 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
5926 EVENT_INDEX(0));
5927}
5928
5929
d35db561
CZ		 5930static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
5931{
5932 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5933 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5934 WRITE_DATA_DST_SEL(0) |
5935 WR_CONFIRM));
5936 amdgpu_ring_write(ring, mmHDP_DEBUG0);
5937 amdgpu_ring_write(ring, 0);
5938 amdgpu_ring_write(ring, 1);
5939
5940}
5941
93323131 5942static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
d88bf583
CK		 5943 struct amdgpu_ib *ib,
5944 unsigned vm_id, bool ctx_switch)
aaa36a97
AD		 5945{
5946 u32 header, control = 0;
aaa36a97 5947
de807f81 5948 if (ib->flags & AMDGPU_IB_FLAG_CE)
aaa36a97
AD		 5949 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
5950 else
5951 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5952
d88bf583 5953 control |= ib->length_dw | (vm_id << 24);
aaa36a97
AD		 5954
5955 amdgpu_ring_write(ring, header);
5956 amdgpu_ring_write(ring,
5957#ifdef __BIG_ENDIAN
5958 (2 << 0) |
5959#endif
5960 (ib->gpu_addr & 0xFFFFFFFC));
5961 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
5962 amdgpu_ring_write(ring, control);
5963}
5964
93323131 5965static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
d88bf583
CK		 5966 struct amdgpu_ib *ib,
5967 unsigned vm_id, bool ctx_switch)
93323131 5968{
33b7ed01 5969 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
93323131 5970
33b7ed01 5971 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
93323131 5972 amdgpu_ring_write(ring,
5973#ifdef __BIG_ENDIAN
62d2ce4b 5974 (2 << 0) |
93323131 5975#endif
62d2ce4b 5976 (ib->gpu_addr & 0xFFFFFFFC));
93323131 5977 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
5978 amdgpu_ring_write(ring, control);
5979}
5980
aaa36a97 5981static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 5982 u64 seq, unsigned flags)
aaa36a97 5983{
890ee23f
CZ		 5984 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5985 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5986
aaa36a97
AD		 5987 /* EVENT_WRITE_EOP - flush caches, send int */
5988 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
5989 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
5990 EOP_TC_ACTION_EN |
f84e63f2 5991 EOP_TC_WB_ACTION_EN |
aaa36a97
AD		 5992 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5993 EVENT_INDEX(5)));
5994 amdgpu_ring_write(ring, addr & 0xfffffffc);
90bea0ab 5995 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 5996 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 5997 amdgpu_ring_write(ring, lower_32_bits(seq));
5998 amdgpu_ring_write(ring, upper_32_bits(seq));
22c01cc4 5999
aaa36a97
AD		 6000}
6001
b8c7b39e 6002static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
aaa36a97 6003{
21cd942e 6004 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5907a0d8 6005 uint32_t seq = ring->fence_drv.sync_seq;
22c01cc4
AA		 6006 uint64_t addr = ring->fence_drv.gpu_addr;
6007
6008 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6009 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
9cac5373
CZ		 6010 WAIT_REG_MEM_FUNCTION(3) | /* equal */
6011 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
22c01cc4
AA		 6012 amdgpu_ring_write(ring, addr & 0xfffffffc);
6013 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
6014 amdgpu_ring_write(ring, seq);
6015 amdgpu_ring_write(ring, 0xffffffff);
6016 amdgpu_ring_write(ring, 4); /* poll interval */
b8c7b39e
CK		 6017}
6018
6019static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6020 unsigned vm_id, uint64_t pd_addr)
6021{
21cd942e 6022 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5c3422b0 6023
aaa36a97
AD		 6024 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6025 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
20a85ff8
CK		 6026 WRITE_DATA_DST_SEL(0)) |
6027 WR_CONFIRM);
aaa36a97
AD		 6028 if (vm_id < 8) {
6029 amdgpu_ring_write(ring,
6030 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
6031 } else {
6032 amdgpu_ring_write(ring,
6033 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
6034 }
6035 amdgpu_ring_write(ring, 0);
6036 amdgpu_ring_write(ring, pd_addr >> 12);
6037
aaa36a97
AD		 6038 /* bits 0-15 are the VM contexts0-15 */
6039 /* invalidate the cache */
6040 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6041 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6042 WRITE_DATA_DST_SEL(0)));
6043 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6044 amdgpu_ring_write(ring, 0);
6045 amdgpu_ring_write(ring, 1 << vm_id);
6046
6047 /* wait for the invalidate to complete */
6048 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6049 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6050 WAIT_REG_MEM_FUNCTION(0) | /* always */
6051 WAIT_REG_MEM_ENGINE(0))); /* me */
6052 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6053 amdgpu_ring_write(ring, 0);
6054 amdgpu_ring_write(ring, 0); /* ref */
6055 amdgpu_ring_write(ring, 0); /* mask */
6056 amdgpu_ring_write(ring, 0x20); /* poll interval */
6057
6058 /* compute doesn't have PFP */
6059 if (usepfp) {
6060 /* sync PFP to ME, otherwise we might get invalid PFP reads */
6061 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6062 amdgpu_ring_write(ring, 0x0);
d4946ccf
ML		 6063 /* GFX8 emits 128 dw nop to prevent CE access VM before vm_flush finish */
6064 amdgpu_ring_insert_nop(ring, 128);
aaa36a97
AD		 6065 }
6066}
6067
aaa36a97
AD		 6068static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6069{
6070 return ring->adev->wb.wb[ring->wptr_offs];
6071}
6072
6073static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6074{
6075 struct amdgpu_device *adev = ring->adev;
6076
6077 /* XXX check if swapping is necessary on BE */
6078 adev->wb.wb[ring->wptr_offs] = ring->wptr;
6079 WDOORBELL32(ring->doorbell_index, ring->wptr);
6080}
6081
6082static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6083 u64 addr, u64 seq,
890ee23f 6084 unsigned flags)
aaa36a97 6085{
890ee23f
CZ		 6086 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6087 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6088
aaa36a97
AD		 6089 /* RELEASE_MEM - flush caches, send int */
6090 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6091 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6092 EOP_TC_ACTION_EN |
a3d5aaa8 6093 EOP_TC_WB_ACTION_EN |
aaa36a97
AD		 6094 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6095 EVENT_INDEX(5)));
890ee23f 6096 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 6097 amdgpu_ring_write(ring, addr & 0xfffffffc);
6098 amdgpu_ring_write(ring, upper_32_bits(addr));
6099 amdgpu_ring_write(ring, lower_32_bits(seq));
6100 amdgpu_ring_write(ring, upper_32_bits(seq));
6101}
6102
c2167a65
ML		 6103static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
6104{
6105 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6106 amdgpu_ring_write(ring, 0);
6107}
6108
753ad49c
ML		 6109static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6110{
6111 uint32_t dw2 = 0;
6112
6113 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6114 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
45682886 6115 gfx_v8_0_ring_emit_vgt_flush(ring);
753ad49c
ML		 6116 /* set load_global_config & load_global_uconfig */
6117 dw2 |= 0x8001;
6118 /* set load_cs_sh_regs */
6119 dw2 |= 0x01000000;
6120 /* set load_per_context_state & load_gfx_sh_regs for GFX */
6121 dw2 |= 0x10002;
6122
6123 /* set load_ce_ram if preamble presented */
6124 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
6125 dw2 |= 0x10000000;
6126 } else {
6127 /* still load_ce_ram if this is the first time preamble presented
6128 * although there is no context switch happens.
6129 */
6130 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
6131 dw2 |= 0x10000000;
6132 }
6133
6134 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6135 amdgpu_ring_write(ring, dw2);
6136 amdgpu_ring_write(ring, 0);
6137}
6138
aaa36a97
AD		 6139static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6140 enum amdgpu_interrupt_state state)
6141{
61cb8cef
TSD		 6142 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
6143 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
aaa36a97
AD		 6144}
6145
6146static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6147 int me, int pipe,
6148 enum amdgpu_interrupt_state state)
6149{
aaa36a97
AD		 6150 /*
6151 * amdgpu controls only pipe 0 of MEC1. That's why this function only
6152 * handles the setting of interrupts for this specific pipe. All other
6153 * pipes' interrupts are set by amdkfd.
6154 */
6155
6156 if (me == 1) {
6157 switch (pipe) {
6158 case 0:
aaa36a97
AD		 6159 break;
6160 default:
6161 DRM_DEBUG("invalid pipe %d\n", pipe);
6162 return;
6163 }
6164 } else {
6165 DRM_DEBUG("invalid me %d\n", me);
6166 return;
6167 }
6168
61cb8cef
TSD		 6169 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, TIME_STAMP_INT_ENABLE,
6170 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
aaa36a97
AD		 6171}
6172
6173static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6174 struct amdgpu_irq_src *source,
6175 unsigned type,
6176 enum amdgpu_interrupt_state state)
6177{
61cb8cef
TSD		 6178 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
6179 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
aaa36a97
AD		 6180
6181 return 0;
6182}
6183
6184static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6185 struct amdgpu_irq_src *source,
6186 unsigned type,
6187 enum amdgpu_interrupt_state state)
6188{
61cb8cef
TSD		 6189 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
6190 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
aaa36a97
AD		 6191
6192 return 0;
6193}
6194
6195static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6196 struct amdgpu_irq_src *src,
6197 unsigned type,
6198 enum amdgpu_interrupt_state state)
6199{
6200 switch (type) {
6201 case AMDGPU_CP_IRQ_GFX_EOP:
6202 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6203 break;
6204 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6205 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6206 break;
6207 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6208 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6209 break;
6210 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6211 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6212 break;
6213 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6214 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6215 break;
6216 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6217 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6218 break;
6219 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6220 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6221 break;
6222 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6223 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6224 break;
6225 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6226 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6227 break;
6228 default:
6229 break;
6230 }
6231 return 0;
6232}
6233
6234static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6235 struct amdgpu_irq_src *source,
6236 struct amdgpu_iv_entry *entry)
6237{
6238 int i;
6239 u8 me_id, pipe_id, queue_id;
6240 struct amdgpu_ring *ring;
6241
6242 DRM_DEBUG("IH: CP EOP\n");
6243 me_id = (entry->ring_id & 0x0c) >> 2;
6244 pipe_id = (entry->ring_id & 0x03) >> 0;
6245 queue_id = (entry->ring_id & 0x70) >> 4;
6246
6247 switch (me_id) {
6248 case 0:
6249 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6250 break;
6251 case 1:
6252 case 2:
6253 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6254 ring = &adev->gfx.compute_ring[i];
6255 /* Per-queue interrupt is supported for MEC starting from VI.
6256 * The interrupt can only be enabled/disabled per pipe instead of per queue.
6257 */
6258 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6259 amdgpu_fence_process(ring);
6260 }
6261 break;
6262 }
6263 return 0;
6264}
6265
6266static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6267 struct amdgpu_irq_src *source,
6268 struct amdgpu_iv_entry *entry)
6269{
6270 DRM_ERROR("Illegal register access in command stream\n");
6271 schedule_work(&adev->reset_work);
6272 return 0;
6273}
6274
6275static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6276 struct amdgpu_irq_src *source,
6277 struct amdgpu_iv_entry *entry)
6278{
6279 DRM_ERROR("Illegal instruction in command stream\n");
6280 schedule_work(&adev->reset_work);
6281 return 0;
6282}
6283
a1255107 6284static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
88a907d6 6285 .name = "gfx_v8_0",
aaa36a97 6286 .early_init = gfx_v8_0_early_init,
ccba7691 6287 .late_init = gfx_v8_0_late_init,
aaa36a97
AD		 6288 .sw_init = gfx_v8_0_sw_init,
6289 .sw_fini = gfx_v8_0_sw_fini,
6290 .hw_init = gfx_v8_0_hw_init,
6291 .hw_fini = gfx_v8_0_hw_fini,
6292 .suspend = gfx_v8_0_suspend,
6293 .resume = gfx_v8_0_resume,
6294 .is_idle = gfx_v8_0_is_idle,
6295 .wait_for_idle = gfx_v8_0_wait_for_idle,
3d7c6384 6296 .check_soft_reset = gfx_v8_0_check_soft_reset,
1057f20c 6297 .pre_soft_reset = gfx_v8_0_pre_soft_reset,
aaa36a97 6298 .soft_reset = gfx_v8_0_soft_reset,
e4ae0fc3 6299 .post_soft_reset = gfx_v8_0_post_soft_reset,
aaa36a97
AD		 6300 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6301 .set_powergating_state = gfx_v8_0_set_powergating_state,
6302};
6303
6304static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
21cd942e 6305 .type = AMDGPU_RING_TYPE_GFX,
79887142
CK		 6306 .align_mask = 0xff,
6307 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
e7706b42 6308 .get_rptr = gfx_v8_0_ring_get_rptr,
aaa36a97
AD		 6309 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6310 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
e12f3d7a
CK		 6311 .emit_frame_size =
6312 20 + /* gfx_v8_0_ring_emit_gds_switch */
6313 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6314 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
6315 6 + 6 + 6 +/* gfx_v8_0_ring_emit_fence_gfx x3 for user fence, vm fence */
6316 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6317 128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */
6318 2 + /* gfx_v8_ring_emit_sb */
45682886 6319 3 + 4, /* gfx_v8_ring_emit_cntxcntl including vgt flush */
e12f3d7a 6320 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
93323131 6321 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
aaa36a97 6322 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
b8c7b39e 6323 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
aaa36a97
AD		 6324 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6325 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
d2edb07b 6326 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
d35db561 6327 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
aaa36a97
AD		 6328 .test_ring = gfx_v8_0_ring_test_ring,
6329 .test_ib = gfx_v8_0_ring_test_ib,
edff0e28 6330 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 6331 .pad_ib = amdgpu_ring_generic_pad_ib,
c2167a65 6332 .emit_switch_buffer = gfx_v8_ring_emit_sb,
753ad49c 6333 .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
aaa36a97
AD		 6334};
6335
6336static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
21cd942e 6337 .type = AMDGPU_RING_TYPE_COMPUTE,
79887142
CK		 6338 .align_mask = 0xff,
6339 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
e7706b42 6340 .get_rptr = gfx_v8_0_ring_get_rptr,
aaa36a97
AD		 6341 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6342 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
e12f3d7a
CK		 6343 .emit_frame_size =
6344 20 + /* gfx_v8_0_ring_emit_gds_switch */
6345 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6346 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
6347 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6348 17 + /* gfx_v8_0_ring_emit_vm_flush */
6349 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6350 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */
93323131 6351 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
aaa36a97 6352 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
b8c7b39e 6353 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
aaa36a97
AD		 6354 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6355 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
35074d2d 6356 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
d35db561 6357 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
aaa36a97
AD		 6358 .test_ring = gfx_v8_0_ring_test_ring,
6359 .test_ib = gfx_v8_0_ring_test_ib,
edff0e28 6360 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 6361 .pad_ib = amdgpu_ring_generic_pad_ib,
aaa36a97
AD		 6362};
6363
6364static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
6365{
6366 int i;
6367
6368 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6369 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
6370
6371 for (i = 0; i < adev->gfx.num_compute_rings; i++)
6372 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
6373}
6374
6375static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
6376 .set = gfx_v8_0_set_eop_interrupt_state,
6377 .process = gfx_v8_0_eop_irq,
6378};
6379
6380static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
6381 .set = gfx_v8_0_set_priv_reg_fault_state,
6382 .process = gfx_v8_0_priv_reg_irq,
6383};
6384
6385static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
6386 .set = gfx_v8_0_set_priv_inst_fault_state,
6387 .process = gfx_v8_0_priv_inst_irq,
6388};
6389
6390static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
6391{
6392 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6393 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
6394
6395 adev->gfx.priv_reg_irq.num_types = 1;
6396 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
6397
6398 adev->gfx.priv_inst_irq.num_types = 1;
6399 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
6400}
6401
dbff57bc
AD		 6402static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
6403{
6404 switch (adev->asic_type) {
6405 case CHIP_TOPAZ:
dbff57bc
AD		 6406 adev->gfx.rlc.funcs = &iceland_rlc_funcs;
6407 break;
6ab3886c 6408 case CHIP_STONEY:
dbff57bc
AD		 6409 case CHIP_CARRIZO:
6410 adev->gfx.rlc.funcs = &cz_rlc_funcs;
6411 break;
6412 default:
6413 adev->gfx.rlc.funcs = &gfx_v8_0_nop_rlc_funcs;
6414 break;
6415 }
6416}
6417
aaa36a97
AD		 6418static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
6419{
6420 /* init asci gds info */
6421 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
6422 adev->gds.gws.total_size = 64;
6423 adev->gds.oa.total_size = 16;
6424
6425 if (adev->gds.mem.total_size == 64 * 1024) {
6426 adev->gds.mem.gfx_partition_size = 4096;
6427 adev->gds.mem.cs_partition_size = 4096;
6428
6429 adev->gds.gws.gfx_partition_size = 4;
6430 adev->gds.gws.cs_partition_size = 4;
6431
6432 adev->gds.oa.gfx_partition_size = 4;
6433 adev->gds.oa.cs_partition_size = 1;
6434 } else {
6435 adev->gds.mem.gfx_partition_size = 1024;
6436 adev->gds.mem.cs_partition_size = 1024;
6437
6438 adev->gds.gws.gfx_partition_size = 16;
6439 adev->gds.gws.cs_partition_size = 16;
6440
6441 adev->gds.oa.gfx_partition_size = 4;
6442 adev->gds.oa.cs_partition_size = 4;
6443 }
6444}
6445
9de06de8
NH		 6446static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
6447 u32 bitmap)
6448{
6449 u32 data;
6450
6451 if (!bitmap)
6452 return;
6453
6454 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
6455 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
6456
6457 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
6458}
6459
8f8e00c1 6460static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
aaa36a97 6461{
8f8e00c1 6462 u32 data, mask;
aaa36a97 6463
5003f278
TSD		 6464 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
6465 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
aaa36a97 6466
6157bd7a 6467 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
aaa36a97 6468
5003f278 6469 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
aaa36a97
AD		 6470}
6471
7dae69a2 6472static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
aaa36a97
AD		 6473{
6474 int i, j, k, counter, active_cu_number = 0;
6475 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7dae69a2 6476 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
9de06de8 6477 unsigned disable_masks[4 * 2];
aaa36a97 6478
6157bd7a
FC		 6479 memset(cu_info, 0, sizeof(*cu_info));
6480
9de06de8
NH		 6481 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
6482
aaa36a97
AD		 6483 mutex_lock(&adev->grbm_idx_mutex);
6484 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6485 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6486 mask = 1;
6487 ao_bitmap = 0;
6488 counter = 0;
9559ef5b 6489 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
9de06de8
NH		 6490 if (i < 4 && j < 2)
6491 gfx_v8_0_set_user_cu_inactive_bitmap(
6492 adev, disable_masks[i * 2 + j]);
8f8e00c1 6493 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
aaa36a97
AD		 6494 cu_info->bitmap[i][j] = bitmap;
6495
8f8e00c1 6496 for (k = 0; k < 16; k ++) {
aaa36a97
AD		 6497 if (bitmap & mask) {
6498 if (counter < 2)
6499 ao_bitmap |= mask;
6500 counter ++;
6501 }
6502 mask <<= 1;
6503 }
6504 active_cu_number += counter;
6505 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
6506 }
6507 }
9559ef5b 6508 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8f8e00c1 6509 mutex_unlock(&adev->grbm_idx_mutex);
aaa36a97
AD		 6510
6511 cu_info->number = active_cu_number;
6512 cu_info->ao_cu_mask = ao_cu_mask;
aaa36a97 6513}
a1255107
AD		 6514
6515const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
6516{
6517 .type = AMD_IP_BLOCK_TYPE_GFX,
6518 .major = 8,
6519 .minor = 0,
6520 .rev = 0,
6521 .funcs = &gfx_v8_0_ip_funcs,
6522};
6523
6524const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
6525{
6526 .type = AMD_IP_BLOCK_TYPE_GFX,
6527 .major = 8,
6528 .minor = 1,
6529 .rev = 0,
6530 .funcs = &gfx_v8_0_ip_funcs,
6531};
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