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drm/amdgpu/gfx9: fix typo in mpd init
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
41#define GFX9_NUM_COMPUTE_RINGS 8
b1023571
KW		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000
43
44MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
45MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
46MODULE_FIRMWARE("amdgpu/vega10_me.bin");
47MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
48MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
49MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
50
51static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
52{
53 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
54 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
55 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
56 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
57 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
58 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
59 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
60 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
61 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
62 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
63 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
64 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
65 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
66 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
67 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
68 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
69 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
71 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
73 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
75 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
77 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
79 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
81 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
83 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
85};
86
87static const u32 golden_settings_gc_9_0[] =
88{
89 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400,
b1023571
KW		 90 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
91 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
92 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
93 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
94 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
95 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
96 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff
97};
98
99static const u32 golden_settings_gc_9_0_vg10[] =
100{
101 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
102 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
103 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
104 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
105 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
106 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
107 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800,
108 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007
109};
110
111#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
112
113static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
114static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
115static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
116static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
117static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
118 struct amdgpu_cu_info *cu_info);
119static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
120static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
121
122static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
123{
124 switch (adev->asic_type) {
125 case CHIP_VEGA10:
126 amdgpu_program_register_sequence(adev,
127 golden_settings_gc_9_0,
128 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
129 amdgpu_program_register_sequence(adev,
130 golden_settings_gc_9_0_vg10,
131 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
132 break;
133 default:
134 break;
135 }
136}
137
138static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
139{
140 adev->gfx.scratch.num_reg = 7;
141 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
142 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
143}
144
145static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
146 bool wc, uint32_t reg, uint32_t val)
147{
148 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
149 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
150 WRITE_DATA_DST_SEL(0) |
151 (wc ? WR_CONFIRM : 0));
152 amdgpu_ring_write(ring, reg);
153 amdgpu_ring_write(ring, 0);
154 amdgpu_ring_write(ring, val);
155}
156
157static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
158 int mem_space, int opt, uint32_t addr0,
159 uint32_t addr1, uint32_t ref, uint32_t mask,
160 uint32_t inv)
161{
162 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
163 amdgpu_ring_write(ring,
164 /* memory (1) or register (0) */
165 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
166 WAIT_REG_MEM_OPERATION(opt) | /* wait */
167 WAIT_REG_MEM_FUNCTION(3) | /* equal */
168 WAIT_REG_MEM_ENGINE(eng_sel)));
169
170 if (mem_space)
171 BUG_ON(addr0 & 0x3); /* Dword align */
172 amdgpu_ring_write(ring, addr0);
173 amdgpu_ring_write(ring, addr1);
174 amdgpu_ring_write(ring, ref);
175 amdgpu_ring_write(ring, mask);
176 amdgpu_ring_write(ring, inv); /* poll interval */
177}
178
179static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
180{
181 struct amdgpu_device *adev = ring->adev;
182 uint32_t scratch;
183 uint32_t tmp = 0;
184 unsigned i;
185 int r;
186
187 r = amdgpu_gfx_scratch_get(adev, &scratch);
188 if (r) {
189 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
190 return r;
191 }
192 WREG32(scratch, 0xCAFEDEAD);
193 r = amdgpu_ring_alloc(ring, 3);
194 if (r) {
195 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
196 ring->idx, r);
197 amdgpu_gfx_scratch_free(adev, scratch);
198 return r;
199 }
200 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
201 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
202 amdgpu_ring_write(ring, 0xDEADBEEF);
203 amdgpu_ring_commit(ring);
204
205 for (i = 0; i < adev->usec_timeout; i++) {
206 tmp = RREG32(scratch);
207 if (tmp == 0xDEADBEEF)
208 break;
209 DRM_UDELAY(1);
210 }
211 if (i < adev->usec_timeout) {
212 DRM_INFO("ring test on %d succeeded in %d usecs\n",
213 ring->idx, i);
214 } else {
215 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
216 ring->idx, scratch, tmp);
217 r = -EINVAL;
218 }
219 amdgpu_gfx_scratch_free(adev, scratch);
220 return r;
221}
222
223static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
224{
225 struct amdgpu_device *adev = ring->adev;
226 struct amdgpu_ib ib;
227 struct dma_fence *f = NULL;
228 uint32_t scratch;
229 uint32_t tmp = 0;
230 long r;
231
232 r = amdgpu_gfx_scratch_get(adev, &scratch);
233 if (r) {
234 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
235 return r;
236 }
237 WREG32(scratch, 0xCAFEDEAD);
238 memset(&ib, 0, sizeof(ib));
239 r = amdgpu_ib_get(adev, NULL, 256, &ib);
240 if (r) {
241 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
242 goto err1;
243 }
244 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
245 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
246 ib.ptr[2] = 0xDEADBEEF;
247 ib.length_dw = 3;
248
249 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
250 if (r)
251 goto err2;
252
253 r = dma_fence_wait_timeout(f, false, timeout);
254 if (r == 0) {
255 DRM_ERROR("amdgpu: IB test timed out.\n");
256 r = -ETIMEDOUT;
257 goto err2;
258 } else if (r < 0) {
259 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
260 goto err2;
261 }
262 tmp = RREG32(scratch);
263 if (tmp == 0xDEADBEEF) {
264 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
265 r = 0;
266 } else {
267 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
268 scratch, tmp);
269 r = -EINVAL;
270 }
271err2:
272 amdgpu_ib_free(adev, &ib, NULL);
273 dma_fence_put(f);
274err1:
275 amdgpu_gfx_scratch_free(adev, scratch);
276 return r;
277}
278
279static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
280{
281 const char *chip_name;
282 char fw_name[30];
283 int err;
284 struct amdgpu_firmware_info *info = NULL;
285 const struct common_firmware_header *header = NULL;
286 const struct gfx_firmware_header_v1_0 *cp_hdr;
287
288 DRM_DEBUG("\n");
289
290 switch (adev->asic_type) {
291 case CHIP_VEGA10:
292 chip_name = "vega10";
293 break;
294 default:
295 BUG();
296 }
297
298 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
299 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
300 if (err)
301 goto out;
302 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
303 if (err)
304 goto out;
305 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
306 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
307 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
308
309 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
310 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
311 if (err)
312 goto out;
313 err = amdgpu_ucode_validate(adev->gfx.me_fw);
314 if (err)
315 goto out;
316 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
317 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
318 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
319
320 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
321 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
322 if (err)
323 goto out;
324 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
325 if (err)
326 goto out;
327 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
328 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
329 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
330
331 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
332 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
333 if (err)
334 goto out;
335 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
336 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
337 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
338 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
339
340 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
341 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
342 if (err)
343 goto out;
344 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
345 if (err)
346 goto out;
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
348 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
349 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
350
351
352 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
353 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
354 if (!err) {
355 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
356 if (err)
357 goto out;
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
359 adev->gfx.mec2_fw->data;
360 adev->gfx.mec2_fw_version =
361 le32_to_cpu(cp_hdr->header.ucode_version);
362 adev->gfx.mec2_feature_version =
363 le32_to_cpu(cp_hdr->ucode_feature_version);
364 } else {
365 err = 0;
366 adev->gfx.mec2_fw = NULL;
367 }
368
369 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
370 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
371 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
372 info->fw = adev->gfx.pfp_fw;
373 header = (const struct common_firmware_header *)info->fw->data;
374 adev->firmware.fw_size +=
375 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
376
377 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
378 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
379 info->fw = adev->gfx.me_fw;
380 header = (const struct common_firmware_header *)info->fw->data;
381 adev->firmware.fw_size +=
382 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
383
384 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
385 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
386 info->fw = adev->gfx.ce_fw;
387 header = (const struct common_firmware_header *)info->fw->data;
388 adev->firmware.fw_size +=
389 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
390
391 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
392 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
393 info->fw = adev->gfx.rlc_fw;
394 header = (const struct common_firmware_header *)info->fw->data;
395 adev->firmware.fw_size +=
396 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
397
398 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
399 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
400 info->fw = adev->gfx.mec_fw;
401 header = (const struct common_firmware_header *)info->fw->data;
402 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
403 adev->firmware.fw_size +=
404 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
405
406 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
407 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
408 info->fw = adev->gfx.mec_fw;
409 adev->firmware.fw_size +=
410 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
411
412 if (adev->gfx.mec2_fw) {
413 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
414 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
415 info->fw = adev->gfx.mec2_fw;
416 header = (const struct common_firmware_header *)info->fw->data;
417 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
418 adev->firmware.fw_size +=
419 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
420 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
421 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
422 info->fw = adev->gfx.mec2_fw;
423 adev->firmware.fw_size +=
424 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
425 }
426
427 }
428
429out:
430 if (err) {
431 dev_err(adev->dev,
432 "gfx9: Failed to load firmware \"%s\"\n",
433 fw_name);
434 release_firmware(adev->gfx.pfp_fw);
435 adev->gfx.pfp_fw = NULL;
436 release_firmware(adev->gfx.me_fw);
437 adev->gfx.me_fw = NULL;
438 release_firmware(adev->gfx.ce_fw);
439 adev->gfx.ce_fw = NULL;
440 release_firmware(adev->gfx.rlc_fw);
441 adev->gfx.rlc_fw = NULL;
442 release_firmware(adev->gfx.mec_fw);
443 adev->gfx.mec_fw = NULL;
444 release_firmware(adev->gfx.mec2_fw);
445 adev->gfx.mec2_fw = NULL;
446 }
447 return err;
448}
449
450static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
451{
452 int r;
453
454 if (adev->gfx.mec.hpd_eop_obj) {
c81a1a74 455 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
b1023571
KW		 456 if (unlikely(r != 0))
457 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
458 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
459 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
460
461 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
462 adev->gfx.mec.hpd_eop_obj = NULL;
463 }
464 if (adev->gfx.mec.mec_fw_obj) {
c81a1a74 465 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true);
b1023571
KW		 466 if (unlikely(r != 0))
467 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
468 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
469 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
470
471 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
472 adev->gfx.mec.mec_fw_obj = NULL;
473 }
474}
475
476#define MEC_HPD_SIZE 2048
477
478static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
479{
480 int r;
481 u32 *hpd;
482 const __le32 *fw_data;
483 unsigned fw_size;
484 u32 *fw;
485
486 const struct gfx_firmware_header_v1_0 *mec_hdr;
487
488 /*
489 * we assign only 1 pipe because all other pipes will
490 * be handled by KFD
491 */
492 adev->gfx.mec.num_mec = 1;
493 adev->gfx.mec.num_pipe = 1;
494 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
495
496 if (adev->gfx.mec.hpd_eop_obj == NULL) {
497 r = amdgpu_bo_create(adev,
498 adev->gfx.mec.num_queue * MEC_HPD_SIZE,
499 PAGE_SIZE, true,
500 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
501 &adev->gfx.mec.hpd_eop_obj);
502 if (r) {
503 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
504 return r;
505 }
506 }
507
508 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
509 if (unlikely(r != 0)) {
510 gfx_v9_0_mec_fini(adev);
511 return r;
512 }
513 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
514 &adev->gfx.mec.hpd_eop_gpu_addr);
515 if (r) {
516 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
517 gfx_v9_0_mec_fini(adev);
518 return r;
519 }
520 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
521 if (r) {
522 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
523 gfx_v9_0_mec_fini(adev);
524 return r;
525 }
526
527 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
528
529 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
530 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
531
532 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
533
534 fw_data = (const __le32 *)
535 (adev->gfx.mec_fw->data +
536 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
537 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
538
539 if (adev->gfx.mec.mec_fw_obj == NULL) {
540 r = amdgpu_bo_create(adev,
541 mec_hdr->header.ucode_size_bytes,
542 PAGE_SIZE, true,
543 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
544 &adev->gfx.mec.mec_fw_obj);
545 if (r) {
546 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
547 return r;
548 }
549 }
550
551 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
552 if (unlikely(r != 0)) {
553 gfx_v9_0_mec_fini(adev);
554 return r;
555 }
556 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
557 &adev->gfx.mec.mec_fw_gpu_addr);
558 if (r) {
559 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
560 gfx_v9_0_mec_fini(adev);
561 return r;
562 }
563 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
564 if (r) {
565 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
566 gfx_v9_0_mec_fini(adev);
567 return r;
568 }
569 memcpy(fw, fw_data, fw_size);
570
571 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
572 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
573
574
575 return 0;
576}
577
ac104e99
XY		 578static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev)
579{
580 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
581
582 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
583}
584
585static int gfx_v9_0_kiq_init(struct amdgpu_device *adev)
586{
587 int r;
588 u32 *hpd;
589 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
590
591 r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE,
592 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
593 &kiq->eop_gpu_addr, (void **)&hpd);
594 if (r) {
595 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
596 return r;
597 }
598
599 memset(hpd, 0, MEC_HPD_SIZE);
600
c81a1a74 601 r = amdgpu_bo_reserve(kiq->eop_obj, true);
f7618a63
AD		 602 if (unlikely(r != 0))
603 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
ac104e99 604 amdgpu_bo_kunmap(kiq->eop_obj);
f7618a63 605 amdgpu_bo_unreserve(kiq->eop_obj);
ac104e99
XY		 606
607 return 0;
608}
609
610static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
611 struct amdgpu_ring *ring,
612 struct amdgpu_irq_src *irq)
613{
d72f2f46 614 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
ac104e99
XY		 615 int r = 0;
616
617 r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
618 if (r)
619 return r;
620
621 ring->adev = NULL;
622 ring->ring_obj = NULL;
623 ring->use_doorbell = true;
624 ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
625 if (adev->gfx.mec2_fw) {
626 ring->me = 2;
627 ring->pipe = 0;
628 } else {
629 ring->me = 1;
630 ring->pipe = 1;
631 }
632
ac104e99 633 ring->queue = 0;
d72f2f46 634 ring->eop_gpu_addr = kiq->eop_gpu_addr;
ac104e99
XY		 635 sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
636 r = amdgpu_ring_init(adev, ring, 1024,
637 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
638 if (r)
639 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
640
641 return r;
642}
643static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
644 struct amdgpu_irq_src *irq)
645{
646 amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
647 amdgpu_ring_fini(ring);
ac104e99
XY		 648}
649
464826d6 650/* create MQD for each compute queue */
e935c211 651static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev)
464826d6
XY		 652{
653 struct amdgpu_ring *ring = NULL;
654 int r, i;
655
656 /* create MQD for KIQ */
657 ring = &adev->gfx.kiq.ring;
658 if (!ring->mqd_obj) {
659 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
b4fcf7f0
AD		 660 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
661 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
464826d6
XY		 662 if (r) {
663 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
664 return r;
665 }
666
667 /*TODO: prepare MQD backup */
668 }
669
670 /* create MQD for each KCQ */
b4fcf7f0 671 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
464826d6
XY		 672 ring = &adev->gfx.compute_ring[i];
673 if (!ring->mqd_obj) {
674 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
b4fcf7f0
AD		 675 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
676 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
464826d6
XY		 677 if (r) {
678 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
679 return r;
680 }
681
682 /* TODO: prepare MQD backup */
683 }
684 }
685
686 return 0;
687}
688
e935c211 689static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev)
464826d6
XY		 690{
691 struct amdgpu_ring *ring = NULL;
692 int i;
693
694 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
695 ring = &adev->gfx.compute_ring[i];
696 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
697 }
698
699 ring = &adev->gfx.kiq.ring;
700 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
701}
702
b1023571
KW		 703static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
704{
5e78835a 705 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 706 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
707 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
708 (address << SQ_IND_INDEX__INDEX__SHIFT) |
709 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 710 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 711}
712
713static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
714 uint32_t wave, uint32_t thread,
715 uint32_t regno, uint32_t num, uint32_t *out)
716{
5e78835a 717 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 718 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
719 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
720 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
721 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
722 (SQ_IND_INDEX__FORCE_READ_MASK) |
723 (SQ_IND_INDEX__AUTO_INCR_MASK));
724 while (num--)
5e78835a 725 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 726}
727
728static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
729{
730 /* type 1 wave data */
731 dst[(*no_fields)++] = 1;
732 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
733 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
734 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
735 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
736 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
737 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
738 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
739 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
740 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
741 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
742 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
743 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
744 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
745 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
746}
747
748static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
749 uint32_t wave, uint32_t start,
750 uint32_t size, uint32_t *dst)
751{
752 wave_read_regs(
753 adev, simd, wave, 0,
754 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
755}
756
757
758static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
759 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
760 .select_se_sh = &gfx_v9_0_select_se_sh,
761 .read_wave_data = &gfx_v9_0_read_wave_data,
762 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
763};
764
765static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
766{
767 u32 gb_addr_config;
768
769 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
770
771 switch (adev->asic_type) {
772 case CHIP_VEGA10:
773 adev->gfx.config.max_shader_engines = 4;
774 adev->gfx.config.max_tile_pipes = 8; //??
775 adev->gfx.config.max_cu_per_sh = 16;
776 adev->gfx.config.max_sh_per_se = 1;
777 adev->gfx.config.max_backends_per_se = 4;
778 adev->gfx.config.max_texture_channel_caches = 16;
779 adev->gfx.config.max_gprs = 256;
780 adev->gfx.config.max_gs_threads = 32;
781 adev->gfx.config.max_hw_contexts = 8;
782
783 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
784 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
785 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
786 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
408bfe7c
JZ		 787 adev->gfx.config.gs_vgt_table_depth = 32;
788 adev->gfx.config.gs_prim_buffer_depth = 1792;
789 adev->gfx.config.max_gs_waves_per_vgt = 32;
b1023571
KW		 790 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
791 break;
792 default:
793 BUG();
794 break;
795 }
796
797 adev->gfx.config.gb_addr_config = gb_addr_config;
798
799 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
800 REG_GET_FIELD(
801 adev->gfx.config.gb_addr_config,
802 GB_ADDR_CONFIG,
803 NUM_PIPES);
804 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
805 REG_GET_FIELD(
806 adev->gfx.config.gb_addr_config,
807 GB_ADDR_CONFIG,
808 NUM_BANKS);
809 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
810 REG_GET_FIELD(
811 adev->gfx.config.gb_addr_config,
812 GB_ADDR_CONFIG,
813 MAX_COMPRESSED_FRAGS);
814 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
815 REG_GET_FIELD(
816 adev->gfx.config.gb_addr_config,
817 GB_ADDR_CONFIG,
818 NUM_RB_PER_SE);
819 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
820 REG_GET_FIELD(
821 adev->gfx.config.gb_addr_config,
822 GB_ADDR_CONFIG,
823 NUM_SHADER_ENGINES);
824 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
825 REG_GET_FIELD(
826 adev->gfx.config.gb_addr_config,
827 GB_ADDR_CONFIG,
828 PIPE_INTERLEAVE_SIZE));
829}
830
831static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
832 struct amdgpu_ngg_buf *ngg_buf,
833 int size_se,
834 int default_size_se)
835{
836 int r;
837
838 if (size_se < 0) {
839 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
840 return -EINVAL;
841 }
842 size_se = size_se ? size_se : default_size_se;
843
42ce2243 844 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 845 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
846 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
847 &ngg_buf->bo,
848 &ngg_buf->gpu_addr,
849 NULL);
850 if (r) {
851 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
852 return r;
853 }
854 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
855
856 return r;
857}
858
859static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
860{
861 int i;
862
863 for (i = 0; i < NGG_BUF_MAX; i++)
864 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
865 &adev->gfx.ngg.buf[i].gpu_addr,
866 NULL);
867
868 memset(&adev->gfx.ngg.buf[0], 0,
869 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
870
871 adev->gfx.ngg.init = false;
872
873 return 0;
874}
875
876static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
877{
878 int r;
879
880 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
881 return 0;
882
883 /* GDS reserve memory: 64 bytes alignment */
884 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
885 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
886 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
887 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
888 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
889
890 /* Primitive Buffer */
891 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PRIM],
892 amdgpu_prim_buf_per_se,
893 64 * 1024);
894 if (r) {
895 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
896 goto err;
897 }
898
899 /* Position Buffer */
900 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[POS],
901 amdgpu_pos_buf_per_se,
902 256 * 1024);
903 if (r) {
904 dev_err(adev->dev, "Failed to create Position Buffer\n");
905 goto err;
906 }
907
908 /* Control Sideband */
909 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[CNTL],
910 amdgpu_cntl_sb_buf_per_se,
911 256);
912 if (r) {
913 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
914 goto err;
915 }
916
917 /* Parameter Cache, not created by default */
918 if (amdgpu_param_buf_per_se <= 0)
919 goto out;
920
921 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PARAM],
922 amdgpu_param_buf_per_se,
923 512 * 1024);
924 if (r) {
925 dev_err(adev->dev, "Failed to create Parameter Cache\n");
926 goto err;
927 }
928
929out:
930 adev->gfx.ngg.init = true;
931 return 0;
932err:
933 gfx_v9_0_ngg_fini(adev);
934 return r;
935}
936
937static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
938{
939 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
940 int r;
941 u32 data;
942 u32 size;
943 u32 base;
944
945 if (!amdgpu_ngg)
946 return 0;
947
948 /* Program buffer size */
949 data = 0;
950 size = adev->gfx.ngg.buf[PRIM].size / 256;
951 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
952
953 size = adev->gfx.ngg.buf[POS].size / 256;
954 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
955
5e78835a 956 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571
KW		 957
958 data = 0;
959 size = adev->gfx.ngg.buf[CNTL].size / 256;
960 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
961
962 size = adev->gfx.ngg.buf[PARAM].size / 1024;
963 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
964
5e78835a 965 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 966
967 /* Program buffer base address */
968 base = lower_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
969 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 970 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571
KW		 971
972 base = upper_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
973 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 974 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571
KW		 975
976 base = lower_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
977 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 978 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571
KW		 979
980 base = upper_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
981 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 982 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571
KW		 983
984 base = lower_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
985 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 986 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571
KW		 987
988 base = upper_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
989 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 990 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 991
992 /* Clear GDS reserved memory */
993 r = amdgpu_ring_alloc(ring, 17);
994 if (r) {
995 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
996 ring->idx, r);
997 return r;
998 }
999
1000 gfx_v9_0_write_data_to_reg(ring, 0, false,
1001 amdgpu_gds_reg_offset[0].mem_size,
1002 (adev->gds.mem.total_size +
1003 adev->gfx.ngg.gds_reserve_size) >>
1004 AMDGPU_GDS_SHIFT);
1005
1006 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1007 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1008 PACKET3_DMA_DATA_SRC_SEL(2)));
1009 amdgpu_ring_write(ring, 0);
1010 amdgpu_ring_write(ring, 0);
1011 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1012 amdgpu_ring_write(ring, 0);
1013 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1014
1015
1016 gfx_v9_0_write_data_to_reg(ring, 0, false,
1017 amdgpu_gds_reg_offset[0].mem_size, 0);
1018
1019 amdgpu_ring_commit(ring);
1020
1021 return 0;
1022}
1023
1024static int gfx_v9_0_sw_init(void *handle)
1025{
1026 int i, r;
1027 struct amdgpu_ring *ring;
ac104e99 1028 struct amdgpu_kiq *kiq;
b1023571
KW		 1029 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1030
97031e25
XY		 1031 /* KIQ event */
1032 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1033 if (r)
1034 return r;
1035
b1023571
KW		 1036 /* EOP Event */
1037 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1038 if (r)
1039 return r;
1040
1041 /* Privileged reg */
1042 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1043 &adev->gfx.priv_reg_irq);
1044 if (r)
1045 return r;
1046
1047 /* Privileged inst */
1048 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1049 &adev->gfx.priv_inst_irq);
1050 if (r)
1051 return r;
1052
1053 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1054
1055 gfx_v9_0_scratch_init(adev);
1056
1057 r = gfx_v9_0_init_microcode(adev);
1058 if (r) {
1059 DRM_ERROR("Failed to load gfx firmware!\n");
1060 return r;
1061 }
1062
1063 r = gfx_v9_0_mec_init(adev);
1064 if (r) {
1065 DRM_ERROR("Failed to init MEC BOs!\n");
1066 return r;
1067 }
1068
1069 /* set up the gfx ring */
1070 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1071 ring = &adev->gfx.gfx_ring[i];
1072 ring->ring_obj = NULL;
1073 sprintf(ring->name, "gfx");
1074 ring->use_doorbell = true;
1075 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1076 r = amdgpu_ring_init(adev, ring, 1024,
1077 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1078 if (r)
1079 return r;
1080 }
1081
1082 /* set up the compute queues */
1083 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1084 unsigned irq_type;
1085
1086 /* max 32 queues per MEC */
1087 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1088 DRM_ERROR("Too many (%d) compute rings!\n", i);
1089 break;
1090 }
1091 ring = &adev->gfx.compute_ring[i];
1092 ring->ring_obj = NULL;
1093 ring->use_doorbell = true;
1094 ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1;
1095 ring->me = 1; /* first MEC */
1096 ring->pipe = i / 8;
1097 ring->queue = i % 8;
d72f2f46 1098 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
e182e234 1099 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
b1023571
KW		 1100 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1101 /* type-2 packets are deprecated on MEC, use type-3 instead */
1102 r = amdgpu_ring_init(adev, ring, 1024,
1103 &adev->gfx.eop_irq, irq_type);
1104 if (r)
1105 return r;
1106 }
1107
ac104e99
XY		 1108 if (amdgpu_sriov_vf(adev)) {
1109 r = gfx_v9_0_kiq_init(adev);
1110 if (r) {
1111 DRM_ERROR("Failed to init KIQ BOs!\n");
1112 return r;
1113 }
1114
1115 kiq = &adev->gfx.kiq;
1116 r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1117 if (r)
1118 return r;
464826d6
XY		 1119
1120 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
e935c211 1121 r = gfx_v9_0_compute_mqd_sw_init(adev);
464826d6
XY		 1122 if (r)
1123 return r;
ac104e99
XY		 1124 }
1125
b1023571
KW		 1126 /* reserve GDS, GWS and OA resource for gfx */
1127 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1128 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1129 &adev->gds.gds_gfx_bo, NULL, NULL);
1130 if (r)
1131 return r;
1132
1133 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1134 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1135 &adev->gds.gws_gfx_bo, NULL, NULL);
1136 if (r)
1137 return r;
1138
1139 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1140 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1141 &adev->gds.oa_gfx_bo, NULL, NULL);
1142 if (r)
1143 return r;
1144
1145 adev->gfx.ce_ram_size = 0x8000;
1146
1147 gfx_v9_0_gpu_early_init(adev);
1148
1149 r = gfx_v9_0_ngg_init(adev);
1150 if (r)
1151 return r;
1152
1153 return 0;
1154}
1155
1156
1157static int gfx_v9_0_sw_fini(void *handle)
1158{
1159 int i;
1160 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1161
1162 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1163 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1164 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1165
1166 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1167 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1168 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1169 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1170
ac104e99 1171 if (amdgpu_sriov_vf(adev)) {
e935c211 1172 gfx_v9_0_compute_mqd_sw_fini(adev);
ac104e99
XY		 1173 gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1174 gfx_v9_0_kiq_fini(adev);
1175 }
1176
b1023571
KW		 1177 gfx_v9_0_mec_fini(adev);
1178 gfx_v9_0_ngg_fini(adev);
1179
1180 return 0;
1181}
1182
1183
1184static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1185{
1186 /* TODO */
1187}
1188
1189static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1190{
1191 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1192
1193 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1194 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1195 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1196 } else if (se_num == 0xffffffff) {
1197 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1198 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1199 } else if (sh_num == 0xffffffff) {
1200 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1201 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1202 } else {
1203 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1204 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1205 }
5e78835a 1206 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1207}
1208
1209static u32 gfx_v9_0_create_bitmask(u32 bit_width)
1210{
1211 return (u32)((1ULL << bit_width) - 1);
1212}
1213
1214static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1215{
1216 u32 data, mask;
1217
5e78835a
TSD		 1218 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1219 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1220
1221 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1222 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1223
1224 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1225 adev->gfx.config.max_sh_per_se);
1226
1227 return (~data) & mask;
1228}
1229
1230static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1231{
1232 int i, j;
2572c24c 1233 u32 data;
b1023571
KW		 1234 u32 active_rbs = 0;
1235 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1236 adev->gfx.config.max_sh_per_se;
1237
1238 mutex_lock(&adev->grbm_idx_mutex);
1239 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1240 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1241 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1242 data = gfx_v9_0_get_rb_active_bitmap(adev);
1243 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1244 rb_bitmap_width_per_sh);
1245 }
1246 }
1247 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1248 mutex_unlock(&adev->grbm_idx_mutex);
1249
1250 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1251 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1252}
1253
1254#define DEFAULT_SH_MEM_BASES (0x6000)
1255#define FIRST_COMPUTE_VMID (8)
1256#define LAST_COMPUTE_VMID (16)
1257static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1258{
1259 int i;
1260 uint32_t sh_mem_config;
1261 uint32_t sh_mem_bases;
1262
1263 /*
1264 * Configure apertures:
1265 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1266 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1267 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1268 */
1269 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1270
1271 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1272 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1273 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1274
1275 mutex_lock(&adev->srbm_mutex);
1276 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1277 soc15_grbm_select(adev, 0, 0, 0, i);
1278 /* CP and shaders */
5e78835a
TSD		 1279 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1280 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1281 }
1282 soc15_grbm_select(adev, 0, 0, 0, 0);
1283 mutex_unlock(&adev->srbm_mutex);
1284}
1285
1286static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1287{
1288 u32 tmp;
1289 int i;
1290
40f06773 1291 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1292
1293 gfx_v9_0_tiling_mode_table_init(adev);
1294
1295 gfx_v9_0_setup_rb(adev);
1296 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1297
1298 /* XXX SH_MEM regs */
1299 /* where to put LDS, scratch, GPUVM in FSA64 space */
1300 mutex_lock(&adev->srbm_mutex);
1301 for (i = 0; i < 16; i++) {
1302 soc15_grbm_select(adev, 0, 0, 0, i);
1303 /* CP and shaders */
1304 tmp = 0;
1305 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1306 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5e78835a
TSD		 1307 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1308 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
b1023571
KW		 1309 }
1310 soc15_grbm_select(adev, 0, 0, 0, 0);
1311
1312 mutex_unlock(&adev->srbm_mutex);
1313
1314 gfx_v9_0_init_compute_vmid(adev);
1315
1316 mutex_lock(&adev->grbm_idx_mutex);
1317 /*
1318 * making sure that the following register writes will be broadcasted
1319 * to all the shaders
1320 */
1321 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1322
5e78835a 1323 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1324 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1325 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1326 (adev->gfx.config.sc_prim_fifo_size_backend <<
1327 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1328 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1329 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1330 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1331 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1332 mutex_unlock(&adev->grbm_idx_mutex);
1333
1334}
1335
1336static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1337{
1338 u32 i, j, k;
1339 u32 mask;
1340
1341 mutex_lock(&adev->grbm_idx_mutex);
1342 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1343 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1344 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1345 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1346 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1347 break;
1348 udelay(1);
1349 }
1350 }
1351 }
1352 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1353 mutex_unlock(&adev->grbm_idx_mutex);
1354
1355 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1356 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1357 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1358 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1359 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1360 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1361 break;
1362 udelay(1);
1363 }
1364}
1365
1366static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1367 bool enable)
1368{
5e78835a 1369 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571
KW		 1370
1371 if (enable)
1372 return;
1373
1374 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1375 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1376 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1377 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1378
5e78835a 1379 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1380}
1381
1382void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1383{
5e78835a 1384 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 1385
1386 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5e78835a 1387 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
b1023571
KW		 1388
1389 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1390
1391 gfx_v9_0_wait_for_rlc_serdes(adev);
1392}
1393
1394static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1395{
596c8e8b 1396 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 1397 udelay(50);
596c8e8b 1398 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 1399 udelay(50);
1400}
1401
1402static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1403{
1404#ifdef AMDGPU_RLC_DEBUG_RETRY
1405 u32 rlc_ucode_ver;
1406#endif
b1023571 1407
342cda25 1408 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 1409
1410 /* carrizo do enable cp interrupt after cp inited */
1411 if (!(adev->flags & AMD_IS_APU))
1412 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1413
1414 udelay(50);
1415
1416#ifdef AMDGPU_RLC_DEBUG_RETRY
1417 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 1418 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 1419 if(rlc_ucode_ver == 0x108) {
1420 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1421 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1422 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1423 * default is 0x9C4 to create a 100us interval */
5e78835a 1424 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571
KW		 1425 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1426 * to disable the page fault retry interrupts, default is
1427 * 0x100 (256) */
5e78835a 1428 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 1429 }
1430#endif
1431}
1432
1433static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
1434{
1435 const struct rlc_firmware_header_v2_0 *hdr;
1436 const __le32 *fw_data;
1437 unsigned i, fw_size;
1438
1439 if (!adev->gfx.rlc_fw)
1440 return -EINVAL;
1441
1442 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1443 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1444
1445 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1446 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1447 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1448
5e78835a 1449 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 1450 RLCG_UCODE_LOADING_START_ADDRESS);
1451 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 1452 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
1453 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 1454
1455 return 0;
1456}
1457
1458static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
1459{
1460 int r;
1461
cfee05bc
ML		 1462 if (amdgpu_sriov_vf(adev))
1463 return 0;
1464
b1023571
KW		 1465 gfx_v9_0_rlc_stop(adev);
1466
1467 /* disable CG */
5e78835a 1468 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 1469
1470 /* disable PG */
5e78835a 1471 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 1472
1473 gfx_v9_0_rlc_reset(adev);
1474
1475 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1476 /* legacy rlc firmware loading */
1477 r = gfx_v9_0_rlc_load_microcode(adev);
1478 if (r)
1479 return r;
1480 }
1481
1482 gfx_v9_0_rlc_start(adev);
1483
1484 return 0;
1485}
1486
1487static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1488{
1489 int i;
5e78835a 1490 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 1491
ea64468e
TSD		 1492 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
1493 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
1494 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
1495 if (!enable) {
b1023571
KW		 1496 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1497 adev->gfx.gfx_ring[i].ready = false;
1498 }
5e78835a 1499 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 1500 udelay(50);
1501}
1502
1503static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1504{
1505 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1506 const struct gfx_firmware_header_v1_0 *ce_hdr;
1507 const struct gfx_firmware_header_v1_0 *me_hdr;
1508 const __le32 *fw_data;
1509 unsigned i, fw_size;
1510
1511 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1512 return -EINVAL;
1513
1514 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
1515 adev->gfx.pfp_fw->data;
1516 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
1517 adev->gfx.ce_fw->data;
1518 me_hdr = (const struct gfx_firmware_header_v1_0 *)
1519 adev->gfx.me_fw->data;
1520
1521 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1522 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1523 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1524
1525 gfx_v9_0_cp_gfx_enable(adev, false);
1526
1527 /* PFP */
1528 fw_data = (const __le32 *)
1529 (adev->gfx.pfp_fw->data +
1530 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1531 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 1532 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 1533 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 1534 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1535 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 1536
1537 /* CE */
1538 fw_data = (const __le32 *)
1539 (adev->gfx.ce_fw->data +
1540 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1541 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 1542 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 1543 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 1544 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1545 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 1546
1547 /* ME */
1548 fw_data = (const __le32 *)
1549 (adev->gfx.me_fw->data +
1550 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1551 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 1552 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 1553 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 1554 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1555 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 1556
1557 return 0;
1558}
1559
1560static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1561{
1562 u32 count = 0;
1563 const struct cs_section_def *sect = NULL;
1564 const struct cs_extent_def *ext = NULL;
1565
1566 /* begin clear state */
1567 count += 2;
1568 /* context control state */
1569 count += 3;
1570
1571 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1572 for (ext = sect->section; ext->extent != NULL; ++ext) {
1573 if (sect->id == SECT_CONTEXT)
1574 count += 2 + ext->reg_count;
1575 else
1576 return 0;
1577 }
1578 }
1579 /* pa_sc_raster_config/pa_sc_raster_config1 */
1580 count += 4;
1581 /* end clear state */
1582 count += 2;
1583 /* clear state */
1584 count += 2;
1585
1586 return count;
1587}
1588
1589static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
1590{
1591 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1592 const struct cs_section_def *sect = NULL;
1593 const struct cs_extent_def *ext = NULL;
1594 int r, i;
1595
1596 /* init the CP */
5e78835a
TSD		 1597 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
1598 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 1599
1600 gfx_v9_0_cp_gfx_enable(adev, true);
1601
1602 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
1603 if (r) {
1604 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1605 return r;
1606 }
1607
1608 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1609 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1610
1611 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1612 amdgpu_ring_write(ring, 0x80000000);
1613 amdgpu_ring_write(ring, 0x80000000);
1614
1615 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1616 for (ext = sect->section; ext->extent != NULL; ++ext) {
1617 if (sect->id == SECT_CONTEXT) {
1618 amdgpu_ring_write(ring,
1619 PACKET3(PACKET3_SET_CONTEXT_REG,
1620 ext->reg_count));
1621 amdgpu_ring_write(ring,
1622 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1623 for (i = 0; i < ext->reg_count; i++)
1624 amdgpu_ring_write(ring, ext->extent[i]);
1625 }
1626 }
1627 }
1628
1629 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1630 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1631
1632 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1633 amdgpu_ring_write(ring, 0);
1634
1635 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1636 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1637 amdgpu_ring_write(ring, 0x8000);
1638 amdgpu_ring_write(ring, 0x8000);
1639
1640 amdgpu_ring_commit(ring);
1641
1642 return 0;
1643}
1644
1645static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
1646{
1647 struct amdgpu_ring *ring;
1648 u32 tmp;
1649 u32 rb_bufsz;
3fc08b61 1650 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 1651
1652 /* Set the write pointer delay */
5e78835a 1653 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 1654
1655 /* set the RB to use vmid 0 */
5e78835a 1656 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 1657
1658 /* Set ring buffer size */
1659 ring = &adev->gfx.gfx_ring[0];
1660 rb_bufsz = order_base_2(ring->ring_size / 8);
1661 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
1662 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
1663#ifdef __BIG_ENDIAN
1664 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
1665#endif
5e78835a 1666 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 1667
1668 /* Initialize the ring buffer's write pointers */
1669 ring->wptr = 0;
5e78835a
TSD		 1670 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
1671 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 1672
1673 /* set the wb address wether it's enabled or not */
1674 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 1675 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
1676 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 1677
3fc08b61 1678 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 1679 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
1680 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 1681
b1023571 1682 mdelay(1);
5e78835a 1683 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 1684
1685 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 1686 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
1687 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 1688
5e78835a 1689 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 1690 if (ring->use_doorbell) {
1691 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1692 DOORBELL_OFFSET, ring->doorbell_index);
1693 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1694 DOORBELL_EN, 1);
1695 } else {
1696 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
1697 }
5e78835a 1698 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 1699
1700 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
1701 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 1702 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 1703
5e78835a 1704 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 1705 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
1706
1707
1708 /* start the ring */
1709 gfx_v9_0_cp_gfx_start(adev);
1710 ring->ready = true;
1711
1712 return 0;
1713}
1714
1715static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
1716{
1717 int i;
1718
1719 if (enable) {
5e78835a 1720 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 1721 } else {
5e78835a 1722 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 1723 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1724 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1725 adev->gfx.compute_ring[i].ready = false;
ac104e99 1726 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 1727 }
1728 udelay(50);
1729}
1730
1731static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
1732{
1733 gfx_v9_0_cp_compute_enable(adev, true);
1734
1735 return 0;
1736}
1737
1738static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
1739{
1740 const struct gfx_firmware_header_v1_0 *mec_hdr;
1741 const __le32 *fw_data;
1742 unsigned i;
1743 u32 tmp;
1744
1745 if (!adev->gfx.mec_fw)
1746 return -EINVAL;
1747
1748 gfx_v9_0_cp_compute_enable(adev, false);
1749
1750 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1751 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1752
1753 fw_data = (const __le32 *)
1754 (adev->gfx.mec_fw->data +
1755 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1756 tmp = 0;
1757 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1758 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 1759 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 1760
5e78835a 1761 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 1762 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 1763 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571
KW		 1764 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1765
1766 /* MEC1 */
5e78835a 1767 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 1768 mec_hdr->jt_offset);
1769 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 1770 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 1771 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1772
5e78835a 1773 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 1774 adev->gfx.mec_fw_version);
1775 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1776
1777 return 0;
1778}
1779
1780static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
1781{
1782 int i, r;
1783
1784 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1785 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1786
1787 if (ring->mqd_obj) {
c81a1a74 1788 r = amdgpu_bo_reserve(ring->mqd_obj, true);
b1023571
KW		 1789 if (unlikely(r != 0))
1790 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
1791
1792 amdgpu_bo_unpin(ring->mqd_obj);
1793 amdgpu_bo_unreserve(ring->mqd_obj);
1794
1795 amdgpu_bo_unref(&ring->mqd_obj);
1796 ring->mqd_obj = NULL;
1797 }
1798 }
1799}
1800
1801static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
1802
1803static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
1804{
1805 int i, r;
1806 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1807 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1808 if (gfx_v9_0_init_queue(ring))
1809 dev_warn(adev->dev, "compute queue %d init failed!\n", i);
1810 }
1811
1812 r = gfx_v9_0_cp_compute_start(adev);
1813 if (r)
1814 return r;
1815
1816 return 0;
1817}
1818
464826d6
XY		 1819/* KIQ functions */
1820static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
1821{
1822 uint32_t tmp;
1823 struct amdgpu_device *adev = ring->adev;
1824
1825 /* tell RLC which is KIQ queue */
5e78835a 1826 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 1827 tmp &= 0xffffff00;
1828 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 1829 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 1830 tmp |= 0x80;
5e78835a 1831 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6
XY		 1832}
1833
1834static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
1835{
1836 amdgpu_ring_alloc(ring, 8);
1837 /* set resources */
1838 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
1839 amdgpu_ring_write(ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
1840 amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */
1841 amdgpu_ring_write(ring, 0); /* queue mask hi */
1842 amdgpu_ring_write(ring, 0); /* gws mask lo */
1843 amdgpu_ring_write(ring, 0); /* gws mask hi */
1844 amdgpu_ring_write(ring, 0); /* oac mask */
1845 amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */
1846 amdgpu_ring_commit(ring);
1847 udelay(50);
1848}
1849
1850static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
1851 struct amdgpu_ring *ring)
1852{
1853 struct amdgpu_device *adev = kiq_ring->adev;
1854 uint64_t mqd_addr, wptr_addr;
1855
1856 mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
1857 wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1858 amdgpu_ring_alloc(kiq_ring, 8);
1859
1860 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
1861 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
1862 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
1863 (0 << 4) | /* Queue_Sel */
1864 (0 << 8) | /* VMID */
1865 (ring->queue << 13 ) |
1866 (ring->pipe << 16) |
1867 ((ring->me == 1 ? 0 : 1) << 18) |
1868 (0 << 21) | /*queue_type: normal compute queue */
1869 (1 << 24) | /* alloc format: all_on_one_pipe */
1870 (0 << 26) | /* engine_sel: compute */
1871 (1 << 29)); /* num_queues: must be 1 */
1872 amdgpu_ring_write(kiq_ring, (ring->doorbell_index << 2));
1873 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
1874 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
1875 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
1876 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
1877 amdgpu_ring_commit(kiq_ring);
1878 udelay(50);
1879}
1880
e322edc3 1881static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 1882{
33fb8698 1883 struct amdgpu_device *adev = ring->adev;
e322edc3 1884 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 1885 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1886 uint32_t tmp;
1887
1888 mqd->header = 0xC0310800;
1889 mqd->compute_pipelinestat_enable = 0x00000001;
1890 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1891 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1892 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1893 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1894 mqd->compute_misc_reserved = 0x00000003;
1895
d72f2f46 1896 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 1897 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
1898 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1899
1900 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 1901 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6
XY		 1902 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1903 (order_base_2(MEC_HPD_SIZE / 4) - 1));
1904
1905 mqd->cp_hqd_eop_control = tmp;
1906
1907 /* enable doorbell? */
5e78835a 1908 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 1909
1910 if (ring->use_doorbell) {
1911 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1912 DOORBELL_OFFSET, ring->doorbell_index);
1913 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1914 DOORBELL_EN, 1);
1915 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1916 DOORBELL_SOURCE, 0);
1917 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1918 DOORBELL_HIT, 0);
1919 }
1920 else
1921 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1922 DOORBELL_EN, 0);
1923
1924 mqd->cp_hqd_pq_doorbell_control = tmp;
1925
1926 /* disable the queue if it's active */
1927 ring->wptr = 0;
1928 mqd->cp_hqd_dequeue_request = 0;
1929 mqd->cp_hqd_pq_rptr = 0;
1930 mqd->cp_hqd_pq_wptr_lo = 0;
1931 mqd->cp_hqd_pq_wptr_hi = 0;
1932
1933 /* set the pointer to the MQD */
33fb8698
AD		 1934 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1935 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 1936
1937 /* set MQD vmid to 0 */
5e78835a 1938 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 1939 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1940 mqd->cp_mqd_control = tmp;
1941
1942 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1943 hqd_gpu_addr = ring->gpu_addr >> 8;
1944 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
1945 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1946
1947 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 1948 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 1949 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1950 (order_base_2(ring->ring_size / 4) - 1));
1951 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1952 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1953#ifdef __BIG_ENDIAN
1954 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
1955#endif
1956 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
1957 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
1958 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1959 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1960 mqd->cp_hqd_pq_control = tmp;
1961
1962 /* set the wb address whether it's enabled or not */
1963 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1964 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1965 mqd->cp_hqd_pq_rptr_report_addr_hi =
1966 upper_32_bits(wb_gpu_addr) & 0xffff;
1967
1968 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1969 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1970 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
1971 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1972
1973 tmp = 0;
1974 /* enable the doorbell if requested */
1975 if (ring->use_doorbell) {
5e78835a 1976 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 1977 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1978 DOORBELL_OFFSET, ring->doorbell_index);
1979
1980 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1981 DOORBELL_EN, 1);
1982 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1983 DOORBELL_SOURCE, 0);
1984 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1985 DOORBELL_HIT, 0);
1986 }
1987
1988 mqd->cp_hqd_pq_doorbell_control = tmp;
1989
1990 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1991 ring->wptr = 0;
0274a9c5 1992 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 1993
1994 /* set the vmid for the queue */
1995 mqd->cp_hqd_vmid = 0;
1996
0274a9c5 1997 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 1998 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
1999 mqd->cp_hqd_persistent_state = tmp;
2000
2001 /* activate the queue */
2002 mqd->cp_hqd_active = 1;
2003
2004 return 0;
2005}
2006
e322edc3 2007static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2008{
33fb8698 2009 struct amdgpu_device *adev = ring->adev;
e322edc3 2010 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2011 int j;
2012
2013 /* disable wptr polling */
72edadd5 2014 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2015
5e78835a 2016 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2017 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2018 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2019 mqd->cp_hqd_eop_base_addr_hi);
2020
2021 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2022 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2023 mqd->cp_hqd_eop_control);
2024
2025 /* enable doorbell? */
5e78835a 2026 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2027 mqd->cp_hqd_pq_doorbell_control);
2028
2029 /* disable the queue if it's active */
5e78835a
TSD		 2030 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2031 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2032 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2033 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2034 break;
2035 udelay(1);
2036 }
5e78835a 2037 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2038 mqd->cp_hqd_dequeue_request);
5e78835a 2039 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2040 mqd->cp_hqd_pq_rptr);
5e78835a 2041 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2042 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2043 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2044 mqd->cp_hqd_pq_wptr_hi);
2045 }
2046
2047 /* set the pointer to the MQD */
5e78835a 2048 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2049 mqd->cp_mqd_base_addr_lo);
5e78835a 2050 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2051 mqd->cp_mqd_base_addr_hi);
2052
2053 /* set MQD vmid to 0 */
5e78835a 2054 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2055 mqd->cp_mqd_control);
2056
2057 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2058 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2059 mqd->cp_hqd_pq_base_lo);
5e78835a 2060 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2061 mqd->cp_hqd_pq_base_hi);
2062
2063 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2064 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2065 mqd->cp_hqd_pq_control);
2066
2067 /* set the wb address whether it's enabled or not */
5e78835a 2068 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2069 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2070 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2071 mqd->cp_hqd_pq_rptr_report_addr_hi);
2072
2073 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2074 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2075 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2076 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2077 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2078
2079 /* enable the doorbell if requested */
2080 if (ring->use_doorbell) {
5e78835a 2081 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2082 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2083 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2084 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2085 }
2086
5e78835a 2087 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2088 mqd->cp_hqd_pq_doorbell_control);
2089
2090 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2091 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2092 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2093 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2094 mqd->cp_hqd_pq_wptr_hi);
2095
2096 /* set the vmid for the queue */
5e78835a 2097 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2098
5e78835a 2099 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2100 mqd->cp_hqd_persistent_state);
2101
2102 /* activate the queue */
5e78835a 2103 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2104 mqd->cp_hqd_active);
2105
72edadd5
TSD		 2106 if (ring->use_doorbell)
2107 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2108
2109 return 0;
2110}
2111
e322edc3 2112static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2113{
2114 struct amdgpu_device *adev = ring->adev;
2115 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
e322edc3 2116 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2117 bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
2118 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2119
2120 if (is_kiq) {
464826d6
XY		 2121 gfx_v9_0_kiq_setting(&kiq->ring);
2122 } else {
464826d6
XY		 2123 mqd_idx = ring - &adev->gfx.compute_ring[0];
2124 }
2125
2126 if (!adev->gfx.in_reset) {
2127 memset((void *)mqd, 0, sizeof(*mqd));
2128 mutex_lock(&adev->srbm_mutex);
2129 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2130 gfx_v9_0_mqd_init(ring);
464826d6 2131 if (is_kiq)
e322edc3 2132 gfx_v9_0_kiq_init_register(ring);
464826d6
XY		 2133 soc15_grbm_select(adev, 0, 0, 0, 0);
2134 mutex_unlock(&adev->srbm_mutex);
2135
2136 } else { /* for GPU_RESET case */
2137 /* reset MQD to a clean status */
2138
2139 /* reset ring buffer */
2140 ring->wptr = 0;
2141
2142 if (is_kiq) {
2143 mutex_lock(&adev->srbm_mutex);
2144 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2145 gfx_v9_0_kiq_init_register(ring);
464826d6
XY		 2146 soc15_grbm_select(adev, 0, 0, 0, 0);
2147 mutex_unlock(&adev->srbm_mutex);
2148 }
2149 }
2150
2151 if (is_kiq)
2152 gfx_v9_0_kiq_enable(ring);
2153 else
2154 gfx_v9_0_map_queue_enable(&kiq->ring, ring);
2155
2156 return 0;
2157}
2158
2159static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2160{
2161 struct amdgpu_ring *ring = NULL;
2162 int r = 0, i;
2163
2164 gfx_v9_0_cp_compute_enable(adev, true);
2165
2166 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2167
2168 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2169 if (unlikely(r != 0))
2170 goto done;
2171
2172 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2173 if (!r) {
e322edc3 2174 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2175 amdgpu_bo_kunmap(ring->mqd_obj);
2176 ring->mqd_ptr = NULL;
464826d6 2177 }
e1d53aa8
AD		 2178 amdgpu_bo_unreserve(ring->mqd_obj);
2179 if (r)
2180 goto done;
464826d6
XY		 2181
2182 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2183 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2184
2185 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2186 if (unlikely(r != 0))
2187 goto done;
2188 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2189 if (!r) {
e322edc3 2190 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2191 amdgpu_bo_kunmap(ring->mqd_obj);
2192 ring->mqd_ptr = NULL;
464826d6 2193 }
e1d53aa8
AD		 2194 amdgpu_bo_unreserve(ring->mqd_obj);
2195 if (r)
2196 goto done;
464826d6
XY		 2197 }
2198
e1d53aa8
AD		 2199done:
2200 return r;
464826d6
XY		 2201}
2202
b1023571
KW		 2203static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2204{
2205 int r,i;
2206 struct amdgpu_ring *ring;
2207
2208 if (!(adev->flags & AMD_IS_APU))
2209 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2210
2211 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2212 /* legacy firmware loading */
2213 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2214 if (r)
2215 return r;
2216
2217 r = gfx_v9_0_cp_compute_load_microcode(adev);
2218 if (r)
2219 return r;
2220 }
2221
2222 r = gfx_v9_0_cp_gfx_resume(adev);
2223 if (r)
2224 return r;
2225
464826d6
XY		 2226 if (amdgpu_sriov_vf(adev))
2227 r = gfx_v9_0_kiq_resume(adev);
2228 else
2229 r = gfx_v9_0_cp_compute_resume(adev);
b1023571
KW		 2230 if (r)
2231 return r;
2232
2233 ring = &adev->gfx.gfx_ring[0];
2234 r = amdgpu_ring_test_ring(ring);
2235 if (r) {
2236 ring->ready = false;
2237 return r;
2238 }
2239 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2240 ring = &adev->gfx.compute_ring[i];
2241
2242 ring->ready = true;
2243 r = amdgpu_ring_test_ring(ring);
2244 if (r)
2245 ring->ready = false;
2246 }
2247
464826d6
XY		 2248 if (amdgpu_sriov_vf(adev)) {
2249 ring = &adev->gfx.kiq.ring;
2250 ring->ready = true;
2251 r = amdgpu_ring_test_ring(ring);
2252 if (r)
2253 ring->ready = false;
2254 }
2255
b1023571
KW		 2256 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2257
2258 return 0;
2259}
2260
2261static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2262{
2263 gfx_v9_0_cp_gfx_enable(adev, enable);
2264 gfx_v9_0_cp_compute_enable(adev, enable);
2265}
2266
2267static int gfx_v9_0_hw_init(void *handle)
2268{
2269 int r;
2270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2271
2272 gfx_v9_0_init_golden_registers(adev);
2273
2274 gfx_v9_0_gpu_init(adev);
2275
2276 r = gfx_v9_0_rlc_resume(adev);
2277 if (r)
2278 return r;
2279
2280 r = gfx_v9_0_cp_resume(adev);
2281 if (r)
2282 return r;
2283
2284 r = gfx_v9_0_ngg_en(adev);
2285 if (r)
2286 return r;
2287
2288 return r;
2289}
2290
2291static int gfx_v9_0_hw_fini(void *handle)
2292{
2293 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2294
2295 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2296 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
464826d6
XY		 2297 if (amdgpu_sriov_vf(adev)) {
2298 pr_debug("For SRIOV client, shouldn't do anything.\n");
2299 return 0;
2300 }
b1023571
KW		 2301 gfx_v9_0_cp_enable(adev, false);
2302 gfx_v9_0_rlc_stop(adev);
2303 gfx_v9_0_cp_compute_fini(adev);
2304
2305 return 0;
2306}
2307
2308static int gfx_v9_0_suspend(void *handle)
2309{
2310 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2311
2312 return gfx_v9_0_hw_fini(adev);
2313}
2314
2315static int gfx_v9_0_resume(void *handle)
2316{
2317 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2318
2319 return gfx_v9_0_hw_init(adev);
2320}
2321
2322static bool gfx_v9_0_is_idle(void *handle)
2323{
2324 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2325
5e78835a 2326 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 2327 GRBM_STATUS, GUI_ACTIVE))
2328 return false;
2329 else
2330 return true;
2331}
2332
2333static int gfx_v9_0_wait_for_idle(void *handle)
2334{
2335 unsigned i;
2336 u32 tmp;
2337 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2338
2339 for (i = 0; i < adev->usec_timeout; i++) {
2340 /* read MC_STATUS */
5e78835a 2341 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
b1023571
KW		 2342 GRBM_STATUS__GUI_ACTIVE_MASK;
2343
2344 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
2345 return 0;
2346 udelay(1);
2347 }
2348 return -ETIMEDOUT;
2349}
2350
b1023571
KW		 2351static int gfx_v9_0_soft_reset(void *handle)
2352{
2353 u32 grbm_soft_reset = 0;
2354 u32 tmp;
2355 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2356
2357 /* GRBM_STATUS */
5e78835a 2358 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 2359 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2360 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2361 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2362 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2363 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2364 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2365 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2366 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2367 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2368 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2369 }
2370
2371 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2372 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2373 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2374 }
2375
2376 /* GRBM_STATUS2 */
5e78835a 2377 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 2378 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2379 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2380 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2381
2382
75bac5c6 2383 if (grbm_soft_reset) {
b1023571
KW		 2384 /* stop the rlc */
2385 gfx_v9_0_rlc_stop(adev);
2386
2387 /* Disable GFX parsing/prefetching */
2388 gfx_v9_0_cp_gfx_enable(adev, false);
2389
2390 /* Disable MEC parsing/prefetching */
2391 gfx_v9_0_cp_compute_enable(adev, false);
2392
2393 if (grbm_soft_reset) {
5e78835a 2394 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 2395 tmp |= grbm_soft_reset;
2396 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 2397 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
2398 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 2399
2400 udelay(50);
2401
2402 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 2403 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
2404 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 2405 }
2406
2407 /* Wait a little for things to settle down */
2408 udelay(50);
b1023571
KW		 2409 }
2410 return 0;
2411}
2412
2413static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2414{
2415 uint64_t clock;
2416
2417 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 2418 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2419 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
2420 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 2421 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2422 return clock;
2423}
2424
2425static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
2426 uint32_t vmid,
2427 uint32_t gds_base, uint32_t gds_size,
2428 uint32_t gws_base, uint32_t gws_size,
2429 uint32_t oa_base, uint32_t oa_size)
2430{
2431 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
2432 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
2433
2434 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
2435 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
2436
2437 oa_base = oa_base >> AMDGPU_OA_SHIFT;
2438 oa_size = oa_size >> AMDGPU_OA_SHIFT;
2439
2440 /* GDS Base */
2441 gfx_v9_0_write_data_to_reg(ring, 0, false,
2442 amdgpu_gds_reg_offset[vmid].mem_base,
2443 gds_base);
2444
2445 /* GDS Size */
2446 gfx_v9_0_write_data_to_reg(ring, 0, false,
2447 amdgpu_gds_reg_offset[vmid].mem_size,
2448 gds_size);
2449
2450 /* GWS */
2451 gfx_v9_0_write_data_to_reg(ring, 0, false,
2452 amdgpu_gds_reg_offset[vmid].gws,
2453 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2454
2455 /* OA */
2456 gfx_v9_0_write_data_to_reg(ring, 0, false,
2457 amdgpu_gds_reg_offset[vmid].oa,
2458 (1 << (oa_size + oa_base)) - (1 << oa_base));
2459}
2460
2461static int gfx_v9_0_early_init(void *handle)
2462{
2463 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2464
2465 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
2466 adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS;
2467 gfx_v9_0_set_ring_funcs(adev);
2468 gfx_v9_0_set_irq_funcs(adev);
2469 gfx_v9_0_set_gds_init(adev);
2470 gfx_v9_0_set_rlc_funcs(adev);
2471
2472 return 0;
2473}
2474
2475static int gfx_v9_0_late_init(void *handle)
2476{
2477 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2478 int r;
2479
2480 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2481 if (r)
2482 return r;
2483
2484 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2485 if (r)
2486 return r;
2487
2488 return 0;
2489}
2490
2491static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
2492{
2493 uint32_t rlc_setting, data;
2494 unsigned i;
2495
2496 if (adev->gfx.rlc.in_safe_mode)
2497 return;
2498
2499 /* if RLC is not enabled, do nothing */
5e78835a 2500 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 2501 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2502 return;
2503
2504 if (adev->cg_flags &
2505 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
2506 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2507 data = RLC_SAFE_MODE__CMD_MASK;
2508 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 2509 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 2510
2511 /* wait for RLC_SAFE_MODE */
2512 for (i = 0; i < adev->usec_timeout; i++) {
2513 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
2514 break;
2515 udelay(1);
2516 }
2517 adev->gfx.rlc.in_safe_mode = true;
2518 }
2519}
2520
2521static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
2522{
2523 uint32_t rlc_setting, data;
2524
2525 if (!adev->gfx.rlc.in_safe_mode)
2526 return;
2527
2528 /* if RLC is not enabled, do nothing */
5e78835a 2529 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 2530 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2531 return;
2532
2533 if (adev->cg_flags &
2534 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
2535 /*
2536 * Try to exit safe mode only if it is already in safe
2537 * mode.
2538 */
2539 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 2540 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 2541 adev->gfx.rlc.in_safe_mode = false;
2542 }
2543}
2544
2545static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2546 bool enable)
2547{
2548 uint32_t data, def;
2549
2550 /* It is disabled by HW by default */
2551 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2552 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 2553 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 2554 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2555 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2556 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2557 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2558
2559 /* only for Vega10 & Raven1 */
2560 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
2561
2562 if (def != data)
5e78835a 2563 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 2564
2565 /* MGLS is a global flag to control all MGLS in GFX */
2566 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2567 /* 2 - RLC memory Light sleep */
2568 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 2569 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 2570 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2571 if (def != data)
5e78835a 2572 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 2573 }
2574 /* 3 - CP memory Light sleep */
2575 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 2576 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 2577 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2578 if (def != data)
5e78835a 2579 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 2580 }
2581 }
2582 } else {
2583 /* 1 - MGCG_OVERRIDE */
5e78835a 2584 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 2585 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2586 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2587 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2588 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2589 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2590 if (def != data)
5e78835a 2591 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 2592
2593 /* 2 - disable MGLS in RLC */
5e78835a 2594 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 2595 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2596 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 2597 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 2598 }
2599
2600 /* 3 - disable MGLS in CP */
5e78835a 2601 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 2602 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2603 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 2604 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 2605 }
2606 }
2607}
2608
2609static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
2610 bool enable)
2611{
2612 uint32_t data, def;
2613
2614 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2615
2616 /* Enable 3D CGCG/CGLS */
2617 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2618 /* write cmd to clear cgcg/cgls ov */
5e78835a 2619 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 2620 /* unset CGCG override */
2621 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
2622 /* update CGCG and CGLS override bits */
2623 if (def != data)
5e78835a 2624 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 2625 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 2626 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 2627 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2628 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
2629 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
2630 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2631 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
2632 if (def != data)
5e78835a 2633 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 2634
2635 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 2636 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 2637 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2638 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2639 if (def != data)
5e78835a 2640 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 2641 } else {
2642 /* Disable CGCG/CGLS */
5e78835a 2643 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 2644 /* disable cgcg, cgls should be disabled */
2645 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
2646 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
2647 /* disable cgcg and cgls in FSM */
2648 if (def != data)
5e78835a 2649 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 2650 }
2651
2652 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2653}
2654
2655static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2656 bool enable)
2657{
2658 uint32_t def, data;
2659
2660 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2661
2662 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 2663 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 2664 /* unset CGCG override */
2665 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2666 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2667 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2668 else
2669 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2670 /* update CGCG and CGLS override bits */
2671 if (def != data)
5e78835a 2672 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 2673
2674 /* enable cgcg FSM(0x0020003F) */
5e78835a 2675 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 2676 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2677 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2678 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2679 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2680 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2681 if (def != data)
5e78835a 2682 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 2683
2684 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 2685 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 2686 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2687 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2688 if (def != data)
5e78835a 2689 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 2690 } else {
5e78835a 2691 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 2692 /* reset CGCG/CGLS bits */
2693 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2694 /* disable cgcg and cgls in FSM */
2695 if (def != data)
5e78835a 2696 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 2697 }
2698
2699 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2700}
2701
2702static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
2703 bool enable)
2704{
2705 if (enable) {
2706 /* CGCG/CGLS should be enabled after MGCG/MGLS
2707 * === MGCG + MGLS ===
2708 */
2709 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2710 /* === CGCG /CGLS for GFX 3D Only === */
2711 gfx_v9_0_update_3d_clock_gating(adev, enable);
2712 /* === CGCG + CGLS === */
2713 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2714 } else {
2715 /* CGCG/CGLS should be disabled before MGCG/MGLS
2716 * === CGCG + CGLS ===
2717 */
2718 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2719 /* === CGCG /CGLS for GFX 3D Only === */
2720 gfx_v9_0_update_3d_clock_gating(adev, enable);
2721 /* === MGCG + MGLS === */
2722 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2723 }
2724 return 0;
2725}
2726
2727static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
2728 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
2729 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
2730};
2731
2732static int gfx_v9_0_set_powergating_state(void *handle,
2733 enum amd_powergating_state state)
2734{
2735 return 0;
2736}
2737
2738static int gfx_v9_0_set_clockgating_state(void *handle,
2739 enum amd_clockgating_state state)
2740{
2741 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2742
fb82afab
XY		 2743 if (amdgpu_sriov_vf(adev))
2744 return 0;
2745
b1023571
KW		 2746 switch (adev->asic_type) {
2747 case CHIP_VEGA10:
2748 gfx_v9_0_update_gfx_clock_gating(adev,
2749 state == AMD_CG_STATE_GATE ? true : false);
2750 break;
2751 default:
2752 break;
2753 }
2754 return 0;
2755}
2756
12ad27fa
HR		 2757static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
2758{
2759 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2760 int data;
2761
2762 if (amdgpu_sriov_vf(adev))
2763 *flags = 0;
2764
2765 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 2766 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 2767 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
2768 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
2769
2770 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 2771 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 2772 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
2773 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
2774
2775 /* AMD_CG_SUPPORT_GFX_CGLS */
2776 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
2777 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
2778
2779 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 2780 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 2781 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
2782 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
2783
2784 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 2785 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 2786 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
2787 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
2788
2789 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 2790 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 2791 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
2792 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
2793
2794 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
2795 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
2796 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
2797}
2798
b1023571
KW		 2799static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2800{
2801 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
2802}
2803
2804static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2805{
2806 struct amdgpu_device *adev = ring->adev;
2807 u64 wptr;
2808
2809 /* XXX check if swapping is necessary on BE */
2810 if (ring->use_doorbell) {
2811 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
2812 } else {
5e78835a
TSD		 2813 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
2814 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 2815 }
2816
2817 return wptr;
2818}
2819
2820static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2821{
2822 struct amdgpu_device *adev = ring->adev;
2823
2824 if (ring->use_doorbell) {
2825 /* XXX check if swapping is necessary on BE */
2826 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2827 WDOORBELL64(ring->doorbell_index, ring->wptr);
2828 } else {
5e78835a
TSD		 2829 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2830 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2831 }
2832}
2833
2834static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2835{
2836 u32 ref_and_mask, reg_mem_engine;
2837 struct nbio_hdp_flush_reg *nbio_hf_reg;
2838
2839 if (ring->adev->asic_type == CHIP_VEGA10)
2840 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
2841
2842 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2843 switch (ring->me) {
2844 case 1:
2845 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2846 break;
2847 case 2:
2848 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2849 break;
2850 default:
2851 return;
2852 }
2853 reg_mem_engine = 0;
2854 } else {
2855 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2856 reg_mem_engine = 1; /* pfp */
2857 }
2858
2859 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2860 nbio_hf_reg->hdp_flush_req_offset,
2861 nbio_hf_reg->hdp_flush_done_offset,
2862 ref_and_mask, ref_and_mask, 0x20);
2863}
2864
2865static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2866{
2867 gfx_v9_0_write_data_to_reg(ring, 0, true,
2868 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
2869}
2870
2871static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2872 struct amdgpu_ib *ib,
2873 unsigned vm_id, bool ctx_switch)
2874{
2875 u32 header, control = 0;
2876
2877 if (ib->flags & AMDGPU_IB_FLAG_CE)
2878 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2879 else
2880 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2881
2882 control |= ib->length_dw | (vm_id << 24);
2883
9ccd52eb
ML		 2884 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
2885 control |= INDIRECT_BUFFER_PRE_ENB(1);
2886
b1023571
KW		 2887 amdgpu_ring_write(ring, header);
2888 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2889 amdgpu_ring_write(ring,
2890#ifdef __BIG_ENDIAN
2891 (2 << 0) |
2892#endif
2893 lower_32_bits(ib->gpu_addr));
2894 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2895 amdgpu_ring_write(ring, control);
2896}
2897
2898#define INDIRECT_BUFFER_VALID (1 << 23)
2899
2900static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2901 struct amdgpu_ib *ib,
2902 unsigned vm_id, bool ctx_switch)
2903{
2904 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2905
2906 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2907 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2908 amdgpu_ring_write(ring,
2909#ifdef __BIG_ENDIAN
2910 (2 << 0) |
2911#endif
2912 lower_32_bits(ib->gpu_addr));
2913 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2914 amdgpu_ring_write(ring, control);
2915}
2916
2917static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2918 u64 seq, unsigned flags)
2919{
2920 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2921 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2922
2923 /* RELEASE_MEM - flush caches, send int */
2924 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2925 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2926 EOP_TC_ACTION_EN |
2927 EOP_TC_WB_ACTION_EN |
2928 EOP_TC_MD_ACTION_EN |
2929 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2930 EVENT_INDEX(5)));
2931 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2932
2933 /*
2934 * the address should be Qword aligned if 64bit write, Dword
2935 * aligned if only send 32bit data low (discard data high)
2936 */
2937 if (write64bit)
2938 BUG_ON(addr & 0x7);
2939 else
2940 BUG_ON(addr & 0x3);
2941 amdgpu_ring_write(ring, lower_32_bits(addr));
2942 amdgpu_ring_write(ring, upper_32_bits(addr));
2943 amdgpu_ring_write(ring, lower_32_bits(seq));
2944 amdgpu_ring_write(ring, upper_32_bits(seq));
2945 amdgpu_ring_write(ring, 0);
2946}
2947
2948static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2949{
2950 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2951 uint32_t seq = ring->fence_drv.sync_seq;
2952 uint64_t addr = ring->fence_drv.gpu_addr;
2953
2954 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
2955 lower_32_bits(addr), upper_32_bits(addr),
2956 seq, 0xffffffff, 4);
2957}
2958
2959static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2960 unsigned vm_id, uint64_t pd_addr)
2961{
2e819849 2962 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
b1023571 2963 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 2964 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 2965 unsigned eng = ring->vm_inv_eng;
b1023571
KW		 2966
2967 pd_addr = pd_addr | 0x1; /* valid bit */
2968 /* now only use physical base address of PDE and valid */
2969 BUG_ON(pd_addr & 0xFFFF00000000003EULL);
2970
2e819849
CK		 2971 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2972 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
2973 lower_32_bits(pd_addr));
b1023571 2974
2e819849
CK		 2975 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2976 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
2977 upper_32_bits(pd_addr));
b1023571 2978
2e819849
CK		 2979 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2980 hub->vm_inv_eng0_req + eng, req);
b1023571 2981
2e819849
CK		 2982 /* wait for the invalidate to complete */
2983 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
2984 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
b1023571
KW		 2985
2986 /* compute doesn't have PFP */
2987 if (usepfp) {
2988 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2989 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2990 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 2991 }
2992}
2993
2994static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2995{
2996 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2997}
2998
2999static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3000{
3001 u64 wptr;
3002
3003 /* XXX check if swapping is necessary on BE */
3004 if (ring->use_doorbell)
3005 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3006 else
3007 BUG();
3008 return wptr;
3009}
3010
3011static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3012{
3013 struct amdgpu_device *adev = ring->adev;
3014
3015 /* XXX check if swapping is necessary on BE */
3016 if (ring->use_doorbell) {
3017 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3018 WDOORBELL64(ring->doorbell_index, ring->wptr);
3019 } else{
3020 BUG(); /* only DOORBELL method supported on gfx9 now */
3021 }
3022}
3023
aa6faa44
XY		 3024static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3025 u64 seq, unsigned int flags)
3026{
3027 /* we only allocate 32bit for each seq wb address */
3028 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3029
3030 /* write fence seq to the "addr" */
3031 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3032 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3033 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3034 amdgpu_ring_write(ring, lower_32_bits(addr));
3035 amdgpu_ring_write(ring, upper_32_bits(addr));
3036 amdgpu_ring_write(ring, lower_32_bits(seq));
3037
3038 if (flags & AMDGPU_FENCE_FLAG_INT) {
3039 /* set register to trigger INT */
3040 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3041 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3042 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3043 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3044 amdgpu_ring_write(ring, 0);
3045 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3046 }
3047}
3048
b1023571
KW		 3049static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3050{
3051 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3052 amdgpu_ring_write(ring, 0);
3053}
3054
cca02cd3
XY		 3055static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3056{
3057 static struct v9_ce_ib_state ce_payload = {0};
3058 uint64_t csa_addr;
3059 int cnt;
3060
3061 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3062 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3063
3064 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3065 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3066 WRITE_DATA_DST_SEL(8) |
3067 WR_CONFIRM) |
3068 WRITE_DATA_CACHE_POLICY(0));
3069 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3070 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3071 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3072}
3073
3074static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3075{
3076 static struct v9_de_ib_state de_payload = {0};
3077 uint64_t csa_addr, gds_addr;
3078 int cnt;
3079
3080 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3081 gds_addr = csa_addr + 4096;
3082 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3083 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3084
3085 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3086 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3087 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3088 WRITE_DATA_DST_SEL(8) |
3089 WR_CONFIRM) |
3090 WRITE_DATA_CACHE_POLICY(0));
3091 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3092 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3093 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3094}
3095
b1023571
KW		 3096static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3097{
3098 uint32_t dw2 = 0;
3099
cca02cd3
XY		 3100 if (amdgpu_sriov_vf(ring->adev))
3101 gfx_v9_0_ring_emit_ce_meta(ring);
3102
b1023571
KW		 3103 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3104 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3105 /* set load_global_config & load_global_uconfig */
3106 dw2 |= 0x8001;
3107 /* set load_cs_sh_regs */
3108 dw2 |= 0x01000000;
3109 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3110 dw2 |= 0x10002;
3111
3112 /* set load_ce_ram if preamble presented */
3113 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3114 dw2 |= 0x10000000;
3115 } else {
3116 /* still load_ce_ram if this is the first time preamble presented
3117 * although there is no context switch happens.
3118 */
3119 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3120 dw2 |= 0x10000000;
3121 }
3122
3123 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3124 amdgpu_ring_write(ring, dw2);
3125 amdgpu_ring_write(ring, 0);
cca02cd3
XY		 3126
3127 if (amdgpu_sriov_vf(ring->adev))
3128 gfx_v9_0_ring_emit_de_meta(ring);
b1023571
KW		 3129}
3130
9a5e02b5
ML		 3131static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3132{
3133 unsigned ret;
3134 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3135 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3136 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3137 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3138 ret = ring->wptr & ring->buf_mask;
3139 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3140 return ret;
3141}
3142
3143static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3144{
3145 unsigned cur;
3146 BUG_ON(offset > ring->buf_mask);
3147 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3148
3149 cur = (ring->wptr & ring->buf_mask) - 1;
3150 if (likely(cur > offset))
3151 ring->ring[offset] = cur - offset;
3152 else
3153 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3154}
3155
aa6faa44
XY		 3156static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3157{
3158 struct amdgpu_device *adev = ring->adev;
3159
3160 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3161 amdgpu_ring_write(ring, 0 | /* src: register*/
3162 (5 << 8) | /* dst: memory */
3163 (1 << 20)); /* write confirm */
3164 amdgpu_ring_write(ring, reg);
3165 amdgpu_ring_write(ring, 0);
3166 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3167 adev->virt.reg_val_offs * 4));
3168 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3169 adev->virt.reg_val_offs * 4));
3170}
3171
3172static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3173 uint32_t val)
3174{
3175 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3176 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3177 amdgpu_ring_write(ring, reg);
3178 amdgpu_ring_write(ring, 0);
3179 amdgpu_ring_write(ring, val);
3180}
3181
b1023571
KW		 3182static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3183 enum amdgpu_interrupt_state state)
3184{
b1023571
KW		 3185 switch (state) {
3186 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3187 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 3188 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3189 TIME_STAMP_INT_ENABLE,
3190 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3191 break;
3192 default:
3193 break;
3194 }
3195}
3196
3197static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3198 int me, int pipe,
3199 enum amdgpu_interrupt_state state)
3200{
3201 u32 mec_int_cntl, mec_int_cntl_reg;
3202
3203 /*
3204 * amdgpu controls only pipe 0 of MEC1. That's why this function only
3205 * handles the setting of interrupts for this specific pipe. All other
3206 * pipes' interrupts are set by amdkfd.
3207 */
3208
3209 if (me == 1) {
3210 switch (pipe) {
3211 case 0:
3212 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3213 break;
3214 default:
3215 DRM_DEBUG("invalid pipe %d\n", pipe);
3216 return;
3217 }
3218 } else {
3219 DRM_DEBUG("invalid me %d\n", me);
3220 return;
3221 }
3222
3223 switch (state) {
3224 case AMDGPU_IRQ_STATE_DISABLE:
3225 mec_int_cntl = RREG32(mec_int_cntl_reg);
3226 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3227 TIME_STAMP_INT_ENABLE, 0);
3228 WREG32(mec_int_cntl_reg, mec_int_cntl);
3229 break;
3230 case AMDGPU_IRQ_STATE_ENABLE:
3231 mec_int_cntl = RREG32(mec_int_cntl_reg);
3232 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3233 TIME_STAMP_INT_ENABLE, 1);
3234 WREG32(mec_int_cntl_reg, mec_int_cntl);
3235 break;
3236 default:
3237 break;
3238 }
3239}
3240
3241static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3242 struct amdgpu_irq_src *source,
3243 unsigned type,
3244 enum amdgpu_interrupt_state state)
3245{
b1023571
KW		 3246 switch (state) {
3247 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3248 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 3249 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3250 PRIV_REG_INT_ENABLE,
3251 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3252 break;
3253 default:
3254 break;
3255 }
3256
3257 return 0;
3258}
3259
3260static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3261 struct amdgpu_irq_src *source,
3262 unsigned type,
3263 enum amdgpu_interrupt_state state)
3264{
b1023571
KW		 3265 switch (state) {
3266 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3267 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 3268 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3269 PRIV_INSTR_INT_ENABLE,
3270 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3271 default:
3272 break;
3273 }
3274
3275 return 0;
3276}
3277
3278static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3279 struct amdgpu_irq_src *src,
3280 unsigned type,
3281 enum amdgpu_interrupt_state state)
3282{
3283 switch (type) {
3284 case AMDGPU_CP_IRQ_GFX_EOP:
3285 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
3286 break;
3287 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3288 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
3289 break;
3290 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3291 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
3292 break;
3293 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
3294 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
3295 break;
3296 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
3297 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
3298 break;
3299 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
3300 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
3301 break;
3302 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
3303 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
3304 break;
3305 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
3306 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
3307 break;
3308 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
3309 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
3310 break;
3311 default:
3312 break;
3313 }
3314 return 0;
3315}
3316
3317static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
3318 struct amdgpu_irq_src *source,
3319 struct amdgpu_iv_entry *entry)
3320{
3321 int i;
3322 u8 me_id, pipe_id, queue_id;
3323 struct amdgpu_ring *ring;
3324
3325 DRM_DEBUG("IH: CP EOP\n");
3326 me_id = (entry->ring_id & 0x0c) >> 2;
3327 pipe_id = (entry->ring_id & 0x03) >> 0;
3328 queue_id = (entry->ring_id & 0x70) >> 4;
3329
3330 switch (me_id) {
3331 case 0:
3332 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3333 break;
3334 case 1:
3335 case 2:
3336 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3337 ring = &adev->gfx.compute_ring[i];
3338 /* Per-queue interrupt is supported for MEC starting from VI.
3339 * The interrupt can only be enabled/disabled per pipe instead of per queue.
3340 */
3341 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
3342 amdgpu_fence_process(ring);
3343 }
3344 break;
3345 }
3346 return 0;
3347}
3348
3349static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
3350 struct amdgpu_irq_src *source,
3351 struct amdgpu_iv_entry *entry)
3352{
3353 DRM_ERROR("Illegal register access in command stream\n");
3354 schedule_work(&adev->reset_work);
3355 return 0;
3356}
3357
3358static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
3359 struct amdgpu_irq_src *source,
3360 struct amdgpu_iv_entry *entry)
3361{
3362 DRM_ERROR("Illegal instruction in command stream\n");
3363 schedule_work(&adev->reset_work);
3364 return 0;
3365}
3366
97031e25
XY		 3367static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
3368 struct amdgpu_irq_src *src,
3369 unsigned int type,
3370 enum amdgpu_interrupt_state state)
3371{
3372 uint32_t tmp, target;
1c4ecf48 3373 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 3374
3375 if (ring->me == 1)
3376 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3377 else
3378 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
3379 target += ring->pipe;
3380
3381 switch (type) {
3382 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
3383 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 3384 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 3385 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
3386 GENERIC2_INT_ENABLE, 0);
5e78835a 3387 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 3388
3389 tmp = RREG32(target);
3390 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
3391 GENERIC2_INT_ENABLE, 0);
3392 WREG32(target, tmp);
3393 } else {
5e78835a 3394 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 3395 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
3396 GENERIC2_INT_ENABLE, 1);
5e78835a 3397 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 3398
3399 tmp = RREG32(target);
3400 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
3401 GENERIC2_INT_ENABLE, 1);
3402 WREG32(target, tmp);
3403 }
3404 break;
3405 default:
3406 BUG(); /* kiq only support GENERIC2_INT now */
3407 break;
3408 }
3409 return 0;
3410}
3411
3412static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
3413 struct amdgpu_irq_src *source,
3414 struct amdgpu_iv_entry *entry)
3415{
3416 u8 me_id, pipe_id, queue_id;
1c4ecf48 3417 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 3418
3419 me_id = (entry->ring_id & 0x0c) >> 2;
3420 pipe_id = (entry->ring_id & 0x03) >> 0;
3421 queue_id = (entry->ring_id & 0x70) >> 4;
3422 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
3423 me_id, pipe_id, queue_id);
3424
3425 amdgpu_fence_process(ring);
3426 return 0;
3427}
3428
b1023571
KW		 3429const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
3430 .name = "gfx_v9_0",
3431 .early_init = gfx_v9_0_early_init,
3432 .late_init = gfx_v9_0_late_init,
3433 .sw_init = gfx_v9_0_sw_init,
3434 .sw_fini = gfx_v9_0_sw_fini,
3435 .hw_init = gfx_v9_0_hw_init,
3436 .hw_fini = gfx_v9_0_hw_fini,
3437 .suspend = gfx_v9_0_suspend,
3438 .resume = gfx_v9_0_resume,
3439 .is_idle = gfx_v9_0_is_idle,
3440 .wait_for_idle = gfx_v9_0_wait_for_idle,
3441 .soft_reset = gfx_v9_0_soft_reset,
3442 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
3443 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 3444 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 3445};
3446
3447static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
3448 .type = AMDGPU_RING_TYPE_GFX,
3449 .align_mask = 0xff,
3450 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3451 .support_64bit_ptrs = true,
0eeb68b3 3452 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 3453 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
3454 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
3455 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 3456 .emit_frame_size = /* totally 242 maximum if 16 IBs */
3457 5 + /* COND_EXEC */
3458 7 + /* PIPELINE_SYNC */
2e819849 3459 24 + /* VM_FLUSH */
e9d672b2
ML		 3460 8 + /* FENCE for VM_FLUSH */
3461 20 + /* GDS switch */
3462 4 + /* double SWITCH_BUFFER,
3463 the first COND_EXEC jump to the place just
3464 prior to this double SWITCH_BUFFER */
3465 5 + /* COND_EXEC */
3466 7 + /* HDP_flush */
3467 4 + /* VGT_flush */
3468 14 + /* CE_META */
3469 31 + /* DE_META */
3470 3 + /* CNTX_CTRL */
3471 5 + /* HDP_INVL */
3472 8 + 8 + /* FENCE x2 */
3473 2, /* SWITCH_BUFFER */
b1023571
KW		 3474 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
3475 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
3476 .emit_fence = gfx_v9_0_ring_emit_fence,
3477 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3478 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3479 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3480 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3481 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3482 .test_ring = gfx_v9_0_ring_test_ring,
3483 .test_ib = gfx_v9_0_ring_test_ib,
3484 .insert_nop = amdgpu_ring_insert_nop,
3485 .pad_ib = amdgpu_ring_generic_pad_ib,
3486 .emit_switch_buffer = gfx_v9_ring_emit_sb,
3487 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 3488 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
3489 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
b1023571
KW		 3490};
3491
3492static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
3493 .type = AMDGPU_RING_TYPE_COMPUTE,
3494 .align_mask = 0xff,
3495 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3496 .support_64bit_ptrs = true,
0eeb68b3 3497 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 3498 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3499 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3500 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3501 .emit_frame_size =
3502 20 + /* gfx_v9_0_ring_emit_gds_switch */
3503 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3504 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3505 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 3506 24 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 3507 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
3508 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3509 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3510 .emit_fence = gfx_v9_0_ring_emit_fence,
3511 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3512 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3513 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3514 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3515 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3516 .test_ring = gfx_v9_0_ring_test_ring,
3517 .test_ib = gfx_v9_0_ring_test_ib,
3518 .insert_nop = amdgpu_ring_insert_nop,
3519 .pad_ib = amdgpu_ring_generic_pad_ib,
3520};
3521
aa6faa44
XY		 3522static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
3523 .type = AMDGPU_RING_TYPE_KIQ,
3524 .align_mask = 0xff,
3525 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3526 .support_64bit_ptrs = true,
0eeb68b3 3527 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 3528 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3529 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3530 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3531 .emit_frame_size =
3532 20 + /* gfx_v9_0_ring_emit_gds_switch */
3533 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3534 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3535 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 3536 24 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 3537 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
3538 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3539 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3540 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 3541 .test_ring = gfx_v9_0_ring_test_ring,
3542 .test_ib = gfx_v9_0_ring_test_ib,
3543 .insert_nop = amdgpu_ring_insert_nop,
3544 .pad_ib = amdgpu_ring_generic_pad_ib,
3545 .emit_rreg = gfx_v9_0_ring_emit_rreg,
3546 .emit_wreg = gfx_v9_0_ring_emit_wreg,
3547};
b1023571
KW		 3548
3549static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
3550{
3551 int i;
3552
aa6faa44
XY		 3553 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
3554
b1023571
KW		 3555 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3556 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
3557
3558 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3559 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
3560}
3561
97031e25
XY		 3562static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
3563 .set = gfx_v9_0_kiq_set_interrupt_state,
3564 .process = gfx_v9_0_kiq_irq,
3565};
3566
b1023571
KW		 3567static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
3568 .set = gfx_v9_0_set_eop_interrupt_state,
3569 .process = gfx_v9_0_eop_irq,
3570};
3571
3572static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
3573 .set = gfx_v9_0_set_priv_reg_fault_state,
3574 .process = gfx_v9_0_priv_reg_irq,
3575};
3576
3577static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
3578 .set = gfx_v9_0_set_priv_inst_fault_state,
3579 .process = gfx_v9_0_priv_inst_irq,
3580};
3581
3582static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
3583{
3584 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3585 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
3586
3587 adev->gfx.priv_reg_irq.num_types = 1;
3588 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
3589
3590 adev->gfx.priv_inst_irq.num_types = 1;
3591 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 3592
3593 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
3594 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 3595}
3596
3597static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
3598{
3599 switch (adev->asic_type) {
3600 case CHIP_VEGA10:
3601 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
3602 break;
3603 default:
3604 break;
3605 }
3606}
3607
3608static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
3609{
3610 /* init asci gds info */
5e78835a 3611 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 3612 adev->gds.gws.total_size = 64;
3613 adev->gds.oa.total_size = 16;
3614
3615 if (adev->gds.mem.total_size == 64 * 1024) {
3616 adev->gds.mem.gfx_partition_size = 4096;
3617 adev->gds.mem.cs_partition_size = 4096;
3618
3619 adev->gds.gws.gfx_partition_size = 4;
3620 adev->gds.gws.cs_partition_size = 4;
3621
3622 adev->gds.oa.gfx_partition_size = 4;
3623 adev->gds.oa.cs_partition_size = 1;
3624 } else {
3625 adev->gds.mem.gfx_partition_size = 1024;
3626 adev->gds.mem.cs_partition_size = 1024;
3627
3628 adev->gds.gws.gfx_partition_size = 16;
3629 adev->gds.gws.cs_partition_size = 16;
3630
3631 adev->gds.oa.gfx_partition_size = 4;
3632 adev->gds.oa.cs_partition_size = 4;
3633 }
3634}
3635
3636static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3637{
3638 u32 data, mask;
3639
5e78835a
TSD		 3640 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
3641 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 3642
3643 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3644 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3645
3646 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3647
3648 return (~data) & mask;
3649}
3650
3651static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
3652 struct amdgpu_cu_info *cu_info)
3653{
3654 int i, j, k, counter, active_cu_number = 0;
3655 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3656
3657 if (!adev || !cu_info)
3658 return -EINVAL;
3659
3660 memset(cu_info, 0, sizeof(*cu_info));
3661
3662 mutex_lock(&adev->grbm_idx_mutex);
3663 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3664 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3665 mask = 1;
3666 ao_bitmap = 0;
3667 counter = 0;
3668 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
3669 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
3670 cu_info->bitmap[i][j] = bitmap;
3671
3672 for (k = 0; k < 16; k ++) {
3673 if (bitmap & mask) {
3674 if (counter < 2)
3675 ao_bitmap |= mask;
3676 counter ++;
3677 }
3678 mask <<= 1;
3679 }
3680 active_cu_number += counter;
3681 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3682 }
3683 }
3684 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3685 mutex_unlock(&adev->grbm_idx_mutex);
3686
3687 cu_info->number = active_cu_number;
3688 cu_info->ao_cu_mask = ao_cu_mask;
3689
3690 return 0;
3691}
3692
3693static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
3694{
3695 int r, j;
3696 u32 tmp;
3697 bool use_doorbell = true;
3698 u64 hqd_gpu_addr;
3699 u64 mqd_gpu_addr;
3700 u64 eop_gpu_addr;
3701 u64 wb_gpu_addr;
3702 u32 *buf;
3703 struct v9_mqd *mqd;
3704 struct amdgpu_device *adev;
3705
3706 adev = ring->adev;
3707 if (ring->mqd_obj == NULL) {
3708 r = amdgpu_bo_create(adev,
3709 sizeof(struct v9_mqd),
3710 PAGE_SIZE,true,
3711 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3712 NULL, &ring->mqd_obj);
3713 if (r) {
3714 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3715 return r;
3716 }
3717 }
3718
3719 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3720 if (unlikely(r != 0)) {
3721 gfx_v9_0_cp_compute_fini(adev);
3722 return r;
3723 }
3724
3725 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3726 &mqd_gpu_addr);
3727 if (r) {
3728 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3729 gfx_v9_0_cp_compute_fini(adev);
3730 return r;
3731 }
3732 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3733 if (r) {
3734 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3735 gfx_v9_0_cp_compute_fini(adev);
3736 return r;
3737 }
3738
3739 /* init the mqd struct */
3740 memset(buf, 0, sizeof(struct v9_mqd));
3741
3742 mqd = (struct v9_mqd *)buf;
3743 mqd->header = 0xC0310800;
3744 mqd->compute_pipelinestat_enable = 0x00000001;
3745 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3746 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3747 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3748 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3749 mqd->compute_misc_reserved = 0x00000003;
3750 mutex_lock(&adev->srbm_mutex);
3751 soc15_grbm_select(adev, ring->me,
3752 ring->pipe,
3753 ring->queue, 0);
3754 /* disable wptr polling */
efe53d8a 3755 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
b1023571
KW		 3756
3757 /* write the EOP addr */
3758 BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
3759 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
3760 eop_gpu_addr >>= 8;
3761
5e78835a
TSD		 3762 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, lower_32_bits(eop_gpu_addr));
3763 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
b1023571
KW		 3764 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
3765 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
3766
3767 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 3768 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
b1023571
KW		 3769 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3770 (order_base_2(MEC_HPD_SIZE / 4) - 1));
5e78835a 3771 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, tmp);
b1023571
KW		 3772
3773 /* enable doorbell? */
5e78835a 3774 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
b1023571
KW		 3775 if (use_doorbell)
3776 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3777 else
3778 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3779
5e78835a 3780 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
b1023571
KW		 3781 mqd->cp_hqd_pq_doorbell_control = tmp;
3782
3783 /* disable the queue if it's active */
3784 ring->wptr = 0;
3785 mqd->cp_hqd_dequeue_request = 0;
3786 mqd->cp_hqd_pq_rptr = 0;
3787 mqd->cp_hqd_pq_wptr_lo = 0;
3788 mqd->cp_hqd_pq_wptr_hi = 0;
5e78835a
TSD		 3789 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3790 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
b1023571 3791 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 3792 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
b1023571
KW		 3793 break;
3794 udelay(1);
3795 }
5e78835a
TSD		 3796 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3797 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3798 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
3799 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
b1023571
KW		 3800 }
3801
3802 /* set the pointer to the MQD */
3803 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3804 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
5e78835a
TSD		 3805 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3806 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
b1023571
KW		 3807
3808 /* set MQD vmid to 0 */
5e78835a 3809 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
b1023571 3810 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
5e78835a 3811 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, tmp);
b1023571
KW		 3812 mqd->cp_mqd_control = tmp;
3813
3814 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3815 hqd_gpu_addr = ring->gpu_addr >> 8;
3816 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3817 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
5e78835a
TSD		 3818 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3819 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
b1023571
KW		 3820
3821 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 3822 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
b1023571
KW		 3823 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3824 (order_base_2(ring->ring_size / 4) - 1));
3825 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3826 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3827#ifdef __BIG_ENDIAN
3828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3829#endif
3830 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3831 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3832 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3833 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
5e78835a 3834 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, tmp);
b1023571
KW		 3835 mqd->cp_hqd_pq_control = tmp;
3836
3837 /* set the wb address wether it's enabled or not */
3838 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3839 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3840 mqd->cp_hqd_pq_rptr_report_addr_hi =
3841 upper_32_bits(wb_gpu_addr) & 0xffff;
5e78835a 3842 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
b1023571 3843 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 3844 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
b1023571
KW		 3845 mqd->cp_hqd_pq_rptr_report_addr_hi);
3846
3847 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3848 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3849 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3850 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
5e78835a 3851 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
b1023571 3852 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 3853 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
b1023571
KW		 3854 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3855
3856 /* enable the doorbell if requested */
3857 if (use_doorbell) {
5e78835a 3858 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
b1023571 3859 (AMDGPU_DOORBELL64_KIQ * 2) << 2);
5e78835a 3860 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
b1023571 3861 (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
5e78835a 3862 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
b1023571
KW		 3863 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3864 DOORBELL_OFFSET, ring->doorbell_index);
3865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3866 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3867 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3868 mqd->cp_hqd_pq_doorbell_control = tmp;
3869
3870 } else {
3871 mqd->cp_hqd_pq_doorbell_control = 0;
3872 }
5e78835a 3873 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
b1023571
KW		 3874 mqd->cp_hqd_pq_doorbell_control);
3875
3876 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a
TSD		 3877 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
3878 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
b1023571
KW		 3879
3880 /* set the vmid for the queue */
3881 mqd->cp_hqd_vmid = 0;
5e78835a 3882 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
b1023571 3883
5e78835a 3884 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
b1023571 3885 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
5e78835a 3886 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, tmp);
b1023571
KW		 3887 mqd->cp_hqd_persistent_state = tmp;
3888
3889 /* activate the queue */
3890 mqd->cp_hqd_active = 1;
5e78835a 3891 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
b1023571
KW		 3892
3893 soc15_grbm_select(adev, 0, 0, 0, 0);
3894 mutex_unlock(&adev->srbm_mutex);
3895
3896 amdgpu_bo_kunmap(ring->mqd_obj);
3897 amdgpu_bo_unreserve(ring->mqd_obj);
3898
efe53d8a
TSD		 3899 if (use_doorbell)
3900 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
b1023571
KW		 3901
3902 return 0;
3903}
3904
3905const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
3906{
3907 .type = AMD_IP_BLOCK_TYPE_GFX,
3908 .major = 9,
3909 .minor = 0,
3910 .rev = 0,
3911 .funcs = &gfx_v9_0_ip_funcs,
3912};
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