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drm/amdgpu:hdp flush should be put it initialized
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
248a1d6f 24#include <drm/drmP.h>
b1023571
KW		 25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
268cb4c7 41#define GFX9_MEC_HPD_SIZE 2048
6bce4667
HZ		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
b1023571 45
91d3130a
HZ		 46#define mmPWR_MISC_CNTL_STATUS 0x0183
47#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
b1023571
KW		 52
53MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
060d124b
CZ		 60MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62MODULE_FIRMWARE("amdgpu/raven_me.bin");
63MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
b1023571
KW		 67static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
68{
35c32f20
TSD		 69 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
73 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
77 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
81 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
85 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
86 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
87 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
88 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
89 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
90 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
91 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
92 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
93 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
94 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
95 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
96 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
97 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
98 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
99 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
100 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
101 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
102 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
103 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
104 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
105 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
106 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
107 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
108 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
109 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
110 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
111 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
112 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
113 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
114 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
115 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
116 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
117 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
118 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
119 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
120 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
121 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
122 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
123 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
124 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
125 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
126 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
127 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
128 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
129 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
130 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
131 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
132 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
b1023571
KW		 133};
134
135static const u32 golden_settings_gc_9_0[] =
136{
f8af9332
KW		 137 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
138 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
139 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
140 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
141 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
142 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
b1023571
KW		 143 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
144 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
145 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
f8af9332
KW		 146 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
147 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
148 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
149 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
150 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
ba219b3c 151 SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
f8af9332 152 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
ba219b3c 153 SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
b1023571
KW		 154 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
155 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
156 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
f8af9332
KW		 157 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
158 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
159 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
b1023571
KW		 160};
161
162static const u32 golden_settings_gc_9_0_vg10[] =
163{
164 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
165 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
166 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
167 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
168 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
169 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
f8af9332 170 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
b1023571
KW		 171};
172
a5fdb336
CZ		 173static const u32 golden_settings_gc_9_1[] =
174{
175 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
01b5cc36
HZ		 176 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
177 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
178 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 179 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
180 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
01b5cc36 181 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 182 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
183 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
184 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
01b5cc36
HZ		 185 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
186 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
187 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
188 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
189 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 190 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
191 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
192 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
01b5cc36
HZ		 193 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
194 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
195 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
a5fdb336
CZ		 196};
197
198static const u32 golden_settings_gc_9_1_rv1[] =
199{
7b6ba9ea
HZ		 200 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
201 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
202 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
203 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
204 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
205 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
a5fdb336 206 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
b1023571
KW		 207};
208
209#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
7b6ba9ea 210#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
b1023571
KW		 211
212static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
213static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
214static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
215static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
216static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
217 struct amdgpu_cu_info *cu_info);
218static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
219static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
635e7132 220static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
b1023571
KW		 221
222static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
223{
224 switch (adev->asic_type) {
225 case CHIP_VEGA10:
226 amdgpu_program_register_sequence(adev,
227 golden_settings_gc_9_0,
228 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
229 amdgpu_program_register_sequence(adev,
230 golden_settings_gc_9_0_vg10,
231 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
232 break;
a5fdb336
CZ		 233 case CHIP_RAVEN:
234 amdgpu_program_register_sequence(adev,
235 golden_settings_gc_9_1,
236 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
237 amdgpu_program_register_sequence(adev,
238 golden_settings_gc_9_1_rv1,
239 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
240 break;
b1023571
KW		 241 default:
242 break;
243 }
244}
245
246static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
247{
6a05148f 248 adev->gfx.scratch.num_reg = 8;
b1023571
KW		 249 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
250 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
251}
252
253static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
254 bool wc, uint32_t reg, uint32_t val)
255{
256 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
257 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
258 WRITE_DATA_DST_SEL(0) |
259 (wc ? WR_CONFIRM : 0));
260 amdgpu_ring_write(ring, reg);
261 amdgpu_ring_write(ring, 0);
262 amdgpu_ring_write(ring, val);
263}
264
265static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
266 int mem_space, int opt, uint32_t addr0,
267 uint32_t addr1, uint32_t ref, uint32_t mask,
268 uint32_t inv)
269{
270 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
271 amdgpu_ring_write(ring,
272 /* memory (1) or register (0) */
273 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
274 WAIT_REG_MEM_OPERATION(opt) | /* wait */
275 WAIT_REG_MEM_FUNCTION(3) | /* equal */
276 WAIT_REG_MEM_ENGINE(eng_sel)));
277
278 if (mem_space)
279 BUG_ON(addr0 & 0x3); /* Dword align */
280 amdgpu_ring_write(ring, addr0);
281 amdgpu_ring_write(ring, addr1);
282 amdgpu_ring_write(ring, ref);
283 amdgpu_ring_write(ring, mask);
284 amdgpu_ring_write(ring, inv); /* poll interval */
285}
286
287static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
288{
289 struct amdgpu_device *adev = ring->adev;
290 uint32_t scratch;
291 uint32_t tmp = 0;
292 unsigned i;
293 int r;
294
295 r = amdgpu_gfx_scratch_get(adev, &scratch);
296 if (r) {
297 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
298 return r;
299 }
300 WREG32(scratch, 0xCAFEDEAD);
301 r = amdgpu_ring_alloc(ring, 3);
302 if (r) {
303 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
304 ring->idx, r);
305 amdgpu_gfx_scratch_free(adev, scratch);
306 return r;
307 }
308 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
309 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
310 amdgpu_ring_write(ring, 0xDEADBEEF);
311 amdgpu_ring_commit(ring);
312
313 for (i = 0; i < adev->usec_timeout; i++) {
314 tmp = RREG32(scratch);
315 if (tmp == 0xDEADBEEF)
316 break;
317 DRM_UDELAY(1);
318 }
319 if (i < adev->usec_timeout) {
320 DRM_INFO("ring test on %d succeeded in %d usecs\n",
321 ring->idx, i);
322 } else {
323 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
324 ring->idx, scratch, tmp);
325 r = -EINVAL;
326 }
327 amdgpu_gfx_scratch_free(adev, scratch);
328 return r;
329}
330
331static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
332{
333 struct amdgpu_device *adev = ring->adev;
334 struct amdgpu_ib ib;
335 struct dma_fence *f = NULL;
336 uint32_t scratch;
337 uint32_t tmp = 0;
338 long r;
339
340 r = amdgpu_gfx_scratch_get(adev, &scratch);
341 if (r) {
342 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
343 return r;
344 }
345 WREG32(scratch, 0xCAFEDEAD);
346 memset(&ib, 0, sizeof(ib));
347 r = amdgpu_ib_get(adev, NULL, 256, &ib);
348 if (r) {
349 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
350 goto err1;
351 }
352 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
353 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
354 ib.ptr[2] = 0xDEADBEEF;
355 ib.length_dw = 3;
356
357 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
358 if (r)
359 goto err2;
360
361 r = dma_fence_wait_timeout(f, false, timeout);
362 if (r == 0) {
363 DRM_ERROR("amdgpu: IB test timed out.\n");
364 r = -ETIMEDOUT;
365 goto err2;
366 } else if (r < 0) {
367 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
368 goto err2;
369 }
370 tmp = RREG32(scratch);
371 if (tmp == 0xDEADBEEF) {
372 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
373 r = 0;
374 } else {
375 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
376 scratch, tmp);
377 r = -EINVAL;
378 }
379err2:
380 amdgpu_ib_free(adev, &ib, NULL);
381 dma_fence_put(f);
382err1:
383 amdgpu_gfx_scratch_free(adev, scratch);
384 return r;
385}
386
387static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
388{
389 const char *chip_name;
390 char fw_name[30];
391 int err;
392 struct amdgpu_firmware_info *info = NULL;
393 const struct common_firmware_header *header = NULL;
394 const struct gfx_firmware_header_v1_0 *cp_hdr;
a4d41ad0
HZ		 395 const struct rlc_firmware_header_v2_0 *rlc_hdr;
396 unsigned int *tmp = NULL;
397 unsigned int i = 0;
b1023571
KW		 398
399 DRM_DEBUG("\n");
400
401 switch (adev->asic_type) {
402 case CHIP_VEGA10:
403 chip_name = "vega10";
404 break;
eaa85724
CZ		 405 case CHIP_RAVEN:
406 chip_name = "raven";
407 break;
b1023571
KW		 408 default:
409 BUG();
410 }
411
412 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
413 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
414 if (err)
415 goto out;
416 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
417 if (err)
418 goto out;
419 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
420 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
421 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
422
423 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
424 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
425 if (err)
426 goto out;
427 err = amdgpu_ucode_validate(adev->gfx.me_fw);
428 if (err)
429 goto out;
430 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
431 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
432 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
433
434 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
435 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
436 if (err)
437 goto out;
438 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
439 if (err)
440 goto out;
441 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
442 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
443 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
444
445 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
446 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
447 if (err)
448 goto out;
449 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
a4d41ad0
HZ		 450 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
451 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
452 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
453 adev->gfx.rlc.save_and_restore_offset =
454 le32_to_cpu(rlc_hdr->save_and_restore_offset);
455 adev->gfx.rlc.clear_state_descriptor_offset =
456 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
457 adev->gfx.rlc.avail_scratch_ram_locations =
458 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
459 adev->gfx.rlc.reg_restore_list_size =
460 le32_to_cpu(rlc_hdr->reg_restore_list_size);
461 adev->gfx.rlc.reg_list_format_start =
462 le32_to_cpu(rlc_hdr->reg_list_format_start);
463 adev->gfx.rlc.reg_list_format_separate_start =
464 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
465 adev->gfx.rlc.starting_offsets_start =
466 le32_to_cpu(rlc_hdr->starting_offsets_start);
467 adev->gfx.rlc.reg_list_format_size_bytes =
468 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
469 adev->gfx.rlc.reg_list_size_bytes =
470 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
471 adev->gfx.rlc.register_list_format =
472 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
473 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
474 if (!adev->gfx.rlc.register_list_format) {
475 err = -ENOMEM;
476 goto out;
477 }
478
479 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
480 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
481 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
482 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
483
484 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
485
486 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
487 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
488 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
489 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
b1023571
KW		 490
491 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
492 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
493 if (err)
494 goto out;
495 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
496 if (err)
497 goto out;
498 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
499 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
500 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
501
502
503 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
504 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
505 if (!err) {
506 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
507 if (err)
508 goto out;
509 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
510 adev->gfx.mec2_fw->data;
511 adev->gfx.mec2_fw_version =
512 le32_to_cpu(cp_hdr->header.ucode_version);
513 adev->gfx.mec2_feature_version =
514 le32_to_cpu(cp_hdr->ucode_feature_version);
515 } else {
516 err = 0;
517 adev->gfx.mec2_fw = NULL;
518 }
519
520 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
521 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
522 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
523 info->fw = adev->gfx.pfp_fw;
524 header = (const struct common_firmware_header *)info->fw->data;
525 adev->firmware.fw_size +=
526 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
527
528 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
529 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
530 info->fw = adev->gfx.me_fw;
531 header = (const struct common_firmware_header *)info->fw->data;
532 adev->firmware.fw_size +=
533 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
534
535 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
536 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
537 info->fw = adev->gfx.ce_fw;
538 header = (const struct common_firmware_header *)info->fw->data;
539 adev->firmware.fw_size +=
540 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
541
542 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
543 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
544 info->fw = adev->gfx.rlc_fw;
545 header = (const struct common_firmware_header *)info->fw->data;
546 adev->firmware.fw_size +=
547 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
548
549 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
550 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
551 info->fw = adev->gfx.mec_fw;
552 header = (const struct common_firmware_header *)info->fw->data;
553 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
554 adev->firmware.fw_size +=
555 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
556
557 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
558 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
559 info->fw = adev->gfx.mec_fw;
560 adev->firmware.fw_size +=
561 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
562
563 if (adev->gfx.mec2_fw) {
564 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
565 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
566 info->fw = adev->gfx.mec2_fw;
567 header = (const struct common_firmware_header *)info->fw->data;
568 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
569 adev->firmware.fw_size +=
570 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
571 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
572 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
573 info->fw = adev->gfx.mec2_fw;
574 adev->firmware.fw_size +=
575 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
576 }
577
578 }
579
580out:
581 if (err) {
582 dev_err(adev->dev,
583 "gfx9: Failed to load firmware \"%s\"\n",
584 fw_name);
585 release_firmware(adev->gfx.pfp_fw);
586 adev->gfx.pfp_fw = NULL;
587 release_firmware(adev->gfx.me_fw);
588 adev->gfx.me_fw = NULL;
589 release_firmware(adev->gfx.ce_fw);
590 adev->gfx.ce_fw = NULL;
591 release_firmware(adev->gfx.rlc_fw);
592 adev->gfx.rlc_fw = NULL;
593 release_firmware(adev->gfx.mec_fw);
594 adev->gfx.mec_fw = NULL;
595 release_firmware(adev->gfx.mec2_fw);
596 adev->gfx.mec2_fw = NULL;
597 }
598 return err;
599}
600
c9719c69
HZ		 601static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
602{
603 u32 count = 0;
604 const struct cs_section_def *sect = NULL;
605 const struct cs_extent_def *ext = NULL;
606
607 /* begin clear state */
608 count += 2;
609 /* context control state */
610 count += 3;
611
612 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
613 for (ext = sect->section; ext->extent != NULL; ++ext) {
614 if (sect->id == SECT_CONTEXT)
615 count += 2 + ext->reg_count;
616 else
617 return 0;
618 }
619 }
620
621 /* end clear state */
622 count += 2;
623 /* clear state */
624 count += 2;
625
626 return count;
627}
628
629static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
630 volatile u32 *buffer)
631{
632 u32 count = 0, i;
633 const struct cs_section_def *sect = NULL;
634 const struct cs_extent_def *ext = NULL;
635
636 if (adev->gfx.rlc.cs_data == NULL)
637 return;
638 if (buffer == NULL)
639 return;
640
641 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
642 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
643
644 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
645 buffer[count++] = cpu_to_le32(0x80000000);
646 buffer[count++] = cpu_to_le32(0x80000000);
647
648 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
649 for (ext = sect->section; ext->extent != NULL; ++ext) {
650 if (sect->id == SECT_CONTEXT) {
651 buffer[count++] =
652 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
653 buffer[count++] = cpu_to_le32(ext->reg_index -
654 PACKET3_SET_CONTEXT_REG_START);
655 for (i = 0; i < ext->reg_count; i++)
656 buffer[count++] = cpu_to_le32(ext->extent[i]);
657 } else {
658 return;
659 }
660 }
661 }
662
663 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
664 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
665
666 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
667 buffer[count++] = cpu_to_le32(0);
668}
669
ba7bb665
HZ		 670static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
671{
e5475e16 672 uint32_t data;
ba7bb665
HZ		 673
674 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
675 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
676 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
677 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
678 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
679
680 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
681 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
682
683 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
684 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
685
686 mutex_lock(&adev->grbm_idx_mutex);
687 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
688 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
689 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
690
691 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
e5475e16
TSD		 692 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
693 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
694 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
ba7bb665
HZ		 695 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
696
697 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
698 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
699 data &= 0x0000FFFF;
700 data |= 0x00C00000;
701 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
702
703 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
704 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
705
706 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
707 * but used for RLC_LB_CNTL configuration */
708 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
e5475e16
TSD		 709 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
710 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
ba7bb665
HZ		 711 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
712 mutex_unlock(&adev->grbm_idx_mutex);
713}
714
e8835e0e
HZ		 715static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
716{
e5475e16 717 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
e8835e0e
HZ		 718}
719
c9719c69
HZ		 720static void rv_init_cp_jump_table(struct amdgpu_device *adev)
721{
722 const __le32 *fw_data;
723 volatile u32 *dst_ptr;
724 int me, i, max_me = 5;
725 u32 bo_offset = 0;
726 u32 table_offset, table_size;
727
728 /* write the cp table buffer */
729 dst_ptr = adev->gfx.rlc.cp_table_ptr;
730 for (me = 0; me < max_me; me++) {
731 if (me == 0) {
732 const struct gfx_firmware_header_v1_0 *hdr =
733 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
734 fw_data = (const __le32 *)
735 (adev->gfx.ce_fw->data +
736 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
737 table_offset = le32_to_cpu(hdr->jt_offset);
738 table_size = le32_to_cpu(hdr->jt_size);
739 } else if (me == 1) {
740 const struct gfx_firmware_header_v1_0 *hdr =
741 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
742 fw_data = (const __le32 *)
743 (adev->gfx.pfp_fw->data +
744 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
745 table_offset = le32_to_cpu(hdr->jt_offset);
746 table_size = le32_to_cpu(hdr->jt_size);
747 } else if (me == 2) {
748 const struct gfx_firmware_header_v1_0 *hdr =
749 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
750 fw_data = (const __le32 *)
751 (adev->gfx.me_fw->data +
752 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
753 table_offset = le32_to_cpu(hdr->jt_offset);
754 table_size = le32_to_cpu(hdr->jt_size);
755 } else if (me == 3) {
756 const struct gfx_firmware_header_v1_0 *hdr =
757 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
758 fw_data = (const __le32 *)
759 (adev->gfx.mec_fw->data +
760 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
761 table_offset = le32_to_cpu(hdr->jt_offset);
762 table_size = le32_to_cpu(hdr->jt_size);
763 } else if (me == 4) {
764 const struct gfx_firmware_header_v1_0 *hdr =
765 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
766 fw_data = (const __le32 *)
767 (adev->gfx.mec2_fw->data +
768 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
769 table_offset = le32_to_cpu(hdr->jt_offset);
770 table_size = le32_to_cpu(hdr->jt_size);
771 }
772
773 for (i = 0; i < table_size; i ++) {
774 dst_ptr[bo_offset + i] =
775 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
776 }
777
778 bo_offset += table_size;
779 }
780}
781
782static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
783{
784 /* clear state block */
785 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
786 &adev->gfx.rlc.clear_state_gpu_addr,
787 (void **)&adev->gfx.rlc.cs_ptr);
788
789 /* jump table block */
790 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
791 &adev->gfx.rlc.cp_table_gpu_addr,
792 (void **)&adev->gfx.rlc.cp_table_ptr);
793}
794
795static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
796{
797 volatile u32 *dst_ptr;
798 u32 dws;
799 const struct cs_section_def *cs_data;
800 int r;
801
802 adev->gfx.rlc.cs_data = gfx9_cs_data;
803
804 cs_data = adev->gfx.rlc.cs_data;
805
806 if (cs_data) {
807 /* clear state block */
808 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
a4a02777
CK		 809 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
810 AMDGPU_GEM_DOMAIN_VRAM,
811 &adev->gfx.rlc.clear_state_obj,
812 &adev->gfx.rlc.clear_state_gpu_addr,
813 (void **)&adev->gfx.rlc.cs_ptr);
814 if (r) {
815 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
816 r);
817 gfx_v9_0_rlc_fini(adev);
818 return r;
c9719c69
HZ		 819 }
820 /* set up the cs buffer */
821 dst_ptr = adev->gfx.rlc.cs_ptr;
822 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
823 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
824 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
825 }
826
827 if (adev->asic_type == CHIP_RAVEN) {
828 /* TODO: double check the cp_table_size for RV */
829 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
a4a02777
CK		 830 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
831 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
832 &adev->gfx.rlc.cp_table_obj,
833 &adev->gfx.rlc.cp_table_gpu_addr,
834 (void **)&adev->gfx.rlc.cp_table_ptr);
835 if (r) {
836 dev_err(adev->dev,
837 "(%d) failed to create cp table bo\n", r);
838 gfx_v9_0_rlc_fini(adev);
839 return r;
c9719c69
HZ		 840 }
841
842 rv_init_cp_jump_table(adev);
843 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
844 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
ba7bb665
HZ		 845
846 gfx_v9_0_init_lbpw(adev);
c9719c69
HZ		 847 }
848
849 return 0;
850}
851
b1023571
KW		 852static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
853{
078af1a3
CK		 854 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
855 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
b1023571
KW		 856}
857
b1023571
KW		 858static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
859{
860 int r;
861 u32 *hpd;
862 const __le32 *fw_data;
863 unsigned fw_size;
864 u32 *fw;
42794b27 865 size_t mec_hpd_size;
b1023571
KW		 866
867 const struct gfx_firmware_header_v1_0 *mec_hdr;
868
78c16834
AR		 869 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
870
78c16834 871 /* take ownership of the relevant compute queues */
41f6a99a 872 amdgpu_gfx_compute_queue_acquire(adev);
78c16834 873 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
b1023571 874
a4a02777
CK		 875 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
876 AMDGPU_GEM_DOMAIN_GTT,
877 &adev->gfx.mec.hpd_eop_obj,
878 &adev->gfx.mec.hpd_eop_gpu_addr,
879 (void **)&hpd);
b1023571 880 if (r) {
a4a02777 881 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
b1023571
KW		 882 gfx_v9_0_mec_fini(adev);
883 return r;
884 }
885
886 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
887
888 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
889 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
890
891 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
892
893 fw_data = (const __le32 *)
894 (adev->gfx.mec_fw->data +
895 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
896 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
897
a4a02777
CK		 898 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
899 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
900 &adev->gfx.mec.mec_fw_obj,
901 &adev->gfx.mec.mec_fw_gpu_addr,
902 (void **)&fw);
b1023571 903 if (r) {
a4a02777 904 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
b1023571
KW		 905 gfx_v9_0_mec_fini(adev);
906 return r;
907 }
a4a02777 908
b1023571
KW		 909 memcpy(fw, fw_data, fw_size);
910
911 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
912 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
913
b1023571
KW		 914 return 0;
915}
916
917static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
918{
5e78835a 919 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 920 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
921 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
922 (address << SQ_IND_INDEX__INDEX__SHIFT) |
923 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 924 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 925}
926
927static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
928 uint32_t wave, uint32_t thread,
929 uint32_t regno, uint32_t num, uint32_t *out)
930{
5e78835a 931 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 932 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
933 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
934 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
935 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
936 (SQ_IND_INDEX__FORCE_READ_MASK) |
937 (SQ_IND_INDEX__AUTO_INCR_MASK));
938 while (num--)
5e78835a 939 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 940}
941
942static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
943{
944 /* type 1 wave data */
945 dst[(*no_fields)++] = 1;
946 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
947 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
948 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
949 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
950 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
951 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
952 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
953 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
954 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
955 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
956 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
957 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
958 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
959 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
960}
961
962static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
963 uint32_t wave, uint32_t start,
964 uint32_t size, uint32_t *dst)
965{
966 wave_read_regs(
967 adev, simd, wave, 0,
968 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
969}
970
971
972static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
973 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
974 .select_se_sh = &gfx_v9_0_select_se_sh,
975 .read_wave_data = &gfx_v9_0_read_wave_data,
976 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
977};
978
979static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
980{
981 u32 gb_addr_config;
982
983 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
984
985 switch (adev->asic_type) {
986 case CHIP_VEGA10:
b1023571 987 adev->gfx.config.max_hw_contexts = 8;
b1023571
KW		 988 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
989 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
990 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
991 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
992 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
993 break;
5cf7433d
CZ		 994 case CHIP_RAVEN:
995 adev->gfx.config.max_hw_contexts = 8;
996 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
997 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
998 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
999 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1000 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1001 break;
b1023571
KW		 1002 default:
1003 BUG();
1004 break;
1005 }
1006
1007 adev->gfx.config.gb_addr_config = gb_addr_config;
1008
1009 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1010 REG_GET_FIELD(
1011 adev->gfx.config.gb_addr_config,
1012 GB_ADDR_CONFIG,
1013 NUM_PIPES);
ad7d0ff3
AD		 1014
1015 adev->gfx.config.max_tile_pipes =
1016 adev->gfx.config.gb_addr_config_fields.num_pipes;
1017
b1023571
KW		 1018 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1019 REG_GET_FIELD(
1020 adev->gfx.config.gb_addr_config,
1021 GB_ADDR_CONFIG,
1022 NUM_BANKS);
1023 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1024 REG_GET_FIELD(
1025 adev->gfx.config.gb_addr_config,
1026 GB_ADDR_CONFIG,
1027 MAX_COMPRESSED_FRAGS);
1028 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1029 REG_GET_FIELD(
1030 adev->gfx.config.gb_addr_config,
1031 GB_ADDR_CONFIG,
1032 NUM_RB_PER_SE);
1033 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1034 REG_GET_FIELD(
1035 adev->gfx.config.gb_addr_config,
1036 GB_ADDR_CONFIG,
1037 NUM_SHADER_ENGINES);
1038 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1039 REG_GET_FIELD(
1040 adev->gfx.config.gb_addr_config,
1041 GB_ADDR_CONFIG,
1042 PIPE_INTERLEAVE_SIZE));
1043}
1044
1045static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1046 struct amdgpu_ngg_buf *ngg_buf,
1047 int size_se,
1048 int default_size_se)
1049{
1050 int r;
1051
1052 if (size_se < 0) {
1053 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1054 return -EINVAL;
1055 }
1056 size_se = size_se ? size_se : default_size_se;
1057
42ce2243 1058 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 1059 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1060 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1061 &ngg_buf->bo,
1062 &ngg_buf->gpu_addr,
1063 NULL);
1064 if (r) {
1065 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1066 return r;
1067 }
1068 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1069
1070 return r;
1071}
1072
1073static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1074{
1075 int i;
1076
1077 for (i = 0; i < NGG_BUF_MAX; i++)
1078 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1079 &adev->gfx.ngg.buf[i].gpu_addr,
1080 NULL);
1081
1082 memset(&adev->gfx.ngg.buf[0], 0,
1083 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1084
1085 adev->gfx.ngg.init = false;
1086
1087 return 0;
1088}
1089
1090static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1091{
1092 int r;
1093
1094 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1095 return 0;
1096
1097 /* GDS reserve memory: 64 bytes alignment */
1098 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1099 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1100 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1101 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1102 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1103
1104 /* Primitive Buffer */
af8baf15 1105 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
b1023571
KW		 1106 amdgpu_prim_buf_per_se,
1107 64 * 1024);
1108 if (r) {
1109 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1110 goto err;
1111 }
1112
1113 /* Position Buffer */
af8baf15 1114 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
b1023571
KW		 1115 amdgpu_pos_buf_per_se,
1116 256 * 1024);
1117 if (r) {
1118 dev_err(adev->dev, "Failed to create Position Buffer\n");
1119 goto err;
1120 }
1121
1122 /* Control Sideband */
af8baf15 1123 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
b1023571
KW		 1124 amdgpu_cntl_sb_buf_per_se,
1125 256);
1126 if (r) {
1127 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1128 goto err;
1129 }
1130
1131 /* Parameter Cache, not created by default */
1132 if (amdgpu_param_buf_per_se <= 0)
1133 goto out;
1134
af8baf15 1135 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
b1023571
KW		 1136 amdgpu_param_buf_per_se,
1137 512 * 1024);
1138 if (r) {
1139 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1140 goto err;
1141 }
1142
1143out:
1144 adev->gfx.ngg.init = true;
1145 return 0;
1146err:
1147 gfx_v9_0_ngg_fini(adev);
1148 return r;
1149}
1150
1151static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1152{
1153 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1154 int r;
91629eff 1155 u32 data, base;
b1023571
KW		 1156
1157 if (!amdgpu_ngg)
1158 return 0;
1159
1160 /* Program buffer size */
91629eff
TSD		 1161 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1162 adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1163 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1164 adev->gfx.ngg.buf[NGG_POS].size >> 8);
5e78835a 1165 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571 1166
91629eff
TSD		 1167 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1168 adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1169 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1170 adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
5e78835a 1171 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 1172
1173 /* Program buffer base address */
af8baf15 1174 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1175 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 1176 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571 1177
af8baf15 1178 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1179 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 1180 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571 1181
af8baf15 1182 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1183 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 1184 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571 1185
af8baf15 1186 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1187 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 1188 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571 1189
af8baf15 1190 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1191 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 1192 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571 1193
af8baf15 1194 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1195 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 1196 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 1197
1198 /* Clear GDS reserved memory */
1199 r = amdgpu_ring_alloc(ring, 17);
1200 if (r) {
1201 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1202 ring->idx, r);
1203 return r;
1204 }
1205
1206 gfx_v9_0_write_data_to_reg(ring, 0, false,
1207 amdgpu_gds_reg_offset[0].mem_size,
1208 (adev->gds.mem.total_size +
1209 adev->gfx.ngg.gds_reserve_size) >>
1210 AMDGPU_GDS_SHIFT);
1211
1212 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1213 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1214 PACKET3_DMA_DATA_SRC_SEL(2)));
1215 amdgpu_ring_write(ring, 0);
1216 amdgpu_ring_write(ring, 0);
1217 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1218 amdgpu_ring_write(ring, 0);
1219 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1220
1221
1222 gfx_v9_0_write_data_to_reg(ring, 0, false,
1223 amdgpu_gds_reg_offset[0].mem_size, 0);
1224
1225 amdgpu_ring_commit(ring);
1226
1227 return 0;
1228}
1229
1361f455
AD		 1230static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1231 int mec, int pipe, int queue)
1232{
1233 int r;
1234 unsigned irq_type;
1235 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1236
1237 ring = &adev->gfx.compute_ring[ring_id];
1238
1239 /* mec0 is me1 */
1240 ring->me = mec + 1;
1241 ring->pipe = pipe;
1242 ring->queue = queue;
1243
1244 ring->ring_obj = NULL;
1245 ring->use_doorbell = true;
7366af81 1246 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1361f455
AD		 1247 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1248 + (ring_id * GFX9_MEC_HPD_SIZE);
1249 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1250
1251 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1252 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1253 + ring->pipe;
1254
1255 /* type-2 packets are deprecated on MEC, use type-3 instead */
1256 r = amdgpu_ring_init(adev, ring, 1024,
1257 &adev->gfx.eop_irq, irq_type);
1258 if (r)
1259 return r;
1260
1261
1262 return 0;
1263}
1264
b1023571
KW		 1265static int gfx_v9_0_sw_init(void *handle)
1266{
1361f455 1267 int i, j, k, r, ring_id;
b1023571 1268 struct amdgpu_ring *ring;
ac104e99 1269 struct amdgpu_kiq *kiq;
b1023571
KW		 1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1271
4853bbb6
AD		 1272 switch (adev->asic_type) {
1273 case CHIP_VEGA10:
1274 case CHIP_RAVEN:
1275 adev->gfx.mec.num_mec = 2;
1276 break;
1277 default:
1278 adev->gfx.mec.num_mec = 1;
1279 break;
1280 }
1281
1282 adev->gfx.mec.num_pipe_per_mec = 4;
1283 adev->gfx.mec.num_queue_per_pipe = 8;
1284
97031e25
XY		 1285 /* KIQ event */
1286 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1287 if (r)
1288 return r;
1289
b1023571
KW		 1290 /* EOP Event */
1291 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1292 if (r)
1293 return r;
1294
1295 /* Privileged reg */
1296 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1297 &adev->gfx.priv_reg_irq);
1298 if (r)
1299 return r;
1300
1301 /* Privileged inst */
1302 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1303 &adev->gfx.priv_inst_irq);
1304 if (r)
1305 return r;
1306
1307 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1308
1309 gfx_v9_0_scratch_init(adev);
1310
1311 r = gfx_v9_0_init_microcode(adev);
1312 if (r) {
1313 DRM_ERROR("Failed to load gfx firmware!\n");
1314 return r;
1315 }
1316
c9719c69
HZ		 1317 r = gfx_v9_0_rlc_init(adev);
1318 if (r) {
1319 DRM_ERROR("Failed to init rlc BOs!\n");
1320 return r;
1321 }
1322
b1023571
KW		 1323 r = gfx_v9_0_mec_init(adev);
1324 if (r) {
1325 DRM_ERROR("Failed to init MEC BOs!\n");
1326 return r;
1327 }
1328
1329 /* set up the gfx ring */
1330 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1331 ring = &adev->gfx.gfx_ring[i];
1332 ring->ring_obj = NULL;
f6886c47
TSD		 1333 if (!i)
1334 sprintf(ring->name, "gfx");
1335 else
1336 sprintf(ring->name, "gfx_%d", i);
b1023571
KW		 1337 ring->use_doorbell = true;
1338 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1339 r = amdgpu_ring_init(adev, ring, 1024,
1340 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1341 if (r)
1342 return r;
1343 }
1344
1361f455
AD		 1345 /* set up the compute queues - allocate horizontally across pipes */
1346 ring_id = 0;
1347 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1348 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1349 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2db0cdbe 1350 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1361f455
AD		 1351 continue;
1352
1353 r = gfx_v9_0_compute_ring_init(adev,
1354 ring_id,
1355 i, k, j);
1356 if (r)
1357 return r;
1358
1359 ring_id++;
1360 }
b1023571 1361 }
b1023571
KW		 1362 }
1363
71c37505 1364 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
e30a5223
AD		 1365 if (r) {
1366 DRM_ERROR("Failed to init KIQ BOs!\n");
1367 return r;
1368 }
ac104e99 1369
e30a5223 1370 kiq = &adev->gfx.kiq;
71c37505 1371 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
e30a5223
AD		 1372 if (r)
1373 return r;
464826d6 1374
e30a5223 1375 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
ffe6d881 1376 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
e30a5223
AD		 1377 if (r)
1378 return r;
ac104e99 1379
b1023571
KW		 1380 /* reserve GDS, GWS and OA resource for gfx */
1381 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1382 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1383 &adev->gds.gds_gfx_bo, NULL, NULL);
1384 if (r)
1385 return r;
1386
1387 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1388 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1389 &adev->gds.gws_gfx_bo, NULL, NULL);
1390 if (r)
1391 return r;
1392
1393 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1394 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1395 &adev->gds.oa_gfx_bo, NULL, NULL);
1396 if (r)
1397 return r;
1398
1399 adev->gfx.ce_ram_size = 0x8000;
1400
1401 gfx_v9_0_gpu_early_init(adev);
1402
1403 r = gfx_v9_0_ngg_init(adev);
1404 if (r)
1405 return r;
1406
1407 return 0;
1408}
1409
1410
1411static int gfx_v9_0_sw_fini(void *handle)
1412{
1413 int i;
1414 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1415
1416 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1417 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1418 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1419
1420 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1421 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1422 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1423 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1424
b9683c21 1425 amdgpu_gfx_compute_mqd_sw_fini(adev);
71c37505
AD		 1426 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1427 amdgpu_gfx_kiq_fini(adev);
ac104e99 1428
b1023571
KW		 1429 gfx_v9_0_mec_fini(adev);
1430 gfx_v9_0_ngg_fini(adev);
1431
1432 return 0;
1433}
1434
1435
1436static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1437{
1438 /* TODO */
1439}
1440
1441static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1442{
be448a4d 1443 u32 data;
b1023571 1444
be448a4d
NH		 1445 if (instance == 0xffffffff)
1446 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1447 else
1448 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1449
1450 if (se_num == 0xffffffff)
b1023571 1451 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
be448a4d 1452 else
b1023571 1453 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
be448a4d
NH		 1454
1455 if (sh_num == 0xffffffff)
1456 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1457 else
b1023571 1458 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
be448a4d 1459
5e78835a 1460 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1461}
1462
b1023571
KW		 1463static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1464{
1465 u32 data, mask;
1466
5e78835a
TSD		 1467 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1468 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1469
1470 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1471 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1472
378506a7
AD		 1473 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1474 adev->gfx.config.max_sh_per_se);
b1023571
KW		 1475
1476 return (~data) & mask;
1477}
1478
1479static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1480{
1481 int i, j;
2572c24c 1482 u32 data;
b1023571
KW		 1483 u32 active_rbs = 0;
1484 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1485 adev->gfx.config.max_sh_per_se;
1486
1487 mutex_lock(&adev->grbm_idx_mutex);
1488 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1489 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1490 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1491 data = gfx_v9_0_get_rb_active_bitmap(adev);
1492 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1493 rb_bitmap_width_per_sh);
1494 }
1495 }
1496 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1497 mutex_unlock(&adev->grbm_idx_mutex);
1498
1499 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1500 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1501}
1502
1503#define DEFAULT_SH_MEM_BASES (0x6000)
1504#define FIRST_COMPUTE_VMID (8)
1505#define LAST_COMPUTE_VMID (16)
1506static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1507{
1508 int i;
1509 uint32_t sh_mem_config;
1510 uint32_t sh_mem_bases;
1511
1512 /*
1513 * Configure apertures:
1514 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1515 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1516 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1517 */
1518 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1519
1520 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1521 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
eaa05d52 1522 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
b1023571
KW		 1523
1524 mutex_lock(&adev->srbm_mutex);
1525 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1526 soc15_grbm_select(adev, 0, 0, 0, i);
1527 /* CP and shaders */
5e78835a
TSD		 1528 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1529 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1530 }
1531 soc15_grbm_select(adev, 0, 0, 0, 0);
1532 mutex_unlock(&adev->srbm_mutex);
1533}
1534
1535static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1536{
1537 u32 tmp;
1538 int i;
1539
40f06773 1540 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1541
1542 gfx_v9_0_tiling_mode_table_init(adev);
1543
1544 gfx_v9_0_setup_rb(adev);
1545 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1546
1547 /* XXX SH_MEM regs */
1548 /* where to put LDS, scratch, GPUVM in FSA64 space */
1549 mutex_lock(&adev->srbm_mutex);
1550 for (i = 0; i < 16; i++) {
1551 soc15_grbm_select(adev, 0, 0, 0, i);
1552 /* CP and shaders */
1553 tmp = 0;
1554 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1555 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5e78835a
TSD		 1556 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1557 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
b1023571
KW		 1558 }
1559 soc15_grbm_select(adev, 0, 0, 0, 0);
1560
1561 mutex_unlock(&adev->srbm_mutex);
1562
1563 gfx_v9_0_init_compute_vmid(adev);
1564
1565 mutex_lock(&adev->grbm_idx_mutex);
1566 /*
1567 * making sure that the following register writes will be broadcasted
1568 * to all the shaders
1569 */
1570 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1571
5e78835a 1572 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1573 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1574 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1575 (adev->gfx.config.sc_prim_fifo_size_backend <<
1576 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1577 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1578 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1579 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1580 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1581 mutex_unlock(&adev->grbm_idx_mutex);
1582
1583}
1584
1585static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1586{
1587 u32 i, j, k;
1588 u32 mask;
1589
1590 mutex_lock(&adev->grbm_idx_mutex);
1591 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1592 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1593 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1594 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1595 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1596 break;
1597 udelay(1);
1598 }
1599 }
1600 }
1601 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1602 mutex_unlock(&adev->grbm_idx_mutex);
1603
1604 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1605 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1606 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1607 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1608 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1609 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1610 break;
1611 udelay(1);
1612 }
1613}
1614
1615static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1616 bool enable)
1617{
5e78835a 1618 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571 1619
b1023571
KW		 1620 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1621 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1622 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1623 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1624
5e78835a 1625 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1626}
1627
6bce4667
HZ		 1628static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1629{
1630 /* csib */
1631 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1632 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1633 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1634 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1635 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1636 adev->gfx.rlc.clear_state_size);
1637}
1638
1639static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1640 int indirect_offset,
1641 int list_size,
1642 int *unique_indirect_regs,
1643 int *unique_indirect_reg_count,
1644 int max_indirect_reg_count,
1645 int *indirect_start_offsets,
1646 int *indirect_start_offsets_count,
1647 int max_indirect_start_offsets_count)
1648{
1649 int idx;
1650 bool new_entry = true;
1651
1652 for (; indirect_offset < list_size; indirect_offset++) {
1653
1654 if (new_entry) {
1655 new_entry = false;
1656 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1657 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1658 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1659 }
1660
1661 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1662 new_entry = true;
1663 continue;
1664 }
1665
1666 indirect_offset += 2;
1667
1668 /* look for the matching indice */
1669 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1670 if (unique_indirect_regs[idx] ==
1671 register_list_format[indirect_offset])
1672 break;
1673 }
1674
1675 if (idx >= *unique_indirect_reg_count) {
1676 unique_indirect_regs[*unique_indirect_reg_count] =
1677 register_list_format[indirect_offset];
1678 idx = *unique_indirect_reg_count;
1679 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1680 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1681 }
1682
1683 register_list_format[indirect_offset] = idx;
1684 }
1685}
1686
1687static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1688{
1689 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1690 int unique_indirect_reg_count = 0;
1691
1692 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1693 int indirect_start_offsets_count = 0;
1694
1695 int list_size = 0;
1696 int i = 0;
1697 u32 tmp = 0;
1698
1699 u32 *register_list_format =
1700 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1701 if (!register_list_format)
1702 return -ENOMEM;
1703 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1704 adev->gfx.rlc.reg_list_format_size_bytes);
1705
1706 /* setup unique_indirect_regs array and indirect_start_offsets array */
1707 gfx_v9_0_parse_ind_reg_list(register_list_format,
1708 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1709 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1710 unique_indirect_regs,
1711 &unique_indirect_reg_count,
1712 sizeof(unique_indirect_regs)/sizeof(int),
1713 indirect_start_offsets,
1714 &indirect_start_offsets_count,
1715 sizeof(indirect_start_offsets)/sizeof(int));
1716
1717 /* enable auto inc in case it is disabled */
1718 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1719 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1720 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1721
1722 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1723 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1724 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1725 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1726 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1727 adev->gfx.rlc.register_restore[i]);
1728
1729 /* load direct register */
1730 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1731 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1732 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1733 adev->gfx.rlc.register_restore[i]);
1734
1735 /* load indirect register */
1736 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1737 adev->gfx.rlc.reg_list_format_start);
1738 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1739 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1740 register_list_format[i]);
1741
1742 /* set save/restore list size */
1743 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1744 list_size = list_size >> 1;
1745 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1746 adev->gfx.rlc.reg_restore_list_size);
1747 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1748
1749 /* write the starting offsets to RLC scratch ram */
1750 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1751 adev->gfx.rlc.starting_offsets_start);
1752 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1753 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1754 indirect_start_offsets[i]);
1755
1756 /* load unique indirect regs*/
1757 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1758 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1759 unique_indirect_regs[i] & 0x3FFFF);
1760 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1761 unique_indirect_regs[i] >> 20);
1762 }
1763
1764 kfree(register_list_format);
1765 return 0;
1766}
1767
1768static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1769{
0e5293d0 1770 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
6bce4667
HZ		 1771}
1772
91d3130a
HZ		 1773static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1774 bool enable)
1775{
1776 uint32_t data = 0;
1777 uint32_t default_data = 0;
1778
1779 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1780 if (enable == true) {
1781 /* enable GFXIP control over CGPG */
1782 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1783 if(default_data != data)
1784 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1785
1786 /* update status */
1787 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1788 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1789 if(default_data != data)
1790 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1791 } else {
1792 /* restore GFXIP control over GCPG */
1793 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1794 if(default_data != data)
1795 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1796 }
1797}
1798
1799static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1800{
1801 uint32_t data = 0;
1802
1803 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1804 AMD_PG_SUPPORT_GFX_SMG |
1805 AMD_PG_SUPPORT_GFX_DMG)) {
1806 /* init IDLE_POLL_COUNT = 60 */
1807 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1808 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1809 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1810 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1811
1812 /* init RLC PG Delay */
1813 data = 0;
1814 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1815 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1816 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1817 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1818 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1819
1820 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1821 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1822 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1823 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1824
1825 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1826 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1827 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1828 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1829
1830 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1831 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1832
1833 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1834 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1835 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1836
1837 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1838 }
1839}
1840
ed5ad1e4
HZ		 1841static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1842 bool enable)
1843{
1844 uint32_t data = 0;
1845 uint32_t default_data = 0;
1846
1847 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
e24c7f06
TSD		 1848 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1849 SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
1850 enable ? 1 : 0);
1851 if (default_data != data)
1852 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
ed5ad1e4
HZ		 1853}
1854
1855static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1856 bool enable)
1857{
1858 uint32_t data = 0;
1859 uint32_t default_data = 0;
1860
1861 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
b926fe8e
TSD		 1862 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1863 SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
1864 enable ? 1 : 0);
1865 if(default_data != data)
1866 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
ed5ad1e4
HZ		 1867}
1868
3a6cc477
HZ		 1869static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1870 bool enable)
1871{
1872 uint32_t data = 0;
1873 uint32_t default_data = 0;
1874
1875 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
54cfe0fc
TSD		 1876 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1877 CP_PG_DISABLE,
1878 enable ? 0 : 1);
1879 if(default_data != data)
1880 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
3a6cc477
HZ		 1881}
1882
197f95c8
HZ		 1883static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
1884 bool enable)
1885{
1886 uint32_t data, default_data;
1887
1888 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
f55ee212
TSD		 1889 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1890 GFX_POWER_GATING_ENABLE,
1891 enable ? 1 : 0);
197f95c8
HZ		 1892 if(default_data != data)
1893 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1894}
1895
1896static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
1897 bool enable)
1898{
1899 uint32_t data, default_data;
1900
1901 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
513f8133
TSD		 1902 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1903 GFX_PIPELINE_PG_ENABLE,
1904 enable ? 1 : 0);
197f95c8
HZ		 1905 if(default_data != data)
1906 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1907
1908 if (!enable)
1909 /* read any GFX register to wake up GFX */
1910 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
1911}
1912
552c8f76 1913static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
1914 bool enable)
18924c71
HZ		 1915{
1916 uint32_t data, default_data;
1917
1918 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
7915c8fd
TSD		 1919 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1920 STATIC_PER_CU_PG_ENABLE,
1921 enable ? 1 : 0);
18924c71
HZ		 1922 if(default_data != data)
1923 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1924}
1925
552c8f76 1926static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
18924c71
HZ		 1927 bool enable)
1928{
1929 uint32_t data, default_data;
1930
1931 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
e567fa69
TSD		 1932 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1933 DYN_PER_CU_PG_ENABLE,
1934 enable ? 1 : 0);
18924c71
HZ		 1935 if(default_data != data)
1936 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1937}
1938
6bce4667
HZ		 1939static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
1940{
1941 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1942 AMD_PG_SUPPORT_GFX_SMG |
1943 AMD_PG_SUPPORT_GFX_DMG |
1944 AMD_PG_SUPPORT_CP |
1945 AMD_PG_SUPPORT_GDS |
1946 AMD_PG_SUPPORT_RLC_SMU_HS)) {
1947 gfx_v9_0_init_csb(adev);
1948 gfx_v9_0_init_rlc_save_restore_list(adev);
1949 gfx_v9_0_enable_save_restore_machine(adev);
91d3130a
HZ		 1950
1951 if (adev->asic_type == CHIP_RAVEN) {
1952 WREG32(mmRLC_JUMP_TABLE_RESTORE,
1953 adev->gfx.rlc.cp_table_gpu_addr >> 8);
1954 gfx_v9_0_init_gfx_power_gating(adev);
3a6cc477 1955
ed5ad1e4
HZ		 1956 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
1957 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
1958 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
1959 } else {
1960 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
1961 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
1962 }
3a6cc477
HZ		 1963
1964 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
1965 gfx_v9_0_enable_cp_power_gating(adev, true);
1966 else
1967 gfx_v9_0_enable_cp_power_gating(adev, false);
91d3130a 1968 }
6bce4667
HZ		 1969 }
1970}
1971
b1023571
KW		 1972void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1973{
b08796ce 1974 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
b1023571 1975 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
b1023571
KW		 1976 gfx_v9_0_wait_for_rlc_serdes(adev);
1977}
1978
1979static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1980{
596c8e8b 1981 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 1982 udelay(50);
596c8e8b 1983 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 1984 udelay(50);
1985}
1986
1987static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1988{
1989#ifdef AMDGPU_RLC_DEBUG_RETRY
1990 u32 rlc_ucode_ver;
1991#endif
b1023571 1992
342cda25 1993 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 1994
1995 /* carrizo do enable cp interrupt after cp inited */
1996 if (!(adev->flags & AMD_IS_APU))
1997 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1998
1999 udelay(50);
2000
2001#ifdef AMDGPU_RLC_DEBUG_RETRY
2002 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 2003 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 2004 if(rlc_ucode_ver == 0x108) {
2005 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2006 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2007 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2008 * default is 0x9C4 to create a 100us interval */
5e78835a 2009 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571 2010 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
eaa05d52 2011 * to disable the page fault retry interrupts, default is
b1023571 2012 * 0x100 (256) */
5e78835a 2013 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 2014 }
2015#endif
2016}
2017
2018static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2019{
2020 const struct rlc_firmware_header_v2_0 *hdr;
2021 const __le32 *fw_data;
2022 unsigned i, fw_size;
2023
2024 if (!adev->gfx.rlc_fw)
2025 return -EINVAL;
2026
2027 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2028 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2029
2030 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2031 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2032 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2033
5e78835a 2034 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 2035 RLCG_UCODE_LOADING_START_ADDRESS);
2036 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2037 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2038 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 2039
2040 return 0;
2041}
2042
2043static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2044{
2045 int r;
2046
cfee05bc
ML		 2047 if (amdgpu_sriov_vf(adev))
2048 return 0;
2049
b1023571
KW		 2050 gfx_v9_0_rlc_stop(adev);
2051
2052 /* disable CG */
5e78835a 2053 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 2054
2055 /* disable PG */
5e78835a 2056 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 2057
2058 gfx_v9_0_rlc_reset(adev);
2059
6bce4667
HZ		 2060 gfx_v9_0_init_pg(adev);
2061
b1023571
KW		 2062 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2063 /* legacy rlc firmware loading */
2064 r = gfx_v9_0_rlc_load_microcode(adev);
2065 if (r)
2066 return r;
2067 }
2068
e8835e0e
HZ		 2069 if (adev->asic_type == CHIP_RAVEN) {
2070 if (amdgpu_lbpw != 0)
2071 gfx_v9_0_enable_lbpw(adev, true);
2072 else
2073 gfx_v9_0_enable_lbpw(adev, false);
2074 }
2075
b1023571
KW		 2076 gfx_v9_0_rlc_start(adev);
2077
2078 return 0;
2079}
2080
2081static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2082{
2083 int i;
5e78835a 2084 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 2085
ea64468e
TSD		 2086 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2087 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2088 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2089 if (!enable) {
b1023571
KW		 2090 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2091 adev->gfx.gfx_ring[i].ready = false;
2092 }
5e78835a 2093 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 2094 udelay(50);
2095}
2096
2097static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2098{
2099 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2100 const struct gfx_firmware_header_v1_0 *ce_hdr;
2101 const struct gfx_firmware_header_v1_0 *me_hdr;
2102 const __le32 *fw_data;
2103 unsigned i, fw_size;
2104
2105 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2106 return -EINVAL;
2107
2108 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2109 adev->gfx.pfp_fw->data;
2110 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2111 adev->gfx.ce_fw->data;
2112 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2113 adev->gfx.me_fw->data;
2114
2115 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2116 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2117 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2118
2119 gfx_v9_0_cp_gfx_enable(adev, false);
2120
2121 /* PFP */
2122 fw_data = (const __le32 *)
2123 (adev->gfx.pfp_fw->data +
2124 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2125 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 2126 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 2127 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2128 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2129 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 2130
2131 /* CE */
2132 fw_data = (const __le32 *)
2133 (adev->gfx.ce_fw->data +
2134 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2135 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 2136 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 2137 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2138 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2139 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 2140
2141 /* ME */
2142 fw_data = (const __le32 *)
2143 (adev->gfx.me_fw->data +
2144 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2145 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 2146 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 2147 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2148 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2149 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 2150
2151 return 0;
2152}
2153
b1023571
KW		 2154static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2155{
2156 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2157 const struct cs_section_def *sect = NULL;
2158 const struct cs_extent_def *ext = NULL;
d5de797f 2159 int r, i, tmp;
b1023571
KW		 2160
2161 /* init the CP */
5e78835a
TSD		 2162 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2163 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 2164
2165 gfx_v9_0_cp_gfx_enable(adev, true);
2166
d5de797f 2167 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
b1023571
KW		 2168 if (r) {
2169 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2170 return r;
2171 }
2172
2173 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2174 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2175
2176 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2177 amdgpu_ring_write(ring, 0x80000000);
2178 amdgpu_ring_write(ring, 0x80000000);
2179
2180 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2181 for (ext = sect->section; ext->extent != NULL; ++ext) {
2182 if (sect->id == SECT_CONTEXT) {
2183 amdgpu_ring_write(ring,
2184 PACKET3(PACKET3_SET_CONTEXT_REG,
2185 ext->reg_count));
2186 amdgpu_ring_write(ring,
2187 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2188 for (i = 0; i < ext->reg_count; i++)
2189 amdgpu_ring_write(ring, ext->extent[i]);
2190 }
2191 }
2192 }
2193
2194 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2195 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2196
2197 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2198 amdgpu_ring_write(ring, 0);
2199
2200 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2201 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2202 amdgpu_ring_write(ring, 0x8000);
2203 amdgpu_ring_write(ring, 0x8000);
2204
d5de797f
KW		 2205 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2206 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2207 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2208 amdgpu_ring_write(ring, tmp);
2209 amdgpu_ring_write(ring, 0);
2210
b1023571
KW		 2211 amdgpu_ring_commit(ring);
2212
2213 return 0;
2214}
2215
2216static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2217{
2218 struct amdgpu_ring *ring;
2219 u32 tmp;
2220 u32 rb_bufsz;
3fc08b61 2221 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 2222
2223 /* Set the write pointer delay */
5e78835a 2224 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 2225
2226 /* set the RB to use vmid 0 */
5e78835a 2227 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 2228
2229 /* Set ring buffer size */
2230 ring = &adev->gfx.gfx_ring[0];
2231 rb_bufsz = order_base_2(ring->ring_size / 8);
2232 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2233 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2234#ifdef __BIG_ENDIAN
2235 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2236#endif
5e78835a 2237 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2238
2239 /* Initialize the ring buffer's write pointers */
2240 ring->wptr = 0;
5e78835a
TSD		 2241 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2242 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2243
2244 /* set the wb address wether it's enabled or not */
2245 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 2246 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2247 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 2248
3fc08b61 2249 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 2250 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2251 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 2252
b1023571 2253 mdelay(1);
5e78835a 2254 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2255
2256 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 2257 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2258 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 2259
5e78835a 2260 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 2261 if (ring->use_doorbell) {
2262 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2263 DOORBELL_OFFSET, ring->doorbell_index);
2264 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2265 DOORBELL_EN, 1);
2266 } else {
2267 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2268 }
5e78835a 2269 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 2270
2271 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2272 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 2273 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 2274
5e78835a 2275 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 2276 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2277
2278
2279 /* start the ring */
2280 gfx_v9_0_cp_gfx_start(adev);
2281 ring->ready = true;
2282
2283 return 0;
2284}
2285
2286static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2287{
2288 int i;
2289
2290 if (enable) {
5e78835a 2291 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 2292 } else {
5e78835a 2293 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 2294 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2295 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2296 adev->gfx.compute_ring[i].ready = false;
ac104e99 2297 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 2298 }
2299 udelay(50);
2300}
2301
b1023571
KW		 2302static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2303{
2304 const struct gfx_firmware_header_v1_0 *mec_hdr;
2305 const __le32 *fw_data;
2306 unsigned i;
2307 u32 tmp;
2308
2309 if (!adev->gfx.mec_fw)
2310 return -EINVAL;
2311
2312 gfx_v9_0_cp_compute_enable(adev, false);
2313
2314 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2315 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2316
2317 fw_data = (const __le32 *)
2318 (adev->gfx.mec_fw->data +
2319 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2320 tmp = 0;
2321 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2322 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 2323 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 2324
5e78835a 2325 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 2326 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 2327 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571 2328 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
eaa05d52 2329
b1023571 2330 /* MEC1 */
5e78835a 2331 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2332 mec_hdr->jt_offset);
2333 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 2334 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 2335 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2336
5e78835a 2337 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2338 adev->gfx.mec_fw_version);
2339 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2340
2341 return 0;
2342}
2343
464826d6
XY		 2344/* KIQ functions */
2345static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
b1023571 2346{
464826d6
XY		 2347 uint32_t tmp;
2348 struct amdgpu_device *adev = ring->adev;
b1023571 2349
464826d6 2350 /* tell RLC which is KIQ queue */
5e78835a 2351 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 2352 tmp &= 0xffffff00;
2353 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 2354 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2355 tmp |= 0x80;
5e78835a 2356 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2357}
b1023571 2358
0f1dfd52 2359static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
464826d6 2360{
bd3402ea 2361 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2fdde9fa 2362 uint32_t scratch, tmp = 0;
de65513a 2363 uint64_t queue_mask = 0;
2fdde9fa 2364 int r, i;
b1023571 2365
de65513a
AR		 2366 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2367 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2368 continue;
b1023571 2369
de65513a
AR		 2370 /* This situation may be hit in the future if a new HW
2371 * generation exposes more than 64 queues. If so, the
2372 * definition of queue_mask needs updating */
1d11ee89 2373 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
de65513a
AR		 2374 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2375 break;
b1023571 2376 }
b1023571 2377
de65513a
AR		 2378 queue_mask |= (1ull << i);
2379 }
b1023571 2380
2fdde9fa
AD		 2381 r = amdgpu_gfx_scratch_get(adev, &scratch);
2382 if (r) {
2383 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2384 return r;
b1023571 2385 }
2fdde9fa 2386 WREG32(scratch, 0xCAFEDEAD);
b1023571 2387
0f1dfd52 2388 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2fdde9fa
AD		 2389 if (r) {
2390 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2391 amdgpu_gfx_scratch_free(adev, scratch);
b1023571 2392 return r;
2fdde9fa 2393 }
b1023571 2394
0f1dfd52
AD		 2395 /* set resources */
2396 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2397 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2398 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
de65513a
AR		 2399 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2400 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
0f1dfd52
AD		 2401 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2402 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2403 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2404 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
bd3402ea
AD		 2405 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2406 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2407 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2408 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2409
2410 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2411 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2412 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2413 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2414 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2415 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2416 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2417 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2418 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2419 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2420 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2421 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2422 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2423 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2424 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2425 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2426 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2427 }
2fdde9fa
AD		 2428 /* write to scratch for completion */
2429 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2430 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2431 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
464826d6 2432 amdgpu_ring_commit(kiq_ring);
b1023571 2433
2fdde9fa
AD		 2434 for (i = 0; i < adev->usec_timeout; i++) {
2435 tmp = RREG32(scratch);
2436 if (tmp == 0xDEADBEEF)
2437 break;
2438 DRM_UDELAY(1);
2439 }
2440 if (i >= adev->usec_timeout) {
2441 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2442 scratch, tmp);
2443 r = -EINVAL;
2444 }
2445 amdgpu_gfx_scratch_free(adev, scratch);
464826d6 2446
2fdde9fa 2447 return r;
464826d6
XY		 2448}
2449
e322edc3 2450static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 2451{
33fb8698 2452 struct amdgpu_device *adev = ring->adev;
e322edc3 2453 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2454 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2455 uint32_t tmp;
2456
2457 mqd->header = 0xC0310800;
2458 mqd->compute_pipelinestat_enable = 0x00000001;
2459 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2460 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2461 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2462 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2463 mqd->compute_misc_reserved = 0x00000003;
2464
ffe6d881
AD		 2465 mqd->dynamic_cu_mask_addr_lo =
2466 lower_32_bits(ring->mqd_gpu_addr
2467 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2468 mqd->dynamic_cu_mask_addr_hi =
2469 upper_32_bits(ring->mqd_gpu_addr
2470 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2471
d72f2f46 2472 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 2473 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2474 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2475
2476 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2477 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6 2478 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
268cb4c7 2479 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
464826d6
XY		 2480
2481 mqd->cp_hqd_eop_control = tmp;
2482
2483 /* enable doorbell? */
5e78835a 2484 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2485
2486 if (ring->use_doorbell) {
2487 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2488 DOORBELL_OFFSET, ring->doorbell_index);
2489 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2490 DOORBELL_EN, 1);
2491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2492 DOORBELL_SOURCE, 0);
2493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2494 DOORBELL_HIT, 0);
78888cff 2495 } else {
464826d6
XY		 2496 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2497 DOORBELL_EN, 0);
78888cff 2498 }
464826d6
XY		 2499
2500 mqd->cp_hqd_pq_doorbell_control = tmp;
2501
2502 /* disable the queue if it's active */
2503 ring->wptr = 0;
2504 mqd->cp_hqd_dequeue_request = 0;
2505 mqd->cp_hqd_pq_rptr = 0;
2506 mqd->cp_hqd_pq_wptr_lo = 0;
2507 mqd->cp_hqd_pq_wptr_hi = 0;
2508
2509 /* set the pointer to the MQD */
33fb8698
AD		 2510 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2511 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 2512
2513 /* set MQD vmid to 0 */
5e78835a 2514 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 2515 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2516 mqd->cp_mqd_control = tmp;
2517
2518 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2519 hqd_gpu_addr = ring->gpu_addr >> 8;
2520 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2521 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2522
2523 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2524 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 2525 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2526 (order_base_2(ring->ring_size / 4) - 1));
2527 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2528 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2529#ifdef __BIG_ENDIAN
2530 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2531#endif
2532 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2533 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2535 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2536 mqd->cp_hqd_pq_control = tmp;
2537
2538 /* set the wb address whether it's enabled or not */
2539 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2540 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2541 mqd->cp_hqd_pq_rptr_report_addr_hi =
2542 upper_32_bits(wb_gpu_addr) & 0xffff;
2543
2544 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2545 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2546 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2547 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2548
2549 tmp = 0;
2550 /* enable the doorbell if requested */
2551 if (ring->use_doorbell) {
5e78835a 2552 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2553 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2554 DOORBELL_OFFSET, ring->doorbell_index);
2555
2556 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2557 DOORBELL_EN, 1);
2558 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2559 DOORBELL_SOURCE, 0);
2560 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2561 DOORBELL_HIT, 0);
2562 }
2563
2564 mqd->cp_hqd_pq_doorbell_control = tmp;
2565
2566 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2567 ring->wptr = 0;
0274a9c5 2568 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 2569
2570 /* set the vmid for the queue */
2571 mqd->cp_hqd_vmid = 0;
2572
0274a9c5 2573 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 2574 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2575 mqd->cp_hqd_persistent_state = tmp;
2576
fca4ce69
AD		 2577 /* set MIN_IB_AVAIL_SIZE */
2578 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2579 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2580 mqd->cp_hqd_ib_control = tmp;
2581
464826d6
XY		 2582 /* activate the queue */
2583 mqd->cp_hqd_active = 1;
2584
2585 return 0;
2586}
2587
e322edc3 2588static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2589{
33fb8698 2590 struct amdgpu_device *adev = ring->adev;
e322edc3 2591 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2592 int j;
2593
2594 /* disable wptr polling */
72edadd5 2595 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2596
5e78835a 2597 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2598 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2599 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2600 mqd->cp_hqd_eop_base_addr_hi);
2601
2602 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2603 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2604 mqd->cp_hqd_eop_control);
2605
2606 /* enable doorbell? */
5e78835a 2607 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2608 mqd->cp_hqd_pq_doorbell_control);
2609
2610 /* disable the queue if it's active */
5e78835a
TSD		 2611 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2612 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2613 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2614 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2615 break;
2616 udelay(1);
2617 }
5e78835a 2618 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2619 mqd->cp_hqd_dequeue_request);
5e78835a 2620 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2621 mqd->cp_hqd_pq_rptr);
5e78835a 2622 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2623 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2624 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2625 mqd->cp_hqd_pq_wptr_hi);
2626 }
2627
2628 /* set the pointer to the MQD */
5e78835a 2629 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2630 mqd->cp_mqd_base_addr_lo);
5e78835a 2631 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2632 mqd->cp_mqd_base_addr_hi);
2633
2634 /* set MQD vmid to 0 */
5e78835a 2635 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2636 mqd->cp_mqd_control);
2637
2638 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2639 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2640 mqd->cp_hqd_pq_base_lo);
5e78835a 2641 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2642 mqd->cp_hqd_pq_base_hi);
2643
2644 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2645 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2646 mqd->cp_hqd_pq_control);
2647
2648 /* set the wb address whether it's enabled or not */
5e78835a 2649 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2650 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2651 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2652 mqd->cp_hqd_pq_rptr_report_addr_hi);
2653
2654 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2655 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2656 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2657 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2658 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2659
2660 /* enable the doorbell if requested */
2661 if (ring->use_doorbell) {
5e78835a 2662 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2663 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2664 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2665 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2666 }
2667
5e78835a 2668 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2669 mqd->cp_hqd_pq_doorbell_control);
2670
2671 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2672 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2673 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2674 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2675 mqd->cp_hqd_pq_wptr_hi);
2676
2677 /* set the vmid for the queue */
5e78835a 2678 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2679
5e78835a 2680 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2681 mqd->cp_hqd_persistent_state);
2682
2683 /* activate the queue */
5e78835a 2684 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2685 mqd->cp_hqd_active);
2686
72edadd5
TSD		 2687 if (ring->use_doorbell)
2688 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2689
2690 return 0;
2691}
2692
e322edc3 2693static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2694{
2695 struct amdgpu_device *adev = ring->adev;
e322edc3 2696 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2697 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2698
898b7893 2699 gfx_v9_0_kiq_setting(ring);
464826d6 2700
3224a12b 2701 if (adev->in_sriov_reset) { /* for GPU_RESET case */
464826d6 2702 /* reset MQD to a clean status */
0ef376ca 2703 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2704 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2705
2706 /* reset ring buffer */
2707 ring->wptr = 0;
b98724db 2708 amdgpu_ring_clear_ring(ring);
464826d6 2709
898b7893
AD		 2710 mutex_lock(&adev->srbm_mutex);
2711 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2712 gfx_v9_0_kiq_init_register(ring);
2713 soc15_grbm_select(adev, 0, 0, 0, 0);
2714 mutex_unlock(&adev->srbm_mutex);
464826d6 2715 } else {
ffe6d881
AD		 2716 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2717 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2718 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
ba0c19f5
AD		 2719 mutex_lock(&adev->srbm_mutex);
2720 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2721 gfx_v9_0_mqd_init(ring);
2722 gfx_v9_0_kiq_init_register(ring);
2723 soc15_grbm_select(adev, 0, 0, 0, 0);
2724 mutex_unlock(&adev->srbm_mutex);
2725
2726 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2727 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
464826d6
XY		 2728 }
2729
0f1dfd52 2730 return 0;
898b7893
AD		 2731}
2732
2733static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2734{
2735 struct amdgpu_device *adev = ring->adev;
898b7893
AD		 2736 struct v9_mqd *mqd = ring->mqd_ptr;
2737 int mqd_idx = ring - &adev->gfx.compute_ring[0];
898b7893 2738
3224a12b 2739 if (!adev->in_sriov_reset && !adev->gfx.in_suspend) {
ffe6d881
AD		 2740 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2741 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2742 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
464826d6
XY		 2743 mutex_lock(&adev->srbm_mutex);
2744 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2745 gfx_v9_0_mqd_init(ring);
464826d6
XY		 2746 soc15_grbm_select(adev, 0, 0, 0, 0);
2747 mutex_unlock(&adev->srbm_mutex);
2748
898b7893 2749 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2750 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3224a12b 2751 } else if (adev->in_sriov_reset) { /* for GPU_RESET case */
464826d6 2752 /* reset MQD to a clean status */
898b7893 2753 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2754 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2755
2756 /* reset ring buffer */
2757 ring->wptr = 0;
898b7893 2758 amdgpu_ring_clear_ring(ring);
ba0c19f5
AD		 2759 } else {
2760 amdgpu_ring_clear_ring(ring);
464826d6
XY		 2761 }
2762
464826d6
XY		 2763 return 0;
2764}
2765
2766static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2767{
2768 struct amdgpu_ring *ring = NULL;
2769 int r = 0, i;
2770
2771 gfx_v9_0_cp_compute_enable(adev, true);
2772
2773 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2774
2775 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2776 if (unlikely(r != 0))
2777 goto done;
2778
2779 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2780 if (!r) {
e322edc3 2781 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2782 amdgpu_bo_kunmap(ring->mqd_obj);
2783 ring->mqd_ptr = NULL;
464826d6 2784 }
e1d53aa8
AD		 2785 amdgpu_bo_unreserve(ring->mqd_obj);
2786 if (r)
2787 goto done;
464826d6
XY		 2788
2789 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2790 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2791
2792 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2793 if (unlikely(r != 0))
2794 goto done;
2795 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2796 if (!r) {
898b7893 2797 r = gfx_v9_0_kcq_init_queue(ring);
464826d6
XY		 2798 amdgpu_bo_kunmap(ring->mqd_obj);
2799 ring->mqd_ptr = NULL;
464826d6 2800 }
e1d53aa8
AD		 2801 amdgpu_bo_unreserve(ring->mqd_obj);
2802 if (r)
2803 goto done;
464826d6
XY		 2804 }
2805
0f1dfd52 2806 r = gfx_v9_0_kiq_kcq_enable(adev);
e1d53aa8
AD		 2807done:
2808 return r;
464826d6
XY		 2809}
2810
b1023571
KW		 2811static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2812{
bd3402ea 2813 int r, i;
b1023571
KW		 2814 struct amdgpu_ring *ring;
2815
2816 if (!(adev->flags & AMD_IS_APU))
2817 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2818
2819 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2820 /* legacy firmware loading */
2821 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2822 if (r)
2823 return r;
2824
2825 r = gfx_v9_0_cp_compute_load_microcode(adev);
2826 if (r)
2827 return r;
2828 }
2829
2830 r = gfx_v9_0_cp_gfx_resume(adev);
2831 if (r)
2832 return r;
2833
e30a5223 2834 r = gfx_v9_0_kiq_resume(adev);
b1023571
KW		 2835 if (r)
2836 return r;
2837
2838 ring = &adev->gfx.gfx_ring[0];
2839 r = amdgpu_ring_test_ring(ring);
2840 if (r) {
2841 ring->ready = false;
2842 return r;
2843 }
e30a5223
AD		 2844
2845 ring = &adev->gfx.kiq.ring;
2846 ring->ready = true;
2847 r = amdgpu_ring_test_ring(ring);
2848 if (r)
2849 ring->ready = false;
2850
b1023571
KW		 2851 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2852 ring = &adev->gfx.compute_ring[i];
2853
2854 ring->ready = true;
2855 r = amdgpu_ring_test_ring(ring);
2856 if (r)
2857 ring->ready = false;
2858 }
2859
2860 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2861
2862 return 0;
2863}
2864
2865static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2866{
2867 gfx_v9_0_cp_gfx_enable(adev, enable);
2868 gfx_v9_0_cp_compute_enable(adev, enable);
2869}
2870
2871static int gfx_v9_0_hw_init(void *handle)
2872{
2873 int r;
2874 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2875
2876 gfx_v9_0_init_golden_registers(adev);
2877
2878 gfx_v9_0_gpu_init(adev);
2879
2880 r = gfx_v9_0_rlc_resume(adev);
2881 if (r)
2882 return r;
2883
2884 r = gfx_v9_0_cp_resume(adev);
2885 if (r)
2886 return r;
2887
2888 r = gfx_v9_0_ngg_en(adev);
2889 if (r)
2890 return r;
2891
2892 return r;
2893}
2894
2895static int gfx_v9_0_hw_fini(void *handle)
2896{
2897 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2898
2899 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2900 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
464826d6
XY		 2901 if (amdgpu_sriov_vf(adev)) {
2902 pr_debug("For SRIOV client, shouldn't do anything.\n");
2903 return 0;
2904 }
b1023571
KW		 2905 gfx_v9_0_cp_enable(adev, false);
2906 gfx_v9_0_rlc_stop(adev);
b1023571
KW		 2907
2908 return 0;
2909}
2910
2911static int gfx_v9_0_suspend(void *handle)
2912{
2913 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2914
e30a5223 2915 adev->gfx.in_suspend = true;
b1023571
KW		 2916 return gfx_v9_0_hw_fini(adev);
2917}
2918
2919static int gfx_v9_0_resume(void *handle)
2920{
2921 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e30a5223 2922 int r;
b1023571 2923
e30a5223
AD		 2924 r = gfx_v9_0_hw_init(adev);
2925 adev->gfx.in_suspend = false;
2926 return r;
b1023571
KW		 2927}
2928
2929static bool gfx_v9_0_is_idle(void *handle)
2930{
2931 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2932
5e78835a 2933 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 2934 GRBM_STATUS, GUI_ACTIVE))
2935 return false;
2936 else
2937 return true;
2938}
2939
2940static int gfx_v9_0_wait_for_idle(void *handle)
2941{
2942 unsigned i;
b1023571
KW		 2943 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2944
2945 for (i = 0; i < adev->usec_timeout; i++) {
2b9bdfa7 2946 if (gfx_v9_0_is_idle(handle))
b1023571
KW		 2947 return 0;
2948 udelay(1);
2949 }
2950 return -ETIMEDOUT;
2951}
2952
b1023571
KW		 2953static int gfx_v9_0_soft_reset(void *handle)
2954{
2955 u32 grbm_soft_reset = 0;
2956 u32 tmp;
2957 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2958
2959 /* GRBM_STATUS */
5e78835a 2960 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 2961 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2962 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2963 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2964 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2965 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2966 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2967 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2968 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2969 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2970 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2971 }
2972
2973 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2974 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2975 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2976 }
2977
2978 /* GRBM_STATUS2 */
5e78835a 2979 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 2980 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2981 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2982 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2983
2984
75bac5c6 2985 if (grbm_soft_reset) {
b1023571
KW		 2986 /* stop the rlc */
2987 gfx_v9_0_rlc_stop(adev);
2988
2989 /* Disable GFX parsing/prefetching */
2990 gfx_v9_0_cp_gfx_enable(adev, false);
2991
2992 /* Disable MEC parsing/prefetching */
2993 gfx_v9_0_cp_compute_enable(adev, false);
2994
2995 if (grbm_soft_reset) {
5e78835a 2996 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 2997 tmp |= grbm_soft_reset;
2998 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 2999 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3000 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3001
3002 udelay(50);
3003
3004 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 3005 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3006 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3007 }
3008
3009 /* Wait a little for things to settle down */
3010 udelay(50);
b1023571
KW		 3011 }
3012 return 0;
3013}
3014
3015static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3016{
3017 uint64_t clock;
3018
3019 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 3020 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3021 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3022 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 3023 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3024 return clock;
3025}
3026
3027static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3028 uint32_t vmid,
3029 uint32_t gds_base, uint32_t gds_size,
3030 uint32_t gws_base, uint32_t gws_size,
3031 uint32_t oa_base, uint32_t oa_size)
3032{
3033 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3034 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3035
3036 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3037 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3038
3039 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3040 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3041
3042 /* GDS Base */
3043 gfx_v9_0_write_data_to_reg(ring, 0, false,
3044 amdgpu_gds_reg_offset[vmid].mem_base,
3045 gds_base);
3046
3047 /* GDS Size */
3048 gfx_v9_0_write_data_to_reg(ring, 0, false,
3049 amdgpu_gds_reg_offset[vmid].mem_size,
3050 gds_size);
3051
3052 /* GWS */
3053 gfx_v9_0_write_data_to_reg(ring, 0, false,
3054 amdgpu_gds_reg_offset[vmid].gws,
3055 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3056
3057 /* OA */
3058 gfx_v9_0_write_data_to_reg(ring, 0, false,
3059 amdgpu_gds_reg_offset[vmid].oa,
3060 (1 << (oa_size + oa_base)) - (1 << oa_base));
3061}
3062
3063static int gfx_v9_0_early_init(void *handle)
3064{
3065 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3066
3067 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
78c16834 3068 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
b1023571
KW		 3069 gfx_v9_0_set_ring_funcs(adev);
3070 gfx_v9_0_set_irq_funcs(adev);
3071 gfx_v9_0_set_gds_init(adev);
3072 gfx_v9_0_set_rlc_funcs(adev);
3073
3074 return 0;
3075}
3076
3077static int gfx_v9_0_late_init(void *handle)
3078{
3079 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3080 int r;
3081
3082 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3083 if (r)
3084 return r;
3085
3086 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3087 if (r)
3088 return r;
3089
3090 return 0;
3091}
3092
3093static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3094{
3095 uint32_t rlc_setting, data;
3096 unsigned i;
3097
3098 if (adev->gfx.rlc.in_safe_mode)
3099 return;
3100
3101 /* if RLC is not enabled, do nothing */
5e78835a 3102 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3103 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3104 return;
3105
3106 if (adev->cg_flags &
3107 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3108 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3109 data = RLC_SAFE_MODE__CMD_MASK;
3110 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 3111 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3112
3113 /* wait for RLC_SAFE_MODE */
3114 for (i = 0; i < adev->usec_timeout; i++) {
3115 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3116 break;
3117 udelay(1);
3118 }
3119 adev->gfx.rlc.in_safe_mode = true;
3120 }
3121}
3122
3123static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3124{
3125 uint32_t rlc_setting, data;
3126
3127 if (!adev->gfx.rlc.in_safe_mode)
3128 return;
3129
3130 /* if RLC is not enabled, do nothing */
5e78835a 3131 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3132 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3133 return;
3134
3135 if (adev->cg_flags &
3136 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3137 /*
3138 * Try to exit safe mode only if it is already in safe
3139 * mode.
3140 */
3141 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 3142 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3143 adev->gfx.rlc.in_safe_mode = false;
3144 }
3145}
3146
197f95c8
HZ		 3147static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3148 bool enable)
3149{
3150 /* TODO: double check if we need to perform under safe mdoe */
3151 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3152
3153 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3154 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3155 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3156 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3157 } else {
3158 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3159 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3160 }
3161
3162 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3163}
3164
18924c71
HZ		 3165static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3166 bool enable)
3167{
3168 /* TODO: double check if we need to perform under safe mode */
3169 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3170
3171 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3172 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3173 else
3174 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3175
3176 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3177 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3178 else
3179 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3180
3181 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3182}
3183
b1023571
KW		 3184static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3185 bool enable)
3186{
3187 uint32_t data, def;
3188
3189 /* It is disabled by HW by default */
3190 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3191 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 3192 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3193 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3194 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3195 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3196 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3197
3198 /* only for Vega10 & Raven1 */
3199 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3200
3201 if (def != data)
5e78835a 3202 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3203
3204 /* MGLS is a global flag to control all MGLS in GFX */
3205 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3206 /* 2 - RLC memory Light sleep */
3207 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 3208 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3209 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3210 if (def != data)
5e78835a 3211 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3212 }
3213 /* 3 - CP memory Light sleep */
3214 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 3215 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3216 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3217 if (def != data)
5e78835a 3218 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3219 }
3220 }
3221 } else {
3222 /* 1 - MGCG_OVERRIDE */
5e78835a 3223 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3224 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3225 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3226 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3227 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3228 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3229 if (def != data)
5e78835a 3230 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3231
3232 /* 2 - disable MGLS in RLC */
5e78835a 3233 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3234 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3235 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 3236 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3237 }
3238
3239 /* 3 - disable MGLS in CP */
5e78835a 3240 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3241 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3242 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 3243 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3244 }
3245 }
3246}
3247
3248static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3249 bool enable)
3250{
3251 uint32_t data, def;
3252
3253 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3254
3255 /* Enable 3D CGCG/CGLS */
3256 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3257 /* write cmd to clear cgcg/cgls ov */
5e78835a 3258 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3259 /* unset CGCG override */
3260 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3261 /* update CGCG and CGLS override bits */
3262 if (def != data)
5e78835a 3263 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 3264 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 3265 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3266 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3267 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3268 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3269 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3270 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3271 if (def != data)
5e78835a 3272 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3273
3274 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3275 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3276 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3277 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3278 if (def != data)
5e78835a 3279 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 3280 } else {
3281 /* Disable CGCG/CGLS */
5e78835a 3282 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3283 /* disable cgcg, cgls should be disabled */
3284 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3285 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3286 /* disable cgcg and cgls in FSM */
3287 if (def != data)
5e78835a 3288 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3289 }
3290
3291 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3292}
3293
3294static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3295 bool enable)
3296{
3297 uint32_t def, data;
3298
3299 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3300
3301 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 3302 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3303 /* unset CGCG override */
3304 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3305 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3306 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3307 else
3308 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3309 /* update CGCG and CGLS override bits */
3310 if (def != data)
5e78835a 3311 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3312
3313 /* enable cgcg FSM(0x0020003F) */
5e78835a 3314 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3315 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3316 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3317 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3318 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3319 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3320 if (def != data)
5e78835a 3321 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3322
3323 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3324 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3325 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3326 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3327 if (def != data)
5e78835a 3328 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 3329 } else {
5e78835a 3330 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3331 /* reset CGCG/CGLS bits */
3332 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3333 /* disable cgcg and cgls in FSM */
3334 if (def != data)
5e78835a 3335 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3336 }
3337
3338 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3339}
3340
3341static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3342 bool enable)
3343{
3344 if (enable) {
3345 /* CGCG/CGLS should be enabled after MGCG/MGLS
3346 * === MGCG + MGLS ===
3347 */
3348 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3349 /* === CGCG /CGLS for GFX 3D Only === */
3350 gfx_v9_0_update_3d_clock_gating(adev, enable);
3351 /* === CGCG + CGLS === */
3352 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3353 } else {
3354 /* CGCG/CGLS should be disabled before MGCG/MGLS
3355 * === CGCG + CGLS ===
3356 */
3357 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3358 /* === CGCG /CGLS for GFX 3D Only === */
3359 gfx_v9_0_update_3d_clock_gating(adev, enable);
3360 /* === MGCG + MGLS === */
3361 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3362 }
3363 return 0;
3364}
3365
3366static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3367 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3368 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3369};
3370
3371static int gfx_v9_0_set_powergating_state(void *handle,
3372 enum amd_powergating_state state)
3373{
5897c99e 3374 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197f95c8 3375 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
5897c99e
HZ		 3376
3377 switch (adev->asic_type) {
3378 case CHIP_RAVEN:
3379 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3380 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3381 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3382 } else {
3383 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3384 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3385 }
3386
3387 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3388 gfx_v9_0_enable_cp_power_gating(adev, true);
3389 else
3390 gfx_v9_0_enable_cp_power_gating(adev, false);
197f95c8
HZ		 3391
3392 /* update gfx cgpg state */
3393 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
18924c71
HZ		 3394
3395 /* update mgcg state */
3396 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5897c99e
HZ		 3397 break;
3398 default:
3399 break;
3400 }
3401
b1023571
KW		 3402 return 0;
3403}
3404
3405static int gfx_v9_0_set_clockgating_state(void *handle,
3406 enum amd_clockgating_state state)
3407{
3408 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3409
fb82afab
XY		 3410 if (amdgpu_sriov_vf(adev))
3411 return 0;
3412
b1023571
KW		 3413 switch (adev->asic_type) {
3414 case CHIP_VEGA10:
a4dc61f5 3415 case CHIP_RAVEN:
b1023571
KW		 3416 gfx_v9_0_update_gfx_clock_gating(adev,
3417 state == AMD_CG_STATE_GATE ? true : false);
3418 break;
3419 default:
3420 break;
3421 }
3422 return 0;
3423}
3424
12ad27fa
HR		 3425static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3426{
3427 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3428 int data;
3429
3430 if (amdgpu_sriov_vf(adev))
3431 *flags = 0;
3432
3433 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 3434 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 3435 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3436 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3437
3438 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 3439 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 3440 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3441 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3442
3443 /* AMD_CG_SUPPORT_GFX_CGLS */
3444 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3445 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3446
3447 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 3448 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 3449 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3450 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3451
3452 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 3453 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 3454 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3455 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3456
3457 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 3458 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 3459 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3460 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3461
3462 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3463 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3464 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3465}
3466
b1023571
KW		 3467static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3468{
3469 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3470}
3471
3472static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3473{
3474 struct amdgpu_device *adev = ring->adev;
3475 u64 wptr;
3476
3477 /* XXX check if swapping is necessary on BE */
3478 if (ring->use_doorbell) {
3479 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3480 } else {
5e78835a
TSD		 3481 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3482 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 3483 }
3484
3485 return wptr;
3486}
3487
3488static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3489{
3490 struct amdgpu_device *adev = ring->adev;
3491
3492 if (ring->use_doorbell) {
3493 /* XXX check if swapping is necessary on BE */
3494 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3495 WDOORBELL64(ring->doorbell_index, ring->wptr);
3496 } else {
5e78835a
TSD		 3497 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3498 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 3499 }
3500}
3501
3502static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3503{
3504 u32 ref_and_mask, reg_mem_engine;
3505 struct nbio_hdp_flush_reg *nbio_hf_reg;
3506
29c3035f
AD		 3507 if (ring->adev->flags & AMD_IS_APU)
3508 nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
3509 else
b1023571
KW		 3510 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3511
3512 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3513 switch (ring->me) {
3514 case 1:
3515 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3516 break;
3517 case 2:
3518 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3519 break;
3520 default:
3521 return;
3522 }
3523 reg_mem_engine = 0;
3524 } else {
3525 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3526 reg_mem_engine = 1; /* pfp */
3527 }
3528
3529 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3530 nbio_hf_reg->hdp_flush_req_offset,
3531 nbio_hf_reg->hdp_flush_done_offset,
3532 ref_and_mask, ref_and_mask, 0x20);
3533}
3534
3535static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3536{
3537 gfx_v9_0_write_data_to_reg(ring, 0, true,
3538 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3539}
3540
3541static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3542 struct amdgpu_ib *ib,
3543 unsigned vm_id, bool ctx_switch)
3544{
eaa05d52 3545 u32 header, control = 0;
b1023571 3546
eaa05d52
ML		 3547 if (ib->flags & AMDGPU_IB_FLAG_CE)
3548 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3549 else
3550 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
b1023571 3551
eaa05d52 3552 control |= ib->length_dw | (vm_id << 24);
b1023571 3553
635e7132 3554 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
eaa05d52 3555 control |= INDIRECT_BUFFER_PRE_ENB(1);
9ccd52eb 3556
635e7132
ML		 3557 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3558 gfx_v9_0_ring_emit_de_meta(ring);
3559 }
3560
eaa05d52
ML		 3561 amdgpu_ring_write(ring, header);
3562BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3563 amdgpu_ring_write(ring,
b1023571 3564#ifdef __BIG_ENDIAN
eaa05d52 3565 (2 << 0) |
b1023571 3566#endif
eaa05d52
ML		 3567 lower_32_bits(ib->gpu_addr));
3568 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3569 amdgpu_ring_write(ring, control);
b1023571
KW		 3570}
3571
b1023571
KW		 3572static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3573 struct amdgpu_ib *ib,
3574 unsigned vm_id, bool ctx_switch)
3575{
3576 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3577
3578 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3579 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3580 amdgpu_ring_write(ring,
3581#ifdef __BIG_ENDIAN
3582 (2 << 0) |
3583#endif
3584 lower_32_bits(ib->gpu_addr));
3585 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3586 amdgpu_ring_write(ring, control);
3587}
3588
3589static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3590 u64 seq, unsigned flags)
3591{
3592 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3593 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3594
3595 /* RELEASE_MEM - flush caches, send int */
3596 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3597 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3598 EOP_TC_ACTION_EN |
3599 EOP_TC_WB_ACTION_EN |
3600 EOP_TC_MD_ACTION_EN |
3601 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3602 EVENT_INDEX(5)));
3603 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3604
3605 /*
3606 * the address should be Qword aligned if 64bit write, Dword
3607 * aligned if only send 32bit data low (discard data high)
3608 */
3609 if (write64bit)
3610 BUG_ON(addr & 0x7);
3611 else
3612 BUG_ON(addr & 0x3);
3613 amdgpu_ring_write(ring, lower_32_bits(addr));
3614 amdgpu_ring_write(ring, upper_32_bits(addr));
3615 amdgpu_ring_write(ring, lower_32_bits(seq));
3616 amdgpu_ring_write(ring, upper_32_bits(seq));
3617 amdgpu_ring_write(ring, 0);
3618}
3619
3620static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3621{
3622 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3623 uint32_t seq = ring->fence_drv.sync_seq;
3624 uint64_t addr = ring->fence_drv.gpu_addr;
3625
3626 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3627 lower_32_bits(addr), upper_32_bits(addr),
3628 seq, 0xffffffff, 4);
3629}
3630
3631static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3632 unsigned vm_id, uint64_t pd_addr)
3633{
2e819849 3634 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
b1023571 3635 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 3636 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 3637 unsigned eng = ring->vm_inv_eng;
b1023571 3638
b1166325
CK		 3639 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3640 pd_addr |= AMDGPU_PTE_VALID;
b1023571 3641
2e819849
CK		 3642 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3643 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3644 lower_32_bits(pd_addr));
b1023571 3645
2e819849
CK		 3646 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3647 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3648 upper_32_bits(pd_addr));
b1023571 3649
2e819849
CK		 3650 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3651 hub->vm_inv_eng0_req + eng, req);
b1023571 3652
2e819849
CK		 3653 /* wait for the invalidate to complete */
3654 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3655 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
b1023571
KW		 3656
3657 /* compute doesn't have PFP */
3658 if (usepfp) {
3659 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3660 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3661 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3662 }
3663}
3664
3665static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3666{
3667 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3668}
3669
3670static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3671{
3672 u64 wptr;
3673
3674 /* XXX check if swapping is necessary on BE */
3675 if (ring->use_doorbell)
3676 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3677 else
3678 BUG();
3679 return wptr;
3680}
3681
3682static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3683{
3684 struct amdgpu_device *adev = ring->adev;
3685
3686 /* XXX check if swapping is necessary on BE */
3687 if (ring->use_doorbell) {
3688 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3689 WDOORBELL64(ring->doorbell_index, ring->wptr);
3690 } else{
3691 BUG(); /* only DOORBELL method supported on gfx9 now */
3692 }
3693}
3694
aa6faa44
XY		 3695static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3696 u64 seq, unsigned int flags)
3697{
3698 /* we only allocate 32bit for each seq wb address */
3699 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3700
3701 /* write fence seq to the "addr" */
3702 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3703 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3704 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3705 amdgpu_ring_write(ring, lower_32_bits(addr));
3706 amdgpu_ring_write(ring, upper_32_bits(addr));
3707 amdgpu_ring_write(ring, lower_32_bits(seq));
3708
3709 if (flags & AMDGPU_FENCE_FLAG_INT) {
3710 /* set register to trigger INT */
3711 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3712 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3713 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3714 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3715 amdgpu_ring_write(ring, 0);
3716 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3717 }
3718}
3719
b1023571
KW		 3720static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3721{
3722 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3723 amdgpu_ring_write(ring, 0);
3724}
3725
cca02cd3
XY		 3726static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3727{
3728 static struct v9_ce_ib_state ce_payload = {0};
3729 uint64_t csa_addr;
3730 int cnt;
3731
3732 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3733 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3734
3735 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3736 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3737 WRITE_DATA_DST_SEL(8) |
3738 WR_CONFIRM) |
3739 WRITE_DATA_CACHE_POLICY(0));
3740 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3741 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3742 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3743}
3744
3745static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3746{
3747 static struct v9_de_ib_state de_payload = {0};
3748 uint64_t csa_addr, gds_addr;
3749 int cnt;
3750
3751 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3752 gds_addr = csa_addr + 4096;
3753 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3754 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3755
3756 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3757 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3758 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3759 WRITE_DATA_DST_SEL(8) |
3760 WR_CONFIRM) |
3761 WRITE_DATA_CACHE_POLICY(0));
3762 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3763 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3764 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3765}
3766
2ea6ab27
ML		 3767static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3768{
3769 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3770 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3771}
3772
b1023571
KW		 3773static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3774{
3775 uint32_t dw2 = 0;
3776
cca02cd3
XY		 3777 if (amdgpu_sriov_vf(ring->adev))
3778 gfx_v9_0_ring_emit_ce_meta(ring);
3779
2ea6ab27
ML		 3780 gfx_v9_0_ring_emit_tmz(ring, true);
3781
b1023571
KW		 3782 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3783 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3784 /* set load_global_config & load_global_uconfig */
3785 dw2 |= 0x8001;
3786 /* set load_cs_sh_regs */
3787 dw2 |= 0x01000000;
3788 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3789 dw2 |= 0x10002;
3790
3791 /* set load_ce_ram if preamble presented */
3792 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3793 dw2 |= 0x10000000;
3794 } else {
3795 /* still load_ce_ram if this is the first time preamble presented
3796 * although there is no context switch happens.
3797 */
3798 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3799 dw2 |= 0x10000000;
3800 }
3801
3802 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3803 amdgpu_ring_write(ring, dw2);
3804 amdgpu_ring_write(ring, 0);
3805}
3806
9a5e02b5
ML		 3807static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3808{
3809 unsigned ret;
3810 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3811 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3812 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3813 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3814 ret = ring->wptr & ring->buf_mask;
3815 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3816 return ret;
3817}
3818
3819static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3820{
3821 unsigned cur;
3822 BUG_ON(offset > ring->buf_mask);
3823 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3824
3825 cur = (ring->wptr & ring->buf_mask) - 1;
3826 if (likely(cur > offset))
3827 ring->ring[offset] = cur - offset;
3828 else
3829 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3830}
3831
aa6faa44
XY		 3832static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3833{
3834 struct amdgpu_device *adev = ring->adev;
3835
3836 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3837 amdgpu_ring_write(ring, 0 | /* src: register*/
3838 (5 << 8) | /* dst: memory */
3839 (1 << 20)); /* write confirm */
3840 amdgpu_ring_write(ring, reg);
3841 amdgpu_ring_write(ring, 0);
3842 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3843 adev->virt.reg_val_offs * 4));
3844 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3845 adev->virt.reg_val_offs * 4));
3846}
3847
3848static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3849 uint32_t val)
3850{
3851 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3852 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3853 amdgpu_ring_write(ring, reg);
3854 amdgpu_ring_write(ring, 0);
3855 amdgpu_ring_write(ring, val);
3856}
3857
b1023571
KW		 3858static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3859 enum amdgpu_interrupt_state state)
3860{
b1023571
KW		 3861 switch (state) {
3862 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3863 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 3864 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3865 TIME_STAMP_INT_ENABLE,
3866 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3867 break;
3868 default:
3869 break;
3870 }
3871}
3872
3873static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3874 int me, int pipe,
3875 enum amdgpu_interrupt_state state)
3876{
3877 u32 mec_int_cntl, mec_int_cntl_reg;
3878
3879 /*
d0c55cdf
AD		 3880 * amdgpu controls only the first MEC. That's why this function only
3881 * handles the setting of interrupts for this specific MEC. All other
b1023571
KW		 3882 * pipes' interrupts are set by amdkfd.
3883 */
3884
3885 if (me == 1) {
3886 switch (pipe) {
3887 case 0:
3888 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3889 break;
d0c55cdf
AD		 3890 case 1:
3891 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
3892 break;
3893 case 2:
3894 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
3895 break;
3896 case 3:
3897 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
3898 break;
b1023571
KW		 3899 default:
3900 DRM_DEBUG("invalid pipe %d\n", pipe);
3901 return;
3902 }
3903 } else {
3904 DRM_DEBUG("invalid me %d\n", me);
3905 return;
3906 }
3907
3908 switch (state) {
3909 case AMDGPU_IRQ_STATE_DISABLE:
3910 mec_int_cntl = RREG32(mec_int_cntl_reg);
3911 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3912 TIME_STAMP_INT_ENABLE, 0);
3913 WREG32(mec_int_cntl_reg, mec_int_cntl);
3914 break;
3915 case AMDGPU_IRQ_STATE_ENABLE:
3916 mec_int_cntl = RREG32(mec_int_cntl_reg);
3917 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3918 TIME_STAMP_INT_ENABLE, 1);
3919 WREG32(mec_int_cntl_reg, mec_int_cntl);
3920 break;
3921 default:
3922 break;
3923 }
3924}
3925
3926static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3927 struct amdgpu_irq_src *source,
3928 unsigned type,
3929 enum amdgpu_interrupt_state state)
3930{
b1023571
KW		 3931 switch (state) {
3932 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3933 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 3934 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3935 PRIV_REG_INT_ENABLE,
3936 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3937 break;
3938 default:
3939 break;
3940 }
3941
3942 return 0;
3943}
3944
3945static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3946 struct amdgpu_irq_src *source,
3947 unsigned type,
3948 enum amdgpu_interrupt_state state)
3949{
b1023571
KW		 3950 switch (state) {
3951 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3952 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 3953 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3954 PRIV_INSTR_INT_ENABLE,
3955 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3956 default:
3957 break;
3958 }
3959
3960 return 0;
3961}
3962
3963static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3964 struct amdgpu_irq_src *src,
3965 unsigned type,
3966 enum amdgpu_interrupt_state state)
3967{
3968 switch (type) {
3969 case AMDGPU_CP_IRQ_GFX_EOP:
3970 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
3971 break;
3972 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3973 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
3974 break;
3975 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3976 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
3977 break;
3978 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
3979 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
3980 break;
3981 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
3982 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
3983 break;
3984 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
3985 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
3986 break;
3987 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
3988 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
3989 break;
3990 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
3991 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
3992 break;
3993 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
3994 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
3995 break;
3996 default:
3997 break;
3998 }
3999 return 0;
4000}
4001
4002static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4003 struct amdgpu_irq_src *source,
4004 struct amdgpu_iv_entry *entry)
4005{
4006 int i;
4007 u8 me_id, pipe_id, queue_id;
4008 struct amdgpu_ring *ring;
4009
4010 DRM_DEBUG("IH: CP EOP\n");
4011 me_id = (entry->ring_id & 0x0c) >> 2;
4012 pipe_id = (entry->ring_id & 0x03) >> 0;
4013 queue_id = (entry->ring_id & 0x70) >> 4;
4014
4015 switch (me_id) {
4016 case 0:
4017 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4018 break;
4019 case 1:
4020 case 2:
4021 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4022 ring = &adev->gfx.compute_ring[i];
4023 /* Per-queue interrupt is supported for MEC starting from VI.
4024 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4025 */
4026 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4027 amdgpu_fence_process(ring);
4028 }
4029 break;
4030 }
4031 return 0;
4032}
4033
4034static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4035 struct amdgpu_irq_src *source,
4036 struct amdgpu_iv_entry *entry)
4037{
4038 DRM_ERROR("Illegal register access in command stream\n");
4039 schedule_work(&adev->reset_work);
4040 return 0;
4041}
4042
4043static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4044 struct amdgpu_irq_src *source,
4045 struct amdgpu_iv_entry *entry)
4046{
4047 DRM_ERROR("Illegal instruction in command stream\n");
4048 schedule_work(&adev->reset_work);
4049 return 0;
4050}
4051
97031e25
XY		 4052static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4053 struct amdgpu_irq_src *src,
4054 unsigned int type,
4055 enum amdgpu_interrupt_state state)
4056{
4057 uint32_t tmp, target;
1c4ecf48 4058 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4059
4060 if (ring->me == 1)
4061 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4062 else
4063 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4064 target += ring->pipe;
4065
4066 switch (type) {
4067 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4068 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 4069 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4070 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4071 GENERIC2_INT_ENABLE, 0);
5e78835a 4072 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4073
4074 tmp = RREG32(target);
4075 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4076 GENERIC2_INT_ENABLE, 0);
4077 WREG32(target, tmp);
4078 } else {
5e78835a 4079 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4080 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4081 GENERIC2_INT_ENABLE, 1);
5e78835a 4082 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4083
4084 tmp = RREG32(target);
4085 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4086 GENERIC2_INT_ENABLE, 1);
4087 WREG32(target, tmp);
4088 }
4089 break;
4090 default:
4091 BUG(); /* kiq only support GENERIC2_INT now */
4092 break;
4093 }
4094 return 0;
4095}
4096
4097static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4098 struct amdgpu_irq_src *source,
4099 struct amdgpu_iv_entry *entry)
4100{
4101 u8 me_id, pipe_id, queue_id;
1c4ecf48 4102 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4103
4104 me_id = (entry->ring_id & 0x0c) >> 2;
4105 pipe_id = (entry->ring_id & 0x03) >> 0;
4106 queue_id = (entry->ring_id & 0x70) >> 4;
4107 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4108 me_id, pipe_id, queue_id);
4109
4110 amdgpu_fence_process(ring);
4111 return 0;
4112}
4113
fa04b6ba 4114static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
b1023571
KW		 4115 .name = "gfx_v9_0",
4116 .early_init = gfx_v9_0_early_init,
4117 .late_init = gfx_v9_0_late_init,
4118 .sw_init = gfx_v9_0_sw_init,
4119 .sw_fini = gfx_v9_0_sw_fini,
4120 .hw_init = gfx_v9_0_hw_init,
4121 .hw_fini = gfx_v9_0_hw_fini,
4122 .suspend = gfx_v9_0_suspend,
4123 .resume = gfx_v9_0_resume,
4124 .is_idle = gfx_v9_0_is_idle,
4125 .wait_for_idle = gfx_v9_0_wait_for_idle,
4126 .soft_reset = gfx_v9_0_soft_reset,
4127 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4128 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 4129 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 4130};
4131
4132static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4133 .type = AMDGPU_RING_TYPE_GFX,
4134 .align_mask = 0xff,
4135 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4136 .support_64bit_ptrs = true,
0eeb68b3 4137 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4138 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4139 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4140 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 4141 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4142 5 + /* COND_EXEC */
4143 7 + /* PIPELINE_SYNC */
2e819849 4144 24 + /* VM_FLUSH */
e9d672b2
ML		 4145 8 + /* FENCE for VM_FLUSH */
4146 20 + /* GDS switch */
4147 4 + /* double SWITCH_BUFFER,
4148 the first COND_EXEC jump to the place just
4149 prior to this double SWITCH_BUFFER */
4150 5 + /* COND_EXEC */
4151 7 + /* HDP_flush */
4152 4 + /* VGT_flush */
4153 14 + /* CE_META */
4154 31 + /* DE_META */
4155 3 + /* CNTX_CTRL */
4156 5 + /* HDP_INVL */
4157 8 + 8 + /* FENCE x2 */
4158 2, /* SWITCH_BUFFER */
b1023571
KW		 4159 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4160 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4161 .emit_fence = gfx_v9_0_ring_emit_fence,
4162 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4163 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4164 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4165 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4166 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4167 .test_ring = gfx_v9_0_ring_test_ring,
4168 .test_ib = gfx_v9_0_ring_test_ib,
4169 .insert_nop = amdgpu_ring_insert_nop,
4170 .pad_ib = amdgpu_ring_generic_pad_ib,
4171 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4172 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 4173 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4174 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3b4d68e9 4175 .emit_tmz = gfx_v9_0_ring_emit_tmz,
b1023571
KW		 4176};
4177
4178static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4179 .type = AMDGPU_RING_TYPE_COMPUTE,
4180 .align_mask = 0xff,
4181 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4182 .support_64bit_ptrs = true,
0eeb68b3 4183 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4184 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4185 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4186 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4187 .emit_frame_size =
4188 20 + /* gfx_v9_0_ring_emit_gds_switch */
4189 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4190 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4191 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4192 24 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 4193 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4194 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4195 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4196 .emit_fence = gfx_v9_0_ring_emit_fence,
4197 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4198 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4199 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4200 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4201 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4202 .test_ring = gfx_v9_0_ring_test_ring,
4203 .test_ib = gfx_v9_0_ring_test_ib,
4204 .insert_nop = amdgpu_ring_insert_nop,
4205 .pad_ib = amdgpu_ring_generic_pad_ib,
4206};
4207
aa6faa44
XY		 4208static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4209 .type = AMDGPU_RING_TYPE_KIQ,
4210 .align_mask = 0xff,
4211 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4212 .support_64bit_ptrs = true,
0eeb68b3 4213 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 4214 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4215 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4216 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4217 .emit_frame_size =
4218 20 + /* gfx_v9_0_ring_emit_gds_switch */
4219 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4220 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4221 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4222 24 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 4223 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4224 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4225 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4226 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 4227 .test_ring = gfx_v9_0_ring_test_ring,
4228 .test_ib = gfx_v9_0_ring_test_ib,
4229 .insert_nop = amdgpu_ring_insert_nop,
4230 .pad_ib = amdgpu_ring_generic_pad_ib,
4231 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4232 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4233};
b1023571
KW		 4234
4235static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4236{
4237 int i;
4238
aa6faa44
XY		 4239 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4240
b1023571
KW		 4241 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4242 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4243
4244 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4245 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4246}
4247
97031e25
XY		 4248static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4249 .set = gfx_v9_0_kiq_set_interrupt_state,
4250 .process = gfx_v9_0_kiq_irq,
4251};
4252
b1023571
KW		 4253static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4254 .set = gfx_v9_0_set_eop_interrupt_state,
4255 .process = gfx_v9_0_eop_irq,
4256};
4257
4258static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4259 .set = gfx_v9_0_set_priv_reg_fault_state,
4260 .process = gfx_v9_0_priv_reg_irq,
4261};
4262
4263static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4264 .set = gfx_v9_0_set_priv_inst_fault_state,
4265 .process = gfx_v9_0_priv_inst_irq,
4266};
4267
4268static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4269{
4270 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4271 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4272
4273 adev->gfx.priv_reg_irq.num_types = 1;
4274 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4275
4276 adev->gfx.priv_inst_irq.num_types = 1;
4277 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 4278
4279 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4280 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 4281}
4282
4283static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4284{
4285 switch (adev->asic_type) {
4286 case CHIP_VEGA10:
a4dc61f5 4287 case CHIP_RAVEN:
b1023571
KW		 4288 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4289 break;
4290 default:
4291 break;
4292 }
4293}
4294
4295static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4296{
4297 /* init asci gds info */
5e78835a 4298 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 4299 adev->gds.gws.total_size = 64;
4300 adev->gds.oa.total_size = 16;
4301
4302 if (adev->gds.mem.total_size == 64 * 1024) {
4303 adev->gds.mem.gfx_partition_size = 4096;
4304 adev->gds.mem.cs_partition_size = 4096;
4305
4306 adev->gds.gws.gfx_partition_size = 4;
4307 adev->gds.gws.cs_partition_size = 4;
4308
4309 adev->gds.oa.gfx_partition_size = 4;
4310 adev->gds.oa.cs_partition_size = 1;
4311 } else {
4312 adev->gds.mem.gfx_partition_size = 1024;
4313 adev->gds.mem.cs_partition_size = 1024;
4314
4315 adev->gds.gws.gfx_partition_size = 16;
4316 adev->gds.gws.cs_partition_size = 16;
4317
4318 adev->gds.oa.gfx_partition_size = 4;
4319 adev->gds.oa.cs_partition_size = 4;
4320 }
4321}
4322
c94d38f0
NH		 4323static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4324 u32 bitmap)
4325{
4326 u32 data;
4327
4328 if (!bitmap)
4329 return;
4330
4331 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4332 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4333
4334 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4335}
4336
b1023571
KW		 4337static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4338{
4339 u32 data, mask;
4340
5e78835a
TSD		 4341 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4342 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 4343
4344 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4345 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4346
378506a7 4347 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
b1023571
KW		 4348
4349 return (~data) & mask;
4350}
4351
4352static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4353 struct amdgpu_cu_info *cu_info)
4354{
4355 int i, j, k, counter, active_cu_number = 0;
4356 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
c94d38f0 4357 unsigned disable_masks[4 * 2];
b1023571
KW		 4358
4359 if (!adev || !cu_info)
4360 return -EINVAL;
4361
c94d38f0
NH		 4362 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4363
b1023571
KW		 4364 mutex_lock(&adev->grbm_idx_mutex);
4365 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4366 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4367 mask = 1;
4368 ao_bitmap = 0;
4369 counter = 0;
4370 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
c94d38f0
NH		 4371 if (i < 4 && j < 2)
4372 gfx_v9_0_set_user_cu_inactive_bitmap(
4373 adev, disable_masks[i * 2 + j]);
b1023571
KW		 4374 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4375 cu_info->bitmap[i][j] = bitmap;
4376
fe723cd3 4377 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
b1023571 4378 if (bitmap & mask) {
fe723cd3 4379 if (counter < adev->gfx.config.max_cu_per_sh)
b1023571
KW		 4380 ao_bitmap |= mask;
4381 counter ++;
4382 }
4383 mask <<= 1;
4384 }
4385 active_cu_number += counter;
dbfe85ea
FC		 4386 if (i < 2 && j < 2)
4387 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4388 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
b1023571
KW		 4389 }
4390 }
4391 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4392 mutex_unlock(&adev->grbm_idx_mutex);
4393
4394 cu_info->number = active_cu_number;
4395 cu_info->ao_cu_mask = ao_cu_mask;
4396
4397 return 0;
4398}
4399
b1023571
KW		 4400const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4401{
4402 .type = AMD_IP_BLOCK_TYPE_GFX,
4403 .major = 9,
4404 .minor = 0,
4405 .rev = 0,
4406 .funcs = &gfx_v9_0_ip_funcs,
4407};
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