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drm/amd/amdgpu: Rename KIQ ring to avoid spaces
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
268cb4c7 41#define GFX9_MEC_HPD_SIZE 2048
6bce4667
HZ		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
b1023571 45
91d3130a
HZ		 46#define mmPWR_MISC_CNTL_STATUS 0x0183
47#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
52
b1023571
KW		 53MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
060d124b
CZ		 60MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62MODULE_FIRMWARE("amdgpu/raven_me.bin");
63MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
b1023571
KW		 67static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
68{
69 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
71 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
73 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
75 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
77 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
79 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
81 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
83 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
85 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
86 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
87 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
88 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
89 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
90 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
91 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
92 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
93 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
94 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
95 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
96 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
97 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
98 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
99 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
100 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
101};
102
103static const u32 golden_settings_gc_9_0[] =
104{
f8af9332
KW		 105 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
106 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
107 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
108 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
109 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
110 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
b1023571
KW		 111 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
112 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
113 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
f8af9332
KW		 114 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
115 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
116 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
117 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
118 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
119 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
b1023571
KW		 120 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
121 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
122 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
f8af9332
KW		 123 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
124 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
125 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
b1023571
KW		 126};
127
128static const u32 golden_settings_gc_9_0_vg10[] =
129{
130 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
131 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
132 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
133 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
134 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
135 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
f8af9332 136 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
b1023571
KW		 137};
138
a5fdb336
CZ		 139static const u32 golden_settings_gc_9_1[] =
140{
141 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
01b5cc36
HZ		 142 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
143 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
144 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 145 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
146 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
01b5cc36 147 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 148 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
149 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
150 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
01b5cc36
HZ		 151 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
152 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
153 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
154 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
155 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 156 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
157 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
158 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
01b5cc36
HZ		 159 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
160 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
161 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
a5fdb336
CZ		 162};
163
164static const u32 golden_settings_gc_9_1_rv1[] =
165{
7b6ba9ea
HZ		 166 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
167 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
168 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
169 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
170 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
171 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
a5fdb336
CZ		 172 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
173};
b1023571 174
5cf7433d 175#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
7b6ba9ea 176#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
5cf7433d 177
b1023571
KW		 178static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
179static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
180static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
181static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
182static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
183 struct amdgpu_cu_info *cu_info);
184static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
185static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
635e7132 186static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
b1023571
KW		 187
188static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
189{
190 switch (adev->asic_type) {
191 case CHIP_VEGA10:
192 amdgpu_program_register_sequence(adev,
193 golden_settings_gc_9_0,
194 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
195 amdgpu_program_register_sequence(adev,
196 golden_settings_gc_9_0_vg10,
197 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
198 break;
a5fdb336
CZ		 199 case CHIP_RAVEN:
200 amdgpu_program_register_sequence(adev,
201 golden_settings_gc_9_1,
202 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
203 amdgpu_program_register_sequence(adev,
204 golden_settings_gc_9_1_rv1,
205 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
206 break;
b1023571
KW		 207 default:
208 break;
209 }
210}
211
212static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
213{
214 adev->gfx.scratch.num_reg = 7;
215 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
216 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
217}
218
219static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
220 bool wc, uint32_t reg, uint32_t val)
221{
222 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
223 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
224 WRITE_DATA_DST_SEL(0) |
225 (wc ? WR_CONFIRM : 0));
226 amdgpu_ring_write(ring, reg);
227 amdgpu_ring_write(ring, 0);
228 amdgpu_ring_write(ring, val);
229}
230
231static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
232 int mem_space, int opt, uint32_t addr0,
233 uint32_t addr1, uint32_t ref, uint32_t mask,
234 uint32_t inv)
235{
236 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
237 amdgpu_ring_write(ring,
238 /* memory (1) or register (0) */
239 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
240 WAIT_REG_MEM_OPERATION(opt) | /* wait */
241 WAIT_REG_MEM_FUNCTION(3) | /* equal */
242 WAIT_REG_MEM_ENGINE(eng_sel)));
243
244 if (mem_space)
245 BUG_ON(addr0 & 0x3); /* Dword align */
246 amdgpu_ring_write(ring, addr0);
247 amdgpu_ring_write(ring, addr1);
248 amdgpu_ring_write(ring, ref);
249 amdgpu_ring_write(ring, mask);
250 amdgpu_ring_write(ring, inv); /* poll interval */
251}
252
253static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
254{
255 struct amdgpu_device *adev = ring->adev;
256 uint32_t scratch;
257 uint32_t tmp = 0;
258 unsigned i;
259 int r;
260
261 r = amdgpu_gfx_scratch_get(adev, &scratch);
262 if (r) {
263 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
264 return r;
265 }
266 WREG32(scratch, 0xCAFEDEAD);
267 r = amdgpu_ring_alloc(ring, 3);
268 if (r) {
269 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
270 ring->idx, r);
271 amdgpu_gfx_scratch_free(adev, scratch);
272 return r;
273 }
274 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
275 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
276 amdgpu_ring_write(ring, 0xDEADBEEF);
277 amdgpu_ring_commit(ring);
278
279 for (i = 0; i < adev->usec_timeout; i++) {
280 tmp = RREG32(scratch);
281 if (tmp == 0xDEADBEEF)
282 break;
283 DRM_UDELAY(1);
284 }
285 if (i < adev->usec_timeout) {
286 DRM_INFO("ring test on %d succeeded in %d usecs\n",
287 ring->idx, i);
288 } else {
289 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
290 ring->idx, scratch, tmp);
291 r = -EINVAL;
292 }
293 amdgpu_gfx_scratch_free(adev, scratch);
294 return r;
295}
296
297static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
298{
299 struct amdgpu_device *adev = ring->adev;
300 struct amdgpu_ib ib;
301 struct dma_fence *f = NULL;
302 uint32_t scratch;
303 uint32_t tmp = 0;
304 long r;
305
306 r = amdgpu_gfx_scratch_get(adev, &scratch);
307 if (r) {
308 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
309 return r;
310 }
311 WREG32(scratch, 0xCAFEDEAD);
312 memset(&ib, 0, sizeof(ib));
313 r = amdgpu_ib_get(adev, NULL, 256, &ib);
314 if (r) {
315 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
316 goto err1;
317 }
318 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
319 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
320 ib.ptr[2] = 0xDEADBEEF;
321 ib.length_dw = 3;
322
323 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
324 if (r)
325 goto err2;
326
327 r = dma_fence_wait_timeout(f, false, timeout);
328 if (r == 0) {
329 DRM_ERROR("amdgpu: IB test timed out.\n");
330 r = -ETIMEDOUT;
331 goto err2;
332 } else if (r < 0) {
333 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
334 goto err2;
335 }
336 tmp = RREG32(scratch);
337 if (tmp == 0xDEADBEEF) {
338 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
339 r = 0;
340 } else {
341 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
342 scratch, tmp);
343 r = -EINVAL;
344 }
345err2:
346 amdgpu_ib_free(adev, &ib, NULL);
347 dma_fence_put(f);
348err1:
349 amdgpu_gfx_scratch_free(adev, scratch);
350 return r;
351}
352
353static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
354{
355 const char *chip_name;
356 char fw_name[30];
357 int err;
358 struct amdgpu_firmware_info *info = NULL;
359 const struct common_firmware_header *header = NULL;
360 const struct gfx_firmware_header_v1_0 *cp_hdr;
a4d41ad0
HZ		 361 const struct rlc_firmware_header_v2_0 *rlc_hdr;
362 unsigned int *tmp = NULL;
363 unsigned int i = 0;
b1023571
KW		 364
365 DRM_DEBUG("\n");
366
367 switch (adev->asic_type) {
368 case CHIP_VEGA10:
369 chip_name = "vega10";
370 break;
eaa85724
CZ		 371 case CHIP_RAVEN:
372 chip_name = "raven";
373 break;
b1023571
KW		 374 default:
375 BUG();
376 }
377
378 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
379 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
380 if (err)
381 goto out;
382 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
383 if (err)
384 goto out;
385 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
386 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
387 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
388
389 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
390 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
391 if (err)
392 goto out;
393 err = amdgpu_ucode_validate(adev->gfx.me_fw);
394 if (err)
395 goto out;
396 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
397 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
398 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
399
400 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
401 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
402 if (err)
403 goto out;
404 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
405 if (err)
406 goto out;
407 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
408 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
409 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
410
411 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
412 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
413 if (err)
414 goto out;
415 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
a4d41ad0
HZ		 416 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
417 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
418 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
419 adev->gfx.rlc.save_and_restore_offset =
420 le32_to_cpu(rlc_hdr->save_and_restore_offset);
421 adev->gfx.rlc.clear_state_descriptor_offset =
422 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
423 adev->gfx.rlc.avail_scratch_ram_locations =
424 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
425 adev->gfx.rlc.reg_restore_list_size =
426 le32_to_cpu(rlc_hdr->reg_restore_list_size);
427 adev->gfx.rlc.reg_list_format_start =
428 le32_to_cpu(rlc_hdr->reg_list_format_start);
429 adev->gfx.rlc.reg_list_format_separate_start =
430 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
431 adev->gfx.rlc.starting_offsets_start =
432 le32_to_cpu(rlc_hdr->starting_offsets_start);
433 adev->gfx.rlc.reg_list_format_size_bytes =
434 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
435 adev->gfx.rlc.reg_list_size_bytes =
436 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
437 adev->gfx.rlc.register_list_format =
438 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
439 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
440 if (!adev->gfx.rlc.register_list_format) {
441 err = -ENOMEM;
442 goto out;
443 }
444
445 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
446 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
447 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
448 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
449
450 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
451
452 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
453 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
454 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
455 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
b1023571
KW		 456
457 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
458 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
459 if (err)
460 goto out;
461 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
462 if (err)
463 goto out;
464 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
465 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
466 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
467
468
469 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
470 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
471 if (!err) {
472 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
473 if (err)
474 goto out;
475 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
476 adev->gfx.mec2_fw->data;
477 adev->gfx.mec2_fw_version =
478 le32_to_cpu(cp_hdr->header.ucode_version);
479 adev->gfx.mec2_feature_version =
480 le32_to_cpu(cp_hdr->ucode_feature_version);
481 } else {
482 err = 0;
483 adev->gfx.mec2_fw = NULL;
484 }
485
486 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
487 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
488 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
489 info->fw = adev->gfx.pfp_fw;
490 header = (const struct common_firmware_header *)info->fw->data;
491 adev->firmware.fw_size +=
492 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
493
494 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
495 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
496 info->fw = adev->gfx.me_fw;
497 header = (const struct common_firmware_header *)info->fw->data;
498 adev->firmware.fw_size +=
499 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
500
501 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
502 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
503 info->fw = adev->gfx.ce_fw;
504 header = (const struct common_firmware_header *)info->fw->data;
505 adev->firmware.fw_size +=
506 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
507
508 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
509 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
510 info->fw = adev->gfx.rlc_fw;
511 header = (const struct common_firmware_header *)info->fw->data;
512 adev->firmware.fw_size +=
513 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
514
515 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
516 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
517 info->fw = adev->gfx.mec_fw;
518 header = (const struct common_firmware_header *)info->fw->data;
519 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
520 adev->firmware.fw_size +=
521 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
522
523 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
524 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
525 info->fw = adev->gfx.mec_fw;
526 adev->firmware.fw_size +=
527 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
528
529 if (adev->gfx.mec2_fw) {
530 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
531 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
532 info->fw = adev->gfx.mec2_fw;
533 header = (const struct common_firmware_header *)info->fw->data;
534 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
535 adev->firmware.fw_size +=
536 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
537 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
538 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
539 info->fw = adev->gfx.mec2_fw;
540 adev->firmware.fw_size +=
541 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
542 }
543
544 }
545
546out:
547 if (err) {
548 dev_err(adev->dev,
549 "gfx9: Failed to load firmware \"%s\"\n",
550 fw_name);
551 release_firmware(adev->gfx.pfp_fw);
552 adev->gfx.pfp_fw = NULL;
553 release_firmware(adev->gfx.me_fw);
554 adev->gfx.me_fw = NULL;
555 release_firmware(adev->gfx.ce_fw);
556 adev->gfx.ce_fw = NULL;
557 release_firmware(adev->gfx.rlc_fw);
558 adev->gfx.rlc_fw = NULL;
559 release_firmware(adev->gfx.mec_fw);
560 adev->gfx.mec_fw = NULL;
561 release_firmware(adev->gfx.mec2_fw);
562 adev->gfx.mec2_fw = NULL;
563 }
564 return err;
565}
566
c9719c69
HZ		 567static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
568{
569 u32 count = 0;
570 const struct cs_section_def *sect = NULL;
571 const struct cs_extent_def *ext = NULL;
572
573 /* begin clear state */
574 count += 2;
575 /* context control state */
576 count += 3;
577
578 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
579 for (ext = sect->section; ext->extent != NULL; ++ext) {
580 if (sect->id == SECT_CONTEXT)
581 count += 2 + ext->reg_count;
582 else
583 return 0;
584 }
585 }
586
587 /* end clear state */
588 count += 2;
589 /* clear state */
590 count += 2;
591
592 return count;
593}
594
595static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
596 volatile u32 *buffer)
597{
598 u32 count = 0, i;
599 const struct cs_section_def *sect = NULL;
600 const struct cs_extent_def *ext = NULL;
601
602 if (adev->gfx.rlc.cs_data == NULL)
603 return;
604 if (buffer == NULL)
605 return;
606
607 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
608 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
609
610 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
611 buffer[count++] = cpu_to_le32(0x80000000);
612 buffer[count++] = cpu_to_le32(0x80000000);
613
614 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
615 for (ext = sect->section; ext->extent != NULL; ++ext) {
616 if (sect->id == SECT_CONTEXT) {
617 buffer[count++] =
618 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
619 buffer[count++] = cpu_to_le32(ext->reg_index -
620 PACKET3_SET_CONTEXT_REG_START);
621 for (i = 0; i < ext->reg_count; i++)
622 buffer[count++] = cpu_to_le32(ext->extent[i]);
623 } else {
624 return;
625 }
626 }
627 }
628
629 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
630 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
631
632 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
633 buffer[count++] = cpu_to_le32(0);
634}
635
ba7bb665
HZ		 636static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
637{
e5475e16 638 uint32_t data;
ba7bb665
HZ		 639
640 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
641 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
642 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
643 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
644 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
645
646 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
647 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
648
649 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
650 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
651
652 mutex_lock(&adev->grbm_idx_mutex);
653 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
654 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
655 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
656
657 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
e5475e16
TSD		 658 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
659 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
660 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
ba7bb665
HZ		 661 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
662
663 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
664 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
665 data &= 0x0000FFFF;
666 data |= 0x00C00000;
667 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
668
669 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
670 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
671
672 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
673 * but used for RLC_LB_CNTL configuration */
674 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
e5475e16
TSD		 675 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
676 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
ba7bb665
HZ		 677 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
678 mutex_unlock(&adev->grbm_idx_mutex);
679}
680
e8835e0e
HZ		 681static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
682{
e5475e16 683 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
e8835e0e
HZ		 684}
685
c9719c69
HZ		 686static void rv_init_cp_jump_table(struct amdgpu_device *adev)
687{
688 const __le32 *fw_data;
689 volatile u32 *dst_ptr;
690 int me, i, max_me = 5;
691 u32 bo_offset = 0;
692 u32 table_offset, table_size;
693
694 /* write the cp table buffer */
695 dst_ptr = adev->gfx.rlc.cp_table_ptr;
696 for (me = 0; me < max_me; me++) {
697 if (me == 0) {
698 const struct gfx_firmware_header_v1_0 *hdr =
699 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
700 fw_data = (const __le32 *)
701 (adev->gfx.ce_fw->data +
702 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
703 table_offset = le32_to_cpu(hdr->jt_offset);
704 table_size = le32_to_cpu(hdr->jt_size);
705 } else if (me == 1) {
706 const struct gfx_firmware_header_v1_0 *hdr =
707 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
708 fw_data = (const __le32 *)
709 (adev->gfx.pfp_fw->data +
710 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
711 table_offset = le32_to_cpu(hdr->jt_offset);
712 table_size = le32_to_cpu(hdr->jt_size);
713 } else if (me == 2) {
714 const struct gfx_firmware_header_v1_0 *hdr =
715 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
716 fw_data = (const __le32 *)
717 (adev->gfx.me_fw->data +
718 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
719 table_offset = le32_to_cpu(hdr->jt_offset);
720 table_size = le32_to_cpu(hdr->jt_size);
721 } else if (me == 3) {
722 const struct gfx_firmware_header_v1_0 *hdr =
723 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
724 fw_data = (const __le32 *)
725 (adev->gfx.mec_fw->data +
726 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
727 table_offset = le32_to_cpu(hdr->jt_offset);
728 table_size = le32_to_cpu(hdr->jt_size);
729 } else if (me == 4) {
730 const struct gfx_firmware_header_v1_0 *hdr =
731 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
732 fw_data = (const __le32 *)
733 (adev->gfx.mec2_fw->data +
734 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
735 table_offset = le32_to_cpu(hdr->jt_offset);
736 table_size = le32_to_cpu(hdr->jt_size);
737 }
738
739 for (i = 0; i < table_size; i ++) {
740 dst_ptr[bo_offset + i] =
741 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
742 }
743
744 bo_offset += table_size;
745 }
746}
747
748static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
749{
750 /* clear state block */
751 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
752 &adev->gfx.rlc.clear_state_gpu_addr,
753 (void **)&adev->gfx.rlc.cs_ptr);
754
755 /* jump table block */
756 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
757 &adev->gfx.rlc.cp_table_gpu_addr,
758 (void **)&adev->gfx.rlc.cp_table_ptr);
759}
760
761static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
762{
763 volatile u32 *dst_ptr;
764 u32 dws;
765 const struct cs_section_def *cs_data;
766 int r;
767
768 adev->gfx.rlc.cs_data = gfx9_cs_data;
769
770 cs_data = adev->gfx.rlc.cs_data;
771
772 if (cs_data) {
773 /* clear state block */
774 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
775 if (adev->gfx.rlc.clear_state_obj == NULL) {
776 r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
777 AMDGPU_GEM_DOMAIN_VRAM,
778 &adev->gfx.rlc.clear_state_obj,
779 &adev->gfx.rlc.clear_state_gpu_addr,
780 (void **)&adev->gfx.rlc.cs_ptr);
781 if (r) {
782 dev_err(adev->dev,
783 "(%d) failed to create rlc csb bo\n", r);
784 gfx_v9_0_rlc_fini(adev);
785 return r;
786 }
787 }
788 /* set up the cs buffer */
789 dst_ptr = adev->gfx.rlc.cs_ptr;
790 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
791 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
792 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
793 }
794
795 if (adev->asic_type == CHIP_RAVEN) {
796 /* TODO: double check the cp_table_size for RV */
797 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
798 if (adev->gfx.rlc.cp_table_obj == NULL) {
799 r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size,
800 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
801 &adev->gfx.rlc.cp_table_obj,
802 &adev->gfx.rlc.cp_table_gpu_addr,
803 (void **)&adev->gfx.rlc.cp_table_ptr);
804 if (r) {
805 dev_err(adev->dev,
806 "(%d) failed to create cp table bo\n", r);
807 gfx_v9_0_rlc_fini(adev);
808 return r;
809 }
810 }
811
812 rv_init_cp_jump_table(adev);
813 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
814 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
ba7bb665
HZ		 815
816 gfx_v9_0_init_lbpw(adev);
c9719c69
HZ		 817 }
818
819 return 0;
820}
821
b1023571
KW		 822static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
823{
824 int r;
825
826 if (adev->gfx.mec.hpd_eop_obj) {
c81a1a74 827 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
b1023571
KW		 828 if (unlikely(r != 0))
829 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
830 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
831 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
832
833 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
834 adev->gfx.mec.hpd_eop_obj = NULL;
835 }
836 if (adev->gfx.mec.mec_fw_obj) {
c81a1a74 837 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true);
b1023571
KW		 838 if (unlikely(r != 0))
839 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
840 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
841 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
842
843 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
844 adev->gfx.mec.mec_fw_obj = NULL;
845 }
846}
847
b1023571
KW		 848static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
849{
850 int r;
851 u32 *hpd;
852 const __le32 *fw_data;
853 unsigned fw_size;
854 u32 *fw;
42794b27 855 size_t mec_hpd_size;
b1023571
KW		 856
857 const struct gfx_firmware_header_v1_0 *mec_hdr;
858
78c16834
AR		 859 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
860
78c16834 861 /* take ownership of the relevant compute queues */
41f6a99a 862 amdgpu_gfx_compute_queue_acquire(adev);
78c16834 863 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
b1023571
KW		 864
865 if (adev->gfx.mec.hpd_eop_obj == NULL) {
866 r = amdgpu_bo_create(adev,
42794b27 867 mec_hpd_size,
b1023571
KW		 868 PAGE_SIZE, true,
869 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
870 &adev->gfx.mec.hpd_eop_obj);
871 if (r) {
872 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
873 return r;
874 }
875 }
876
877 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
878 if (unlikely(r != 0)) {
879 gfx_v9_0_mec_fini(adev);
880 return r;
881 }
882 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
883 &adev->gfx.mec.hpd_eop_gpu_addr);
884 if (r) {
885 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
886 gfx_v9_0_mec_fini(adev);
887 return r;
888 }
889 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
890 if (r) {
891 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
892 gfx_v9_0_mec_fini(adev);
893 return r;
894 }
895
896 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
897
898 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
899 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
900
901 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
902
903 fw_data = (const __le32 *)
904 (adev->gfx.mec_fw->data +
905 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
906 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
907
908 if (adev->gfx.mec.mec_fw_obj == NULL) {
909 r = amdgpu_bo_create(adev,
910 mec_hdr->header.ucode_size_bytes,
911 PAGE_SIZE, true,
912 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
913 &adev->gfx.mec.mec_fw_obj);
914 if (r) {
915 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
916 return r;
917 }
918 }
919
920 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
921 if (unlikely(r != 0)) {
922 gfx_v9_0_mec_fini(adev);
923 return r;
924 }
925 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
926 &adev->gfx.mec.mec_fw_gpu_addr);
927 if (r) {
928 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
929 gfx_v9_0_mec_fini(adev);
930 return r;
931 }
932 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
933 if (r) {
934 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
935 gfx_v9_0_mec_fini(adev);
936 return r;
937 }
938 memcpy(fw, fw_data, fw_size);
939
940 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
941 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
942
943
944 return 0;
945}
946
947static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
948{
5e78835a 949 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 950 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
951 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
952 (address << SQ_IND_INDEX__INDEX__SHIFT) |
953 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 954 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 955}
956
957static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
958 uint32_t wave, uint32_t thread,
959 uint32_t regno, uint32_t num, uint32_t *out)
960{
5e78835a 961 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 962 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
963 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
964 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
965 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
966 (SQ_IND_INDEX__FORCE_READ_MASK) |
967 (SQ_IND_INDEX__AUTO_INCR_MASK));
968 while (num--)
5e78835a 969 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 970}
971
972static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
973{
974 /* type 1 wave data */
975 dst[(*no_fields)++] = 1;
976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
980 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
981 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
982 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
983 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
984 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
985 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
986 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
987 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
988 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
989 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
990}
991
992static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
993 uint32_t wave, uint32_t start,
994 uint32_t size, uint32_t *dst)
995{
996 wave_read_regs(
997 adev, simd, wave, 0,
998 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
999}
1000
1001
1002static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1003 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1004 .select_se_sh = &gfx_v9_0_select_se_sh,
1005 .read_wave_data = &gfx_v9_0_read_wave_data,
1006 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1007};
1008
1009static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1010{
1011 u32 gb_addr_config;
1012
1013 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1014
1015 switch (adev->asic_type) {
1016 case CHIP_VEGA10:
b1023571 1017 adev->gfx.config.max_hw_contexts = 8;
b1023571
KW		 1018 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1019 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1020 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1021 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1022 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1023 break;
5cf7433d
CZ		 1024 case CHIP_RAVEN:
1025 adev->gfx.config.max_hw_contexts = 8;
1026 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1027 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1028 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1029 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1030 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1031 break;
b1023571
KW		 1032 default:
1033 BUG();
1034 break;
1035 }
1036
1037 adev->gfx.config.gb_addr_config = gb_addr_config;
1038
1039 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1040 REG_GET_FIELD(
1041 adev->gfx.config.gb_addr_config,
1042 GB_ADDR_CONFIG,
1043 NUM_PIPES);
ad7d0ff3
AD		 1044
1045 adev->gfx.config.max_tile_pipes =
1046 adev->gfx.config.gb_addr_config_fields.num_pipes;
1047
b1023571
KW		 1048 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1049 REG_GET_FIELD(
1050 adev->gfx.config.gb_addr_config,
1051 GB_ADDR_CONFIG,
1052 NUM_BANKS);
1053 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1054 REG_GET_FIELD(
1055 adev->gfx.config.gb_addr_config,
1056 GB_ADDR_CONFIG,
1057 MAX_COMPRESSED_FRAGS);
1058 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1059 REG_GET_FIELD(
1060 adev->gfx.config.gb_addr_config,
1061 GB_ADDR_CONFIG,
1062 NUM_RB_PER_SE);
1063 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1064 REG_GET_FIELD(
1065 adev->gfx.config.gb_addr_config,
1066 GB_ADDR_CONFIG,
1067 NUM_SHADER_ENGINES);
1068 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1069 REG_GET_FIELD(
1070 adev->gfx.config.gb_addr_config,
1071 GB_ADDR_CONFIG,
1072 PIPE_INTERLEAVE_SIZE));
1073}
1074
1075static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1076 struct amdgpu_ngg_buf *ngg_buf,
1077 int size_se,
1078 int default_size_se)
1079{
1080 int r;
1081
1082 if (size_se < 0) {
1083 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1084 return -EINVAL;
1085 }
1086 size_se = size_se ? size_se : default_size_se;
1087
42ce2243 1088 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 1089 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1090 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1091 &ngg_buf->bo,
1092 &ngg_buf->gpu_addr,
1093 NULL);
1094 if (r) {
1095 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1096 return r;
1097 }
1098 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1099
1100 return r;
1101}
1102
1103static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1104{
1105 int i;
1106
1107 for (i = 0; i < NGG_BUF_MAX; i++)
1108 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1109 &adev->gfx.ngg.buf[i].gpu_addr,
1110 NULL);
1111
1112 memset(&adev->gfx.ngg.buf[0], 0,
1113 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1114
1115 adev->gfx.ngg.init = false;
1116
1117 return 0;
1118}
1119
1120static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1121{
1122 int r;
1123
1124 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1125 return 0;
1126
1127 /* GDS reserve memory: 64 bytes alignment */
1128 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1129 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1130 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1131 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1132 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1133
1134 /* Primitive Buffer */
af8baf15 1135 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
b1023571
KW		 1136 amdgpu_prim_buf_per_se,
1137 64 * 1024);
1138 if (r) {
1139 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1140 goto err;
1141 }
1142
1143 /* Position Buffer */
af8baf15 1144 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
b1023571
KW		 1145 amdgpu_pos_buf_per_se,
1146 256 * 1024);
1147 if (r) {
1148 dev_err(adev->dev, "Failed to create Position Buffer\n");
1149 goto err;
1150 }
1151
1152 /* Control Sideband */
af8baf15 1153 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
b1023571
KW		 1154 amdgpu_cntl_sb_buf_per_se,
1155 256);
1156 if (r) {
1157 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1158 goto err;
1159 }
1160
1161 /* Parameter Cache, not created by default */
1162 if (amdgpu_param_buf_per_se <= 0)
1163 goto out;
1164
af8baf15 1165 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
b1023571
KW		 1166 amdgpu_param_buf_per_se,
1167 512 * 1024);
1168 if (r) {
1169 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1170 goto err;
1171 }
1172
1173out:
1174 adev->gfx.ngg.init = true;
1175 return 0;
1176err:
1177 gfx_v9_0_ngg_fini(adev);
1178 return r;
1179}
1180
1181static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1182{
1183 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1184 int r;
1185 u32 data;
1186 u32 size;
1187 u32 base;
1188
1189 if (!amdgpu_ngg)
1190 return 0;
1191
1192 /* Program buffer size */
1193 data = 0;
af8baf15 1194 size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
b1023571
KW		 1195 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
1196
af8baf15 1197 size = adev->gfx.ngg.buf[NGG_POS].size / 256;
b1023571
KW		 1198 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
1199
5e78835a 1200 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571
KW		 1201
1202 data = 0;
af8baf15 1203 size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
b1023571
KW		 1204 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
1205
af8baf15 1206 size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
b1023571
KW		 1207 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
1208
5e78835a 1209 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 1210
1211 /* Program buffer base address */
af8baf15 1212 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1213 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 1214 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571 1215
af8baf15 1216 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1217 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 1218 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571 1219
af8baf15 1220 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1221 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 1222 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571 1223
af8baf15 1224 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1225 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 1226 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571 1227
af8baf15 1228 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1229 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 1230 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571 1231
af8baf15 1232 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1233 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 1234 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 1235
1236 /* Clear GDS reserved memory */
1237 r = amdgpu_ring_alloc(ring, 17);
1238 if (r) {
1239 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1240 ring->idx, r);
1241 return r;
1242 }
1243
1244 gfx_v9_0_write_data_to_reg(ring, 0, false,
1245 amdgpu_gds_reg_offset[0].mem_size,
1246 (adev->gds.mem.total_size +
1247 adev->gfx.ngg.gds_reserve_size) >>
1248 AMDGPU_GDS_SHIFT);
1249
1250 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1251 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1252 PACKET3_DMA_DATA_SRC_SEL(2)));
1253 amdgpu_ring_write(ring, 0);
1254 amdgpu_ring_write(ring, 0);
1255 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1256 amdgpu_ring_write(ring, 0);
1257 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1258
1259
1260 gfx_v9_0_write_data_to_reg(ring, 0, false,
1261 amdgpu_gds_reg_offset[0].mem_size, 0);
1262
1263 amdgpu_ring_commit(ring);
1264
1265 return 0;
1266}
1267
1361f455
AD		 1268static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1269 int mec, int pipe, int queue)
1270{
1271 int r;
1272 unsigned irq_type;
1273 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1274
1275 ring = &adev->gfx.compute_ring[ring_id];
1276
1277 /* mec0 is me1 */
1278 ring->me = mec + 1;
1279 ring->pipe = pipe;
1280 ring->queue = queue;
1281
1282 ring->ring_obj = NULL;
1283 ring->use_doorbell = true;
1284 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
1285 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1286 + (ring_id * GFX9_MEC_HPD_SIZE);
1287 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1288
1289 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1290 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1291 + ring->pipe;
1292
1293 /* type-2 packets are deprecated on MEC, use type-3 instead */
1294 r = amdgpu_ring_init(adev, ring, 1024,
1295 &adev->gfx.eop_irq, irq_type);
1296 if (r)
1297 return r;
1298
1299
1300 return 0;
1301}
1302
b1023571
KW		 1303static int gfx_v9_0_sw_init(void *handle)
1304{
1361f455 1305 int i, j, k, r, ring_id;
b1023571 1306 struct amdgpu_ring *ring;
ac104e99 1307 struct amdgpu_kiq *kiq;
b1023571
KW		 1308 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1309
4853bbb6
AD		 1310 switch (adev->asic_type) {
1311 case CHIP_VEGA10:
1312 case CHIP_RAVEN:
1313 adev->gfx.mec.num_mec = 2;
1314 break;
1315 default:
1316 adev->gfx.mec.num_mec = 1;
1317 break;
1318 }
1319
1320 adev->gfx.mec.num_pipe_per_mec = 4;
1321 adev->gfx.mec.num_queue_per_pipe = 8;
1322
97031e25
XY		 1323 /* KIQ event */
1324 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1325 if (r)
1326 return r;
1327
b1023571
KW		 1328 /* EOP Event */
1329 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1330 if (r)
1331 return r;
1332
1333 /* Privileged reg */
1334 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1335 &adev->gfx.priv_reg_irq);
1336 if (r)
1337 return r;
1338
1339 /* Privileged inst */
1340 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1341 &adev->gfx.priv_inst_irq);
1342 if (r)
1343 return r;
1344
1345 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1346
1347 gfx_v9_0_scratch_init(adev);
1348
1349 r = gfx_v9_0_init_microcode(adev);
1350 if (r) {
1351 DRM_ERROR("Failed to load gfx firmware!\n");
1352 return r;
1353 }
1354
c9719c69
HZ		 1355 r = gfx_v9_0_rlc_init(adev);
1356 if (r) {
1357 DRM_ERROR("Failed to init rlc BOs!\n");
1358 return r;
1359 }
1360
b1023571
KW		 1361 r = gfx_v9_0_mec_init(adev);
1362 if (r) {
1363 DRM_ERROR("Failed to init MEC BOs!\n");
1364 return r;
1365 }
1366
1367 /* set up the gfx ring */
1368 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1369 ring = &adev->gfx.gfx_ring[i];
1370 ring->ring_obj = NULL;
1371 sprintf(ring->name, "gfx");
1372 ring->use_doorbell = true;
1373 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1374 r = amdgpu_ring_init(adev, ring, 1024,
1375 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1376 if (r)
1377 return r;
1378 }
1379
1361f455
AD		 1380 /* set up the compute queues - allocate horizontally across pipes */
1381 ring_id = 0;
1382 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1383 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1384 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2db0cdbe 1385 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1361f455
AD		 1386 continue;
1387
1388 r = gfx_v9_0_compute_ring_init(adev,
1389 ring_id,
1390 i, k, j);
1391 if (r)
1392 return r;
1393
1394 ring_id++;
1395 }
b1023571 1396 }
b1023571
KW		 1397 }
1398
71c37505 1399 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
e30a5223
AD		 1400 if (r) {
1401 DRM_ERROR("Failed to init KIQ BOs!\n");
1402 return r;
1403 }
ac104e99 1404
e30a5223 1405 kiq = &adev->gfx.kiq;
71c37505 1406 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
e30a5223
AD		 1407 if (r)
1408 return r;
464826d6 1409
e30a5223 1410 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
b9683c21 1411 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd));
e30a5223
AD		 1412 if (r)
1413 return r;
ac104e99 1414
b1023571
KW		 1415 /* reserve GDS, GWS and OA resource for gfx */
1416 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1417 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1418 &adev->gds.gds_gfx_bo, NULL, NULL);
1419 if (r)
1420 return r;
1421
1422 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1423 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1424 &adev->gds.gws_gfx_bo, NULL, NULL);
1425 if (r)
1426 return r;
1427
1428 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1429 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1430 &adev->gds.oa_gfx_bo, NULL, NULL);
1431 if (r)
1432 return r;
1433
1434 adev->gfx.ce_ram_size = 0x8000;
1435
1436 gfx_v9_0_gpu_early_init(adev);
1437
1438 r = gfx_v9_0_ngg_init(adev);
1439 if (r)
1440 return r;
1441
1442 return 0;
1443}
1444
1445
1446static int gfx_v9_0_sw_fini(void *handle)
1447{
1448 int i;
1449 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1450
1451 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1452 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1453 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1454
1455 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1456 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1457 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1458 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1459
b9683c21 1460 amdgpu_gfx_compute_mqd_sw_fini(adev);
71c37505
AD		 1461 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1462 amdgpu_gfx_kiq_fini(adev);
ac104e99 1463
b1023571
KW		 1464 gfx_v9_0_mec_fini(adev);
1465 gfx_v9_0_ngg_fini(adev);
1466
1467 return 0;
1468}
1469
1470
1471static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1472{
1473 /* TODO */
1474}
1475
1476static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1477{
1478 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1479
1480 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1481 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1482 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1483 } else if (se_num == 0xffffffff) {
1484 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1485 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1486 } else if (sh_num == 0xffffffff) {
1487 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1488 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1489 } else {
1490 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1491 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1492 }
5e78835a 1493 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1494}
1495
b1023571
KW		 1496static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1497{
1498 u32 data, mask;
1499
5e78835a
TSD		 1500 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1501 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1502
1503 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1504 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1505
378506a7
AD		 1506 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1507 adev->gfx.config.max_sh_per_se);
b1023571
KW		 1508
1509 return (~data) & mask;
1510}
1511
1512static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1513{
1514 int i, j;
2572c24c 1515 u32 data;
b1023571
KW		 1516 u32 active_rbs = 0;
1517 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1518 adev->gfx.config.max_sh_per_se;
1519
1520 mutex_lock(&adev->grbm_idx_mutex);
1521 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1522 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1523 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1524 data = gfx_v9_0_get_rb_active_bitmap(adev);
1525 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1526 rb_bitmap_width_per_sh);
1527 }
1528 }
1529 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1530 mutex_unlock(&adev->grbm_idx_mutex);
1531
1532 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1533 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1534}
1535
1536#define DEFAULT_SH_MEM_BASES (0x6000)
1537#define FIRST_COMPUTE_VMID (8)
1538#define LAST_COMPUTE_VMID (16)
1539static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1540{
1541 int i;
1542 uint32_t sh_mem_config;
1543 uint32_t sh_mem_bases;
1544
1545 /*
1546 * Configure apertures:
1547 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1548 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1549 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1550 */
1551 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1552
1553 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1554 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
eaa05d52 1555 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
b1023571
KW		 1556
1557 mutex_lock(&adev->srbm_mutex);
1558 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1559 soc15_grbm_select(adev, 0, 0, 0, i);
1560 /* CP and shaders */
5e78835a
TSD		 1561 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1562 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1563 }
1564 soc15_grbm_select(adev, 0, 0, 0, 0);
1565 mutex_unlock(&adev->srbm_mutex);
1566}
1567
1568static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1569{
1570 u32 tmp;
1571 int i;
1572
40f06773 1573 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1574
1575 gfx_v9_0_tiling_mode_table_init(adev);
1576
1577 gfx_v9_0_setup_rb(adev);
1578 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1579
1580 /* XXX SH_MEM regs */
1581 /* where to put LDS, scratch, GPUVM in FSA64 space */
1582 mutex_lock(&adev->srbm_mutex);
1583 for (i = 0; i < 16; i++) {
1584 soc15_grbm_select(adev, 0, 0, 0, i);
1585 /* CP and shaders */
1586 tmp = 0;
1587 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1588 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5e78835a
TSD		 1589 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1590 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
b1023571
KW		 1591 }
1592 soc15_grbm_select(adev, 0, 0, 0, 0);
1593
1594 mutex_unlock(&adev->srbm_mutex);
1595
1596 gfx_v9_0_init_compute_vmid(adev);
1597
1598 mutex_lock(&adev->grbm_idx_mutex);
1599 /*
1600 * making sure that the following register writes will be broadcasted
1601 * to all the shaders
1602 */
1603 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1604
5e78835a 1605 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1606 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1607 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1608 (adev->gfx.config.sc_prim_fifo_size_backend <<
1609 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1610 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1611 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1612 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1613 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1614 mutex_unlock(&adev->grbm_idx_mutex);
1615
1616}
1617
1618static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1619{
1620 u32 i, j, k;
1621 u32 mask;
1622
1623 mutex_lock(&adev->grbm_idx_mutex);
1624 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1625 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1626 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1627 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1628 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1629 break;
1630 udelay(1);
1631 }
1632 }
1633 }
1634 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1635 mutex_unlock(&adev->grbm_idx_mutex);
1636
1637 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1638 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1639 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1640 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1641 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1642 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1643 break;
1644 udelay(1);
1645 }
1646}
1647
1648static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1649 bool enable)
1650{
5e78835a 1651 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571 1652
b1023571
KW		 1653 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1654 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1655 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1656 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1657
5e78835a 1658 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1659}
1660
6bce4667
HZ		 1661static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1662{
1663 /* csib */
1664 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1665 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1666 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1667 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1668 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1669 adev->gfx.rlc.clear_state_size);
1670}
1671
1672static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1673 int indirect_offset,
1674 int list_size,
1675 int *unique_indirect_regs,
1676 int *unique_indirect_reg_count,
1677 int max_indirect_reg_count,
1678 int *indirect_start_offsets,
1679 int *indirect_start_offsets_count,
1680 int max_indirect_start_offsets_count)
1681{
1682 int idx;
1683 bool new_entry = true;
1684
1685 for (; indirect_offset < list_size; indirect_offset++) {
1686
1687 if (new_entry) {
1688 new_entry = false;
1689 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1690 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1691 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1692 }
1693
1694 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1695 new_entry = true;
1696 continue;
1697 }
1698
1699 indirect_offset += 2;
1700
1701 /* look for the matching indice */
1702 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1703 if (unique_indirect_regs[idx] ==
1704 register_list_format[indirect_offset])
1705 break;
1706 }
1707
1708 if (idx >= *unique_indirect_reg_count) {
1709 unique_indirect_regs[*unique_indirect_reg_count] =
1710 register_list_format[indirect_offset];
1711 idx = *unique_indirect_reg_count;
1712 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1713 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1714 }
1715
1716 register_list_format[indirect_offset] = idx;
1717 }
1718}
1719
1720static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1721{
1722 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1723 int unique_indirect_reg_count = 0;
1724
1725 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1726 int indirect_start_offsets_count = 0;
1727
1728 int list_size = 0;
1729 int i = 0;
1730 u32 tmp = 0;
1731
1732 u32 *register_list_format =
1733 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1734 if (!register_list_format)
1735 return -ENOMEM;
1736 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1737 adev->gfx.rlc.reg_list_format_size_bytes);
1738
1739 /* setup unique_indirect_regs array and indirect_start_offsets array */
1740 gfx_v9_0_parse_ind_reg_list(register_list_format,
1741 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1742 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1743 unique_indirect_regs,
1744 &unique_indirect_reg_count,
1745 sizeof(unique_indirect_regs)/sizeof(int),
1746 indirect_start_offsets,
1747 &indirect_start_offsets_count,
1748 sizeof(indirect_start_offsets)/sizeof(int));
1749
1750 /* enable auto inc in case it is disabled */
1751 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1752 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1753 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1754
1755 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1756 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1757 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1758 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1759 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1760 adev->gfx.rlc.register_restore[i]);
1761
1762 /* load direct register */
1763 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1764 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1765 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1766 adev->gfx.rlc.register_restore[i]);
1767
1768 /* load indirect register */
1769 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1770 adev->gfx.rlc.reg_list_format_start);
1771 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1772 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1773 register_list_format[i]);
1774
1775 /* set save/restore list size */
1776 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1777 list_size = list_size >> 1;
1778 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1779 adev->gfx.rlc.reg_restore_list_size);
1780 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1781
1782 /* write the starting offsets to RLC scratch ram */
1783 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1784 adev->gfx.rlc.starting_offsets_start);
1785 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1786 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1787 indirect_start_offsets[i]);
1788
1789 /* load unique indirect regs*/
1790 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1791 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1792 unique_indirect_regs[i] & 0x3FFFF);
1793 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1794 unique_indirect_regs[i] >> 20);
1795 }
1796
1797 kfree(register_list_format);
1798 return 0;
1799}
1800
1801static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1802{
1803 u32 tmp = 0;
1804
1805 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1806 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1807 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1808}
1809
91d3130a
HZ		 1810static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1811 bool enable)
1812{
1813 uint32_t data = 0;
1814 uint32_t default_data = 0;
1815
1816 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1817 if (enable == true) {
1818 /* enable GFXIP control over CGPG */
1819 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1820 if(default_data != data)
1821 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1822
1823 /* update status */
1824 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1825 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1826 if(default_data != data)
1827 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1828 } else {
1829 /* restore GFXIP control over GCPG */
1830 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1831 if(default_data != data)
1832 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1833 }
1834}
1835
1836static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1837{
1838 uint32_t data = 0;
1839
1840 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1841 AMD_PG_SUPPORT_GFX_SMG |
1842 AMD_PG_SUPPORT_GFX_DMG)) {
1843 /* init IDLE_POLL_COUNT = 60 */
1844 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1845 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1846 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1847 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1848
1849 /* init RLC PG Delay */
1850 data = 0;
1851 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1852 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1853 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1854 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1855 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1856
1857 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1858 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1859 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1860 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1861
1862 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1863 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1864 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1865 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1866
1867 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1868 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1869
1870 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1871 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1872 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1873
1874 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1875 }
1876}
1877
ed5ad1e4
HZ		 1878static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1879 bool enable)
1880{
1881 uint32_t data = 0;
1882 uint32_t default_data = 0;
1883
1884 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1885
1886 if (enable == true) {
1887 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1888 if (default_data != data)
1889 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1890 } else {
1891 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1892 if(default_data != data)
1893 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1894 }
1895}
1896
1897static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1898 bool enable)
1899{
1900 uint32_t data = 0;
1901 uint32_t default_data = 0;
1902
1903 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1904
1905 if (enable == true) {
1906 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1907 if(default_data != data)
1908 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1909 } else {
1910 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1911 if(default_data != data)
1912 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1913 }
1914}
1915
3a6cc477
HZ		 1916static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1917 bool enable)
1918{
1919 uint32_t data = 0;
1920 uint32_t default_data = 0;
1921
1922 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1923
1924 if (enable == true) {
1925 data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
1926 if(default_data != data)
1927 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1928 } else {
1929 data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
1930 if(default_data != data)
1931 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1932 }
1933}
1934
197f95c8
HZ		 1935static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
1936 bool enable)
1937{
1938 uint32_t data, default_data;
1939
1940 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1941 if (enable == true)
1942 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
1943 else
1944 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
1945 if(default_data != data)
1946 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1947}
1948
1949static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
1950 bool enable)
1951{
1952 uint32_t data, default_data;
1953
1954 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1955 if (enable == true)
1956 data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
1957 else
1958 data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
1959 if(default_data != data)
1960 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1961
1962 if (!enable)
1963 /* read any GFX register to wake up GFX */
1964 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
1965}
1966
18924c71
HZ		 1967void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
1968 bool enable)
1969{
1970 uint32_t data, default_data;
1971
1972 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1973 if (enable == true)
1974 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
1975 else
1976 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
1977 if(default_data != data)
1978 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1979}
1980
1981void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
1982 bool enable)
1983{
1984 uint32_t data, default_data;
1985
1986 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1987 if (enable == true)
1988 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
1989 else
1990 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
1991 if(default_data != data)
1992 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1993}
1994
6bce4667
HZ		 1995static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
1996{
1997 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1998 AMD_PG_SUPPORT_GFX_SMG |
1999 AMD_PG_SUPPORT_GFX_DMG |
2000 AMD_PG_SUPPORT_CP |
2001 AMD_PG_SUPPORT_GDS |
2002 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2003 gfx_v9_0_init_csb(adev);
2004 gfx_v9_0_init_rlc_save_restore_list(adev);
2005 gfx_v9_0_enable_save_restore_machine(adev);
91d3130a
HZ		 2006
2007 if (adev->asic_type == CHIP_RAVEN) {
2008 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2009 adev->gfx.rlc.cp_table_gpu_addr >> 8);
2010 gfx_v9_0_init_gfx_power_gating(adev);
3a6cc477 2011
ed5ad1e4
HZ		 2012 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
2013 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
2014 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
2015 } else {
2016 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
2017 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
2018 }
3a6cc477
HZ		 2019
2020 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
2021 gfx_v9_0_enable_cp_power_gating(adev, true);
2022 else
2023 gfx_v9_0_enable_cp_power_gating(adev, false);
91d3130a 2024 }
6bce4667
HZ		 2025 }
2026}
2027
b1023571
KW		 2028void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2029{
5e78835a 2030 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 2031
2032 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5e78835a 2033 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
b1023571
KW		 2034
2035 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2036
2037 gfx_v9_0_wait_for_rlc_serdes(adev);
2038}
2039
2040static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2041{
596c8e8b 2042 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 2043 udelay(50);
596c8e8b 2044 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 2045 udelay(50);
2046}
2047
2048static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2049{
2050#ifdef AMDGPU_RLC_DEBUG_RETRY
2051 u32 rlc_ucode_ver;
2052#endif
b1023571 2053
342cda25 2054 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 2055
2056 /* carrizo do enable cp interrupt after cp inited */
2057 if (!(adev->flags & AMD_IS_APU))
2058 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2059
2060 udelay(50);
2061
2062#ifdef AMDGPU_RLC_DEBUG_RETRY
2063 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 2064 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 2065 if(rlc_ucode_ver == 0x108) {
2066 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2067 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2068 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2069 * default is 0x9C4 to create a 100us interval */
5e78835a 2070 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571 2071 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
eaa05d52 2072 * to disable the page fault retry interrupts, default is
b1023571 2073 * 0x100 (256) */
5e78835a 2074 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 2075 }
2076#endif
2077}
2078
2079static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2080{
2081 const struct rlc_firmware_header_v2_0 *hdr;
2082 const __le32 *fw_data;
2083 unsigned i, fw_size;
2084
2085 if (!adev->gfx.rlc_fw)
2086 return -EINVAL;
2087
2088 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2089 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2090
2091 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2092 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2093 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2094
5e78835a 2095 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 2096 RLCG_UCODE_LOADING_START_ADDRESS);
2097 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2098 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2099 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 2100
2101 return 0;
2102}
2103
2104static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2105{
2106 int r;
2107
cfee05bc
ML		 2108 if (amdgpu_sriov_vf(adev))
2109 return 0;
2110
b1023571
KW		 2111 gfx_v9_0_rlc_stop(adev);
2112
2113 /* disable CG */
5e78835a 2114 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 2115
2116 /* disable PG */
5e78835a 2117 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 2118
2119 gfx_v9_0_rlc_reset(adev);
2120
6bce4667
HZ		 2121 gfx_v9_0_init_pg(adev);
2122
b1023571
KW		 2123 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2124 /* legacy rlc firmware loading */
2125 r = gfx_v9_0_rlc_load_microcode(adev);
2126 if (r)
2127 return r;
2128 }
2129
e8835e0e
HZ		 2130 if (adev->asic_type == CHIP_RAVEN) {
2131 if (amdgpu_lbpw != 0)
2132 gfx_v9_0_enable_lbpw(adev, true);
2133 else
2134 gfx_v9_0_enable_lbpw(adev, false);
2135 }
2136
b1023571
KW		 2137 gfx_v9_0_rlc_start(adev);
2138
2139 return 0;
2140}
2141
2142static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2143{
2144 int i;
5e78835a 2145 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 2146
ea64468e
TSD		 2147 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2148 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2149 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2150 if (!enable) {
b1023571
KW		 2151 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2152 adev->gfx.gfx_ring[i].ready = false;
2153 }
5e78835a 2154 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 2155 udelay(50);
2156}
2157
2158static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2159{
2160 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2161 const struct gfx_firmware_header_v1_0 *ce_hdr;
2162 const struct gfx_firmware_header_v1_0 *me_hdr;
2163 const __le32 *fw_data;
2164 unsigned i, fw_size;
2165
2166 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2167 return -EINVAL;
2168
2169 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2170 adev->gfx.pfp_fw->data;
2171 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2172 adev->gfx.ce_fw->data;
2173 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2174 adev->gfx.me_fw->data;
2175
2176 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2177 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2178 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2179
2180 gfx_v9_0_cp_gfx_enable(adev, false);
2181
2182 /* PFP */
2183 fw_data = (const __le32 *)
2184 (adev->gfx.pfp_fw->data +
2185 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2186 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 2187 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 2188 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2189 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2190 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 2191
2192 /* CE */
2193 fw_data = (const __le32 *)
2194 (adev->gfx.ce_fw->data +
2195 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2196 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 2197 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 2198 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2199 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2200 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 2201
2202 /* ME */
2203 fw_data = (const __le32 *)
2204 (adev->gfx.me_fw->data +
2205 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2206 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 2207 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 2208 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2209 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2210 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 2211
2212 return 0;
2213}
2214
b1023571
KW		 2215static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2216{
2217 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2218 const struct cs_section_def *sect = NULL;
2219 const struct cs_extent_def *ext = NULL;
2220 int r, i;
2221
2222 /* init the CP */
5e78835a
TSD		 2223 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2224 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 2225
2226 gfx_v9_0_cp_gfx_enable(adev, true);
2227
2228 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
2229 if (r) {
2230 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2231 return r;
2232 }
2233
2234 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2235 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2236
2237 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2238 amdgpu_ring_write(ring, 0x80000000);
2239 amdgpu_ring_write(ring, 0x80000000);
2240
2241 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2242 for (ext = sect->section; ext->extent != NULL; ++ext) {
2243 if (sect->id == SECT_CONTEXT) {
2244 amdgpu_ring_write(ring,
2245 PACKET3(PACKET3_SET_CONTEXT_REG,
2246 ext->reg_count));
2247 amdgpu_ring_write(ring,
2248 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2249 for (i = 0; i < ext->reg_count; i++)
2250 amdgpu_ring_write(ring, ext->extent[i]);
2251 }
2252 }
2253 }
2254
2255 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2256 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2257
2258 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2259 amdgpu_ring_write(ring, 0);
2260
2261 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2262 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2263 amdgpu_ring_write(ring, 0x8000);
2264 amdgpu_ring_write(ring, 0x8000);
2265
2266 amdgpu_ring_commit(ring);
2267
2268 return 0;
2269}
2270
2271static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2272{
2273 struct amdgpu_ring *ring;
2274 u32 tmp;
2275 u32 rb_bufsz;
3fc08b61 2276 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 2277
2278 /* Set the write pointer delay */
5e78835a 2279 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 2280
2281 /* set the RB to use vmid 0 */
5e78835a 2282 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 2283
2284 /* Set ring buffer size */
2285 ring = &adev->gfx.gfx_ring[0];
2286 rb_bufsz = order_base_2(ring->ring_size / 8);
2287 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2288 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2289#ifdef __BIG_ENDIAN
2290 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2291#endif
5e78835a 2292 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2293
2294 /* Initialize the ring buffer's write pointers */
2295 ring->wptr = 0;
5e78835a
TSD		 2296 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2297 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2298
2299 /* set the wb address wether it's enabled or not */
2300 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 2301 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2302 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 2303
3fc08b61 2304 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 2305 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2306 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 2307
b1023571 2308 mdelay(1);
5e78835a 2309 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2310
2311 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 2312 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2313 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 2314
5e78835a 2315 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 2316 if (ring->use_doorbell) {
2317 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2318 DOORBELL_OFFSET, ring->doorbell_index);
2319 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2320 DOORBELL_EN, 1);
2321 } else {
2322 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2323 }
5e78835a 2324 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 2325
2326 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2327 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 2328 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 2329
5e78835a 2330 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 2331 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2332
2333
2334 /* start the ring */
2335 gfx_v9_0_cp_gfx_start(adev);
2336 ring->ready = true;
2337
2338 return 0;
2339}
2340
2341static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2342{
2343 int i;
2344
2345 if (enable) {
5e78835a 2346 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 2347 } else {
5e78835a 2348 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 2349 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2350 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2351 adev->gfx.compute_ring[i].ready = false;
ac104e99 2352 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 2353 }
2354 udelay(50);
2355}
2356
b1023571
KW		 2357static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2358{
2359 const struct gfx_firmware_header_v1_0 *mec_hdr;
2360 const __le32 *fw_data;
2361 unsigned i;
2362 u32 tmp;
2363
2364 if (!adev->gfx.mec_fw)
2365 return -EINVAL;
2366
2367 gfx_v9_0_cp_compute_enable(adev, false);
2368
2369 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2370 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2371
2372 fw_data = (const __le32 *)
2373 (adev->gfx.mec_fw->data +
2374 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2375 tmp = 0;
2376 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2377 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 2378 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 2379
5e78835a 2380 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 2381 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 2382 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571 2383 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
eaa05d52 2384
b1023571 2385 /* MEC1 */
5e78835a 2386 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2387 mec_hdr->jt_offset);
2388 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 2389 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 2390 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2391
5e78835a 2392 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2393 adev->gfx.mec_fw_version);
2394 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2395
2396 return 0;
2397}
2398
464826d6
XY		 2399/* KIQ functions */
2400static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2401{
2402 uint32_t tmp;
2403 struct amdgpu_device *adev = ring->adev;
2404
2405 /* tell RLC which is KIQ queue */
5e78835a 2406 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 2407 tmp &= 0xffffff00;
2408 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 2409 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2410 tmp |= 0x80;
5e78835a 2411 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6
XY		 2412}
2413
0f1dfd52 2414static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
464826d6 2415{
bd3402ea 2416 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2fdde9fa 2417 uint32_t scratch, tmp = 0;
de65513a 2418 uint64_t queue_mask = 0;
2fdde9fa
AD		 2419 int r, i;
2420
de65513a
AR		 2421 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2422 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2423 continue;
2424
2425 /* This situation may be hit in the future if a new HW
2426 * generation exposes more than 64 queues. If so, the
2427 * definition of queue_mask needs updating */
2428 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
2429 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2430 break;
2431 }
2432
2433 queue_mask |= (1ull << i);
2434 }
2435
2fdde9fa
AD		 2436 r = amdgpu_gfx_scratch_get(adev, &scratch);
2437 if (r) {
2438 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2439 return r;
2440 }
2441 WREG32(scratch, 0xCAFEDEAD);
2442
0f1dfd52 2443 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2fdde9fa
AD		 2444 if (r) {
2445 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2446 amdgpu_gfx_scratch_free(adev, scratch);
2447 return r;
2448 }
464826d6 2449
0f1dfd52
AD		 2450 /* set resources */
2451 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2452 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2453 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
de65513a
AR		 2454 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2455 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
0f1dfd52
AD		 2456 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2457 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2458 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2459 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
bd3402ea
AD		 2460 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2461 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2462 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2463 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2464
2465 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2466 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2467 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2468 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2469 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2470 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2471 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2472 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2473 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2474 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2475 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2476 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2477 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2478 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2479 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2480 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2481 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2482 }
2fdde9fa
AD		 2483 /* write to scratch for completion */
2484 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2485 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2486 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
464826d6 2487 amdgpu_ring_commit(kiq_ring);
2fdde9fa
AD		 2488
2489 for (i = 0; i < adev->usec_timeout; i++) {
2490 tmp = RREG32(scratch);
2491 if (tmp == 0xDEADBEEF)
2492 break;
2493 DRM_UDELAY(1);
2494 }
2495 if (i >= adev->usec_timeout) {
2496 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2497 scratch, tmp);
2498 r = -EINVAL;
2499 }
2500 amdgpu_gfx_scratch_free(adev, scratch);
2501
2502 return r;
464826d6
XY		 2503}
2504
e30a5223
AD		 2505static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
2506{
2507 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2508 uint32_t scratch, tmp = 0;
2509 int r, i;
2510
2511 r = amdgpu_gfx_scratch_get(adev, &scratch);
2512 if (r) {
2513 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2514 return r;
2515 }
2516 WREG32(scratch, 0xCAFEDEAD);
2517
2518 r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
2519 if (r) {
2520 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2521 amdgpu_gfx_scratch_free(adev, scratch);
2522 return r;
2523 }
2524 /* unmap queues */
2525 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
2526 amdgpu_ring_write(kiq_ring,
2527 PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
2528 PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all queues */
2529 amdgpu_ring_write(kiq_ring, 0);
2530 amdgpu_ring_write(kiq_ring, 0);
2531 amdgpu_ring_write(kiq_ring, 0);
2532 amdgpu_ring_write(kiq_ring, 0);
2533 /* write to scratch for completion */
2534 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2535 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2536 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2537 amdgpu_ring_commit(kiq_ring);
2538
2539 for (i = 0; i < adev->usec_timeout; i++) {
2540 tmp = RREG32(scratch);
2541 if (tmp == 0xDEADBEEF)
2542 break;
2543 DRM_UDELAY(1);
2544 }
2545 if (i >= adev->usec_timeout) {
2546 DRM_ERROR("KCQ disable failed (scratch(0x%04X)=0x%08X)\n",
2547 scratch, tmp);
2548 r = -EINVAL;
2549 }
2550 amdgpu_gfx_scratch_free(adev, scratch);
2551
2552 return r;
2553}
2554
e322edc3 2555static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 2556{
33fb8698 2557 struct amdgpu_device *adev = ring->adev;
e322edc3 2558 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2559 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2560 uint32_t tmp;
2561
2562 mqd->header = 0xC0310800;
2563 mqd->compute_pipelinestat_enable = 0x00000001;
2564 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2565 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2566 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2567 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2568 mqd->compute_misc_reserved = 0x00000003;
2569
d72f2f46 2570 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 2571 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2572 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2573
2574 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2575 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6 2576 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
268cb4c7 2577 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
464826d6
XY		 2578
2579 mqd->cp_hqd_eop_control = tmp;
2580
2581 /* enable doorbell? */
5e78835a 2582 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2583
2584 if (ring->use_doorbell) {
2585 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2586 DOORBELL_OFFSET, ring->doorbell_index);
2587 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2588 DOORBELL_EN, 1);
2589 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2590 DOORBELL_SOURCE, 0);
2591 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2592 DOORBELL_HIT, 0);
2593 }
2594 else
2595 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2596 DOORBELL_EN, 0);
2597
2598 mqd->cp_hqd_pq_doorbell_control = tmp;
2599
2600 /* disable the queue if it's active */
2601 ring->wptr = 0;
2602 mqd->cp_hqd_dequeue_request = 0;
2603 mqd->cp_hqd_pq_rptr = 0;
2604 mqd->cp_hqd_pq_wptr_lo = 0;
2605 mqd->cp_hqd_pq_wptr_hi = 0;
2606
2607 /* set the pointer to the MQD */
33fb8698
AD		 2608 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2609 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 2610
2611 /* set MQD vmid to 0 */
5e78835a 2612 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 2613 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2614 mqd->cp_mqd_control = tmp;
2615
2616 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2617 hqd_gpu_addr = ring->gpu_addr >> 8;
2618 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2619 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2620
2621 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2622 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 2623 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2624 (order_base_2(ring->ring_size / 4) - 1));
2625 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2626 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2627#ifdef __BIG_ENDIAN
2628 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2629#endif
2630 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2631 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2632 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2633 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2634 mqd->cp_hqd_pq_control = tmp;
2635
2636 /* set the wb address whether it's enabled or not */
2637 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2638 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2639 mqd->cp_hqd_pq_rptr_report_addr_hi =
2640 upper_32_bits(wb_gpu_addr) & 0xffff;
2641
2642 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2643 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2644 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2645 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2646
2647 tmp = 0;
2648 /* enable the doorbell if requested */
2649 if (ring->use_doorbell) {
5e78835a 2650 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2651 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2652 DOORBELL_OFFSET, ring->doorbell_index);
2653
2654 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2655 DOORBELL_EN, 1);
2656 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2657 DOORBELL_SOURCE, 0);
2658 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2659 DOORBELL_HIT, 0);
2660 }
2661
2662 mqd->cp_hqd_pq_doorbell_control = tmp;
2663
2664 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2665 ring->wptr = 0;
0274a9c5 2666 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 2667
2668 /* set the vmid for the queue */
2669 mqd->cp_hqd_vmid = 0;
2670
0274a9c5 2671 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 2672 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2673 mqd->cp_hqd_persistent_state = tmp;
2674
fca4ce69
AD		 2675 /* set MIN_IB_AVAIL_SIZE */
2676 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2677 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2678 mqd->cp_hqd_ib_control = tmp;
2679
464826d6
XY		 2680 /* activate the queue */
2681 mqd->cp_hqd_active = 1;
2682
2683 return 0;
2684}
2685
e322edc3 2686static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2687{
33fb8698 2688 struct amdgpu_device *adev = ring->adev;
e322edc3 2689 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2690 int j;
2691
2692 /* disable wptr polling */
72edadd5 2693 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2694
5e78835a 2695 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2696 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2697 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2698 mqd->cp_hqd_eop_base_addr_hi);
2699
2700 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2701 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2702 mqd->cp_hqd_eop_control);
2703
2704 /* enable doorbell? */
5e78835a 2705 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2706 mqd->cp_hqd_pq_doorbell_control);
2707
2708 /* disable the queue if it's active */
5e78835a
TSD		 2709 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2710 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2711 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2712 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2713 break;
2714 udelay(1);
2715 }
5e78835a 2716 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2717 mqd->cp_hqd_dequeue_request);
5e78835a 2718 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2719 mqd->cp_hqd_pq_rptr);
5e78835a 2720 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2721 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2722 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2723 mqd->cp_hqd_pq_wptr_hi);
2724 }
2725
2726 /* set the pointer to the MQD */
5e78835a 2727 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2728 mqd->cp_mqd_base_addr_lo);
5e78835a 2729 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2730 mqd->cp_mqd_base_addr_hi);
2731
2732 /* set MQD vmid to 0 */
5e78835a 2733 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2734 mqd->cp_mqd_control);
2735
2736 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2737 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2738 mqd->cp_hqd_pq_base_lo);
5e78835a 2739 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2740 mqd->cp_hqd_pq_base_hi);
2741
2742 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2743 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2744 mqd->cp_hqd_pq_control);
2745
2746 /* set the wb address whether it's enabled or not */
5e78835a 2747 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2748 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2749 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2750 mqd->cp_hqd_pq_rptr_report_addr_hi);
2751
2752 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2753 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2754 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2755 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2756 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2757
2758 /* enable the doorbell if requested */
2759 if (ring->use_doorbell) {
5e78835a 2760 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2761 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2762 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2763 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2764 }
2765
5e78835a 2766 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2767 mqd->cp_hqd_pq_doorbell_control);
2768
2769 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2770 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2771 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2772 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2773 mqd->cp_hqd_pq_wptr_hi);
2774
2775 /* set the vmid for the queue */
5e78835a 2776 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2777
5e78835a 2778 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2779 mqd->cp_hqd_persistent_state);
2780
2781 /* activate the queue */
5e78835a 2782 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2783 mqd->cp_hqd_active);
2784
72edadd5
TSD		 2785 if (ring->use_doorbell)
2786 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2787
2788 return 0;
2789}
2790
e322edc3 2791static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2792{
2793 struct amdgpu_device *adev = ring->adev;
e322edc3 2794 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2795 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2796
898b7893 2797 gfx_v9_0_kiq_setting(ring);
464826d6 2798
ba0c19f5 2799 if (adev->gfx.in_reset) { /* for GPU_RESET case */
464826d6 2800 /* reset MQD to a clean status */
0ef376ca
AD		 2801 if (adev->gfx.mec.mqd_backup[mqd_idx])
2802 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
464826d6
XY		 2803
2804 /* reset ring buffer */
2805 ring->wptr = 0;
b98724db 2806 amdgpu_ring_clear_ring(ring);
464826d6 2807
898b7893
AD		 2808 mutex_lock(&adev->srbm_mutex);
2809 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2810 gfx_v9_0_kiq_init_register(ring);
2811 soc15_grbm_select(adev, 0, 0, 0, 0);
2812 mutex_unlock(&adev->srbm_mutex);
ba0c19f5
AD		 2813 } else {
2814 memset((void *)mqd, 0, sizeof(*mqd));
2815 mutex_lock(&adev->srbm_mutex);
2816 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2817 gfx_v9_0_mqd_init(ring);
2818 gfx_v9_0_kiq_init_register(ring);
2819 soc15_grbm_select(adev, 0, 0, 0, 0);
2820 mutex_unlock(&adev->srbm_mutex);
2821
2822 if (adev->gfx.mec.mqd_backup[mqd_idx])
2823 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
464826d6
XY		 2824 }
2825
0f1dfd52 2826 return 0;
898b7893
AD		 2827}
2828
2829static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2830{
2831 struct amdgpu_device *adev = ring->adev;
898b7893
AD		 2832 struct v9_mqd *mqd = ring->mqd_ptr;
2833 int mqd_idx = ring - &adev->gfx.compute_ring[0];
898b7893 2834
e30a5223 2835 if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
898b7893
AD		 2836 memset((void *)mqd, 0, sizeof(*mqd));
2837 mutex_lock(&adev->srbm_mutex);
2838 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2839 gfx_v9_0_mqd_init(ring);
2840 soc15_grbm_select(adev, 0, 0, 0, 0);
2841 mutex_unlock(&adev->srbm_mutex);
2842
2843 if (adev->gfx.mec.mqd_backup[mqd_idx])
2844 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
ba0c19f5 2845 } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
898b7893
AD		 2846 /* reset MQD to a clean status */
2847 if (adev->gfx.mec.mqd_backup[mqd_idx])
2848 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
2849
2850 /* reset ring buffer */
2851 ring->wptr = 0;
2852 amdgpu_ring_clear_ring(ring);
ba0c19f5
AD		 2853 } else {
2854 amdgpu_ring_clear_ring(ring);
898b7893
AD		 2855 }
2856
bd3402ea 2857 return 0;
464826d6
XY		 2858}
2859
2860static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2861{
2862 struct amdgpu_ring *ring = NULL;
2863 int r = 0, i;
2864
2865 gfx_v9_0_cp_compute_enable(adev, true);
2866
2867 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2868
2869 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2870 if (unlikely(r != 0))
2871 goto done;
2872
2873 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2874 if (!r) {
e322edc3 2875 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2876 amdgpu_bo_kunmap(ring->mqd_obj);
2877 ring->mqd_ptr = NULL;
464826d6 2878 }
e1d53aa8
AD		 2879 amdgpu_bo_unreserve(ring->mqd_obj);
2880 if (r)
2881 goto done;
464826d6
XY		 2882
2883 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2884 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2885
2886 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2887 if (unlikely(r != 0))
2888 goto done;
2889 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2890 if (!r) {
898b7893 2891 r = gfx_v9_0_kcq_init_queue(ring);
464826d6
XY		 2892 amdgpu_bo_kunmap(ring->mqd_obj);
2893 ring->mqd_ptr = NULL;
464826d6 2894 }
e1d53aa8
AD		 2895 amdgpu_bo_unreserve(ring->mqd_obj);
2896 if (r)
2897 goto done;
464826d6
XY		 2898 }
2899
0f1dfd52 2900 r = gfx_v9_0_kiq_kcq_enable(adev);
e1d53aa8
AD		 2901done:
2902 return r;
464826d6
XY		 2903}
2904
b1023571
KW		 2905static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2906{
bd3402ea 2907 int r, i;
b1023571
KW		 2908 struct amdgpu_ring *ring;
2909
2910 if (!(adev->flags & AMD_IS_APU))
2911 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2912
2913 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2914 /* legacy firmware loading */
2915 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2916 if (r)
2917 return r;
2918
2919 r = gfx_v9_0_cp_compute_load_microcode(adev);
2920 if (r)
2921 return r;
2922 }
2923
2924 r = gfx_v9_0_cp_gfx_resume(adev);
2925 if (r)
2926 return r;
2927
e30a5223 2928 r = gfx_v9_0_kiq_resume(adev);
b1023571
KW		 2929 if (r)
2930 return r;
2931
2932 ring = &adev->gfx.gfx_ring[0];
2933 r = amdgpu_ring_test_ring(ring);
2934 if (r) {
2935 ring->ready = false;
2936 return r;
2937 }
e30a5223
AD		 2938
2939 ring = &adev->gfx.kiq.ring;
2940 ring->ready = true;
2941 r = amdgpu_ring_test_ring(ring);
2942 if (r)
2943 ring->ready = false;
2944
b1023571
KW		 2945 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2946 ring = &adev->gfx.compute_ring[i];
2947
2948 ring->ready = true;
2949 r = amdgpu_ring_test_ring(ring);
2950 if (r)
2951 ring->ready = false;
2952 }
2953
2954 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2955
2956 return 0;
2957}
2958
2959static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2960{
2961 gfx_v9_0_cp_gfx_enable(adev, enable);
2962 gfx_v9_0_cp_compute_enable(adev, enable);
2963}
2964
2965static int gfx_v9_0_hw_init(void *handle)
2966{
2967 int r;
2968 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2969
2970 gfx_v9_0_init_golden_registers(adev);
2971
2972 gfx_v9_0_gpu_init(adev);
2973
2974 r = gfx_v9_0_rlc_resume(adev);
2975 if (r)
2976 return r;
2977
2978 r = gfx_v9_0_cp_resume(adev);
2979 if (r)
2980 return r;
2981
2982 r = gfx_v9_0_ngg_en(adev);
2983 if (r)
2984 return r;
2985
2986 return r;
2987}
2988
2989static int gfx_v9_0_hw_fini(void *handle)
2990{
2991 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2992
2993 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2994 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
464826d6
XY		 2995 if (amdgpu_sriov_vf(adev)) {
2996 pr_debug("For SRIOV client, shouldn't do anything.\n");
2997 return 0;
2998 }
e30a5223 2999 gfx_v9_0_kiq_kcq_disable(adev);
b1023571
KW		 3000 gfx_v9_0_cp_enable(adev, false);
3001 gfx_v9_0_rlc_stop(adev);
b1023571
KW		 3002
3003 return 0;
3004}
3005
3006static int gfx_v9_0_suspend(void *handle)
3007{
3008 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3009
e30a5223 3010 adev->gfx.in_suspend = true;
b1023571
KW		 3011 return gfx_v9_0_hw_fini(adev);
3012}
3013
3014static int gfx_v9_0_resume(void *handle)
3015{
3016 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e30a5223 3017 int r;
b1023571 3018
e30a5223
AD		 3019 r = gfx_v9_0_hw_init(adev);
3020 adev->gfx.in_suspend = false;
3021 return r;
b1023571
KW		 3022}
3023
3024static bool gfx_v9_0_is_idle(void *handle)
3025{
3026 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3027
5e78835a 3028 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 3029 GRBM_STATUS, GUI_ACTIVE))
3030 return false;
3031 else
3032 return true;
3033}
3034
3035static int gfx_v9_0_wait_for_idle(void *handle)
3036{
3037 unsigned i;
3038 u32 tmp;
3039 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3040
3041 for (i = 0; i < adev->usec_timeout; i++) {
3042 /* read MC_STATUS */
5e78835a 3043 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
b1023571
KW		 3044 GRBM_STATUS__GUI_ACTIVE_MASK;
3045
3046 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3047 return 0;
3048 udelay(1);
3049 }
3050 return -ETIMEDOUT;
3051}
3052
b1023571
KW		 3053static int gfx_v9_0_soft_reset(void *handle)
3054{
3055 u32 grbm_soft_reset = 0;
3056 u32 tmp;
3057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3058
3059 /* GRBM_STATUS */
5e78835a 3060 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 3061 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3062 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3063 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3064 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3065 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3066 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3067 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3068 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3069 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3070 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3071 }
3072
3073 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3074 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3075 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3076 }
3077
3078 /* GRBM_STATUS2 */
5e78835a 3079 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 3080 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3081 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3082 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3083
3084
75bac5c6 3085 if (grbm_soft_reset) {
b1023571
KW		 3086 /* stop the rlc */
3087 gfx_v9_0_rlc_stop(adev);
3088
3089 /* Disable GFX parsing/prefetching */
3090 gfx_v9_0_cp_gfx_enable(adev, false);
3091
3092 /* Disable MEC parsing/prefetching */
3093 gfx_v9_0_cp_compute_enable(adev, false);
3094
3095 if (grbm_soft_reset) {
5e78835a 3096 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3097 tmp |= grbm_soft_reset;
3098 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 3099 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3100 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3101
3102 udelay(50);
3103
3104 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 3105 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3106 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3107 }
3108
3109 /* Wait a little for things to settle down */
3110 udelay(50);
b1023571
KW		 3111 }
3112 return 0;
3113}
3114
3115static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3116{
3117 uint64_t clock;
3118
3119 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 3120 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3121 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3122 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 3123 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3124 return clock;
3125}
3126
3127static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3128 uint32_t vmid,
3129 uint32_t gds_base, uint32_t gds_size,
3130 uint32_t gws_base, uint32_t gws_size,
3131 uint32_t oa_base, uint32_t oa_size)
3132{
3133 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3134 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3135
3136 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3137 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3138
3139 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3140 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3141
3142 /* GDS Base */
3143 gfx_v9_0_write_data_to_reg(ring, 0, false,
3144 amdgpu_gds_reg_offset[vmid].mem_base,
3145 gds_base);
3146
3147 /* GDS Size */
3148 gfx_v9_0_write_data_to_reg(ring, 0, false,
3149 amdgpu_gds_reg_offset[vmid].mem_size,
3150 gds_size);
3151
3152 /* GWS */
3153 gfx_v9_0_write_data_to_reg(ring, 0, false,
3154 amdgpu_gds_reg_offset[vmid].gws,
3155 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3156
3157 /* OA */
3158 gfx_v9_0_write_data_to_reg(ring, 0, false,
3159 amdgpu_gds_reg_offset[vmid].oa,
3160 (1 << (oa_size + oa_base)) - (1 << oa_base));
3161}
3162
3163static int gfx_v9_0_early_init(void *handle)
3164{
3165 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3166
3167 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
78c16834 3168 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
b1023571
KW		 3169 gfx_v9_0_set_ring_funcs(adev);
3170 gfx_v9_0_set_irq_funcs(adev);
3171 gfx_v9_0_set_gds_init(adev);
3172 gfx_v9_0_set_rlc_funcs(adev);
3173
3174 return 0;
3175}
3176
3177static int gfx_v9_0_late_init(void *handle)
3178{
3179 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3180 int r;
3181
3182 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3183 if (r)
3184 return r;
3185
3186 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3187 if (r)
3188 return r;
3189
3190 return 0;
3191}
3192
3193static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3194{
3195 uint32_t rlc_setting, data;
3196 unsigned i;
3197
3198 if (adev->gfx.rlc.in_safe_mode)
3199 return;
3200
3201 /* if RLC is not enabled, do nothing */
5e78835a 3202 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3203 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3204 return;
3205
3206 if (adev->cg_flags &
3207 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3208 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3209 data = RLC_SAFE_MODE__CMD_MASK;
3210 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 3211 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3212
3213 /* wait for RLC_SAFE_MODE */
3214 for (i = 0; i < adev->usec_timeout; i++) {
3215 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3216 break;
3217 udelay(1);
3218 }
3219 adev->gfx.rlc.in_safe_mode = true;
3220 }
3221}
3222
3223static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3224{
3225 uint32_t rlc_setting, data;
3226
3227 if (!adev->gfx.rlc.in_safe_mode)
3228 return;
3229
3230 /* if RLC is not enabled, do nothing */
5e78835a 3231 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3232 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3233 return;
3234
3235 if (adev->cg_flags &
3236 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3237 /*
3238 * Try to exit safe mode only if it is already in safe
3239 * mode.
3240 */
3241 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 3242 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3243 adev->gfx.rlc.in_safe_mode = false;
3244 }
3245}
3246
197f95c8
HZ		 3247static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3248 bool enable)
3249{
3250 /* TODO: double check if we need to perform under safe mdoe */
3251 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3252
3253 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3254 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3255 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3256 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3257 } else {
3258 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3259 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3260 }
3261
3262 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3263}
3264
18924c71
HZ		 3265static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3266 bool enable)
3267{
3268 /* TODO: double check if we need to perform under safe mode */
3269 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3270
3271 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3272 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3273 else
3274 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3275
3276 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3277 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3278 else
3279 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3280
3281 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3282}
3283
b1023571
KW		 3284static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3285 bool enable)
3286{
3287 uint32_t data, def;
3288
3289 /* It is disabled by HW by default */
3290 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3291 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 3292 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3293 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3294 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3295 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3296 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3297
3298 /* only for Vega10 & Raven1 */
3299 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3300
3301 if (def != data)
5e78835a 3302 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3303
3304 /* MGLS is a global flag to control all MGLS in GFX */
3305 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3306 /* 2 - RLC memory Light sleep */
3307 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 3308 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3309 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3310 if (def != data)
5e78835a 3311 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3312 }
3313 /* 3 - CP memory Light sleep */
3314 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 3315 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3316 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3317 if (def != data)
5e78835a 3318 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3319 }
3320 }
3321 } else {
3322 /* 1 - MGCG_OVERRIDE */
5e78835a 3323 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3324 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3325 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3326 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3327 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3328 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3329 if (def != data)
5e78835a 3330 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3331
3332 /* 2 - disable MGLS in RLC */
5e78835a 3333 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3334 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3335 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 3336 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3337 }
3338
3339 /* 3 - disable MGLS in CP */
5e78835a 3340 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3341 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3342 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 3343 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3344 }
3345 }
3346}
3347
3348static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3349 bool enable)
3350{
3351 uint32_t data, def;
3352
3353 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3354
3355 /* Enable 3D CGCG/CGLS */
3356 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3357 /* write cmd to clear cgcg/cgls ov */
5e78835a 3358 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3359 /* unset CGCG override */
3360 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3361 /* update CGCG and CGLS override bits */
3362 if (def != data)
5e78835a 3363 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 3364 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 3365 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3366 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3367 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3368 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3369 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3370 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3371 if (def != data)
5e78835a 3372 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3373
3374 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3375 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3376 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3377 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3378 if (def != data)
5e78835a 3379 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 3380 } else {
3381 /* Disable CGCG/CGLS */
5e78835a 3382 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3383 /* disable cgcg, cgls should be disabled */
3384 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3385 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3386 /* disable cgcg and cgls in FSM */
3387 if (def != data)
5e78835a 3388 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3389 }
3390
3391 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3392}
3393
3394static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3395 bool enable)
3396{
3397 uint32_t def, data;
3398
3399 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3400
3401 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 3402 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3403 /* unset CGCG override */
3404 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3405 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3406 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3407 else
3408 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3409 /* update CGCG and CGLS override bits */
3410 if (def != data)
5e78835a 3411 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3412
3413 /* enable cgcg FSM(0x0020003F) */
5e78835a 3414 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3415 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3416 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3417 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3418 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3419 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3420 if (def != data)
5e78835a 3421 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3422
3423 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3424 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3425 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3426 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3427 if (def != data)
5e78835a 3428 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 3429 } else {
5e78835a 3430 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3431 /* reset CGCG/CGLS bits */
3432 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3433 /* disable cgcg and cgls in FSM */
3434 if (def != data)
5e78835a 3435 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3436 }
3437
3438 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3439}
3440
3441static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3442 bool enable)
3443{
3444 if (enable) {
3445 /* CGCG/CGLS should be enabled after MGCG/MGLS
3446 * === MGCG + MGLS ===
3447 */
3448 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3449 /* === CGCG /CGLS for GFX 3D Only === */
3450 gfx_v9_0_update_3d_clock_gating(adev, enable);
3451 /* === CGCG + CGLS === */
3452 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3453 } else {
3454 /* CGCG/CGLS should be disabled before MGCG/MGLS
3455 * === CGCG + CGLS ===
3456 */
3457 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3458 /* === CGCG /CGLS for GFX 3D Only === */
3459 gfx_v9_0_update_3d_clock_gating(adev, enable);
3460 /* === MGCG + MGLS === */
3461 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3462 }
3463 return 0;
3464}
3465
3466static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3467 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3468 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3469};
3470
3471static int gfx_v9_0_set_powergating_state(void *handle,
3472 enum amd_powergating_state state)
3473{
5897c99e 3474 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197f95c8 3475 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
5897c99e
HZ		 3476
3477 switch (adev->asic_type) {
3478 case CHIP_RAVEN:
3479 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3480 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3481 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3482 } else {
3483 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3484 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3485 }
3486
3487 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3488 gfx_v9_0_enable_cp_power_gating(adev, true);
3489 else
3490 gfx_v9_0_enable_cp_power_gating(adev, false);
197f95c8
HZ		 3491
3492 /* update gfx cgpg state */
3493 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
18924c71
HZ		 3494
3495 /* update mgcg state */
3496 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5897c99e
HZ		 3497 break;
3498 default:
3499 break;
3500 }
3501
b1023571
KW		 3502 return 0;
3503}
3504
3505static int gfx_v9_0_set_clockgating_state(void *handle,
3506 enum amd_clockgating_state state)
3507{
3508 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3509
fb82afab
XY		 3510 if (amdgpu_sriov_vf(adev))
3511 return 0;
3512
b1023571
KW		 3513 switch (adev->asic_type) {
3514 case CHIP_VEGA10:
a4dc61f5 3515 case CHIP_RAVEN:
b1023571
KW		 3516 gfx_v9_0_update_gfx_clock_gating(adev,
3517 state == AMD_CG_STATE_GATE ? true : false);
3518 break;
3519 default:
3520 break;
3521 }
3522 return 0;
3523}
3524
12ad27fa
HR		 3525static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3526{
3527 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3528 int data;
3529
3530 if (amdgpu_sriov_vf(adev))
3531 *flags = 0;
3532
3533 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 3534 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 3535 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3536 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3537
3538 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 3539 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 3540 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3541 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3542
3543 /* AMD_CG_SUPPORT_GFX_CGLS */
3544 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3545 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3546
3547 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 3548 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 3549 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3550 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3551
3552 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 3553 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 3554 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3555 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3556
3557 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 3558 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 3559 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3560 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3561
3562 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3563 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3564 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3565}
3566
b1023571
KW		 3567static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3568{
3569 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3570}
3571
3572static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3573{
3574 struct amdgpu_device *adev = ring->adev;
3575 u64 wptr;
3576
3577 /* XXX check if swapping is necessary on BE */
3578 if (ring->use_doorbell) {
3579 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3580 } else {
5e78835a
TSD		 3581 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3582 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 3583 }
3584
3585 return wptr;
3586}
3587
3588static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3589{
3590 struct amdgpu_device *adev = ring->adev;
3591
3592 if (ring->use_doorbell) {
3593 /* XXX check if swapping is necessary on BE */
3594 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3595 WDOORBELL64(ring->doorbell_index, ring->wptr);
3596 } else {
5e78835a
TSD		 3597 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3598 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 3599 }
3600}
3601
3602static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3603{
3604 u32 ref_and_mask, reg_mem_engine;
3605 struct nbio_hdp_flush_reg *nbio_hf_reg;
3606
3607 if (ring->adev->asic_type == CHIP_VEGA10)
3608 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3609
3610 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3611 switch (ring->me) {
3612 case 1:
3613 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3614 break;
3615 case 2:
3616 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3617 break;
3618 default:
3619 return;
3620 }
3621 reg_mem_engine = 0;
3622 } else {
3623 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3624 reg_mem_engine = 1; /* pfp */
3625 }
3626
3627 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3628 nbio_hf_reg->hdp_flush_req_offset,
3629 nbio_hf_reg->hdp_flush_done_offset,
3630 ref_and_mask, ref_and_mask, 0x20);
3631}
3632
3633static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3634{
3635 gfx_v9_0_write_data_to_reg(ring, 0, true,
3636 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3637}
3638
3639static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3640 struct amdgpu_ib *ib,
3641 unsigned vm_id, bool ctx_switch)
3642{
eaa05d52 3643 u32 header, control = 0;
b1023571 3644
eaa05d52
ML		 3645 if (ib->flags & AMDGPU_IB_FLAG_CE)
3646 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3647 else
3648 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
b1023571 3649
eaa05d52 3650 control |= ib->length_dw | (vm_id << 24);
b1023571 3651
635e7132 3652 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
eaa05d52 3653 control |= INDIRECT_BUFFER_PRE_ENB(1);
9ccd52eb 3654
635e7132
ML		 3655 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3656 gfx_v9_0_ring_emit_de_meta(ring);
3657 }
3658
eaa05d52
ML		 3659 amdgpu_ring_write(ring, header);
3660BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3661 amdgpu_ring_write(ring,
b1023571 3662#ifdef __BIG_ENDIAN
eaa05d52 3663 (2 << 0) |
b1023571 3664#endif
eaa05d52
ML		 3665 lower_32_bits(ib->gpu_addr));
3666 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3667 amdgpu_ring_write(ring, control);
b1023571
KW		 3668}
3669
b1023571
KW		 3670static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3671 struct amdgpu_ib *ib,
3672 unsigned vm_id, bool ctx_switch)
3673{
3674 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3675
3676 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3677 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3678 amdgpu_ring_write(ring,
3679#ifdef __BIG_ENDIAN
3680 (2 << 0) |
3681#endif
3682 lower_32_bits(ib->gpu_addr));
3683 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3684 amdgpu_ring_write(ring, control);
3685}
3686
3687static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3688 u64 seq, unsigned flags)
3689{
3690 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3691 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3692
3693 /* RELEASE_MEM - flush caches, send int */
3694 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3695 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3696 EOP_TC_ACTION_EN |
3697 EOP_TC_WB_ACTION_EN |
3698 EOP_TC_MD_ACTION_EN |
3699 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3700 EVENT_INDEX(5)));
3701 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3702
3703 /*
3704 * the address should be Qword aligned if 64bit write, Dword
3705 * aligned if only send 32bit data low (discard data high)
3706 */
3707 if (write64bit)
3708 BUG_ON(addr & 0x7);
3709 else
3710 BUG_ON(addr & 0x3);
3711 amdgpu_ring_write(ring, lower_32_bits(addr));
3712 amdgpu_ring_write(ring, upper_32_bits(addr));
3713 amdgpu_ring_write(ring, lower_32_bits(seq));
3714 amdgpu_ring_write(ring, upper_32_bits(seq));
3715 amdgpu_ring_write(ring, 0);
3716}
3717
3718static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3719{
3720 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3721 uint32_t seq = ring->fence_drv.sync_seq;
3722 uint64_t addr = ring->fence_drv.gpu_addr;
3723
3724 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3725 lower_32_bits(addr), upper_32_bits(addr),
3726 seq, 0xffffffff, 4);
3727}
3728
3729static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3730 unsigned vm_id, uint64_t pd_addr)
3731{
2e819849 3732 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
b1023571 3733 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 3734 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 3735 unsigned eng = ring->vm_inv_eng;
b1023571 3736
b1166325
CK		 3737 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3738 pd_addr |= AMDGPU_PTE_VALID;
b1023571 3739
2e819849
CK		 3740 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3741 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3742 lower_32_bits(pd_addr));
b1023571 3743
2e819849
CK		 3744 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3745 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3746 upper_32_bits(pd_addr));
b1023571 3747
2e819849
CK		 3748 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3749 hub->vm_inv_eng0_req + eng, req);
b1023571 3750
2e819849
CK		 3751 /* wait for the invalidate to complete */
3752 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3753 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
b1023571
KW		 3754
3755 /* compute doesn't have PFP */
3756 if (usepfp) {
3757 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3758 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3759 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3760 }
3761}
3762
3763static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3764{
3765 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3766}
3767
3768static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3769{
3770 u64 wptr;
3771
3772 /* XXX check if swapping is necessary on BE */
3773 if (ring->use_doorbell)
3774 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3775 else
3776 BUG();
3777 return wptr;
3778}
3779
3780static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3781{
3782 struct amdgpu_device *adev = ring->adev;
3783
3784 /* XXX check if swapping is necessary on BE */
3785 if (ring->use_doorbell) {
3786 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3787 WDOORBELL64(ring->doorbell_index, ring->wptr);
3788 } else{
3789 BUG(); /* only DOORBELL method supported on gfx9 now */
3790 }
3791}
3792
aa6faa44
XY		 3793static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3794 u64 seq, unsigned int flags)
3795{
3796 /* we only allocate 32bit for each seq wb address */
3797 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3798
3799 /* write fence seq to the "addr" */
3800 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3801 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3802 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3803 amdgpu_ring_write(ring, lower_32_bits(addr));
3804 amdgpu_ring_write(ring, upper_32_bits(addr));
3805 amdgpu_ring_write(ring, lower_32_bits(seq));
3806
3807 if (flags & AMDGPU_FENCE_FLAG_INT) {
3808 /* set register to trigger INT */
3809 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3810 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3811 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3812 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3813 amdgpu_ring_write(ring, 0);
3814 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3815 }
3816}
3817
b1023571
KW		 3818static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3819{
3820 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3821 amdgpu_ring_write(ring, 0);
3822}
3823
cca02cd3
XY		 3824static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3825{
3826 static struct v9_ce_ib_state ce_payload = {0};
3827 uint64_t csa_addr;
3828 int cnt;
3829
3830 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3831 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3832
3833 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3834 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3835 WRITE_DATA_DST_SEL(8) |
3836 WR_CONFIRM) |
3837 WRITE_DATA_CACHE_POLICY(0));
3838 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3839 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3840 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3841}
3842
3843static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3844{
3845 static struct v9_de_ib_state de_payload = {0};
3846 uint64_t csa_addr, gds_addr;
3847 int cnt;
3848
3849 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3850 gds_addr = csa_addr + 4096;
3851 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3852 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3853
3854 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3855 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3856 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3857 WRITE_DATA_DST_SEL(8) |
3858 WR_CONFIRM) |
3859 WRITE_DATA_CACHE_POLICY(0));
3860 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3861 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3862 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3863}
3864
b1023571
KW		 3865static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3866{
3867 uint32_t dw2 = 0;
3868
cca02cd3
XY		 3869 if (amdgpu_sriov_vf(ring->adev))
3870 gfx_v9_0_ring_emit_ce_meta(ring);
3871
b1023571
KW		 3872 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3873 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3874 /* set load_global_config & load_global_uconfig */
3875 dw2 |= 0x8001;
3876 /* set load_cs_sh_regs */
3877 dw2 |= 0x01000000;
3878 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3879 dw2 |= 0x10002;
3880
3881 /* set load_ce_ram if preamble presented */
3882 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3883 dw2 |= 0x10000000;
3884 } else {
3885 /* still load_ce_ram if this is the first time preamble presented
3886 * although there is no context switch happens.
3887 */
3888 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3889 dw2 |= 0x10000000;
3890 }
3891
3892 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3893 amdgpu_ring_write(ring, dw2);
3894 amdgpu_ring_write(ring, 0);
3895}
3896
9a5e02b5
ML		 3897static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3898{
3899 unsigned ret;
3900 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3901 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3902 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3903 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3904 ret = ring->wptr & ring->buf_mask;
3905 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3906 return ret;
3907}
3908
3909static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3910{
3911 unsigned cur;
3912 BUG_ON(offset > ring->buf_mask);
3913 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3914
3915 cur = (ring->wptr & ring->buf_mask) - 1;
3916 if (likely(cur > offset))
3917 ring->ring[offset] = cur - offset;
3918 else
3919 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3920}
3921
3b4d68e9
ML		 3922static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3923{
3924 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3925 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3926}
3927
aa6faa44
XY		 3928static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3929{
3930 struct amdgpu_device *adev = ring->adev;
3931
3932 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3933 amdgpu_ring_write(ring, 0 | /* src: register*/
3934 (5 << 8) | /* dst: memory */
3935 (1 << 20)); /* write confirm */
3936 amdgpu_ring_write(ring, reg);
3937 amdgpu_ring_write(ring, 0);
3938 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3939 adev->virt.reg_val_offs * 4));
3940 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3941 adev->virt.reg_val_offs * 4));
3942}
3943
3944static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3945 uint32_t val)
3946{
3947 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3948 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3949 amdgpu_ring_write(ring, reg);
3950 amdgpu_ring_write(ring, 0);
3951 amdgpu_ring_write(ring, val);
3952}
3953
b1023571
KW		 3954static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3955 enum amdgpu_interrupt_state state)
3956{
b1023571
KW		 3957 switch (state) {
3958 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3959 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 3960 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3961 TIME_STAMP_INT_ENABLE,
3962 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3963 break;
3964 default:
3965 break;
3966 }
3967}
3968
3969static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3970 int me, int pipe,
3971 enum amdgpu_interrupt_state state)
3972{
d0c55cdf 3973 u32 mec_int_cntl, mec_int_cntl_reg;
b1023571 3974
d0c55cdf
AD		 3975 /*
3976 * amdgpu controls only the first MEC. That's why this function only
3977 * handles the setting of interrupts for this specific MEC. All other
3978 * pipes' interrupts are set by amdkfd.
3979 */
3980
3981 if (me == 1) {
3982 switch (pipe) {
3983 case 0:
3984 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3985 break;
3986 case 1:
3987 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
3988 break;
3989 case 2:
3990 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
3991 break;
3992 case 3:
3993 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
3994 break;
3995 default:
3996 DRM_DEBUG("invalid pipe %d\n", pipe);
3997 return;
3998 }
3999 } else {
4000 DRM_DEBUG("invalid me %d\n", me);
763a47b8 4001 return;
b1023571 4002 }
763a47b8 4003
d0c55cdf
AD		 4004 switch (state) {
4005 case AMDGPU_IRQ_STATE_DISABLE:
4006 mec_int_cntl = RREG32(mec_int_cntl_reg);
4007 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4008 TIME_STAMP_INT_ENABLE, 0);
4009 WREG32(mec_int_cntl_reg, mec_int_cntl);
4010 break;
4011 case AMDGPU_IRQ_STATE_ENABLE:
4012 mec_int_cntl = RREG32(mec_int_cntl_reg);
4013 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4014 TIME_STAMP_INT_ENABLE, 1);
4015 WREG32(mec_int_cntl_reg, mec_int_cntl);
4016 break;
4017 default:
4018 break;
4019 }
b1023571
KW		 4020}
4021
4022static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4023 struct amdgpu_irq_src *source,
4024 unsigned type,
4025 enum amdgpu_interrupt_state state)
4026{
b1023571
KW		 4027 switch (state) {
4028 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4029 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 4030 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4031 PRIV_REG_INT_ENABLE,
4032 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4033 break;
4034 default:
4035 break;
4036 }
4037
4038 return 0;
4039}
4040
4041static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4042 struct amdgpu_irq_src *source,
4043 unsigned type,
4044 enum amdgpu_interrupt_state state)
4045{
b1023571
KW		 4046 switch (state) {
4047 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4048 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 4049 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4050 PRIV_INSTR_INT_ENABLE,
4051 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4052 default:
4053 break;
4054 }
4055
4056 return 0;
4057}
4058
4059static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4060 struct amdgpu_irq_src *src,
4061 unsigned type,
4062 enum amdgpu_interrupt_state state)
4063{
4064 switch (type) {
4065 case AMDGPU_CP_IRQ_GFX_EOP:
4066 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4067 break;
4068 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4069 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4070 break;
4071 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4072 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4073 break;
4074 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4075 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4076 break;
4077 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4078 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4079 break;
4080 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4081 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4082 break;
4083 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4084 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4085 break;
4086 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4087 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4088 break;
4089 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4090 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4091 break;
4092 default:
4093 break;
4094 }
4095 return 0;
4096}
4097
4098static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4099 struct amdgpu_irq_src *source,
4100 struct amdgpu_iv_entry *entry)
4101{
4102 int i;
4103 u8 me_id, pipe_id, queue_id;
4104 struct amdgpu_ring *ring;
4105
4106 DRM_DEBUG("IH: CP EOP\n");
4107 me_id = (entry->ring_id & 0x0c) >> 2;
4108 pipe_id = (entry->ring_id & 0x03) >> 0;
4109 queue_id = (entry->ring_id & 0x70) >> 4;
4110
4111 switch (me_id) {
4112 case 0:
4113 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4114 break;
4115 case 1:
4116 case 2:
4117 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4118 ring = &adev->gfx.compute_ring[i];
4119 /* Per-queue interrupt is supported for MEC starting from VI.
4120 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4121 */
4122 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4123 amdgpu_fence_process(ring);
4124 }
4125 break;
4126 }
4127 return 0;
4128}
4129
4130static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4131 struct amdgpu_irq_src *source,
4132 struct amdgpu_iv_entry *entry)
4133{
4134 DRM_ERROR("Illegal register access in command stream\n");
4135 schedule_work(&adev->reset_work);
4136 return 0;
4137}
4138
4139static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4140 struct amdgpu_irq_src *source,
4141 struct amdgpu_iv_entry *entry)
4142{
4143 DRM_ERROR("Illegal instruction in command stream\n");
4144 schedule_work(&adev->reset_work);
4145 return 0;
4146}
4147
97031e25
XY		 4148static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4149 struct amdgpu_irq_src *src,
4150 unsigned int type,
4151 enum amdgpu_interrupt_state state)
4152{
4153 uint32_t tmp, target;
1c4ecf48 4154 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4155
4156 if (ring->me == 1)
4157 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4158 else
4159 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4160 target += ring->pipe;
4161
4162 switch (type) {
4163 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4164 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 4165 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4166 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4167 GENERIC2_INT_ENABLE, 0);
5e78835a 4168 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4169
4170 tmp = RREG32(target);
4171 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4172 GENERIC2_INT_ENABLE, 0);
4173 WREG32(target, tmp);
4174 } else {
5e78835a 4175 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4176 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4177 GENERIC2_INT_ENABLE, 1);
5e78835a 4178 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4179
4180 tmp = RREG32(target);
4181 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4182 GENERIC2_INT_ENABLE, 1);
4183 WREG32(target, tmp);
4184 }
4185 break;
4186 default:
4187 BUG(); /* kiq only support GENERIC2_INT now */
4188 break;
4189 }
4190 return 0;
4191}
4192
4193static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4194 struct amdgpu_irq_src *source,
4195 struct amdgpu_iv_entry *entry)
4196{
4197 u8 me_id, pipe_id, queue_id;
1c4ecf48 4198 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4199
4200 me_id = (entry->ring_id & 0x0c) >> 2;
4201 pipe_id = (entry->ring_id & 0x03) >> 0;
4202 queue_id = (entry->ring_id & 0x70) >> 4;
4203 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4204 me_id, pipe_id, queue_id);
4205
4206 amdgpu_fence_process(ring);
4207 return 0;
4208}
4209
b1023571
KW		 4210const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4211 .name = "gfx_v9_0",
4212 .early_init = gfx_v9_0_early_init,
4213 .late_init = gfx_v9_0_late_init,
4214 .sw_init = gfx_v9_0_sw_init,
4215 .sw_fini = gfx_v9_0_sw_fini,
4216 .hw_init = gfx_v9_0_hw_init,
4217 .hw_fini = gfx_v9_0_hw_fini,
4218 .suspend = gfx_v9_0_suspend,
4219 .resume = gfx_v9_0_resume,
4220 .is_idle = gfx_v9_0_is_idle,
4221 .wait_for_idle = gfx_v9_0_wait_for_idle,
4222 .soft_reset = gfx_v9_0_soft_reset,
4223 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4224 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 4225 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 4226};
4227
4228static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4229 .type = AMDGPU_RING_TYPE_GFX,
4230 .align_mask = 0xff,
4231 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4232 .support_64bit_ptrs = true,
0eeb68b3 4233 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4234 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4235 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4236 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 4237 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4238 5 + /* COND_EXEC */
4239 7 + /* PIPELINE_SYNC */
2e819849 4240 24 + /* VM_FLUSH */
e9d672b2
ML		 4241 8 + /* FENCE for VM_FLUSH */
4242 20 + /* GDS switch */
4243 4 + /* double SWITCH_BUFFER,
4244 the first COND_EXEC jump to the place just
4245 prior to this double SWITCH_BUFFER */
4246 5 + /* COND_EXEC */
4247 7 + /* HDP_flush */
4248 4 + /* VGT_flush */
4249 14 + /* CE_META */
4250 31 + /* DE_META */
4251 3 + /* CNTX_CTRL */
4252 5 + /* HDP_INVL */
4253 8 + 8 + /* FENCE x2 */
4254 2, /* SWITCH_BUFFER */
b1023571
KW		 4255 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4256 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4257 .emit_fence = gfx_v9_0_ring_emit_fence,
4258 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4259 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4260 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4261 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4262 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4263 .test_ring = gfx_v9_0_ring_test_ring,
4264 .test_ib = gfx_v9_0_ring_test_ib,
4265 .insert_nop = amdgpu_ring_insert_nop,
4266 .pad_ib = amdgpu_ring_generic_pad_ib,
4267 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4268 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 4269 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4270 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3b4d68e9 4271 .emit_tmz = gfx_v9_0_ring_emit_tmz,
b1023571
KW		 4272};
4273
4274static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4275 .type = AMDGPU_RING_TYPE_COMPUTE,
4276 .align_mask = 0xff,
4277 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4278 .support_64bit_ptrs = true,
0eeb68b3 4279 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4280 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4281 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4282 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4283 .emit_frame_size =
4284 20 + /* gfx_v9_0_ring_emit_gds_switch */
4285 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4286 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4287 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4288 24 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 4289 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4290 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4291 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4292 .emit_fence = gfx_v9_0_ring_emit_fence,
4293 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4294 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4295 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4296 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4297 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4298 .test_ring = gfx_v9_0_ring_test_ring,
4299 .test_ib = gfx_v9_0_ring_test_ib,
4300 .insert_nop = amdgpu_ring_insert_nop,
4301 .pad_ib = amdgpu_ring_generic_pad_ib,
4302};
4303
aa6faa44
XY		 4304static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4305 .type = AMDGPU_RING_TYPE_KIQ,
4306 .align_mask = 0xff,
4307 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4308 .support_64bit_ptrs = true,
0eeb68b3 4309 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 4310 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4311 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4312 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4313 .emit_frame_size =
4314 20 + /* gfx_v9_0_ring_emit_gds_switch */
4315 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4316 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4317 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4318 24 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 4319 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4320 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4321 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4322 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 4323 .test_ring = gfx_v9_0_ring_test_ring,
4324 .test_ib = gfx_v9_0_ring_test_ib,
4325 .insert_nop = amdgpu_ring_insert_nop,
4326 .pad_ib = amdgpu_ring_generic_pad_ib,
4327 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4328 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4329};
b1023571
KW		 4330
4331static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4332{
4333 int i;
4334
aa6faa44
XY		 4335 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4336
b1023571
KW		 4337 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4338 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4339
4340 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4341 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4342}
4343
97031e25
XY		 4344static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4345 .set = gfx_v9_0_kiq_set_interrupt_state,
4346 .process = gfx_v9_0_kiq_irq,
4347};
4348
b1023571
KW		 4349static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4350 .set = gfx_v9_0_set_eop_interrupt_state,
4351 .process = gfx_v9_0_eop_irq,
4352};
4353
4354static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4355 .set = gfx_v9_0_set_priv_reg_fault_state,
4356 .process = gfx_v9_0_priv_reg_irq,
4357};
4358
4359static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4360 .set = gfx_v9_0_set_priv_inst_fault_state,
4361 .process = gfx_v9_0_priv_inst_irq,
4362};
4363
4364static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4365{
4366 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4367 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4368
4369 adev->gfx.priv_reg_irq.num_types = 1;
4370 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4371
4372 adev->gfx.priv_inst_irq.num_types = 1;
4373 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 4374
4375 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4376 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 4377}
4378
4379static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4380{
4381 switch (adev->asic_type) {
4382 case CHIP_VEGA10:
a4dc61f5 4383 case CHIP_RAVEN:
b1023571
KW		 4384 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4385 break;
4386 default:
4387 break;
4388 }
4389}
4390
4391static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4392{
4393 /* init asci gds info */
5e78835a 4394 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 4395 adev->gds.gws.total_size = 64;
4396 adev->gds.oa.total_size = 16;
4397
4398 if (adev->gds.mem.total_size == 64 * 1024) {
4399 adev->gds.mem.gfx_partition_size = 4096;
4400 adev->gds.mem.cs_partition_size = 4096;
4401
4402 adev->gds.gws.gfx_partition_size = 4;
4403 adev->gds.gws.cs_partition_size = 4;
4404
4405 adev->gds.oa.gfx_partition_size = 4;
4406 adev->gds.oa.cs_partition_size = 1;
4407 } else {
4408 adev->gds.mem.gfx_partition_size = 1024;
4409 adev->gds.mem.cs_partition_size = 1024;
4410
4411 adev->gds.gws.gfx_partition_size = 16;
4412 adev->gds.gws.cs_partition_size = 16;
4413
4414 adev->gds.oa.gfx_partition_size = 4;
4415 adev->gds.oa.cs_partition_size = 4;
4416 }
4417}
4418
4419static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4420{
4421 u32 data, mask;
4422
5e78835a
TSD		 4423 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4424 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 4425
4426 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4427 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4428
378506a7 4429 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
b1023571
KW		 4430
4431 return (~data) & mask;
4432}
4433
4434static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4435 struct amdgpu_cu_info *cu_info)
4436{
4437 int i, j, k, counter, active_cu_number = 0;
4438 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4439
4440 if (!adev || !cu_info)
4441 return -EINVAL;
4442
b1023571
KW		 4443 mutex_lock(&adev->grbm_idx_mutex);
4444 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4445 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4446 mask = 1;
4447 ao_bitmap = 0;
4448 counter = 0;
4449 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4450 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4451 cu_info->bitmap[i][j] = bitmap;
4452
fe723cd3 4453 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
b1023571 4454 if (bitmap & mask) {
fe723cd3 4455 if (counter < adev->gfx.config.max_cu_per_sh)
b1023571
KW		 4456 ao_bitmap |= mask;
4457 counter ++;
4458 }
4459 mask <<= 1;
4460 }
4461 active_cu_number += counter;
4462 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4463 }
4464 }
4465 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4466 mutex_unlock(&adev->grbm_idx_mutex);
4467
4468 cu_info->number = active_cu_number;
4469 cu_info->ao_cu_mask = ao_cu_mask;
4470
4471 return 0;
4472}
4473
b1023571
KW		 4474const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4475{
4476 .type = AMD_IP_BLOCK_TYPE_GFX,
4477 .major = 9,
4478 .minor = 0,
4479 .rev = 0,
4480 .funcs = &gfx_v9_0_ip_funcs,
4481};
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