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amdgpu/soc15: make the pcie index/data registers constant.
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
248a1d6f 24#include <drm/drmP.h>
b1023571
KW		 25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
268cb4c7 41#define GFX9_MEC_HPD_SIZE 2048
6bce4667
HZ		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
b1023571 45
91d3130a
HZ		 46#define mmPWR_MISC_CNTL_STATUS 0x0183
47#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
b1023571
KW		 52
53MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
060d124b
CZ		 60MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62MODULE_FIRMWARE("amdgpu/raven_me.bin");
63MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
b1023571
KW		 67static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
68{
35c32f20
TSD		 69 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
73 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
77 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
81 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
85 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
86 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
87 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
88 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
89 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
90 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
91 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
92 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
93 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
94 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
95 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
96 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
97 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
98 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
99 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
100 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
101 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
102 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
103 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
104 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
105 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
106 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
107 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
108 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
109 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
110 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
111 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
112 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
113 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
114 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
115 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
116 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
117 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
118 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
119 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
120 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
121 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
122 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
123 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
124 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
125 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
126 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
127 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
128 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
129 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
130 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
131 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
132 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
b1023571
KW		 133};
134
135static const u32 golden_settings_gc_9_0[] =
136{
f8af9332
KW		 137 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
138 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
139 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
140 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
141 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
142 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
b1023571
KW		 143 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
144 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
145 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
f8af9332
KW		 146 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
147 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
148 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
149 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
150 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
ba219b3c 151 SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
f8af9332 152 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
ba219b3c 153 SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
b1023571
KW		 154 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
155 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
156 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
f8af9332
KW		 157 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
158 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
159 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
b1023571
KW		 160};
161
162static const u32 golden_settings_gc_9_0_vg10[] =
163{
164 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
165 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
166 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
167 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
168 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
169 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
f8af9332 170 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
b1023571
KW		 171};
172
a5fdb336
CZ		 173static const u32 golden_settings_gc_9_1[] =
174{
175 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
01b5cc36
HZ		 176 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
177 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
178 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 179 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
180 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
01b5cc36 181 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 182 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
183 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
184 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
01b5cc36
HZ		 185 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
186 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
187 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
188 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
189 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 190 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
191 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
192 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
01b5cc36
HZ		 193 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
194 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
195 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
a5fdb336
CZ		 196};
197
198static const u32 golden_settings_gc_9_1_rv1[] =
199{
7b6ba9ea
HZ		 200 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
201 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
202 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
203 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
204 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
205 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
a5fdb336 206 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
b1023571
KW		 207};
208
209#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
7b6ba9ea 210#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
b1023571
KW		 211
212static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
213static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
214static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
215static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
216static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
217 struct amdgpu_cu_info *cu_info);
218static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
219static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
635e7132 220static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
b1023571
KW		 221
222static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
223{
224 switch (adev->asic_type) {
225 case CHIP_VEGA10:
226 amdgpu_program_register_sequence(adev,
227 golden_settings_gc_9_0,
228 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
229 amdgpu_program_register_sequence(adev,
230 golden_settings_gc_9_0_vg10,
231 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
232 break;
a5fdb336
CZ		 233 case CHIP_RAVEN:
234 amdgpu_program_register_sequence(adev,
235 golden_settings_gc_9_1,
236 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
237 amdgpu_program_register_sequence(adev,
238 golden_settings_gc_9_1_rv1,
239 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
240 break;
b1023571
KW		 241 default:
242 break;
243 }
244}
245
246static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
247{
6a05148f 248 adev->gfx.scratch.num_reg = 8;
b1023571
KW		 249 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
250 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
251}
252
253static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
254 bool wc, uint32_t reg, uint32_t val)
255{
256 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
257 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
258 WRITE_DATA_DST_SEL(0) |
259 (wc ? WR_CONFIRM : 0));
260 amdgpu_ring_write(ring, reg);
261 amdgpu_ring_write(ring, 0);
262 amdgpu_ring_write(ring, val);
263}
264
265static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
266 int mem_space, int opt, uint32_t addr0,
267 uint32_t addr1, uint32_t ref, uint32_t mask,
268 uint32_t inv)
269{
270 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
271 amdgpu_ring_write(ring,
272 /* memory (1) or register (0) */
273 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
274 WAIT_REG_MEM_OPERATION(opt) | /* wait */
275 WAIT_REG_MEM_FUNCTION(3) | /* equal */
276 WAIT_REG_MEM_ENGINE(eng_sel)));
277
278 if (mem_space)
279 BUG_ON(addr0 & 0x3); /* Dword align */
280 amdgpu_ring_write(ring, addr0);
281 amdgpu_ring_write(ring, addr1);
282 amdgpu_ring_write(ring, ref);
283 amdgpu_ring_write(ring, mask);
284 amdgpu_ring_write(ring, inv); /* poll interval */
285}
286
287static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
288{
289 struct amdgpu_device *adev = ring->adev;
290 uint32_t scratch;
291 uint32_t tmp = 0;
292 unsigned i;
293 int r;
294
295 r = amdgpu_gfx_scratch_get(adev, &scratch);
296 if (r) {
297 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
298 return r;
299 }
300 WREG32(scratch, 0xCAFEDEAD);
301 r = amdgpu_ring_alloc(ring, 3);
302 if (r) {
303 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
304 ring->idx, r);
305 amdgpu_gfx_scratch_free(adev, scratch);
306 return r;
307 }
308 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
309 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
310 amdgpu_ring_write(ring, 0xDEADBEEF);
311 amdgpu_ring_commit(ring);
312
313 for (i = 0; i < adev->usec_timeout; i++) {
314 tmp = RREG32(scratch);
315 if (tmp == 0xDEADBEEF)
316 break;
317 DRM_UDELAY(1);
318 }
319 if (i < adev->usec_timeout) {
320 DRM_INFO("ring test on %d succeeded in %d usecs\n",
321 ring->idx, i);
322 } else {
323 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
324 ring->idx, scratch, tmp);
325 r = -EINVAL;
326 }
327 amdgpu_gfx_scratch_free(adev, scratch);
328 return r;
329}
330
331static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
332{
333 struct amdgpu_device *adev = ring->adev;
334 struct amdgpu_ib ib;
335 struct dma_fence *f = NULL;
336 uint32_t scratch;
337 uint32_t tmp = 0;
338 long r;
339
340 r = amdgpu_gfx_scratch_get(adev, &scratch);
341 if (r) {
342 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
343 return r;
344 }
345 WREG32(scratch, 0xCAFEDEAD);
346 memset(&ib, 0, sizeof(ib));
347 r = amdgpu_ib_get(adev, NULL, 256, &ib);
348 if (r) {
349 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
350 goto err1;
351 }
352 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
353 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
354 ib.ptr[2] = 0xDEADBEEF;
355 ib.length_dw = 3;
356
357 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
358 if (r)
359 goto err2;
360
361 r = dma_fence_wait_timeout(f, false, timeout);
362 if (r == 0) {
363 DRM_ERROR("amdgpu: IB test timed out.\n");
364 r = -ETIMEDOUT;
365 goto err2;
366 } else if (r < 0) {
367 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
368 goto err2;
369 }
370 tmp = RREG32(scratch);
371 if (tmp == 0xDEADBEEF) {
372 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
373 r = 0;
374 } else {
375 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
376 scratch, tmp);
377 r = -EINVAL;
378 }
379err2:
380 amdgpu_ib_free(adev, &ib, NULL);
381 dma_fence_put(f);
382err1:
383 amdgpu_gfx_scratch_free(adev, scratch);
384 return r;
385}
386
c833d8aa
ML		 387
388static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
389{
390 release_firmware(adev->gfx.pfp_fw);
391 adev->gfx.pfp_fw = NULL;
392 release_firmware(adev->gfx.me_fw);
393 adev->gfx.me_fw = NULL;
394 release_firmware(adev->gfx.ce_fw);
395 adev->gfx.ce_fw = NULL;
396 release_firmware(adev->gfx.rlc_fw);
397 adev->gfx.rlc_fw = NULL;
398 release_firmware(adev->gfx.mec_fw);
399 adev->gfx.mec_fw = NULL;
400 release_firmware(adev->gfx.mec2_fw);
401 adev->gfx.mec2_fw = NULL;
402
403 kfree(adev->gfx.rlc.register_list_format);
404}
405
b1023571
KW		 406static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
407{
408 const char *chip_name;
409 char fw_name[30];
410 int err;
411 struct amdgpu_firmware_info *info = NULL;
412 const struct common_firmware_header *header = NULL;
413 const struct gfx_firmware_header_v1_0 *cp_hdr;
a4d41ad0
HZ		 414 const struct rlc_firmware_header_v2_0 *rlc_hdr;
415 unsigned int *tmp = NULL;
416 unsigned int i = 0;
b1023571
KW		 417
418 DRM_DEBUG("\n");
419
420 switch (adev->asic_type) {
421 case CHIP_VEGA10:
422 chip_name = "vega10";
423 break;
eaa85724
CZ		 424 case CHIP_RAVEN:
425 chip_name = "raven";
426 break;
b1023571
KW		 427 default:
428 BUG();
429 }
430
431 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
432 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
433 if (err)
434 goto out;
435 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
436 if (err)
437 goto out;
438 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
439 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
440 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
441
442 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
443 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
444 if (err)
445 goto out;
446 err = amdgpu_ucode_validate(adev->gfx.me_fw);
447 if (err)
448 goto out;
449 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
450 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
451 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
452
453 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
454 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
455 if (err)
456 goto out;
457 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
458 if (err)
459 goto out;
460 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
461 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
462 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
463
464 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
465 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
466 if (err)
467 goto out;
468 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
a4d41ad0
HZ		 469 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
470 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
471 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
472 adev->gfx.rlc.save_and_restore_offset =
473 le32_to_cpu(rlc_hdr->save_and_restore_offset);
474 adev->gfx.rlc.clear_state_descriptor_offset =
475 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
476 adev->gfx.rlc.avail_scratch_ram_locations =
477 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
478 adev->gfx.rlc.reg_restore_list_size =
479 le32_to_cpu(rlc_hdr->reg_restore_list_size);
480 adev->gfx.rlc.reg_list_format_start =
481 le32_to_cpu(rlc_hdr->reg_list_format_start);
482 adev->gfx.rlc.reg_list_format_separate_start =
483 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
484 adev->gfx.rlc.starting_offsets_start =
485 le32_to_cpu(rlc_hdr->starting_offsets_start);
486 adev->gfx.rlc.reg_list_format_size_bytes =
487 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
488 adev->gfx.rlc.reg_list_size_bytes =
489 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
490 adev->gfx.rlc.register_list_format =
491 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
492 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
493 if (!adev->gfx.rlc.register_list_format) {
494 err = -ENOMEM;
495 goto out;
496 }
497
498 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
499 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
500 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
501 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
502
503 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
504
505 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
506 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
507 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
508 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
b1023571
KW		 509
510 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
511 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
512 if (err)
513 goto out;
514 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
515 if (err)
516 goto out;
517 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
518 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
519 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
520
521
522 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
523 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
524 if (!err) {
525 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
526 if (err)
527 goto out;
528 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
529 adev->gfx.mec2_fw->data;
530 adev->gfx.mec2_fw_version =
531 le32_to_cpu(cp_hdr->header.ucode_version);
532 adev->gfx.mec2_feature_version =
533 le32_to_cpu(cp_hdr->ucode_feature_version);
534 } else {
535 err = 0;
536 adev->gfx.mec2_fw = NULL;
537 }
538
539 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
540 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
541 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
542 info->fw = adev->gfx.pfp_fw;
543 header = (const struct common_firmware_header *)info->fw->data;
544 adev->firmware.fw_size +=
545 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
546
547 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
548 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
549 info->fw = adev->gfx.me_fw;
550 header = (const struct common_firmware_header *)info->fw->data;
551 adev->firmware.fw_size +=
552 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
553
554 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
555 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
556 info->fw = adev->gfx.ce_fw;
557 header = (const struct common_firmware_header *)info->fw->data;
558 adev->firmware.fw_size +=
559 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
560
561 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
562 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
563 info->fw = adev->gfx.rlc_fw;
564 header = (const struct common_firmware_header *)info->fw->data;
565 adev->firmware.fw_size +=
566 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
567
568 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
569 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
570 info->fw = adev->gfx.mec_fw;
571 header = (const struct common_firmware_header *)info->fw->data;
572 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
573 adev->firmware.fw_size +=
574 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
575
576 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
577 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
578 info->fw = adev->gfx.mec_fw;
579 adev->firmware.fw_size +=
580 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
581
582 if (adev->gfx.mec2_fw) {
583 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
584 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
585 info->fw = adev->gfx.mec2_fw;
586 header = (const struct common_firmware_header *)info->fw->data;
587 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
588 adev->firmware.fw_size +=
589 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
590 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
591 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
592 info->fw = adev->gfx.mec2_fw;
593 adev->firmware.fw_size +=
594 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
595 }
596
597 }
598
599out:
600 if (err) {
601 dev_err(adev->dev,
602 "gfx9: Failed to load firmware \"%s\"\n",
603 fw_name);
604 release_firmware(adev->gfx.pfp_fw);
605 adev->gfx.pfp_fw = NULL;
606 release_firmware(adev->gfx.me_fw);
607 adev->gfx.me_fw = NULL;
608 release_firmware(adev->gfx.ce_fw);
609 adev->gfx.ce_fw = NULL;
610 release_firmware(adev->gfx.rlc_fw);
611 adev->gfx.rlc_fw = NULL;
612 release_firmware(adev->gfx.mec_fw);
613 adev->gfx.mec_fw = NULL;
614 release_firmware(adev->gfx.mec2_fw);
615 adev->gfx.mec2_fw = NULL;
616 }
617 return err;
618}
619
c9719c69
HZ		 620static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
621{
622 u32 count = 0;
623 const struct cs_section_def *sect = NULL;
624 const struct cs_extent_def *ext = NULL;
625
626 /* begin clear state */
627 count += 2;
628 /* context control state */
629 count += 3;
630
631 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
632 for (ext = sect->section; ext->extent != NULL; ++ext) {
633 if (sect->id == SECT_CONTEXT)
634 count += 2 + ext->reg_count;
635 else
636 return 0;
637 }
638 }
639
640 /* end clear state */
641 count += 2;
642 /* clear state */
643 count += 2;
644
645 return count;
646}
647
648static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
649 volatile u32 *buffer)
650{
651 u32 count = 0, i;
652 const struct cs_section_def *sect = NULL;
653 const struct cs_extent_def *ext = NULL;
654
655 if (adev->gfx.rlc.cs_data == NULL)
656 return;
657 if (buffer == NULL)
658 return;
659
660 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
661 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
662
663 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
664 buffer[count++] = cpu_to_le32(0x80000000);
665 buffer[count++] = cpu_to_le32(0x80000000);
666
667 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
668 for (ext = sect->section; ext->extent != NULL; ++ext) {
669 if (sect->id == SECT_CONTEXT) {
670 buffer[count++] =
671 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
672 buffer[count++] = cpu_to_le32(ext->reg_index -
673 PACKET3_SET_CONTEXT_REG_START);
674 for (i = 0; i < ext->reg_count; i++)
675 buffer[count++] = cpu_to_le32(ext->extent[i]);
676 } else {
677 return;
678 }
679 }
680 }
681
682 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
683 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
684
685 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
686 buffer[count++] = cpu_to_le32(0);
687}
688
ba7bb665
HZ		 689static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
690{
e5475e16 691 uint32_t data;
ba7bb665
HZ		 692
693 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
694 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
695 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
696 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
697 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
698
699 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
700 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
701
702 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
703 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
704
705 mutex_lock(&adev->grbm_idx_mutex);
706 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
707 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
708 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
709
710 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
e5475e16
TSD		 711 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
712 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
713 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
ba7bb665
HZ		 714 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
715
716 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
717 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
718 data &= 0x0000FFFF;
719 data |= 0x00C00000;
720 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
721
722 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
723 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
724
725 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
726 * but used for RLC_LB_CNTL configuration */
727 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
e5475e16
TSD		 728 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
729 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
ba7bb665
HZ		 730 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
731 mutex_unlock(&adev->grbm_idx_mutex);
732}
733
e8835e0e
HZ		 734static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
735{
e5475e16 736 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
e8835e0e
HZ		 737}
738
c9719c69
HZ		 739static void rv_init_cp_jump_table(struct amdgpu_device *adev)
740{
741 const __le32 *fw_data;
742 volatile u32 *dst_ptr;
743 int me, i, max_me = 5;
744 u32 bo_offset = 0;
745 u32 table_offset, table_size;
746
747 /* write the cp table buffer */
748 dst_ptr = adev->gfx.rlc.cp_table_ptr;
749 for (me = 0; me < max_me; me++) {
750 if (me == 0) {
751 const struct gfx_firmware_header_v1_0 *hdr =
752 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
753 fw_data = (const __le32 *)
754 (adev->gfx.ce_fw->data +
755 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
756 table_offset = le32_to_cpu(hdr->jt_offset);
757 table_size = le32_to_cpu(hdr->jt_size);
758 } else if (me == 1) {
759 const struct gfx_firmware_header_v1_0 *hdr =
760 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
761 fw_data = (const __le32 *)
762 (adev->gfx.pfp_fw->data +
763 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
764 table_offset = le32_to_cpu(hdr->jt_offset);
765 table_size = le32_to_cpu(hdr->jt_size);
766 } else if (me == 2) {
767 const struct gfx_firmware_header_v1_0 *hdr =
768 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
769 fw_data = (const __le32 *)
770 (adev->gfx.me_fw->data +
771 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
772 table_offset = le32_to_cpu(hdr->jt_offset);
773 table_size = le32_to_cpu(hdr->jt_size);
774 } else if (me == 3) {
775 const struct gfx_firmware_header_v1_0 *hdr =
776 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
777 fw_data = (const __le32 *)
778 (adev->gfx.mec_fw->data +
779 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
780 table_offset = le32_to_cpu(hdr->jt_offset);
781 table_size = le32_to_cpu(hdr->jt_size);
782 } else if (me == 4) {
783 const struct gfx_firmware_header_v1_0 *hdr =
784 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
785 fw_data = (const __le32 *)
786 (adev->gfx.mec2_fw->data +
787 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
788 table_offset = le32_to_cpu(hdr->jt_offset);
789 table_size = le32_to_cpu(hdr->jt_size);
790 }
791
792 for (i = 0; i < table_size; i ++) {
793 dst_ptr[bo_offset + i] =
794 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
795 }
796
797 bo_offset += table_size;
798 }
799}
800
801static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
802{
803 /* clear state block */
804 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
805 &adev->gfx.rlc.clear_state_gpu_addr,
806 (void **)&adev->gfx.rlc.cs_ptr);
807
808 /* jump table block */
809 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
810 &adev->gfx.rlc.cp_table_gpu_addr,
811 (void **)&adev->gfx.rlc.cp_table_ptr);
812}
813
814static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
815{
816 volatile u32 *dst_ptr;
817 u32 dws;
818 const struct cs_section_def *cs_data;
819 int r;
820
821 adev->gfx.rlc.cs_data = gfx9_cs_data;
822
823 cs_data = adev->gfx.rlc.cs_data;
824
825 if (cs_data) {
826 /* clear state block */
827 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
a4a02777
CK		 828 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
829 AMDGPU_GEM_DOMAIN_VRAM,
830 &adev->gfx.rlc.clear_state_obj,
831 &adev->gfx.rlc.clear_state_gpu_addr,
832 (void **)&adev->gfx.rlc.cs_ptr);
833 if (r) {
834 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
835 r);
836 gfx_v9_0_rlc_fini(adev);
837 return r;
c9719c69
HZ		 838 }
839 /* set up the cs buffer */
840 dst_ptr = adev->gfx.rlc.cs_ptr;
841 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
842 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
843 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
844 }
845
846 if (adev->asic_type == CHIP_RAVEN) {
847 /* TODO: double check the cp_table_size for RV */
848 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
a4a02777
CK		 849 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
850 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
851 &adev->gfx.rlc.cp_table_obj,
852 &adev->gfx.rlc.cp_table_gpu_addr,
853 (void **)&adev->gfx.rlc.cp_table_ptr);
854 if (r) {
855 dev_err(adev->dev,
856 "(%d) failed to create cp table bo\n", r);
857 gfx_v9_0_rlc_fini(adev);
858 return r;
c9719c69
HZ		 859 }
860
861 rv_init_cp_jump_table(adev);
862 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
863 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
ba7bb665
HZ		 864
865 gfx_v9_0_init_lbpw(adev);
c9719c69
HZ		 866 }
867
868 return 0;
869}
870
b1023571
KW		 871static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
872{
078af1a3
CK		 873 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
874 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
b1023571
KW		 875}
876
b1023571
KW		 877static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
878{
879 int r;
880 u32 *hpd;
881 const __le32 *fw_data;
882 unsigned fw_size;
883 u32 *fw;
42794b27 884 size_t mec_hpd_size;
b1023571
KW		 885
886 const struct gfx_firmware_header_v1_0 *mec_hdr;
887
78c16834
AR		 888 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
889
78c16834 890 /* take ownership of the relevant compute queues */
41f6a99a 891 amdgpu_gfx_compute_queue_acquire(adev);
78c16834 892 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
b1023571 893
a4a02777
CK		 894 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
895 AMDGPU_GEM_DOMAIN_GTT,
896 &adev->gfx.mec.hpd_eop_obj,
897 &adev->gfx.mec.hpd_eop_gpu_addr,
898 (void **)&hpd);
b1023571 899 if (r) {
a4a02777 900 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
b1023571
KW		 901 gfx_v9_0_mec_fini(adev);
902 return r;
903 }
904
905 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
906
907 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
908 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
909
910 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
911
912 fw_data = (const __le32 *)
913 (adev->gfx.mec_fw->data +
914 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
915 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
916
a4a02777
CK		 917 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
918 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
919 &adev->gfx.mec.mec_fw_obj,
920 &adev->gfx.mec.mec_fw_gpu_addr,
921 (void **)&fw);
b1023571 922 if (r) {
a4a02777 923 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
b1023571
KW		 924 gfx_v9_0_mec_fini(adev);
925 return r;
926 }
a4a02777 927
b1023571
KW		 928 memcpy(fw, fw_data, fw_size);
929
930 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
931 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
932
b1023571
KW		 933 return 0;
934}
935
936static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
937{
5e78835a 938 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 939 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
940 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
941 (address << SQ_IND_INDEX__INDEX__SHIFT) |
942 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 943 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 944}
945
946static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
947 uint32_t wave, uint32_t thread,
948 uint32_t regno, uint32_t num, uint32_t *out)
949{
5e78835a 950 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 951 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
952 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
953 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
954 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
955 (SQ_IND_INDEX__FORCE_READ_MASK) |
956 (SQ_IND_INDEX__AUTO_INCR_MASK));
957 while (num--)
5e78835a 958 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 959}
960
961static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
962{
963 /* type 1 wave data */
964 dst[(*no_fields)++] = 1;
965 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
966 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
967 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
968 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
969 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
970 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
971 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
972 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
973 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
974 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
979}
980
981static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
982 uint32_t wave, uint32_t start,
983 uint32_t size, uint32_t *dst)
984{
985 wave_read_regs(
986 adev, simd, wave, 0,
987 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
988}
989
990
991static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
992 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
993 .select_se_sh = &gfx_v9_0_select_se_sh,
994 .read_wave_data = &gfx_v9_0_read_wave_data,
995 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
996};
997
998static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
999{
1000 u32 gb_addr_config;
1001
1002 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1003
1004 switch (adev->asic_type) {
1005 case CHIP_VEGA10:
b1023571 1006 adev->gfx.config.max_hw_contexts = 8;
b1023571
KW		 1007 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1008 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1009 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1010 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1011 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1012 break;
5cf7433d
CZ		 1013 case CHIP_RAVEN:
1014 adev->gfx.config.max_hw_contexts = 8;
1015 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1016 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1017 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1018 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1019 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1020 break;
b1023571
KW		 1021 default:
1022 BUG();
1023 break;
1024 }
1025
1026 adev->gfx.config.gb_addr_config = gb_addr_config;
1027
1028 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1029 REG_GET_FIELD(
1030 adev->gfx.config.gb_addr_config,
1031 GB_ADDR_CONFIG,
1032 NUM_PIPES);
ad7d0ff3
AD		 1033
1034 adev->gfx.config.max_tile_pipes =
1035 adev->gfx.config.gb_addr_config_fields.num_pipes;
1036
b1023571
KW		 1037 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1038 REG_GET_FIELD(
1039 adev->gfx.config.gb_addr_config,
1040 GB_ADDR_CONFIG,
1041 NUM_BANKS);
1042 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1043 REG_GET_FIELD(
1044 adev->gfx.config.gb_addr_config,
1045 GB_ADDR_CONFIG,
1046 MAX_COMPRESSED_FRAGS);
1047 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1048 REG_GET_FIELD(
1049 adev->gfx.config.gb_addr_config,
1050 GB_ADDR_CONFIG,
1051 NUM_RB_PER_SE);
1052 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1053 REG_GET_FIELD(
1054 adev->gfx.config.gb_addr_config,
1055 GB_ADDR_CONFIG,
1056 NUM_SHADER_ENGINES);
1057 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1058 REG_GET_FIELD(
1059 adev->gfx.config.gb_addr_config,
1060 GB_ADDR_CONFIG,
1061 PIPE_INTERLEAVE_SIZE));
1062}
1063
1064static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1065 struct amdgpu_ngg_buf *ngg_buf,
1066 int size_se,
1067 int default_size_se)
1068{
1069 int r;
1070
1071 if (size_se < 0) {
1072 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1073 return -EINVAL;
1074 }
1075 size_se = size_se ? size_se : default_size_se;
1076
42ce2243 1077 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 1078 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1079 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1080 &ngg_buf->bo,
1081 &ngg_buf->gpu_addr,
1082 NULL);
1083 if (r) {
1084 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1085 return r;
1086 }
1087 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1088
1089 return r;
1090}
1091
1092static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1093{
1094 int i;
1095
1096 for (i = 0; i < NGG_BUF_MAX; i++)
1097 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1098 &adev->gfx.ngg.buf[i].gpu_addr,
1099 NULL);
1100
1101 memset(&adev->gfx.ngg.buf[0], 0,
1102 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1103
1104 adev->gfx.ngg.init = false;
1105
1106 return 0;
1107}
1108
1109static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1110{
1111 int r;
1112
1113 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1114 return 0;
1115
1116 /* GDS reserve memory: 64 bytes alignment */
1117 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1118 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1119 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1120 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1121 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1122
1123 /* Primitive Buffer */
af8baf15 1124 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
b1023571
KW		 1125 amdgpu_prim_buf_per_se,
1126 64 * 1024);
1127 if (r) {
1128 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1129 goto err;
1130 }
1131
1132 /* Position Buffer */
af8baf15 1133 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
b1023571
KW		 1134 amdgpu_pos_buf_per_se,
1135 256 * 1024);
1136 if (r) {
1137 dev_err(adev->dev, "Failed to create Position Buffer\n");
1138 goto err;
1139 }
1140
1141 /* Control Sideband */
af8baf15 1142 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
b1023571
KW		 1143 amdgpu_cntl_sb_buf_per_se,
1144 256);
1145 if (r) {
1146 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1147 goto err;
1148 }
1149
1150 /* Parameter Cache, not created by default */
1151 if (amdgpu_param_buf_per_se <= 0)
1152 goto out;
1153
af8baf15 1154 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
b1023571
KW		 1155 amdgpu_param_buf_per_se,
1156 512 * 1024);
1157 if (r) {
1158 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1159 goto err;
1160 }
1161
1162out:
1163 adev->gfx.ngg.init = true;
1164 return 0;
1165err:
1166 gfx_v9_0_ngg_fini(adev);
1167 return r;
1168}
1169
1170static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1171{
1172 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1173 int r;
91629eff 1174 u32 data, base;
b1023571
KW		 1175
1176 if (!amdgpu_ngg)
1177 return 0;
1178
1179 /* Program buffer size */
91629eff
TSD		 1180 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1181 adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1182 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1183 adev->gfx.ngg.buf[NGG_POS].size >> 8);
5e78835a 1184 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571 1185
91629eff
TSD		 1186 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1187 adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1188 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1189 adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
5e78835a 1190 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 1191
1192 /* Program buffer base address */
af8baf15 1193 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1194 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 1195 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571 1196
af8baf15 1197 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1198 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 1199 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571 1200
af8baf15 1201 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1202 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 1203 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571 1204
af8baf15 1205 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1206 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 1207 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571 1208
af8baf15 1209 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1210 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 1211 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571 1212
af8baf15 1213 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1214 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 1215 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 1216
1217 /* Clear GDS reserved memory */
1218 r = amdgpu_ring_alloc(ring, 17);
1219 if (r) {
1220 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1221 ring->idx, r);
1222 return r;
1223 }
1224
1225 gfx_v9_0_write_data_to_reg(ring, 0, false,
1226 amdgpu_gds_reg_offset[0].mem_size,
1227 (adev->gds.mem.total_size +
1228 adev->gfx.ngg.gds_reserve_size) >>
1229 AMDGPU_GDS_SHIFT);
1230
1231 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1232 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1233 PACKET3_DMA_DATA_SRC_SEL(2)));
1234 amdgpu_ring_write(ring, 0);
1235 amdgpu_ring_write(ring, 0);
1236 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1237 amdgpu_ring_write(ring, 0);
1238 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1239
1240
1241 gfx_v9_0_write_data_to_reg(ring, 0, false,
1242 amdgpu_gds_reg_offset[0].mem_size, 0);
1243
1244 amdgpu_ring_commit(ring);
1245
1246 return 0;
1247}
1248
1361f455
AD		 1249static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1250 int mec, int pipe, int queue)
1251{
1252 int r;
1253 unsigned irq_type;
1254 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1255
1256 ring = &adev->gfx.compute_ring[ring_id];
1257
1258 /* mec0 is me1 */
1259 ring->me = mec + 1;
1260 ring->pipe = pipe;
1261 ring->queue = queue;
1262
1263 ring->ring_obj = NULL;
1264 ring->use_doorbell = true;
7366af81 1265 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1361f455
AD		 1266 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1267 + (ring_id * GFX9_MEC_HPD_SIZE);
1268 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1269
1270 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1271 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1272 + ring->pipe;
1273
1274 /* type-2 packets are deprecated on MEC, use type-3 instead */
1275 r = amdgpu_ring_init(adev, ring, 1024,
1276 &adev->gfx.eop_irq, irq_type);
1277 if (r)
1278 return r;
1279
1280
1281 return 0;
1282}
1283
b1023571
KW		 1284static int gfx_v9_0_sw_init(void *handle)
1285{
1361f455 1286 int i, j, k, r, ring_id;
b1023571 1287 struct amdgpu_ring *ring;
ac104e99 1288 struct amdgpu_kiq *kiq;
b1023571
KW		 1289 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1290
4853bbb6
AD		 1291 switch (adev->asic_type) {
1292 case CHIP_VEGA10:
1293 case CHIP_RAVEN:
1294 adev->gfx.mec.num_mec = 2;
1295 break;
1296 default:
1297 adev->gfx.mec.num_mec = 1;
1298 break;
1299 }
1300
1301 adev->gfx.mec.num_pipe_per_mec = 4;
1302 adev->gfx.mec.num_queue_per_pipe = 8;
1303
97031e25
XY		 1304 /* KIQ event */
1305 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1306 if (r)
1307 return r;
1308
b1023571
KW		 1309 /* EOP Event */
1310 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1311 if (r)
1312 return r;
1313
1314 /* Privileged reg */
1315 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1316 &adev->gfx.priv_reg_irq);
1317 if (r)
1318 return r;
1319
1320 /* Privileged inst */
1321 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1322 &adev->gfx.priv_inst_irq);
1323 if (r)
1324 return r;
1325
1326 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1327
1328 gfx_v9_0_scratch_init(adev);
1329
1330 r = gfx_v9_0_init_microcode(adev);
1331 if (r) {
1332 DRM_ERROR("Failed to load gfx firmware!\n");
1333 return r;
1334 }
1335
c9719c69
HZ		 1336 r = gfx_v9_0_rlc_init(adev);
1337 if (r) {
1338 DRM_ERROR("Failed to init rlc BOs!\n");
1339 return r;
1340 }
1341
b1023571
KW		 1342 r = gfx_v9_0_mec_init(adev);
1343 if (r) {
1344 DRM_ERROR("Failed to init MEC BOs!\n");
1345 return r;
1346 }
1347
1348 /* set up the gfx ring */
1349 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1350 ring = &adev->gfx.gfx_ring[i];
1351 ring->ring_obj = NULL;
f6886c47
TSD		 1352 if (!i)
1353 sprintf(ring->name, "gfx");
1354 else
1355 sprintf(ring->name, "gfx_%d", i);
b1023571
KW		 1356 ring->use_doorbell = true;
1357 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1358 r = amdgpu_ring_init(adev, ring, 1024,
1359 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1360 if (r)
1361 return r;
1362 }
1363
1361f455
AD		 1364 /* set up the compute queues - allocate horizontally across pipes */
1365 ring_id = 0;
1366 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1367 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1368 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2db0cdbe 1369 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1361f455
AD		 1370 continue;
1371
1372 r = gfx_v9_0_compute_ring_init(adev,
1373 ring_id,
1374 i, k, j);
1375 if (r)
1376 return r;
1377
1378 ring_id++;
1379 }
b1023571 1380 }
b1023571
KW		 1381 }
1382
71c37505 1383 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
e30a5223
AD		 1384 if (r) {
1385 DRM_ERROR("Failed to init KIQ BOs!\n");
1386 return r;
1387 }
ac104e99 1388
e30a5223 1389 kiq = &adev->gfx.kiq;
71c37505 1390 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
e30a5223
AD		 1391 if (r)
1392 return r;
464826d6 1393
e30a5223 1394 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
ffe6d881 1395 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
e30a5223
AD		 1396 if (r)
1397 return r;
ac104e99 1398
b1023571
KW		 1399 /* reserve GDS, GWS and OA resource for gfx */
1400 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1401 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1402 &adev->gds.gds_gfx_bo, NULL, NULL);
1403 if (r)
1404 return r;
1405
1406 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1407 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1408 &adev->gds.gws_gfx_bo, NULL, NULL);
1409 if (r)
1410 return r;
1411
1412 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1413 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1414 &adev->gds.oa_gfx_bo, NULL, NULL);
1415 if (r)
1416 return r;
1417
1418 adev->gfx.ce_ram_size = 0x8000;
1419
1420 gfx_v9_0_gpu_early_init(adev);
1421
1422 r = gfx_v9_0_ngg_init(adev);
1423 if (r)
1424 return r;
1425
1426 return 0;
1427}
1428
1429
1430static int gfx_v9_0_sw_fini(void *handle)
1431{
1432 int i;
1433 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1434
1435 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1436 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1437 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1438
1439 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1440 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1441 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1442 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1443
b9683c21 1444 amdgpu_gfx_compute_mqd_sw_fini(adev);
71c37505
AD		 1445 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1446 amdgpu_gfx_kiq_fini(adev);
030308fc 1447 amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
ac104e99 1448
b1023571
KW		 1449 gfx_v9_0_mec_fini(adev);
1450 gfx_v9_0_ngg_fini(adev);
c833d8aa 1451 gfx_v9_0_free_microcode(adev);
b1023571
KW		 1452
1453 return 0;
1454}
1455
1456
1457static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1458{
1459 /* TODO */
1460}
1461
1462static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1463{
be448a4d 1464 u32 data;
b1023571 1465
be448a4d
NH		 1466 if (instance == 0xffffffff)
1467 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1468 else
1469 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1470
1471 if (se_num == 0xffffffff)
b1023571 1472 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
be448a4d 1473 else
b1023571 1474 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
be448a4d
NH		 1475
1476 if (sh_num == 0xffffffff)
1477 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1478 else
b1023571 1479 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
be448a4d 1480
5e78835a 1481 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1482}
1483
b1023571
KW		 1484static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1485{
1486 u32 data, mask;
1487
5e78835a
TSD		 1488 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1489 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1490
1491 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1492 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1493
378506a7
AD		 1494 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1495 adev->gfx.config.max_sh_per_se);
b1023571
KW		 1496
1497 return (~data) & mask;
1498}
1499
1500static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1501{
1502 int i, j;
2572c24c 1503 u32 data;
b1023571
KW		 1504 u32 active_rbs = 0;
1505 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1506 adev->gfx.config.max_sh_per_se;
1507
1508 mutex_lock(&adev->grbm_idx_mutex);
1509 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1510 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1511 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1512 data = gfx_v9_0_get_rb_active_bitmap(adev);
1513 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1514 rb_bitmap_width_per_sh);
1515 }
1516 }
1517 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1518 mutex_unlock(&adev->grbm_idx_mutex);
1519
1520 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1521 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1522}
1523
1524#define DEFAULT_SH_MEM_BASES (0x6000)
1525#define FIRST_COMPUTE_VMID (8)
1526#define LAST_COMPUTE_VMID (16)
1527static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1528{
1529 int i;
1530 uint32_t sh_mem_config;
1531 uint32_t sh_mem_bases;
1532
1533 /*
1534 * Configure apertures:
1535 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1536 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1537 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1538 */
1539 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1540
1541 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1542 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
eaa05d52 1543 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
b1023571
KW		 1544
1545 mutex_lock(&adev->srbm_mutex);
1546 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1547 soc15_grbm_select(adev, 0, 0, 0, i);
1548 /* CP and shaders */
5e78835a
TSD		 1549 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1550 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1551 }
1552 soc15_grbm_select(adev, 0, 0, 0, 0);
1553 mutex_unlock(&adev->srbm_mutex);
1554}
1555
1556static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1557{
1558 u32 tmp;
1559 int i;
1560
40f06773 1561 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1562
1563 gfx_v9_0_tiling_mode_table_init(adev);
1564
1565 gfx_v9_0_setup_rb(adev);
1566 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1567
1568 /* XXX SH_MEM regs */
1569 /* where to put LDS, scratch, GPUVM in FSA64 space */
1570 mutex_lock(&adev->srbm_mutex);
1571 for (i = 0; i < 16; i++) {
1572 soc15_grbm_select(adev, 0, 0, 0, i);
1573 /* CP and shaders */
1574 tmp = 0;
1575 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1576 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5e78835a
TSD		 1577 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1578 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
b1023571
KW		 1579 }
1580 soc15_grbm_select(adev, 0, 0, 0, 0);
1581
1582 mutex_unlock(&adev->srbm_mutex);
1583
1584 gfx_v9_0_init_compute_vmid(adev);
1585
1586 mutex_lock(&adev->grbm_idx_mutex);
1587 /*
1588 * making sure that the following register writes will be broadcasted
1589 * to all the shaders
1590 */
1591 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1592
5e78835a 1593 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1594 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1595 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1596 (adev->gfx.config.sc_prim_fifo_size_backend <<
1597 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1598 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1599 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1600 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1601 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1602 mutex_unlock(&adev->grbm_idx_mutex);
1603
1604}
1605
1606static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1607{
1608 u32 i, j, k;
1609 u32 mask;
1610
1611 mutex_lock(&adev->grbm_idx_mutex);
1612 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1613 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1614 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1615 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1616 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1617 break;
1618 udelay(1);
1619 }
1620 }
1621 }
1622 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1623 mutex_unlock(&adev->grbm_idx_mutex);
1624
1625 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1626 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1627 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1628 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1629 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1630 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1631 break;
1632 udelay(1);
1633 }
1634}
1635
1636static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1637 bool enable)
1638{
5e78835a 1639 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571 1640
b1023571
KW		 1641 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1642 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1643 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1644 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1645
5e78835a 1646 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1647}
1648
6bce4667
HZ		 1649static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1650{
1651 /* csib */
1652 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1653 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1654 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1655 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1656 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1657 adev->gfx.rlc.clear_state_size);
1658}
1659
1660static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1661 int indirect_offset,
1662 int list_size,
1663 int *unique_indirect_regs,
1664 int *unique_indirect_reg_count,
1665 int max_indirect_reg_count,
1666 int *indirect_start_offsets,
1667 int *indirect_start_offsets_count,
1668 int max_indirect_start_offsets_count)
1669{
1670 int idx;
1671 bool new_entry = true;
1672
1673 for (; indirect_offset < list_size; indirect_offset++) {
1674
1675 if (new_entry) {
1676 new_entry = false;
1677 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1678 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1679 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1680 }
1681
1682 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1683 new_entry = true;
1684 continue;
1685 }
1686
1687 indirect_offset += 2;
1688
1689 /* look for the matching indice */
1690 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1691 if (unique_indirect_regs[idx] ==
1692 register_list_format[indirect_offset])
1693 break;
1694 }
1695
1696 if (idx >= *unique_indirect_reg_count) {
1697 unique_indirect_regs[*unique_indirect_reg_count] =
1698 register_list_format[indirect_offset];
1699 idx = *unique_indirect_reg_count;
1700 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1701 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1702 }
1703
1704 register_list_format[indirect_offset] = idx;
1705 }
1706}
1707
1708static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1709{
1710 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1711 int unique_indirect_reg_count = 0;
1712
1713 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1714 int indirect_start_offsets_count = 0;
1715
1716 int list_size = 0;
1717 int i = 0;
1718 u32 tmp = 0;
1719
1720 u32 *register_list_format =
1721 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1722 if (!register_list_format)
1723 return -ENOMEM;
1724 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1725 adev->gfx.rlc.reg_list_format_size_bytes);
1726
1727 /* setup unique_indirect_regs array and indirect_start_offsets array */
1728 gfx_v9_0_parse_ind_reg_list(register_list_format,
1729 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1730 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1731 unique_indirect_regs,
1732 &unique_indirect_reg_count,
1733 sizeof(unique_indirect_regs)/sizeof(int),
1734 indirect_start_offsets,
1735 &indirect_start_offsets_count,
1736 sizeof(indirect_start_offsets)/sizeof(int));
1737
1738 /* enable auto inc in case it is disabled */
1739 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1740 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1741 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1742
1743 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1744 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1745 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1746 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1747 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1748 adev->gfx.rlc.register_restore[i]);
1749
1750 /* load direct register */
1751 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1752 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1753 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1754 adev->gfx.rlc.register_restore[i]);
1755
1756 /* load indirect register */
1757 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1758 adev->gfx.rlc.reg_list_format_start);
1759 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1760 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1761 register_list_format[i]);
1762
1763 /* set save/restore list size */
1764 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1765 list_size = list_size >> 1;
1766 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1767 adev->gfx.rlc.reg_restore_list_size);
1768 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1769
1770 /* write the starting offsets to RLC scratch ram */
1771 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1772 adev->gfx.rlc.starting_offsets_start);
1773 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1774 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1775 indirect_start_offsets[i]);
1776
1777 /* load unique indirect regs*/
1778 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1779 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1780 unique_indirect_regs[i] & 0x3FFFF);
1781 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1782 unique_indirect_regs[i] >> 20);
1783 }
1784
1785 kfree(register_list_format);
1786 return 0;
1787}
1788
1789static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1790{
0e5293d0 1791 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
6bce4667
HZ		 1792}
1793
91d3130a
HZ		 1794static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1795 bool enable)
1796{
1797 uint32_t data = 0;
1798 uint32_t default_data = 0;
1799
1800 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1801 if (enable == true) {
1802 /* enable GFXIP control over CGPG */
1803 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1804 if(default_data != data)
1805 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1806
1807 /* update status */
1808 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1809 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1810 if(default_data != data)
1811 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1812 } else {
1813 /* restore GFXIP control over GCPG */
1814 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1815 if(default_data != data)
1816 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1817 }
1818}
1819
1820static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1821{
1822 uint32_t data = 0;
1823
1824 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1825 AMD_PG_SUPPORT_GFX_SMG |
1826 AMD_PG_SUPPORT_GFX_DMG)) {
1827 /* init IDLE_POLL_COUNT = 60 */
1828 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1829 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1830 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1831 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1832
1833 /* init RLC PG Delay */
1834 data = 0;
1835 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1836 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1837 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1838 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1839 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1840
1841 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1842 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1843 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1844 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1845
1846 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1847 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1848 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1849 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1850
1851 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1852 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1853
1854 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1855 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1856 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1857
1858 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1859 }
1860}
1861
ed5ad1e4
HZ		 1862static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1863 bool enable)
1864{
1865 uint32_t data = 0;
1866 uint32_t default_data = 0;
1867
1868 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
e24c7f06
TSD		 1869 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1870 SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
1871 enable ? 1 : 0);
1872 if (default_data != data)
1873 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
ed5ad1e4
HZ		 1874}
1875
1876static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1877 bool enable)
1878{
1879 uint32_t data = 0;
1880 uint32_t default_data = 0;
1881
1882 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
b926fe8e
TSD		 1883 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1884 SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
1885 enable ? 1 : 0);
1886 if(default_data != data)
1887 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
ed5ad1e4
HZ		 1888}
1889
3a6cc477
HZ		 1890static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1891 bool enable)
1892{
1893 uint32_t data = 0;
1894 uint32_t default_data = 0;
1895
1896 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
54cfe0fc
TSD		 1897 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1898 CP_PG_DISABLE,
1899 enable ? 0 : 1);
1900 if(default_data != data)
1901 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
3a6cc477
HZ		 1902}
1903
197f95c8
HZ		 1904static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
1905 bool enable)
1906{
1907 uint32_t data, default_data;
1908
1909 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
f55ee212
TSD		 1910 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1911 GFX_POWER_GATING_ENABLE,
1912 enable ? 1 : 0);
197f95c8
HZ		 1913 if(default_data != data)
1914 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1915}
1916
1917static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
1918 bool enable)
1919{
1920 uint32_t data, default_data;
1921
1922 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
513f8133
TSD		 1923 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1924 GFX_PIPELINE_PG_ENABLE,
1925 enable ? 1 : 0);
197f95c8
HZ		 1926 if(default_data != data)
1927 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1928
1929 if (!enable)
1930 /* read any GFX register to wake up GFX */
1931 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
1932}
1933
552c8f76 1934static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
1935 bool enable)
18924c71
HZ		 1936{
1937 uint32_t data, default_data;
1938
1939 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
7915c8fd
TSD		 1940 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1941 STATIC_PER_CU_PG_ENABLE,
1942 enable ? 1 : 0);
18924c71
HZ		 1943 if(default_data != data)
1944 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1945}
1946
552c8f76 1947static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
18924c71
HZ		 1948 bool enable)
1949{
1950 uint32_t data, default_data;
1951
1952 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
e567fa69
TSD		 1953 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1954 DYN_PER_CU_PG_ENABLE,
1955 enable ? 1 : 0);
18924c71
HZ		 1956 if(default_data != data)
1957 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1958}
1959
6bce4667
HZ		 1960static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
1961{
1962 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1963 AMD_PG_SUPPORT_GFX_SMG |
1964 AMD_PG_SUPPORT_GFX_DMG |
1965 AMD_PG_SUPPORT_CP |
1966 AMD_PG_SUPPORT_GDS |
1967 AMD_PG_SUPPORT_RLC_SMU_HS)) {
1968 gfx_v9_0_init_csb(adev);
1969 gfx_v9_0_init_rlc_save_restore_list(adev);
1970 gfx_v9_0_enable_save_restore_machine(adev);
91d3130a
HZ		 1971
1972 if (adev->asic_type == CHIP_RAVEN) {
1973 WREG32(mmRLC_JUMP_TABLE_RESTORE,
1974 adev->gfx.rlc.cp_table_gpu_addr >> 8);
1975 gfx_v9_0_init_gfx_power_gating(adev);
3a6cc477 1976
ed5ad1e4
HZ		 1977 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
1978 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
1979 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
1980 } else {
1981 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
1982 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
1983 }
3a6cc477
HZ		 1984
1985 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
1986 gfx_v9_0_enable_cp_power_gating(adev, true);
1987 else
1988 gfx_v9_0_enable_cp_power_gating(adev, false);
91d3130a 1989 }
6bce4667
HZ		 1990 }
1991}
1992
b1023571
KW		 1993void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1994{
b08796ce 1995 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
b1023571 1996 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
b1023571
KW		 1997 gfx_v9_0_wait_for_rlc_serdes(adev);
1998}
1999
2000static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2001{
596c8e8b 2002 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 2003 udelay(50);
596c8e8b 2004 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 2005 udelay(50);
2006}
2007
2008static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2009{
2010#ifdef AMDGPU_RLC_DEBUG_RETRY
2011 u32 rlc_ucode_ver;
2012#endif
b1023571 2013
342cda25 2014 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 2015
2016 /* carrizo do enable cp interrupt after cp inited */
2017 if (!(adev->flags & AMD_IS_APU))
2018 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2019
2020 udelay(50);
2021
2022#ifdef AMDGPU_RLC_DEBUG_RETRY
2023 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 2024 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 2025 if(rlc_ucode_ver == 0x108) {
2026 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2027 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2028 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2029 * default is 0x9C4 to create a 100us interval */
5e78835a 2030 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571 2031 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
eaa05d52 2032 * to disable the page fault retry interrupts, default is
b1023571 2033 * 0x100 (256) */
5e78835a 2034 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 2035 }
2036#endif
2037}
2038
2039static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2040{
2041 const struct rlc_firmware_header_v2_0 *hdr;
2042 const __le32 *fw_data;
2043 unsigned i, fw_size;
2044
2045 if (!adev->gfx.rlc_fw)
2046 return -EINVAL;
2047
2048 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2049 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2050
2051 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2052 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2053 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2054
5e78835a 2055 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 2056 RLCG_UCODE_LOADING_START_ADDRESS);
2057 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2058 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2059 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 2060
2061 return 0;
2062}
2063
2064static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2065{
2066 int r;
2067
f840cc5f
ML		 2068 if (amdgpu_sriov_vf(adev)) {
2069 gfx_v9_0_init_csb(adev);
cfee05bc 2070 return 0;
f840cc5f 2071 }
cfee05bc 2072
b1023571
KW		 2073 gfx_v9_0_rlc_stop(adev);
2074
2075 /* disable CG */
5e78835a 2076 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 2077
2078 /* disable PG */
5e78835a 2079 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 2080
2081 gfx_v9_0_rlc_reset(adev);
2082
6bce4667
HZ		 2083 gfx_v9_0_init_pg(adev);
2084
b1023571
KW		 2085 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2086 /* legacy rlc firmware loading */
2087 r = gfx_v9_0_rlc_load_microcode(adev);
2088 if (r)
2089 return r;
2090 }
2091
e8835e0e
HZ		 2092 if (adev->asic_type == CHIP_RAVEN) {
2093 if (amdgpu_lbpw != 0)
2094 gfx_v9_0_enable_lbpw(adev, true);
2095 else
2096 gfx_v9_0_enable_lbpw(adev, false);
2097 }
2098
b1023571
KW		 2099 gfx_v9_0_rlc_start(adev);
2100
2101 return 0;
2102}
2103
2104static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2105{
2106 int i;
5e78835a 2107 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 2108
ea64468e
TSD		 2109 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2110 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2111 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2112 if (!enable) {
b1023571
KW		 2113 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2114 adev->gfx.gfx_ring[i].ready = false;
2115 }
5e78835a 2116 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 2117 udelay(50);
2118}
2119
2120static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2121{
2122 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2123 const struct gfx_firmware_header_v1_0 *ce_hdr;
2124 const struct gfx_firmware_header_v1_0 *me_hdr;
2125 const __le32 *fw_data;
2126 unsigned i, fw_size;
2127
2128 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2129 return -EINVAL;
2130
2131 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2132 adev->gfx.pfp_fw->data;
2133 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2134 adev->gfx.ce_fw->data;
2135 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2136 adev->gfx.me_fw->data;
2137
2138 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2139 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2140 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2141
2142 gfx_v9_0_cp_gfx_enable(adev, false);
2143
2144 /* PFP */
2145 fw_data = (const __le32 *)
2146 (adev->gfx.pfp_fw->data +
2147 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2148 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 2149 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 2150 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2151 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2152 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 2153
2154 /* CE */
2155 fw_data = (const __le32 *)
2156 (adev->gfx.ce_fw->data +
2157 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2158 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 2159 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 2160 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2161 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2162 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 2163
2164 /* ME */
2165 fw_data = (const __le32 *)
2166 (adev->gfx.me_fw->data +
2167 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2168 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 2169 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 2170 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2171 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2172 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 2173
2174 return 0;
2175}
2176
b1023571
KW		 2177static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2178{
2179 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2180 const struct cs_section_def *sect = NULL;
2181 const struct cs_extent_def *ext = NULL;
d5de797f 2182 int r, i, tmp;
b1023571
KW		 2183
2184 /* init the CP */
5e78835a
TSD		 2185 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2186 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 2187
2188 gfx_v9_0_cp_gfx_enable(adev, true);
2189
d5de797f 2190 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
b1023571
KW		 2191 if (r) {
2192 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2193 return r;
2194 }
2195
2196 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2197 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2198
2199 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2200 amdgpu_ring_write(ring, 0x80000000);
2201 amdgpu_ring_write(ring, 0x80000000);
2202
2203 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2204 for (ext = sect->section; ext->extent != NULL; ++ext) {
2205 if (sect->id == SECT_CONTEXT) {
2206 amdgpu_ring_write(ring,
2207 PACKET3(PACKET3_SET_CONTEXT_REG,
2208 ext->reg_count));
2209 amdgpu_ring_write(ring,
2210 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2211 for (i = 0; i < ext->reg_count; i++)
2212 amdgpu_ring_write(ring, ext->extent[i]);
2213 }
2214 }
2215 }
2216
2217 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2218 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2219
2220 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2221 amdgpu_ring_write(ring, 0);
2222
2223 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2224 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2225 amdgpu_ring_write(ring, 0x8000);
2226 amdgpu_ring_write(ring, 0x8000);
2227
d5de797f
KW		 2228 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2229 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2230 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2231 amdgpu_ring_write(ring, tmp);
2232 amdgpu_ring_write(ring, 0);
2233
b1023571
KW		 2234 amdgpu_ring_commit(ring);
2235
2236 return 0;
2237}
2238
2239static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2240{
2241 struct amdgpu_ring *ring;
2242 u32 tmp;
2243 u32 rb_bufsz;
3fc08b61 2244 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 2245
2246 /* Set the write pointer delay */
5e78835a 2247 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 2248
2249 /* set the RB to use vmid 0 */
5e78835a 2250 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 2251
2252 /* Set ring buffer size */
2253 ring = &adev->gfx.gfx_ring[0];
2254 rb_bufsz = order_base_2(ring->ring_size / 8);
2255 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2256 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2257#ifdef __BIG_ENDIAN
2258 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2259#endif
5e78835a 2260 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2261
2262 /* Initialize the ring buffer's write pointers */
2263 ring->wptr = 0;
5e78835a
TSD		 2264 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2265 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2266
2267 /* set the wb address wether it's enabled or not */
2268 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 2269 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2270 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 2271
3fc08b61 2272 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 2273 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2274 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 2275
b1023571 2276 mdelay(1);
5e78835a 2277 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2278
2279 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 2280 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2281 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 2282
5e78835a 2283 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 2284 if (ring->use_doorbell) {
2285 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2286 DOORBELL_OFFSET, ring->doorbell_index);
2287 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2288 DOORBELL_EN, 1);
2289 } else {
2290 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2291 }
5e78835a 2292 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 2293
2294 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2295 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 2296 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 2297
5e78835a 2298 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 2299 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2300
2301
2302 /* start the ring */
2303 gfx_v9_0_cp_gfx_start(adev);
2304 ring->ready = true;
2305
2306 return 0;
2307}
2308
2309static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2310{
2311 int i;
2312
2313 if (enable) {
5e78835a 2314 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 2315 } else {
5e78835a 2316 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 2317 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2318 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2319 adev->gfx.compute_ring[i].ready = false;
ac104e99 2320 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 2321 }
2322 udelay(50);
2323}
2324
b1023571
KW		 2325static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2326{
2327 const struct gfx_firmware_header_v1_0 *mec_hdr;
2328 const __le32 *fw_data;
2329 unsigned i;
2330 u32 tmp;
2331
2332 if (!adev->gfx.mec_fw)
2333 return -EINVAL;
2334
2335 gfx_v9_0_cp_compute_enable(adev, false);
2336
2337 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2338 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2339
2340 fw_data = (const __le32 *)
2341 (adev->gfx.mec_fw->data +
2342 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2343 tmp = 0;
2344 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2345 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 2346 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 2347
5e78835a 2348 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 2349 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 2350 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571 2351 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
eaa05d52 2352
b1023571 2353 /* MEC1 */
5e78835a 2354 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2355 mec_hdr->jt_offset);
2356 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 2357 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 2358 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2359
5e78835a 2360 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2361 adev->gfx.mec_fw_version);
2362 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2363
2364 return 0;
2365}
2366
464826d6
XY		 2367/* KIQ functions */
2368static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
b1023571 2369{
464826d6
XY		 2370 uint32_t tmp;
2371 struct amdgpu_device *adev = ring->adev;
b1023571 2372
464826d6 2373 /* tell RLC which is KIQ queue */
5e78835a 2374 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 2375 tmp &= 0xffffff00;
2376 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 2377 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2378 tmp |= 0x80;
5e78835a 2379 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2380}
b1023571 2381
0f1dfd52 2382static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
464826d6 2383{
bd3402ea 2384 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2fdde9fa 2385 uint32_t scratch, tmp = 0;
de65513a 2386 uint64_t queue_mask = 0;
2fdde9fa 2387 int r, i;
b1023571 2388
de65513a
AR		 2389 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2390 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2391 continue;
b1023571 2392
de65513a
AR		 2393 /* This situation may be hit in the future if a new HW
2394 * generation exposes more than 64 queues. If so, the
2395 * definition of queue_mask needs updating */
1d11ee89 2396 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
de65513a
AR		 2397 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2398 break;
b1023571 2399 }
b1023571 2400
de65513a
AR		 2401 queue_mask |= (1ull << i);
2402 }
b1023571 2403
2fdde9fa
AD		 2404 r = amdgpu_gfx_scratch_get(adev, &scratch);
2405 if (r) {
2406 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2407 return r;
b1023571 2408 }
2fdde9fa 2409 WREG32(scratch, 0xCAFEDEAD);
b1023571 2410
0f1dfd52 2411 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2fdde9fa
AD		 2412 if (r) {
2413 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2414 amdgpu_gfx_scratch_free(adev, scratch);
b1023571 2415 return r;
2fdde9fa 2416 }
b1023571 2417
0f1dfd52
AD		 2418 /* set resources */
2419 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2420 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2421 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
de65513a
AR		 2422 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2423 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
0f1dfd52
AD		 2424 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2425 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2426 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2427 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
bd3402ea
AD		 2428 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2429 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2430 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2431 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2432
2433 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2434 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2435 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2436 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2437 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2438 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2439 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2440 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2441 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2442 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2443 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2444 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2445 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2446 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2447 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2448 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2449 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2450 }
2fdde9fa
AD		 2451 /* write to scratch for completion */
2452 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2453 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2454 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
464826d6 2455 amdgpu_ring_commit(kiq_ring);
b1023571 2456
2fdde9fa
AD		 2457 for (i = 0; i < adev->usec_timeout; i++) {
2458 tmp = RREG32(scratch);
2459 if (tmp == 0xDEADBEEF)
2460 break;
2461 DRM_UDELAY(1);
2462 }
2463 if (i >= adev->usec_timeout) {
2464 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2465 scratch, tmp);
2466 r = -EINVAL;
2467 }
2468 amdgpu_gfx_scratch_free(adev, scratch);
464826d6 2469
2fdde9fa 2470 return r;
464826d6
XY		 2471}
2472
e322edc3 2473static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 2474{
33fb8698 2475 struct amdgpu_device *adev = ring->adev;
e322edc3 2476 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2477 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2478 uint32_t tmp;
2479
2480 mqd->header = 0xC0310800;
2481 mqd->compute_pipelinestat_enable = 0x00000001;
2482 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2483 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2484 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2485 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2486 mqd->compute_misc_reserved = 0x00000003;
2487
ffe6d881
AD		 2488 mqd->dynamic_cu_mask_addr_lo =
2489 lower_32_bits(ring->mqd_gpu_addr
2490 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2491 mqd->dynamic_cu_mask_addr_hi =
2492 upper_32_bits(ring->mqd_gpu_addr
2493 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2494
d72f2f46 2495 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 2496 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2497 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2498
2499 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2500 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6 2501 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
268cb4c7 2502 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
464826d6
XY		 2503
2504 mqd->cp_hqd_eop_control = tmp;
2505
2506 /* enable doorbell? */
5e78835a 2507 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2508
2509 if (ring->use_doorbell) {
2510 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2511 DOORBELL_OFFSET, ring->doorbell_index);
2512 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2513 DOORBELL_EN, 1);
2514 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2515 DOORBELL_SOURCE, 0);
2516 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2517 DOORBELL_HIT, 0);
78888cff 2518 } else {
464826d6
XY		 2519 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2520 DOORBELL_EN, 0);
78888cff 2521 }
464826d6
XY		 2522
2523 mqd->cp_hqd_pq_doorbell_control = tmp;
2524
2525 /* disable the queue if it's active */
2526 ring->wptr = 0;
2527 mqd->cp_hqd_dequeue_request = 0;
2528 mqd->cp_hqd_pq_rptr = 0;
2529 mqd->cp_hqd_pq_wptr_lo = 0;
2530 mqd->cp_hqd_pq_wptr_hi = 0;
2531
2532 /* set the pointer to the MQD */
33fb8698
AD		 2533 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2534 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 2535
2536 /* set MQD vmid to 0 */
5e78835a 2537 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 2538 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2539 mqd->cp_mqd_control = tmp;
2540
2541 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2542 hqd_gpu_addr = ring->gpu_addr >> 8;
2543 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2544 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2545
2546 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2547 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 2548 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2549 (order_base_2(ring->ring_size / 4) - 1));
2550 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2551 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2552#ifdef __BIG_ENDIAN
2553 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2554#endif
2555 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2556 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2557 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2558 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2559 mqd->cp_hqd_pq_control = tmp;
2560
2561 /* set the wb address whether it's enabled or not */
2562 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2563 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2564 mqd->cp_hqd_pq_rptr_report_addr_hi =
2565 upper_32_bits(wb_gpu_addr) & 0xffff;
2566
2567 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2568 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2569 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2570 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2571
2572 tmp = 0;
2573 /* enable the doorbell if requested */
2574 if (ring->use_doorbell) {
5e78835a 2575 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2576 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2577 DOORBELL_OFFSET, ring->doorbell_index);
2578
2579 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2580 DOORBELL_EN, 1);
2581 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2582 DOORBELL_SOURCE, 0);
2583 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2584 DOORBELL_HIT, 0);
2585 }
2586
2587 mqd->cp_hqd_pq_doorbell_control = tmp;
2588
2589 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2590 ring->wptr = 0;
0274a9c5 2591 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 2592
2593 /* set the vmid for the queue */
2594 mqd->cp_hqd_vmid = 0;
2595
0274a9c5 2596 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 2597 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2598 mqd->cp_hqd_persistent_state = tmp;
2599
fca4ce69
AD		 2600 /* set MIN_IB_AVAIL_SIZE */
2601 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2602 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2603 mqd->cp_hqd_ib_control = tmp;
2604
464826d6
XY		 2605 /* activate the queue */
2606 mqd->cp_hqd_active = 1;
2607
2608 return 0;
2609}
2610
e322edc3 2611static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2612{
33fb8698 2613 struct amdgpu_device *adev = ring->adev;
e322edc3 2614 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2615 int j;
2616
2617 /* disable wptr polling */
72edadd5 2618 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2619
5e78835a 2620 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2621 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2622 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2623 mqd->cp_hqd_eop_base_addr_hi);
2624
2625 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2626 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2627 mqd->cp_hqd_eop_control);
2628
2629 /* enable doorbell? */
5e78835a 2630 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2631 mqd->cp_hqd_pq_doorbell_control);
2632
2633 /* disable the queue if it's active */
5e78835a
TSD		 2634 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2635 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2636 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2637 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2638 break;
2639 udelay(1);
2640 }
5e78835a 2641 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2642 mqd->cp_hqd_dequeue_request);
5e78835a 2643 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2644 mqd->cp_hqd_pq_rptr);
5e78835a 2645 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2646 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2647 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2648 mqd->cp_hqd_pq_wptr_hi);
2649 }
2650
2651 /* set the pointer to the MQD */
5e78835a 2652 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2653 mqd->cp_mqd_base_addr_lo);
5e78835a 2654 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2655 mqd->cp_mqd_base_addr_hi);
2656
2657 /* set MQD vmid to 0 */
5e78835a 2658 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2659 mqd->cp_mqd_control);
2660
2661 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2662 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2663 mqd->cp_hqd_pq_base_lo);
5e78835a 2664 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2665 mqd->cp_hqd_pq_base_hi);
2666
2667 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2668 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2669 mqd->cp_hqd_pq_control);
2670
2671 /* set the wb address whether it's enabled or not */
5e78835a 2672 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2673 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2674 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2675 mqd->cp_hqd_pq_rptr_report_addr_hi);
2676
2677 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2678 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2679 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2680 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2681 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2682
2683 /* enable the doorbell if requested */
2684 if (ring->use_doorbell) {
5e78835a 2685 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2686 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2687 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2688 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2689 }
2690
5e78835a 2691 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2692 mqd->cp_hqd_pq_doorbell_control);
2693
2694 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2695 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2696 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2697 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2698 mqd->cp_hqd_pq_wptr_hi);
2699
2700 /* set the vmid for the queue */
5e78835a 2701 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2702
5e78835a 2703 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2704 mqd->cp_hqd_persistent_state);
2705
2706 /* activate the queue */
5e78835a 2707 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2708 mqd->cp_hqd_active);
2709
72edadd5
TSD		 2710 if (ring->use_doorbell)
2711 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2712
2713 return 0;
2714}
2715
e322edc3 2716static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2717{
2718 struct amdgpu_device *adev = ring->adev;
e322edc3 2719 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2720 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2721
898b7893 2722 gfx_v9_0_kiq_setting(ring);
464826d6 2723
3224a12b 2724 if (adev->in_sriov_reset) { /* for GPU_RESET case */
464826d6 2725 /* reset MQD to a clean status */
0ef376ca 2726 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2727 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2728
2729 /* reset ring buffer */
2730 ring->wptr = 0;
b98724db 2731 amdgpu_ring_clear_ring(ring);
464826d6 2732
898b7893
AD		 2733 mutex_lock(&adev->srbm_mutex);
2734 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2735 gfx_v9_0_kiq_init_register(ring);
2736 soc15_grbm_select(adev, 0, 0, 0, 0);
2737 mutex_unlock(&adev->srbm_mutex);
464826d6 2738 } else {
ffe6d881
AD		 2739 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2740 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2741 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
ba0c19f5
AD		 2742 mutex_lock(&adev->srbm_mutex);
2743 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2744 gfx_v9_0_mqd_init(ring);
2745 gfx_v9_0_kiq_init_register(ring);
2746 soc15_grbm_select(adev, 0, 0, 0, 0);
2747 mutex_unlock(&adev->srbm_mutex);
2748
2749 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2750 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
464826d6
XY		 2751 }
2752
0f1dfd52 2753 return 0;
898b7893
AD		 2754}
2755
2756static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2757{
2758 struct amdgpu_device *adev = ring->adev;
898b7893
AD		 2759 struct v9_mqd *mqd = ring->mqd_ptr;
2760 int mqd_idx = ring - &adev->gfx.compute_ring[0];
898b7893 2761
3224a12b 2762 if (!adev->in_sriov_reset && !adev->gfx.in_suspend) {
ffe6d881
AD		 2763 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2764 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2765 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
464826d6
XY		 2766 mutex_lock(&adev->srbm_mutex);
2767 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2768 gfx_v9_0_mqd_init(ring);
464826d6
XY		 2769 soc15_grbm_select(adev, 0, 0, 0, 0);
2770 mutex_unlock(&adev->srbm_mutex);
2771
898b7893 2772 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2773 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3224a12b 2774 } else if (adev->in_sriov_reset) { /* for GPU_RESET case */
464826d6 2775 /* reset MQD to a clean status */
898b7893 2776 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2777 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2778
2779 /* reset ring buffer */
2780 ring->wptr = 0;
898b7893 2781 amdgpu_ring_clear_ring(ring);
ba0c19f5
AD		 2782 } else {
2783 amdgpu_ring_clear_ring(ring);
464826d6
XY		 2784 }
2785
464826d6
XY		 2786 return 0;
2787}
2788
2789static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2790{
2791 struct amdgpu_ring *ring = NULL;
2792 int r = 0, i;
2793
2794 gfx_v9_0_cp_compute_enable(adev, true);
2795
2796 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2797
2798 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2799 if (unlikely(r != 0))
2800 goto done;
2801
2802 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2803 if (!r) {
e322edc3 2804 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2805 amdgpu_bo_kunmap(ring->mqd_obj);
2806 ring->mqd_ptr = NULL;
464826d6 2807 }
e1d53aa8
AD		 2808 amdgpu_bo_unreserve(ring->mqd_obj);
2809 if (r)
2810 goto done;
464826d6
XY		 2811
2812 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2813 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2814
2815 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2816 if (unlikely(r != 0))
2817 goto done;
2818 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2819 if (!r) {
898b7893 2820 r = gfx_v9_0_kcq_init_queue(ring);
464826d6
XY		 2821 amdgpu_bo_kunmap(ring->mqd_obj);
2822 ring->mqd_ptr = NULL;
464826d6 2823 }
e1d53aa8
AD		 2824 amdgpu_bo_unreserve(ring->mqd_obj);
2825 if (r)
2826 goto done;
464826d6
XY		 2827 }
2828
0f1dfd52 2829 r = gfx_v9_0_kiq_kcq_enable(adev);
e1d53aa8
AD		 2830done:
2831 return r;
464826d6
XY		 2832}
2833
b1023571
KW		 2834static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2835{
bd3402ea 2836 int r, i;
b1023571
KW		 2837 struct amdgpu_ring *ring;
2838
2839 if (!(adev->flags & AMD_IS_APU))
2840 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2841
2842 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2843 /* legacy firmware loading */
2844 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2845 if (r)
2846 return r;
2847
2848 r = gfx_v9_0_cp_compute_load_microcode(adev);
2849 if (r)
2850 return r;
2851 }
2852
2853 r = gfx_v9_0_cp_gfx_resume(adev);
2854 if (r)
2855 return r;
2856
e30a5223 2857 r = gfx_v9_0_kiq_resume(adev);
b1023571
KW		 2858 if (r)
2859 return r;
2860
2861 ring = &adev->gfx.gfx_ring[0];
2862 r = amdgpu_ring_test_ring(ring);
2863 if (r) {
2864 ring->ready = false;
2865 return r;
2866 }
e30a5223
AD		 2867
2868 ring = &adev->gfx.kiq.ring;
2869 ring->ready = true;
2870 r = amdgpu_ring_test_ring(ring);
2871 if (r)
2872 ring->ready = false;
2873
b1023571
KW		 2874 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2875 ring = &adev->gfx.compute_ring[i];
2876
2877 ring->ready = true;
2878 r = amdgpu_ring_test_ring(ring);
2879 if (r)
2880 ring->ready = false;
2881 }
2882
2883 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2884
2885 return 0;
2886}
2887
2888static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2889{
2890 gfx_v9_0_cp_gfx_enable(adev, enable);
2891 gfx_v9_0_cp_compute_enable(adev, enable);
2892}
2893
2894static int gfx_v9_0_hw_init(void *handle)
2895{
2896 int r;
2897 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2898
2899 gfx_v9_0_init_golden_registers(adev);
2900
2901 gfx_v9_0_gpu_init(adev);
2902
2903 r = gfx_v9_0_rlc_resume(adev);
2904 if (r)
2905 return r;
2906
2907 r = gfx_v9_0_cp_resume(adev);
2908 if (r)
2909 return r;
2910
2911 r = gfx_v9_0_ngg_en(adev);
2912 if (r)
2913 return r;
2914
2915 return r;
2916}
2917
85f95ad6
ML		 2918static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
2919{
2920 struct amdgpu_device *adev = kiq_ring->adev;
2921 uint32_t scratch, tmp = 0;
2922 int r, i;
2923
2924 r = amdgpu_gfx_scratch_get(adev, &scratch);
2925 if (r) {
2926 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2927 return r;
2928 }
2929 WREG32(scratch, 0xCAFEDEAD);
2930
2931 r = amdgpu_ring_alloc(kiq_ring, 10);
2932 if (r) {
2933 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2934 amdgpu_gfx_scratch_free(adev, scratch);
2935 return r;
2936 }
2937
2938 /* unmap queues */
2939 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
2940 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2941 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
2942 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
2943 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
2944 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
2945 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
2946 amdgpu_ring_write(kiq_ring, 0);
2947 amdgpu_ring_write(kiq_ring, 0);
2948 amdgpu_ring_write(kiq_ring, 0);
2949 /* write to scratch for completion */
2950 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2951 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2952 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2953 amdgpu_ring_commit(kiq_ring);
2954
2955 for (i = 0; i < adev->usec_timeout; i++) {
2956 tmp = RREG32(scratch);
2957 if (tmp == 0xDEADBEEF)
2958 break;
2959 DRM_UDELAY(1);
2960 }
2961 if (i >= adev->usec_timeout) {
2962 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
2963 r = -EINVAL;
2964 }
2965 amdgpu_gfx_scratch_free(adev, scratch);
2966 return r;
2967}
2968
2969
b1023571
KW		 2970static int gfx_v9_0_hw_fini(void *handle)
2971{
2972 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
85f95ad6 2973 int i;
b1023571
KW		 2974
2975 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2976 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
85f95ad6
ML		 2977
2978 /* disable KCQ to avoid CPC touch memory not valid anymore */
2979 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2980 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
2981
464826d6
XY		 2982 if (amdgpu_sriov_vf(adev)) {
2983 pr_debug("For SRIOV client, shouldn't do anything.\n");
2984 return 0;
2985 }
b1023571
KW		 2986 gfx_v9_0_cp_enable(adev, false);
2987 gfx_v9_0_rlc_stop(adev);
b1023571
KW		 2988
2989 return 0;
2990}
2991
2992static int gfx_v9_0_suspend(void *handle)
2993{
2994 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2995
e30a5223 2996 adev->gfx.in_suspend = true;
b1023571
KW		 2997 return gfx_v9_0_hw_fini(adev);
2998}
2999
3000static int gfx_v9_0_resume(void *handle)
3001{
3002 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e30a5223 3003 int r;
b1023571 3004
e30a5223
AD		 3005 r = gfx_v9_0_hw_init(adev);
3006 adev->gfx.in_suspend = false;
3007 return r;
b1023571
KW		 3008}
3009
3010static bool gfx_v9_0_is_idle(void *handle)
3011{
3012 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3013
5e78835a 3014 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 3015 GRBM_STATUS, GUI_ACTIVE))
3016 return false;
3017 else
3018 return true;
3019}
3020
3021static int gfx_v9_0_wait_for_idle(void *handle)
3022{
3023 unsigned i;
b1023571
KW		 3024 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3025
3026 for (i = 0; i < adev->usec_timeout; i++) {
2b9bdfa7 3027 if (gfx_v9_0_is_idle(handle))
b1023571
KW		 3028 return 0;
3029 udelay(1);
3030 }
3031 return -ETIMEDOUT;
3032}
3033
b1023571
KW		 3034static int gfx_v9_0_soft_reset(void *handle)
3035{
3036 u32 grbm_soft_reset = 0;
3037 u32 tmp;
3038 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3039
3040 /* GRBM_STATUS */
5e78835a 3041 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 3042 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3043 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3044 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3045 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3046 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3047 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3048 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3049 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3050 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3051 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3052 }
3053
3054 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3055 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3056 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3057 }
3058
3059 /* GRBM_STATUS2 */
5e78835a 3060 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 3061 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3062 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3063 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3064
3065
75bac5c6 3066 if (grbm_soft_reset) {
b1023571
KW		 3067 /* stop the rlc */
3068 gfx_v9_0_rlc_stop(adev);
3069
3070 /* Disable GFX parsing/prefetching */
3071 gfx_v9_0_cp_gfx_enable(adev, false);
3072
3073 /* Disable MEC parsing/prefetching */
3074 gfx_v9_0_cp_compute_enable(adev, false);
3075
3076 if (grbm_soft_reset) {
5e78835a 3077 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3078 tmp |= grbm_soft_reset;
3079 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 3080 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3081 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3082
3083 udelay(50);
3084
3085 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 3086 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3087 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3088 }
3089
3090 /* Wait a little for things to settle down */
3091 udelay(50);
b1023571
KW		 3092 }
3093 return 0;
3094}
3095
3096static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3097{
3098 uint64_t clock;
3099
3100 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 3101 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3102 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3103 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 3104 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3105 return clock;
3106}
3107
3108static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3109 uint32_t vmid,
3110 uint32_t gds_base, uint32_t gds_size,
3111 uint32_t gws_base, uint32_t gws_size,
3112 uint32_t oa_base, uint32_t oa_size)
3113{
3114 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3115 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3116
3117 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3118 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3119
3120 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3121 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3122
3123 /* GDS Base */
3124 gfx_v9_0_write_data_to_reg(ring, 0, false,
3125 amdgpu_gds_reg_offset[vmid].mem_base,
3126 gds_base);
3127
3128 /* GDS Size */
3129 gfx_v9_0_write_data_to_reg(ring, 0, false,
3130 amdgpu_gds_reg_offset[vmid].mem_size,
3131 gds_size);
3132
3133 /* GWS */
3134 gfx_v9_0_write_data_to_reg(ring, 0, false,
3135 amdgpu_gds_reg_offset[vmid].gws,
3136 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3137
3138 /* OA */
3139 gfx_v9_0_write_data_to_reg(ring, 0, false,
3140 amdgpu_gds_reg_offset[vmid].oa,
3141 (1 << (oa_size + oa_base)) - (1 << oa_base));
3142}
3143
3144static int gfx_v9_0_early_init(void *handle)
3145{
3146 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3147
3148 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
78c16834 3149 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
b1023571
KW		 3150 gfx_v9_0_set_ring_funcs(adev);
3151 gfx_v9_0_set_irq_funcs(adev);
3152 gfx_v9_0_set_gds_init(adev);
3153 gfx_v9_0_set_rlc_funcs(adev);
3154
3155 return 0;
3156}
3157
3158static int gfx_v9_0_late_init(void *handle)
3159{
3160 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3161 int r;
3162
3163 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3164 if (r)
3165 return r;
3166
3167 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3168 if (r)
3169 return r;
3170
3171 return 0;
3172}
3173
3174static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3175{
3176 uint32_t rlc_setting, data;
3177 unsigned i;
3178
3179 if (adev->gfx.rlc.in_safe_mode)
3180 return;
3181
3182 /* if RLC is not enabled, do nothing */
5e78835a 3183 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3184 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3185 return;
3186
3187 if (adev->cg_flags &
3188 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3189 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3190 data = RLC_SAFE_MODE__CMD_MASK;
3191 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 3192 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3193
3194 /* wait for RLC_SAFE_MODE */
3195 for (i = 0; i < adev->usec_timeout; i++) {
3196 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3197 break;
3198 udelay(1);
3199 }
3200 adev->gfx.rlc.in_safe_mode = true;
3201 }
3202}
3203
3204static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3205{
3206 uint32_t rlc_setting, data;
3207
3208 if (!adev->gfx.rlc.in_safe_mode)
3209 return;
3210
3211 /* if RLC is not enabled, do nothing */
5e78835a 3212 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3213 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3214 return;
3215
3216 if (adev->cg_flags &
3217 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3218 /*
3219 * Try to exit safe mode only if it is already in safe
3220 * mode.
3221 */
3222 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 3223 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3224 adev->gfx.rlc.in_safe_mode = false;
3225 }
3226}
3227
197f95c8
HZ		 3228static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3229 bool enable)
3230{
3231 /* TODO: double check if we need to perform under safe mdoe */
3232 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3233
3234 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3235 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3236 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3237 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3238 } else {
3239 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3240 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3241 }
3242
3243 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3244}
3245
18924c71
HZ		 3246static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3247 bool enable)
3248{
3249 /* TODO: double check if we need to perform under safe mode */
3250 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3251
3252 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3253 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3254 else
3255 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3256
3257 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3258 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3259 else
3260 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3261
3262 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3263}
3264
b1023571
KW		 3265static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3266 bool enable)
3267{
3268 uint32_t data, def;
3269
3270 /* It is disabled by HW by default */
3271 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3272 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 3273 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3274 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3275 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3276 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3277 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3278
3279 /* only for Vega10 & Raven1 */
3280 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3281
3282 if (def != data)
5e78835a 3283 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3284
3285 /* MGLS is a global flag to control all MGLS in GFX */
3286 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3287 /* 2 - RLC memory Light sleep */
3288 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 3289 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3290 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3291 if (def != data)
5e78835a 3292 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3293 }
3294 /* 3 - CP memory Light sleep */
3295 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 3296 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3297 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3298 if (def != data)
5e78835a 3299 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3300 }
3301 }
3302 } else {
3303 /* 1 - MGCG_OVERRIDE */
5e78835a 3304 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3305 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3306 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3307 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3308 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3309 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3310 if (def != data)
5e78835a 3311 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3312
3313 /* 2 - disable MGLS in RLC */
5e78835a 3314 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3315 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3316 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 3317 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3318 }
3319
3320 /* 3 - disable MGLS in CP */
5e78835a 3321 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3322 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3323 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 3324 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3325 }
3326 }
3327}
3328
3329static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3330 bool enable)
3331{
3332 uint32_t data, def;
3333
3334 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3335
3336 /* Enable 3D CGCG/CGLS */
3337 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3338 /* write cmd to clear cgcg/cgls ov */
5e78835a 3339 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3340 /* unset CGCG override */
3341 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3342 /* update CGCG and CGLS override bits */
3343 if (def != data)
5e78835a 3344 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 3345 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 3346 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3347 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3348 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3349 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3350 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3351 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3352 if (def != data)
5e78835a 3353 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3354
3355 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3356 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3357 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3358 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3359 if (def != data)
5e78835a 3360 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 3361 } else {
3362 /* Disable CGCG/CGLS */
5e78835a 3363 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3364 /* disable cgcg, cgls should be disabled */
3365 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3366 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3367 /* disable cgcg and cgls in FSM */
3368 if (def != data)
5e78835a 3369 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3370 }
3371
3372 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3373}
3374
3375static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3376 bool enable)
3377{
3378 uint32_t def, data;
3379
3380 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3381
3382 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 3383 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3384 /* unset CGCG override */
3385 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3386 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3387 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3388 else
3389 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3390 /* update CGCG and CGLS override bits */
3391 if (def != data)
5e78835a 3392 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3393
3394 /* enable cgcg FSM(0x0020003F) */
5e78835a 3395 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3396 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3397 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3398 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3399 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3400 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3401 if (def != data)
5e78835a 3402 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3403
3404 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3405 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3406 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3407 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3408 if (def != data)
5e78835a 3409 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 3410 } else {
5e78835a 3411 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3412 /* reset CGCG/CGLS bits */
3413 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3414 /* disable cgcg and cgls in FSM */
3415 if (def != data)
5e78835a 3416 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3417 }
3418
3419 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3420}
3421
3422static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3423 bool enable)
3424{
3425 if (enable) {
3426 /* CGCG/CGLS should be enabled after MGCG/MGLS
3427 * === MGCG + MGLS ===
3428 */
3429 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3430 /* === CGCG /CGLS for GFX 3D Only === */
3431 gfx_v9_0_update_3d_clock_gating(adev, enable);
3432 /* === CGCG + CGLS === */
3433 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3434 } else {
3435 /* CGCG/CGLS should be disabled before MGCG/MGLS
3436 * === CGCG + CGLS ===
3437 */
3438 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3439 /* === CGCG /CGLS for GFX 3D Only === */
3440 gfx_v9_0_update_3d_clock_gating(adev, enable);
3441 /* === MGCG + MGLS === */
3442 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3443 }
3444 return 0;
3445}
3446
3447static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3448 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3449 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3450};
3451
3452static int gfx_v9_0_set_powergating_state(void *handle,
3453 enum amd_powergating_state state)
3454{
5897c99e 3455 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197f95c8 3456 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
5897c99e
HZ		 3457
3458 switch (adev->asic_type) {
3459 case CHIP_RAVEN:
3460 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3461 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3462 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3463 } else {
3464 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3465 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3466 }
3467
3468 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3469 gfx_v9_0_enable_cp_power_gating(adev, true);
3470 else
3471 gfx_v9_0_enable_cp_power_gating(adev, false);
197f95c8
HZ		 3472
3473 /* update gfx cgpg state */
3474 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
18924c71
HZ		 3475
3476 /* update mgcg state */
3477 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5897c99e
HZ		 3478 break;
3479 default:
3480 break;
3481 }
3482
b1023571
KW		 3483 return 0;
3484}
3485
3486static int gfx_v9_0_set_clockgating_state(void *handle,
3487 enum amd_clockgating_state state)
3488{
3489 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3490
fb82afab
XY		 3491 if (amdgpu_sriov_vf(adev))
3492 return 0;
3493
b1023571
KW		 3494 switch (adev->asic_type) {
3495 case CHIP_VEGA10:
a4dc61f5 3496 case CHIP_RAVEN:
b1023571
KW		 3497 gfx_v9_0_update_gfx_clock_gating(adev,
3498 state == AMD_CG_STATE_GATE ? true : false);
3499 break;
3500 default:
3501 break;
3502 }
3503 return 0;
3504}
3505
12ad27fa
HR		 3506static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3507{
3508 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3509 int data;
3510
3511 if (amdgpu_sriov_vf(adev))
3512 *flags = 0;
3513
3514 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 3515 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 3516 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3517 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3518
3519 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 3520 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 3521 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3522 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3523
3524 /* AMD_CG_SUPPORT_GFX_CGLS */
3525 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3526 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3527
3528 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 3529 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 3530 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3531 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3532
3533 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 3534 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 3535 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3536 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3537
3538 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 3539 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 3540 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3541 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3542
3543 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3544 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3545 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3546}
3547
b1023571
KW		 3548static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3549{
3550 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3551}
3552
3553static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3554{
3555 struct amdgpu_device *adev = ring->adev;
3556 u64 wptr;
3557
3558 /* XXX check if swapping is necessary on BE */
3559 if (ring->use_doorbell) {
3560 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3561 } else {
5e78835a
TSD		 3562 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3563 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 3564 }
3565
3566 return wptr;
3567}
3568
3569static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3570{
3571 struct amdgpu_device *adev = ring->adev;
3572
3573 if (ring->use_doorbell) {
3574 /* XXX check if swapping is necessary on BE */
3575 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3576 WDOORBELL64(ring->doorbell_index, ring->wptr);
3577 } else {
5e78835a
TSD		 3578 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3579 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 3580 }
3581}
3582
3583static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3584{
3585 u32 ref_and_mask, reg_mem_engine;
3586 struct nbio_hdp_flush_reg *nbio_hf_reg;
3587
29c3035f
AD		 3588 if (ring->adev->flags & AMD_IS_APU)
3589 nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
3590 else
b1023571
KW		 3591 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3592
3593 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3594 switch (ring->me) {
3595 case 1:
3596 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3597 break;
3598 case 2:
3599 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3600 break;
3601 default:
3602 return;
3603 }
3604 reg_mem_engine = 0;
3605 } else {
3606 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3607 reg_mem_engine = 1; /* pfp */
3608 }
3609
3610 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3611 nbio_hf_reg->hdp_flush_req_offset,
3612 nbio_hf_reg->hdp_flush_done_offset,
3613 ref_and_mask, ref_and_mask, 0x20);
3614}
3615
3616static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3617{
3618 gfx_v9_0_write_data_to_reg(ring, 0, true,
6e2e216f 3619 SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
b1023571
KW		 3620}
3621
3622static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3623 struct amdgpu_ib *ib,
3624 unsigned vm_id, bool ctx_switch)
3625{
eaa05d52 3626 u32 header, control = 0;
b1023571 3627
eaa05d52
ML		 3628 if (ib->flags & AMDGPU_IB_FLAG_CE)
3629 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3630 else
3631 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
b1023571 3632
eaa05d52 3633 control |= ib->length_dw | (vm_id << 24);
b1023571 3634
635e7132 3635 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
eaa05d52 3636 control |= INDIRECT_BUFFER_PRE_ENB(1);
9ccd52eb 3637
635e7132
ML		 3638 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3639 gfx_v9_0_ring_emit_de_meta(ring);
3640 }
3641
eaa05d52
ML		 3642 amdgpu_ring_write(ring, header);
3643BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3644 amdgpu_ring_write(ring,
b1023571 3645#ifdef __BIG_ENDIAN
eaa05d52 3646 (2 << 0) |
b1023571 3647#endif
eaa05d52
ML		 3648 lower_32_bits(ib->gpu_addr));
3649 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3650 amdgpu_ring_write(ring, control);
b1023571
KW		 3651}
3652
b1023571
KW		 3653static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3654 struct amdgpu_ib *ib,
3655 unsigned vm_id, bool ctx_switch)
3656{
3657 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3658
3659 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3660 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3661 amdgpu_ring_write(ring,
3662#ifdef __BIG_ENDIAN
3663 (2 << 0) |
3664#endif
3665 lower_32_bits(ib->gpu_addr));
3666 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3667 amdgpu_ring_write(ring, control);
3668}
3669
3670static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3671 u64 seq, unsigned flags)
3672{
3673 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3674 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3675
3676 /* RELEASE_MEM - flush caches, send int */
3677 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3678 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3679 EOP_TC_ACTION_EN |
3680 EOP_TC_WB_ACTION_EN |
3681 EOP_TC_MD_ACTION_EN |
3682 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3683 EVENT_INDEX(5)));
3684 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3685
3686 /*
3687 * the address should be Qword aligned if 64bit write, Dword
3688 * aligned if only send 32bit data low (discard data high)
3689 */
3690 if (write64bit)
3691 BUG_ON(addr & 0x7);
3692 else
3693 BUG_ON(addr & 0x3);
3694 amdgpu_ring_write(ring, lower_32_bits(addr));
3695 amdgpu_ring_write(ring, upper_32_bits(addr));
3696 amdgpu_ring_write(ring, lower_32_bits(seq));
3697 amdgpu_ring_write(ring, upper_32_bits(seq));
3698 amdgpu_ring_write(ring, 0);
3699}
3700
3701static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3702{
3703 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3704 uint32_t seq = ring->fence_drv.sync_seq;
3705 uint64_t addr = ring->fence_drv.gpu_addr;
3706
3707 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3708 lower_32_bits(addr), upper_32_bits(addr),
3709 seq, 0xffffffff, 4);
3710}
3711
3712static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3713 unsigned vm_id, uint64_t pd_addr)
3714{
2e819849 3715 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
b1023571 3716 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 3717 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 3718 unsigned eng = ring->vm_inv_eng;
b1023571 3719
b1166325
CK		 3720 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3721 pd_addr |= AMDGPU_PTE_VALID;
b1023571 3722
2e819849
CK		 3723 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3724 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3725 lower_32_bits(pd_addr));
b1023571 3726
2e819849
CK		 3727 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3728 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3729 upper_32_bits(pd_addr));
b1023571 3730
2e819849
CK		 3731 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3732 hub->vm_inv_eng0_req + eng, req);
b1023571 3733
2e819849
CK		 3734 /* wait for the invalidate to complete */
3735 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3736 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
b1023571
KW		 3737
3738 /* compute doesn't have PFP */
3739 if (usepfp) {
3740 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3741 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3742 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3743 }
3744}
3745
3746static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3747{
3748 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3749}
3750
3751static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3752{
3753 u64 wptr;
3754
3755 /* XXX check if swapping is necessary on BE */
3756 if (ring->use_doorbell)
3757 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3758 else
3759 BUG();
3760 return wptr;
3761}
3762
3763static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3764{
3765 struct amdgpu_device *adev = ring->adev;
3766
3767 /* XXX check if swapping is necessary on BE */
3768 if (ring->use_doorbell) {
3769 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3770 WDOORBELL64(ring->doorbell_index, ring->wptr);
3771 } else{
3772 BUG(); /* only DOORBELL method supported on gfx9 now */
3773 }
3774}
3775
aa6faa44
XY		 3776static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3777 u64 seq, unsigned int flags)
3778{
3779 /* we only allocate 32bit for each seq wb address */
3780 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3781
3782 /* write fence seq to the "addr" */
3783 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3784 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3785 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3786 amdgpu_ring_write(ring, lower_32_bits(addr));
3787 amdgpu_ring_write(ring, upper_32_bits(addr));
3788 amdgpu_ring_write(ring, lower_32_bits(seq));
3789
3790 if (flags & AMDGPU_FENCE_FLAG_INT) {
3791 /* set register to trigger INT */
3792 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3793 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3794 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3795 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3796 amdgpu_ring_write(ring, 0);
3797 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3798 }
3799}
3800
b1023571
KW		 3801static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3802{
3803 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3804 amdgpu_ring_write(ring, 0);
3805}
3806
cca02cd3
XY		 3807static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3808{
d81a2209 3809 struct v9_ce_ib_state ce_payload = {0};
cca02cd3
XY		 3810 uint64_t csa_addr;
3811 int cnt;
3812
3813 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3814 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3815
3816 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3817 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3818 WRITE_DATA_DST_SEL(8) |
3819 WR_CONFIRM) |
3820 WRITE_DATA_CACHE_POLICY(0));
3821 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3822 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3823 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3824}
3825
3826static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3827{
d81a2209 3828 struct v9_de_ib_state de_payload = {0};
cca02cd3
XY		 3829 uint64_t csa_addr, gds_addr;
3830 int cnt;
3831
3832 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3833 gds_addr = csa_addr + 4096;
3834 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3835 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3836
3837 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3838 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3839 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3840 WRITE_DATA_DST_SEL(8) |
3841 WR_CONFIRM) |
3842 WRITE_DATA_CACHE_POLICY(0));
3843 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3844 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3845 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3846}
3847
2ea6ab27
ML		 3848static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3849{
3850 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3851 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3852}
3853
b1023571
KW		 3854static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3855{
3856 uint32_t dw2 = 0;
3857
cca02cd3
XY		 3858 if (amdgpu_sriov_vf(ring->adev))
3859 gfx_v9_0_ring_emit_ce_meta(ring);
3860
2ea6ab27
ML		 3861 gfx_v9_0_ring_emit_tmz(ring, true);
3862
b1023571
KW		 3863 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3864 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3865 /* set load_global_config & load_global_uconfig */
3866 dw2 |= 0x8001;
3867 /* set load_cs_sh_regs */
3868 dw2 |= 0x01000000;
3869 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3870 dw2 |= 0x10002;
3871
3872 /* set load_ce_ram if preamble presented */
3873 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3874 dw2 |= 0x10000000;
3875 } else {
3876 /* still load_ce_ram if this is the first time preamble presented
3877 * although there is no context switch happens.
3878 */
3879 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3880 dw2 |= 0x10000000;
3881 }
3882
3883 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3884 amdgpu_ring_write(ring, dw2);
3885 amdgpu_ring_write(ring, 0);
3886}
3887
9a5e02b5
ML		 3888static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3889{
3890 unsigned ret;
3891 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3892 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3893 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3894 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3895 ret = ring->wptr & ring->buf_mask;
3896 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3897 return ret;
3898}
3899
3900static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3901{
3902 unsigned cur;
3903 BUG_ON(offset > ring->buf_mask);
3904 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3905
3906 cur = (ring->wptr & ring->buf_mask) - 1;
3907 if (likely(cur > offset))
3908 ring->ring[offset] = cur - offset;
3909 else
3910 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3911}
3912
aa6faa44
XY		 3913static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3914{
3915 struct amdgpu_device *adev = ring->adev;
3916
3917 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3918 amdgpu_ring_write(ring, 0 | /* src: register*/
3919 (5 << 8) | /* dst: memory */
3920 (1 << 20)); /* write confirm */
3921 amdgpu_ring_write(ring, reg);
3922 amdgpu_ring_write(ring, 0);
3923 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3924 adev->virt.reg_val_offs * 4));
3925 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3926 adev->virt.reg_val_offs * 4));
3927}
3928
3929static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3930 uint32_t val)
3931{
3932 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3933 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3934 amdgpu_ring_write(ring, reg);
3935 amdgpu_ring_write(ring, 0);
3936 amdgpu_ring_write(ring, val);
3937}
3938
b1023571
KW		 3939static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3940 enum amdgpu_interrupt_state state)
3941{
b1023571
KW		 3942 switch (state) {
3943 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3944 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 3945 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3946 TIME_STAMP_INT_ENABLE,
3947 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3948 break;
3949 default:
3950 break;
3951 }
3952}
3953
3954static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3955 int me, int pipe,
3956 enum amdgpu_interrupt_state state)
3957{
3958 u32 mec_int_cntl, mec_int_cntl_reg;
3959
3960 /*
d0c55cdf
AD		 3961 * amdgpu controls only the first MEC. That's why this function only
3962 * handles the setting of interrupts for this specific MEC. All other
b1023571
KW		 3963 * pipes' interrupts are set by amdkfd.
3964 */
3965
3966 if (me == 1) {
3967 switch (pipe) {
3968 case 0:
3969 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3970 break;
d0c55cdf
AD		 3971 case 1:
3972 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
3973 break;
3974 case 2:
3975 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
3976 break;
3977 case 3:
3978 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
3979 break;
b1023571
KW		 3980 default:
3981 DRM_DEBUG("invalid pipe %d\n", pipe);
3982 return;
3983 }
3984 } else {
3985 DRM_DEBUG("invalid me %d\n", me);
3986 return;
3987 }
3988
3989 switch (state) {
3990 case AMDGPU_IRQ_STATE_DISABLE:
3991 mec_int_cntl = RREG32(mec_int_cntl_reg);
3992 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3993 TIME_STAMP_INT_ENABLE, 0);
3994 WREG32(mec_int_cntl_reg, mec_int_cntl);
3995 break;
3996 case AMDGPU_IRQ_STATE_ENABLE:
3997 mec_int_cntl = RREG32(mec_int_cntl_reg);
3998 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3999 TIME_STAMP_INT_ENABLE, 1);
4000 WREG32(mec_int_cntl_reg, mec_int_cntl);
4001 break;
4002 default:
4003 break;
4004 }
4005}
4006
4007static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4008 struct amdgpu_irq_src *source,
4009 unsigned type,
4010 enum amdgpu_interrupt_state state)
4011{
b1023571
KW		 4012 switch (state) {
4013 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4014 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 4015 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4016 PRIV_REG_INT_ENABLE,
4017 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4018 break;
4019 default:
4020 break;
4021 }
4022
4023 return 0;
4024}
4025
4026static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4027 struct amdgpu_irq_src *source,
4028 unsigned type,
4029 enum amdgpu_interrupt_state state)
4030{
b1023571
KW		 4031 switch (state) {
4032 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4033 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 4034 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4035 PRIV_INSTR_INT_ENABLE,
4036 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4037 default:
4038 break;
4039 }
4040
4041 return 0;
4042}
4043
4044static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4045 struct amdgpu_irq_src *src,
4046 unsigned type,
4047 enum amdgpu_interrupt_state state)
4048{
4049 switch (type) {
4050 case AMDGPU_CP_IRQ_GFX_EOP:
4051 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4052 break;
4053 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4054 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4055 break;
4056 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4057 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4058 break;
4059 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4060 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4061 break;
4062 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4063 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4064 break;
4065 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4066 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4067 break;
4068 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4069 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4070 break;
4071 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4072 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4073 break;
4074 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4075 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4076 break;
4077 default:
4078 break;
4079 }
4080 return 0;
4081}
4082
4083static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4084 struct amdgpu_irq_src *source,
4085 struct amdgpu_iv_entry *entry)
4086{
4087 int i;
4088 u8 me_id, pipe_id, queue_id;
4089 struct amdgpu_ring *ring;
4090
4091 DRM_DEBUG("IH: CP EOP\n");
4092 me_id = (entry->ring_id & 0x0c) >> 2;
4093 pipe_id = (entry->ring_id & 0x03) >> 0;
4094 queue_id = (entry->ring_id & 0x70) >> 4;
4095
4096 switch (me_id) {
4097 case 0:
4098 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4099 break;
4100 case 1:
4101 case 2:
4102 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4103 ring = &adev->gfx.compute_ring[i];
4104 /* Per-queue interrupt is supported for MEC starting from VI.
4105 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4106 */
4107 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4108 amdgpu_fence_process(ring);
4109 }
4110 break;
4111 }
4112 return 0;
4113}
4114
4115static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4116 struct amdgpu_irq_src *source,
4117 struct amdgpu_iv_entry *entry)
4118{
4119 DRM_ERROR("Illegal register access in command stream\n");
4120 schedule_work(&adev->reset_work);
4121 return 0;
4122}
4123
4124static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4125 struct amdgpu_irq_src *source,
4126 struct amdgpu_iv_entry *entry)
4127{
4128 DRM_ERROR("Illegal instruction in command stream\n");
4129 schedule_work(&adev->reset_work);
4130 return 0;
4131}
4132
97031e25
XY		 4133static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4134 struct amdgpu_irq_src *src,
4135 unsigned int type,
4136 enum amdgpu_interrupt_state state)
4137{
4138 uint32_t tmp, target;
1c4ecf48 4139 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4140
4141 if (ring->me == 1)
4142 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4143 else
4144 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4145 target += ring->pipe;
4146
4147 switch (type) {
4148 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4149 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 4150 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4151 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4152 GENERIC2_INT_ENABLE, 0);
5e78835a 4153 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4154
4155 tmp = RREG32(target);
4156 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4157 GENERIC2_INT_ENABLE, 0);
4158 WREG32(target, tmp);
4159 } else {
5e78835a 4160 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4161 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4162 GENERIC2_INT_ENABLE, 1);
5e78835a 4163 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4164
4165 tmp = RREG32(target);
4166 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4167 GENERIC2_INT_ENABLE, 1);
4168 WREG32(target, tmp);
4169 }
4170 break;
4171 default:
4172 BUG(); /* kiq only support GENERIC2_INT now */
4173 break;
4174 }
4175 return 0;
4176}
4177
4178static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4179 struct amdgpu_irq_src *source,
4180 struct amdgpu_iv_entry *entry)
4181{
4182 u8 me_id, pipe_id, queue_id;
1c4ecf48 4183 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4184
4185 me_id = (entry->ring_id & 0x0c) >> 2;
4186 pipe_id = (entry->ring_id & 0x03) >> 0;
4187 queue_id = (entry->ring_id & 0x70) >> 4;
4188 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4189 me_id, pipe_id, queue_id);
4190
4191 amdgpu_fence_process(ring);
4192 return 0;
4193}
4194
fa04b6ba 4195static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
b1023571
KW		 4196 .name = "gfx_v9_0",
4197 .early_init = gfx_v9_0_early_init,
4198 .late_init = gfx_v9_0_late_init,
4199 .sw_init = gfx_v9_0_sw_init,
4200 .sw_fini = gfx_v9_0_sw_fini,
4201 .hw_init = gfx_v9_0_hw_init,
4202 .hw_fini = gfx_v9_0_hw_fini,
4203 .suspend = gfx_v9_0_suspend,
4204 .resume = gfx_v9_0_resume,
4205 .is_idle = gfx_v9_0_is_idle,
4206 .wait_for_idle = gfx_v9_0_wait_for_idle,
4207 .soft_reset = gfx_v9_0_soft_reset,
4208 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4209 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 4210 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 4211};
4212
4213static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4214 .type = AMDGPU_RING_TYPE_GFX,
4215 .align_mask = 0xff,
4216 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4217 .support_64bit_ptrs = true,
0eeb68b3 4218 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4219 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4220 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4221 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 4222 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4223 5 + /* COND_EXEC */
4224 7 + /* PIPELINE_SYNC */
2e819849 4225 24 + /* VM_FLUSH */
e9d672b2
ML		 4226 8 + /* FENCE for VM_FLUSH */
4227 20 + /* GDS switch */
4228 4 + /* double SWITCH_BUFFER,
4229 the first COND_EXEC jump to the place just
4230 prior to this double SWITCH_BUFFER */
4231 5 + /* COND_EXEC */
4232 7 + /* HDP_flush */
4233 4 + /* VGT_flush */
4234 14 + /* CE_META */
4235 31 + /* DE_META */
4236 3 + /* CNTX_CTRL */
4237 5 + /* HDP_INVL */
4238 8 + 8 + /* FENCE x2 */
4239 2, /* SWITCH_BUFFER */
b1023571
KW		 4240 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4241 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4242 .emit_fence = gfx_v9_0_ring_emit_fence,
4243 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4244 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4245 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4246 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4247 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4248 .test_ring = gfx_v9_0_ring_test_ring,
4249 .test_ib = gfx_v9_0_ring_test_ib,
4250 .insert_nop = amdgpu_ring_insert_nop,
4251 .pad_ib = amdgpu_ring_generic_pad_ib,
4252 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4253 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 4254 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4255 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3b4d68e9 4256 .emit_tmz = gfx_v9_0_ring_emit_tmz,
b1023571
KW		 4257};
4258
4259static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4260 .type = AMDGPU_RING_TYPE_COMPUTE,
4261 .align_mask = 0xff,
4262 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4263 .support_64bit_ptrs = true,
0eeb68b3 4264 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4265 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4266 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4267 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4268 .emit_frame_size =
4269 20 + /* gfx_v9_0_ring_emit_gds_switch */
4270 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4271 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4272 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4273 24 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 4274 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4275 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4276 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4277 .emit_fence = gfx_v9_0_ring_emit_fence,
4278 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4279 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4280 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4281 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4282 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4283 .test_ring = gfx_v9_0_ring_test_ring,
4284 .test_ib = gfx_v9_0_ring_test_ib,
4285 .insert_nop = amdgpu_ring_insert_nop,
4286 .pad_ib = amdgpu_ring_generic_pad_ib,
4287};
4288
aa6faa44
XY		 4289static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4290 .type = AMDGPU_RING_TYPE_KIQ,
4291 .align_mask = 0xff,
4292 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4293 .support_64bit_ptrs = true,
0eeb68b3 4294 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 4295 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4296 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4297 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4298 .emit_frame_size =
4299 20 + /* gfx_v9_0_ring_emit_gds_switch */
4300 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4301 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4302 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4303 24 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 4304 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4305 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4306 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4307 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 4308 .test_ring = gfx_v9_0_ring_test_ring,
4309 .test_ib = gfx_v9_0_ring_test_ib,
4310 .insert_nop = amdgpu_ring_insert_nop,
4311 .pad_ib = amdgpu_ring_generic_pad_ib,
4312 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4313 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4314};
b1023571
KW		 4315
4316static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4317{
4318 int i;
4319
aa6faa44
XY		 4320 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4321
b1023571
KW		 4322 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4323 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4324
4325 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4326 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4327}
4328
97031e25
XY		 4329static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4330 .set = gfx_v9_0_kiq_set_interrupt_state,
4331 .process = gfx_v9_0_kiq_irq,
4332};
4333
b1023571
KW		 4334static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4335 .set = gfx_v9_0_set_eop_interrupt_state,
4336 .process = gfx_v9_0_eop_irq,
4337};
4338
4339static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4340 .set = gfx_v9_0_set_priv_reg_fault_state,
4341 .process = gfx_v9_0_priv_reg_irq,
4342};
4343
4344static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4345 .set = gfx_v9_0_set_priv_inst_fault_state,
4346 .process = gfx_v9_0_priv_inst_irq,
4347};
4348
4349static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4350{
4351 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4352 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4353
4354 adev->gfx.priv_reg_irq.num_types = 1;
4355 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4356
4357 adev->gfx.priv_inst_irq.num_types = 1;
4358 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 4359
4360 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4361 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 4362}
4363
4364static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4365{
4366 switch (adev->asic_type) {
4367 case CHIP_VEGA10:
a4dc61f5 4368 case CHIP_RAVEN:
b1023571
KW		 4369 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4370 break;
4371 default:
4372 break;
4373 }
4374}
4375
4376static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4377{
4378 /* init asci gds info */
5e78835a 4379 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 4380 adev->gds.gws.total_size = 64;
4381 adev->gds.oa.total_size = 16;
4382
4383 if (adev->gds.mem.total_size == 64 * 1024) {
4384 adev->gds.mem.gfx_partition_size = 4096;
4385 adev->gds.mem.cs_partition_size = 4096;
4386
4387 adev->gds.gws.gfx_partition_size = 4;
4388 adev->gds.gws.cs_partition_size = 4;
4389
4390 adev->gds.oa.gfx_partition_size = 4;
4391 adev->gds.oa.cs_partition_size = 1;
4392 } else {
4393 adev->gds.mem.gfx_partition_size = 1024;
4394 adev->gds.mem.cs_partition_size = 1024;
4395
4396 adev->gds.gws.gfx_partition_size = 16;
4397 adev->gds.gws.cs_partition_size = 16;
4398
4399 adev->gds.oa.gfx_partition_size = 4;
4400 adev->gds.oa.cs_partition_size = 4;
4401 }
4402}
4403
c94d38f0
NH		 4404static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4405 u32 bitmap)
4406{
4407 u32 data;
4408
4409 if (!bitmap)
4410 return;
4411
4412 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4413 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4414
4415 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4416}
4417
b1023571
KW		 4418static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4419{
4420 u32 data, mask;
4421
5e78835a
TSD		 4422 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4423 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 4424
4425 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4426 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4427
378506a7 4428 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
b1023571
KW		 4429
4430 return (~data) & mask;
4431}
4432
4433static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4434 struct amdgpu_cu_info *cu_info)
4435{
4436 int i, j, k, counter, active_cu_number = 0;
4437 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
c94d38f0 4438 unsigned disable_masks[4 * 2];
b1023571
KW		 4439
4440 if (!adev || !cu_info)
4441 return -EINVAL;
4442
c94d38f0
NH		 4443 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4444
b1023571
KW		 4445 mutex_lock(&adev->grbm_idx_mutex);
4446 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4447 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4448 mask = 1;
4449 ao_bitmap = 0;
4450 counter = 0;
4451 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
c94d38f0
NH		 4452 if (i < 4 && j < 2)
4453 gfx_v9_0_set_user_cu_inactive_bitmap(
4454 adev, disable_masks[i * 2 + j]);
b1023571
KW		 4455 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4456 cu_info->bitmap[i][j] = bitmap;
4457
fe723cd3 4458 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
b1023571 4459 if (bitmap & mask) {
fe723cd3 4460 if (counter < adev->gfx.config.max_cu_per_sh)
b1023571
KW		 4461 ao_bitmap |= mask;
4462 counter ++;
4463 }
4464 mask <<= 1;
4465 }
4466 active_cu_number += counter;
dbfe85ea
FC		 4467 if (i < 2 && j < 2)
4468 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4469 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
b1023571
KW		 4470 }
4471 }
4472 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4473 mutex_unlock(&adev->grbm_idx_mutex);
4474
4475 cu_info->number = active_cu_number;
4476 cu_info->ao_cu_mask = ao_cu_mask;
4477
4478 return 0;
4479}
4480
b1023571
KW		 4481const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4482{
4483 .type = AMD_IP_BLOCK_TYPE_GFX,
4484 .major = 9,
4485 .minor = 0,
4486 .rev = 0,
4487 .funcs = &gfx_v9_0_ip_funcs,
4488};
Ubuntu Jammy Linux kernel mirror