]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd/amdgpu: Tidy up register list formatting.
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
248a1d6f 24#include <drm/drmP.h>
b1023571
KW		 25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
268cb4c7 41#define GFX9_MEC_HPD_SIZE 2048
6bce4667
HZ		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
b1023571 45
91d3130a
HZ		 46#define mmPWR_MISC_CNTL_STATUS 0x0183
47#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
b1023571
KW		 52
53MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
060d124b
CZ		 60MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62MODULE_FIRMWARE("amdgpu/raven_me.bin");
63MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
b1023571
KW		 67static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
68{
35c32f20
TSD		 69 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
73 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
77 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
81 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
85 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
86 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
87 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
88 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
89 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
90 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
91 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
92 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
93 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
94 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
95 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
96 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
97 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
98 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
99 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
100 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
101 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
102 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
103 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
104 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
105 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
106 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
107 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
108 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
109 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
110 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
111 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
112 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
113 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
114 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
115 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
116 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
117 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
118 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
119 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
120 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
121 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
122 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
123 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
124 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
125 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
126 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
127 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
128 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
129 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
130 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
131 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
132 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
b1023571
KW		 133};
134
135static const u32 golden_settings_gc_9_0[] =
136{
f8af9332
KW		 137 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
138 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
139 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
140 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
141 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
142 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
b1023571
KW		 143 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
144 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
145 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
f8af9332
KW		 146 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
147 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
148 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
149 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
150 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
ba219b3c 151 SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
f8af9332 152 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
ba219b3c 153 SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
b1023571
KW		 154 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
155 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
156 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
f8af9332
KW		 157 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
158 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
159 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
b1023571
KW		 160};
161
162static const u32 golden_settings_gc_9_0_vg10[] =
163{
164 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
165 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
166 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
167 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
168 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
169 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
f8af9332 170 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
b1023571
KW		 171};
172
a5fdb336
CZ		 173static const u32 golden_settings_gc_9_1[] =
174{
175 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
01b5cc36
HZ		 176 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
177 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
178 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 179 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
180 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
01b5cc36 181 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 182 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
183 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
184 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
01b5cc36
HZ		 185 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
186 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
187 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
188 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
189 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 190 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
191 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
192 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
01b5cc36
HZ		 193 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
194 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
195 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
a5fdb336
CZ		 196};
197
198static const u32 golden_settings_gc_9_1_rv1[] =
199{
7b6ba9ea
HZ		 200 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
201 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
202 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
203 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
204 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
205 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
a5fdb336 206 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
b1023571
KW		 207};
208
209#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
7b6ba9ea 210#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
b1023571
KW		 211
212static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
213static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
214static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
215static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
216static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
217 struct amdgpu_cu_info *cu_info);
218static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
219static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
635e7132 220static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
b1023571
KW		 221
222static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
223{
224 switch (adev->asic_type) {
225 case CHIP_VEGA10:
226 amdgpu_program_register_sequence(adev,
227 golden_settings_gc_9_0,
228 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
229 amdgpu_program_register_sequence(adev,
230 golden_settings_gc_9_0_vg10,
231 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
232 break;
a5fdb336
CZ		 233 case CHIP_RAVEN:
234 amdgpu_program_register_sequence(adev,
235 golden_settings_gc_9_1,
236 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
237 amdgpu_program_register_sequence(adev,
238 golden_settings_gc_9_1_rv1,
239 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
240 break;
b1023571
KW		 241 default:
242 break;
243 }
244}
245
246static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
247{
6a05148f 248 adev->gfx.scratch.num_reg = 8;
b1023571
KW		 249 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
250 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
251}
252
253static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
254 bool wc, uint32_t reg, uint32_t val)
255{
256 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
257 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
258 WRITE_DATA_DST_SEL(0) |
259 (wc ? WR_CONFIRM : 0));
260 amdgpu_ring_write(ring, reg);
261 amdgpu_ring_write(ring, 0);
262 amdgpu_ring_write(ring, val);
263}
264
265static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
266 int mem_space, int opt, uint32_t addr0,
267 uint32_t addr1, uint32_t ref, uint32_t mask,
268 uint32_t inv)
269{
270 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
271 amdgpu_ring_write(ring,
272 /* memory (1) or register (0) */
273 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
274 WAIT_REG_MEM_OPERATION(opt) | /* wait */
275 WAIT_REG_MEM_FUNCTION(3) | /* equal */
276 WAIT_REG_MEM_ENGINE(eng_sel)));
277
278 if (mem_space)
279 BUG_ON(addr0 & 0x3); /* Dword align */
280 amdgpu_ring_write(ring, addr0);
281 amdgpu_ring_write(ring, addr1);
282 amdgpu_ring_write(ring, ref);
283 amdgpu_ring_write(ring, mask);
284 amdgpu_ring_write(ring, inv); /* poll interval */
285}
286
287static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
288{
289 struct amdgpu_device *adev = ring->adev;
290 uint32_t scratch;
291 uint32_t tmp = 0;
292 unsigned i;
293 int r;
294
295 r = amdgpu_gfx_scratch_get(adev, &scratch);
296 if (r) {
297 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
298 return r;
299 }
300 WREG32(scratch, 0xCAFEDEAD);
301 r = amdgpu_ring_alloc(ring, 3);
302 if (r) {
303 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
304 ring->idx, r);
305 amdgpu_gfx_scratch_free(adev, scratch);
306 return r;
307 }
308 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
309 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
310 amdgpu_ring_write(ring, 0xDEADBEEF);
311 amdgpu_ring_commit(ring);
312
313 for (i = 0; i < adev->usec_timeout; i++) {
314 tmp = RREG32(scratch);
315 if (tmp == 0xDEADBEEF)
316 break;
317 DRM_UDELAY(1);
318 }
319 if (i < adev->usec_timeout) {
320 DRM_INFO("ring test on %d succeeded in %d usecs\n",
321 ring->idx, i);
322 } else {
323 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
324 ring->idx, scratch, tmp);
325 r = -EINVAL;
326 }
327 amdgpu_gfx_scratch_free(adev, scratch);
328 return r;
329}
330
331static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
332{
333 struct amdgpu_device *adev = ring->adev;
334 struct amdgpu_ib ib;
335 struct dma_fence *f = NULL;
336 uint32_t scratch;
337 uint32_t tmp = 0;
338 long r;
339
340 r = amdgpu_gfx_scratch_get(adev, &scratch);
341 if (r) {
342 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
343 return r;
344 }
345 WREG32(scratch, 0xCAFEDEAD);
346 memset(&ib, 0, sizeof(ib));
347 r = amdgpu_ib_get(adev, NULL, 256, &ib);
348 if (r) {
349 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
350 goto err1;
351 }
352 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
353 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
354 ib.ptr[2] = 0xDEADBEEF;
355 ib.length_dw = 3;
356
357 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
358 if (r)
359 goto err2;
360
361 r = dma_fence_wait_timeout(f, false, timeout);
362 if (r == 0) {
363 DRM_ERROR("amdgpu: IB test timed out.\n");
364 r = -ETIMEDOUT;
365 goto err2;
366 } else if (r < 0) {
367 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
368 goto err2;
369 }
370 tmp = RREG32(scratch);
371 if (tmp == 0xDEADBEEF) {
372 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
373 r = 0;
374 } else {
375 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
376 scratch, tmp);
377 r = -EINVAL;
378 }
379err2:
380 amdgpu_ib_free(adev, &ib, NULL);
381 dma_fence_put(f);
382err1:
383 amdgpu_gfx_scratch_free(adev, scratch);
384 return r;
385}
386
387static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
388{
389 const char *chip_name;
390 char fw_name[30];
391 int err;
392 struct amdgpu_firmware_info *info = NULL;
393 const struct common_firmware_header *header = NULL;
394 const struct gfx_firmware_header_v1_0 *cp_hdr;
a4d41ad0
HZ		 395 const struct rlc_firmware_header_v2_0 *rlc_hdr;
396 unsigned int *tmp = NULL;
397 unsigned int i = 0;
b1023571
KW		 398
399 DRM_DEBUG("\n");
400
401 switch (adev->asic_type) {
402 case CHIP_VEGA10:
403 chip_name = "vega10";
404 break;
eaa85724
CZ		 405 case CHIP_RAVEN:
406 chip_name = "raven";
407 break;
b1023571
KW		 408 default:
409 BUG();
410 }
411
412 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
413 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
414 if (err)
415 goto out;
416 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
417 if (err)
418 goto out;
419 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
420 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
421 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
422
423 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
424 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
425 if (err)
426 goto out;
427 err = amdgpu_ucode_validate(adev->gfx.me_fw);
428 if (err)
429 goto out;
430 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
431 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
432 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
433
434 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
435 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
436 if (err)
437 goto out;
438 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
439 if (err)
440 goto out;
441 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
442 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
443 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
444
445 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
446 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
447 if (err)
448 goto out;
449 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
a4d41ad0
HZ		 450 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
451 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
452 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
453 adev->gfx.rlc.save_and_restore_offset =
454 le32_to_cpu(rlc_hdr->save_and_restore_offset);
455 adev->gfx.rlc.clear_state_descriptor_offset =
456 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
457 adev->gfx.rlc.avail_scratch_ram_locations =
458 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
459 adev->gfx.rlc.reg_restore_list_size =
460 le32_to_cpu(rlc_hdr->reg_restore_list_size);
461 adev->gfx.rlc.reg_list_format_start =
462 le32_to_cpu(rlc_hdr->reg_list_format_start);
463 adev->gfx.rlc.reg_list_format_separate_start =
464 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
465 adev->gfx.rlc.starting_offsets_start =
466 le32_to_cpu(rlc_hdr->starting_offsets_start);
467 adev->gfx.rlc.reg_list_format_size_bytes =
468 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
469 adev->gfx.rlc.reg_list_size_bytes =
470 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
471 adev->gfx.rlc.register_list_format =
472 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
473 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
474 if (!adev->gfx.rlc.register_list_format) {
475 err = -ENOMEM;
476 goto out;
477 }
478
479 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
480 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
481 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
482 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
483
484 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
485
486 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
487 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
488 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
489 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
b1023571
KW		 490
491 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
492 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
493 if (err)
494 goto out;
495 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
496 if (err)
497 goto out;
498 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
499 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
500 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
501
502
503 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
504 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
505 if (!err) {
506 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
507 if (err)
508 goto out;
509 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
510 adev->gfx.mec2_fw->data;
511 adev->gfx.mec2_fw_version =
512 le32_to_cpu(cp_hdr->header.ucode_version);
513 adev->gfx.mec2_feature_version =
514 le32_to_cpu(cp_hdr->ucode_feature_version);
515 } else {
516 err = 0;
517 adev->gfx.mec2_fw = NULL;
518 }
519
520 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
521 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
522 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
523 info->fw = adev->gfx.pfp_fw;
524 header = (const struct common_firmware_header *)info->fw->data;
525 adev->firmware.fw_size +=
526 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
527
528 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
529 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
530 info->fw = adev->gfx.me_fw;
531 header = (const struct common_firmware_header *)info->fw->data;
532 adev->firmware.fw_size +=
533 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
534
535 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
536 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
537 info->fw = adev->gfx.ce_fw;
538 header = (const struct common_firmware_header *)info->fw->data;
539 adev->firmware.fw_size +=
540 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
541
542 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
543 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
544 info->fw = adev->gfx.rlc_fw;
545 header = (const struct common_firmware_header *)info->fw->data;
546 adev->firmware.fw_size +=
547 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
548
549 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
550 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
551 info->fw = adev->gfx.mec_fw;
552 header = (const struct common_firmware_header *)info->fw->data;
553 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
554 adev->firmware.fw_size +=
555 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
556
557 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
558 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
559 info->fw = adev->gfx.mec_fw;
560 adev->firmware.fw_size +=
561 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
562
563 if (adev->gfx.mec2_fw) {
564 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
565 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
566 info->fw = adev->gfx.mec2_fw;
567 header = (const struct common_firmware_header *)info->fw->data;
568 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
569 adev->firmware.fw_size +=
570 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
571 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
572 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
573 info->fw = adev->gfx.mec2_fw;
574 adev->firmware.fw_size +=
575 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
576 }
577
578 }
579
580out:
581 if (err) {
582 dev_err(adev->dev,
583 "gfx9: Failed to load firmware \"%s\"\n",
584 fw_name);
585 release_firmware(adev->gfx.pfp_fw);
586 adev->gfx.pfp_fw = NULL;
587 release_firmware(adev->gfx.me_fw);
588 adev->gfx.me_fw = NULL;
589 release_firmware(adev->gfx.ce_fw);
590 adev->gfx.ce_fw = NULL;
591 release_firmware(adev->gfx.rlc_fw);
592 adev->gfx.rlc_fw = NULL;
593 release_firmware(adev->gfx.mec_fw);
594 adev->gfx.mec_fw = NULL;
595 release_firmware(adev->gfx.mec2_fw);
596 adev->gfx.mec2_fw = NULL;
597 }
598 return err;
599}
600
c9719c69
HZ		 601static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
602{
603 u32 count = 0;
604 const struct cs_section_def *sect = NULL;
605 const struct cs_extent_def *ext = NULL;
606
607 /* begin clear state */
608 count += 2;
609 /* context control state */
610 count += 3;
611
612 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
613 for (ext = sect->section; ext->extent != NULL; ++ext) {
614 if (sect->id == SECT_CONTEXT)
615 count += 2 + ext->reg_count;
616 else
617 return 0;
618 }
619 }
620
621 /* end clear state */
622 count += 2;
623 /* clear state */
624 count += 2;
625
626 return count;
627}
628
629static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
630 volatile u32 *buffer)
631{
632 u32 count = 0, i;
633 const struct cs_section_def *sect = NULL;
634 const struct cs_extent_def *ext = NULL;
635
636 if (adev->gfx.rlc.cs_data == NULL)
637 return;
638 if (buffer == NULL)
639 return;
640
641 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
642 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
643
644 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
645 buffer[count++] = cpu_to_le32(0x80000000);
646 buffer[count++] = cpu_to_le32(0x80000000);
647
648 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
649 for (ext = sect->section; ext->extent != NULL; ++ext) {
650 if (sect->id == SECT_CONTEXT) {
651 buffer[count++] =
652 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
653 buffer[count++] = cpu_to_le32(ext->reg_index -
654 PACKET3_SET_CONTEXT_REG_START);
655 for (i = 0; i < ext->reg_count; i++)
656 buffer[count++] = cpu_to_le32(ext->extent[i]);
657 } else {
658 return;
659 }
660 }
661 }
662
663 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
664 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
665
666 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
667 buffer[count++] = cpu_to_le32(0);
668}
669
ba7bb665
HZ		 670static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
671{
e5475e16 672 uint32_t data;
ba7bb665
HZ		 673
674 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
675 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
676 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
677 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
678 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
679
680 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
681 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
682
683 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
684 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
685
686 mutex_lock(&adev->grbm_idx_mutex);
687 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
688 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
689 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
690
691 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
e5475e16
TSD		 692 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
693 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
694 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
ba7bb665
HZ		 695 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
696
697 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
698 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
699 data &= 0x0000FFFF;
700 data |= 0x00C00000;
701 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
702
703 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
704 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
705
706 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
707 * but used for RLC_LB_CNTL configuration */
708 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
e5475e16
TSD		 709 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
710 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
ba7bb665
HZ		 711 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
712 mutex_unlock(&adev->grbm_idx_mutex);
713}
714
e8835e0e
HZ		 715static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
716{
e5475e16 717 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
e8835e0e
HZ		 718}
719
c9719c69
HZ		 720static void rv_init_cp_jump_table(struct amdgpu_device *adev)
721{
722 const __le32 *fw_data;
723 volatile u32 *dst_ptr;
724 int me, i, max_me = 5;
725 u32 bo_offset = 0;
726 u32 table_offset, table_size;
727
728 /* write the cp table buffer */
729 dst_ptr = adev->gfx.rlc.cp_table_ptr;
730 for (me = 0; me < max_me; me++) {
731 if (me == 0) {
732 const struct gfx_firmware_header_v1_0 *hdr =
733 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
734 fw_data = (const __le32 *)
735 (adev->gfx.ce_fw->data +
736 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
737 table_offset = le32_to_cpu(hdr->jt_offset);
738 table_size = le32_to_cpu(hdr->jt_size);
739 } else if (me == 1) {
740 const struct gfx_firmware_header_v1_0 *hdr =
741 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
742 fw_data = (const __le32 *)
743 (adev->gfx.pfp_fw->data +
744 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
745 table_offset = le32_to_cpu(hdr->jt_offset);
746 table_size = le32_to_cpu(hdr->jt_size);
747 } else if (me == 2) {
748 const struct gfx_firmware_header_v1_0 *hdr =
749 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
750 fw_data = (const __le32 *)
751 (adev->gfx.me_fw->data +
752 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
753 table_offset = le32_to_cpu(hdr->jt_offset);
754 table_size = le32_to_cpu(hdr->jt_size);
755 } else if (me == 3) {
756 const struct gfx_firmware_header_v1_0 *hdr =
757 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
758 fw_data = (const __le32 *)
759 (adev->gfx.mec_fw->data +
760 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
761 table_offset = le32_to_cpu(hdr->jt_offset);
762 table_size = le32_to_cpu(hdr->jt_size);
763 } else if (me == 4) {
764 const struct gfx_firmware_header_v1_0 *hdr =
765 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
766 fw_data = (const __le32 *)
767 (adev->gfx.mec2_fw->data +
768 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
769 table_offset = le32_to_cpu(hdr->jt_offset);
770 table_size = le32_to_cpu(hdr->jt_size);
771 }
772
773 for (i = 0; i < table_size; i ++) {
774 dst_ptr[bo_offset + i] =
775 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
776 }
777
778 bo_offset += table_size;
779 }
780}
781
782static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
783{
784 /* clear state block */
785 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
786 &adev->gfx.rlc.clear_state_gpu_addr,
787 (void **)&adev->gfx.rlc.cs_ptr);
788
789 /* jump table block */
790 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
791 &adev->gfx.rlc.cp_table_gpu_addr,
792 (void **)&adev->gfx.rlc.cp_table_ptr);
793}
794
795static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
796{
797 volatile u32 *dst_ptr;
798 u32 dws;
799 const struct cs_section_def *cs_data;
800 int r;
801
802 adev->gfx.rlc.cs_data = gfx9_cs_data;
803
804 cs_data = adev->gfx.rlc.cs_data;
805
806 if (cs_data) {
807 /* clear state block */
808 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
a4a02777
CK		 809 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
810 AMDGPU_GEM_DOMAIN_VRAM,
811 &adev->gfx.rlc.clear_state_obj,
812 &adev->gfx.rlc.clear_state_gpu_addr,
813 (void **)&adev->gfx.rlc.cs_ptr);
814 if (r) {
815 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
816 r);
817 gfx_v9_0_rlc_fini(adev);
818 return r;
c9719c69
HZ		 819 }
820 /* set up the cs buffer */
821 dst_ptr = adev->gfx.rlc.cs_ptr;
822 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
823 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
824 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
825 }
826
827 if (adev->asic_type == CHIP_RAVEN) {
828 /* TODO: double check the cp_table_size for RV */
829 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
a4a02777
CK		 830 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
831 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
832 &adev->gfx.rlc.cp_table_obj,
833 &adev->gfx.rlc.cp_table_gpu_addr,
834 (void **)&adev->gfx.rlc.cp_table_ptr);
835 if (r) {
836 dev_err(adev->dev,
837 "(%d) failed to create cp table bo\n", r);
838 gfx_v9_0_rlc_fini(adev);
839 return r;
c9719c69
HZ		 840 }
841
842 rv_init_cp_jump_table(adev);
843 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
844 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
ba7bb665
HZ		 845
846 gfx_v9_0_init_lbpw(adev);
c9719c69
HZ		 847 }
848
849 return 0;
850}
851
b1023571
KW		 852static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
853{
078af1a3
CK		 854 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
855 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
b1023571
KW		 856}
857
b1023571
KW		 858static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
859{
860 int r;
861 u32 *hpd;
862 const __le32 *fw_data;
863 unsigned fw_size;
864 u32 *fw;
42794b27 865 size_t mec_hpd_size;
b1023571
KW		 866
867 const struct gfx_firmware_header_v1_0 *mec_hdr;
868
78c16834
AR		 869 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
870
78c16834 871 /* take ownership of the relevant compute queues */
41f6a99a 872 amdgpu_gfx_compute_queue_acquire(adev);
78c16834 873 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
b1023571 874
a4a02777
CK		 875 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
876 AMDGPU_GEM_DOMAIN_GTT,
877 &adev->gfx.mec.hpd_eop_obj,
878 &adev->gfx.mec.hpd_eop_gpu_addr,
879 (void **)&hpd);
b1023571 880 if (r) {
a4a02777 881 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
b1023571
KW		 882 gfx_v9_0_mec_fini(adev);
883 return r;
884 }
885
886 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
887
888 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
889 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
890
891 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
892
893 fw_data = (const __le32 *)
894 (adev->gfx.mec_fw->data +
895 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
896 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
897
a4a02777
CK		 898 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
899 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
900 &adev->gfx.mec.mec_fw_obj,
901 &adev->gfx.mec.mec_fw_gpu_addr,
902 (void **)&fw);
b1023571 903 if (r) {
a4a02777 904 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
b1023571
KW		 905 gfx_v9_0_mec_fini(adev);
906 return r;
907 }
a4a02777 908
b1023571
KW		 909 memcpy(fw, fw_data, fw_size);
910
911 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
912 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
913
b1023571
KW		 914 return 0;
915}
916
917static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
918{
5e78835a 919 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 920 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
921 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
922 (address << SQ_IND_INDEX__INDEX__SHIFT) |
923 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 924 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 925}
926
927static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
928 uint32_t wave, uint32_t thread,
929 uint32_t regno, uint32_t num, uint32_t *out)
930{
5e78835a 931 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 932 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
933 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
934 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
935 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
936 (SQ_IND_INDEX__FORCE_READ_MASK) |
937 (SQ_IND_INDEX__AUTO_INCR_MASK));
938 while (num--)
5e78835a 939 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 940}
941
942static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
943{
944 /* type 1 wave data */
945 dst[(*no_fields)++] = 1;
946 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
947 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
948 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
949 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
950 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
951 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
952 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
953 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
954 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
955 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
956 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
957 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
958 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
959 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
960}
961
962static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
963 uint32_t wave, uint32_t start,
964 uint32_t size, uint32_t *dst)
965{
966 wave_read_regs(
967 adev, simd, wave, 0,
968 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
969}
970
971
972static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
973 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
974 .select_se_sh = &gfx_v9_0_select_se_sh,
975 .read_wave_data = &gfx_v9_0_read_wave_data,
976 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
977};
978
979static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
980{
981 u32 gb_addr_config;
982
983 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
984
985 switch (adev->asic_type) {
986 case CHIP_VEGA10:
b1023571 987 adev->gfx.config.max_hw_contexts = 8;
b1023571
KW		 988 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
989 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
990 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
991 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
992 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
993 break;
5cf7433d
CZ		 994 case CHIP_RAVEN:
995 adev->gfx.config.max_hw_contexts = 8;
996 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
997 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
998 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
999 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1000 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1001 break;
b1023571
KW		 1002 default:
1003 BUG();
1004 break;
1005 }
1006
1007 adev->gfx.config.gb_addr_config = gb_addr_config;
1008
1009 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1010 REG_GET_FIELD(
1011 adev->gfx.config.gb_addr_config,
1012 GB_ADDR_CONFIG,
1013 NUM_PIPES);
ad7d0ff3
AD		 1014
1015 adev->gfx.config.max_tile_pipes =
1016 adev->gfx.config.gb_addr_config_fields.num_pipes;
1017
b1023571
KW		 1018 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1019 REG_GET_FIELD(
1020 adev->gfx.config.gb_addr_config,
1021 GB_ADDR_CONFIG,
1022 NUM_BANKS);
1023 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1024 REG_GET_FIELD(
1025 adev->gfx.config.gb_addr_config,
1026 GB_ADDR_CONFIG,
1027 MAX_COMPRESSED_FRAGS);
1028 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1029 REG_GET_FIELD(
1030 adev->gfx.config.gb_addr_config,
1031 GB_ADDR_CONFIG,
1032 NUM_RB_PER_SE);
1033 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1034 REG_GET_FIELD(
1035 adev->gfx.config.gb_addr_config,
1036 GB_ADDR_CONFIG,
1037 NUM_SHADER_ENGINES);
1038 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1039 REG_GET_FIELD(
1040 adev->gfx.config.gb_addr_config,
1041 GB_ADDR_CONFIG,
1042 PIPE_INTERLEAVE_SIZE));
1043}
1044
1045static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1046 struct amdgpu_ngg_buf *ngg_buf,
1047 int size_se,
1048 int default_size_se)
1049{
1050 int r;
1051
1052 if (size_se < 0) {
1053 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1054 return -EINVAL;
1055 }
1056 size_se = size_se ? size_se : default_size_se;
1057
42ce2243 1058 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 1059 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1060 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1061 &ngg_buf->bo,
1062 &ngg_buf->gpu_addr,
1063 NULL);
1064 if (r) {
1065 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1066 return r;
1067 }
1068 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1069
1070 return r;
1071}
1072
1073static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1074{
1075 int i;
1076
1077 for (i = 0; i < NGG_BUF_MAX; i++)
1078 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1079 &adev->gfx.ngg.buf[i].gpu_addr,
1080 NULL);
1081
1082 memset(&adev->gfx.ngg.buf[0], 0,
1083 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1084
1085 adev->gfx.ngg.init = false;
1086
1087 return 0;
1088}
1089
1090static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1091{
1092 int r;
1093
1094 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1095 return 0;
1096
1097 /* GDS reserve memory: 64 bytes alignment */
1098 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1099 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1100 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1101 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1102 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1103
1104 /* Primitive Buffer */
af8baf15 1105 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
b1023571
KW		 1106 amdgpu_prim_buf_per_se,
1107 64 * 1024);
1108 if (r) {
1109 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1110 goto err;
1111 }
1112
1113 /* Position Buffer */
af8baf15 1114 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
b1023571
KW		 1115 amdgpu_pos_buf_per_se,
1116 256 * 1024);
1117 if (r) {
1118 dev_err(adev->dev, "Failed to create Position Buffer\n");
1119 goto err;
1120 }
1121
1122 /* Control Sideband */
af8baf15 1123 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
b1023571
KW		 1124 amdgpu_cntl_sb_buf_per_se,
1125 256);
1126 if (r) {
1127 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1128 goto err;
1129 }
1130
1131 /* Parameter Cache, not created by default */
1132 if (amdgpu_param_buf_per_se <= 0)
1133 goto out;
1134
af8baf15 1135 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
b1023571
KW		 1136 amdgpu_param_buf_per_se,
1137 512 * 1024);
1138 if (r) {
1139 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1140 goto err;
1141 }
1142
1143out:
1144 adev->gfx.ngg.init = true;
1145 return 0;
1146err:
1147 gfx_v9_0_ngg_fini(adev);
1148 return r;
1149}
1150
1151static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1152{
1153 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1154 int r;
1155 u32 data;
1156 u32 size;
1157 u32 base;
1158
1159 if (!amdgpu_ngg)
1160 return 0;
1161
1162 /* Program buffer size */
1163 data = 0;
af8baf15 1164 size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
b1023571
KW		 1165 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
1166
af8baf15 1167 size = adev->gfx.ngg.buf[NGG_POS].size / 256;
b1023571
KW		 1168 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
1169
5e78835a 1170 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571
KW		 1171
1172 data = 0;
af8baf15 1173 size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
b1023571
KW		 1174 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
1175
af8baf15 1176 size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
b1023571
KW		 1177 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
1178
5e78835a 1179 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 1180
1181 /* Program buffer base address */
af8baf15 1182 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1183 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 1184 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571 1185
af8baf15 1186 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1187 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 1188 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571 1189
af8baf15 1190 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1191 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 1192 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571 1193
af8baf15 1194 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1195 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 1196 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571 1197
af8baf15 1198 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1199 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 1200 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571 1201
af8baf15 1202 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1203 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 1204 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 1205
1206 /* Clear GDS reserved memory */
1207 r = amdgpu_ring_alloc(ring, 17);
1208 if (r) {
1209 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1210 ring->idx, r);
1211 return r;
1212 }
1213
1214 gfx_v9_0_write_data_to_reg(ring, 0, false,
1215 amdgpu_gds_reg_offset[0].mem_size,
1216 (adev->gds.mem.total_size +
1217 adev->gfx.ngg.gds_reserve_size) >>
1218 AMDGPU_GDS_SHIFT);
1219
1220 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1221 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1222 PACKET3_DMA_DATA_SRC_SEL(2)));
1223 amdgpu_ring_write(ring, 0);
1224 amdgpu_ring_write(ring, 0);
1225 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1226 amdgpu_ring_write(ring, 0);
1227 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1228
1229
1230 gfx_v9_0_write_data_to_reg(ring, 0, false,
1231 amdgpu_gds_reg_offset[0].mem_size, 0);
1232
1233 amdgpu_ring_commit(ring);
1234
1235 return 0;
1236}
1237
1361f455
AD		 1238static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1239 int mec, int pipe, int queue)
1240{
1241 int r;
1242 unsigned irq_type;
1243 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1244
1245 ring = &adev->gfx.compute_ring[ring_id];
1246
1247 /* mec0 is me1 */
1248 ring->me = mec + 1;
1249 ring->pipe = pipe;
1250 ring->queue = queue;
1251
1252 ring->ring_obj = NULL;
1253 ring->use_doorbell = true;
7366af81 1254 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1361f455
AD		 1255 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1256 + (ring_id * GFX9_MEC_HPD_SIZE);
1257 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1258
1259 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1260 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1261 + ring->pipe;
1262
1263 /* type-2 packets are deprecated on MEC, use type-3 instead */
1264 r = amdgpu_ring_init(adev, ring, 1024,
1265 &adev->gfx.eop_irq, irq_type);
1266 if (r)
1267 return r;
1268
1269
1270 return 0;
1271}
1272
b1023571
KW		 1273static int gfx_v9_0_sw_init(void *handle)
1274{
1361f455 1275 int i, j, k, r, ring_id;
b1023571 1276 struct amdgpu_ring *ring;
ac104e99 1277 struct amdgpu_kiq *kiq;
b1023571
KW		 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279
4853bbb6
AD		 1280 switch (adev->asic_type) {
1281 case CHIP_VEGA10:
1282 case CHIP_RAVEN:
1283 adev->gfx.mec.num_mec = 2;
1284 break;
1285 default:
1286 adev->gfx.mec.num_mec = 1;
1287 break;
1288 }
1289
1290 adev->gfx.mec.num_pipe_per_mec = 4;
1291 adev->gfx.mec.num_queue_per_pipe = 8;
1292
97031e25
XY		 1293 /* KIQ event */
1294 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1295 if (r)
1296 return r;
1297
b1023571
KW		 1298 /* EOP Event */
1299 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1300 if (r)
1301 return r;
1302
1303 /* Privileged reg */
1304 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1305 &adev->gfx.priv_reg_irq);
1306 if (r)
1307 return r;
1308
1309 /* Privileged inst */
1310 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1311 &adev->gfx.priv_inst_irq);
1312 if (r)
1313 return r;
1314
1315 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1316
1317 gfx_v9_0_scratch_init(adev);
1318
1319 r = gfx_v9_0_init_microcode(adev);
1320 if (r) {
1321 DRM_ERROR("Failed to load gfx firmware!\n");
1322 return r;
1323 }
1324
c9719c69
HZ		 1325 r = gfx_v9_0_rlc_init(adev);
1326 if (r) {
1327 DRM_ERROR("Failed to init rlc BOs!\n");
1328 return r;
1329 }
1330
b1023571
KW		 1331 r = gfx_v9_0_mec_init(adev);
1332 if (r) {
1333 DRM_ERROR("Failed to init MEC BOs!\n");
1334 return r;
1335 }
1336
1337 /* set up the gfx ring */
1338 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1339 ring = &adev->gfx.gfx_ring[i];
1340 ring->ring_obj = NULL;
1341 sprintf(ring->name, "gfx");
1342 ring->use_doorbell = true;
1343 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1344 r = amdgpu_ring_init(adev, ring, 1024,
1345 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1346 if (r)
1347 return r;
1348 }
1349
1361f455
AD		 1350 /* set up the compute queues - allocate horizontally across pipes */
1351 ring_id = 0;
1352 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1353 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1354 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2db0cdbe 1355 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1361f455
AD		 1356 continue;
1357
1358 r = gfx_v9_0_compute_ring_init(adev,
1359 ring_id,
1360 i, k, j);
1361 if (r)
1362 return r;
1363
1364 ring_id++;
1365 }
b1023571 1366 }
b1023571
KW		 1367 }
1368
71c37505 1369 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
e30a5223
AD		 1370 if (r) {
1371 DRM_ERROR("Failed to init KIQ BOs!\n");
1372 return r;
1373 }
ac104e99 1374
e30a5223 1375 kiq = &adev->gfx.kiq;
71c37505 1376 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
e30a5223
AD		 1377 if (r)
1378 return r;
464826d6 1379
e30a5223 1380 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
ffe6d881 1381 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
e30a5223
AD		 1382 if (r)
1383 return r;
ac104e99 1384
b1023571
KW		 1385 /* reserve GDS, GWS and OA resource for gfx */
1386 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1387 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1388 &adev->gds.gds_gfx_bo, NULL, NULL);
1389 if (r)
1390 return r;
1391
1392 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1393 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1394 &adev->gds.gws_gfx_bo, NULL, NULL);
1395 if (r)
1396 return r;
1397
1398 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1399 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1400 &adev->gds.oa_gfx_bo, NULL, NULL);
1401 if (r)
1402 return r;
1403
1404 adev->gfx.ce_ram_size = 0x8000;
1405
1406 gfx_v9_0_gpu_early_init(adev);
1407
1408 r = gfx_v9_0_ngg_init(adev);
1409 if (r)
1410 return r;
1411
1412 return 0;
1413}
1414
1415
1416static int gfx_v9_0_sw_fini(void *handle)
1417{
1418 int i;
1419 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1420
1421 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1422 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1423 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1424
1425 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1426 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1427 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1428 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1429
b9683c21 1430 amdgpu_gfx_compute_mqd_sw_fini(adev);
71c37505
AD		 1431 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1432 amdgpu_gfx_kiq_fini(adev);
ac104e99 1433
b1023571
KW		 1434 gfx_v9_0_mec_fini(adev);
1435 gfx_v9_0_ngg_fini(adev);
1436
1437 return 0;
1438}
1439
1440
1441static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1442{
1443 /* TODO */
1444}
1445
1446static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1447{
be448a4d 1448 u32 data;
b1023571 1449
be448a4d
NH		 1450 if (instance == 0xffffffff)
1451 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1452 else
1453 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1454
1455 if (se_num == 0xffffffff)
b1023571 1456 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
be448a4d 1457 else
b1023571 1458 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
be448a4d
NH		 1459
1460 if (sh_num == 0xffffffff)
1461 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1462 else
b1023571 1463 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
be448a4d 1464
5e78835a 1465 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1466}
1467
b1023571
KW		 1468static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1469{
1470 u32 data, mask;
1471
5e78835a
TSD		 1472 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1473 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1474
1475 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1476 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1477
378506a7
AD		 1478 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1479 adev->gfx.config.max_sh_per_se);
b1023571
KW		 1480
1481 return (~data) & mask;
1482}
1483
1484static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1485{
1486 int i, j;
2572c24c 1487 u32 data;
b1023571
KW		 1488 u32 active_rbs = 0;
1489 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1490 adev->gfx.config.max_sh_per_se;
1491
1492 mutex_lock(&adev->grbm_idx_mutex);
1493 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1494 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1495 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1496 data = gfx_v9_0_get_rb_active_bitmap(adev);
1497 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1498 rb_bitmap_width_per_sh);
1499 }
1500 }
1501 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1502 mutex_unlock(&adev->grbm_idx_mutex);
1503
1504 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1505 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1506}
1507
1508#define DEFAULT_SH_MEM_BASES (0x6000)
1509#define FIRST_COMPUTE_VMID (8)
1510#define LAST_COMPUTE_VMID (16)
1511static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1512{
1513 int i;
1514 uint32_t sh_mem_config;
1515 uint32_t sh_mem_bases;
1516
1517 /*
1518 * Configure apertures:
1519 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1520 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1521 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1522 */
1523 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1524
1525 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1526 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
eaa05d52 1527 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
b1023571
KW		 1528
1529 mutex_lock(&adev->srbm_mutex);
1530 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1531 soc15_grbm_select(adev, 0, 0, 0, i);
1532 /* CP and shaders */
5e78835a
TSD		 1533 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1534 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1535 }
1536 soc15_grbm_select(adev, 0, 0, 0, 0);
1537 mutex_unlock(&adev->srbm_mutex);
1538}
1539
1540static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1541{
1542 u32 tmp;
1543 int i;
1544
40f06773 1545 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1546
1547 gfx_v9_0_tiling_mode_table_init(adev);
1548
1549 gfx_v9_0_setup_rb(adev);
1550 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1551
1552 /* XXX SH_MEM regs */
1553 /* where to put LDS, scratch, GPUVM in FSA64 space */
1554 mutex_lock(&adev->srbm_mutex);
1555 for (i = 0; i < 16; i++) {
1556 soc15_grbm_select(adev, 0, 0, 0, i);
1557 /* CP and shaders */
1558 tmp = 0;
1559 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1560 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5e78835a
TSD		 1561 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1562 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
b1023571
KW		 1563 }
1564 soc15_grbm_select(adev, 0, 0, 0, 0);
1565
1566 mutex_unlock(&adev->srbm_mutex);
1567
1568 gfx_v9_0_init_compute_vmid(adev);
1569
1570 mutex_lock(&adev->grbm_idx_mutex);
1571 /*
1572 * making sure that the following register writes will be broadcasted
1573 * to all the shaders
1574 */
1575 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1576
5e78835a 1577 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1578 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1579 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1580 (adev->gfx.config.sc_prim_fifo_size_backend <<
1581 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1582 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1583 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1584 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1585 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1586 mutex_unlock(&adev->grbm_idx_mutex);
1587
1588}
1589
1590static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1591{
1592 u32 i, j, k;
1593 u32 mask;
1594
1595 mutex_lock(&adev->grbm_idx_mutex);
1596 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1597 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1598 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1599 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1600 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1601 break;
1602 udelay(1);
1603 }
1604 }
1605 }
1606 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1607 mutex_unlock(&adev->grbm_idx_mutex);
1608
1609 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1610 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1611 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1612 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1613 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1614 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1615 break;
1616 udelay(1);
1617 }
1618}
1619
1620static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1621 bool enable)
1622{
5e78835a 1623 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571 1624
b1023571
KW		 1625 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1626 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1627 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1628 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1629
5e78835a 1630 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1631}
1632
6bce4667
HZ		 1633static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1634{
1635 /* csib */
1636 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1637 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1638 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1639 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1640 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1641 adev->gfx.rlc.clear_state_size);
1642}
1643
1644static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1645 int indirect_offset,
1646 int list_size,
1647 int *unique_indirect_regs,
1648 int *unique_indirect_reg_count,
1649 int max_indirect_reg_count,
1650 int *indirect_start_offsets,
1651 int *indirect_start_offsets_count,
1652 int max_indirect_start_offsets_count)
1653{
1654 int idx;
1655 bool new_entry = true;
1656
1657 for (; indirect_offset < list_size; indirect_offset++) {
1658
1659 if (new_entry) {
1660 new_entry = false;
1661 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1662 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1663 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1664 }
1665
1666 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1667 new_entry = true;
1668 continue;
1669 }
1670
1671 indirect_offset += 2;
1672
1673 /* look for the matching indice */
1674 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1675 if (unique_indirect_regs[idx] ==
1676 register_list_format[indirect_offset])
1677 break;
1678 }
1679
1680 if (idx >= *unique_indirect_reg_count) {
1681 unique_indirect_regs[*unique_indirect_reg_count] =
1682 register_list_format[indirect_offset];
1683 idx = *unique_indirect_reg_count;
1684 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1685 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1686 }
1687
1688 register_list_format[indirect_offset] = idx;
1689 }
1690}
1691
1692static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1693{
1694 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1695 int unique_indirect_reg_count = 0;
1696
1697 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1698 int indirect_start_offsets_count = 0;
1699
1700 int list_size = 0;
1701 int i = 0;
1702 u32 tmp = 0;
1703
1704 u32 *register_list_format =
1705 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1706 if (!register_list_format)
1707 return -ENOMEM;
1708 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1709 adev->gfx.rlc.reg_list_format_size_bytes);
1710
1711 /* setup unique_indirect_regs array and indirect_start_offsets array */
1712 gfx_v9_0_parse_ind_reg_list(register_list_format,
1713 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1714 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1715 unique_indirect_regs,
1716 &unique_indirect_reg_count,
1717 sizeof(unique_indirect_regs)/sizeof(int),
1718 indirect_start_offsets,
1719 &indirect_start_offsets_count,
1720 sizeof(indirect_start_offsets)/sizeof(int));
1721
1722 /* enable auto inc in case it is disabled */
1723 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1724 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1725 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1726
1727 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1728 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1729 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1730 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1731 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1732 adev->gfx.rlc.register_restore[i]);
1733
1734 /* load direct register */
1735 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1736 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1737 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1738 adev->gfx.rlc.register_restore[i]);
1739
1740 /* load indirect register */
1741 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1742 adev->gfx.rlc.reg_list_format_start);
1743 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1744 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1745 register_list_format[i]);
1746
1747 /* set save/restore list size */
1748 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1749 list_size = list_size >> 1;
1750 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1751 adev->gfx.rlc.reg_restore_list_size);
1752 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1753
1754 /* write the starting offsets to RLC scratch ram */
1755 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1756 adev->gfx.rlc.starting_offsets_start);
1757 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1758 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1759 indirect_start_offsets[i]);
1760
1761 /* load unique indirect regs*/
1762 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1763 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1764 unique_indirect_regs[i] & 0x3FFFF);
1765 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1766 unique_indirect_regs[i] >> 20);
1767 }
1768
1769 kfree(register_list_format);
1770 return 0;
1771}
1772
1773static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1774{
1775 u32 tmp = 0;
1776
1777 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1778 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1779 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1780}
1781
91d3130a
HZ		 1782static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1783 bool enable)
1784{
1785 uint32_t data = 0;
1786 uint32_t default_data = 0;
1787
1788 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1789 if (enable == true) {
1790 /* enable GFXIP control over CGPG */
1791 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1792 if(default_data != data)
1793 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1794
1795 /* update status */
1796 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1797 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1798 if(default_data != data)
1799 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1800 } else {
1801 /* restore GFXIP control over GCPG */
1802 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1803 if(default_data != data)
1804 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1805 }
1806}
1807
1808static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1809{
1810 uint32_t data = 0;
1811
1812 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1813 AMD_PG_SUPPORT_GFX_SMG |
1814 AMD_PG_SUPPORT_GFX_DMG)) {
1815 /* init IDLE_POLL_COUNT = 60 */
1816 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1817 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1818 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1819 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1820
1821 /* init RLC PG Delay */
1822 data = 0;
1823 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1824 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1825 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1826 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1827 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1828
1829 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1830 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1831 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1832 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1833
1834 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1835 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1836 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1837 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1838
1839 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1840 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1841
1842 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1843 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1844 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1845
1846 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1847 }
1848}
1849
ed5ad1e4
HZ		 1850static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1851 bool enable)
1852{
1853 uint32_t data = 0;
1854 uint32_t default_data = 0;
1855
1856 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1857
1858 if (enable == true) {
1859 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1860 if (default_data != data)
1861 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1862 } else {
1863 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1864 if(default_data != data)
1865 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1866 }
1867}
1868
1869static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1870 bool enable)
1871{
1872 uint32_t data = 0;
1873 uint32_t default_data = 0;
1874
1875 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1876
1877 if (enable == true) {
1878 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1879 if(default_data != data)
1880 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1881 } else {
1882 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1883 if(default_data != data)
1884 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1885 }
1886}
1887
3a6cc477
HZ		 1888static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1889 bool enable)
1890{
1891 uint32_t data = 0;
1892 uint32_t default_data = 0;
1893
1894 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1895
1896 if (enable == true) {
1897 data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
1898 if(default_data != data)
1899 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1900 } else {
1901 data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
1902 if(default_data != data)
1903 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1904 }
1905}
1906
197f95c8
HZ		 1907static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
1908 bool enable)
1909{
1910 uint32_t data, default_data;
1911
1912 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1913 if (enable == true)
1914 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
1915 else
1916 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
1917 if(default_data != data)
1918 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1919}
1920
1921static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
1922 bool enable)
1923{
1924 uint32_t data, default_data;
1925
1926 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1927 if (enable == true)
1928 data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
1929 else
1930 data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
1931 if(default_data != data)
1932 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1933
1934 if (!enable)
1935 /* read any GFX register to wake up GFX */
1936 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
1937}
1938
552c8f76 1939static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
1940 bool enable)
18924c71
HZ		 1941{
1942 uint32_t data, default_data;
1943
1944 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1945 if (enable == true)
1946 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
1947 else
1948 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
1949 if(default_data != data)
1950 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1951}
1952
552c8f76 1953static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
18924c71
HZ		 1954 bool enable)
1955{
1956 uint32_t data, default_data;
1957
1958 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1959 if (enable == true)
1960 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
1961 else
1962 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
1963 if(default_data != data)
1964 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1965}
1966
6bce4667
HZ		 1967static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
1968{
1969 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1970 AMD_PG_SUPPORT_GFX_SMG |
1971 AMD_PG_SUPPORT_GFX_DMG |
1972 AMD_PG_SUPPORT_CP |
1973 AMD_PG_SUPPORT_GDS |
1974 AMD_PG_SUPPORT_RLC_SMU_HS)) {
1975 gfx_v9_0_init_csb(adev);
1976 gfx_v9_0_init_rlc_save_restore_list(adev);
1977 gfx_v9_0_enable_save_restore_machine(adev);
91d3130a
HZ		 1978
1979 if (adev->asic_type == CHIP_RAVEN) {
1980 WREG32(mmRLC_JUMP_TABLE_RESTORE,
1981 adev->gfx.rlc.cp_table_gpu_addr >> 8);
1982 gfx_v9_0_init_gfx_power_gating(adev);
3a6cc477 1983
ed5ad1e4
HZ		 1984 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
1985 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
1986 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
1987 } else {
1988 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
1989 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
1990 }
3a6cc477
HZ		 1991
1992 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
1993 gfx_v9_0_enable_cp_power_gating(adev, true);
1994 else
1995 gfx_v9_0_enable_cp_power_gating(adev, false);
91d3130a 1996 }
6bce4667
HZ		 1997 }
1998}
1999
b1023571
KW		 2000void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2001{
5e78835a 2002 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 2003
2004 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5e78835a 2005 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
b1023571
KW		 2006
2007 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2008
2009 gfx_v9_0_wait_for_rlc_serdes(adev);
2010}
2011
2012static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2013{
596c8e8b 2014 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 2015 udelay(50);
596c8e8b 2016 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 2017 udelay(50);
2018}
2019
2020static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2021{
2022#ifdef AMDGPU_RLC_DEBUG_RETRY
2023 u32 rlc_ucode_ver;
2024#endif
b1023571 2025
342cda25 2026 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 2027
2028 /* carrizo do enable cp interrupt after cp inited */
2029 if (!(adev->flags & AMD_IS_APU))
2030 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2031
2032 udelay(50);
2033
2034#ifdef AMDGPU_RLC_DEBUG_RETRY
2035 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 2036 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 2037 if(rlc_ucode_ver == 0x108) {
2038 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2039 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2040 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2041 * default is 0x9C4 to create a 100us interval */
5e78835a 2042 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571 2043 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
eaa05d52 2044 * to disable the page fault retry interrupts, default is
b1023571 2045 * 0x100 (256) */
5e78835a 2046 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 2047 }
2048#endif
2049}
2050
2051static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2052{
2053 const struct rlc_firmware_header_v2_0 *hdr;
2054 const __le32 *fw_data;
2055 unsigned i, fw_size;
2056
2057 if (!adev->gfx.rlc_fw)
2058 return -EINVAL;
2059
2060 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2061 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2062
2063 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2064 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2065 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2066
5e78835a 2067 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 2068 RLCG_UCODE_LOADING_START_ADDRESS);
2069 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2070 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2071 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 2072
2073 return 0;
2074}
2075
2076static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2077{
2078 int r;
2079
cfee05bc
ML		 2080 if (amdgpu_sriov_vf(adev))
2081 return 0;
2082
b1023571
KW		 2083 gfx_v9_0_rlc_stop(adev);
2084
2085 /* disable CG */
5e78835a 2086 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 2087
2088 /* disable PG */
5e78835a 2089 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 2090
2091 gfx_v9_0_rlc_reset(adev);
2092
6bce4667
HZ		 2093 gfx_v9_0_init_pg(adev);
2094
b1023571
KW		 2095 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2096 /* legacy rlc firmware loading */
2097 r = gfx_v9_0_rlc_load_microcode(adev);
2098 if (r)
2099 return r;
2100 }
2101
e8835e0e
HZ		 2102 if (adev->asic_type == CHIP_RAVEN) {
2103 if (amdgpu_lbpw != 0)
2104 gfx_v9_0_enable_lbpw(adev, true);
2105 else
2106 gfx_v9_0_enable_lbpw(adev, false);
2107 }
2108
b1023571
KW		 2109 gfx_v9_0_rlc_start(adev);
2110
2111 return 0;
2112}
2113
2114static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2115{
2116 int i;
5e78835a 2117 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 2118
ea64468e
TSD		 2119 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2120 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2121 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2122 if (!enable) {
b1023571
KW		 2123 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2124 adev->gfx.gfx_ring[i].ready = false;
2125 }
5e78835a 2126 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 2127 udelay(50);
2128}
2129
2130static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2131{
2132 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2133 const struct gfx_firmware_header_v1_0 *ce_hdr;
2134 const struct gfx_firmware_header_v1_0 *me_hdr;
2135 const __le32 *fw_data;
2136 unsigned i, fw_size;
2137
2138 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2139 return -EINVAL;
2140
2141 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2142 adev->gfx.pfp_fw->data;
2143 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2144 adev->gfx.ce_fw->data;
2145 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2146 adev->gfx.me_fw->data;
2147
2148 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2149 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2150 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2151
2152 gfx_v9_0_cp_gfx_enable(adev, false);
2153
2154 /* PFP */
2155 fw_data = (const __le32 *)
2156 (adev->gfx.pfp_fw->data +
2157 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2158 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 2159 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 2160 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2161 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2162 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 2163
2164 /* CE */
2165 fw_data = (const __le32 *)
2166 (adev->gfx.ce_fw->data +
2167 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2168 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 2169 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 2170 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2171 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2172 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 2173
2174 /* ME */
2175 fw_data = (const __le32 *)
2176 (adev->gfx.me_fw->data +
2177 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2178 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 2179 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 2180 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2181 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2182 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 2183
2184 return 0;
2185}
2186
b1023571
KW		 2187static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2188{
2189 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2190 const struct cs_section_def *sect = NULL;
2191 const struct cs_extent_def *ext = NULL;
d5de797f 2192 int r, i, tmp;
b1023571
KW		 2193
2194 /* init the CP */
5e78835a
TSD		 2195 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2196 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 2197
2198 gfx_v9_0_cp_gfx_enable(adev, true);
2199
d5de797f 2200 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
b1023571
KW		 2201 if (r) {
2202 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2203 return r;
2204 }
2205
2206 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2207 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2208
2209 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2210 amdgpu_ring_write(ring, 0x80000000);
2211 amdgpu_ring_write(ring, 0x80000000);
2212
2213 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2214 for (ext = sect->section; ext->extent != NULL; ++ext) {
2215 if (sect->id == SECT_CONTEXT) {
2216 amdgpu_ring_write(ring,
2217 PACKET3(PACKET3_SET_CONTEXT_REG,
2218 ext->reg_count));
2219 amdgpu_ring_write(ring,
2220 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2221 for (i = 0; i < ext->reg_count; i++)
2222 amdgpu_ring_write(ring, ext->extent[i]);
2223 }
2224 }
2225 }
2226
2227 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2228 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2229
2230 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2231 amdgpu_ring_write(ring, 0);
2232
2233 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2234 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2235 amdgpu_ring_write(ring, 0x8000);
2236 amdgpu_ring_write(ring, 0x8000);
2237
d5de797f
KW		 2238 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2239 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2240 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2241 amdgpu_ring_write(ring, tmp);
2242 amdgpu_ring_write(ring, 0);
2243
b1023571
KW		 2244 amdgpu_ring_commit(ring);
2245
2246 return 0;
2247}
2248
2249static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2250{
2251 struct amdgpu_ring *ring;
2252 u32 tmp;
2253 u32 rb_bufsz;
3fc08b61 2254 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 2255
2256 /* Set the write pointer delay */
5e78835a 2257 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 2258
2259 /* set the RB to use vmid 0 */
5e78835a 2260 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 2261
2262 /* Set ring buffer size */
2263 ring = &adev->gfx.gfx_ring[0];
2264 rb_bufsz = order_base_2(ring->ring_size / 8);
2265 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2266 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2267#ifdef __BIG_ENDIAN
2268 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2269#endif
5e78835a 2270 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2271
2272 /* Initialize the ring buffer's write pointers */
2273 ring->wptr = 0;
5e78835a
TSD		 2274 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2275 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2276
2277 /* set the wb address wether it's enabled or not */
2278 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 2279 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2280 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 2281
3fc08b61 2282 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 2283 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2284 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 2285
b1023571 2286 mdelay(1);
5e78835a 2287 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2288
2289 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 2290 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2291 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 2292
5e78835a 2293 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 2294 if (ring->use_doorbell) {
2295 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2296 DOORBELL_OFFSET, ring->doorbell_index);
2297 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2298 DOORBELL_EN, 1);
2299 } else {
2300 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2301 }
5e78835a 2302 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 2303
2304 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2305 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 2306 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 2307
5e78835a 2308 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 2309 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2310
2311
2312 /* start the ring */
2313 gfx_v9_0_cp_gfx_start(adev);
2314 ring->ready = true;
2315
2316 return 0;
2317}
2318
2319static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2320{
2321 int i;
2322
2323 if (enable) {
5e78835a 2324 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 2325 } else {
5e78835a 2326 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 2327 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2328 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2329 adev->gfx.compute_ring[i].ready = false;
ac104e99 2330 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 2331 }
2332 udelay(50);
2333}
2334
b1023571
KW		 2335static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2336{
2337 const struct gfx_firmware_header_v1_0 *mec_hdr;
2338 const __le32 *fw_data;
2339 unsigned i;
2340 u32 tmp;
2341
2342 if (!adev->gfx.mec_fw)
2343 return -EINVAL;
2344
2345 gfx_v9_0_cp_compute_enable(adev, false);
2346
2347 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2348 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2349
2350 fw_data = (const __le32 *)
2351 (adev->gfx.mec_fw->data +
2352 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2353 tmp = 0;
2354 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2355 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 2356 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 2357
5e78835a 2358 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 2359 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 2360 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571 2361 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
eaa05d52 2362
b1023571 2363 /* MEC1 */
5e78835a 2364 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2365 mec_hdr->jt_offset);
2366 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 2367 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 2368 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2369
5e78835a 2370 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2371 adev->gfx.mec_fw_version);
2372 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2373
2374 return 0;
2375}
2376
464826d6
XY		 2377/* KIQ functions */
2378static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
b1023571 2379{
464826d6
XY		 2380 uint32_t tmp;
2381 struct amdgpu_device *adev = ring->adev;
b1023571 2382
464826d6 2383 /* tell RLC which is KIQ queue */
5e78835a 2384 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 2385 tmp &= 0xffffff00;
2386 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 2387 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2388 tmp |= 0x80;
5e78835a 2389 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2390}
b1023571 2391
0f1dfd52 2392static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
464826d6 2393{
bd3402ea 2394 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2fdde9fa 2395 uint32_t scratch, tmp = 0;
de65513a 2396 uint64_t queue_mask = 0;
2fdde9fa 2397 int r, i;
b1023571 2398
de65513a
AR		 2399 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2400 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2401 continue;
b1023571 2402
de65513a
AR		 2403 /* This situation may be hit in the future if a new HW
2404 * generation exposes more than 64 queues. If so, the
2405 * definition of queue_mask needs updating */
1d11ee89 2406 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
de65513a
AR		 2407 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2408 break;
b1023571 2409 }
b1023571 2410
de65513a
AR		 2411 queue_mask |= (1ull << i);
2412 }
b1023571 2413
2fdde9fa
AD		 2414 r = amdgpu_gfx_scratch_get(adev, &scratch);
2415 if (r) {
2416 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2417 return r;
b1023571 2418 }
2fdde9fa 2419 WREG32(scratch, 0xCAFEDEAD);
b1023571 2420
0f1dfd52 2421 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2fdde9fa
AD		 2422 if (r) {
2423 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2424 amdgpu_gfx_scratch_free(adev, scratch);
b1023571 2425 return r;
2fdde9fa 2426 }
b1023571 2427
0f1dfd52
AD		 2428 /* set resources */
2429 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2430 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2431 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
de65513a
AR		 2432 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2433 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
0f1dfd52
AD		 2434 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2435 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2436 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2437 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
bd3402ea
AD		 2438 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2439 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2440 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2441 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2442
2443 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2444 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2445 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2446 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2447 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2448 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2449 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2450 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2451 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2452 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2453 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2454 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2455 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2456 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2457 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2458 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2459 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2460 }
2fdde9fa
AD		 2461 /* write to scratch for completion */
2462 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2463 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2464 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
464826d6 2465 amdgpu_ring_commit(kiq_ring);
b1023571 2466
2fdde9fa
AD		 2467 for (i = 0; i < adev->usec_timeout; i++) {
2468 tmp = RREG32(scratch);
2469 if (tmp == 0xDEADBEEF)
2470 break;
2471 DRM_UDELAY(1);
2472 }
2473 if (i >= adev->usec_timeout) {
2474 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2475 scratch, tmp);
2476 r = -EINVAL;
2477 }
2478 amdgpu_gfx_scratch_free(adev, scratch);
464826d6 2479
2fdde9fa 2480 return r;
464826d6
XY		 2481}
2482
e322edc3 2483static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 2484{
33fb8698 2485 struct amdgpu_device *adev = ring->adev;
e322edc3 2486 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2487 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2488 uint32_t tmp;
2489
2490 mqd->header = 0xC0310800;
2491 mqd->compute_pipelinestat_enable = 0x00000001;
2492 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2493 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2494 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2495 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2496 mqd->compute_misc_reserved = 0x00000003;
2497
ffe6d881
AD		 2498 mqd->dynamic_cu_mask_addr_lo =
2499 lower_32_bits(ring->mqd_gpu_addr
2500 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2501 mqd->dynamic_cu_mask_addr_hi =
2502 upper_32_bits(ring->mqd_gpu_addr
2503 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2504
d72f2f46 2505 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 2506 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2507 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2508
2509 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2510 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6 2511 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
268cb4c7 2512 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
464826d6
XY		 2513
2514 mqd->cp_hqd_eop_control = tmp;
2515
2516 /* enable doorbell? */
5e78835a 2517 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2518
2519 if (ring->use_doorbell) {
2520 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2521 DOORBELL_OFFSET, ring->doorbell_index);
2522 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2523 DOORBELL_EN, 1);
2524 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2525 DOORBELL_SOURCE, 0);
2526 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2527 DOORBELL_HIT, 0);
2528 }
2529 else
2530 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2531 DOORBELL_EN, 0);
2532
2533 mqd->cp_hqd_pq_doorbell_control = tmp;
2534
2535 /* disable the queue if it's active */
2536 ring->wptr = 0;
2537 mqd->cp_hqd_dequeue_request = 0;
2538 mqd->cp_hqd_pq_rptr = 0;
2539 mqd->cp_hqd_pq_wptr_lo = 0;
2540 mqd->cp_hqd_pq_wptr_hi = 0;
2541
2542 /* set the pointer to the MQD */
33fb8698
AD		 2543 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2544 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 2545
2546 /* set MQD vmid to 0 */
5e78835a 2547 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 2548 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2549 mqd->cp_mqd_control = tmp;
2550
2551 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2552 hqd_gpu_addr = ring->gpu_addr >> 8;
2553 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2554 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2555
2556 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2557 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 2558 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2559 (order_base_2(ring->ring_size / 4) - 1));
2560 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2561 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2562#ifdef __BIG_ENDIAN
2563 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2564#endif
2565 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2566 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2567 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2568 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2569 mqd->cp_hqd_pq_control = tmp;
2570
2571 /* set the wb address whether it's enabled or not */
2572 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2573 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2574 mqd->cp_hqd_pq_rptr_report_addr_hi =
2575 upper_32_bits(wb_gpu_addr) & 0xffff;
2576
2577 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2578 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2579 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2580 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2581
2582 tmp = 0;
2583 /* enable the doorbell if requested */
2584 if (ring->use_doorbell) {
5e78835a 2585 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2586 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2587 DOORBELL_OFFSET, ring->doorbell_index);
2588
2589 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2590 DOORBELL_EN, 1);
2591 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2592 DOORBELL_SOURCE, 0);
2593 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2594 DOORBELL_HIT, 0);
2595 }
2596
2597 mqd->cp_hqd_pq_doorbell_control = tmp;
2598
2599 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2600 ring->wptr = 0;
0274a9c5 2601 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 2602
2603 /* set the vmid for the queue */
2604 mqd->cp_hqd_vmid = 0;
2605
0274a9c5 2606 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 2607 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2608 mqd->cp_hqd_persistent_state = tmp;
2609
fca4ce69
AD		 2610 /* set MIN_IB_AVAIL_SIZE */
2611 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2612 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2613 mqd->cp_hqd_ib_control = tmp;
2614
464826d6
XY		 2615 /* activate the queue */
2616 mqd->cp_hqd_active = 1;
2617
2618 return 0;
2619}
2620
e322edc3 2621static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2622{
33fb8698 2623 struct amdgpu_device *adev = ring->adev;
e322edc3 2624 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2625 int j;
2626
2627 /* disable wptr polling */
72edadd5 2628 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2629
5e78835a 2630 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2631 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2632 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2633 mqd->cp_hqd_eop_base_addr_hi);
2634
2635 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2636 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2637 mqd->cp_hqd_eop_control);
2638
2639 /* enable doorbell? */
5e78835a 2640 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2641 mqd->cp_hqd_pq_doorbell_control);
2642
2643 /* disable the queue if it's active */
5e78835a
TSD		 2644 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2645 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2646 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2647 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2648 break;
2649 udelay(1);
2650 }
5e78835a 2651 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2652 mqd->cp_hqd_dequeue_request);
5e78835a 2653 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2654 mqd->cp_hqd_pq_rptr);
5e78835a 2655 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2656 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2657 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2658 mqd->cp_hqd_pq_wptr_hi);
2659 }
2660
2661 /* set the pointer to the MQD */
5e78835a 2662 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2663 mqd->cp_mqd_base_addr_lo);
5e78835a 2664 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2665 mqd->cp_mqd_base_addr_hi);
2666
2667 /* set MQD vmid to 0 */
5e78835a 2668 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2669 mqd->cp_mqd_control);
2670
2671 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2672 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2673 mqd->cp_hqd_pq_base_lo);
5e78835a 2674 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2675 mqd->cp_hqd_pq_base_hi);
2676
2677 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2678 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2679 mqd->cp_hqd_pq_control);
2680
2681 /* set the wb address whether it's enabled or not */
5e78835a 2682 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2683 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2684 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2685 mqd->cp_hqd_pq_rptr_report_addr_hi);
2686
2687 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2688 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2689 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2690 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2691 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2692
2693 /* enable the doorbell if requested */
2694 if (ring->use_doorbell) {
5e78835a 2695 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2696 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2697 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2698 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2699 }
2700
5e78835a 2701 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2702 mqd->cp_hqd_pq_doorbell_control);
2703
2704 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2705 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2706 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2707 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2708 mqd->cp_hqd_pq_wptr_hi);
2709
2710 /* set the vmid for the queue */
5e78835a 2711 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2712
5e78835a 2713 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2714 mqd->cp_hqd_persistent_state);
2715
2716 /* activate the queue */
5e78835a 2717 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2718 mqd->cp_hqd_active);
2719
72edadd5
TSD		 2720 if (ring->use_doorbell)
2721 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2722
2723 return 0;
2724}
2725
e322edc3 2726static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2727{
2728 struct amdgpu_device *adev = ring->adev;
e322edc3 2729 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2730 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2731
898b7893 2732 gfx_v9_0_kiq_setting(ring);
464826d6 2733
ba0c19f5 2734 if (adev->gfx.in_reset) { /* for GPU_RESET case */
464826d6 2735 /* reset MQD to a clean status */
0ef376ca 2736 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2737 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2738
2739 /* reset ring buffer */
2740 ring->wptr = 0;
b98724db 2741 amdgpu_ring_clear_ring(ring);
464826d6 2742
898b7893
AD		 2743 mutex_lock(&adev->srbm_mutex);
2744 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2745 gfx_v9_0_kiq_init_register(ring);
2746 soc15_grbm_select(adev, 0, 0, 0, 0);
2747 mutex_unlock(&adev->srbm_mutex);
464826d6 2748 } else {
ffe6d881
AD		 2749 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2750 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2751 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
ba0c19f5
AD		 2752 mutex_lock(&adev->srbm_mutex);
2753 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2754 gfx_v9_0_mqd_init(ring);
2755 gfx_v9_0_kiq_init_register(ring);
2756 soc15_grbm_select(adev, 0, 0, 0, 0);
2757 mutex_unlock(&adev->srbm_mutex);
2758
2759 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2760 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
464826d6
XY		 2761 }
2762
0f1dfd52 2763 return 0;
898b7893
AD		 2764}
2765
2766static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2767{
2768 struct amdgpu_device *adev = ring->adev;
898b7893
AD		 2769 struct v9_mqd *mqd = ring->mqd_ptr;
2770 int mqd_idx = ring - &adev->gfx.compute_ring[0];
898b7893 2771
e30a5223 2772 if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
ffe6d881
AD		 2773 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2774 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2775 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
464826d6
XY		 2776 mutex_lock(&adev->srbm_mutex);
2777 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2778 gfx_v9_0_mqd_init(ring);
464826d6
XY		 2779 soc15_grbm_select(adev, 0, 0, 0, 0);
2780 mutex_unlock(&adev->srbm_mutex);
2781
898b7893 2782 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2783 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
ba0c19f5 2784 } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
464826d6 2785 /* reset MQD to a clean status */
898b7893 2786 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2787 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2788
2789 /* reset ring buffer */
2790 ring->wptr = 0;
898b7893 2791 amdgpu_ring_clear_ring(ring);
ba0c19f5
AD		 2792 } else {
2793 amdgpu_ring_clear_ring(ring);
464826d6
XY		 2794 }
2795
464826d6
XY		 2796 return 0;
2797}
2798
2799static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2800{
2801 struct amdgpu_ring *ring = NULL;
2802 int r = 0, i;
2803
2804 gfx_v9_0_cp_compute_enable(adev, true);
2805
2806 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2807
2808 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2809 if (unlikely(r != 0))
2810 goto done;
2811
2812 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2813 if (!r) {
e322edc3 2814 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2815 amdgpu_bo_kunmap(ring->mqd_obj);
2816 ring->mqd_ptr = NULL;
464826d6 2817 }
e1d53aa8
AD		 2818 amdgpu_bo_unreserve(ring->mqd_obj);
2819 if (r)
2820 goto done;
464826d6
XY		 2821
2822 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2823 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2824
2825 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2826 if (unlikely(r != 0))
2827 goto done;
2828 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2829 if (!r) {
898b7893 2830 r = gfx_v9_0_kcq_init_queue(ring);
464826d6
XY		 2831 amdgpu_bo_kunmap(ring->mqd_obj);
2832 ring->mqd_ptr = NULL;
464826d6 2833 }
e1d53aa8
AD		 2834 amdgpu_bo_unreserve(ring->mqd_obj);
2835 if (r)
2836 goto done;
464826d6
XY		 2837 }
2838
0f1dfd52 2839 r = gfx_v9_0_kiq_kcq_enable(adev);
e1d53aa8
AD		 2840done:
2841 return r;
464826d6
XY		 2842}
2843
b1023571
KW		 2844static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2845{
bd3402ea 2846 int r, i;
b1023571
KW		 2847 struct amdgpu_ring *ring;
2848
2849 if (!(adev->flags & AMD_IS_APU))
2850 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2851
2852 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2853 /* legacy firmware loading */
2854 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2855 if (r)
2856 return r;
2857
2858 r = gfx_v9_0_cp_compute_load_microcode(adev);
2859 if (r)
2860 return r;
2861 }
2862
2863 r = gfx_v9_0_cp_gfx_resume(adev);
2864 if (r)
2865 return r;
2866
e30a5223 2867 r = gfx_v9_0_kiq_resume(adev);
b1023571
KW		 2868 if (r)
2869 return r;
2870
2871 ring = &adev->gfx.gfx_ring[0];
2872 r = amdgpu_ring_test_ring(ring);
2873 if (r) {
2874 ring->ready = false;
2875 return r;
2876 }
e30a5223
AD		 2877
2878 ring = &adev->gfx.kiq.ring;
2879 ring->ready = true;
2880 r = amdgpu_ring_test_ring(ring);
2881 if (r)
2882 ring->ready = false;
2883
b1023571
KW		 2884 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2885 ring = &adev->gfx.compute_ring[i];
2886
2887 ring->ready = true;
2888 r = amdgpu_ring_test_ring(ring);
2889 if (r)
2890 ring->ready = false;
2891 }
2892
2893 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2894
2895 return 0;
2896}
2897
2898static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2899{
2900 gfx_v9_0_cp_gfx_enable(adev, enable);
2901 gfx_v9_0_cp_compute_enable(adev, enable);
2902}
2903
2904static int gfx_v9_0_hw_init(void *handle)
2905{
2906 int r;
2907 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2908
2909 gfx_v9_0_init_golden_registers(adev);
2910
2911 gfx_v9_0_gpu_init(adev);
2912
2913 r = gfx_v9_0_rlc_resume(adev);
2914 if (r)
2915 return r;
2916
2917 r = gfx_v9_0_cp_resume(adev);
2918 if (r)
2919 return r;
2920
2921 r = gfx_v9_0_ngg_en(adev);
2922 if (r)
2923 return r;
2924
2925 return r;
2926}
2927
2928static int gfx_v9_0_hw_fini(void *handle)
2929{
2930 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2931
2932 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2933 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
464826d6
XY		 2934 if (amdgpu_sriov_vf(adev)) {
2935 pr_debug("For SRIOV client, shouldn't do anything.\n");
2936 return 0;
2937 }
b1023571
KW		 2938 gfx_v9_0_cp_enable(adev, false);
2939 gfx_v9_0_rlc_stop(adev);
b1023571
KW		 2940
2941 return 0;
2942}
2943
2944static int gfx_v9_0_suspend(void *handle)
2945{
2946 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2947
e30a5223 2948 adev->gfx.in_suspend = true;
b1023571
KW		 2949 return gfx_v9_0_hw_fini(adev);
2950}
2951
2952static int gfx_v9_0_resume(void *handle)
2953{
2954 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e30a5223 2955 int r;
b1023571 2956
e30a5223
AD		 2957 r = gfx_v9_0_hw_init(adev);
2958 adev->gfx.in_suspend = false;
2959 return r;
b1023571
KW		 2960}
2961
2962static bool gfx_v9_0_is_idle(void *handle)
2963{
2964 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2965
5e78835a 2966 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 2967 GRBM_STATUS, GUI_ACTIVE))
2968 return false;
2969 else
2970 return true;
2971}
2972
2973static int gfx_v9_0_wait_for_idle(void *handle)
2974{
2975 unsigned i;
2976 u32 tmp;
2977 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2978
2979 for (i = 0; i < adev->usec_timeout; i++) {
2980 /* read MC_STATUS */
5e78835a 2981 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
b1023571
KW		 2982 GRBM_STATUS__GUI_ACTIVE_MASK;
2983
2984 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
2985 return 0;
2986 udelay(1);
2987 }
2988 return -ETIMEDOUT;
2989}
2990
b1023571
KW		 2991static int gfx_v9_0_soft_reset(void *handle)
2992{
2993 u32 grbm_soft_reset = 0;
2994 u32 tmp;
2995 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2996
2997 /* GRBM_STATUS */
5e78835a 2998 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 2999 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3000 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3001 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3002 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3003 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3004 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3005 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3006 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3007 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3008 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3009 }
3010
3011 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3012 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3013 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3014 }
3015
3016 /* GRBM_STATUS2 */
5e78835a 3017 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 3018 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3019 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3020 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3021
3022
75bac5c6 3023 if (grbm_soft_reset) {
b1023571
KW		 3024 /* stop the rlc */
3025 gfx_v9_0_rlc_stop(adev);
3026
3027 /* Disable GFX parsing/prefetching */
3028 gfx_v9_0_cp_gfx_enable(adev, false);
3029
3030 /* Disable MEC parsing/prefetching */
3031 gfx_v9_0_cp_compute_enable(adev, false);
3032
3033 if (grbm_soft_reset) {
5e78835a 3034 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3035 tmp |= grbm_soft_reset;
3036 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 3037 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3038 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3039
3040 udelay(50);
3041
3042 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 3043 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3044 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3045 }
3046
3047 /* Wait a little for things to settle down */
3048 udelay(50);
b1023571
KW		 3049 }
3050 return 0;
3051}
3052
3053static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3054{
3055 uint64_t clock;
3056
3057 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 3058 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3059 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3060 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 3061 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3062 return clock;
3063}
3064
3065static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3066 uint32_t vmid,
3067 uint32_t gds_base, uint32_t gds_size,
3068 uint32_t gws_base, uint32_t gws_size,
3069 uint32_t oa_base, uint32_t oa_size)
3070{
3071 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3072 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3073
3074 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3075 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3076
3077 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3078 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3079
3080 /* GDS Base */
3081 gfx_v9_0_write_data_to_reg(ring, 0, false,
3082 amdgpu_gds_reg_offset[vmid].mem_base,
3083 gds_base);
3084
3085 /* GDS Size */
3086 gfx_v9_0_write_data_to_reg(ring, 0, false,
3087 amdgpu_gds_reg_offset[vmid].mem_size,
3088 gds_size);
3089
3090 /* GWS */
3091 gfx_v9_0_write_data_to_reg(ring, 0, false,
3092 amdgpu_gds_reg_offset[vmid].gws,
3093 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3094
3095 /* OA */
3096 gfx_v9_0_write_data_to_reg(ring, 0, false,
3097 amdgpu_gds_reg_offset[vmid].oa,
3098 (1 << (oa_size + oa_base)) - (1 << oa_base));
3099}
3100
3101static int gfx_v9_0_early_init(void *handle)
3102{
3103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3104
3105 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
78c16834 3106 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
b1023571
KW		 3107 gfx_v9_0_set_ring_funcs(adev);
3108 gfx_v9_0_set_irq_funcs(adev);
3109 gfx_v9_0_set_gds_init(adev);
3110 gfx_v9_0_set_rlc_funcs(adev);
3111
3112 return 0;
3113}
3114
3115static int gfx_v9_0_late_init(void *handle)
3116{
3117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3118 int r;
3119
3120 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3121 if (r)
3122 return r;
3123
3124 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3125 if (r)
3126 return r;
3127
3128 return 0;
3129}
3130
3131static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3132{
3133 uint32_t rlc_setting, data;
3134 unsigned i;
3135
3136 if (adev->gfx.rlc.in_safe_mode)
3137 return;
3138
3139 /* if RLC is not enabled, do nothing */
5e78835a 3140 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3141 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3142 return;
3143
3144 if (adev->cg_flags &
3145 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3146 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3147 data = RLC_SAFE_MODE__CMD_MASK;
3148 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 3149 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3150
3151 /* wait for RLC_SAFE_MODE */
3152 for (i = 0; i < adev->usec_timeout; i++) {
3153 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3154 break;
3155 udelay(1);
3156 }
3157 adev->gfx.rlc.in_safe_mode = true;
3158 }
3159}
3160
3161static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3162{
3163 uint32_t rlc_setting, data;
3164
3165 if (!adev->gfx.rlc.in_safe_mode)
3166 return;
3167
3168 /* if RLC is not enabled, do nothing */
5e78835a 3169 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3170 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3171 return;
3172
3173 if (adev->cg_flags &
3174 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3175 /*
3176 * Try to exit safe mode only if it is already in safe
3177 * mode.
3178 */
3179 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 3180 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3181 adev->gfx.rlc.in_safe_mode = false;
3182 }
3183}
3184
197f95c8
HZ		 3185static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3186 bool enable)
3187{
3188 /* TODO: double check if we need to perform under safe mdoe */
3189 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3190
3191 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3192 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3193 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3194 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3195 } else {
3196 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3197 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3198 }
3199
3200 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3201}
3202
18924c71
HZ		 3203static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3204 bool enable)
3205{
3206 /* TODO: double check if we need to perform under safe mode */
3207 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3208
3209 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3210 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3211 else
3212 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3213
3214 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3215 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3216 else
3217 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3218
3219 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3220}
3221
b1023571
KW		 3222static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3223 bool enable)
3224{
3225 uint32_t data, def;
3226
3227 /* It is disabled by HW by default */
3228 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3229 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 3230 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3231 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3232 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3233 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3234 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3235
3236 /* only for Vega10 & Raven1 */
3237 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3238
3239 if (def != data)
5e78835a 3240 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3241
3242 /* MGLS is a global flag to control all MGLS in GFX */
3243 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3244 /* 2 - RLC memory Light sleep */
3245 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 3246 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3247 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3248 if (def != data)
5e78835a 3249 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3250 }
3251 /* 3 - CP memory Light sleep */
3252 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 3253 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3254 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3255 if (def != data)
5e78835a 3256 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3257 }
3258 }
3259 } else {
3260 /* 1 - MGCG_OVERRIDE */
5e78835a 3261 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3262 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3263 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3264 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3265 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3266 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3267 if (def != data)
5e78835a 3268 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3269
3270 /* 2 - disable MGLS in RLC */
5e78835a 3271 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3272 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3273 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 3274 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3275 }
3276
3277 /* 3 - disable MGLS in CP */
5e78835a 3278 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3279 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3280 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 3281 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3282 }
3283 }
3284}
3285
3286static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3287 bool enable)
3288{
3289 uint32_t data, def;
3290
3291 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3292
3293 /* Enable 3D CGCG/CGLS */
3294 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3295 /* write cmd to clear cgcg/cgls ov */
5e78835a 3296 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3297 /* unset CGCG override */
3298 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3299 /* update CGCG and CGLS override bits */
3300 if (def != data)
5e78835a 3301 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 3302 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 3303 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3304 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3305 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3306 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3307 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3308 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3309 if (def != data)
5e78835a 3310 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3311
3312 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3313 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3314 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3315 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3316 if (def != data)
5e78835a 3317 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 3318 } else {
3319 /* Disable CGCG/CGLS */
5e78835a 3320 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3321 /* disable cgcg, cgls should be disabled */
3322 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3323 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3324 /* disable cgcg and cgls in FSM */
3325 if (def != data)
5e78835a 3326 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3327 }
3328
3329 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3330}
3331
3332static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3333 bool enable)
3334{
3335 uint32_t def, data;
3336
3337 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3338
3339 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 3340 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3341 /* unset CGCG override */
3342 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3343 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3344 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3345 else
3346 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3347 /* update CGCG and CGLS override bits */
3348 if (def != data)
5e78835a 3349 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3350
3351 /* enable cgcg FSM(0x0020003F) */
5e78835a 3352 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3353 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3354 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3355 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3356 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3357 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3358 if (def != data)
5e78835a 3359 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3360
3361 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3362 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3363 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3364 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3365 if (def != data)
5e78835a 3366 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 3367 } else {
5e78835a 3368 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3369 /* reset CGCG/CGLS bits */
3370 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3371 /* disable cgcg and cgls in FSM */
3372 if (def != data)
5e78835a 3373 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3374 }
3375
3376 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3377}
3378
3379static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3380 bool enable)
3381{
3382 if (enable) {
3383 /* CGCG/CGLS should be enabled after MGCG/MGLS
3384 * === MGCG + MGLS ===
3385 */
3386 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3387 /* === CGCG /CGLS for GFX 3D Only === */
3388 gfx_v9_0_update_3d_clock_gating(adev, enable);
3389 /* === CGCG + CGLS === */
3390 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3391 } else {
3392 /* CGCG/CGLS should be disabled before MGCG/MGLS
3393 * === CGCG + CGLS ===
3394 */
3395 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3396 /* === CGCG /CGLS for GFX 3D Only === */
3397 gfx_v9_0_update_3d_clock_gating(adev, enable);
3398 /* === MGCG + MGLS === */
3399 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3400 }
3401 return 0;
3402}
3403
3404static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3405 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3406 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3407};
3408
3409static int gfx_v9_0_set_powergating_state(void *handle,
3410 enum amd_powergating_state state)
3411{
5897c99e 3412 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197f95c8 3413 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
5897c99e
HZ		 3414
3415 switch (adev->asic_type) {
3416 case CHIP_RAVEN:
3417 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3418 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3419 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3420 } else {
3421 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3422 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3423 }
3424
3425 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3426 gfx_v9_0_enable_cp_power_gating(adev, true);
3427 else
3428 gfx_v9_0_enable_cp_power_gating(adev, false);
197f95c8
HZ		 3429
3430 /* update gfx cgpg state */
3431 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
18924c71
HZ		 3432
3433 /* update mgcg state */
3434 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5897c99e
HZ		 3435 break;
3436 default:
3437 break;
3438 }
3439
b1023571
KW		 3440 return 0;
3441}
3442
3443static int gfx_v9_0_set_clockgating_state(void *handle,
3444 enum amd_clockgating_state state)
3445{
3446 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3447
fb82afab
XY		 3448 if (amdgpu_sriov_vf(adev))
3449 return 0;
3450
b1023571
KW		 3451 switch (adev->asic_type) {
3452 case CHIP_VEGA10:
a4dc61f5 3453 case CHIP_RAVEN:
b1023571
KW		 3454 gfx_v9_0_update_gfx_clock_gating(adev,
3455 state == AMD_CG_STATE_GATE ? true : false);
3456 break;
3457 default:
3458 break;
3459 }
3460 return 0;
3461}
3462
12ad27fa
HR		 3463static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3464{
3465 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3466 int data;
3467
3468 if (amdgpu_sriov_vf(adev))
3469 *flags = 0;
3470
3471 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 3472 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 3473 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3474 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3475
3476 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 3477 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 3478 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3479 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3480
3481 /* AMD_CG_SUPPORT_GFX_CGLS */
3482 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3483 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3484
3485 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 3486 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 3487 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3488 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3489
3490 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 3491 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 3492 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3493 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3494
3495 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 3496 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 3497 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3498 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3499
3500 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3501 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3502 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3503}
3504
b1023571
KW		 3505static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3506{
3507 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3508}
3509
3510static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3511{
3512 struct amdgpu_device *adev = ring->adev;
3513 u64 wptr;
3514
3515 /* XXX check if swapping is necessary on BE */
3516 if (ring->use_doorbell) {
3517 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3518 } else {
5e78835a
TSD		 3519 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3520 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 3521 }
3522
3523 return wptr;
3524}
3525
3526static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3527{
3528 struct amdgpu_device *adev = ring->adev;
3529
3530 if (ring->use_doorbell) {
3531 /* XXX check if swapping is necessary on BE */
3532 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3533 WDOORBELL64(ring->doorbell_index, ring->wptr);
3534 } else {
5e78835a
TSD		 3535 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3536 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 3537 }
3538}
3539
3540static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3541{
3542 u32 ref_and_mask, reg_mem_engine;
3543 struct nbio_hdp_flush_reg *nbio_hf_reg;
3544
3545 if (ring->adev->asic_type == CHIP_VEGA10)
3546 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3547
3548 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3549 switch (ring->me) {
3550 case 1:
3551 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3552 break;
3553 case 2:
3554 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3555 break;
3556 default:
3557 return;
3558 }
3559 reg_mem_engine = 0;
3560 } else {
3561 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3562 reg_mem_engine = 1; /* pfp */
3563 }
3564
3565 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3566 nbio_hf_reg->hdp_flush_req_offset,
3567 nbio_hf_reg->hdp_flush_done_offset,
3568 ref_and_mask, ref_and_mask, 0x20);
3569}
3570
3571static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3572{
3573 gfx_v9_0_write_data_to_reg(ring, 0, true,
3574 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3575}
3576
3577static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3578 struct amdgpu_ib *ib,
3579 unsigned vm_id, bool ctx_switch)
3580{
eaa05d52 3581 u32 header, control = 0;
b1023571 3582
eaa05d52
ML		 3583 if (ib->flags & AMDGPU_IB_FLAG_CE)
3584 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3585 else
3586 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
b1023571 3587
eaa05d52 3588 control |= ib->length_dw | (vm_id << 24);
b1023571 3589
635e7132 3590 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
eaa05d52 3591 control |= INDIRECT_BUFFER_PRE_ENB(1);
9ccd52eb 3592
635e7132
ML		 3593 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3594 gfx_v9_0_ring_emit_de_meta(ring);
3595 }
3596
eaa05d52
ML		 3597 amdgpu_ring_write(ring, header);
3598BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3599 amdgpu_ring_write(ring,
b1023571 3600#ifdef __BIG_ENDIAN
eaa05d52 3601 (2 << 0) |
b1023571 3602#endif
eaa05d52
ML		 3603 lower_32_bits(ib->gpu_addr));
3604 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3605 amdgpu_ring_write(ring, control);
b1023571
KW		 3606}
3607
b1023571
KW		 3608static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3609 struct amdgpu_ib *ib,
3610 unsigned vm_id, bool ctx_switch)
3611{
3612 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3613
3614 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3615 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3616 amdgpu_ring_write(ring,
3617#ifdef __BIG_ENDIAN
3618 (2 << 0) |
3619#endif
3620 lower_32_bits(ib->gpu_addr));
3621 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3622 amdgpu_ring_write(ring, control);
3623}
3624
3625static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3626 u64 seq, unsigned flags)
3627{
3628 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3629 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3630
3631 /* RELEASE_MEM - flush caches, send int */
3632 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3633 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3634 EOP_TC_ACTION_EN |
3635 EOP_TC_WB_ACTION_EN |
3636 EOP_TC_MD_ACTION_EN |
3637 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3638 EVENT_INDEX(5)));
3639 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3640
3641 /*
3642 * the address should be Qword aligned if 64bit write, Dword
3643 * aligned if only send 32bit data low (discard data high)
3644 */
3645 if (write64bit)
3646 BUG_ON(addr & 0x7);
3647 else
3648 BUG_ON(addr & 0x3);
3649 amdgpu_ring_write(ring, lower_32_bits(addr));
3650 amdgpu_ring_write(ring, upper_32_bits(addr));
3651 amdgpu_ring_write(ring, lower_32_bits(seq));
3652 amdgpu_ring_write(ring, upper_32_bits(seq));
3653 amdgpu_ring_write(ring, 0);
3654}
3655
3656static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3657{
3658 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3659 uint32_t seq = ring->fence_drv.sync_seq;
3660 uint64_t addr = ring->fence_drv.gpu_addr;
3661
3662 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3663 lower_32_bits(addr), upper_32_bits(addr),
3664 seq, 0xffffffff, 4);
3665}
3666
3667static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3668 unsigned vm_id, uint64_t pd_addr)
3669{
2e819849 3670 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
b1023571 3671 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 3672 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 3673 unsigned eng = ring->vm_inv_eng;
b1023571 3674
b1166325
CK		 3675 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3676 pd_addr |= AMDGPU_PTE_VALID;
b1023571 3677
2e819849
CK		 3678 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3679 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3680 lower_32_bits(pd_addr));
b1023571 3681
2e819849
CK		 3682 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3683 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3684 upper_32_bits(pd_addr));
b1023571 3685
2e819849
CK		 3686 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3687 hub->vm_inv_eng0_req + eng, req);
b1023571 3688
2e819849
CK		 3689 /* wait for the invalidate to complete */
3690 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3691 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
b1023571
KW		 3692
3693 /* compute doesn't have PFP */
3694 if (usepfp) {
3695 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3696 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3697 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3698 }
3699}
3700
3701static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3702{
3703 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3704}
3705
3706static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3707{
3708 u64 wptr;
3709
3710 /* XXX check if swapping is necessary on BE */
3711 if (ring->use_doorbell)
3712 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3713 else
3714 BUG();
3715 return wptr;
3716}
3717
3718static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3719{
3720 struct amdgpu_device *adev = ring->adev;
3721
3722 /* XXX check if swapping is necessary on BE */
3723 if (ring->use_doorbell) {
3724 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3725 WDOORBELL64(ring->doorbell_index, ring->wptr);
3726 } else{
3727 BUG(); /* only DOORBELL method supported on gfx9 now */
3728 }
3729}
3730
aa6faa44
XY		 3731static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3732 u64 seq, unsigned int flags)
3733{
3734 /* we only allocate 32bit for each seq wb address */
3735 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3736
3737 /* write fence seq to the "addr" */
3738 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3739 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3740 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3741 amdgpu_ring_write(ring, lower_32_bits(addr));
3742 amdgpu_ring_write(ring, upper_32_bits(addr));
3743 amdgpu_ring_write(ring, lower_32_bits(seq));
3744
3745 if (flags & AMDGPU_FENCE_FLAG_INT) {
3746 /* set register to trigger INT */
3747 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3748 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3749 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3750 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3751 amdgpu_ring_write(ring, 0);
3752 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3753 }
3754}
3755
b1023571
KW		 3756static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3757{
3758 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3759 amdgpu_ring_write(ring, 0);
3760}
3761
cca02cd3
XY		 3762static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3763{
3764 static struct v9_ce_ib_state ce_payload = {0};
3765 uint64_t csa_addr;
3766 int cnt;
3767
3768 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3769 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3770
3771 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3772 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3773 WRITE_DATA_DST_SEL(8) |
3774 WR_CONFIRM) |
3775 WRITE_DATA_CACHE_POLICY(0));
3776 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3777 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3778 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3779}
3780
3781static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3782{
3783 static struct v9_de_ib_state de_payload = {0};
3784 uint64_t csa_addr, gds_addr;
3785 int cnt;
3786
3787 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3788 gds_addr = csa_addr + 4096;
3789 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3790 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3791
3792 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3793 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3794 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3795 WRITE_DATA_DST_SEL(8) |
3796 WR_CONFIRM) |
3797 WRITE_DATA_CACHE_POLICY(0));
3798 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3799 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3800 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3801}
3802
b1023571
KW		 3803static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3804{
3805 uint32_t dw2 = 0;
3806
cca02cd3
XY		 3807 if (amdgpu_sriov_vf(ring->adev))
3808 gfx_v9_0_ring_emit_ce_meta(ring);
3809
b1023571
KW		 3810 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3811 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3812 /* set load_global_config & load_global_uconfig */
3813 dw2 |= 0x8001;
3814 /* set load_cs_sh_regs */
3815 dw2 |= 0x01000000;
3816 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3817 dw2 |= 0x10002;
3818
3819 /* set load_ce_ram if preamble presented */
3820 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3821 dw2 |= 0x10000000;
3822 } else {
3823 /* still load_ce_ram if this is the first time preamble presented
3824 * although there is no context switch happens.
3825 */
3826 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3827 dw2 |= 0x10000000;
3828 }
3829
3830 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3831 amdgpu_ring_write(ring, dw2);
3832 amdgpu_ring_write(ring, 0);
3833}
3834
9a5e02b5
ML		 3835static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3836{
3837 unsigned ret;
3838 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3839 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3840 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3841 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3842 ret = ring->wptr & ring->buf_mask;
3843 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3844 return ret;
3845}
3846
3847static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3848{
3849 unsigned cur;
3850 BUG_ON(offset > ring->buf_mask);
3851 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3852
3853 cur = (ring->wptr & ring->buf_mask) - 1;
3854 if (likely(cur > offset))
3855 ring->ring[offset] = cur - offset;
3856 else
3857 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3858}
3859
3b4d68e9
ML		 3860static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3861{
3862 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3863 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3864}
3865
aa6faa44
XY		 3866static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3867{
3868 struct amdgpu_device *adev = ring->adev;
3869
3870 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3871 amdgpu_ring_write(ring, 0 | /* src: register*/
3872 (5 << 8) | /* dst: memory */
3873 (1 << 20)); /* write confirm */
3874 amdgpu_ring_write(ring, reg);
3875 amdgpu_ring_write(ring, 0);
3876 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3877 adev->virt.reg_val_offs * 4));
3878 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3879 adev->virt.reg_val_offs * 4));
3880}
3881
3882static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3883 uint32_t val)
3884{
3885 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3886 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3887 amdgpu_ring_write(ring, reg);
3888 amdgpu_ring_write(ring, 0);
3889 amdgpu_ring_write(ring, val);
3890}
3891
b1023571
KW		 3892static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3893 enum amdgpu_interrupt_state state)
3894{
b1023571
KW		 3895 switch (state) {
3896 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3897 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 3898 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3899 TIME_STAMP_INT_ENABLE,
3900 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3901 break;
3902 default:
3903 break;
3904 }
3905}
3906
3907static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3908 int me, int pipe,
3909 enum amdgpu_interrupt_state state)
3910{
3911 u32 mec_int_cntl, mec_int_cntl_reg;
3912
3913 /*
d0c55cdf
AD		 3914 * amdgpu controls only the first MEC. That's why this function only
3915 * handles the setting of interrupts for this specific MEC. All other
b1023571
KW		 3916 * pipes' interrupts are set by amdkfd.
3917 */
3918
3919 if (me == 1) {
3920 switch (pipe) {
3921 case 0:
3922 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3923 break;
d0c55cdf
AD		 3924 case 1:
3925 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
3926 break;
3927 case 2:
3928 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
3929 break;
3930 case 3:
3931 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
3932 break;
b1023571
KW		 3933 default:
3934 DRM_DEBUG("invalid pipe %d\n", pipe);
3935 return;
3936 }
3937 } else {
3938 DRM_DEBUG("invalid me %d\n", me);
3939 return;
3940 }
3941
3942 switch (state) {
3943 case AMDGPU_IRQ_STATE_DISABLE:
3944 mec_int_cntl = RREG32(mec_int_cntl_reg);
3945 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3946 TIME_STAMP_INT_ENABLE, 0);
3947 WREG32(mec_int_cntl_reg, mec_int_cntl);
3948 break;
3949 case AMDGPU_IRQ_STATE_ENABLE:
3950 mec_int_cntl = RREG32(mec_int_cntl_reg);
3951 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3952 TIME_STAMP_INT_ENABLE, 1);
3953 WREG32(mec_int_cntl_reg, mec_int_cntl);
3954 break;
3955 default:
3956 break;
3957 }
3958}
3959
3960static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3961 struct amdgpu_irq_src *source,
3962 unsigned type,
3963 enum amdgpu_interrupt_state state)
3964{
b1023571
KW		 3965 switch (state) {
3966 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3967 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 3968 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3969 PRIV_REG_INT_ENABLE,
3970 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3971 break;
3972 default:
3973 break;
3974 }
3975
3976 return 0;
3977}
3978
3979static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3980 struct amdgpu_irq_src *source,
3981 unsigned type,
3982 enum amdgpu_interrupt_state state)
3983{
b1023571
KW		 3984 switch (state) {
3985 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3986 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 3987 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3988 PRIV_INSTR_INT_ENABLE,
3989 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3990 default:
3991 break;
3992 }
3993
3994 return 0;
3995}
3996
3997static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3998 struct amdgpu_irq_src *src,
3999 unsigned type,
4000 enum amdgpu_interrupt_state state)
4001{
4002 switch (type) {
4003 case AMDGPU_CP_IRQ_GFX_EOP:
4004 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4005 break;
4006 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4007 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4008 break;
4009 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4010 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4011 break;
4012 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4013 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4014 break;
4015 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4016 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4017 break;
4018 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4019 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4020 break;
4021 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4022 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4023 break;
4024 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4025 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4026 break;
4027 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4028 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4029 break;
4030 default:
4031 break;
4032 }
4033 return 0;
4034}
4035
4036static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4037 struct amdgpu_irq_src *source,
4038 struct amdgpu_iv_entry *entry)
4039{
4040 int i;
4041 u8 me_id, pipe_id, queue_id;
4042 struct amdgpu_ring *ring;
4043
4044 DRM_DEBUG("IH: CP EOP\n");
4045 me_id = (entry->ring_id & 0x0c) >> 2;
4046 pipe_id = (entry->ring_id & 0x03) >> 0;
4047 queue_id = (entry->ring_id & 0x70) >> 4;
4048
4049 switch (me_id) {
4050 case 0:
4051 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4052 break;
4053 case 1:
4054 case 2:
4055 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4056 ring = &adev->gfx.compute_ring[i];
4057 /* Per-queue interrupt is supported for MEC starting from VI.
4058 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4059 */
4060 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4061 amdgpu_fence_process(ring);
4062 }
4063 break;
4064 }
4065 return 0;
4066}
4067
4068static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4069 struct amdgpu_irq_src *source,
4070 struct amdgpu_iv_entry *entry)
4071{
4072 DRM_ERROR("Illegal register access in command stream\n");
4073 schedule_work(&adev->reset_work);
4074 return 0;
4075}
4076
4077static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4078 struct amdgpu_irq_src *source,
4079 struct amdgpu_iv_entry *entry)
4080{
4081 DRM_ERROR("Illegal instruction in command stream\n");
4082 schedule_work(&adev->reset_work);
4083 return 0;
4084}
4085
97031e25
XY		 4086static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4087 struct amdgpu_irq_src *src,
4088 unsigned int type,
4089 enum amdgpu_interrupt_state state)
4090{
4091 uint32_t tmp, target;
1c4ecf48 4092 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4093
4094 if (ring->me == 1)
4095 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4096 else
4097 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4098 target += ring->pipe;
4099
4100 switch (type) {
4101 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4102 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 4103 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4104 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4105 GENERIC2_INT_ENABLE, 0);
5e78835a 4106 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4107
4108 tmp = RREG32(target);
4109 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4110 GENERIC2_INT_ENABLE, 0);
4111 WREG32(target, tmp);
4112 } else {
5e78835a 4113 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4114 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4115 GENERIC2_INT_ENABLE, 1);
5e78835a 4116 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4117
4118 tmp = RREG32(target);
4119 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4120 GENERIC2_INT_ENABLE, 1);
4121 WREG32(target, tmp);
4122 }
4123 break;
4124 default:
4125 BUG(); /* kiq only support GENERIC2_INT now */
4126 break;
4127 }
4128 return 0;
4129}
4130
4131static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4132 struct amdgpu_irq_src *source,
4133 struct amdgpu_iv_entry *entry)
4134{
4135 u8 me_id, pipe_id, queue_id;
1c4ecf48 4136 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4137
4138 me_id = (entry->ring_id & 0x0c) >> 2;
4139 pipe_id = (entry->ring_id & 0x03) >> 0;
4140 queue_id = (entry->ring_id & 0x70) >> 4;
4141 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4142 me_id, pipe_id, queue_id);
4143
4144 amdgpu_fence_process(ring);
4145 return 0;
4146}
4147
fa04b6ba 4148static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
b1023571
KW		 4149 .name = "gfx_v9_0",
4150 .early_init = gfx_v9_0_early_init,
4151 .late_init = gfx_v9_0_late_init,
4152 .sw_init = gfx_v9_0_sw_init,
4153 .sw_fini = gfx_v9_0_sw_fini,
4154 .hw_init = gfx_v9_0_hw_init,
4155 .hw_fini = gfx_v9_0_hw_fini,
4156 .suspend = gfx_v9_0_suspend,
4157 .resume = gfx_v9_0_resume,
4158 .is_idle = gfx_v9_0_is_idle,
4159 .wait_for_idle = gfx_v9_0_wait_for_idle,
4160 .soft_reset = gfx_v9_0_soft_reset,
4161 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4162 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 4163 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 4164};
4165
4166static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4167 .type = AMDGPU_RING_TYPE_GFX,
4168 .align_mask = 0xff,
4169 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4170 .support_64bit_ptrs = true,
0eeb68b3 4171 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4172 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4173 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4174 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 4175 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4176 5 + /* COND_EXEC */
4177 7 + /* PIPELINE_SYNC */
2e819849 4178 24 + /* VM_FLUSH */
e9d672b2
ML		 4179 8 + /* FENCE for VM_FLUSH */
4180 20 + /* GDS switch */
4181 4 + /* double SWITCH_BUFFER,
4182 the first COND_EXEC jump to the place just
4183 prior to this double SWITCH_BUFFER */
4184 5 + /* COND_EXEC */
4185 7 + /* HDP_flush */
4186 4 + /* VGT_flush */
4187 14 + /* CE_META */
4188 31 + /* DE_META */
4189 3 + /* CNTX_CTRL */
4190 5 + /* HDP_INVL */
4191 8 + 8 + /* FENCE x2 */
4192 2, /* SWITCH_BUFFER */
b1023571
KW		 4193 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4194 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4195 .emit_fence = gfx_v9_0_ring_emit_fence,
4196 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4197 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4198 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4199 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4200 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4201 .test_ring = gfx_v9_0_ring_test_ring,
4202 .test_ib = gfx_v9_0_ring_test_ib,
4203 .insert_nop = amdgpu_ring_insert_nop,
4204 .pad_ib = amdgpu_ring_generic_pad_ib,
4205 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4206 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 4207 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4208 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3b4d68e9 4209 .emit_tmz = gfx_v9_0_ring_emit_tmz,
b1023571
KW		 4210};
4211
4212static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4213 .type = AMDGPU_RING_TYPE_COMPUTE,
4214 .align_mask = 0xff,
4215 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4216 .support_64bit_ptrs = true,
0eeb68b3 4217 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4218 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4219 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4220 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4221 .emit_frame_size =
4222 20 + /* gfx_v9_0_ring_emit_gds_switch */
4223 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4224 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4225 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4226 24 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 4227 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4228 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4229 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4230 .emit_fence = gfx_v9_0_ring_emit_fence,
4231 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4232 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4233 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4234 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4235 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4236 .test_ring = gfx_v9_0_ring_test_ring,
4237 .test_ib = gfx_v9_0_ring_test_ib,
4238 .insert_nop = amdgpu_ring_insert_nop,
4239 .pad_ib = amdgpu_ring_generic_pad_ib,
4240};
4241
aa6faa44
XY		 4242static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4243 .type = AMDGPU_RING_TYPE_KIQ,
4244 .align_mask = 0xff,
4245 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4246 .support_64bit_ptrs = true,
0eeb68b3 4247 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 4248 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4249 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4250 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4251 .emit_frame_size =
4252 20 + /* gfx_v9_0_ring_emit_gds_switch */
4253 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4254 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4255 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4256 24 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 4257 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4258 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4259 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4260 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 4261 .test_ring = gfx_v9_0_ring_test_ring,
4262 .test_ib = gfx_v9_0_ring_test_ib,
4263 .insert_nop = amdgpu_ring_insert_nop,
4264 .pad_ib = amdgpu_ring_generic_pad_ib,
4265 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4266 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4267};
b1023571
KW		 4268
4269static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4270{
4271 int i;
4272
aa6faa44
XY		 4273 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4274
b1023571
KW		 4275 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4276 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4277
4278 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4279 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4280}
4281
97031e25
XY		 4282static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4283 .set = gfx_v9_0_kiq_set_interrupt_state,
4284 .process = gfx_v9_0_kiq_irq,
4285};
4286
b1023571
KW		 4287static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4288 .set = gfx_v9_0_set_eop_interrupt_state,
4289 .process = gfx_v9_0_eop_irq,
4290};
4291
4292static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4293 .set = gfx_v9_0_set_priv_reg_fault_state,
4294 .process = gfx_v9_0_priv_reg_irq,
4295};
4296
4297static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4298 .set = gfx_v9_0_set_priv_inst_fault_state,
4299 .process = gfx_v9_0_priv_inst_irq,
4300};
4301
4302static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4303{
4304 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4305 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4306
4307 adev->gfx.priv_reg_irq.num_types = 1;
4308 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4309
4310 adev->gfx.priv_inst_irq.num_types = 1;
4311 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 4312
4313 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4314 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 4315}
4316
4317static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4318{
4319 switch (adev->asic_type) {
4320 case CHIP_VEGA10:
a4dc61f5 4321 case CHIP_RAVEN:
b1023571
KW		 4322 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4323 break;
4324 default:
4325 break;
4326 }
4327}
4328
4329static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4330{
4331 /* init asci gds info */
5e78835a 4332 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 4333 adev->gds.gws.total_size = 64;
4334 adev->gds.oa.total_size = 16;
4335
4336 if (adev->gds.mem.total_size == 64 * 1024) {
4337 adev->gds.mem.gfx_partition_size = 4096;
4338 adev->gds.mem.cs_partition_size = 4096;
4339
4340 adev->gds.gws.gfx_partition_size = 4;
4341 adev->gds.gws.cs_partition_size = 4;
4342
4343 adev->gds.oa.gfx_partition_size = 4;
4344 adev->gds.oa.cs_partition_size = 1;
4345 } else {
4346 adev->gds.mem.gfx_partition_size = 1024;
4347 adev->gds.mem.cs_partition_size = 1024;
4348
4349 adev->gds.gws.gfx_partition_size = 16;
4350 adev->gds.gws.cs_partition_size = 16;
4351
4352 adev->gds.oa.gfx_partition_size = 4;
4353 adev->gds.oa.cs_partition_size = 4;
4354 }
4355}
4356
c94d38f0
NH		 4357static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4358 u32 bitmap)
4359{
4360 u32 data;
4361
4362 if (!bitmap)
4363 return;
4364
4365 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4366 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4367
4368 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4369}
4370
b1023571
KW		 4371static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4372{
4373 u32 data, mask;
4374
5e78835a
TSD		 4375 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4376 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 4377
4378 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4379 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4380
378506a7 4381 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
b1023571
KW		 4382
4383 return (~data) & mask;
4384}
4385
4386static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4387 struct amdgpu_cu_info *cu_info)
4388{
4389 int i, j, k, counter, active_cu_number = 0;
4390 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
c94d38f0 4391 unsigned disable_masks[4 * 2];
b1023571
KW		 4392
4393 if (!adev || !cu_info)
4394 return -EINVAL;
4395
c94d38f0
NH		 4396 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4397
b1023571
KW		 4398 mutex_lock(&adev->grbm_idx_mutex);
4399 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4400 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4401 mask = 1;
4402 ao_bitmap = 0;
4403 counter = 0;
4404 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
c94d38f0
NH		 4405 if (i < 4 && j < 2)
4406 gfx_v9_0_set_user_cu_inactive_bitmap(
4407 adev, disable_masks[i * 2 + j]);
b1023571
KW		 4408 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4409 cu_info->bitmap[i][j] = bitmap;
4410
fe723cd3 4411 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
b1023571 4412 if (bitmap & mask) {
fe723cd3 4413 if (counter < adev->gfx.config.max_cu_per_sh)
b1023571
KW		 4414 ao_bitmap |= mask;
4415 counter ++;
4416 }
4417 mask <<= 1;
4418 }
4419 active_cu_number += counter;
dbfe85ea
FC		 4420 if (i < 2 && j < 2)
4421 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4422 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
b1023571
KW		 4423 }
4424 }
4425 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4426 mutex_unlock(&adev->grbm_idx_mutex);
4427
4428 cu_info->number = active_cu_number;
4429 cu_info->ao_cu_mask = ao_cu_mask;
4430
4431 return 0;
4432}
4433
b1023571
KW		 4434const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4435{
4436 .type = AMD_IP_BLOCK_TYPE_GFX,
4437 .major = 9,
4438 .minor = 0,
4439 .rev = 0,
4440 .funcs = &gfx_v9_0_ip_funcs,
4441};
Ubuntu Jammy Linux kernel mirror