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drm/amdgpu:fix uvd ring fini routine(v2)
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
248a1d6f 24#include <drm/drmP.h>
b1023571
KW		 25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
268cb4c7 41#define GFX9_MEC_HPD_SIZE 2048
6bce4667
HZ		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
b1023571 45
91d3130a
HZ		 46#define mmPWR_MISC_CNTL_STATUS 0x0183
47#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
b1023571
KW		 52
53MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
060d124b
CZ		 60MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62MODULE_FIRMWARE("amdgpu/raven_me.bin");
63MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
b1023571
KW		 67static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
68{
35c32f20
TSD		 69 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
73 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
77 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
81 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
85 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
86 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
87 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
88 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
89 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
90 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
91 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
92 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
93 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
94 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
95 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
96 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
97 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
98 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
99 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
100 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
101 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
102 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
103 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
104 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
105 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
106 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
107 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
108 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
109 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
110 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
111 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
112 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
113 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
114 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
115 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
116 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
117 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
118 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
119 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
120 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
121 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
122 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
123 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
124 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
125 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
126 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
127 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
128 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
129 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
130 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
131 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
132 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
b1023571
KW		 133};
134
135static const u32 golden_settings_gc_9_0[] =
136{
f8af9332
KW		 137 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
138 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
139 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
140 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
141 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
142 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
b1023571
KW		 143 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
144 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
145 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
f8af9332
KW		 146 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
147 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
148 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
149 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
150 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
ba219b3c 151 SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
f8af9332 152 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
ba219b3c 153 SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
b1023571
KW		 154 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
155 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
156 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
f8af9332
KW		 157 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
158 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
159 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
b1023571
KW		 160};
161
162static const u32 golden_settings_gc_9_0_vg10[] =
163{
164 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
165 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
166 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
167 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
168 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
169 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
f8af9332 170 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
b1023571
KW		 171};
172
a5fdb336
CZ		 173static const u32 golden_settings_gc_9_1[] =
174{
175 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
01b5cc36
HZ		 176 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
177 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
178 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 179 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
180 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
01b5cc36 181 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 182 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
183 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
184 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
01b5cc36
HZ		 185 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
186 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
187 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
188 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
189 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 190 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
191 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
192 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
01b5cc36
HZ		 193 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
194 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
195 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
a5fdb336
CZ		 196};
197
198static const u32 golden_settings_gc_9_1_rv1[] =
199{
7b6ba9ea
HZ		 200 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
201 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
202 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
203 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
204 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
205 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
a5fdb336 206 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
b1023571
KW		 207};
208
209#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
7b6ba9ea 210#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
b1023571
KW		 211
212static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
213static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
214static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
215static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
216static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
217 struct amdgpu_cu_info *cu_info);
218static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
219static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
635e7132 220static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
b1023571
KW		 221
222static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
223{
224 switch (adev->asic_type) {
225 case CHIP_VEGA10:
226 amdgpu_program_register_sequence(adev,
227 golden_settings_gc_9_0,
228 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
229 amdgpu_program_register_sequence(adev,
230 golden_settings_gc_9_0_vg10,
231 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
232 break;
a5fdb336
CZ		 233 case CHIP_RAVEN:
234 amdgpu_program_register_sequence(adev,
235 golden_settings_gc_9_1,
236 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
237 amdgpu_program_register_sequence(adev,
238 golden_settings_gc_9_1_rv1,
239 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
240 break;
b1023571
KW		 241 default:
242 break;
243 }
244}
245
246static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
247{
6a05148f 248 adev->gfx.scratch.num_reg = 8;
b1023571
KW		 249 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
250 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
251}
252
253static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
254 bool wc, uint32_t reg, uint32_t val)
255{
256 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
257 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
258 WRITE_DATA_DST_SEL(0) |
259 (wc ? WR_CONFIRM : 0));
260 amdgpu_ring_write(ring, reg);
261 amdgpu_ring_write(ring, 0);
262 amdgpu_ring_write(ring, val);
263}
264
265static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
266 int mem_space, int opt, uint32_t addr0,
267 uint32_t addr1, uint32_t ref, uint32_t mask,
268 uint32_t inv)
269{
270 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
271 amdgpu_ring_write(ring,
272 /* memory (1) or register (0) */
273 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
274 WAIT_REG_MEM_OPERATION(opt) | /* wait */
275 WAIT_REG_MEM_FUNCTION(3) | /* equal */
276 WAIT_REG_MEM_ENGINE(eng_sel)));
277
278 if (mem_space)
279 BUG_ON(addr0 & 0x3); /* Dword align */
280 amdgpu_ring_write(ring, addr0);
281 amdgpu_ring_write(ring, addr1);
282 amdgpu_ring_write(ring, ref);
283 amdgpu_ring_write(ring, mask);
284 amdgpu_ring_write(ring, inv); /* poll interval */
285}
286
287static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
288{
289 struct amdgpu_device *adev = ring->adev;
290 uint32_t scratch;
291 uint32_t tmp = 0;
292 unsigned i;
293 int r;
294
295 r = amdgpu_gfx_scratch_get(adev, &scratch);
296 if (r) {
297 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
298 return r;
299 }
300 WREG32(scratch, 0xCAFEDEAD);
301 r = amdgpu_ring_alloc(ring, 3);
302 if (r) {
303 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
304 ring->idx, r);
305 amdgpu_gfx_scratch_free(adev, scratch);
306 return r;
307 }
308 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
309 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
310 amdgpu_ring_write(ring, 0xDEADBEEF);
311 amdgpu_ring_commit(ring);
312
313 for (i = 0; i < adev->usec_timeout; i++) {
314 tmp = RREG32(scratch);
315 if (tmp == 0xDEADBEEF)
316 break;
317 DRM_UDELAY(1);
318 }
319 if (i < adev->usec_timeout) {
320 DRM_INFO("ring test on %d succeeded in %d usecs\n",
321 ring->idx, i);
322 } else {
323 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
324 ring->idx, scratch, tmp);
325 r = -EINVAL;
326 }
327 amdgpu_gfx_scratch_free(adev, scratch);
328 return r;
329}
330
331static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
332{
333 struct amdgpu_device *adev = ring->adev;
334 struct amdgpu_ib ib;
335 struct dma_fence *f = NULL;
336 uint32_t scratch;
337 uint32_t tmp = 0;
338 long r;
339
340 r = amdgpu_gfx_scratch_get(adev, &scratch);
341 if (r) {
342 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
343 return r;
344 }
345 WREG32(scratch, 0xCAFEDEAD);
346 memset(&ib, 0, sizeof(ib));
347 r = amdgpu_ib_get(adev, NULL, 256, &ib);
348 if (r) {
349 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
350 goto err1;
351 }
352 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
353 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
354 ib.ptr[2] = 0xDEADBEEF;
355 ib.length_dw = 3;
356
357 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
358 if (r)
359 goto err2;
360
361 r = dma_fence_wait_timeout(f, false, timeout);
362 if (r == 0) {
363 DRM_ERROR("amdgpu: IB test timed out.\n");
364 r = -ETIMEDOUT;
365 goto err2;
366 } else if (r < 0) {
367 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
368 goto err2;
369 }
370 tmp = RREG32(scratch);
371 if (tmp == 0xDEADBEEF) {
372 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
373 r = 0;
374 } else {
375 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
376 scratch, tmp);
377 r = -EINVAL;
378 }
379err2:
380 amdgpu_ib_free(adev, &ib, NULL);
381 dma_fence_put(f);
382err1:
383 amdgpu_gfx_scratch_free(adev, scratch);
384 return r;
385}
386
387static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
388{
389 const char *chip_name;
390 char fw_name[30];
391 int err;
392 struct amdgpu_firmware_info *info = NULL;
393 const struct common_firmware_header *header = NULL;
394 const struct gfx_firmware_header_v1_0 *cp_hdr;
a4d41ad0
HZ		 395 const struct rlc_firmware_header_v2_0 *rlc_hdr;
396 unsigned int *tmp = NULL;
397 unsigned int i = 0;
b1023571
KW		 398
399 DRM_DEBUG("\n");
400
401 switch (adev->asic_type) {
402 case CHIP_VEGA10:
403 chip_name = "vega10";
404 break;
eaa85724
CZ		 405 case CHIP_RAVEN:
406 chip_name = "raven";
407 break;
b1023571
KW		 408 default:
409 BUG();
410 }
411
412 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
413 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
414 if (err)
415 goto out;
416 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
417 if (err)
418 goto out;
419 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
420 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
421 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
422
423 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
424 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
425 if (err)
426 goto out;
427 err = amdgpu_ucode_validate(adev->gfx.me_fw);
428 if (err)
429 goto out;
430 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
431 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
432 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
433
434 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
435 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
436 if (err)
437 goto out;
438 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
439 if (err)
440 goto out;
441 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
442 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
443 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
444
445 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
446 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
447 if (err)
448 goto out;
449 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
a4d41ad0
HZ		 450 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
451 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
452 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
453 adev->gfx.rlc.save_and_restore_offset =
454 le32_to_cpu(rlc_hdr->save_and_restore_offset);
455 adev->gfx.rlc.clear_state_descriptor_offset =
456 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
457 adev->gfx.rlc.avail_scratch_ram_locations =
458 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
459 adev->gfx.rlc.reg_restore_list_size =
460 le32_to_cpu(rlc_hdr->reg_restore_list_size);
461 adev->gfx.rlc.reg_list_format_start =
462 le32_to_cpu(rlc_hdr->reg_list_format_start);
463 adev->gfx.rlc.reg_list_format_separate_start =
464 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
465 adev->gfx.rlc.starting_offsets_start =
466 le32_to_cpu(rlc_hdr->starting_offsets_start);
467 adev->gfx.rlc.reg_list_format_size_bytes =
468 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
469 adev->gfx.rlc.reg_list_size_bytes =
470 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
471 adev->gfx.rlc.register_list_format =
472 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
473 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
474 if (!adev->gfx.rlc.register_list_format) {
475 err = -ENOMEM;
476 goto out;
477 }
478
479 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
480 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
481 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
482 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
483
484 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
485
486 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
487 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
488 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
489 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
b1023571
KW		 490
491 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
492 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
493 if (err)
494 goto out;
495 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
496 if (err)
497 goto out;
498 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
499 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
500 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
501
502
503 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
504 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
505 if (!err) {
506 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
507 if (err)
508 goto out;
509 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
510 adev->gfx.mec2_fw->data;
511 adev->gfx.mec2_fw_version =
512 le32_to_cpu(cp_hdr->header.ucode_version);
513 adev->gfx.mec2_feature_version =
514 le32_to_cpu(cp_hdr->ucode_feature_version);
515 } else {
516 err = 0;
517 adev->gfx.mec2_fw = NULL;
518 }
519
520 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
521 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
522 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
523 info->fw = adev->gfx.pfp_fw;
524 header = (const struct common_firmware_header *)info->fw->data;
525 adev->firmware.fw_size +=
526 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
527
528 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
529 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
530 info->fw = adev->gfx.me_fw;
531 header = (const struct common_firmware_header *)info->fw->data;
532 adev->firmware.fw_size +=
533 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
534
535 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
536 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
537 info->fw = adev->gfx.ce_fw;
538 header = (const struct common_firmware_header *)info->fw->data;
539 adev->firmware.fw_size +=
540 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
541
542 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
543 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
544 info->fw = adev->gfx.rlc_fw;
545 header = (const struct common_firmware_header *)info->fw->data;
546 adev->firmware.fw_size +=
547 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
548
549 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
550 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
551 info->fw = adev->gfx.mec_fw;
552 header = (const struct common_firmware_header *)info->fw->data;
553 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
554 adev->firmware.fw_size +=
555 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
556
557 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
558 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
559 info->fw = adev->gfx.mec_fw;
560 adev->firmware.fw_size +=
561 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
562
563 if (adev->gfx.mec2_fw) {
564 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
565 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
566 info->fw = adev->gfx.mec2_fw;
567 header = (const struct common_firmware_header *)info->fw->data;
568 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
569 adev->firmware.fw_size +=
570 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
571 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
572 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
573 info->fw = adev->gfx.mec2_fw;
574 adev->firmware.fw_size +=
575 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
576 }
577
578 }
579
580out:
581 if (err) {
582 dev_err(adev->dev,
583 "gfx9: Failed to load firmware \"%s\"\n",
584 fw_name);
585 release_firmware(adev->gfx.pfp_fw);
586 adev->gfx.pfp_fw = NULL;
587 release_firmware(adev->gfx.me_fw);
588 adev->gfx.me_fw = NULL;
589 release_firmware(adev->gfx.ce_fw);
590 adev->gfx.ce_fw = NULL;
591 release_firmware(adev->gfx.rlc_fw);
592 adev->gfx.rlc_fw = NULL;
593 release_firmware(adev->gfx.mec_fw);
594 adev->gfx.mec_fw = NULL;
595 release_firmware(adev->gfx.mec2_fw);
596 adev->gfx.mec2_fw = NULL;
597 }
598 return err;
599}
600
c9719c69
HZ		 601static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
602{
603 u32 count = 0;
604 const struct cs_section_def *sect = NULL;
605 const struct cs_extent_def *ext = NULL;
606
607 /* begin clear state */
608 count += 2;
609 /* context control state */
610 count += 3;
611
612 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
613 for (ext = sect->section; ext->extent != NULL; ++ext) {
614 if (sect->id == SECT_CONTEXT)
615 count += 2 + ext->reg_count;
616 else
617 return 0;
618 }
619 }
620
621 /* end clear state */
622 count += 2;
623 /* clear state */
624 count += 2;
625
626 return count;
627}
628
629static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
630 volatile u32 *buffer)
631{
632 u32 count = 0, i;
633 const struct cs_section_def *sect = NULL;
634 const struct cs_extent_def *ext = NULL;
635
636 if (adev->gfx.rlc.cs_data == NULL)
637 return;
638 if (buffer == NULL)
639 return;
640
641 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
642 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
643
644 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
645 buffer[count++] = cpu_to_le32(0x80000000);
646 buffer[count++] = cpu_to_le32(0x80000000);
647
648 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
649 for (ext = sect->section; ext->extent != NULL; ++ext) {
650 if (sect->id == SECT_CONTEXT) {
651 buffer[count++] =
652 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
653 buffer[count++] = cpu_to_le32(ext->reg_index -
654 PACKET3_SET_CONTEXT_REG_START);
655 for (i = 0; i < ext->reg_count; i++)
656 buffer[count++] = cpu_to_le32(ext->extent[i]);
657 } else {
658 return;
659 }
660 }
661 }
662
663 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
664 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
665
666 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
667 buffer[count++] = cpu_to_le32(0);
668}
669
ba7bb665
HZ		 670static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
671{
e5475e16 672 uint32_t data;
ba7bb665
HZ		 673
674 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
675 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
676 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
677 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
678 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
679
680 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
681 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
682
683 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
684 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
685
686 mutex_lock(&adev->grbm_idx_mutex);
687 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
688 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
689 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
690
691 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
e5475e16
TSD		 692 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
693 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
694 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
ba7bb665
HZ		 695 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
696
697 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
698 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
699 data &= 0x0000FFFF;
700 data |= 0x00C00000;
701 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
702
703 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
704 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
705
706 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
707 * but used for RLC_LB_CNTL configuration */
708 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
e5475e16
TSD		 709 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
710 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
ba7bb665
HZ		 711 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
712 mutex_unlock(&adev->grbm_idx_mutex);
713}
714
e8835e0e
HZ		 715static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
716{
e5475e16 717 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
e8835e0e
HZ		 718}
719
c9719c69
HZ		 720static void rv_init_cp_jump_table(struct amdgpu_device *adev)
721{
722 const __le32 *fw_data;
723 volatile u32 *dst_ptr;
724 int me, i, max_me = 5;
725 u32 bo_offset = 0;
726 u32 table_offset, table_size;
727
728 /* write the cp table buffer */
729 dst_ptr = adev->gfx.rlc.cp_table_ptr;
730 for (me = 0; me < max_me; me++) {
731 if (me == 0) {
732 const struct gfx_firmware_header_v1_0 *hdr =
733 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
734 fw_data = (const __le32 *)
735 (adev->gfx.ce_fw->data +
736 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
737 table_offset = le32_to_cpu(hdr->jt_offset);
738 table_size = le32_to_cpu(hdr->jt_size);
739 } else if (me == 1) {
740 const struct gfx_firmware_header_v1_0 *hdr =
741 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
742 fw_data = (const __le32 *)
743 (adev->gfx.pfp_fw->data +
744 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
745 table_offset = le32_to_cpu(hdr->jt_offset);
746 table_size = le32_to_cpu(hdr->jt_size);
747 } else if (me == 2) {
748 const struct gfx_firmware_header_v1_0 *hdr =
749 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
750 fw_data = (const __le32 *)
751 (adev->gfx.me_fw->data +
752 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
753 table_offset = le32_to_cpu(hdr->jt_offset);
754 table_size = le32_to_cpu(hdr->jt_size);
755 } else if (me == 3) {
756 const struct gfx_firmware_header_v1_0 *hdr =
757 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
758 fw_data = (const __le32 *)
759 (adev->gfx.mec_fw->data +
760 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
761 table_offset = le32_to_cpu(hdr->jt_offset);
762 table_size = le32_to_cpu(hdr->jt_size);
763 } else if (me == 4) {
764 const struct gfx_firmware_header_v1_0 *hdr =
765 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
766 fw_data = (const __le32 *)
767 (adev->gfx.mec2_fw->data +
768 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
769 table_offset = le32_to_cpu(hdr->jt_offset);
770 table_size = le32_to_cpu(hdr->jt_size);
771 }
772
773 for (i = 0; i < table_size; i ++) {
774 dst_ptr[bo_offset + i] =
775 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
776 }
777
778 bo_offset += table_size;
779 }
780}
781
782static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
783{
784 /* clear state block */
785 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
786 &adev->gfx.rlc.clear_state_gpu_addr,
787 (void **)&adev->gfx.rlc.cs_ptr);
788
789 /* jump table block */
790 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
791 &adev->gfx.rlc.cp_table_gpu_addr,
792 (void **)&adev->gfx.rlc.cp_table_ptr);
793}
794
795static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
796{
797 volatile u32 *dst_ptr;
798 u32 dws;
799 const struct cs_section_def *cs_data;
800 int r;
801
802 adev->gfx.rlc.cs_data = gfx9_cs_data;
803
804 cs_data = adev->gfx.rlc.cs_data;
805
806 if (cs_data) {
807 /* clear state block */
808 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
a4a02777
CK		 809 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
810 AMDGPU_GEM_DOMAIN_VRAM,
811 &adev->gfx.rlc.clear_state_obj,
812 &adev->gfx.rlc.clear_state_gpu_addr,
813 (void **)&adev->gfx.rlc.cs_ptr);
814 if (r) {
815 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
816 r);
817 gfx_v9_0_rlc_fini(adev);
818 return r;
c9719c69
HZ		 819 }
820 /* set up the cs buffer */
821 dst_ptr = adev->gfx.rlc.cs_ptr;
822 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
823 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
824 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
825 }
826
827 if (adev->asic_type == CHIP_RAVEN) {
828 /* TODO: double check the cp_table_size for RV */
829 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
a4a02777
CK		 830 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
831 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
832 &adev->gfx.rlc.cp_table_obj,
833 &adev->gfx.rlc.cp_table_gpu_addr,
834 (void **)&adev->gfx.rlc.cp_table_ptr);
835 if (r) {
836 dev_err(adev->dev,
837 "(%d) failed to create cp table bo\n", r);
838 gfx_v9_0_rlc_fini(adev);
839 return r;
c9719c69
HZ		 840 }
841
842 rv_init_cp_jump_table(adev);
843 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
844 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
ba7bb665
HZ		 845
846 gfx_v9_0_init_lbpw(adev);
c9719c69
HZ		 847 }
848
849 return 0;
850}
851
b1023571
KW		 852static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
853{
078af1a3
CK		 854 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
855 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
b1023571
KW		 856}
857
b1023571
KW		 858static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
859{
860 int r;
861 u32 *hpd;
862 const __le32 *fw_data;
863 unsigned fw_size;
864 u32 *fw;
42794b27 865 size_t mec_hpd_size;
b1023571
KW		 866
867 const struct gfx_firmware_header_v1_0 *mec_hdr;
868
78c16834
AR		 869 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
870
78c16834 871 /* take ownership of the relevant compute queues */
41f6a99a 872 amdgpu_gfx_compute_queue_acquire(adev);
78c16834 873 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
b1023571 874
a4a02777
CK		 875 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
876 AMDGPU_GEM_DOMAIN_GTT,
877 &adev->gfx.mec.hpd_eop_obj,
878 &adev->gfx.mec.hpd_eop_gpu_addr,
879 (void **)&hpd);
b1023571 880 if (r) {
a4a02777 881 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
b1023571
KW		 882 gfx_v9_0_mec_fini(adev);
883 return r;
884 }
885
886 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
887
888 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
889 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
890
891 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
892
893 fw_data = (const __le32 *)
894 (adev->gfx.mec_fw->data +
895 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
896 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
897
a4a02777
CK		 898 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
899 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
900 &adev->gfx.mec.mec_fw_obj,
901 &adev->gfx.mec.mec_fw_gpu_addr,
902 (void **)&fw);
b1023571 903 if (r) {
a4a02777 904 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
b1023571
KW		 905 gfx_v9_0_mec_fini(adev);
906 return r;
907 }
a4a02777 908
b1023571
KW		 909 memcpy(fw, fw_data, fw_size);
910
911 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
912 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
913
b1023571
KW		 914 return 0;
915}
916
917static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
918{
5e78835a 919 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 920 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
921 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
922 (address << SQ_IND_INDEX__INDEX__SHIFT) |
923 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 924 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 925}
926
927static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
928 uint32_t wave, uint32_t thread,
929 uint32_t regno, uint32_t num, uint32_t *out)
930{
5e78835a 931 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 932 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
933 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
934 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
935 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
936 (SQ_IND_INDEX__FORCE_READ_MASK) |
937 (SQ_IND_INDEX__AUTO_INCR_MASK));
938 while (num--)
5e78835a 939 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 940}
941
942static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
943{
944 /* type 1 wave data */
945 dst[(*no_fields)++] = 1;
946 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
947 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
948 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
949 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
950 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
951 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
952 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
953 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
954 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
955 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
956 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
957 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
958 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
959 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
960}
961
962static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
963 uint32_t wave, uint32_t start,
964 uint32_t size, uint32_t *dst)
965{
966 wave_read_regs(
967 adev, simd, wave, 0,
968 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
969}
970
971
972static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
973 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
974 .select_se_sh = &gfx_v9_0_select_se_sh,
975 .read_wave_data = &gfx_v9_0_read_wave_data,
976 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
977};
978
979static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
980{
981 u32 gb_addr_config;
982
983 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
984
985 switch (adev->asic_type) {
986 case CHIP_VEGA10:
b1023571 987 adev->gfx.config.max_hw_contexts = 8;
b1023571
KW		 988 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
989 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
990 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
991 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
992 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
993 break;
5cf7433d
CZ		 994 case CHIP_RAVEN:
995 adev->gfx.config.max_hw_contexts = 8;
996 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
997 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
998 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
999 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1000 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1001 break;
b1023571
KW		 1002 default:
1003 BUG();
1004 break;
1005 }
1006
1007 adev->gfx.config.gb_addr_config = gb_addr_config;
1008
1009 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1010 REG_GET_FIELD(
1011 adev->gfx.config.gb_addr_config,
1012 GB_ADDR_CONFIG,
1013 NUM_PIPES);
ad7d0ff3
AD		 1014
1015 adev->gfx.config.max_tile_pipes =
1016 adev->gfx.config.gb_addr_config_fields.num_pipes;
1017
b1023571
KW		 1018 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1019 REG_GET_FIELD(
1020 adev->gfx.config.gb_addr_config,
1021 GB_ADDR_CONFIG,
1022 NUM_BANKS);
1023 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1024 REG_GET_FIELD(
1025 adev->gfx.config.gb_addr_config,
1026 GB_ADDR_CONFIG,
1027 MAX_COMPRESSED_FRAGS);
1028 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1029 REG_GET_FIELD(
1030 adev->gfx.config.gb_addr_config,
1031 GB_ADDR_CONFIG,
1032 NUM_RB_PER_SE);
1033 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1034 REG_GET_FIELD(
1035 adev->gfx.config.gb_addr_config,
1036 GB_ADDR_CONFIG,
1037 NUM_SHADER_ENGINES);
1038 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1039 REG_GET_FIELD(
1040 adev->gfx.config.gb_addr_config,
1041 GB_ADDR_CONFIG,
1042 PIPE_INTERLEAVE_SIZE));
1043}
1044
1045static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1046 struct amdgpu_ngg_buf *ngg_buf,
1047 int size_se,
1048 int default_size_se)
1049{
1050 int r;
1051
1052 if (size_se < 0) {
1053 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1054 return -EINVAL;
1055 }
1056 size_se = size_se ? size_se : default_size_se;
1057
42ce2243 1058 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 1059 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1060 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1061 &ngg_buf->bo,
1062 &ngg_buf->gpu_addr,
1063 NULL);
1064 if (r) {
1065 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1066 return r;
1067 }
1068 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1069
1070 return r;
1071}
1072
1073static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1074{
1075 int i;
1076
1077 for (i = 0; i < NGG_BUF_MAX; i++)
1078 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1079 &adev->gfx.ngg.buf[i].gpu_addr,
1080 NULL);
1081
1082 memset(&adev->gfx.ngg.buf[0], 0,
1083 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1084
1085 adev->gfx.ngg.init = false;
1086
1087 return 0;
1088}
1089
1090static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1091{
1092 int r;
1093
1094 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1095 return 0;
1096
1097 /* GDS reserve memory: 64 bytes alignment */
1098 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1099 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1100 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1101 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1102 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1103
1104 /* Primitive Buffer */
af8baf15 1105 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
b1023571
KW		 1106 amdgpu_prim_buf_per_se,
1107 64 * 1024);
1108 if (r) {
1109 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1110 goto err;
1111 }
1112
1113 /* Position Buffer */
af8baf15 1114 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
b1023571
KW		 1115 amdgpu_pos_buf_per_se,
1116 256 * 1024);
1117 if (r) {
1118 dev_err(adev->dev, "Failed to create Position Buffer\n");
1119 goto err;
1120 }
1121
1122 /* Control Sideband */
af8baf15 1123 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
b1023571
KW		 1124 amdgpu_cntl_sb_buf_per_se,
1125 256);
1126 if (r) {
1127 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1128 goto err;
1129 }
1130
1131 /* Parameter Cache, not created by default */
1132 if (amdgpu_param_buf_per_se <= 0)
1133 goto out;
1134
af8baf15 1135 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
b1023571
KW		 1136 amdgpu_param_buf_per_se,
1137 512 * 1024);
1138 if (r) {
1139 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1140 goto err;
1141 }
1142
1143out:
1144 adev->gfx.ngg.init = true;
1145 return 0;
1146err:
1147 gfx_v9_0_ngg_fini(adev);
1148 return r;
1149}
1150
1151static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1152{
1153 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1154 int r;
91629eff 1155 u32 data, base;
b1023571
KW		 1156
1157 if (!amdgpu_ngg)
1158 return 0;
1159
1160 /* Program buffer size */
91629eff
TSD		 1161 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1162 adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1163 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1164 adev->gfx.ngg.buf[NGG_POS].size >> 8);
5e78835a 1165 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571 1166
91629eff
TSD		 1167 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1168 adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1169 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1170 adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
5e78835a 1171 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 1172
1173 /* Program buffer base address */
af8baf15 1174 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1175 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 1176 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571 1177
af8baf15 1178 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1179 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 1180 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571 1181
af8baf15 1182 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1183 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 1184 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571 1185
af8baf15 1186 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1187 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 1188 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571 1189
af8baf15 1190 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1191 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 1192 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571 1193
af8baf15 1194 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1195 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 1196 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 1197
1198 /* Clear GDS reserved memory */
1199 r = amdgpu_ring_alloc(ring, 17);
1200 if (r) {
1201 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1202 ring->idx, r);
1203 return r;
1204 }
1205
1206 gfx_v9_0_write_data_to_reg(ring, 0, false,
1207 amdgpu_gds_reg_offset[0].mem_size,
1208 (adev->gds.mem.total_size +
1209 adev->gfx.ngg.gds_reserve_size) >>
1210 AMDGPU_GDS_SHIFT);
1211
1212 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1213 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1214 PACKET3_DMA_DATA_SRC_SEL(2)));
1215 amdgpu_ring_write(ring, 0);
1216 amdgpu_ring_write(ring, 0);
1217 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1218 amdgpu_ring_write(ring, 0);
1219 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1220
1221
1222 gfx_v9_0_write_data_to_reg(ring, 0, false,
1223 amdgpu_gds_reg_offset[0].mem_size, 0);
1224
1225 amdgpu_ring_commit(ring);
1226
1227 return 0;
1228}
1229
1361f455
AD		 1230static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1231 int mec, int pipe, int queue)
1232{
1233 int r;
1234 unsigned irq_type;
1235 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1236
1237 ring = &adev->gfx.compute_ring[ring_id];
1238
1239 /* mec0 is me1 */
1240 ring->me = mec + 1;
1241 ring->pipe = pipe;
1242 ring->queue = queue;
1243
1244 ring->ring_obj = NULL;
1245 ring->use_doorbell = true;
7366af81 1246 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1361f455
AD		 1247 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1248 + (ring_id * GFX9_MEC_HPD_SIZE);
1249 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1250
1251 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1252 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1253 + ring->pipe;
1254
1255 /* type-2 packets are deprecated on MEC, use type-3 instead */
1256 r = amdgpu_ring_init(adev, ring, 1024,
1257 &adev->gfx.eop_irq, irq_type);
1258 if (r)
1259 return r;
1260
1261
1262 return 0;
1263}
1264
b1023571
KW		 1265static int gfx_v9_0_sw_init(void *handle)
1266{
1361f455 1267 int i, j, k, r, ring_id;
b1023571 1268 struct amdgpu_ring *ring;
ac104e99 1269 struct amdgpu_kiq *kiq;
b1023571
KW		 1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1271
4853bbb6
AD		 1272 switch (adev->asic_type) {
1273 case CHIP_VEGA10:
1274 case CHIP_RAVEN:
1275 adev->gfx.mec.num_mec = 2;
1276 break;
1277 default:
1278 adev->gfx.mec.num_mec = 1;
1279 break;
1280 }
1281
1282 adev->gfx.mec.num_pipe_per_mec = 4;
1283 adev->gfx.mec.num_queue_per_pipe = 8;
1284
97031e25
XY		 1285 /* KIQ event */
1286 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1287 if (r)
1288 return r;
1289
b1023571
KW		 1290 /* EOP Event */
1291 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1292 if (r)
1293 return r;
1294
1295 /* Privileged reg */
1296 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1297 &adev->gfx.priv_reg_irq);
1298 if (r)
1299 return r;
1300
1301 /* Privileged inst */
1302 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1303 &adev->gfx.priv_inst_irq);
1304 if (r)
1305 return r;
1306
1307 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1308
1309 gfx_v9_0_scratch_init(adev);
1310
1311 r = gfx_v9_0_init_microcode(adev);
1312 if (r) {
1313 DRM_ERROR("Failed to load gfx firmware!\n");
1314 return r;
1315 }
1316
c9719c69
HZ		 1317 r = gfx_v9_0_rlc_init(adev);
1318 if (r) {
1319 DRM_ERROR("Failed to init rlc BOs!\n");
1320 return r;
1321 }
1322
b1023571
KW		 1323 r = gfx_v9_0_mec_init(adev);
1324 if (r) {
1325 DRM_ERROR("Failed to init MEC BOs!\n");
1326 return r;
1327 }
1328
1329 /* set up the gfx ring */
1330 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1331 ring = &adev->gfx.gfx_ring[i];
1332 ring->ring_obj = NULL;
f6886c47
TSD		 1333 if (!i)
1334 sprintf(ring->name, "gfx");
1335 else
1336 sprintf(ring->name, "gfx_%d", i);
b1023571
KW		 1337 ring->use_doorbell = true;
1338 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1339 r = amdgpu_ring_init(adev, ring, 1024,
1340 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1341 if (r)
1342 return r;
1343 }
1344
1361f455
AD		 1345 /* set up the compute queues - allocate horizontally across pipes */
1346 ring_id = 0;
1347 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1348 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1349 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2db0cdbe 1350 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1361f455
AD		 1351 continue;
1352
1353 r = gfx_v9_0_compute_ring_init(adev,
1354 ring_id,
1355 i, k, j);
1356 if (r)
1357 return r;
1358
1359 ring_id++;
1360 }
b1023571 1361 }
b1023571
KW		 1362 }
1363
71c37505 1364 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
e30a5223
AD		 1365 if (r) {
1366 DRM_ERROR("Failed to init KIQ BOs!\n");
1367 return r;
1368 }
ac104e99 1369
e30a5223 1370 kiq = &adev->gfx.kiq;
71c37505 1371 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
e30a5223
AD		 1372 if (r)
1373 return r;
464826d6 1374
e30a5223 1375 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
ffe6d881 1376 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
e30a5223
AD		 1377 if (r)
1378 return r;
ac104e99 1379
b1023571
KW		 1380 /* reserve GDS, GWS and OA resource for gfx */
1381 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1382 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1383 &adev->gds.gds_gfx_bo, NULL, NULL);
1384 if (r)
1385 return r;
1386
1387 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1388 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1389 &adev->gds.gws_gfx_bo, NULL, NULL);
1390 if (r)
1391 return r;
1392
1393 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1394 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1395 &adev->gds.oa_gfx_bo, NULL, NULL);
1396 if (r)
1397 return r;
1398
1399 adev->gfx.ce_ram_size = 0x8000;
1400
1401 gfx_v9_0_gpu_early_init(adev);
1402
1403 r = gfx_v9_0_ngg_init(adev);
1404 if (r)
1405 return r;
1406
1407 return 0;
1408}
1409
1410
1411static int gfx_v9_0_sw_fini(void *handle)
1412{
1413 int i;
1414 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1415
1416 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1417 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1418 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1419
1420 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1421 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1422 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1423 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1424
b9683c21 1425 amdgpu_gfx_compute_mqd_sw_fini(adev);
71c37505
AD		 1426 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1427 amdgpu_gfx_kiq_fini(adev);
030308fc 1428 amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
ac104e99 1429
b1023571
KW		 1430 gfx_v9_0_mec_fini(adev);
1431 gfx_v9_0_ngg_fini(adev);
1432
1433 return 0;
1434}
1435
1436
1437static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1438{
1439 /* TODO */
1440}
1441
1442static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1443{
be448a4d 1444 u32 data;
b1023571 1445
be448a4d
NH		 1446 if (instance == 0xffffffff)
1447 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1448 else
1449 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1450
1451 if (se_num == 0xffffffff)
b1023571 1452 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
be448a4d 1453 else
b1023571 1454 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
be448a4d
NH		 1455
1456 if (sh_num == 0xffffffff)
1457 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1458 else
b1023571 1459 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
be448a4d 1460
5e78835a 1461 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1462}
1463
b1023571
KW		 1464static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1465{
1466 u32 data, mask;
1467
5e78835a
TSD		 1468 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1469 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1470
1471 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1472 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1473
378506a7
AD		 1474 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1475 adev->gfx.config.max_sh_per_se);
b1023571
KW		 1476
1477 return (~data) & mask;
1478}
1479
1480static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1481{
1482 int i, j;
2572c24c 1483 u32 data;
b1023571
KW		 1484 u32 active_rbs = 0;
1485 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1486 adev->gfx.config.max_sh_per_se;
1487
1488 mutex_lock(&adev->grbm_idx_mutex);
1489 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1490 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1491 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1492 data = gfx_v9_0_get_rb_active_bitmap(adev);
1493 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1494 rb_bitmap_width_per_sh);
1495 }
1496 }
1497 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1498 mutex_unlock(&adev->grbm_idx_mutex);
1499
1500 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1501 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1502}
1503
1504#define DEFAULT_SH_MEM_BASES (0x6000)
1505#define FIRST_COMPUTE_VMID (8)
1506#define LAST_COMPUTE_VMID (16)
1507static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1508{
1509 int i;
1510 uint32_t sh_mem_config;
1511 uint32_t sh_mem_bases;
1512
1513 /*
1514 * Configure apertures:
1515 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1516 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1517 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1518 */
1519 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1520
1521 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1522 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
eaa05d52 1523 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
b1023571
KW		 1524
1525 mutex_lock(&adev->srbm_mutex);
1526 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1527 soc15_grbm_select(adev, 0, 0, 0, i);
1528 /* CP and shaders */
5e78835a
TSD		 1529 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1530 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1531 }
1532 soc15_grbm_select(adev, 0, 0, 0, 0);
1533 mutex_unlock(&adev->srbm_mutex);
1534}
1535
1536static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1537{
1538 u32 tmp;
1539 int i;
1540
40f06773 1541 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1542
1543 gfx_v9_0_tiling_mode_table_init(adev);
1544
1545 gfx_v9_0_setup_rb(adev);
1546 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1547
1548 /* XXX SH_MEM regs */
1549 /* where to put LDS, scratch, GPUVM in FSA64 space */
1550 mutex_lock(&adev->srbm_mutex);
1551 for (i = 0; i < 16; i++) {
1552 soc15_grbm_select(adev, 0, 0, 0, i);
1553 /* CP and shaders */
1554 tmp = 0;
1555 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1556 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5e78835a
TSD		 1557 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1558 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
b1023571
KW		 1559 }
1560 soc15_grbm_select(adev, 0, 0, 0, 0);
1561
1562 mutex_unlock(&adev->srbm_mutex);
1563
1564 gfx_v9_0_init_compute_vmid(adev);
1565
1566 mutex_lock(&adev->grbm_idx_mutex);
1567 /*
1568 * making sure that the following register writes will be broadcasted
1569 * to all the shaders
1570 */
1571 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1572
5e78835a 1573 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1574 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1575 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1576 (adev->gfx.config.sc_prim_fifo_size_backend <<
1577 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1578 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1579 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1580 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1581 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1582 mutex_unlock(&adev->grbm_idx_mutex);
1583
1584}
1585
1586static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1587{
1588 u32 i, j, k;
1589 u32 mask;
1590
1591 mutex_lock(&adev->grbm_idx_mutex);
1592 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1593 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1594 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1595 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1596 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1597 break;
1598 udelay(1);
1599 }
1600 }
1601 }
1602 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1603 mutex_unlock(&adev->grbm_idx_mutex);
1604
1605 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1606 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1607 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1608 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1609 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1610 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1611 break;
1612 udelay(1);
1613 }
1614}
1615
1616static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1617 bool enable)
1618{
5e78835a 1619 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571 1620
b1023571
KW		 1621 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1622 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1623 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1624 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1625
5e78835a 1626 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1627}
1628
6bce4667
HZ		 1629static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1630{
1631 /* csib */
1632 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1633 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1634 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1635 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1636 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1637 adev->gfx.rlc.clear_state_size);
1638}
1639
1640static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1641 int indirect_offset,
1642 int list_size,
1643 int *unique_indirect_regs,
1644 int *unique_indirect_reg_count,
1645 int max_indirect_reg_count,
1646 int *indirect_start_offsets,
1647 int *indirect_start_offsets_count,
1648 int max_indirect_start_offsets_count)
1649{
1650 int idx;
1651 bool new_entry = true;
1652
1653 for (; indirect_offset < list_size; indirect_offset++) {
1654
1655 if (new_entry) {
1656 new_entry = false;
1657 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1658 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1659 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1660 }
1661
1662 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1663 new_entry = true;
1664 continue;
1665 }
1666
1667 indirect_offset += 2;
1668
1669 /* look for the matching indice */
1670 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1671 if (unique_indirect_regs[idx] ==
1672 register_list_format[indirect_offset])
1673 break;
1674 }
1675
1676 if (idx >= *unique_indirect_reg_count) {
1677 unique_indirect_regs[*unique_indirect_reg_count] =
1678 register_list_format[indirect_offset];
1679 idx = *unique_indirect_reg_count;
1680 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1681 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1682 }
1683
1684 register_list_format[indirect_offset] = idx;
1685 }
1686}
1687
1688static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1689{
1690 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1691 int unique_indirect_reg_count = 0;
1692
1693 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1694 int indirect_start_offsets_count = 0;
1695
1696 int list_size = 0;
1697 int i = 0;
1698 u32 tmp = 0;
1699
1700 u32 *register_list_format =
1701 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1702 if (!register_list_format)
1703 return -ENOMEM;
1704 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1705 adev->gfx.rlc.reg_list_format_size_bytes);
1706
1707 /* setup unique_indirect_regs array and indirect_start_offsets array */
1708 gfx_v9_0_parse_ind_reg_list(register_list_format,
1709 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1710 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1711 unique_indirect_regs,
1712 &unique_indirect_reg_count,
1713 sizeof(unique_indirect_regs)/sizeof(int),
1714 indirect_start_offsets,
1715 &indirect_start_offsets_count,
1716 sizeof(indirect_start_offsets)/sizeof(int));
1717
1718 /* enable auto inc in case it is disabled */
1719 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1720 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1721 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1722
1723 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1724 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1725 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1726 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1727 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1728 adev->gfx.rlc.register_restore[i]);
1729
1730 /* load direct register */
1731 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1732 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1733 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1734 adev->gfx.rlc.register_restore[i]);
1735
1736 /* load indirect register */
1737 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1738 adev->gfx.rlc.reg_list_format_start);
1739 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1740 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1741 register_list_format[i]);
1742
1743 /* set save/restore list size */
1744 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1745 list_size = list_size >> 1;
1746 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1747 adev->gfx.rlc.reg_restore_list_size);
1748 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1749
1750 /* write the starting offsets to RLC scratch ram */
1751 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1752 adev->gfx.rlc.starting_offsets_start);
1753 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1754 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1755 indirect_start_offsets[i]);
1756
1757 /* load unique indirect regs*/
1758 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1759 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1760 unique_indirect_regs[i] & 0x3FFFF);
1761 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1762 unique_indirect_regs[i] >> 20);
1763 }
1764
1765 kfree(register_list_format);
1766 return 0;
1767}
1768
1769static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1770{
0e5293d0 1771 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
6bce4667
HZ		 1772}
1773
91d3130a
HZ		 1774static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1775 bool enable)
1776{
1777 uint32_t data = 0;
1778 uint32_t default_data = 0;
1779
1780 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1781 if (enable == true) {
1782 /* enable GFXIP control over CGPG */
1783 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1784 if(default_data != data)
1785 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1786
1787 /* update status */
1788 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1789 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1790 if(default_data != data)
1791 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1792 } else {
1793 /* restore GFXIP control over GCPG */
1794 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1795 if(default_data != data)
1796 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1797 }
1798}
1799
1800static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1801{
1802 uint32_t data = 0;
1803
1804 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1805 AMD_PG_SUPPORT_GFX_SMG |
1806 AMD_PG_SUPPORT_GFX_DMG)) {
1807 /* init IDLE_POLL_COUNT = 60 */
1808 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1809 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1810 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1811 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1812
1813 /* init RLC PG Delay */
1814 data = 0;
1815 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1816 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1817 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1818 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1819 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1820
1821 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1822 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1823 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1824 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1825
1826 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1827 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1828 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1829 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1830
1831 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1832 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1833
1834 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1835 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1836 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1837
1838 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1839 }
1840}
1841
ed5ad1e4
HZ		 1842static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1843 bool enable)
1844{
1845 uint32_t data = 0;
1846 uint32_t default_data = 0;
1847
1848 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
e24c7f06
TSD		 1849 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1850 SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
1851 enable ? 1 : 0);
1852 if (default_data != data)
1853 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
ed5ad1e4
HZ		 1854}
1855
1856static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1857 bool enable)
1858{
1859 uint32_t data = 0;
1860 uint32_t default_data = 0;
1861
1862 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
b926fe8e
TSD		 1863 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1864 SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
1865 enable ? 1 : 0);
1866 if(default_data != data)
1867 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
ed5ad1e4
HZ		 1868}
1869
3a6cc477
HZ		 1870static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1871 bool enable)
1872{
1873 uint32_t data = 0;
1874 uint32_t default_data = 0;
1875
1876 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
54cfe0fc
TSD		 1877 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1878 CP_PG_DISABLE,
1879 enable ? 0 : 1);
1880 if(default_data != data)
1881 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
3a6cc477
HZ		 1882}
1883
197f95c8
HZ		 1884static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
1885 bool enable)
1886{
1887 uint32_t data, default_data;
1888
1889 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
f55ee212
TSD		 1890 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1891 GFX_POWER_GATING_ENABLE,
1892 enable ? 1 : 0);
197f95c8
HZ		 1893 if(default_data != data)
1894 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1895}
1896
1897static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
1898 bool enable)
1899{
1900 uint32_t data, default_data;
1901
1902 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
513f8133
TSD		 1903 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1904 GFX_PIPELINE_PG_ENABLE,
1905 enable ? 1 : 0);
197f95c8
HZ		 1906 if(default_data != data)
1907 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1908
1909 if (!enable)
1910 /* read any GFX register to wake up GFX */
1911 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
1912}
1913
552c8f76 1914static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
1915 bool enable)
18924c71
HZ		 1916{
1917 uint32_t data, default_data;
1918
1919 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
7915c8fd
TSD		 1920 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1921 STATIC_PER_CU_PG_ENABLE,
1922 enable ? 1 : 0);
18924c71
HZ		 1923 if(default_data != data)
1924 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1925}
1926
552c8f76 1927static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
18924c71
HZ		 1928 bool enable)
1929{
1930 uint32_t data, default_data;
1931
1932 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
e567fa69
TSD		 1933 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1934 DYN_PER_CU_PG_ENABLE,
1935 enable ? 1 : 0);
18924c71
HZ		 1936 if(default_data != data)
1937 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1938}
1939
6bce4667
HZ		 1940static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
1941{
1942 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1943 AMD_PG_SUPPORT_GFX_SMG |
1944 AMD_PG_SUPPORT_GFX_DMG |
1945 AMD_PG_SUPPORT_CP |
1946 AMD_PG_SUPPORT_GDS |
1947 AMD_PG_SUPPORT_RLC_SMU_HS)) {
1948 gfx_v9_0_init_csb(adev);
1949 gfx_v9_0_init_rlc_save_restore_list(adev);
1950 gfx_v9_0_enable_save_restore_machine(adev);
91d3130a
HZ		 1951
1952 if (adev->asic_type == CHIP_RAVEN) {
1953 WREG32(mmRLC_JUMP_TABLE_RESTORE,
1954 adev->gfx.rlc.cp_table_gpu_addr >> 8);
1955 gfx_v9_0_init_gfx_power_gating(adev);
3a6cc477 1956
ed5ad1e4
HZ		 1957 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
1958 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
1959 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
1960 } else {
1961 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
1962 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
1963 }
3a6cc477
HZ		 1964
1965 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
1966 gfx_v9_0_enable_cp_power_gating(adev, true);
1967 else
1968 gfx_v9_0_enable_cp_power_gating(adev, false);
91d3130a 1969 }
6bce4667
HZ		 1970 }
1971}
1972
b1023571
KW		 1973void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1974{
b08796ce 1975 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
b1023571 1976 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
b1023571
KW		 1977 gfx_v9_0_wait_for_rlc_serdes(adev);
1978}
1979
1980static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1981{
596c8e8b 1982 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 1983 udelay(50);
596c8e8b 1984 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 1985 udelay(50);
1986}
1987
1988static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1989{
1990#ifdef AMDGPU_RLC_DEBUG_RETRY
1991 u32 rlc_ucode_ver;
1992#endif
b1023571 1993
342cda25 1994 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 1995
1996 /* carrizo do enable cp interrupt after cp inited */
1997 if (!(adev->flags & AMD_IS_APU))
1998 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1999
2000 udelay(50);
2001
2002#ifdef AMDGPU_RLC_DEBUG_RETRY
2003 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 2004 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 2005 if(rlc_ucode_ver == 0x108) {
2006 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2007 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2008 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2009 * default is 0x9C4 to create a 100us interval */
5e78835a 2010 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571 2011 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
eaa05d52 2012 * to disable the page fault retry interrupts, default is
b1023571 2013 * 0x100 (256) */
5e78835a 2014 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 2015 }
2016#endif
2017}
2018
2019static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2020{
2021 const struct rlc_firmware_header_v2_0 *hdr;
2022 const __le32 *fw_data;
2023 unsigned i, fw_size;
2024
2025 if (!adev->gfx.rlc_fw)
2026 return -EINVAL;
2027
2028 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2029 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2030
2031 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2032 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2033 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2034
5e78835a 2035 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 2036 RLCG_UCODE_LOADING_START_ADDRESS);
2037 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2038 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2039 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 2040
2041 return 0;
2042}
2043
2044static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2045{
2046 int r;
2047
f840cc5f
ML		 2048 if (amdgpu_sriov_vf(adev)) {
2049 gfx_v9_0_init_csb(adev);
cfee05bc 2050 return 0;
f840cc5f 2051 }
cfee05bc 2052
b1023571
KW		 2053 gfx_v9_0_rlc_stop(adev);
2054
2055 /* disable CG */
5e78835a 2056 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 2057
2058 /* disable PG */
5e78835a 2059 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 2060
2061 gfx_v9_0_rlc_reset(adev);
2062
6bce4667
HZ		 2063 gfx_v9_0_init_pg(adev);
2064
b1023571
KW		 2065 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2066 /* legacy rlc firmware loading */
2067 r = gfx_v9_0_rlc_load_microcode(adev);
2068 if (r)
2069 return r;
2070 }
2071
e8835e0e
HZ		 2072 if (adev->asic_type == CHIP_RAVEN) {
2073 if (amdgpu_lbpw != 0)
2074 gfx_v9_0_enable_lbpw(adev, true);
2075 else
2076 gfx_v9_0_enable_lbpw(adev, false);
2077 }
2078
b1023571
KW		 2079 gfx_v9_0_rlc_start(adev);
2080
2081 return 0;
2082}
2083
2084static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2085{
2086 int i;
5e78835a 2087 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 2088
ea64468e
TSD		 2089 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2090 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2091 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2092 if (!enable) {
b1023571
KW		 2093 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2094 adev->gfx.gfx_ring[i].ready = false;
2095 }
5e78835a 2096 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 2097 udelay(50);
2098}
2099
2100static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2101{
2102 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2103 const struct gfx_firmware_header_v1_0 *ce_hdr;
2104 const struct gfx_firmware_header_v1_0 *me_hdr;
2105 const __le32 *fw_data;
2106 unsigned i, fw_size;
2107
2108 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2109 return -EINVAL;
2110
2111 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2112 adev->gfx.pfp_fw->data;
2113 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2114 adev->gfx.ce_fw->data;
2115 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2116 adev->gfx.me_fw->data;
2117
2118 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2119 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2120 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2121
2122 gfx_v9_0_cp_gfx_enable(adev, false);
2123
2124 /* PFP */
2125 fw_data = (const __le32 *)
2126 (adev->gfx.pfp_fw->data +
2127 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2128 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 2129 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 2130 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2131 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2132 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 2133
2134 /* CE */
2135 fw_data = (const __le32 *)
2136 (adev->gfx.ce_fw->data +
2137 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2138 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 2139 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 2140 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2141 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2142 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 2143
2144 /* ME */
2145 fw_data = (const __le32 *)
2146 (adev->gfx.me_fw->data +
2147 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2148 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 2149 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 2150 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2151 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2152 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 2153
2154 return 0;
2155}
2156
b1023571
KW		 2157static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2158{
2159 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2160 const struct cs_section_def *sect = NULL;
2161 const struct cs_extent_def *ext = NULL;
d5de797f 2162 int r, i, tmp;
b1023571
KW		 2163
2164 /* init the CP */
5e78835a
TSD		 2165 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2166 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 2167
2168 gfx_v9_0_cp_gfx_enable(adev, true);
2169
d5de797f 2170 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
b1023571
KW		 2171 if (r) {
2172 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2173 return r;
2174 }
2175
2176 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2177 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2178
2179 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2180 amdgpu_ring_write(ring, 0x80000000);
2181 amdgpu_ring_write(ring, 0x80000000);
2182
2183 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2184 for (ext = sect->section; ext->extent != NULL; ++ext) {
2185 if (sect->id == SECT_CONTEXT) {
2186 amdgpu_ring_write(ring,
2187 PACKET3(PACKET3_SET_CONTEXT_REG,
2188 ext->reg_count));
2189 amdgpu_ring_write(ring,
2190 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2191 for (i = 0; i < ext->reg_count; i++)
2192 amdgpu_ring_write(ring, ext->extent[i]);
2193 }
2194 }
2195 }
2196
2197 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2198 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2199
2200 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2201 amdgpu_ring_write(ring, 0);
2202
2203 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2204 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2205 amdgpu_ring_write(ring, 0x8000);
2206 amdgpu_ring_write(ring, 0x8000);
2207
d5de797f
KW		 2208 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2209 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2210 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2211 amdgpu_ring_write(ring, tmp);
2212 amdgpu_ring_write(ring, 0);
2213
b1023571
KW		 2214 amdgpu_ring_commit(ring);
2215
2216 return 0;
2217}
2218
2219static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2220{
2221 struct amdgpu_ring *ring;
2222 u32 tmp;
2223 u32 rb_bufsz;
3fc08b61 2224 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 2225
2226 /* Set the write pointer delay */
5e78835a 2227 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 2228
2229 /* set the RB to use vmid 0 */
5e78835a 2230 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 2231
2232 /* Set ring buffer size */
2233 ring = &adev->gfx.gfx_ring[0];
2234 rb_bufsz = order_base_2(ring->ring_size / 8);
2235 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2236 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2237#ifdef __BIG_ENDIAN
2238 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2239#endif
5e78835a 2240 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2241
2242 /* Initialize the ring buffer's write pointers */
2243 ring->wptr = 0;
5e78835a
TSD		 2244 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2245 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2246
2247 /* set the wb address wether it's enabled or not */
2248 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 2249 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2250 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 2251
3fc08b61 2252 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 2253 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2254 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 2255
b1023571 2256 mdelay(1);
5e78835a 2257 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2258
2259 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 2260 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2261 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 2262
5e78835a 2263 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 2264 if (ring->use_doorbell) {
2265 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2266 DOORBELL_OFFSET, ring->doorbell_index);
2267 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2268 DOORBELL_EN, 1);
2269 } else {
2270 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2271 }
5e78835a 2272 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 2273
2274 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2275 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 2276 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 2277
5e78835a 2278 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 2279 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2280
2281
2282 /* start the ring */
2283 gfx_v9_0_cp_gfx_start(adev);
2284 ring->ready = true;
2285
2286 return 0;
2287}
2288
2289static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2290{
2291 int i;
2292
2293 if (enable) {
5e78835a 2294 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 2295 } else {
5e78835a 2296 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 2297 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2298 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2299 adev->gfx.compute_ring[i].ready = false;
ac104e99 2300 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 2301 }
2302 udelay(50);
2303}
2304
b1023571
KW		 2305static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2306{
2307 const struct gfx_firmware_header_v1_0 *mec_hdr;
2308 const __le32 *fw_data;
2309 unsigned i;
2310 u32 tmp;
2311
2312 if (!adev->gfx.mec_fw)
2313 return -EINVAL;
2314
2315 gfx_v9_0_cp_compute_enable(adev, false);
2316
2317 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2318 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2319
2320 fw_data = (const __le32 *)
2321 (adev->gfx.mec_fw->data +
2322 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2323 tmp = 0;
2324 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2325 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 2326 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 2327
5e78835a 2328 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 2329 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 2330 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571 2331 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
eaa05d52 2332
b1023571 2333 /* MEC1 */
5e78835a 2334 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2335 mec_hdr->jt_offset);
2336 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 2337 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 2338 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2339
5e78835a 2340 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2341 adev->gfx.mec_fw_version);
2342 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2343
2344 return 0;
2345}
2346
464826d6
XY		 2347/* KIQ functions */
2348static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
b1023571 2349{
464826d6
XY		 2350 uint32_t tmp;
2351 struct amdgpu_device *adev = ring->adev;
b1023571 2352
464826d6 2353 /* tell RLC which is KIQ queue */
5e78835a 2354 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 2355 tmp &= 0xffffff00;
2356 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 2357 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2358 tmp |= 0x80;
5e78835a 2359 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2360}
b1023571 2361
0f1dfd52 2362static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
464826d6 2363{
bd3402ea 2364 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2fdde9fa 2365 uint32_t scratch, tmp = 0;
de65513a 2366 uint64_t queue_mask = 0;
2fdde9fa 2367 int r, i;
b1023571 2368
de65513a
AR		 2369 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2370 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2371 continue;
b1023571 2372
de65513a
AR		 2373 /* This situation may be hit in the future if a new HW
2374 * generation exposes more than 64 queues. If so, the
2375 * definition of queue_mask needs updating */
1d11ee89 2376 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
de65513a
AR		 2377 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2378 break;
b1023571 2379 }
b1023571 2380
de65513a
AR		 2381 queue_mask |= (1ull << i);
2382 }
b1023571 2383
2fdde9fa
AD		 2384 r = amdgpu_gfx_scratch_get(adev, &scratch);
2385 if (r) {
2386 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2387 return r;
b1023571 2388 }
2fdde9fa 2389 WREG32(scratch, 0xCAFEDEAD);
b1023571 2390
0f1dfd52 2391 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2fdde9fa
AD		 2392 if (r) {
2393 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2394 amdgpu_gfx_scratch_free(adev, scratch);
b1023571 2395 return r;
2fdde9fa 2396 }
b1023571 2397
0f1dfd52
AD		 2398 /* set resources */
2399 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2400 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2401 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
de65513a
AR		 2402 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2403 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
0f1dfd52
AD		 2404 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2405 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2406 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2407 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
bd3402ea
AD		 2408 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2409 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2410 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2411 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2412
2413 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2414 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2415 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2416 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2417 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2418 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2419 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2420 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2421 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2422 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2423 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2424 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2425 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2426 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2427 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2428 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2429 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2430 }
2fdde9fa
AD		 2431 /* write to scratch for completion */
2432 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2433 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2434 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
464826d6 2435 amdgpu_ring_commit(kiq_ring);
b1023571 2436
2fdde9fa
AD		 2437 for (i = 0; i < adev->usec_timeout; i++) {
2438 tmp = RREG32(scratch);
2439 if (tmp == 0xDEADBEEF)
2440 break;
2441 DRM_UDELAY(1);
2442 }
2443 if (i >= adev->usec_timeout) {
2444 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2445 scratch, tmp);
2446 r = -EINVAL;
2447 }
2448 amdgpu_gfx_scratch_free(adev, scratch);
464826d6 2449
2fdde9fa 2450 return r;
464826d6
XY		 2451}
2452
e322edc3 2453static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 2454{
33fb8698 2455 struct amdgpu_device *adev = ring->adev;
e322edc3 2456 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2457 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2458 uint32_t tmp;
2459
2460 mqd->header = 0xC0310800;
2461 mqd->compute_pipelinestat_enable = 0x00000001;
2462 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2463 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2464 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2465 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2466 mqd->compute_misc_reserved = 0x00000003;
2467
ffe6d881
AD		 2468 mqd->dynamic_cu_mask_addr_lo =
2469 lower_32_bits(ring->mqd_gpu_addr
2470 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2471 mqd->dynamic_cu_mask_addr_hi =
2472 upper_32_bits(ring->mqd_gpu_addr
2473 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2474
d72f2f46 2475 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 2476 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2477 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2478
2479 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2480 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6 2481 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
268cb4c7 2482 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
464826d6
XY		 2483
2484 mqd->cp_hqd_eop_control = tmp;
2485
2486 /* enable doorbell? */
5e78835a 2487 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2488
2489 if (ring->use_doorbell) {
2490 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2491 DOORBELL_OFFSET, ring->doorbell_index);
2492 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2493 DOORBELL_EN, 1);
2494 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2495 DOORBELL_SOURCE, 0);
2496 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2497 DOORBELL_HIT, 0);
78888cff 2498 } else {
464826d6
XY		 2499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2500 DOORBELL_EN, 0);
78888cff 2501 }
464826d6
XY		 2502
2503 mqd->cp_hqd_pq_doorbell_control = tmp;
2504
2505 /* disable the queue if it's active */
2506 ring->wptr = 0;
2507 mqd->cp_hqd_dequeue_request = 0;
2508 mqd->cp_hqd_pq_rptr = 0;
2509 mqd->cp_hqd_pq_wptr_lo = 0;
2510 mqd->cp_hqd_pq_wptr_hi = 0;
2511
2512 /* set the pointer to the MQD */
33fb8698
AD		 2513 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2514 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 2515
2516 /* set MQD vmid to 0 */
5e78835a 2517 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 2518 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2519 mqd->cp_mqd_control = tmp;
2520
2521 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2522 hqd_gpu_addr = ring->gpu_addr >> 8;
2523 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2524 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2525
2526 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2527 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 2528 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2529 (order_base_2(ring->ring_size / 4) - 1));
2530 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2531 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2532#ifdef __BIG_ENDIAN
2533 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2534#endif
2535 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2536 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2538 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2539 mqd->cp_hqd_pq_control = tmp;
2540
2541 /* set the wb address whether it's enabled or not */
2542 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2543 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2544 mqd->cp_hqd_pq_rptr_report_addr_hi =
2545 upper_32_bits(wb_gpu_addr) & 0xffff;
2546
2547 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2548 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2549 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2550 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2551
2552 tmp = 0;
2553 /* enable the doorbell if requested */
2554 if (ring->use_doorbell) {
5e78835a 2555 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2556 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2557 DOORBELL_OFFSET, ring->doorbell_index);
2558
2559 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2560 DOORBELL_EN, 1);
2561 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2562 DOORBELL_SOURCE, 0);
2563 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2564 DOORBELL_HIT, 0);
2565 }
2566
2567 mqd->cp_hqd_pq_doorbell_control = tmp;
2568
2569 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2570 ring->wptr = 0;
0274a9c5 2571 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 2572
2573 /* set the vmid for the queue */
2574 mqd->cp_hqd_vmid = 0;
2575
0274a9c5 2576 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 2577 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2578 mqd->cp_hqd_persistent_state = tmp;
2579
fca4ce69
AD		 2580 /* set MIN_IB_AVAIL_SIZE */
2581 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2582 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2583 mqd->cp_hqd_ib_control = tmp;
2584
464826d6
XY		 2585 /* activate the queue */
2586 mqd->cp_hqd_active = 1;
2587
2588 return 0;
2589}
2590
e322edc3 2591static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2592{
33fb8698 2593 struct amdgpu_device *adev = ring->adev;
e322edc3 2594 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2595 int j;
2596
2597 /* disable wptr polling */
72edadd5 2598 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2599
5e78835a 2600 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2601 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2602 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2603 mqd->cp_hqd_eop_base_addr_hi);
2604
2605 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2606 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2607 mqd->cp_hqd_eop_control);
2608
2609 /* enable doorbell? */
5e78835a 2610 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2611 mqd->cp_hqd_pq_doorbell_control);
2612
2613 /* disable the queue if it's active */
5e78835a
TSD		 2614 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2615 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2616 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2617 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2618 break;
2619 udelay(1);
2620 }
5e78835a 2621 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2622 mqd->cp_hqd_dequeue_request);
5e78835a 2623 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2624 mqd->cp_hqd_pq_rptr);
5e78835a 2625 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2626 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2627 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2628 mqd->cp_hqd_pq_wptr_hi);
2629 }
2630
2631 /* set the pointer to the MQD */
5e78835a 2632 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2633 mqd->cp_mqd_base_addr_lo);
5e78835a 2634 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2635 mqd->cp_mqd_base_addr_hi);
2636
2637 /* set MQD vmid to 0 */
5e78835a 2638 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2639 mqd->cp_mqd_control);
2640
2641 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2642 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2643 mqd->cp_hqd_pq_base_lo);
5e78835a 2644 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2645 mqd->cp_hqd_pq_base_hi);
2646
2647 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2648 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2649 mqd->cp_hqd_pq_control);
2650
2651 /* set the wb address whether it's enabled or not */
5e78835a 2652 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2653 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2654 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2655 mqd->cp_hqd_pq_rptr_report_addr_hi);
2656
2657 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2658 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2659 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2660 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2661 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2662
2663 /* enable the doorbell if requested */
2664 if (ring->use_doorbell) {
5e78835a 2665 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2666 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2667 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2668 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2669 }
2670
5e78835a 2671 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2672 mqd->cp_hqd_pq_doorbell_control);
2673
2674 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2675 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2676 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2677 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2678 mqd->cp_hqd_pq_wptr_hi);
2679
2680 /* set the vmid for the queue */
5e78835a 2681 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2682
5e78835a 2683 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2684 mqd->cp_hqd_persistent_state);
2685
2686 /* activate the queue */
5e78835a 2687 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2688 mqd->cp_hqd_active);
2689
72edadd5
TSD		 2690 if (ring->use_doorbell)
2691 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2692
2693 return 0;
2694}
2695
e322edc3 2696static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2697{
2698 struct amdgpu_device *adev = ring->adev;
e322edc3 2699 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2700 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2701
898b7893 2702 gfx_v9_0_kiq_setting(ring);
464826d6 2703
3224a12b 2704 if (adev->in_sriov_reset) { /* for GPU_RESET case */
464826d6 2705 /* reset MQD to a clean status */
0ef376ca 2706 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2707 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2708
2709 /* reset ring buffer */
2710 ring->wptr = 0;
b98724db 2711 amdgpu_ring_clear_ring(ring);
464826d6 2712
898b7893
AD		 2713 mutex_lock(&adev->srbm_mutex);
2714 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2715 gfx_v9_0_kiq_init_register(ring);
2716 soc15_grbm_select(adev, 0, 0, 0, 0);
2717 mutex_unlock(&adev->srbm_mutex);
464826d6 2718 } else {
ffe6d881
AD		 2719 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2720 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2721 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
ba0c19f5
AD		 2722 mutex_lock(&adev->srbm_mutex);
2723 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2724 gfx_v9_0_mqd_init(ring);
2725 gfx_v9_0_kiq_init_register(ring);
2726 soc15_grbm_select(adev, 0, 0, 0, 0);
2727 mutex_unlock(&adev->srbm_mutex);
2728
2729 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2730 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
464826d6
XY		 2731 }
2732
0f1dfd52 2733 return 0;
898b7893
AD		 2734}
2735
2736static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2737{
2738 struct amdgpu_device *adev = ring->adev;
898b7893
AD		 2739 struct v9_mqd *mqd = ring->mqd_ptr;
2740 int mqd_idx = ring - &adev->gfx.compute_ring[0];
898b7893 2741
3224a12b 2742 if (!adev->in_sriov_reset && !adev->gfx.in_suspend) {
ffe6d881
AD		 2743 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2744 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2745 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
464826d6
XY		 2746 mutex_lock(&adev->srbm_mutex);
2747 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2748 gfx_v9_0_mqd_init(ring);
464826d6
XY		 2749 soc15_grbm_select(adev, 0, 0, 0, 0);
2750 mutex_unlock(&adev->srbm_mutex);
2751
898b7893 2752 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2753 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3224a12b 2754 } else if (adev->in_sriov_reset) { /* for GPU_RESET case */
464826d6 2755 /* reset MQD to a clean status */
898b7893 2756 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2757 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2758
2759 /* reset ring buffer */
2760 ring->wptr = 0;
898b7893 2761 amdgpu_ring_clear_ring(ring);
ba0c19f5
AD		 2762 } else {
2763 amdgpu_ring_clear_ring(ring);
464826d6
XY		 2764 }
2765
464826d6
XY		 2766 return 0;
2767}
2768
2769static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2770{
2771 struct amdgpu_ring *ring = NULL;
2772 int r = 0, i;
2773
2774 gfx_v9_0_cp_compute_enable(adev, true);
2775
2776 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2777
2778 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2779 if (unlikely(r != 0))
2780 goto done;
2781
2782 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2783 if (!r) {
e322edc3 2784 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2785 amdgpu_bo_kunmap(ring->mqd_obj);
2786 ring->mqd_ptr = NULL;
464826d6 2787 }
e1d53aa8
AD		 2788 amdgpu_bo_unreserve(ring->mqd_obj);
2789 if (r)
2790 goto done;
464826d6
XY		 2791
2792 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2793 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2794
2795 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2796 if (unlikely(r != 0))
2797 goto done;
2798 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2799 if (!r) {
898b7893 2800 r = gfx_v9_0_kcq_init_queue(ring);
464826d6
XY		 2801 amdgpu_bo_kunmap(ring->mqd_obj);
2802 ring->mqd_ptr = NULL;
464826d6 2803 }
e1d53aa8
AD		 2804 amdgpu_bo_unreserve(ring->mqd_obj);
2805 if (r)
2806 goto done;
464826d6
XY		 2807 }
2808
0f1dfd52 2809 r = gfx_v9_0_kiq_kcq_enable(adev);
e1d53aa8
AD		 2810done:
2811 return r;
464826d6
XY		 2812}
2813
b1023571
KW		 2814static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2815{
bd3402ea 2816 int r, i;
b1023571
KW		 2817 struct amdgpu_ring *ring;
2818
2819 if (!(adev->flags & AMD_IS_APU))
2820 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2821
2822 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2823 /* legacy firmware loading */
2824 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2825 if (r)
2826 return r;
2827
2828 r = gfx_v9_0_cp_compute_load_microcode(adev);
2829 if (r)
2830 return r;
2831 }
2832
2833 r = gfx_v9_0_cp_gfx_resume(adev);
2834 if (r)
2835 return r;
2836
e30a5223 2837 r = gfx_v9_0_kiq_resume(adev);
b1023571
KW		 2838 if (r)
2839 return r;
2840
2841 ring = &adev->gfx.gfx_ring[0];
2842 r = amdgpu_ring_test_ring(ring);
2843 if (r) {
2844 ring->ready = false;
2845 return r;
2846 }
e30a5223
AD		 2847
2848 ring = &adev->gfx.kiq.ring;
2849 ring->ready = true;
2850 r = amdgpu_ring_test_ring(ring);
2851 if (r)
2852 ring->ready = false;
2853
b1023571
KW		 2854 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2855 ring = &adev->gfx.compute_ring[i];
2856
2857 ring->ready = true;
2858 r = amdgpu_ring_test_ring(ring);
2859 if (r)
2860 ring->ready = false;
2861 }
2862
2863 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2864
2865 return 0;
2866}
2867
2868static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2869{
2870 gfx_v9_0_cp_gfx_enable(adev, enable);
2871 gfx_v9_0_cp_compute_enable(adev, enable);
2872}
2873
2874static int gfx_v9_0_hw_init(void *handle)
2875{
2876 int r;
2877 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2878
2879 gfx_v9_0_init_golden_registers(adev);
2880
2881 gfx_v9_0_gpu_init(adev);
2882
2883 r = gfx_v9_0_rlc_resume(adev);
2884 if (r)
2885 return r;
2886
2887 r = gfx_v9_0_cp_resume(adev);
2888 if (r)
2889 return r;
2890
2891 r = gfx_v9_0_ngg_en(adev);
2892 if (r)
2893 return r;
2894
2895 return r;
2896}
2897
85f95ad6
ML		 2898static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
2899{
2900 struct amdgpu_device *adev = kiq_ring->adev;
2901 uint32_t scratch, tmp = 0;
2902 int r, i;
2903
2904 r = amdgpu_gfx_scratch_get(adev, &scratch);
2905 if (r) {
2906 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2907 return r;
2908 }
2909 WREG32(scratch, 0xCAFEDEAD);
2910
2911 r = amdgpu_ring_alloc(kiq_ring, 10);
2912 if (r) {
2913 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2914 amdgpu_gfx_scratch_free(adev, scratch);
2915 return r;
2916 }
2917
2918 /* unmap queues */
2919 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
2920 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2921 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
2922 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
2923 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
2924 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
2925 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
2926 amdgpu_ring_write(kiq_ring, 0);
2927 amdgpu_ring_write(kiq_ring, 0);
2928 amdgpu_ring_write(kiq_ring, 0);
2929 /* write to scratch for completion */
2930 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2931 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2932 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2933 amdgpu_ring_commit(kiq_ring);
2934
2935 for (i = 0; i < adev->usec_timeout; i++) {
2936 tmp = RREG32(scratch);
2937 if (tmp == 0xDEADBEEF)
2938 break;
2939 DRM_UDELAY(1);
2940 }
2941 if (i >= adev->usec_timeout) {
2942 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
2943 r = -EINVAL;
2944 }
2945 amdgpu_gfx_scratch_free(adev, scratch);
2946 return r;
2947}
2948
2949
b1023571
KW		 2950static int gfx_v9_0_hw_fini(void *handle)
2951{
2952 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
85f95ad6 2953 int i;
b1023571
KW		 2954
2955 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2956 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
85f95ad6
ML		 2957
2958 /* disable KCQ to avoid CPC touch memory not valid anymore */
2959 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2960 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
2961
464826d6
XY		 2962 if (amdgpu_sriov_vf(adev)) {
2963 pr_debug("For SRIOV client, shouldn't do anything.\n");
2964 return 0;
2965 }
b1023571
KW		 2966 gfx_v9_0_cp_enable(adev, false);
2967 gfx_v9_0_rlc_stop(adev);
b1023571
KW		 2968
2969 return 0;
2970}
2971
2972static int gfx_v9_0_suspend(void *handle)
2973{
2974 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2975
e30a5223 2976 adev->gfx.in_suspend = true;
b1023571
KW		 2977 return gfx_v9_0_hw_fini(adev);
2978}
2979
2980static int gfx_v9_0_resume(void *handle)
2981{
2982 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e30a5223 2983 int r;
b1023571 2984
e30a5223
AD		 2985 r = gfx_v9_0_hw_init(adev);
2986 adev->gfx.in_suspend = false;
2987 return r;
b1023571
KW		 2988}
2989
2990static bool gfx_v9_0_is_idle(void *handle)
2991{
2992 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2993
5e78835a 2994 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 2995 GRBM_STATUS, GUI_ACTIVE))
2996 return false;
2997 else
2998 return true;
2999}
3000
3001static int gfx_v9_0_wait_for_idle(void *handle)
3002{
3003 unsigned i;
b1023571
KW		 3004 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3005
3006 for (i = 0; i < adev->usec_timeout; i++) {
2b9bdfa7 3007 if (gfx_v9_0_is_idle(handle))
b1023571
KW		 3008 return 0;
3009 udelay(1);
3010 }
3011 return -ETIMEDOUT;
3012}
3013
b1023571
KW		 3014static int gfx_v9_0_soft_reset(void *handle)
3015{
3016 u32 grbm_soft_reset = 0;
3017 u32 tmp;
3018 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3019
3020 /* GRBM_STATUS */
5e78835a 3021 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 3022 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3023 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3024 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3025 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3026 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3027 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3028 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3029 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3030 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3031 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3032 }
3033
3034 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3035 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3036 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3037 }
3038
3039 /* GRBM_STATUS2 */
5e78835a 3040 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 3041 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3042 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3043 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3044
3045
75bac5c6 3046 if (grbm_soft_reset) {
b1023571
KW		 3047 /* stop the rlc */
3048 gfx_v9_0_rlc_stop(adev);
3049
3050 /* Disable GFX parsing/prefetching */
3051 gfx_v9_0_cp_gfx_enable(adev, false);
3052
3053 /* Disable MEC parsing/prefetching */
3054 gfx_v9_0_cp_compute_enable(adev, false);
3055
3056 if (grbm_soft_reset) {
5e78835a 3057 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3058 tmp |= grbm_soft_reset;
3059 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 3060 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3061 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3062
3063 udelay(50);
3064
3065 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 3066 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3067 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3068 }
3069
3070 /* Wait a little for things to settle down */
3071 udelay(50);
b1023571
KW		 3072 }
3073 return 0;
3074}
3075
3076static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3077{
3078 uint64_t clock;
3079
3080 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 3081 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3082 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3083 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 3084 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3085 return clock;
3086}
3087
3088static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3089 uint32_t vmid,
3090 uint32_t gds_base, uint32_t gds_size,
3091 uint32_t gws_base, uint32_t gws_size,
3092 uint32_t oa_base, uint32_t oa_size)
3093{
3094 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3095 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3096
3097 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3098 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3099
3100 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3101 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3102
3103 /* GDS Base */
3104 gfx_v9_0_write_data_to_reg(ring, 0, false,
3105 amdgpu_gds_reg_offset[vmid].mem_base,
3106 gds_base);
3107
3108 /* GDS Size */
3109 gfx_v9_0_write_data_to_reg(ring, 0, false,
3110 amdgpu_gds_reg_offset[vmid].mem_size,
3111 gds_size);
3112
3113 /* GWS */
3114 gfx_v9_0_write_data_to_reg(ring, 0, false,
3115 amdgpu_gds_reg_offset[vmid].gws,
3116 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3117
3118 /* OA */
3119 gfx_v9_0_write_data_to_reg(ring, 0, false,
3120 amdgpu_gds_reg_offset[vmid].oa,
3121 (1 << (oa_size + oa_base)) - (1 << oa_base));
3122}
3123
3124static int gfx_v9_0_early_init(void *handle)
3125{
3126 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3127
3128 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
78c16834 3129 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
b1023571
KW		 3130 gfx_v9_0_set_ring_funcs(adev);
3131 gfx_v9_0_set_irq_funcs(adev);
3132 gfx_v9_0_set_gds_init(adev);
3133 gfx_v9_0_set_rlc_funcs(adev);
3134
3135 return 0;
3136}
3137
3138static int gfx_v9_0_late_init(void *handle)
3139{
3140 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3141 int r;
3142
3143 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3144 if (r)
3145 return r;
3146
3147 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3148 if (r)
3149 return r;
3150
3151 return 0;
3152}
3153
3154static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3155{
3156 uint32_t rlc_setting, data;
3157 unsigned i;
3158
3159 if (adev->gfx.rlc.in_safe_mode)
3160 return;
3161
3162 /* if RLC is not enabled, do nothing */
5e78835a 3163 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3164 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3165 return;
3166
3167 if (adev->cg_flags &
3168 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3169 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3170 data = RLC_SAFE_MODE__CMD_MASK;
3171 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 3172 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3173
3174 /* wait for RLC_SAFE_MODE */
3175 for (i = 0; i < adev->usec_timeout; i++) {
3176 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3177 break;
3178 udelay(1);
3179 }
3180 adev->gfx.rlc.in_safe_mode = true;
3181 }
3182}
3183
3184static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3185{
3186 uint32_t rlc_setting, data;
3187
3188 if (!adev->gfx.rlc.in_safe_mode)
3189 return;
3190
3191 /* if RLC is not enabled, do nothing */
5e78835a 3192 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3193 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3194 return;
3195
3196 if (adev->cg_flags &
3197 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3198 /*
3199 * Try to exit safe mode only if it is already in safe
3200 * mode.
3201 */
3202 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 3203 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3204 adev->gfx.rlc.in_safe_mode = false;
3205 }
3206}
3207
197f95c8
HZ		 3208static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3209 bool enable)
3210{
3211 /* TODO: double check if we need to perform under safe mdoe */
3212 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3213
3214 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3215 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3216 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3217 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3218 } else {
3219 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3220 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3221 }
3222
3223 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3224}
3225
18924c71
HZ		 3226static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3227 bool enable)
3228{
3229 /* TODO: double check if we need to perform under safe mode */
3230 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3231
3232 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3233 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3234 else
3235 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3236
3237 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3238 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3239 else
3240 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3241
3242 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3243}
3244
b1023571
KW		 3245static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3246 bool enable)
3247{
3248 uint32_t data, def;
3249
3250 /* It is disabled by HW by default */
3251 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3252 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 3253 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3254 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3255 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3256 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3257 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3258
3259 /* only for Vega10 & Raven1 */
3260 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3261
3262 if (def != data)
5e78835a 3263 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3264
3265 /* MGLS is a global flag to control all MGLS in GFX */
3266 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3267 /* 2 - RLC memory Light sleep */
3268 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 3269 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3270 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3271 if (def != data)
5e78835a 3272 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3273 }
3274 /* 3 - CP memory Light sleep */
3275 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 3276 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3277 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3278 if (def != data)
5e78835a 3279 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3280 }
3281 }
3282 } else {
3283 /* 1 - MGCG_OVERRIDE */
5e78835a 3284 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3285 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3286 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3287 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3288 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3289 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3290 if (def != data)
5e78835a 3291 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3292
3293 /* 2 - disable MGLS in RLC */
5e78835a 3294 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3295 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3296 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 3297 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3298 }
3299
3300 /* 3 - disable MGLS in CP */
5e78835a 3301 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3302 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3303 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 3304 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3305 }
3306 }
3307}
3308
3309static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3310 bool enable)
3311{
3312 uint32_t data, def;
3313
3314 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3315
3316 /* Enable 3D CGCG/CGLS */
3317 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3318 /* write cmd to clear cgcg/cgls ov */
5e78835a 3319 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3320 /* unset CGCG override */
3321 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3322 /* update CGCG and CGLS override bits */
3323 if (def != data)
5e78835a 3324 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 3325 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 3326 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3327 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3328 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3329 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3330 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3331 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3332 if (def != data)
5e78835a 3333 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3334
3335 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3336 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3337 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3338 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3339 if (def != data)
5e78835a 3340 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 3341 } else {
3342 /* Disable CGCG/CGLS */
5e78835a 3343 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3344 /* disable cgcg, cgls should be disabled */
3345 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3346 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3347 /* disable cgcg and cgls in FSM */
3348 if (def != data)
5e78835a 3349 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3350 }
3351
3352 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3353}
3354
3355static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3356 bool enable)
3357{
3358 uint32_t def, data;
3359
3360 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3361
3362 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 3363 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3364 /* unset CGCG override */
3365 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3366 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3367 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3368 else
3369 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3370 /* update CGCG and CGLS override bits */
3371 if (def != data)
5e78835a 3372 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3373
3374 /* enable cgcg FSM(0x0020003F) */
5e78835a 3375 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3376 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3377 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3378 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3379 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3380 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3381 if (def != data)
5e78835a 3382 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3383
3384 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3385 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3386 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3387 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3388 if (def != data)
5e78835a 3389 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 3390 } else {
5e78835a 3391 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3392 /* reset CGCG/CGLS bits */
3393 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3394 /* disable cgcg and cgls in FSM */
3395 if (def != data)
5e78835a 3396 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3397 }
3398
3399 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3400}
3401
3402static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3403 bool enable)
3404{
3405 if (enable) {
3406 /* CGCG/CGLS should be enabled after MGCG/MGLS
3407 * === MGCG + MGLS ===
3408 */
3409 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3410 /* === CGCG /CGLS for GFX 3D Only === */
3411 gfx_v9_0_update_3d_clock_gating(adev, enable);
3412 /* === CGCG + CGLS === */
3413 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3414 } else {
3415 /* CGCG/CGLS should be disabled before MGCG/MGLS
3416 * === CGCG + CGLS ===
3417 */
3418 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3419 /* === CGCG /CGLS for GFX 3D Only === */
3420 gfx_v9_0_update_3d_clock_gating(adev, enable);
3421 /* === MGCG + MGLS === */
3422 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3423 }
3424 return 0;
3425}
3426
3427static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3428 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3429 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3430};
3431
3432static int gfx_v9_0_set_powergating_state(void *handle,
3433 enum amd_powergating_state state)
3434{
5897c99e 3435 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197f95c8 3436 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
5897c99e
HZ		 3437
3438 switch (adev->asic_type) {
3439 case CHIP_RAVEN:
3440 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3441 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3442 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3443 } else {
3444 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3445 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3446 }
3447
3448 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3449 gfx_v9_0_enable_cp_power_gating(adev, true);
3450 else
3451 gfx_v9_0_enable_cp_power_gating(adev, false);
197f95c8
HZ		 3452
3453 /* update gfx cgpg state */
3454 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
18924c71
HZ		 3455
3456 /* update mgcg state */
3457 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5897c99e
HZ		 3458 break;
3459 default:
3460 break;
3461 }
3462
b1023571
KW		 3463 return 0;
3464}
3465
3466static int gfx_v9_0_set_clockgating_state(void *handle,
3467 enum amd_clockgating_state state)
3468{
3469 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3470
fb82afab
XY		 3471 if (amdgpu_sriov_vf(adev))
3472 return 0;
3473
b1023571
KW		 3474 switch (adev->asic_type) {
3475 case CHIP_VEGA10:
a4dc61f5 3476 case CHIP_RAVEN:
b1023571
KW		 3477 gfx_v9_0_update_gfx_clock_gating(adev,
3478 state == AMD_CG_STATE_GATE ? true : false);
3479 break;
3480 default:
3481 break;
3482 }
3483 return 0;
3484}
3485
12ad27fa
HR		 3486static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3487{
3488 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3489 int data;
3490
3491 if (amdgpu_sriov_vf(adev))
3492 *flags = 0;
3493
3494 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 3495 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 3496 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3497 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3498
3499 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 3500 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 3501 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3502 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3503
3504 /* AMD_CG_SUPPORT_GFX_CGLS */
3505 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3506 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3507
3508 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 3509 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 3510 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3511 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3512
3513 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 3514 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 3515 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3516 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3517
3518 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 3519 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 3520 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3521 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3522
3523 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3524 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3525 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3526}
3527
b1023571
KW		 3528static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3529{
3530 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3531}
3532
3533static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3534{
3535 struct amdgpu_device *adev = ring->adev;
3536 u64 wptr;
3537
3538 /* XXX check if swapping is necessary on BE */
3539 if (ring->use_doorbell) {
3540 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3541 } else {
5e78835a
TSD		 3542 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3543 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 3544 }
3545
3546 return wptr;
3547}
3548
3549static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3550{
3551 struct amdgpu_device *adev = ring->adev;
3552
3553 if (ring->use_doorbell) {
3554 /* XXX check if swapping is necessary on BE */
3555 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3556 WDOORBELL64(ring->doorbell_index, ring->wptr);
3557 } else {
5e78835a
TSD		 3558 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3559 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 3560 }
3561}
3562
3563static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3564{
3565 u32 ref_and_mask, reg_mem_engine;
3566 struct nbio_hdp_flush_reg *nbio_hf_reg;
3567
29c3035f
AD		 3568 if (ring->adev->flags & AMD_IS_APU)
3569 nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
3570 else
b1023571
KW		 3571 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3572
3573 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3574 switch (ring->me) {
3575 case 1:
3576 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3577 break;
3578 case 2:
3579 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3580 break;
3581 default:
3582 return;
3583 }
3584 reg_mem_engine = 0;
3585 } else {
3586 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3587 reg_mem_engine = 1; /* pfp */
3588 }
3589
3590 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3591 nbio_hf_reg->hdp_flush_req_offset,
3592 nbio_hf_reg->hdp_flush_done_offset,
3593 ref_and_mask, ref_and_mask, 0x20);
3594}
3595
3596static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3597{
3598 gfx_v9_0_write_data_to_reg(ring, 0, true,
6e2e216f 3599 SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
b1023571
KW		 3600}
3601
3602static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3603 struct amdgpu_ib *ib,
3604 unsigned vm_id, bool ctx_switch)
3605{
eaa05d52 3606 u32 header, control = 0;
b1023571 3607
eaa05d52
ML		 3608 if (ib->flags & AMDGPU_IB_FLAG_CE)
3609 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3610 else
3611 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
b1023571 3612
eaa05d52 3613 control |= ib->length_dw | (vm_id << 24);
b1023571 3614
635e7132 3615 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
eaa05d52 3616 control |= INDIRECT_BUFFER_PRE_ENB(1);
9ccd52eb 3617
635e7132
ML		 3618 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3619 gfx_v9_0_ring_emit_de_meta(ring);
3620 }
3621
eaa05d52
ML		 3622 amdgpu_ring_write(ring, header);
3623BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3624 amdgpu_ring_write(ring,
b1023571 3625#ifdef __BIG_ENDIAN
eaa05d52 3626 (2 << 0) |
b1023571 3627#endif
eaa05d52
ML		 3628 lower_32_bits(ib->gpu_addr));
3629 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3630 amdgpu_ring_write(ring, control);
b1023571
KW		 3631}
3632
b1023571
KW		 3633static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3634 struct amdgpu_ib *ib,
3635 unsigned vm_id, bool ctx_switch)
3636{
3637 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3638
3639 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3640 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3641 amdgpu_ring_write(ring,
3642#ifdef __BIG_ENDIAN
3643 (2 << 0) |
3644#endif
3645 lower_32_bits(ib->gpu_addr));
3646 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3647 amdgpu_ring_write(ring, control);
3648}
3649
3650static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3651 u64 seq, unsigned flags)
3652{
3653 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3654 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3655
3656 /* RELEASE_MEM - flush caches, send int */
3657 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3658 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3659 EOP_TC_ACTION_EN |
3660 EOP_TC_WB_ACTION_EN |
3661 EOP_TC_MD_ACTION_EN |
3662 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3663 EVENT_INDEX(5)));
3664 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3665
3666 /*
3667 * the address should be Qword aligned if 64bit write, Dword
3668 * aligned if only send 32bit data low (discard data high)
3669 */
3670 if (write64bit)
3671 BUG_ON(addr & 0x7);
3672 else
3673 BUG_ON(addr & 0x3);
3674 amdgpu_ring_write(ring, lower_32_bits(addr));
3675 amdgpu_ring_write(ring, upper_32_bits(addr));
3676 amdgpu_ring_write(ring, lower_32_bits(seq));
3677 amdgpu_ring_write(ring, upper_32_bits(seq));
3678 amdgpu_ring_write(ring, 0);
3679}
3680
3681static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3682{
3683 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3684 uint32_t seq = ring->fence_drv.sync_seq;
3685 uint64_t addr = ring->fence_drv.gpu_addr;
3686
3687 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3688 lower_32_bits(addr), upper_32_bits(addr),
3689 seq, 0xffffffff, 4);
3690}
3691
3692static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3693 unsigned vm_id, uint64_t pd_addr)
3694{
2e819849 3695 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
b1023571 3696 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 3697 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 3698 unsigned eng = ring->vm_inv_eng;
b1023571 3699
b1166325
CK		 3700 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3701 pd_addr |= AMDGPU_PTE_VALID;
b1023571 3702
2e819849
CK		 3703 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3704 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3705 lower_32_bits(pd_addr));
b1023571 3706
2e819849
CK		 3707 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3708 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3709 upper_32_bits(pd_addr));
b1023571 3710
2e819849
CK		 3711 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3712 hub->vm_inv_eng0_req + eng, req);
b1023571 3713
2e819849
CK		 3714 /* wait for the invalidate to complete */
3715 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3716 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
b1023571
KW		 3717
3718 /* compute doesn't have PFP */
3719 if (usepfp) {
3720 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3721 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3722 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3723 }
3724}
3725
3726static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3727{
3728 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3729}
3730
3731static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3732{
3733 u64 wptr;
3734
3735 /* XXX check if swapping is necessary on BE */
3736 if (ring->use_doorbell)
3737 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3738 else
3739 BUG();
3740 return wptr;
3741}
3742
3743static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3744{
3745 struct amdgpu_device *adev = ring->adev;
3746
3747 /* XXX check if swapping is necessary on BE */
3748 if (ring->use_doorbell) {
3749 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3750 WDOORBELL64(ring->doorbell_index, ring->wptr);
3751 } else{
3752 BUG(); /* only DOORBELL method supported on gfx9 now */
3753 }
3754}
3755
aa6faa44
XY		 3756static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3757 u64 seq, unsigned int flags)
3758{
3759 /* we only allocate 32bit for each seq wb address */
3760 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3761
3762 /* write fence seq to the "addr" */
3763 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3764 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3765 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3766 amdgpu_ring_write(ring, lower_32_bits(addr));
3767 amdgpu_ring_write(ring, upper_32_bits(addr));
3768 amdgpu_ring_write(ring, lower_32_bits(seq));
3769
3770 if (flags & AMDGPU_FENCE_FLAG_INT) {
3771 /* set register to trigger INT */
3772 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3773 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3774 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3775 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3776 amdgpu_ring_write(ring, 0);
3777 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3778 }
3779}
3780
b1023571
KW		 3781static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3782{
3783 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3784 amdgpu_ring_write(ring, 0);
3785}
3786
cca02cd3
XY		 3787static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3788{
3789 static struct v9_ce_ib_state ce_payload = {0};
3790 uint64_t csa_addr;
3791 int cnt;
3792
3793 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3794 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3795
3796 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3797 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3798 WRITE_DATA_DST_SEL(8) |
3799 WR_CONFIRM) |
3800 WRITE_DATA_CACHE_POLICY(0));
3801 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3802 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3803 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3804}
3805
3806static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3807{
3808 static struct v9_de_ib_state de_payload = {0};
3809 uint64_t csa_addr, gds_addr;
3810 int cnt;
3811
3812 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3813 gds_addr = csa_addr + 4096;
3814 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3815 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3816
3817 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3818 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3819 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3820 WRITE_DATA_DST_SEL(8) |
3821 WR_CONFIRM) |
3822 WRITE_DATA_CACHE_POLICY(0));
3823 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3824 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3825 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3826}
3827
2ea6ab27
ML		 3828static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3829{
3830 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3831 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3832}
3833
b1023571
KW		 3834static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3835{
3836 uint32_t dw2 = 0;
3837
cca02cd3
XY		 3838 if (amdgpu_sriov_vf(ring->adev))
3839 gfx_v9_0_ring_emit_ce_meta(ring);
3840
2ea6ab27
ML		 3841 gfx_v9_0_ring_emit_tmz(ring, true);
3842
b1023571
KW		 3843 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3844 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3845 /* set load_global_config & load_global_uconfig */
3846 dw2 |= 0x8001;
3847 /* set load_cs_sh_regs */
3848 dw2 |= 0x01000000;
3849 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3850 dw2 |= 0x10002;
3851
3852 /* set load_ce_ram if preamble presented */
3853 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3854 dw2 |= 0x10000000;
3855 } else {
3856 /* still load_ce_ram if this is the first time preamble presented
3857 * although there is no context switch happens.
3858 */
3859 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3860 dw2 |= 0x10000000;
3861 }
3862
3863 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3864 amdgpu_ring_write(ring, dw2);
3865 amdgpu_ring_write(ring, 0);
3866}
3867
9a5e02b5
ML		 3868static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3869{
3870 unsigned ret;
3871 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3872 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3873 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3874 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3875 ret = ring->wptr & ring->buf_mask;
3876 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3877 return ret;
3878}
3879
3880static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3881{
3882 unsigned cur;
3883 BUG_ON(offset > ring->buf_mask);
3884 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3885
3886 cur = (ring->wptr & ring->buf_mask) - 1;
3887 if (likely(cur > offset))
3888 ring->ring[offset] = cur - offset;
3889 else
3890 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3891}
3892
aa6faa44
XY		 3893static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3894{
3895 struct amdgpu_device *adev = ring->adev;
3896
3897 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3898 amdgpu_ring_write(ring, 0 | /* src: register*/
3899 (5 << 8) | /* dst: memory */
3900 (1 << 20)); /* write confirm */
3901 amdgpu_ring_write(ring, reg);
3902 amdgpu_ring_write(ring, 0);
3903 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3904 adev->virt.reg_val_offs * 4));
3905 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3906 adev->virt.reg_val_offs * 4));
3907}
3908
3909static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3910 uint32_t val)
3911{
3912 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3913 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3914 amdgpu_ring_write(ring, reg);
3915 amdgpu_ring_write(ring, 0);
3916 amdgpu_ring_write(ring, val);
3917}
3918
b1023571
KW		 3919static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3920 enum amdgpu_interrupt_state state)
3921{
b1023571
KW		 3922 switch (state) {
3923 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3924 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 3925 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3926 TIME_STAMP_INT_ENABLE,
3927 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3928 break;
3929 default:
3930 break;
3931 }
3932}
3933
3934static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3935 int me, int pipe,
3936 enum amdgpu_interrupt_state state)
3937{
3938 u32 mec_int_cntl, mec_int_cntl_reg;
3939
3940 /*
d0c55cdf
AD		 3941 * amdgpu controls only the first MEC. That's why this function only
3942 * handles the setting of interrupts for this specific MEC. All other
b1023571
KW		 3943 * pipes' interrupts are set by amdkfd.
3944 */
3945
3946 if (me == 1) {
3947 switch (pipe) {
3948 case 0:
3949 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3950 break;
d0c55cdf
AD		 3951 case 1:
3952 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
3953 break;
3954 case 2:
3955 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
3956 break;
3957 case 3:
3958 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
3959 break;
b1023571
KW		 3960 default:
3961 DRM_DEBUG("invalid pipe %d\n", pipe);
3962 return;
3963 }
3964 } else {
3965 DRM_DEBUG("invalid me %d\n", me);
3966 return;
3967 }
3968
3969 switch (state) {
3970 case AMDGPU_IRQ_STATE_DISABLE:
3971 mec_int_cntl = RREG32(mec_int_cntl_reg);
3972 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3973 TIME_STAMP_INT_ENABLE, 0);
3974 WREG32(mec_int_cntl_reg, mec_int_cntl);
3975 break;
3976 case AMDGPU_IRQ_STATE_ENABLE:
3977 mec_int_cntl = RREG32(mec_int_cntl_reg);
3978 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3979 TIME_STAMP_INT_ENABLE, 1);
3980 WREG32(mec_int_cntl_reg, mec_int_cntl);
3981 break;
3982 default:
3983 break;
3984 }
3985}
3986
3987static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3988 struct amdgpu_irq_src *source,
3989 unsigned type,
3990 enum amdgpu_interrupt_state state)
3991{
b1023571
KW		 3992 switch (state) {
3993 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3994 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 3995 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3996 PRIV_REG_INT_ENABLE,
3997 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3998 break;
3999 default:
4000 break;
4001 }
4002
4003 return 0;
4004}
4005
4006static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4007 struct amdgpu_irq_src *source,
4008 unsigned type,
4009 enum amdgpu_interrupt_state state)
4010{
b1023571
KW		 4011 switch (state) {
4012 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4013 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 4014 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4015 PRIV_INSTR_INT_ENABLE,
4016 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4017 default:
4018 break;
4019 }
4020
4021 return 0;
4022}
4023
4024static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4025 struct amdgpu_irq_src *src,
4026 unsigned type,
4027 enum amdgpu_interrupt_state state)
4028{
4029 switch (type) {
4030 case AMDGPU_CP_IRQ_GFX_EOP:
4031 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4032 break;
4033 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4034 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4035 break;
4036 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4037 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4038 break;
4039 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4040 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4041 break;
4042 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4043 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4044 break;
4045 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4046 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4047 break;
4048 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4049 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4050 break;
4051 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4052 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4053 break;
4054 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4055 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4056 break;
4057 default:
4058 break;
4059 }
4060 return 0;
4061}
4062
4063static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4064 struct amdgpu_irq_src *source,
4065 struct amdgpu_iv_entry *entry)
4066{
4067 int i;
4068 u8 me_id, pipe_id, queue_id;
4069 struct amdgpu_ring *ring;
4070
4071 DRM_DEBUG("IH: CP EOP\n");
4072 me_id = (entry->ring_id & 0x0c) >> 2;
4073 pipe_id = (entry->ring_id & 0x03) >> 0;
4074 queue_id = (entry->ring_id & 0x70) >> 4;
4075
4076 switch (me_id) {
4077 case 0:
4078 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4079 break;
4080 case 1:
4081 case 2:
4082 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4083 ring = &adev->gfx.compute_ring[i];
4084 /* Per-queue interrupt is supported for MEC starting from VI.
4085 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4086 */
4087 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4088 amdgpu_fence_process(ring);
4089 }
4090 break;
4091 }
4092 return 0;
4093}
4094
4095static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4096 struct amdgpu_irq_src *source,
4097 struct amdgpu_iv_entry *entry)
4098{
4099 DRM_ERROR("Illegal register access in command stream\n");
4100 schedule_work(&adev->reset_work);
4101 return 0;
4102}
4103
4104static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4105 struct amdgpu_irq_src *source,
4106 struct amdgpu_iv_entry *entry)
4107{
4108 DRM_ERROR("Illegal instruction in command stream\n");
4109 schedule_work(&adev->reset_work);
4110 return 0;
4111}
4112
97031e25
XY		 4113static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4114 struct amdgpu_irq_src *src,
4115 unsigned int type,
4116 enum amdgpu_interrupt_state state)
4117{
4118 uint32_t tmp, target;
1c4ecf48 4119 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4120
4121 if (ring->me == 1)
4122 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4123 else
4124 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4125 target += ring->pipe;
4126
4127 switch (type) {
4128 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4129 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 4130 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4131 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4132 GENERIC2_INT_ENABLE, 0);
5e78835a 4133 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4134
4135 tmp = RREG32(target);
4136 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4137 GENERIC2_INT_ENABLE, 0);
4138 WREG32(target, tmp);
4139 } else {
5e78835a 4140 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4141 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4142 GENERIC2_INT_ENABLE, 1);
5e78835a 4143 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4144
4145 tmp = RREG32(target);
4146 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4147 GENERIC2_INT_ENABLE, 1);
4148 WREG32(target, tmp);
4149 }
4150 break;
4151 default:
4152 BUG(); /* kiq only support GENERIC2_INT now */
4153 break;
4154 }
4155 return 0;
4156}
4157
4158static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4159 struct amdgpu_irq_src *source,
4160 struct amdgpu_iv_entry *entry)
4161{
4162 u8 me_id, pipe_id, queue_id;
1c4ecf48 4163 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4164
4165 me_id = (entry->ring_id & 0x0c) >> 2;
4166 pipe_id = (entry->ring_id & 0x03) >> 0;
4167 queue_id = (entry->ring_id & 0x70) >> 4;
4168 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4169 me_id, pipe_id, queue_id);
4170
4171 amdgpu_fence_process(ring);
4172 return 0;
4173}
4174
fa04b6ba 4175static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
b1023571
KW		 4176 .name = "gfx_v9_0",
4177 .early_init = gfx_v9_0_early_init,
4178 .late_init = gfx_v9_0_late_init,
4179 .sw_init = gfx_v9_0_sw_init,
4180 .sw_fini = gfx_v9_0_sw_fini,
4181 .hw_init = gfx_v9_0_hw_init,
4182 .hw_fini = gfx_v9_0_hw_fini,
4183 .suspend = gfx_v9_0_suspend,
4184 .resume = gfx_v9_0_resume,
4185 .is_idle = gfx_v9_0_is_idle,
4186 .wait_for_idle = gfx_v9_0_wait_for_idle,
4187 .soft_reset = gfx_v9_0_soft_reset,
4188 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4189 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 4190 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 4191};
4192
4193static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4194 .type = AMDGPU_RING_TYPE_GFX,
4195 .align_mask = 0xff,
4196 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4197 .support_64bit_ptrs = true,
0eeb68b3 4198 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4199 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4200 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4201 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 4202 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4203 5 + /* COND_EXEC */
4204 7 + /* PIPELINE_SYNC */
2e819849 4205 24 + /* VM_FLUSH */
e9d672b2
ML		 4206 8 + /* FENCE for VM_FLUSH */
4207 20 + /* GDS switch */
4208 4 + /* double SWITCH_BUFFER,
4209 the first COND_EXEC jump to the place just
4210 prior to this double SWITCH_BUFFER */
4211 5 + /* COND_EXEC */
4212 7 + /* HDP_flush */
4213 4 + /* VGT_flush */
4214 14 + /* CE_META */
4215 31 + /* DE_META */
4216 3 + /* CNTX_CTRL */
4217 5 + /* HDP_INVL */
4218 8 + 8 + /* FENCE x2 */
4219 2, /* SWITCH_BUFFER */
b1023571
KW		 4220 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4221 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4222 .emit_fence = gfx_v9_0_ring_emit_fence,
4223 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4224 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4225 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4226 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4227 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4228 .test_ring = gfx_v9_0_ring_test_ring,
4229 .test_ib = gfx_v9_0_ring_test_ib,
4230 .insert_nop = amdgpu_ring_insert_nop,
4231 .pad_ib = amdgpu_ring_generic_pad_ib,
4232 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4233 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 4234 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4235 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3b4d68e9 4236 .emit_tmz = gfx_v9_0_ring_emit_tmz,
b1023571
KW		 4237};
4238
4239static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4240 .type = AMDGPU_RING_TYPE_COMPUTE,
4241 .align_mask = 0xff,
4242 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4243 .support_64bit_ptrs = true,
0eeb68b3 4244 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4245 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4246 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4247 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4248 .emit_frame_size =
4249 20 + /* gfx_v9_0_ring_emit_gds_switch */
4250 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4251 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4252 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4253 24 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 4254 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4255 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4256 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4257 .emit_fence = gfx_v9_0_ring_emit_fence,
4258 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4259 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4260 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4261 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4262 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4263 .test_ring = gfx_v9_0_ring_test_ring,
4264 .test_ib = gfx_v9_0_ring_test_ib,
4265 .insert_nop = amdgpu_ring_insert_nop,
4266 .pad_ib = amdgpu_ring_generic_pad_ib,
4267};
4268
aa6faa44
XY		 4269static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4270 .type = AMDGPU_RING_TYPE_KIQ,
4271 .align_mask = 0xff,
4272 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4273 .support_64bit_ptrs = true,
0eeb68b3 4274 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 4275 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4276 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4277 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4278 .emit_frame_size =
4279 20 + /* gfx_v9_0_ring_emit_gds_switch */
4280 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4281 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4282 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4283 24 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 4284 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4285 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4286 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4287 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 4288 .test_ring = gfx_v9_0_ring_test_ring,
4289 .test_ib = gfx_v9_0_ring_test_ib,
4290 .insert_nop = amdgpu_ring_insert_nop,
4291 .pad_ib = amdgpu_ring_generic_pad_ib,
4292 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4293 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4294};
b1023571
KW		 4295
4296static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4297{
4298 int i;
4299
aa6faa44
XY		 4300 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4301
b1023571
KW		 4302 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4303 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4304
4305 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4306 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4307}
4308
97031e25
XY		 4309static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4310 .set = gfx_v9_0_kiq_set_interrupt_state,
4311 .process = gfx_v9_0_kiq_irq,
4312};
4313
b1023571
KW		 4314static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4315 .set = gfx_v9_0_set_eop_interrupt_state,
4316 .process = gfx_v9_0_eop_irq,
4317};
4318
4319static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4320 .set = gfx_v9_0_set_priv_reg_fault_state,
4321 .process = gfx_v9_0_priv_reg_irq,
4322};
4323
4324static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4325 .set = gfx_v9_0_set_priv_inst_fault_state,
4326 .process = gfx_v9_0_priv_inst_irq,
4327};
4328
4329static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4330{
4331 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4332 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4333
4334 adev->gfx.priv_reg_irq.num_types = 1;
4335 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4336
4337 adev->gfx.priv_inst_irq.num_types = 1;
4338 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 4339
4340 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4341 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 4342}
4343
4344static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4345{
4346 switch (adev->asic_type) {
4347 case CHIP_VEGA10:
a4dc61f5 4348 case CHIP_RAVEN:
b1023571
KW		 4349 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4350 break;
4351 default:
4352 break;
4353 }
4354}
4355
4356static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4357{
4358 /* init asci gds info */
5e78835a 4359 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 4360 adev->gds.gws.total_size = 64;
4361 adev->gds.oa.total_size = 16;
4362
4363 if (adev->gds.mem.total_size == 64 * 1024) {
4364 adev->gds.mem.gfx_partition_size = 4096;
4365 adev->gds.mem.cs_partition_size = 4096;
4366
4367 adev->gds.gws.gfx_partition_size = 4;
4368 adev->gds.gws.cs_partition_size = 4;
4369
4370 adev->gds.oa.gfx_partition_size = 4;
4371 adev->gds.oa.cs_partition_size = 1;
4372 } else {
4373 adev->gds.mem.gfx_partition_size = 1024;
4374 adev->gds.mem.cs_partition_size = 1024;
4375
4376 adev->gds.gws.gfx_partition_size = 16;
4377 adev->gds.gws.cs_partition_size = 16;
4378
4379 adev->gds.oa.gfx_partition_size = 4;
4380 adev->gds.oa.cs_partition_size = 4;
4381 }
4382}
4383
c94d38f0
NH		 4384static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4385 u32 bitmap)
4386{
4387 u32 data;
4388
4389 if (!bitmap)
4390 return;
4391
4392 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4393 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4394
4395 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4396}
4397
b1023571
KW		 4398static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4399{
4400 u32 data, mask;
4401
5e78835a
TSD		 4402 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4403 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 4404
4405 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4406 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4407
378506a7 4408 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
b1023571
KW		 4409
4410 return (~data) & mask;
4411}
4412
4413static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4414 struct amdgpu_cu_info *cu_info)
4415{
4416 int i, j, k, counter, active_cu_number = 0;
4417 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
c94d38f0 4418 unsigned disable_masks[4 * 2];
b1023571
KW		 4419
4420 if (!adev || !cu_info)
4421 return -EINVAL;
4422
c94d38f0
NH		 4423 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4424
b1023571
KW		 4425 mutex_lock(&adev->grbm_idx_mutex);
4426 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4427 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4428 mask = 1;
4429 ao_bitmap = 0;
4430 counter = 0;
4431 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
c94d38f0
NH		 4432 if (i < 4 && j < 2)
4433 gfx_v9_0_set_user_cu_inactive_bitmap(
4434 adev, disable_masks[i * 2 + j]);
b1023571
KW		 4435 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4436 cu_info->bitmap[i][j] = bitmap;
4437
fe723cd3 4438 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
b1023571 4439 if (bitmap & mask) {
fe723cd3 4440 if (counter < adev->gfx.config.max_cu_per_sh)
b1023571
KW		 4441 ao_bitmap |= mask;
4442 counter ++;
4443 }
4444 mask <<= 1;
4445 }
4446 active_cu_number += counter;
dbfe85ea
FC		 4447 if (i < 2 && j < 2)
4448 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4449 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
b1023571
KW		 4450 }
4451 }
4452 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4453 mutex_unlock(&adev->grbm_idx_mutex);
4454
4455 cu_info->number = active_cu_number;
4456 cu_info->ao_cu_mask = ao_cu_mask;
4457
4458 return 0;
4459}
4460
b1023571
KW		 4461const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4462{
4463 .type = AMD_IP_BLOCK_TYPE_GFX,
4464 .major = 9,
4465 .minor = 0,
4466 .rev = 0,
4467 .funcs = &gfx_v9_0_ip_funcs,
4468};
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