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drm/amdgpu/gfx: move more common KIQ code to amdgpu_gfx.c
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
268cb4c7 41#define GFX9_MEC_HPD_SIZE 2048
6bce4667
HZ		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
b1023571 45
91d3130a
HZ		 46#define mmPWR_MISC_CNTL_STATUS 0x0183
47#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
52
b1023571
KW		 53MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
060d124b
CZ		 60MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62MODULE_FIRMWARE("amdgpu/raven_me.bin");
63MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
b1023571
KW		 67static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
68{
69 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
71 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
73 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
75 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
77 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
79 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
81 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
83 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
85 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
86 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
87 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
88 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
89 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
90 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
91 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
92 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
93 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
94 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
95 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
96 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
97 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
98 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
99 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
100 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
101};
102
103static const u32 golden_settings_gc_9_0[] =
104{
f8af9332
KW		 105 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
106 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
107 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
108 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
109 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
110 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
b1023571
KW		 111 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
112 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
113 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
f8af9332
KW		 114 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
115 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
116 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
117 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
118 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
119 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
b1023571
KW		 120 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
121 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
122 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
f8af9332
KW		 123 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
124 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
125 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
b1023571
KW		 126};
127
128static const u32 golden_settings_gc_9_0_vg10[] =
129{
130 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
131 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
132 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
133 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
134 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
135 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
f8af9332 136 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
b1023571
KW		 137};
138
a5fdb336
CZ		 139static const u32 golden_settings_gc_9_1[] =
140{
141 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
01b5cc36
HZ		 142 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
143 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
144 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 145 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
146 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
01b5cc36 147 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 148 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
149 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
150 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
01b5cc36
HZ		 151 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
152 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
153 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
154 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
155 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 156 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
157 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
158 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
01b5cc36
HZ		 159 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
160 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
161 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
a5fdb336
CZ		 162};
163
164static const u32 golden_settings_gc_9_1_rv1[] =
165{
7b6ba9ea
HZ		 166 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
167 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
168 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
169 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
170 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
171 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
a5fdb336
CZ		 172 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
173};
b1023571 174
5cf7433d 175#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
7b6ba9ea 176#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
5cf7433d 177
b1023571
KW		 178static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
179static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
180static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
181static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
182static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
183 struct amdgpu_cu_info *cu_info);
184static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
185static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
635e7132 186static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
b1023571
KW		 187
188static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
189{
190 switch (adev->asic_type) {
191 case CHIP_VEGA10:
192 amdgpu_program_register_sequence(adev,
193 golden_settings_gc_9_0,
194 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
195 amdgpu_program_register_sequence(adev,
196 golden_settings_gc_9_0_vg10,
197 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
198 break;
a5fdb336
CZ		 199 case CHIP_RAVEN:
200 amdgpu_program_register_sequence(adev,
201 golden_settings_gc_9_1,
202 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
203 amdgpu_program_register_sequence(adev,
204 golden_settings_gc_9_1_rv1,
205 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
206 break;
b1023571
KW		 207 default:
208 break;
209 }
210}
211
212static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
213{
214 adev->gfx.scratch.num_reg = 7;
215 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
216 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
217}
218
219static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
220 bool wc, uint32_t reg, uint32_t val)
221{
222 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
223 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
224 WRITE_DATA_DST_SEL(0) |
225 (wc ? WR_CONFIRM : 0));
226 amdgpu_ring_write(ring, reg);
227 amdgpu_ring_write(ring, 0);
228 amdgpu_ring_write(ring, val);
229}
230
231static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
232 int mem_space, int opt, uint32_t addr0,
233 uint32_t addr1, uint32_t ref, uint32_t mask,
234 uint32_t inv)
235{
236 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
237 amdgpu_ring_write(ring,
238 /* memory (1) or register (0) */
239 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
240 WAIT_REG_MEM_OPERATION(opt) | /* wait */
241 WAIT_REG_MEM_FUNCTION(3) | /* equal */
242 WAIT_REG_MEM_ENGINE(eng_sel)));
243
244 if (mem_space)
245 BUG_ON(addr0 & 0x3); /* Dword align */
246 amdgpu_ring_write(ring, addr0);
247 amdgpu_ring_write(ring, addr1);
248 amdgpu_ring_write(ring, ref);
249 amdgpu_ring_write(ring, mask);
250 amdgpu_ring_write(ring, inv); /* poll interval */
251}
252
253static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
254{
255 struct amdgpu_device *adev = ring->adev;
256 uint32_t scratch;
257 uint32_t tmp = 0;
258 unsigned i;
259 int r;
260
261 r = amdgpu_gfx_scratch_get(adev, &scratch);
262 if (r) {
263 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
264 return r;
265 }
266 WREG32(scratch, 0xCAFEDEAD);
267 r = amdgpu_ring_alloc(ring, 3);
268 if (r) {
269 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
270 ring->idx, r);
271 amdgpu_gfx_scratch_free(adev, scratch);
272 return r;
273 }
274 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
275 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
276 amdgpu_ring_write(ring, 0xDEADBEEF);
277 amdgpu_ring_commit(ring);
278
279 for (i = 0; i < adev->usec_timeout; i++) {
280 tmp = RREG32(scratch);
281 if (tmp == 0xDEADBEEF)
282 break;
283 DRM_UDELAY(1);
284 }
285 if (i < adev->usec_timeout) {
286 DRM_INFO("ring test on %d succeeded in %d usecs\n",
287 ring->idx, i);
288 } else {
289 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
290 ring->idx, scratch, tmp);
291 r = -EINVAL;
292 }
293 amdgpu_gfx_scratch_free(adev, scratch);
294 return r;
295}
296
297static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
298{
299 struct amdgpu_device *adev = ring->adev;
300 struct amdgpu_ib ib;
301 struct dma_fence *f = NULL;
302 uint32_t scratch;
303 uint32_t tmp = 0;
304 long r;
305
306 r = amdgpu_gfx_scratch_get(adev, &scratch);
307 if (r) {
308 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
309 return r;
310 }
311 WREG32(scratch, 0xCAFEDEAD);
312 memset(&ib, 0, sizeof(ib));
313 r = amdgpu_ib_get(adev, NULL, 256, &ib);
314 if (r) {
315 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
316 goto err1;
317 }
318 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
319 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
320 ib.ptr[2] = 0xDEADBEEF;
321 ib.length_dw = 3;
322
323 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
324 if (r)
325 goto err2;
326
327 r = dma_fence_wait_timeout(f, false, timeout);
328 if (r == 0) {
329 DRM_ERROR("amdgpu: IB test timed out.\n");
330 r = -ETIMEDOUT;
331 goto err2;
332 } else if (r < 0) {
333 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
334 goto err2;
335 }
336 tmp = RREG32(scratch);
337 if (tmp == 0xDEADBEEF) {
338 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
339 r = 0;
340 } else {
341 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
342 scratch, tmp);
343 r = -EINVAL;
344 }
345err2:
346 amdgpu_ib_free(adev, &ib, NULL);
347 dma_fence_put(f);
348err1:
349 amdgpu_gfx_scratch_free(adev, scratch);
350 return r;
351}
352
353static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
354{
355 const char *chip_name;
356 char fw_name[30];
357 int err;
358 struct amdgpu_firmware_info *info = NULL;
359 const struct common_firmware_header *header = NULL;
360 const struct gfx_firmware_header_v1_0 *cp_hdr;
a4d41ad0
HZ		 361 const struct rlc_firmware_header_v2_0 *rlc_hdr;
362 unsigned int *tmp = NULL;
363 unsigned int i = 0;
b1023571
KW		 364
365 DRM_DEBUG("\n");
366
367 switch (adev->asic_type) {
368 case CHIP_VEGA10:
369 chip_name = "vega10";
370 break;
eaa85724
CZ		 371 case CHIP_RAVEN:
372 chip_name = "raven";
373 break;
b1023571
KW		 374 default:
375 BUG();
376 }
377
378 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
379 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
380 if (err)
381 goto out;
382 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
383 if (err)
384 goto out;
385 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
386 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
387 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
388
389 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
390 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
391 if (err)
392 goto out;
393 err = amdgpu_ucode_validate(adev->gfx.me_fw);
394 if (err)
395 goto out;
396 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
397 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
398 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
399
400 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
401 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
402 if (err)
403 goto out;
404 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
405 if (err)
406 goto out;
407 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
408 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
409 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
410
411 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
412 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
413 if (err)
414 goto out;
415 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
a4d41ad0
HZ		 416 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
417 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
418 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
419 adev->gfx.rlc.save_and_restore_offset =
420 le32_to_cpu(rlc_hdr->save_and_restore_offset);
421 adev->gfx.rlc.clear_state_descriptor_offset =
422 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
423 adev->gfx.rlc.avail_scratch_ram_locations =
424 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
425 adev->gfx.rlc.reg_restore_list_size =
426 le32_to_cpu(rlc_hdr->reg_restore_list_size);
427 adev->gfx.rlc.reg_list_format_start =
428 le32_to_cpu(rlc_hdr->reg_list_format_start);
429 adev->gfx.rlc.reg_list_format_separate_start =
430 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
431 adev->gfx.rlc.starting_offsets_start =
432 le32_to_cpu(rlc_hdr->starting_offsets_start);
433 adev->gfx.rlc.reg_list_format_size_bytes =
434 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
435 adev->gfx.rlc.reg_list_size_bytes =
436 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
437 adev->gfx.rlc.register_list_format =
438 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
439 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
440 if (!adev->gfx.rlc.register_list_format) {
441 err = -ENOMEM;
442 goto out;
443 }
444
445 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
446 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
447 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
448 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
449
450 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
451
452 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
453 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
454 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
455 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
b1023571
KW		 456
457 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
458 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
459 if (err)
460 goto out;
461 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
462 if (err)
463 goto out;
464 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
465 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
466 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
467
468
469 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
470 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
471 if (!err) {
472 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
473 if (err)
474 goto out;
475 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
476 adev->gfx.mec2_fw->data;
477 adev->gfx.mec2_fw_version =
478 le32_to_cpu(cp_hdr->header.ucode_version);
479 adev->gfx.mec2_feature_version =
480 le32_to_cpu(cp_hdr->ucode_feature_version);
481 } else {
482 err = 0;
483 adev->gfx.mec2_fw = NULL;
484 }
485
486 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
487 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
488 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
489 info->fw = adev->gfx.pfp_fw;
490 header = (const struct common_firmware_header *)info->fw->data;
491 adev->firmware.fw_size +=
492 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
493
494 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
495 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
496 info->fw = adev->gfx.me_fw;
497 header = (const struct common_firmware_header *)info->fw->data;
498 adev->firmware.fw_size +=
499 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
500
501 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
502 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
503 info->fw = adev->gfx.ce_fw;
504 header = (const struct common_firmware_header *)info->fw->data;
505 adev->firmware.fw_size +=
506 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
507
508 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
509 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
510 info->fw = adev->gfx.rlc_fw;
511 header = (const struct common_firmware_header *)info->fw->data;
512 adev->firmware.fw_size +=
513 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
514
515 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
516 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
517 info->fw = adev->gfx.mec_fw;
518 header = (const struct common_firmware_header *)info->fw->data;
519 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
520 adev->firmware.fw_size +=
521 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
522
523 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
524 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
525 info->fw = adev->gfx.mec_fw;
526 adev->firmware.fw_size +=
527 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
528
529 if (adev->gfx.mec2_fw) {
530 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
531 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
532 info->fw = adev->gfx.mec2_fw;
533 header = (const struct common_firmware_header *)info->fw->data;
534 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
535 adev->firmware.fw_size +=
536 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
537 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
538 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
539 info->fw = adev->gfx.mec2_fw;
540 adev->firmware.fw_size +=
541 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
542 }
543
544 }
545
546out:
547 if (err) {
548 dev_err(adev->dev,
549 "gfx9: Failed to load firmware \"%s\"\n",
550 fw_name);
551 release_firmware(adev->gfx.pfp_fw);
552 adev->gfx.pfp_fw = NULL;
553 release_firmware(adev->gfx.me_fw);
554 adev->gfx.me_fw = NULL;
555 release_firmware(adev->gfx.ce_fw);
556 adev->gfx.ce_fw = NULL;
557 release_firmware(adev->gfx.rlc_fw);
558 adev->gfx.rlc_fw = NULL;
559 release_firmware(adev->gfx.mec_fw);
560 adev->gfx.mec_fw = NULL;
561 release_firmware(adev->gfx.mec2_fw);
562 adev->gfx.mec2_fw = NULL;
563 }
564 return err;
565}
566
c9719c69
HZ		 567static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
568{
569 u32 count = 0;
570 const struct cs_section_def *sect = NULL;
571 const struct cs_extent_def *ext = NULL;
572
573 /* begin clear state */
574 count += 2;
575 /* context control state */
576 count += 3;
577
578 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
579 for (ext = sect->section; ext->extent != NULL; ++ext) {
580 if (sect->id == SECT_CONTEXT)
581 count += 2 + ext->reg_count;
582 else
583 return 0;
584 }
585 }
586
587 /* end clear state */
588 count += 2;
589 /* clear state */
590 count += 2;
591
592 return count;
593}
594
595static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
596 volatile u32 *buffer)
597{
598 u32 count = 0, i;
599 const struct cs_section_def *sect = NULL;
600 const struct cs_extent_def *ext = NULL;
601
602 if (adev->gfx.rlc.cs_data == NULL)
603 return;
604 if (buffer == NULL)
605 return;
606
607 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
608 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
609
610 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
611 buffer[count++] = cpu_to_le32(0x80000000);
612 buffer[count++] = cpu_to_le32(0x80000000);
613
614 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
615 for (ext = sect->section; ext->extent != NULL; ++ext) {
616 if (sect->id == SECT_CONTEXT) {
617 buffer[count++] =
618 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
619 buffer[count++] = cpu_to_le32(ext->reg_index -
620 PACKET3_SET_CONTEXT_REG_START);
621 for (i = 0; i < ext->reg_count; i++)
622 buffer[count++] = cpu_to_le32(ext->extent[i]);
623 } else {
624 return;
625 }
626 }
627 }
628
629 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
630 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
631
632 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
633 buffer[count++] = cpu_to_le32(0);
634}
635
ba7bb665
HZ		 636static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
637{
638 uint32_t data = 0;
639
640 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
641 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
642 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
643 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
644 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
645
646 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
647 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
648
649 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
650 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
651
652 mutex_lock(&adev->grbm_idx_mutex);
653 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
654 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
655 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
656
657 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
658 data |= (0x0003 << RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT) &
659 RLC_LB_PARAMS__FIFO_SAMPLES_MASK;
660 data |= (0x0010 << RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT) &
661 RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK;
662 data |= (0x033F << RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT) &
663 RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK;
664 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
665
666 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
667 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
668 data &= 0x0000FFFF;
669 data |= 0x00C00000;
670 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
671
672 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
673 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
674
675 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
676 * but used for RLC_LB_CNTL configuration */
677 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
678 data |= (0x09 << RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT) &
679 RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK;
680 data |= (0x80000 << RLC_LB_CNTL__RESERVED__SHIFT) &
681 RLC_LB_CNTL__RESERVED_MASK;
682 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
683 mutex_unlock(&adev->grbm_idx_mutex);
684}
685
e8835e0e
HZ		 686static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
687{
688 uint32_t data = 0;
689
690 data = RREG32_SOC15(GC, 0, mmRLC_LB_CNTL);
691 if (enable)
692 data |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
693 else
694 data &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
695 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
696}
697
c9719c69
HZ		 698static void rv_init_cp_jump_table(struct amdgpu_device *adev)
699{
700 const __le32 *fw_data;
701 volatile u32 *dst_ptr;
702 int me, i, max_me = 5;
703 u32 bo_offset = 0;
704 u32 table_offset, table_size;
705
706 /* write the cp table buffer */
707 dst_ptr = adev->gfx.rlc.cp_table_ptr;
708 for (me = 0; me < max_me; me++) {
709 if (me == 0) {
710 const struct gfx_firmware_header_v1_0 *hdr =
711 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
712 fw_data = (const __le32 *)
713 (adev->gfx.ce_fw->data +
714 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
715 table_offset = le32_to_cpu(hdr->jt_offset);
716 table_size = le32_to_cpu(hdr->jt_size);
717 } else if (me == 1) {
718 const struct gfx_firmware_header_v1_0 *hdr =
719 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
720 fw_data = (const __le32 *)
721 (adev->gfx.pfp_fw->data +
722 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
723 table_offset = le32_to_cpu(hdr->jt_offset);
724 table_size = le32_to_cpu(hdr->jt_size);
725 } else if (me == 2) {
726 const struct gfx_firmware_header_v1_0 *hdr =
727 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
728 fw_data = (const __le32 *)
729 (adev->gfx.me_fw->data +
730 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
731 table_offset = le32_to_cpu(hdr->jt_offset);
732 table_size = le32_to_cpu(hdr->jt_size);
733 } else if (me == 3) {
734 const struct gfx_firmware_header_v1_0 *hdr =
735 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
736 fw_data = (const __le32 *)
737 (adev->gfx.mec_fw->data +
738 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
739 table_offset = le32_to_cpu(hdr->jt_offset);
740 table_size = le32_to_cpu(hdr->jt_size);
741 } else if (me == 4) {
742 const struct gfx_firmware_header_v1_0 *hdr =
743 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
744 fw_data = (const __le32 *)
745 (adev->gfx.mec2_fw->data +
746 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
747 table_offset = le32_to_cpu(hdr->jt_offset);
748 table_size = le32_to_cpu(hdr->jt_size);
749 }
750
751 for (i = 0; i < table_size; i ++) {
752 dst_ptr[bo_offset + i] =
753 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
754 }
755
756 bo_offset += table_size;
757 }
758}
759
760static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
761{
762 /* clear state block */
763 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
764 &adev->gfx.rlc.clear_state_gpu_addr,
765 (void **)&adev->gfx.rlc.cs_ptr);
766
767 /* jump table block */
768 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
769 &adev->gfx.rlc.cp_table_gpu_addr,
770 (void **)&adev->gfx.rlc.cp_table_ptr);
771}
772
773static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
774{
775 volatile u32 *dst_ptr;
776 u32 dws;
777 const struct cs_section_def *cs_data;
778 int r;
779
780 adev->gfx.rlc.cs_data = gfx9_cs_data;
781
782 cs_data = adev->gfx.rlc.cs_data;
783
784 if (cs_data) {
785 /* clear state block */
786 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
787 if (adev->gfx.rlc.clear_state_obj == NULL) {
788 r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
789 AMDGPU_GEM_DOMAIN_VRAM,
790 &adev->gfx.rlc.clear_state_obj,
791 &adev->gfx.rlc.clear_state_gpu_addr,
792 (void **)&adev->gfx.rlc.cs_ptr);
793 if (r) {
794 dev_err(adev->dev,
795 "(%d) failed to create rlc csb bo\n", r);
796 gfx_v9_0_rlc_fini(adev);
797 return r;
798 }
799 }
800 /* set up the cs buffer */
801 dst_ptr = adev->gfx.rlc.cs_ptr;
802 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
803 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
804 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
805 }
806
807 if (adev->asic_type == CHIP_RAVEN) {
808 /* TODO: double check the cp_table_size for RV */
809 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
810 if (adev->gfx.rlc.cp_table_obj == NULL) {
811 r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size,
812 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
813 &adev->gfx.rlc.cp_table_obj,
814 &adev->gfx.rlc.cp_table_gpu_addr,
815 (void **)&adev->gfx.rlc.cp_table_ptr);
816 if (r) {
817 dev_err(adev->dev,
818 "(%d) failed to create cp table bo\n", r);
819 gfx_v9_0_rlc_fini(adev);
820 return r;
821 }
822 }
823
824 rv_init_cp_jump_table(adev);
825 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
826 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
ba7bb665
HZ		 827
828 gfx_v9_0_init_lbpw(adev);
c9719c69
HZ		 829 }
830
831 return 0;
832}
833
b1023571
KW		 834static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
835{
836 int r;
837
838 if (adev->gfx.mec.hpd_eop_obj) {
c81a1a74 839 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
b1023571
KW		 840 if (unlikely(r != 0))
841 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
842 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
843 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
844
845 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
846 adev->gfx.mec.hpd_eop_obj = NULL;
847 }
848 if (adev->gfx.mec.mec_fw_obj) {
c81a1a74 849 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true);
b1023571
KW		 850 if (unlikely(r != 0))
851 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
852 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
853 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
854
855 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
856 adev->gfx.mec.mec_fw_obj = NULL;
857 }
858}
859
b1023571
KW		 860static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
861{
862 int r;
863 u32 *hpd;
864 const __le32 *fw_data;
865 unsigned fw_size;
866 u32 *fw;
42794b27 867 size_t mec_hpd_size;
b1023571
KW		 868
869 const struct gfx_firmware_header_v1_0 *mec_hdr;
870
78c16834
AR		 871 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
872
42794b27
AR		 873 switch (adev->asic_type) {
874 case CHIP_VEGA10:
5e7c8b06 875 case CHIP_RAVEN:
42794b27
AR		 876 adev->gfx.mec.num_mec = 2;
877 break;
878 default:
879 adev->gfx.mec.num_mec = 1;
880 break;
881 }
882
883 adev->gfx.mec.num_pipe_per_mec = 4;
884 adev->gfx.mec.num_queue_per_pipe = 8;
885
78c16834 886 /* take ownership of the relevant compute queues */
41f6a99a 887 amdgpu_gfx_compute_queue_acquire(adev);
78c16834 888 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
b1023571
KW		 889
890 if (adev->gfx.mec.hpd_eop_obj == NULL) {
891 r = amdgpu_bo_create(adev,
42794b27 892 mec_hpd_size,
b1023571
KW		 893 PAGE_SIZE, true,
894 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
895 &adev->gfx.mec.hpd_eop_obj);
896 if (r) {
897 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
898 return r;
899 }
900 }
901
902 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
903 if (unlikely(r != 0)) {
904 gfx_v9_0_mec_fini(adev);
905 return r;
906 }
907 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
908 &adev->gfx.mec.hpd_eop_gpu_addr);
909 if (r) {
910 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
911 gfx_v9_0_mec_fini(adev);
912 return r;
913 }
914 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
915 if (r) {
916 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
917 gfx_v9_0_mec_fini(adev);
918 return r;
919 }
920
921 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
922
923 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
924 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
925
926 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
927
928 fw_data = (const __le32 *)
929 (adev->gfx.mec_fw->data +
930 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
931 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
932
933 if (adev->gfx.mec.mec_fw_obj == NULL) {
934 r = amdgpu_bo_create(adev,
935 mec_hdr->header.ucode_size_bytes,
936 PAGE_SIZE, true,
937 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
938 &adev->gfx.mec.mec_fw_obj);
939 if (r) {
940 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
941 return r;
942 }
943 }
944
945 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
946 if (unlikely(r != 0)) {
947 gfx_v9_0_mec_fini(adev);
948 return r;
949 }
950 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
951 &adev->gfx.mec.mec_fw_gpu_addr);
952 if (r) {
953 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
954 gfx_v9_0_mec_fini(adev);
955 return r;
956 }
957 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
958 if (r) {
959 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
960 gfx_v9_0_mec_fini(adev);
961 return r;
962 }
963 memcpy(fw, fw_data, fw_size);
964
965 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
966 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
967
968
969 return 0;
970}
971
464826d6 972/* create MQD for each compute queue */
e935c211 973static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev)
464826d6
XY		 974{
975 struct amdgpu_ring *ring = NULL;
976 int r, i;
977
978 /* create MQD for KIQ */
979 ring = &adev->gfx.kiq.ring;
980 if (!ring->mqd_obj) {
981 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
b4fcf7f0
AD		 982 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
983 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
464826d6
XY		 984 if (r) {
985 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
986 return r;
987 }
988
0ef376ca
AD		 989 /* prepare MQD backup */
990 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL);
991 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
992 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
464826d6
XY		 993 }
994
995 /* create MQD for each KCQ */
b4fcf7f0 996 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
464826d6
XY		 997 ring = &adev->gfx.compute_ring[i];
998 if (!ring->mqd_obj) {
999 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
b4fcf7f0
AD		 1000 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1001 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
464826d6
XY		 1002 if (r) {
1003 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
1004 return r;
1005 }
1006
0ef376ca
AD		 1007 /* prepare MQD backup */
1008 adev->gfx.mec.mqd_backup[i] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL);
1009 if (!adev->gfx.mec.mqd_backup[i])
1010 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
464826d6
XY		 1011 }
1012 }
1013
1014 return 0;
1015}
1016
e935c211 1017static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev)
464826d6
XY		 1018{
1019 struct amdgpu_ring *ring = NULL;
1020 int i;
1021
1022 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1023 ring = &adev->gfx.compute_ring[i];
0ef376ca 1024 kfree(adev->gfx.mec.mqd_backup[i]);
464826d6
XY		 1025 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1026 }
1027
1028 ring = &adev->gfx.kiq.ring;
0ef376ca 1029 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
464826d6
XY		 1030 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1031}
1032
b1023571
KW		 1033static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1034{
5e78835a 1035 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 1036 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1037 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1038 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1039 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 1040 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 1041}
1042
1043static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1044 uint32_t wave, uint32_t thread,
1045 uint32_t regno, uint32_t num, uint32_t *out)
1046{
5e78835a 1047 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 1048 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1049 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1050 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1051 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1052 (SQ_IND_INDEX__FORCE_READ_MASK) |
1053 (SQ_IND_INDEX__AUTO_INCR_MASK));
1054 while (num--)
5e78835a 1055 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 1056}
1057
1058static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1059{
1060 /* type 1 wave data */
1061 dst[(*no_fields)++] = 1;
1062 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1063 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1064 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1065 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1066 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1067 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1068 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1069 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1070 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1071 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1072 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1073 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1074 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1075 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1076}
1077
1078static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1079 uint32_t wave, uint32_t start,
1080 uint32_t size, uint32_t *dst)
1081{
1082 wave_read_regs(
1083 adev, simd, wave, 0,
1084 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1085}
1086
1087
1088static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1089 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1090 .select_se_sh = &gfx_v9_0_select_se_sh,
1091 .read_wave_data = &gfx_v9_0_read_wave_data,
1092 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1093};
1094
1095static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1096{
1097 u32 gb_addr_config;
1098
1099 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1100
1101 switch (adev->asic_type) {
1102 case CHIP_VEGA10:
b1023571 1103 adev->gfx.config.max_hw_contexts = 8;
b1023571
KW		 1104 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1105 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1106 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1107 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1108 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1109 break;
5cf7433d
CZ		 1110 case CHIP_RAVEN:
1111 adev->gfx.config.max_hw_contexts = 8;
1112 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1113 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1114 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1115 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1116 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1117 break;
b1023571
KW		 1118 default:
1119 BUG();
1120 break;
1121 }
1122
1123 adev->gfx.config.gb_addr_config = gb_addr_config;
1124
1125 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1126 REG_GET_FIELD(
1127 adev->gfx.config.gb_addr_config,
1128 GB_ADDR_CONFIG,
1129 NUM_PIPES);
ad7d0ff3
AD		 1130
1131 adev->gfx.config.max_tile_pipes =
1132 adev->gfx.config.gb_addr_config_fields.num_pipes;
1133
b1023571
KW		 1134 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1135 REG_GET_FIELD(
1136 adev->gfx.config.gb_addr_config,
1137 GB_ADDR_CONFIG,
1138 NUM_BANKS);
1139 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1140 REG_GET_FIELD(
1141 adev->gfx.config.gb_addr_config,
1142 GB_ADDR_CONFIG,
1143 MAX_COMPRESSED_FRAGS);
1144 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1145 REG_GET_FIELD(
1146 adev->gfx.config.gb_addr_config,
1147 GB_ADDR_CONFIG,
1148 NUM_RB_PER_SE);
1149 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1150 REG_GET_FIELD(
1151 adev->gfx.config.gb_addr_config,
1152 GB_ADDR_CONFIG,
1153 NUM_SHADER_ENGINES);
1154 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1155 REG_GET_FIELD(
1156 adev->gfx.config.gb_addr_config,
1157 GB_ADDR_CONFIG,
1158 PIPE_INTERLEAVE_SIZE));
1159}
1160
1161static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1162 struct amdgpu_ngg_buf *ngg_buf,
1163 int size_se,
1164 int default_size_se)
1165{
1166 int r;
1167
1168 if (size_se < 0) {
1169 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1170 return -EINVAL;
1171 }
1172 size_se = size_se ? size_se : default_size_se;
1173
42ce2243 1174 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 1175 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1176 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1177 &ngg_buf->bo,
1178 &ngg_buf->gpu_addr,
1179 NULL);
1180 if (r) {
1181 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1182 return r;
1183 }
1184 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1185
1186 return r;
1187}
1188
1189static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1190{
1191 int i;
1192
1193 for (i = 0; i < NGG_BUF_MAX; i++)
1194 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1195 &adev->gfx.ngg.buf[i].gpu_addr,
1196 NULL);
1197
1198 memset(&adev->gfx.ngg.buf[0], 0,
1199 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1200
1201 adev->gfx.ngg.init = false;
1202
1203 return 0;
1204}
1205
1206static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1207{
1208 int r;
1209
1210 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1211 return 0;
1212
1213 /* GDS reserve memory: 64 bytes alignment */
1214 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1215 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1216 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1217 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1218 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1219
1220 /* Primitive Buffer */
af8baf15 1221 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
b1023571
KW		 1222 amdgpu_prim_buf_per_se,
1223 64 * 1024);
1224 if (r) {
1225 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1226 goto err;
1227 }
1228
1229 /* Position Buffer */
af8baf15 1230 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
b1023571
KW		 1231 amdgpu_pos_buf_per_se,
1232 256 * 1024);
1233 if (r) {
1234 dev_err(adev->dev, "Failed to create Position Buffer\n");
1235 goto err;
1236 }
1237
1238 /* Control Sideband */
af8baf15 1239 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
b1023571
KW		 1240 amdgpu_cntl_sb_buf_per_se,
1241 256);
1242 if (r) {
1243 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1244 goto err;
1245 }
1246
1247 /* Parameter Cache, not created by default */
1248 if (amdgpu_param_buf_per_se <= 0)
1249 goto out;
1250
af8baf15 1251 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
b1023571
KW		 1252 amdgpu_param_buf_per_se,
1253 512 * 1024);
1254 if (r) {
1255 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1256 goto err;
1257 }
1258
1259out:
1260 adev->gfx.ngg.init = true;
1261 return 0;
1262err:
1263 gfx_v9_0_ngg_fini(adev);
1264 return r;
1265}
1266
1267static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1268{
1269 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1270 int r;
1271 u32 data;
1272 u32 size;
1273 u32 base;
1274
1275 if (!amdgpu_ngg)
1276 return 0;
1277
1278 /* Program buffer size */
1279 data = 0;
af8baf15 1280 size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
b1023571
KW		 1281 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
1282
af8baf15 1283 size = adev->gfx.ngg.buf[NGG_POS].size / 256;
b1023571
KW		 1284 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
1285
5e78835a 1286 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571
KW		 1287
1288 data = 0;
af8baf15 1289 size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
b1023571
KW		 1290 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
1291
af8baf15 1292 size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
b1023571
KW		 1293 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
1294
5e78835a 1295 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 1296
1297 /* Program buffer base address */
af8baf15 1298 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1299 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 1300 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571 1301
af8baf15 1302 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1303 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 1304 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571 1305
af8baf15 1306 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1307 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 1308 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571 1309
af8baf15 1310 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1311 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 1312 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571 1313
af8baf15 1314 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1315 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 1316 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571 1317
af8baf15 1318 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1319 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 1320 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 1321
1322 /* Clear GDS reserved memory */
1323 r = amdgpu_ring_alloc(ring, 17);
1324 if (r) {
1325 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1326 ring->idx, r);
1327 return r;
1328 }
1329
1330 gfx_v9_0_write_data_to_reg(ring, 0, false,
1331 amdgpu_gds_reg_offset[0].mem_size,
1332 (adev->gds.mem.total_size +
1333 adev->gfx.ngg.gds_reserve_size) >>
1334 AMDGPU_GDS_SHIFT);
1335
1336 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1337 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1338 PACKET3_DMA_DATA_SRC_SEL(2)));
1339 amdgpu_ring_write(ring, 0);
1340 amdgpu_ring_write(ring, 0);
1341 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1342 amdgpu_ring_write(ring, 0);
1343 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1344
1345
1346 gfx_v9_0_write_data_to_reg(ring, 0, false,
1347 amdgpu_gds_reg_offset[0].mem_size, 0);
1348
1349 amdgpu_ring_commit(ring);
1350
1351 return 0;
1352}
1353
1361f455
AD		 1354static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1355 int mec, int pipe, int queue)
1356{
1357 int r;
1358 unsigned irq_type;
1359 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1360
1361 ring = &adev->gfx.compute_ring[ring_id];
1362
1363 /* mec0 is me1 */
1364 ring->me = mec + 1;
1365 ring->pipe = pipe;
1366 ring->queue = queue;
1367
1368 ring->ring_obj = NULL;
1369 ring->use_doorbell = true;
1370 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
1371 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1372 + (ring_id * GFX9_MEC_HPD_SIZE);
1373 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1374
1375 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1376 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1377 + ring->pipe;
1378
1379 /* type-2 packets are deprecated on MEC, use type-3 instead */
1380 r = amdgpu_ring_init(adev, ring, 1024,
1381 &adev->gfx.eop_irq, irq_type);
1382 if (r)
1383 return r;
1384
1385
1386 return 0;
1387}
1388
b1023571
KW		 1389static int gfx_v9_0_sw_init(void *handle)
1390{
1361f455 1391 int i, j, k, r, ring_id;
b1023571 1392 struct amdgpu_ring *ring;
ac104e99 1393 struct amdgpu_kiq *kiq;
b1023571
KW		 1394 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1395
97031e25
XY		 1396 /* KIQ event */
1397 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1398 if (r)
1399 return r;
1400
b1023571
KW		 1401 /* EOP Event */
1402 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1403 if (r)
1404 return r;
1405
1406 /* Privileged reg */
1407 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1408 &adev->gfx.priv_reg_irq);
1409 if (r)
1410 return r;
1411
1412 /* Privileged inst */
1413 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1414 &adev->gfx.priv_inst_irq);
1415 if (r)
1416 return r;
1417
1418 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1419
1420 gfx_v9_0_scratch_init(adev);
1421
1422 r = gfx_v9_0_init_microcode(adev);
1423 if (r) {
1424 DRM_ERROR("Failed to load gfx firmware!\n");
1425 return r;
1426 }
1427
c9719c69
HZ		 1428 r = gfx_v9_0_rlc_init(adev);
1429 if (r) {
1430 DRM_ERROR("Failed to init rlc BOs!\n");
1431 return r;
1432 }
1433
b1023571
KW		 1434 r = gfx_v9_0_mec_init(adev);
1435 if (r) {
1436 DRM_ERROR("Failed to init MEC BOs!\n");
1437 return r;
1438 }
1439
1440 /* set up the gfx ring */
1441 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1442 ring = &adev->gfx.gfx_ring[i];
1443 ring->ring_obj = NULL;
1444 sprintf(ring->name, "gfx");
1445 ring->use_doorbell = true;
1446 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1447 r = amdgpu_ring_init(adev, ring, 1024,
1448 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1449 if (r)
1450 return r;
1451 }
1452
1361f455
AD		 1453 /* set up the compute queues - allocate horizontally across pipes */
1454 ring_id = 0;
1455 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1456 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1457 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2db0cdbe 1458 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1361f455
AD		 1459 continue;
1460
1461 r = gfx_v9_0_compute_ring_init(adev,
1462 ring_id,
1463 i, k, j);
1464 if (r)
1465 return r;
1466
1467 ring_id++;
1468 }
b1023571 1469 }
b1023571
KW		 1470 }
1471
71c37505 1472 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
e30a5223
AD		 1473 if (r) {
1474 DRM_ERROR("Failed to init KIQ BOs!\n");
1475 return r;
1476 }
ac104e99 1477
e30a5223 1478 kiq = &adev->gfx.kiq;
71c37505 1479 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
e30a5223
AD		 1480 if (r)
1481 return r;
464826d6 1482
e30a5223
AD		 1483 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1484 r = gfx_v9_0_compute_mqd_sw_init(adev);
1485 if (r)
1486 return r;
ac104e99 1487
b1023571
KW		 1488 /* reserve GDS, GWS and OA resource for gfx */
1489 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1490 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1491 &adev->gds.gds_gfx_bo, NULL, NULL);
1492 if (r)
1493 return r;
1494
1495 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1496 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1497 &adev->gds.gws_gfx_bo, NULL, NULL);
1498 if (r)
1499 return r;
1500
1501 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1503 &adev->gds.oa_gfx_bo, NULL, NULL);
1504 if (r)
1505 return r;
1506
1507 adev->gfx.ce_ram_size = 0x8000;
1508
1509 gfx_v9_0_gpu_early_init(adev);
1510
1511 r = gfx_v9_0_ngg_init(adev);
1512 if (r)
1513 return r;
1514
1515 return 0;
1516}
1517
1518
1519static int gfx_v9_0_sw_fini(void *handle)
1520{
1521 int i;
1522 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1523
1524 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1525 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1526 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1527
1528 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1529 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1530 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1531 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1532
e30a5223 1533 gfx_v9_0_compute_mqd_sw_fini(adev);
71c37505
AD		 1534 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1535 amdgpu_gfx_kiq_fini(adev);
ac104e99 1536
b1023571
KW		 1537 gfx_v9_0_mec_fini(adev);
1538 gfx_v9_0_ngg_fini(adev);
1539
1540 return 0;
1541}
1542
1543
1544static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1545{
1546 /* TODO */
1547}
1548
1549static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1550{
1551 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1552
1553 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1554 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1555 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1556 } else if (se_num == 0xffffffff) {
1557 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1558 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1559 } else if (sh_num == 0xffffffff) {
1560 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1561 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1562 } else {
1563 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1564 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1565 }
5e78835a 1566 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1567}
1568
b1023571
KW		 1569static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1570{
1571 u32 data, mask;
1572
5e78835a
TSD		 1573 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1574 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1575
1576 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1577 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1578
378506a7
AD		 1579 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1580 adev->gfx.config.max_sh_per_se);
b1023571
KW		 1581
1582 return (~data) & mask;
1583}
1584
1585static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1586{
1587 int i, j;
2572c24c 1588 u32 data;
b1023571
KW		 1589 u32 active_rbs = 0;
1590 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1591 adev->gfx.config.max_sh_per_se;
1592
1593 mutex_lock(&adev->grbm_idx_mutex);
1594 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1595 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1596 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1597 data = gfx_v9_0_get_rb_active_bitmap(adev);
1598 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1599 rb_bitmap_width_per_sh);
1600 }
1601 }
1602 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1603 mutex_unlock(&adev->grbm_idx_mutex);
1604
1605 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1606 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1607}
1608
1609#define DEFAULT_SH_MEM_BASES (0x6000)
1610#define FIRST_COMPUTE_VMID (8)
1611#define LAST_COMPUTE_VMID (16)
1612static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1613{
1614 int i;
1615 uint32_t sh_mem_config;
1616 uint32_t sh_mem_bases;
1617
1618 /*
1619 * Configure apertures:
1620 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1621 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1622 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1623 */
1624 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1625
1626 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1627 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
eaa05d52 1628 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
b1023571
KW		 1629
1630 mutex_lock(&adev->srbm_mutex);
1631 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1632 soc15_grbm_select(adev, 0, 0, 0, i);
1633 /* CP and shaders */
5e78835a
TSD		 1634 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1635 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1636 }
1637 soc15_grbm_select(adev, 0, 0, 0, 0);
1638 mutex_unlock(&adev->srbm_mutex);
1639}
1640
1641static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1642{
1643 u32 tmp;
1644 int i;
1645
40f06773 1646 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1647
1648 gfx_v9_0_tiling_mode_table_init(adev);
1649
1650 gfx_v9_0_setup_rb(adev);
1651 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1652
1653 /* XXX SH_MEM regs */
1654 /* where to put LDS, scratch, GPUVM in FSA64 space */
1655 mutex_lock(&adev->srbm_mutex);
1656 for (i = 0; i < 16; i++) {
1657 soc15_grbm_select(adev, 0, 0, 0, i);
1658 /* CP and shaders */
1659 tmp = 0;
1660 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1661 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5e78835a
TSD		 1662 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1663 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
b1023571
KW		 1664 }
1665 soc15_grbm_select(adev, 0, 0, 0, 0);
1666
1667 mutex_unlock(&adev->srbm_mutex);
1668
1669 gfx_v9_0_init_compute_vmid(adev);
1670
1671 mutex_lock(&adev->grbm_idx_mutex);
1672 /*
1673 * making sure that the following register writes will be broadcasted
1674 * to all the shaders
1675 */
1676 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1677
5e78835a 1678 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1679 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1680 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1681 (adev->gfx.config.sc_prim_fifo_size_backend <<
1682 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1683 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1684 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1685 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1686 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1687 mutex_unlock(&adev->grbm_idx_mutex);
1688
1689}
1690
1691static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1692{
1693 u32 i, j, k;
1694 u32 mask;
1695
1696 mutex_lock(&adev->grbm_idx_mutex);
1697 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1698 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1699 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1700 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1701 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1702 break;
1703 udelay(1);
1704 }
1705 }
1706 }
1707 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1708 mutex_unlock(&adev->grbm_idx_mutex);
1709
1710 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1711 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1712 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1713 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1714 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1715 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1716 break;
1717 udelay(1);
1718 }
1719}
1720
1721static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1722 bool enable)
1723{
5e78835a 1724 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571 1725
b1023571
KW		 1726 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1727 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1728 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1729 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1730
5e78835a 1731 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1732}
1733
6bce4667
HZ		 1734static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1735{
1736 /* csib */
1737 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1738 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1739 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1740 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1741 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1742 adev->gfx.rlc.clear_state_size);
1743}
1744
1745static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1746 int indirect_offset,
1747 int list_size,
1748 int *unique_indirect_regs,
1749 int *unique_indirect_reg_count,
1750 int max_indirect_reg_count,
1751 int *indirect_start_offsets,
1752 int *indirect_start_offsets_count,
1753 int max_indirect_start_offsets_count)
1754{
1755 int idx;
1756 bool new_entry = true;
1757
1758 for (; indirect_offset < list_size; indirect_offset++) {
1759
1760 if (new_entry) {
1761 new_entry = false;
1762 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1763 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1764 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1765 }
1766
1767 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1768 new_entry = true;
1769 continue;
1770 }
1771
1772 indirect_offset += 2;
1773
1774 /* look for the matching indice */
1775 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1776 if (unique_indirect_regs[idx] ==
1777 register_list_format[indirect_offset])
1778 break;
1779 }
1780
1781 if (idx >= *unique_indirect_reg_count) {
1782 unique_indirect_regs[*unique_indirect_reg_count] =
1783 register_list_format[indirect_offset];
1784 idx = *unique_indirect_reg_count;
1785 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1786 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1787 }
1788
1789 register_list_format[indirect_offset] = idx;
1790 }
1791}
1792
1793static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1794{
1795 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1796 int unique_indirect_reg_count = 0;
1797
1798 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1799 int indirect_start_offsets_count = 0;
1800
1801 int list_size = 0;
1802 int i = 0;
1803 u32 tmp = 0;
1804
1805 u32 *register_list_format =
1806 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1807 if (!register_list_format)
1808 return -ENOMEM;
1809 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1810 adev->gfx.rlc.reg_list_format_size_bytes);
1811
1812 /* setup unique_indirect_regs array and indirect_start_offsets array */
1813 gfx_v9_0_parse_ind_reg_list(register_list_format,
1814 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1815 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1816 unique_indirect_regs,
1817 &unique_indirect_reg_count,
1818 sizeof(unique_indirect_regs)/sizeof(int),
1819 indirect_start_offsets,
1820 &indirect_start_offsets_count,
1821 sizeof(indirect_start_offsets)/sizeof(int));
1822
1823 /* enable auto inc in case it is disabled */
1824 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1825 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1826 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1827
1828 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1829 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1830 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1831 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1832 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1833 adev->gfx.rlc.register_restore[i]);
1834
1835 /* load direct register */
1836 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1837 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1838 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1839 adev->gfx.rlc.register_restore[i]);
1840
1841 /* load indirect register */
1842 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1843 adev->gfx.rlc.reg_list_format_start);
1844 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1845 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1846 register_list_format[i]);
1847
1848 /* set save/restore list size */
1849 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1850 list_size = list_size >> 1;
1851 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1852 adev->gfx.rlc.reg_restore_list_size);
1853 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1854
1855 /* write the starting offsets to RLC scratch ram */
1856 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1857 adev->gfx.rlc.starting_offsets_start);
1858 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1859 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1860 indirect_start_offsets[i]);
1861
1862 /* load unique indirect regs*/
1863 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1864 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1865 unique_indirect_regs[i] & 0x3FFFF);
1866 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1867 unique_indirect_regs[i] >> 20);
1868 }
1869
1870 kfree(register_list_format);
1871 return 0;
1872}
1873
1874static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1875{
1876 u32 tmp = 0;
1877
1878 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1879 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1880 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1881}
1882
91d3130a
HZ		 1883static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1884 bool enable)
1885{
1886 uint32_t data = 0;
1887 uint32_t default_data = 0;
1888
1889 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1890 if (enable == true) {
1891 /* enable GFXIP control over CGPG */
1892 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1893 if(default_data != data)
1894 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1895
1896 /* update status */
1897 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1898 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1899 if(default_data != data)
1900 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1901 } else {
1902 /* restore GFXIP control over GCPG */
1903 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1904 if(default_data != data)
1905 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1906 }
1907}
1908
1909static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1910{
1911 uint32_t data = 0;
1912
1913 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1914 AMD_PG_SUPPORT_GFX_SMG |
1915 AMD_PG_SUPPORT_GFX_DMG)) {
1916 /* init IDLE_POLL_COUNT = 60 */
1917 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1918 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1919 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1920 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1921
1922 /* init RLC PG Delay */
1923 data = 0;
1924 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1925 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1926 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1927 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1928 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1929
1930 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1931 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1932 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1933 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1934
1935 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1936 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1937 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1938 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1939
1940 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1941 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1942
1943 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1944 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1945 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1946
1947 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1948 }
1949}
1950
ed5ad1e4
HZ		 1951static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1952 bool enable)
1953{
1954 uint32_t data = 0;
1955 uint32_t default_data = 0;
1956
1957 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1958
1959 if (enable == true) {
1960 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1961 if (default_data != data)
1962 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1963 } else {
1964 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1965 if(default_data != data)
1966 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1967 }
1968}
1969
1970static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1971 bool enable)
1972{
1973 uint32_t data = 0;
1974 uint32_t default_data = 0;
1975
1976 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1977
1978 if (enable == true) {
1979 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1980 if(default_data != data)
1981 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1982 } else {
1983 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1984 if(default_data != data)
1985 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1986 }
1987}
1988
3a6cc477
HZ		 1989static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1990 bool enable)
1991{
1992 uint32_t data = 0;
1993 uint32_t default_data = 0;
1994
1995 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1996
1997 if (enable == true) {
1998 data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
1999 if(default_data != data)
2000 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2001 } else {
2002 data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
2003 if(default_data != data)
2004 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2005 }
2006}
2007
197f95c8
HZ		 2008static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2009 bool enable)
2010{
2011 uint32_t data, default_data;
2012
2013 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2014 if (enable == true)
2015 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
2016 else
2017 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
2018 if(default_data != data)
2019 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2020}
2021
2022static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2023 bool enable)
2024{
2025 uint32_t data, default_data;
2026
2027 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2028 if (enable == true)
2029 data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
2030 else
2031 data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
2032 if(default_data != data)
2033 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2034
2035 if (!enable)
2036 /* read any GFX register to wake up GFX */
2037 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2038}
2039
18924c71
HZ		 2040void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2041 bool enable)
2042{
2043 uint32_t data, default_data;
2044
2045 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2046 if (enable == true)
2047 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2048 else
2049 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2050 if(default_data != data)
2051 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2052}
2053
2054void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2055 bool enable)
2056{
2057 uint32_t data, default_data;
2058
2059 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2060 if (enable == true)
2061 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2062 else
2063 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2064 if(default_data != data)
2065 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2066}
2067
6bce4667
HZ		 2068static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2069{
2070 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2071 AMD_PG_SUPPORT_GFX_SMG |
2072 AMD_PG_SUPPORT_GFX_DMG |
2073 AMD_PG_SUPPORT_CP |
2074 AMD_PG_SUPPORT_GDS |
2075 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2076 gfx_v9_0_init_csb(adev);
2077 gfx_v9_0_init_rlc_save_restore_list(adev);
2078 gfx_v9_0_enable_save_restore_machine(adev);
91d3130a
HZ		 2079
2080 if (adev->asic_type == CHIP_RAVEN) {
2081 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2082 adev->gfx.rlc.cp_table_gpu_addr >> 8);
2083 gfx_v9_0_init_gfx_power_gating(adev);
3a6cc477 2084
ed5ad1e4
HZ		 2085 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
2086 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
2087 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
2088 } else {
2089 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
2090 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
2091 }
3a6cc477
HZ		 2092
2093 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
2094 gfx_v9_0_enable_cp_power_gating(adev, true);
2095 else
2096 gfx_v9_0_enable_cp_power_gating(adev, false);
91d3130a 2097 }
6bce4667
HZ		 2098 }
2099}
2100
b1023571
KW		 2101void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2102{
5e78835a 2103 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 2104
2105 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5e78835a 2106 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
b1023571
KW		 2107
2108 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2109
2110 gfx_v9_0_wait_for_rlc_serdes(adev);
2111}
2112
2113static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2114{
596c8e8b 2115 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 2116 udelay(50);
596c8e8b 2117 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 2118 udelay(50);
2119}
2120
2121static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2122{
2123#ifdef AMDGPU_RLC_DEBUG_RETRY
2124 u32 rlc_ucode_ver;
2125#endif
b1023571 2126
342cda25 2127 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 2128
2129 /* carrizo do enable cp interrupt after cp inited */
2130 if (!(adev->flags & AMD_IS_APU))
2131 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2132
2133 udelay(50);
2134
2135#ifdef AMDGPU_RLC_DEBUG_RETRY
2136 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 2137 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 2138 if(rlc_ucode_ver == 0x108) {
2139 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2140 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2141 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2142 * default is 0x9C4 to create a 100us interval */
5e78835a 2143 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571 2144 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
eaa05d52 2145 * to disable the page fault retry interrupts, default is
b1023571 2146 * 0x100 (256) */
5e78835a 2147 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 2148 }
2149#endif
2150}
2151
2152static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2153{
2154 const struct rlc_firmware_header_v2_0 *hdr;
2155 const __le32 *fw_data;
2156 unsigned i, fw_size;
2157
2158 if (!adev->gfx.rlc_fw)
2159 return -EINVAL;
2160
2161 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2162 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2163
2164 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2165 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2166 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2167
5e78835a 2168 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 2169 RLCG_UCODE_LOADING_START_ADDRESS);
2170 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2171 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2172 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 2173
2174 return 0;
2175}
2176
2177static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2178{
2179 int r;
2180
cfee05bc
ML		 2181 if (amdgpu_sriov_vf(adev))
2182 return 0;
2183
b1023571
KW		 2184 gfx_v9_0_rlc_stop(adev);
2185
2186 /* disable CG */
5e78835a 2187 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 2188
2189 /* disable PG */
5e78835a 2190 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 2191
2192 gfx_v9_0_rlc_reset(adev);
2193
6bce4667
HZ		 2194 gfx_v9_0_init_pg(adev);
2195
b1023571
KW		 2196 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2197 /* legacy rlc firmware loading */
2198 r = gfx_v9_0_rlc_load_microcode(adev);
2199 if (r)
2200 return r;
2201 }
2202
e8835e0e
HZ		 2203 if (adev->asic_type == CHIP_RAVEN) {
2204 if (amdgpu_lbpw != 0)
2205 gfx_v9_0_enable_lbpw(adev, true);
2206 else
2207 gfx_v9_0_enable_lbpw(adev, false);
2208 }
2209
b1023571
KW		 2210 gfx_v9_0_rlc_start(adev);
2211
2212 return 0;
2213}
2214
2215static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2216{
2217 int i;
5e78835a 2218 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 2219
ea64468e
TSD		 2220 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2221 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2222 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2223 if (!enable) {
b1023571
KW		 2224 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2225 adev->gfx.gfx_ring[i].ready = false;
2226 }
5e78835a 2227 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 2228 udelay(50);
2229}
2230
2231static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2232{
2233 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2234 const struct gfx_firmware_header_v1_0 *ce_hdr;
2235 const struct gfx_firmware_header_v1_0 *me_hdr;
2236 const __le32 *fw_data;
2237 unsigned i, fw_size;
2238
2239 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2240 return -EINVAL;
2241
2242 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2243 adev->gfx.pfp_fw->data;
2244 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2245 adev->gfx.ce_fw->data;
2246 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2247 adev->gfx.me_fw->data;
2248
2249 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2250 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2251 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2252
2253 gfx_v9_0_cp_gfx_enable(adev, false);
2254
2255 /* PFP */
2256 fw_data = (const __le32 *)
2257 (adev->gfx.pfp_fw->data +
2258 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2259 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 2260 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 2261 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2262 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2263 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 2264
2265 /* CE */
2266 fw_data = (const __le32 *)
2267 (adev->gfx.ce_fw->data +
2268 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2269 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 2270 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 2271 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2272 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2273 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 2274
2275 /* ME */
2276 fw_data = (const __le32 *)
2277 (adev->gfx.me_fw->data +
2278 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2279 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 2280 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 2281 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2282 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2283 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 2284
2285 return 0;
2286}
2287
b1023571
KW		 2288static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2289{
2290 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2291 const struct cs_section_def *sect = NULL;
2292 const struct cs_extent_def *ext = NULL;
2293 int r, i;
2294
2295 /* init the CP */
5e78835a
TSD		 2296 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2297 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 2298
2299 gfx_v9_0_cp_gfx_enable(adev, true);
2300
2301 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
2302 if (r) {
2303 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2304 return r;
2305 }
2306
2307 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2308 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2309
2310 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2311 amdgpu_ring_write(ring, 0x80000000);
2312 amdgpu_ring_write(ring, 0x80000000);
2313
2314 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2315 for (ext = sect->section; ext->extent != NULL; ++ext) {
2316 if (sect->id == SECT_CONTEXT) {
2317 amdgpu_ring_write(ring,
2318 PACKET3(PACKET3_SET_CONTEXT_REG,
2319 ext->reg_count));
2320 amdgpu_ring_write(ring,
2321 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2322 for (i = 0; i < ext->reg_count; i++)
2323 amdgpu_ring_write(ring, ext->extent[i]);
2324 }
2325 }
2326 }
2327
2328 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2329 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2330
2331 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2332 amdgpu_ring_write(ring, 0);
2333
2334 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2335 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2336 amdgpu_ring_write(ring, 0x8000);
2337 amdgpu_ring_write(ring, 0x8000);
2338
2339 amdgpu_ring_commit(ring);
2340
2341 return 0;
2342}
2343
2344static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2345{
2346 struct amdgpu_ring *ring;
2347 u32 tmp;
2348 u32 rb_bufsz;
3fc08b61 2349 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 2350
2351 /* Set the write pointer delay */
5e78835a 2352 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 2353
2354 /* set the RB to use vmid 0 */
5e78835a 2355 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 2356
2357 /* Set ring buffer size */
2358 ring = &adev->gfx.gfx_ring[0];
2359 rb_bufsz = order_base_2(ring->ring_size / 8);
2360 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2361 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2362#ifdef __BIG_ENDIAN
2363 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2364#endif
5e78835a 2365 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2366
2367 /* Initialize the ring buffer's write pointers */
2368 ring->wptr = 0;
5e78835a
TSD		 2369 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2370 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2371
2372 /* set the wb address wether it's enabled or not */
2373 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 2374 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2375 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 2376
3fc08b61 2377 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 2378 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2379 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 2380
b1023571 2381 mdelay(1);
5e78835a 2382 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2383
2384 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 2385 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2386 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 2387
5e78835a 2388 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 2389 if (ring->use_doorbell) {
2390 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2391 DOORBELL_OFFSET, ring->doorbell_index);
2392 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2393 DOORBELL_EN, 1);
2394 } else {
2395 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2396 }
5e78835a 2397 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 2398
2399 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2400 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 2401 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 2402
5e78835a 2403 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 2404 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2405
2406
2407 /* start the ring */
2408 gfx_v9_0_cp_gfx_start(adev);
2409 ring->ready = true;
2410
2411 return 0;
2412}
2413
2414static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2415{
2416 int i;
2417
2418 if (enable) {
5e78835a 2419 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 2420 } else {
5e78835a 2421 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 2422 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2423 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2424 adev->gfx.compute_ring[i].ready = false;
ac104e99 2425 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 2426 }
2427 udelay(50);
2428}
2429
b1023571
KW		 2430static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2431{
2432 const struct gfx_firmware_header_v1_0 *mec_hdr;
2433 const __le32 *fw_data;
2434 unsigned i;
2435 u32 tmp;
2436
2437 if (!adev->gfx.mec_fw)
2438 return -EINVAL;
2439
2440 gfx_v9_0_cp_compute_enable(adev, false);
2441
2442 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2443 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2444
2445 fw_data = (const __le32 *)
2446 (adev->gfx.mec_fw->data +
2447 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2448 tmp = 0;
2449 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2450 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 2451 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 2452
5e78835a 2453 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 2454 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 2455 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571 2456 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
eaa05d52 2457
b1023571 2458 /* MEC1 */
5e78835a 2459 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2460 mec_hdr->jt_offset);
2461 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 2462 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 2463 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2464
5e78835a 2465 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2466 adev->gfx.mec_fw_version);
2467 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2468
2469 return 0;
2470}
2471
464826d6
XY		 2472/* KIQ functions */
2473static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2474{
2475 uint32_t tmp;
2476 struct amdgpu_device *adev = ring->adev;
2477
2478 /* tell RLC which is KIQ queue */
5e78835a 2479 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 2480 tmp &= 0xffffff00;
2481 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 2482 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2483 tmp |= 0x80;
5e78835a 2484 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6
XY		 2485}
2486
0f1dfd52 2487static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
464826d6 2488{
bd3402ea 2489 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2fdde9fa 2490 uint32_t scratch, tmp = 0;
de65513a 2491 uint64_t queue_mask = 0;
2fdde9fa
AD		 2492 int r, i;
2493
de65513a
AR		 2494 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2495 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2496 continue;
2497
2498 /* This situation may be hit in the future if a new HW
2499 * generation exposes more than 64 queues. If so, the
2500 * definition of queue_mask needs updating */
2501 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
2502 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2503 break;
2504 }
2505
2506 queue_mask |= (1ull << i);
2507 }
2508
2fdde9fa
AD		 2509 r = amdgpu_gfx_scratch_get(adev, &scratch);
2510 if (r) {
2511 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2512 return r;
2513 }
2514 WREG32(scratch, 0xCAFEDEAD);
2515
0f1dfd52 2516 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2fdde9fa
AD		 2517 if (r) {
2518 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2519 amdgpu_gfx_scratch_free(adev, scratch);
2520 return r;
2521 }
464826d6 2522
0f1dfd52
AD		 2523 /* set resources */
2524 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2525 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2526 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
de65513a
AR		 2527 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2528 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
0f1dfd52
AD		 2529 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2530 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2531 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2532 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
bd3402ea
AD		 2533 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2534 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2535 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2536 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2537
2538 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2539 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2540 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2541 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2542 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2543 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2544 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2545 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2546 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2547 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2548 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2549 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2550 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2551 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2552 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2553 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2554 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2555 }
2fdde9fa
AD		 2556 /* write to scratch for completion */
2557 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2558 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2559 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
464826d6 2560 amdgpu_ring_commit(kiq_ring);
2fdde9fa
AD		 2561
2562 for (i = 0; i < adev->usec_timeout; i++) {
2563 tmp = RREG32(scratch);
2564 if (tmp == 0xDEADBEEF)
2565 break;
2566 DRM_UDELAY(1);
2567 }
2568 if (i >= adev->usec_timeout) {
2569 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2570 scratch, tmp);
2571 r = -EINVAL;
2572 }
2573 amdgpu_gfx_scratch_free(adev, scratch);
2574
2575 return r;
464826d6
XY		 2576}
2577
e30a5223
AD		 2578static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
2579{
2580 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2581 uint32_t scratch, tmp = 0;
2582 int r, i;
2583
2584 r = amdgpu_gfx_scratch_get(adev, &scratch);
2585 if (r) {
2586 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2587 return r;
2588 }
2589 WREG32(scratch, 0xCAFEDEAD);
2590
2591 r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
2592 if (r) {
2593 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2594 amdgpu_gfx_scratch_free(adev, scratch);
2595 return r;
2596 }
2597 /* unmap queues */
2598 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
2599 amdgpu_ring_write(kiq_ring,
2600 PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
2601 PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all queues */
2602 amdgpu_ring_write(kiq_ring, 0);
2603 amdgpu_ring_write(kiq_ring, 0);
2604 amdgpu_ring_write(kiq_ring, 0);
2605 amdgpu_ring_write(kiq_ring, 0);
2606 /* write to scratch for completion */
2607 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2608 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2609 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2610 amdgpu_ring_commit(kiq_ring);
2611
2612 for (i = 0; i < adev->usec_timeout; i++) {
2613 tmp = RREG32(scratch);
2614 if (tmp == 0xDEADBEEF)
2615 break;
2616 DRM_UDELAY(1);
2617 }
2618 if (i >= adev->usec_timeout) {
2619 DRM_ERROR("KCQ disable failed (scratch(0x%04X)=0x%08X)\n",
2620 scratch, tmp);
2621 r = -EINVAL;
2622 }
2623 amdgpu_gfx_scratch_free(adev, scratch);
2624
2625 return r;
2626}
2627
e322edc3 2628static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 2629{
33fb8698 2630 struct amdgpu_device *adev = ring->adev;
e322edc3 2631 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2632 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2633 uint32_t tmp;
2634
2635 mqd->header = 0xC0310800;
2636 mqd->compute_pipelinestat_enable = 0x00000001;
2637 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2638 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2639 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2640 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2641 mqd->compute_misc_reserved = 0x00000003;
2642
d72f2f46 2643 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 2644 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2645 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2646
2647 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2648 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6 2649 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
268cb4c7 2650 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
464826d6
XY		 2651
2652 mqd->cp_hqd_eop_control = tmp;
2653
2654 /* enable doorbell? */
5e78835a 2655 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2656
2657 if (ring->use_doorbell) {
2658 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2659 DOORBELL_OFFSET, ring->doorbell_index);
2660 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2661 DOORBELL_EN, 1);
2662 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2663 DOORBELL_SOURCE, 0);
2664 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2665 DOORBELL_HIT, 0);
2666 }
2667 else
2668 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2669 DOORBELL_EN, 0);
2670
2671 mqd->cp_hqd_pq_doorbell_control = tmp;
2672
2673 /* disable the queue if it's active */
2674 ring->wptr = 0;
2675 mqd->cp_hqd_dequeue_request = 0;
2676 mqd->cp_hqd_pq_rptr = 0;
2677 mqd->cp_hqd_pq_wptr_lo = 0;
2678 mqd->cp_hqd_pq_wptr_hi = 0;
2679
2680 /* set the pointer to the MQD */
33fb8698
AD		 2681 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2682 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 2683
2684 /* set MQD vmid to 0 */
5e78835a 2685 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 2686 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2687 mqd->cp_mqd_control = tmp;
2688
2689 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2690 hqd_gpu_addr = ring->gpu_addr >> 8;
2691 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2692 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2693
2694 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2695 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 2696 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2697 (order_base_2(ring->ring_size / 4) - 1));
2698 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2699 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2700#ifdef __BIG_ENDIAN
2701 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2702#endif
2703 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2704 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2705 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2706 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2707 mqd->cp_hqd_pq_control = tmp;
2708
2709 /* set the wb address whether it's enabled or not */
2710 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2711 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2712 mqd->cp_hqd_pq_rptr_report_addr_hi =
2713 upper_32_bits(wb_gpu_addr) & 0xffff;
2714
2715 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2716 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2717 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2718 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2719
2720 tmp = 0;
2721 /* enable the doorbell if requested */
2722 if (ring->use_doorbell) {
5e78835a 2723 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2724 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2725 DOORBELL_OFFSET, ring->doorbell_index);
2726
2727 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2728 DOORBELL_EN, 1);
2729 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2730 DOORBELL_SOURCE, 0);
2731 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2732 DOORBELL_HIT, 0);
2733 }
2734
2735 mqd->cp_hqd_pq_doorbell_control = tmp;
2736
2737 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2738 ring->wptr = 0;
0274a9c5 2739 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 2740
2741 /* set the vmid for the queue */
2742 mqd->cp_hqd_vmid = 0;
2743
0274a9c5 2744 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 2745 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2746 mqd->cp_hqd_persistent_state = tmp;
2747
fca4ce69
AD		 2748 /* set MIN_IB_AVAIL_SIZE */
2749 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2750 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2751 mqd->cp_hqd_ib_control = tmp;
2752
464826d6
XY		 2753 /* activate the queue */
2754 mqd->cp_hqd_active = 1;
2755
2756 return 0;
2757}
2758
e322edc3 2759static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2760{
33fb8698 2761 struct amdgpu_device *adev = ring->adev;
e322edc3 2762 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2763 int j;
2764
2765 /* disable wptr polling */
72edadd5 2766 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2767
5e78835a 2768 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2769 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2770 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2771 mqd->cp_hqd_eop_base_addr_hi);
2772
2773 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2774 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2775 mqd->cp_hqd_eop_control);
2776
2777 /* enable doorbell? */
5e78835a 2778 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2779 mqd->cp_hqd_pq_doorbell_control);
2780
2781 /* disable the queue if it's active */
5e78835a
TSD		 2782 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2783 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2784 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2785 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2786 break;
2787 udelay(1);
2788 }
5e78835a 2789 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2790 mqd->cp_hqd_dequeue_request);
5e78835a 2791 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2792 mqd->cp_hqd_pq_rptr);
5e78835a 2793 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2794 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2795 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2796 mqd->cp_hqd_pq_wptr_hi);
2797 }
2798
2799 /* set the pointer to the MQD */
5e78835a 2800 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2801 mqd->cp_mqd_base_addr_lo);
5e78835a 2802 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2803 mqd->cp_mqd_base_addr_hi);
2804
2805 /* set MQD vmid to 0 */
5e78835a 2806 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2807 mqd->cp_mqd_control);
2808
2809 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2810 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2811 mqd->cp_hqd_pq_base_lo);
5e78835a 2812 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2813 mqd->cp_hqd_pq_base_hi);
2814
2815 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2816 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2817 mqd->cp_hqd_pq_control);
2818
2819 /* set the wb address whether it's enabled or not */
5e78835a 2820 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2821 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2822 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2823 mqd->cp_hqd_pq_rptr_report_addr_hi);
2824
2825 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2826 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2827 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2828 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2829 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2830
2831 /* enable the doorbell if requested */
2832 if (ring->use_doorbell) {
5e78835a 2833 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2834 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2835 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2836 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2837 }
2838
5e78835a 2839 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2840 mqd->cp_hqd_pq_doorbell_control);
2841
2842 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2843 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2844 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2845 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2846 mqd->cp_hqd_pq_wptr_hi);
2847
2848 /* set the vmid for the queue */
5e78835a 2849 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2850
5e78835a 2851 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2852 mqd->cp_hqd_persistent_state);
2853
2854 /* activate the queue */
5e78835a 2855 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2856 mqd->cp_hqd_active);
2857
72edadd5
TSD		 2858 if (ring->use_doorbell)
2859 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2860
2861 return 0;
2862}
2863
e322edc3 2864static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2865{
2866 struct amdgpu_device *adev = ring->adev;
e322edc3 2867 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2868 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2869
898b7893 2870 gfx_v9_0_kiq_setting(ring);
464826d6 2871
ba0c19f5 2872 if (adev->gfx.in_reset) { /* for GPU_RESET case */
464826d6 2873 /* reset MQD to a clean status */
0ef376ca
AD		 2874 if (adev->gfx.mec.mqd_backup[mqd_idx])
2875 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
464826d6
XY		 2876
2877 /* reset ring buffer */
2878 ring->wptr = 0;
b98724db 2879 amdgpu_ring_clear_ring(ring);
464826d6 2880
898b7893
AD		 2881 mutex_lock(&adev->srbm_mutex);
2882 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2883 gfx_v9_0_kiq_init_register(ring);
2884 soc15_grbm_select(adev, 0, 0, 0, 0);
2885 mutex_unlock(&adev->srbm_mutex);
ba0c19f5
AD		 2886 } else {
2887 memset((void *)mqd, 0, sizeof(*mqd));
2888 mutex_lock(&adev->srbm_mutex);
2889 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2890 gfx_v9_0_mqd_init(ring);
2891 gfx_v9_0_kiq_init_register(ring);
2892 soc15_grbm_select(adev, 0, 0, 0, 0);
2893 mutex_unlock(&adev->srbm_mutex);
2894
2895 if (adev->gfx.mec.mqd_backup[mqd_idx])
2896 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
464826d6
XY		 2897 }
2898
0f1dfd52 2899 return 0;
898b7893
AD		 2900}
2901
2902static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2903{
2904 struct amdgpu_device *adev = ring->adev;
898b7893
AD		 2905 struct v9_mqd *mqd = ring->mqd_ptr;
2906 int mqd_idx = ring - &adev->gfx.compute_ring[0];
898b7893 2907
e30a5223 2908 if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
898b7893
AD		 2909 memset((void *)mqd, 0, sizeof(*mqd));
2910 mutex_lock(&adev->srbm_mutex);
2911 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2912 gfx_v9_0_mqd_init(ring);
2913 soc15_grbm_select(adev, 0, 0, 0, 0);
2914 mutex_unlock(&adev->srbm_mutex);
2915
2916 if (adev->gfx.mec.mqd_backup[mqd_idx])
2917 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
ba0c19f5 2918 } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
898b7893
AD		 2919 /* reset MQD to a clean status */
2920 if (adev->gfx.mec.mqd_backup[mqd_idx])
2921 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
2922
2923 /* reset ring buffer */
2924 ring->wptr = 0;
2925 amdgpu_ring_clear_ring(ring);
ba0c19f5
AD		 2926 } else {
2927 amdgpu_ring_clear_ring(ring);
898b7893
AD		 2928 }
2929
bd3402ea 2930 return 0;
464826d6
XY		 2931}
2932
2933static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2934{
2935 struct amdgpu_ring *ring = NULL;
2936 int r = 0, i;
2937
2938 gfx_v9_0_cp_compute_enable(adev, true);
2939
2940 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2941
2942 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2943 if (unlikely(r != 0))
2944 goto done;
2945
2946 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2947 if (!r) {
e322edc3 2948 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2949 amdgpu_bo_kunmap(ring->mqd_obj);
2950 ring->mqd_ptr = NULL;
464826d6 2951 }
e1d53aa8
AD		 2952 amdgpu_bo_unreserve(ring->mqd_obj);
2953 if (r)
2954 goto done;
464826d6
XY		 2955
2956 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2957 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2958
2959 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2960 if (unlikely(r != 0))
2961 goto done;
2962 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2963 if (!r) {
898b7893 2964 r = gfx_v9_0_kcq_init_queue(ring);
464826d6
XY		 2965 amdgpu_bo_kunmap(ring->mqd_obj);
2966 ring->mqd_ptr = NULL;
464826d6 2967 }
e1d53aa8
AD		 2968 amdgpu_bo_unreserve(ring->mqd_obj);
2969 if (r)
2970 goto done;
464826d6
XY		 2971 }
2972
0f1dfd52 2973 r = gfx_v9_0_kiq_kcq_enable(adev);
e1d53aa8
AD		 2974done:
2975 return r;
464826d6
XY		 2976}
2977
b1023571
KW		 2978static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2979{
bd3402ea 2980 int r, i;
b1023571
KW		 2981 struct amdgpu_ring *ring;
2982
2983 if (!(adev->flags & AMD_IS_APU))
2984 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2985
2986 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2987 /* legacy firmware loading */
2988 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2989 if (r)
2990 return r;
2991
2992 r = gfx_v9_0_cp_compute_load_microcode(adev);
2993 if (r)
2994 return r;
2995 }
2996
2997 r = gfx_v9_0_cp_gfx_resume(adev);
2998 if (r)
2999 return r;
3000
e30a5223 3001 r = gfx_v9_0_kiq_resume(adev);
b1023571
KW		 3002 if (r)
3003 return r;
3004
3005 ring = &adev->gfx.gfx_ring[0];
3006 r = amdgpu_ring_test_ring(ring);
3007 if (r) {
3008 ring->ready = false;
3009 return r;
3010 }
e30a5223
AD		 3011
3012 ring = &adev->gfx.kiq.ring;
3013 ring->ready = true;
3014 r = amdgpu_ring_test_ring(ring);
3015 if (r)
3016 ring->ready = false;
3017
b1023571
KW		 3018 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3019 ring = &adev->gfx.compute_ring[i];
3020
3021 ring->ready = true;
3022 r = amdgpu_ring_test_ring(ring);
3023 if (r)
3024 ring->ready = false;
3025 }
3026
3027 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3028
3029 return 0;
3030}
3031
3032static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3033{
3034 gfx_v9_0_cp_gfx_enable(adev, enable);
3035 gfx_v9_0_cp_compute_enable(adev, enable);
3036}
3037
3038static int gfx_v9_0_hw_init(void *handle)
3039{
3040 int r;
3041 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3042
3043 gfx_v9_0_init_golden_registers(adev);
3044
3045 gfx_v9_0_gpu_init(adev);
3046
3047 r = gfx_v9_0_rlc_resume(adev);
3048 if (r)
3049 return r;
3050
3051 r = gfx_v9_0_cp_resume(adev);
3052 if (r)
3053 return r;
3054
3055 r = gfx_v9_0_ngg_en(adev);
3056 if (r)
3057 return r;
3058
3059 return r;
3060}
3061
3062static int gfx_v9_0_hw_fini(void *handle)
3063{
3064 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3065
3066 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3067 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
464826d6
XY		 3068 if (amdgpu_sriov_vf(adev)) {
3069 pr_debug("For SRIOV client, shouldn't do anything.\n");
3070 return 0;
3071 }
e30a5223 3072 gfx_v9_0_kiq_kcq_disable(adev);
b1023571
KW		 3073 gfx_v9_0_cp_enable(adev, false);
3074 gfx_v9_0_rlc_stop(adev);
b1023571
KW		 3075
3076 return 0;
3077}
3078
3079static int gfx_v9_0_suspend(void *handle)
3080{
3081 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3082
e30a5223 3083 adev->gfx.in_suspend = true;
b1023571
KW		 3084 return gfx_v9_0_hw_fini(adev);
3085}
3086
3087static int gfx_v9_0_resume(void *handle)
3088{
3089 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e30a5223 3090 int r;
b1023571 3091
e30a5223
AD		 3092 r = gfx_v9_0_hw_init(adev);
3093 adev->gfx.in_suspend = false;
3094 return r;
b1023571
KW		 3095}
3096
3097static bool gfx_v9_0_is_idle(void *handle)
3098{
3099 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3100
5e78835a 3101 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 3102 GRBM_STATUS, GUI_ACTIVE))
3103 return false;
3104 else
3105 return true;
3106}
3107
3108static int gfx_v9_0_wait_for_idle(void *handle)
3109{
3110 unsigned i;
3111 u32 tmp;
3112 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3113
3114 for (i = 0; i < adev->usec_timeout; i++) {
3115 /* read MC_STATUS */
5e78835a 3116 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
b1023571
KW		 3117 GRBM_STATUS__GUI_ACTIVE_MASK;
3118
3119 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3120 return 0;
3121 udelay(1);
3122 }
3123 return -ETIMEDOUT;
3124}
3125
b1023571
KW		 3126static int gfx_v9_0_soft_reset(void *handle)
3127{
3128 u32 grbm_soft_reset = 0;
3129 u32 tmp;
3130 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3131
3132 /* GRBM_STATUS */
5e78835a 3133 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 3134 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3135 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3136 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3137 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3138 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3139 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3140 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3141 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3142 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3143 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3144 }
3145
3146 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3147 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3148 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3149 }
3150
3151 /* GRBM_STATUS2 */
5e78835a 3152 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 3153 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3154 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3155 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3156
3157
75bac5c6 3158 if (grbm_soft_reset) {
b1023571
KW		 3159 /* stop the rlc */
3160 gfx_v9_0_rlc_stop(adev);
3161
3162 /* Disable GFX parsing/prefetching */
3163 gfx_v9_0_cp_gfx_enable(adev, false);
3164
3165 /* Disable MEC parsing/prefetching */
3166 gfx_v9_0_cp_compute_enable(adev, false);
3167
3168 if (grbm_soft_reset) {
5e78835a 3169 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3170 tmp |= grbm_soft_reset;
3171 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 3172 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3173 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3174
3175 udelay(50);
3176
3177 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 3178 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3179 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3180 }
3181
3182 /* Wait a little for things to settle down */
3183 udelay(50);
b1023571
KW		 3184 }
3185 return 0;
3186}
3187
3188static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3189{
3190 uint64_t clock;
3191
3192 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 3193 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3194 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3195 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 3196 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3197 return clock;
3198}
3199
3200static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3201 uint32_t vmid,
3202 uint32_t gds_base, uint32_t gds_size,
3203 uint32_t gws_base, uint32_t gws_size,
3204 uint32_t oa_base, uint32_t oa_size)
3205{
3206 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3207 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3208
3209 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3210 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3211
3212 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3213 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3214
3215 /* GDS Base */
3216 gfx_v9_0_write_data_to_reg(ring, 0, false,
3217 amdgpu_gds_reg_offset[vmid].mem_base,
3218 gds_base);
3219
3220 /* GDS Size */
3221 gfx_v9_0_write_data_to_reg(ring, 0, false,
3222 amdgpu_gds_reg_offset[vmid].mem_size,
3223 gds_size);
3224
3225 /* GWS */
3226 gfx_v9_0_write_data_to_reg(ring, 0, false,
3227 amdgpu_gds_reg_offset[vmid].gws,
3228 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3229
3230 /* OA */
3231 gfx_v9_0_write_data_to_reg(ring, 0, false,
3232 amdgpu_gds_reg_offset[vmid].oa,
3233 (1 << (oa_size + oa_base)) - (1 << oa_base));
3234}
3235
3236static int gfx_v9_0_early_init(void *handle)
3237{
3238 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3239
3240 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
78c16834 3241 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
b1023571
KW		 3242 gfx_v9_0_set_ring_funcs(adev);
3243 gfx_v9_0_set_irq_funcs(adev);
3244 gfx_v9_0_set_gds_init(adev);
3245 gfx_v9_0_set_rlc_funcs(adev);
3246
3247 return 0;
3248}
3249
3250static int gfx_v9_0_late_init(void *handle)
3251{
3252 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3253 int r;
3254
3255 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3256 if (r)
3257 return r;
3258
3259 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3260 if (r)
3261 return r;
3262
3263 return 0;
3264}
3265
3266static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3267{
3268 uint32_t rlc_setting, data;
3269 unsigned i;
3270
3271 if (adev->gfx.rlc.in_safe_mode)
3272 return;
3273
3274 /* if RLC is not enabled, do nothing */
5e78835a 3275 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3276 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3277 return;
3278
3279 if (adev->cg_flags &
3280 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3281 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3282 data = RLC_SAFE_MODE__CMD_MASK;
3283 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 3284 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3285
3286 /* wait for RLC_SAFE_MODE */
3287 for (i = 0; i < adev->usec_timeout; i++) {
3288 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3289 break;
3290 udelay(1);
3291 }
3292 adev->gfx.rlc.in_safe_mode = true;
3293 }
3294}
3295
3296static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3297{
3298 uint32_t rlc_setting, data;
3299
3300 if (!adev->gfx.rlc.in_safe_mode)
3301 return;
3302
3303 /* if RLC is not enabled, do nothing */
5e78835a 3304 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3305 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3306 return;
3307
3308 if (adev->cg_flags &
3309 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3310 /*
3311 * Try to exit safe mode only if it is already in safe
3312 * mode.
3313 */
3314 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 3315 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3316 adev->gfx.rlc.in_safe_mode = false;
3317 }
3318}
3319
197f95c8
HZ		 3320static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3321 bool enable)
3322{
3323 /* TODO: double check if we need to perform under safe mdoe */
3324 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3325
3326 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3327 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3328 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3329 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3330 } else {
3331 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3332 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3333 }
3334
3335 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3336}
3337
18924c71
HZ		 3338static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3339 bool enable)
3340{
3341 /* TODO: double check if we need to perform under safe mode */
3342 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3343
3344 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3345 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3346 else
3347 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3348
3349 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3350 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3351 else
3352 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3353
3354 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3355}
3356
b1023571
KW		 3357static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3358 bool enable)
3359{
3360 uint32_t data, def;
3361
3362 /* It is disabled by HW by default */
3363 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3364 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 3365 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3366 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3367 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3368 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3369 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3370
3371 /* only for Vega10 & Raven1 */
3372 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3373
3374 if (def != data)
5e78835a 3375 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3376
3377 /* MGLS is a global flag to control all MGLS in GFX */
3378 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3379 /* 2 - RLC memory Light sleep */
3380 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 3381 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3382 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3383 if (def != data)
5e78835a 3384 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3385 }
3386 /* 3 - CP memory Light sleep */
3387 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 3388 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3389 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3390 if (def != data)
5e78835a 3391 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3392 }
3393 }
3394 } else {
3395 /* 1 - MGCG_OVERRIDE */
5e78835a 3396 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3397 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3398 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3399 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3400 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3401 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3402 if (def != data)
5e78835a 3403 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3404
3405 /* 2 - disable MGLS in RLC */
5e78835a 3406 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3407 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3408 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 3409 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3410 }
3411
3412 /* 3 - disable MGLS in CP */
5e78835a 3413 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3414 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3415 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 3416 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3417 }
3418 }
3419}
3420
3421static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3422 bool enable)
3423{
3424 uint32_t data, def;
3425
3426 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3427
3428 /* Enable 3D CGCG/CGLS */
3429 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3430 /* write cmd to clear cgcg/cgls ov */
5e78835a 3431 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3432 /* unset CGCG override */
3433 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3434 /* update CGCG and CGLS override bits */
3435 if (def != data)
5e78835a 3436 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 3437 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 3438 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3439 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3440 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3441 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3442 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3443 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3444 if (def != data)
5e78835a 3445 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3446
3447 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3448 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3449 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3450 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3451 if (def != data)
5e78835a 3452 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 3453 } else {
3454 /* Disable CGCG/CGLS */
5e78835a 3455 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3456 /* disable cgcg, cgls should be disabled */
3457 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3458 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3459 /* disable cgcg and cgls in FSM */
3460 if (def != data)
5e78835a 3461 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3462 }
3463
3464 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3465}
3466
3467static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3468 bool enable)
3469{
3470 uint32_t def, data;
3471
3472 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3473
3474 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 3475 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3476 /* unset CGCG override */
3477 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3478 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3479 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3480 else
3481 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3482 /* update CGCG and CGLS override bits */
3483 if (def != data)
5e78835a 3484 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3485
3486 /* enable cgcg FSM(0x0020003F) */
5e78835a 3487 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3488 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3489 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3490 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3491 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3492 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3493 if (def != data)
5e78835a 3494 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3495
3496 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3497 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3498 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3499 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3500 if (def != data)
5e78835a 3501 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 3502 } else {
5e78835a 3503 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3504 /* reset CGCG/CGLS bits */
3505 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3506 /* disable cgcg and cgls in FSM */
3507 if (def != data)
5e78835a 3508 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3509 }
3510
3511 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3512}
3513
3514static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3515 bool enable)
3516{
3517 if (enable) {
3518 /* CGCG/CGLS should be enabled after MGCG/MGLS
3519 * === MGCG + MGLS ===
3520 */
3521 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3522 /* === CGCG /CGLS for GFX 3D Only === */
3523 gfx_v9_0_update_3d_clock_gating(adev, enable);
3524 /* === CGCG + CGLS === */
3525 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3526 } else {
3527 /* CGCG/CGLS should be disabled before MGCG/MGLS
3528 * === CGCG + CGLS ===
3529 */
3530 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3531 /* === CGCG /CGLS for GFX 3D Only === */
3532 gfx_v9_0_update_3d_clock_gating(adev, enable);
3533 /* === MGCG + MGLS === */
3534 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3535 }
3536 return 0;
3537}
3538
3539static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3540 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3541 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3542};
3543
3544static int gfx_v9_0_set_powergating_state(void *handle,
3545 enum amd_powergating_state state)
3546{
5897c99e 3547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197f95c8 3548 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
5897c99e
HZ		 3549
3550 switch (adev->asic_type) {
3551 case CHIP_RAVEN:
3552 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3553 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3554 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3555 } else {
3556 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3557 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3558 }
3559
3560 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3561 gfx_v9_0_enable_cp_power_gating(adev, true);
3562 else
3563 gfx_v9_0_enable_cp_power_gating(adev, false);
197f95c8
HZ		 3564
3565 /* update gfx cgpg state */
3566 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
18924c71
HZ		 3567
3568 /* update mgcg state */
3569 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5897c99e
HZ		 3570 break;
3571 default:
3572 break;
3573 }
3574
b1023571
KW		 3575 return 0;
3576}
3577
3578static int gfx_v9_0_set_clockgating_state(void *handle,
3579 enum amd_clockgating_state state)
3580{
3581 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3582
fb82afab
XY		 3583 if (amdgpu_sriov_vf(adev))
3584 return 0;
3585
b1023571
KW		 3586 switch (adev->asic_type) {
3587 case CHIP_VEGA10:
a4dc61f5 3588 case CHIP_RAVEN:
b1023571
KW		 3589 gfx_v9_0_update_gfx_clock_gating(adev,
3590 state == AMD_CG_STATE_GATE ? true : false);
3591 break;
3592 default:
3593 break;
3594 }
3595 return 0;
3596}
3597
12ad27fa
HR		 3598static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3599{
3600 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3601 int data;
3602
3603 if (amdgpu_sriov_vf(adev))
3604 *flags = 0;
3605
3606 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 3607 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 3608 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3609 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3610
3611 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 3612 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 3613 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3614 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3615
3616 /* AMD_CG_SUPPORT_GFX_CGLS */
3617 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3618 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3619
3620 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 3621 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 3622 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3623 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3624
3625 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 3626 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 3627 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3628 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3629
3630 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 3631 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 3632 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3633 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3634
3635 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3636 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3637 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3638}
3639
b1023571
KW		 3640static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3641{
3642 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3643}
3644
3645static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3646{
3647 struct amdgpu_device *adev = ring->adev;
3648 u64 wptr;
3649
3650 /* XXX check if swapping is necessary on BE */
3651 if (ring->use_doorbell) {
3652 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3653 } else {
5e78835a
TSD		 3654 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3655 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 3656 }
3657
3658 return wptr;
3659}
3660
3661static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3662{
3663 struct amdgpu_device *adev = ring->adev;
3664
3665 if (ring->use_doorbell) {
3666 /* XXX check if swapping is necessary on BE */
3667 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3668 WDOORBELL64(ring->doorbell_index, ring->wptr);
3669 } else {
5e78835a
TSD		 3670 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3671 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 3672 }
3673}
3674
3675static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3676{
3677 u32 ref_and_mask, reg_mem_engine;
3678 struct nbio_hdp_flush_reg *nbio_hf_reg;
3679
3680 if (ring->adev->asic_type == CHIP_VEGA10)
3681 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3682
3683 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3684 switch (ring->me) {
3685 case 1:
3686 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3687 break;
3688 case 2:
3689 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3690 break;
3691 default:
3692 return;
3693 }
3694 reg_mem_engine = 0;
3695 } else {
3696 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3697 reg_mem_engine = 1; /* pfp */
3698 }
3699
3700 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3701 nbio_hf_reg->hdp_flush_req_offset,
3702 nbio_hf_reg->hdp_flush_done_offset,
3703 ref_and_mask, ref_and_mask, 0x20);
3704}
3705
3706static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3707{
3708 gfx_v9_0_write_data_to_reg(ring, 0, true,
3709 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3710}
3711
3712static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3713 struct amdgpu_ib *ib,
3714 unsigned vm_id, bool ctx_switch)
3715{
eaa05d52 3716 u32 header, control = 0;
b1023571 3717
eaa05d52
ML		 3718 if (ib->flags & AMDGPU_IB_FLAG_CE)
3719 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3720 else
3721 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
b1023571 3722
eaa05d52 3723 control |= ib->length_dw | (vm_id << 24);
b1023571 3724
635e7132 3725 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
eaa05d52 3726 control |= INDIRECT_BUFFER_PRE_ENB(1);
9ccd52eb 3727
635e7132
ML		 3728 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3729 gfx_v9_0_ring_emit_de_meta(ring);
3730 }
3731
eaa05d52
ML		 3732 amdgpu_ring_write(ring, header);
3733BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3734 amdgpu_ring_write(ring,
b1023571 3735#ifdef __BIG_ENDIAN
eaa05d52 3736 (2 << 0) |
b1023571 3737#endif
eaa05d52
ML		 3738 lower_32_bits(ib->gpu_addr));
3739 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3740 amdgpu_ring_write(ring, control);
b1023571
KW		 3741}
3742
b1023571
KW		 3743static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3744 struct amdgpu_ib *ib,
3745 unsigned vm_id, bool ctx_switch)
3746{
3747 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3748
3749 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3750 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3751 amdgpu_ring_write(ring,
3752#ifdef __BIG_ENDIAN
3753 (2 << 0) |
3754#endif
3755 lower_32_bits(ib->gpu_addr));
3756 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3757 amdgpu_ring_write(ring, control);
3758}
3759
3760static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3761 u64 seq, unsigned flags)
3762{
3763 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3764 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3765
3766 /* RELEASE_MEM - flush caches, send int */
3767 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3768 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3769 EOP_TC_ACTION_EN |
3770 EOP_TC_WB_ACTION_EN |
3771 EOP_TC_MD_ACTION_EN |
3772 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3773 EVENT_INDEX(5)));
3774 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3775
3776 /*
3777 * the address should be Qword aligned if 64bit write, Dword
3778 * aligned if only send 32bit data low (discard data high)
3779 */
3780 if (write64bit)
3781 BUG_ON(addr & 0x7);
3782 else
3783 BUG_ON(addr & 0x3);
3784 amdgpu_ring_write(ring, lower_32_bits(addr));
3785 amdgpu_ring_write(ring, upper_32_bits(addr));
3786 amdgpu_ring_write(ring, lower_32_bits(seq));
3787 amdgpu_ring_write(ring, upper_32_bits(seq));
3788 amdgpu_ring_write(ring, 0);
3789}
3790
3791static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3792{
3793 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3794 uint32_t seq = ring->fence_drv.sync_seq;
3795 uint64_t addr = ring->fence_drv.gpu_addr;
3796
3797 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3798 lower_32_bits(addr), upper_32_bits(addr),
3799 seq, 0xffffffff, 4);
3800}
3801
3802static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3803 unsigned vm_id, uint64_t pd_addr)
3804{
2e819849 3805 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
b1023571 3806 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 3807 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 3808 unsigned eng = ring->vm_inv_eng;
b1023571 3809
b1166325
CK		 3810 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3811 pd_addr |= AMDGPU_PTE_VALID;
b1023571 3812
2e819849
CK		 3813 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3814 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3815 lower_32_bits(pd_addr));
b1023571 3816
2e819849
CK		 3817 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3818 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3819 upper_32_bits(pd_addr));
b1023571 3820
2e819849
CK		 3821 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3822 hub->vm_inv_eng0_req + eng, req);
b1023571 3823
2e819849
CK		 3824 /* wait for the invalidate to complete */
3825 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3826 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
b1023571
KW		 3827
3828 /* compute doesn't have PFP */
3829 if (usepfp) {
3830 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3831 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3832 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3833 }
3834}
3835
3836static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3837{
3838 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3839}
3840
3841static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3842{
3843 u64 wptr;
3844
3845 /* XXX check if swapping is necessary on BE */
3846 if (ring->use_doorbell)
3847 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3848 else
3849 BUG();
3850 return wptr;
3851}
3852
3853static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3854{
3855 struct amdgpu_device *adev = ring->adev;
3856
3857 /* XXX check if swapping is necessary on BE */
3858 if (ring->use_doorbell) {
3859 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3860 WDOORBELL64(ring->doorbell_index, ring->wptr);
3861 } else{
3862 BUG(); /* only DOORBELL method supported on gfx9 now */
3863 }
3864}
3865
aa6faa44
XY		 3866static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3867 u64 seq, unsigned int flags)
3868{
3869 /* we only allocate 32bit for each seq wb address */
3870 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3871
3872 /* write fence seq to the "addr" */
3873 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3874 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3875 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3876 amdgpu_ring_write(ring, lower_32_bits(addr));
3877 amdgpu_ring_write(ring, upper_32_bits(addr));
3878 amdgpu_ring_write(ring, lower_32_bits(seq));
3879
3880 if (flags & AMDGPU_FENCE_FLAG_INT) {
3881 /* set register to trigger INT */
3882 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3883 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3884 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3885 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3886 amdgpu_ring_write(ring, 0);
3887 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3888 }
3889}
3890
b1023571
KW		 3891static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3892{
3893 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3894 amdgpu_ring_write(ring, 0);
3895}
3896
cca02cd3
XY		 3897static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3898{
3899 static struct v9_ce_ib_state ce_payload = {0};
3900 uint64_t csa_addr;
3901 int cnt;
3902
3903 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3904 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3905
3906 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3907 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3908 WRITE_DATA_DST_SEL(8) |
3909 WR_CONFIRM) |
3910 WRITE_DATA_CACHE_POLICY(0));
3911 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3912 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3913 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3914}
3915
3916static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3917{
3918 static struct v9_de_ib_state de_payload = {0};
3919 uint64_t csa_addr, gds_addr;
3920 int cnt;
3921
3922 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3923 gds_addr = csa_addr + 4096;
3924 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3925 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3926
3927 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3928 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3929 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3930 WRITE_DATA_DST_SEL(8) |
3931 WR_CONFIRM) |
3932 WRITE_DATA_CACHE_POLICY(0));
3933 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3934 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3935 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3936}
3937
b1023571
KW		 3938static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3939{
3940 uint32_t dw2 = 0;
3941
cca02cd3
XY		 3942 if (amdgpu_sriov_vf(ring->adev))
3943 gfx_v9_0_ring_emit_ce_meta(ring);
3944
b1023571
KW		 3945 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3946 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3947 /* set load_global_config & load_global_uconfig */
3948 dw2 |= 0x8001;
3949 /* set load_cs_sh_regs */
3950 dw2 |= 0x01000000;
3951 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3952 dw2 |= 0x10002;
3953
3954 /* set load_ce_ram if preamble presented */
3955 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3956 dw2 |= 0x10000000;
3957 } else {
3958 /* still load_ce_ram if this is the first time preamble presented
3959 * although there is no context switch happens.
3960 */
3961 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3962 dw2 |= 0x10000000;
3963 }
3964
3965 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3966 amdgpu_ring_write(ring, dw2);
3967 amdgpu_ring_write(ring, 0);
3968}
3969
9a5e02b5
ML		 3970static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3971{
3972 unsigned ret;
3973 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3974 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3975 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3976 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3977 ret = ring->wptr & ring->buf_mask;
3978 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3979 return ret;
3980}
3981
3982static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3983{
3984 unsigned cur;
3985 BUG_ON(offset > ring->buf_mask);
3986 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3987
3988 cur = (ring->wptr & ring->buf_mask) - 1;
3989 if (likely(cur > offset))
3990 ring->ring[offset] = cur - offset;
3991 else
3992 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3993}
3994
3b4d68e9
ML		 3995static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3996{
3997 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3998 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3999}
4000
aa6faa44
XY		 4001static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4002{
4003 struct amdgpu_device *adev = ring->adev;
4004
4005 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4006 amdgpu_ring_write(ring, 0 | /* src: register*/
4007 (5 << 8) | /* dst: memory */
4008 (1 << 20)); /* write confirm */
4009 amdgpu_ring_write(ring, reg);
4010 amdgpu_ring_write(ring, 0);
4011 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4012 adev->virt.reg_val_offs * 4));
4013 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4014 adev->virt.reg_val_offs * 4));
4015}
4016
4017static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4018 uint32_t val)
4019{
4020 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4021 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
4022 amdgpu_ring_write(ring, reg);
4023 amdgpu_ring_write(ring, 0);
4024 amdgpu_ring_write(ring, val);
4025}
4026
b1023571
KW		 4027static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4028 enum amdgpu_interrupt_state state)
4029{
b1023571
KW		 4030 switch (state) {
4031 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4032 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 4033 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4034 TIME_STAMP_INT_ENABLE,
4035 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4036 break;
4037 default:
4038 break;
4039 }
4040}
4041
4042static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4043 int me, int pipe,
4044 enum amdgpu_interrupt_state state)
4045{
763a47b8
AR		 4046 /* Me 0 is reserved for graphics */
4047 if (me < 1 || me > adev->gfx.mec.num_mec) {
4048 DRM_ERROR("Ignoring request to enable interrupts for invalid me:%d\n", me);
b1023571
KW		 4049 return;
4050 }
4051
763a47b8
AR		 4052 if (pipe >= adev->gfx.mec.num_pipe_per_mec) {
4053 DRM_ERROR("Ignoring request to enable interrupts for invalid "
4054 "me:%d pipe:%d\n", pipe, me);
4055 return;
b1023571 4056 }
763a47b8
AR		 4057
4058 mutex_lock(&adev->srbm_mutex);
4059 soc15_grbm_select(adev, me, pipe, 0, 0);
4060
4061 WREG32_FIELD(CPC_INT_CNTL, TIME_STAMP_INT_ENABLE,
4062 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
4063
4064 soc15_grbm_select(adev, 0, 0, 0, 0);
4065 mutex_unlock(&adev->srbm_mutex);
b1023571
KW		 4066}
4067
4068static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4069 struct amdgpu_irq_src *source,
4070 unsigned type,
4071 enum amdgpu_interrupt_state state)
4072{
b1023571
KW		 4073 switch (state) {
4074 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4075 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 4076 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4077 PRIV_REG_INT_ENABLE,
4078 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4079 break;
4080 default:
4081 break;
4082 }
4083
4084 return 0;
4085}
4086
4087static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4088 struct amdgpu_irq_src *source,
4089 unsigned type,
4090 enum amdgpu_interrupt_state state)
4091{
b1023571
KW		 4092 switch (state) {
4093 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4094 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 4095 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4096 PRIV_INSTR_INT_ENABLE,
4097 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4098 default:
4099 break;
4100 }
4101
4102 return 0;
4103}
4104
4105static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4106 struct amdgpu_irq_src *src,
4107 unsigned type,
4108 enum amdgpu_interrupt_state state)
4109{
4110 switch (type) {
4111 case AMDGPU_CP_IRQ_GFX_EOP:
4112 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4113 break;
4114 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4115 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4116 break;
4117 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4118 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4119 break;
4120 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4121 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4122 break;
4123 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4124 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4125 break;
4126 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4127 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4128 break;
4129 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4130 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4131 break;
4132 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4133 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4134 break;
4135 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4136 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4137 break;
4138 default:
4139 break;
4140 }
4141 return 0;
4142}
4143
4144static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4145 struct amdgpu_irq_src *source,
4146 struct amdgpu_iv_entry *entry)
4147{
4148 int i;
4149 u8 me_id, pipe_id, queue_id;
4150 struct amdgpu_ring *ring;
4151
4152 DRM_DEBUG("IH: CP EOP\n");
4153 me_id = (entry->ring_id & 0x0c) >> 2;
4154 pipe_id = (entry->ring_id & 0x03) >> 0;
4155 queue_id = (entry->ring_id & 0x70) >> 4;
4156
4157 switch (me_id) {
4158 case 0:
4159 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4160 break;
4161 case 1:
4162 case 2:
4163 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4164 ring = &adev->gfx.compute_ring[i];
4165 /* Per-queue interrupt is supported for MEC starting from VI.
4166 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4167 */
4168 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4169 amdgpu_fence_process(ring);
4170 }
4171 break;
4172 }
4173 return 0;
4174}
4175
4176static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4177 struct amdgpu_irq_src *source,
4178 struct amdgpu_iv_entry *entry)
4179{
4180 DRM_ERROR("Illegal register access in command stream\n");
4181 schedule_work(&adev->reset_work);
4182 return 0;
4183}
4184
4185static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4186 struct amdgpu_irq_src *source,
4187 struct amdgpu_iv_entry *entry)
4188{
4189 DRM_ERROR("Illegal instruction in command stream\n");
4190 schedule_work(&adev->reset_work);
4191 return 0;
4192}
4193
97031e25
XY		 4194static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4195 struct amdgpu_irq_src *src,
4196 unsigned int type,
4197 enum amdgpu_interrupt_state state)
4198{
4199 uint32_t tmp, target;
1c4ecf48 4200 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4201
4202 if (ring->me == 1)
4203 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4204 else
4205 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4206 target += ring->pipe;
4207
4208 switch (type) {
4209 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4210 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 4211 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4212 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4213 GENERIC2_INT_ENABLE, 0);
5e78835a 4214 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4215
4216 tmp = RREG32(target);
4217 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4218 GENERIC2_INT_ENABLE, 0);
4219 WREG32(target, tmp);
4220 } else {
5e78835a 4221 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4222 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4223 GENERIC2_INT_ENABLE, 1);
5e78835a 4224 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4225
4226 tmp = RREG32(target);
4227 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4228 GENERIC2_INT_ENABLE, 1);
4229 WREG32(target, tmp);
4230 }
4231 break;
4232 default:
4233 BUG(); /* kiq only support GENERIC2_INT now */
4234 break;
4235 }
4236 return 0;
4237}
4238
4239static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4240 struct amdgpu_irq_src *source,
4241 struct amdgpu_iv_entry *entry)
4242{
4243 u8 me_id, pipe_id, queue_id;
1c4ecf48 4244 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4245
4246 me_id = (entry->ring_id & 0x0c) >> 2;
4247 pipe_id = (entry->ring_id & 0x03) >> 0;
4248 queue_id = (entry->ring_id & 0x70) >> 4;
4249 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4250 me_id, pipe_id, queue_id);
4251
4252 amdgpu_fence_process(ring);
4253 return 0;
4254}
4255
b1023571
KW		 4256const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4257 .name = "gfx_v9_0",
4258 .early_init = gfx_v9_0_early_init,
4259 .late_init = gfx_v9_0_late_init,
4260 .sw_init = gfx_v9_0_sw_init,
4261 .sw_fini = gfx_v9_0_sw_fini,
4262 .hw_init = gfx_v9_0_hw_init,
4263 .hw_fini = gfx_v9_0_hw_fini,
4264 .suspend = gfx_v9_0_suspend,
4265 .resume = gfx_v9_0_resume,
4266 .is_idle = gfx_v9_0_is_idle,
4267 .wait_for_idle = gfx_v9_0_wait_for_idle,
4268 .soft_reset = gfx_v9_0_soft_reset,
4269 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4270 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 4271 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 4272};
4273
4274static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4275 .type = AMDGPU_RING_TYPE_GFX,
4276 .align_mask = 0xff,
4277 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4278 .support_64bit_ptrs = true,
0eeb68b3 4279 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4280 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4281 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4282 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 4283 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4284 5 + /* COND_EXEC */
4285 7 + /* PIPELINE_SYNC */
2e819849 4286 24 + /* VM_FLUSH */
e9d672b2
ML		 4287 8 + /* FENCE for VM_FLUSH */
4288 20 + /* GDS switch */
4289 4 + /* double SWITCH_BUFFER,
4290 the first COND_EXEC jump to the place just
4291 prior to this double SWITCH_BUFFER */
4292 5 + /* COND_EXEC */
4293 7 + /* HDP_flush */
4294 4 + /* VGT_flush */
4295 14 + /* CE_META */
4296 31 + /* DE_META */
4297 3 + /* CNTX_CTRL */
4298 5 + /* HDP_INVL */
4299 8 + 8 + /* FENCE x2 */
4300 2, /* SWITCH_BUFFER */
b1023571
KW		 4301 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4302 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4303 .emit_fence = gfx_v9_0_ring_emit_fence,
4304 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4305 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4306 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4307 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4308 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4309 .test_ring = gfx_v9_0_ring_test_ring,
4310 .test_ib = gfx_v9_0_ring_test_ib,
4311 .insert_nop = amdgpu_ring_insert_nop,
4312 .pad_ib = amdgpu_ring_generic_pad_ib,
4313 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4314 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 4315 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4316 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3b4d68e9 4317 .emit_tmz = gfx_v9_0_ring_emit_tmz,
b1023571
KW		 4318};
4319
4320static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4321 .type = AMDGPU_RING_TYPE_COMPUTE,
4322 .align_mask = 0xff,
4323 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4324 .support_64bit_ptrs = true,
0eeb68b3 4325 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4326 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4327 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4328 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4329 .emit_frame_size =
4330 20 + /* gfx_v9_0_ring_emit_gds_switch */
4331 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4332 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4333 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4334 24 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 4335 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4336 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4337 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4338 .emit_fence = gfx_v9_0_ring_emit_fence,
4339 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4340 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4341 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4342 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4343 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4344 .test_ring = gfx_v9_0_ring_test_ring,
4345 .test_ib = gfx_v9_0_ring_test_ib,
4346 .insert_nop = amdgpu_ring_insert_nop,
4347 .pad_ib = amdgpu_ring_generic_pad_ib,
4348};
4349
aa6faa44
XY		 4350static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4351 .type = AMDGPU_RING_TYPE_KIQ,
4352 .align_mask = 0xff,
4353 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4354 .support_64bit_ptrs = true,
0eeb68b3 4355 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 4356 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4357 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4358 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4359 .emit_frame_size =
4360 20 + /* gfx_v9_0_ring_emit_gds_switch */
4361 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4362 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4363 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4364 24 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 4365 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4366 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4367 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4368 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 4369 .test_ring = gfx_v9_0_ring_test_ring,
4370 .test_ib = gfx_v9_0_ring_test_ib,
4371 .insert_nop = amdgpu_ring_insert_nop,
4372 .pad_ib = amdgpu_ring_generic_pad_ib,
4373 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4374 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4375};
b1023571
KW		 4376
4377static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4378{
4379 int i;
4380
aa6faa44
XY		 4381 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4382
b1023571
KW		 4383 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4384 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4385
4386 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4387 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4388}
4389
97031e25
XY		 4390static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4391 .set = gfx_v9_0_kiq_set_interrupt_state,
4392 .process = gfx_v9_0_kiq_irq,
4393};
4394
b1023571
KW		 4395static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4396 .set = gfx_v9_0_set_eop_interrupt_state,
4397 .process = gfx_v9_0_eop_irq,
4398};
4399
4400static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4401 .set = gfx_v9_0_set_priv_reg_fault_state,
4402 .process = gfx_v9_0_priv_reg_irq,
4403};
4404
4405static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4406 .set = gfx_v9_0_set_priv_inst_fault_state,
4407 .process = gfx_v9_0_priv_inst_irq,
4408};
4409
4410static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4411{
4412 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4413 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4414
4415 adev->gfx.priv_reg_irq.num_types = 1;
4416 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4417
4418 adev->gfx.priv_inst_irq.num_types = 1;
4419 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 4420
4421 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4422 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 4423}
4424
4425static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4426{
4427 switch (adev->asic_type) {
4428 case CHIP_VEGA10:
a4dc61f5 4429 case CHIP_RAVEN:
b1023571
KW		 4430 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4431 break;
4432 default:
4433 break;
4434 }
4435}
4436
4437static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4438{
4439 /* init asci gds info */
5e78835a 4440 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 4441 adev->gds.gws.total_size = 64;
4442 adev->gds.oa.total_size = 16;
4443
4444 if (adev->gds.mem.total_size == 64 * 1024) {
4445 adev->gds.mem.gfx_partition_size = 4096;
4446 adev->gds.mem.cs_partition_size = 4096;
4447
4448 adev->gds.gws.gfx_partition_size = 4;
4449 adev->gds.gws.cs_partition_size = 4;
4450
4451 adev->gds.oa.gfx_partition_size = 4;
4452 adev->gds.oa.cs_partition_size = 1;
4453 } else {
4454 adev->gds.mem.gfx_partition_size = 1024;
4455 adev->gds.mem.cs_partition_size = 1024;
4456
4457 adev->gds.gws.gfx_partition_size = 16;
4458 adev->gds.gws.cs_partition_size = 16;
4459
4460 adev->gds.oa.gfx_partition_size = 4;
4461 adev->gds.oa.cs_partition_size = 4;
4462 }
4463}
4464
4465static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4466{
4467 u32 data, mask;
4468
5e78835a
TSD		 4469 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4470 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 4471
4472 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4473 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4474
378506a7 4475 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
b1023571
KW		 4476
4477 return (~data) & mask;
4478}
4479
4480static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4481 struct amdgpu_cu_info *cu_info)
4482{
4483 int i, j, k, counter, active_cu_number = 0;
4484 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4485
4486 if (!adev || !cu_info)
4487 return -EINVAL;
4488
4489 memset(cu_info, 0, sizeof(*cu_info));
4490
4491 mutex_lock(&adev->grbm_idx_mutex);
4492 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4493 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4494 mask = 1;
4495 ao_bitmap = 0;
4496 counter = 0;
4497 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4498 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4499 cu_info->bitmap[i][j] = bitmap;
4500
fe723cd3 4501 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
b1023571 4502 if (bitmap & mask) {
fe723cd3 4503 if (counter < adev->gfx.config.max_cu_per_sh)
b1023571
KW		 4504 ao_bitmap |= mask;
4505 counter ++;
4506 }
4507 mask <<= 1;
4508 }
4509 active_cu_number += counter;
4510 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4511 }
4512 }
4513 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4514 mutex_unlock(&adev->grbm_idx_mutex);
4515
4516 cu_info->number = active_cu_number;
4517 cu_info->ao_cu_mask = ao_cu_mask;
4518
4519 return 0;
4520}
4521
b1023571
KW		 4522const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4523{
4524 .type = AMD_IP_BLOCK_TYPE_GFX,
4525 .major = 9,
4526 .minor = 0,
4527 .rev = 0,
4528 .funcs = &gfx_v9_0_ip_funcs,
4529};
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