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drm/amd/amdgpu: Fix indentation in gfx_v9_0_mqd_init()
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
248a1d6f 24#include <drm/drmP.h>
b1023571
KW		 25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
268cb4c7 41#define GFX9_MEC_HPD_SIZE 2048
6bce4667
HZ		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
b1023571 45
91d3130a
HZ		 46#define mmPWR_MISC_CNTL_STATUS 0x0183
47#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
b1023571
KW		 52
53MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
060d124b
CZ		 60MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62MODULE_FIRMWARE("amdgpu/raven_me.bin");
63MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
b1023571
KW		 67static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
68{
35c32f20
TSD		 69 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
73 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
77 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
81 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
85 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
86 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
87 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
88 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
89 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
90 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
91 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
92 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
93 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
94 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
95 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
96 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
97 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
98 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
99 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
100 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
101 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
102 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
103 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
104 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
105 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
106 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
107 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
108 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
109 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
110 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
111 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
112 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
113 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
114 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
115 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
116 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
117 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
118 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
119 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
120 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
121 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
122 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
123 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
124 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
125 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
126 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
127 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
128 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
129 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
130 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
131 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
132 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
b1023571
KW		 133};
134
135static const u32 golden_settings_gc_9_0[] =
136{
f8af9332
KW		 137 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
138 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
139 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
140 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
141 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
142 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
b1023571
KW		 143 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
144 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
145 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
f8af9332
KW		 146 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
147 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
148 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
149 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
150 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
ba219b3c 151 SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
f8af9332 152 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
ba219b3c 153 SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
b1023571
KW		 154 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
155 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
156 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
f8af9332
KW		 157 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
158 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
159 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
b1023571
KW		 160};
161
162static const u32 golden_settings_gc_9_0_vg10[] =
163{
164 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
165 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
166 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
167 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
168 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
169 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
f8af9332 170 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
b1023571
KW		 171};
172
a5fdb336
CZ		 173static const u32 golden_settings_gc_9_1[] =
174{
175 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
01b5cc36
HZ		 176 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
177 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
178 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 179 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
180 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
01b5cc36 181 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 182 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
183 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
184 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
01b5cc36
HZ		 185 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
186 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
187 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
188 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
189 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
a5fdb336
CZ		 190 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
191 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
192 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
01b5cc36
HZ		 193 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
194 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
195 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
a5fdb336
CZ		 196};
197
198static const u32 golden_settings_gc_9_1_rv1[] =
199{
7b6ba9ea
HZ		 200 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
201 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
202 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
203 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
204 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
205 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
a5fdb336 206 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
b1023571
KW		 207};
208
209#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
7b6ba9ea 210#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
b1023571
KW		 211
212static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
213static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
214static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
215static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
216static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
217 struct amdgpu_cu_info *cu_info);
218static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
219static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
635e7132 220static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
b1023571
KW		 221
222static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
223{
224 switch (adev->asic_type) {
225 case CHIP_VEGA10:
226 amdgpu_program_register_sequence(adev,
227 golden_settings_gc_9_0,
228 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
229 amdgpu_program_register_sequence(adev,
230 golden_settings_gc_9_0_vg10,
231 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
232 break;
a5fdb336
CZ		 233 case CHIP_RAVEN:
234 amdgpu_program_register_sequence(adev,
235 golden_settings_gc_9_1,
236 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
237 amdgpu_program_register_sequence(adev,
238 golden_settings_gc_9_1_rv1,
239 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
240 break;
b1023571
KW		 241 default:
242 break;
243 }
244}
245
246static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
247{
6a05148f 248 adev->gfx.scratch.num_reg = 8;
b1023571
KW		 249 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
250 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
251}
252
253static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
254 bool wc, uint32_t reg, uint32_t val)
255{
256 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
257 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
258 WRITE_DATA_DST_SEL(0) |
259 (wc ? WR_CONFIRM : 0));
260 amdgpu_ring_write(ring, reg);
261 amdgpu_ring_write(ring, 0);
262 amdgpu_ring_write(ring, val);
263}
264
265static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
266 int mem_space, int opt, uint32_t addr0,
267 uint32_t addr1, uint32_t ref, uint32_t mask,
268 uint32_t inv)
269{
270 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
271 amdgpu_ring_write(ring,
272 /* memory (1) or register (0) */
273 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
274 WAIT_REG_MEM_OPERATION(opt) | /* wait */
275 WAIT_REG_MEM_FUNCTION(3) | /* equal */
276 WAIT_REG_MEM_ENGINE(eng_sel)));
277
278 if (mem_space)
279 BUG_ON(addr0 & 0x3); /* Dword align */
280 amdgpu_ring_write(ring, addr0);
281 amdgpu_ring_write(ring, addr1);
282 amdgpu_ring_write(ring, ref);
283 amdgpu_ring_write(ring, mask);
284 amdgpu_ring_write(ring, inv); /* poll interval */
285}
286
287static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
288{
289 struct amdgpu_device *adev = ring->adev;
290 uint32_t scratch;
291 uint32_t tmp = 0;
292 unsigned i;
293 int r;
294
295 r = amdgpu_gfx_scratch_get(adev, &scratch);
296 if (r) {
297 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
298 return r;
299 }
300 WREG32(scratch, 0xCAFEDEAD);
301 r = amdgpu_ring_alloc(ring, 3);
302 if (r) {
303 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
304 ring->idx, r);
305 amdgpu_gfx_scratch_free(adev, scratch);
306 return r;
307 }
308 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
309 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
310 amdgpu_ring_write(ring, 0xDEADBEEF);
311 amdgpu_ring_commit(ring);
312
313 for (i = 0; i < adev->usec_timeout; i++) {
314 tmp = RREG32(scratch);
315 if (tmp == 0xDEADBEEF)
316 break;
317 DRM_UDELAY(1);
318 }
319 if (i < adev->usec_timeout) {
320 DRM_INFO("ring test on %d succeeded in %d usecs\n",
321 ring->idx, i);
322 } else {
323 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
324 ring->idx, scratch, tmp);
325 r = -EINVAL;
326 }
327 amdgpu_gfx_scratch_free(adev, scratch);
328 return r;
329}
330
331static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
332{
333 struct amdgpu_device *adev = ring->adev;
334 struct amdgpu_ib ib;
335 struct dma_fence *f = NULL;
336 uint32_t scratch;
337 uint32_t tmp = 0;
338 long r;
339
340 r = amdgpu_gfx_scratch_get(adev, &scratch);
341 if (r) {
342 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
343 return r;
344 }
345 WREG32(scratch, 0xCAFEDEAD);
346 memset(&ib, 0, sizeof(ib));
347 r = amdgpu_ib_get(adev, NULL, 256, &ib);
348 if (r) {
349 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
350 goto err1;
351 }
352 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
353 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
354 ib.ptr[2] = 0xDEADBEEF;
355 ib.length_dw = 3;
356
357 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
358 if (r)
359 goto err2;
360
361 r = dma_fence_wait_timeout(f, false, timeout);
362 if (r == 0) {
363 DRM_ERROR("amdgpu: IB test timed out.\n");
364 r = -ETIMEDOUT;
365 goto err2;
366 } else if (r < 0) {
367 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
368 goto err2;
369 }
370 tmp = RREG32(scratch);
371 if (tmp == 0xDEADBEEF) {
372 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
373 r = 0;
374 } else {
375 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
376 scratch, tmp);
377 r = -EINVAL;
378 }
379err2:
380 amdgpu_ib_free(adev, &ib, NULL);
381 dma_fence_put(f);
382err1:
383 amdgpu_gfx_scratch_free(adev, scratch);
384 return r;
385}
386
387static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
388{
389 const char *chip_name;
390 char fw_name[30];
391 int err;
392 struct amdgpu_firmware_info *info = NULL;
393 const struct common_firmware_header *header = NULL;
394 const struct gfx_firmware_header_v1_0 *cp_hdr;
a4d41ad0
HZ		 395 const struct rlc_firmware_header_v2_0 *rlc_hdr;
396 unsigned int *tmp = NULL;
397 unsigned int i = 0;
b1023571
KW		 398
399 DRM_DEBUG("\n");
400
401 switch (adev->asic_type) {
402 case CHIP_VEGA10:
403 chip_name = "vega10";
404 break;
eaa85724
CZ		 405 case CHIP_RAVEN:
406 chip_name = "raven";
407 break;
b1023571
KW		 408 default:
409 BUG();
410 }
411
412 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
413 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
414 if (err)
415 goto out;
416 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
417 if (err)
418 goto out;
419 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
420 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
421 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
422
423 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
424 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
425 if (err)
426 goto out;
427 err = amdgpu_ucode_validate(adev->gfx.me_fw);
428 if (err)
429 goto out;
430 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
431 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
432 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
433
434 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
435 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
436 if (err)
437 goto out;
438 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
439 if (err)
440 goto out;
441 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
442 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
443 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
444
445 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
446 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
447 if (err)
448 goto out;
449 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
a4d41ad0
HZ		 450 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
451 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
452 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
453 adev->gfx.rlc.save_and_restore_offset =
454 le32_to_cpu(rlc_hdr->save_and_restore_offset);
455 adev->gfx.rlc.clear_state_descriptor_offset =
456 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
457 adev->gfx.rlc.avail_scratch_ram_locations =
458 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
459 adev->gfx.rlc.reg_restore_list_size =
460 le32_to_cpu(rlc_hdr->reg_restore_list_size);
461 adev->gfx.rlc.reg_list_format_start =
462 le32_to_cpu(rlc_hdr->reg_list_format_start);
463 adev->gfx.rlc.reg_list_format_separate_start =
464 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
465 adev->gfx.rlc.starting_offsets_start =
466 le32_to_cpu(rlc_hdr->starting_offsets_start);
467 adev->gfx.rlc.reg_list_format_size_bytes =
468 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
469 adev->gfx.rlc.reg_list_size_bytes =
470 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
471 adev->gfx.rlc.register_list_format =
472 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
473 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
474 if (!adev->gfx.rlc.register_list_format) {
475 err = -ENOMEM;
476 goto out;
477 }
478
479 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
480 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
481 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
482 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
483
484 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
485
486 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
487 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
488 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
489 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
b1023571
KW		 490
491 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
492 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
493 if (err)
494 goto out;
495 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
496 if (err)
497 goto out;
498 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
499 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
500 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
501
502
503 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
504 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
505 if (!err) {
506 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
507 if (err)
508 goto out;
509 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
510 adev->gfx.mec2_fw->data;
511 adev->gfx.mec2_fw_version =
512 le32_to_cpu(cp_hdr->header.ucode_version);
513 adev->gfx.mec2_feature_version =
514 le32_to_cpu(cp_hdr->ucode_feature_version);
515 } else {
516 err = 0;
517 adev->gfx.mec2_fw = NULL;
518 }
519
520 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
521 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
522 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
523 info->fw = adev->gfx.pfp_fw;
524 header = (const struct common_firmware_header *)info->fw->data;
525 adev->firmware.fw_size +=
526 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
527
528 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
529 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
530 info->fw = adev->gfx.me_fw;
531 header = (const struct common_firmware_header *)info->fw->data;
532 adev->firmware.fw_size +=
533 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
534
535 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
536 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
537 info->fw = adev->gfx.ce_fw;
538 header = (const struct common_firmware_header *)info->fw->data;
539 adev->firmware.fw_size +=
540 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
541
542 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
543 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
544 info->fw = adev->gfx.rlc_fw;
545 header = (const struct common_firmware_header *)info->fw->data;
546 adev->firmware.fw_size +=
547 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
548
549 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
550 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
551 info->fw = adev->gfx.mec_fw;
552 header = (const struct common_firmware_header *)info->fw->data;
553 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
554 adev->firmware.fw_size +=
555 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
556
557 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
558 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
559 info->fw = adev->gfx.mec_fw;
560 adev->firmware.fw_size +=
561 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
562
563 if (adev->gfx.mec2_fw) {
564 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
565 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
566 info->fw = adev->gfx.mec2_fw;
567 header = (const struct common_firmware_header *)info->fw->data;
568 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
569 adev->firmware.fw_size +=
570 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
571 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
572 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
573 info->fw = adev->gfx.mec2_fw;
574 adev->firmware.fw_size +=
575 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
576 }
577
578 }
579
580out:
581 if (err) {
582 dev_err(adev->dev,
583 "gfx9: Failed to load firmware \"%s\"\n",
584 fw_name);
585 release_firmware(adev->gfx.pfp_fw);
586 adev->gfx.pfp_fw = NULL;
587 release_firmware(adev->gfx.me_fw);
588 adev->gfx.me_fw = NULL;
589 release_firmware(adev->gfx.ce_fw);
590 adev->gfx.ce_fw = NULL;
591 release_firmware(adev->gfx.rlc_fw);
592 adev->gfx.rlc_fw = NULL;
593 release_firmware(adev->gfx.mec_fw);
594 adev->gfx.mec_fw = NULL;
595 release_firmware(adev->gfx.mec2_fw);
596 adev->gfx.mec2_fw = NULL;
597 }
598 return err;
599}
600
c9719c69
HZ		 601static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
602{
603 u32 count = 0;
604 const struct cs_section_def *sect = NULL;
605 const struct cs_extent_def *ext = NULL;
606
607 /* begin clear state */
608 count += 2;
609 /* context control state */
610 count += 3;
611
612 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
613 for (ext = sect->section; ext->extent != NULL; ++ext) {
614 if (sect->id == SECT_CONTEXT)
615 count += 2 + ext->reg_count;
616 else
617 return 0;
618 }
619 }
620
621 /* end clear state */
622 count += 2;
623 /* clear state */
624 count += 2;
625
626 return count;
627}
628
629static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
630 volatile u32 *buffer)
631{
632 u32 count = 0, i;
633 const struct cs_section_def *sect = NULL;
634 const struct cs_extent_def *ext = NULL;
635
636 if (adev->gfx.rlc.cs_data == NULL)
637 return;
638 if (buffer == NULL)
639 return;
640
641 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
642 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
643
644 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
645 buffer[count++] = cpu_to_le32(0x80000000);
646 buffer[count++] = cpu_to_le32(0x80000000);
647
648 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
649 for (ext = sect->section; ext->extent != NULL; ++ext) {
650 if (sect->id == SECT_CONTEXT) {
651 buffer[count++] =
652 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
653 buffer[count++] = cpu_to_le32(ext->reg_index -
654 PACKET3_SET_CONTEXT_REG_START);
655 for (i = 0; i < ext->reg_count; i++)
656 buffer[count++] = cpu_to_le32(ext->extent[i]);
657 } else {
658 return;
659 }
660 }
661 }
662
663 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
664 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
665
666 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
667 buffer[count++] = cpu_to_le32(0);
668}
669
ba7bb665
HZ		 670static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
671{
e5475e16 672 uint32_t data;
ba7bb665
HZ		 673
674 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
675 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
676 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
677 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
678 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
679
680 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
681 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
682
683 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
684 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
685
686 mutex_lock(&adev->grbm_idx_mutex);
687 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
688 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
689 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
690
691 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
e5475e16
TSD		 692 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
693 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
694 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
ba7bb665
HZ		 695 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
696
697 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
698 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
699 data &= 0x0000FFFF;
700 data |= 0x00C00000;
701 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
702
703 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
704 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
705
706 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
707 * but used for RLC_LB_CNTL configuration */
708 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
e5475e16
TSD		 709 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
710 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
ba7bb665
HZ		 711 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
712 mutex_unlock(&adev->grbm_idx_mutex);
713}
714
e8835e0e
HZ		 715static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
716{
e5475e16 717 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
e8835e0e
HZ		 718}
719
c9719c69
HZ		 720static void rv_init_cp_jump_table(struct amdgpu_device *adev)
721{
722 const __le32 *fw_data;
723 volatile u32 *dst_ptr;
724 int me, i, max_me = 5;
725 u32 bo_offset = 0;
726 u32 table_offset, table_size;
727
728 /* write the cp table buffer */
729 dst_ptr = adev->gfx.rlc.cp_table_ptr;
730 for (me = 0; me < max_me; me++) {
731 if (me == 0) {
732 const struct gfx_firmware_header_v1_0 *hdr =
733 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
734 fw_data = (const __le32 *)
735 (adev->gfx.ce_fw->data +
736 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
737 table_offset = le32_to_cpu(hdr->jt_offset);
738 table_size = le32_to_cpu(hdr->jt_size);
739 } else if (me == 1) {
740 const struct gfx_firmware_header_v1_0 *hdr =
741 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
742 fw_data = (const __le32 *)
743 (adev->gfx.pfp_fw->data +
744 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
745 table_offset = le32_to_cpu(hdr->jt_offset);
746 table_size = le32_to_cpu(hdr->jt_size);
747 } else if (me == 2) {
748 const struct gfx_firmware_header_v1_0 *hdr =
749 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
750 fw_data = (const __le32 *)
751 (adev->gfx.me_fw->data +
752 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
753 table_offset = le32_to_cpu(hdr->jt_offset);
754 table_size = le32_to_cpu(hdr->jt_size);
755 } else if (me == 3) {
756 const struct gfx_firmware_header_v1_0 *hdr =
757 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
758 fw_data = (const __le32 *)
759 (adev->gfx.mec_fw->data +
760 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
761 table_offset = le32_to_cpu(hdr->jt_offset);
762 table_size = le32_to_cpu(hdr->jt_size);
763 } else if (me == 4) {
764 const struct gfx_firmware_header_v1_0 *hdr =
765 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
766 fw_data = (const __le32 *)
767 (adev->gfx.mec2_fw->data +
768 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
769 table_offset = le32_to_cpu(hdr->jt_offset);
770 table_size = le32_to_cpu(hdr->jt_size);
771 }
772
773 for (i = 0; i < table_size; i ++) {
774 dst_ptr[bo_offset + i] =
775 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
776 }
777
778 bo_offset += table_size;
779 }
780}
781
782static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
783{
784 /* clear state block */
785 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
786 &adev->gfx.rlc.clear_state_gpu_addr,
787 (void **)&adev->gfx.rlc.cs_ptr);
788
789 /* jump table block */
790 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
791 &adev->gfx.rlc.cp_table_gpu_addr,
792 (void **)&adev->gfx.rlc.cp_table_ptr);
793}
794
795static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
796{
797 volatile u32 *dst_ptr;
798 u32 dws;
799 const struct cs_section_def *cs_data;
800 int r;
801
802 adev->gfx.rlc.cs_data = gfx9_cs_data;
803
804 cs_data = adev->gfx.rlc.cs_data;
805
806 if (cs_data) {
807 /* clear state block */
808 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
a4a02777
CK		 809 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
810 AMDGPU_GEM_DOMAIN_VRAM,
811 &adev->gfx.rlc.clear_state_obj,
812 &adev->gfx.rlc.clear_state_gpu_addr,
813 (void **)&adev->gfx.rlc.cs_ptr);
814 if (r) {
815 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
816 r);
817 gfx_v9_0_rlc_fini(adev);
818 return r;
c9719c69
HZ		 819 }
820 /* set up the cs buffer */
821 dst_ptr = adev->gfx.rlc.cs_ptr;
822 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
823 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
824 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
825 }
826
827 if (adev->asic_type == CHIP_RAVEN) {
828 /* TODO: double check the cp_table_size for RV */
829 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
a4a02777
CK		 830 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
831 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
832 &adev->gfx.rlc.cp_table_obj,
833 &adev->gfx.rlc.cp_table_gpu_addr,
834 (void **)&adev->gfx.rlc.cp_table_ptr);
835 if (r) {
836 dev_err(adev->dev,
837 "(%d) failed to create cp table bo\n", r);
838 gfx_v9_0_rlc_fini(adev);
839 return r;
c9719c69
HZ		 840 }
841
842 rv_init_cp_jump_table(adev);
843 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
844 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
ba7bb665
HZ		 845
846 gfx_v9_0_init_lbpw(adev);
c9719c69
HZ		 847 }
848
849 return 0;
850}
851
b1023571
KW		 852static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
853{
078af1a3
CK		 854 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
855 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
b1023571
KW		 856}
857
b1023571
KW		 858static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
859{
860 int r;
861 u32 *hpd;
862 const __le32 *fw_data;
863 unsigned fw_size;
864 u32 *fw;
42794b27 865 size_t mec_hpd_size;
b1023571
KW		 866
867 const struct gfx_firmware_header_v1_0 *mec_hdr;
868
78c16834
AR		 869 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
870
78c16834 871 /* take ownership of the relevant compute queues */
41f6a99a 872 amdgpu_gfx_compute_queue_acquire(adev);
78c16834 873 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
b1023571 874
a4a02777
CK		 875 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
876 AMDGPU_GEM_DOMAIN_GTT,
877 &adev->gfx.mec.hpd_eop_obj,
878 &adev->gfx.mec.hpd_eop_gpu_addr,
879 (void **)&hpd);
b1023571 880 if (r) {
a4a02777 881 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
b1023571
KW		 882 gfx_v9_0_mec_fini(adev);
883 return r;
884 }
885
886 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
887
888 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
889 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
890
891 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
892
893 fw_data = (const __le32 *)
894 (adev->gfx.mec_fw->data +
895 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
896 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
897
a4a02777
CK		 898 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
899 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
900 &adev->gfx.mec.mec_fw_obj,
901 &adev->gfx.mec.mec_fw_gpu_addr,
902 (void **)&fw);
b1023571 903 if (r) {
a4a02777 904 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
b1023571
KW		 905 gfx_v9_0_mec_fini(adev);
906 return r;
907 }
a4a02777 908
b1023571
KW		 909 memcpy(fw, fw_data, fw_size);
910
911 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
912 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
913
b1023571
KW		 914 return 0;
915}
916
917static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
918{
5e78835a 919 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 920 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
921 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
922 (address << SQ_IND_INDEX__INDEX__SHIFT) |
923 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 924 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 925}
926
927static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
928 uint32_t wave, uint32_t thread,
929 uint32_t regno, uint32_t num, uint32_t *out)
930{
5e78835a 931 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 932 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
933 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
934 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
935 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
936 (SQ_IND_INDEX__FORCE_READ_MASK) |
937 (SQ_IND_INDEX__AUTO_INCR_MASK));
938 while (num--)
5e78835a 939 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 940}
941
942static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
943{
944 /* type 1 wave data */
945 dst[(*no_fields)++] = 1;
946 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
947 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
948 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
949 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
950 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
951 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
952 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
953 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
954 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
955 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
956 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
957 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
958 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
959 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
960}
961
962static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
963 uint32_t wave, uint32_t start,
964 uint32_t size, uint32_t *dst)
965{
966 wave_read_regs(
967 adev, simd, wave, 0,
968 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
969}
970
971
972static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
973 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
974 .select_se_sh = &gfx_v9_0_select_se_sh,
975 .read_wave_data = &gfx_v9_0_read_wave_data,
976 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
977};
978
979static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
980{
981 u32 gb_addr_config;
982
983 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
984
985 switch (adev->asic_type) {
986 case CHIP_VEGA10:
b1023571 987 adev->gfx.config.max_hw_contexts = 8;
b1023571
KW		 988 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
989 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
990 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
991 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
992 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
993 break;
5cf7433d
CZ		 994 case CHIP_RAVEN:
995 adev->gfx.config.max_hw_contexts = 8;
996 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
997 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
998 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
999 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1000 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1001 break;
b1023571
KW		 1002 default:
1003 BUG();
1004 break;
1005 }
1006
1007 adev->gfx.config.gb_addr_config = gb_addr_config;
1008
1009 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1010 REG_GET_FIELD(
1011 adev->gfx.config.gb_addr_config,
1012 GB_ADDR_CONFIG,
1013 NUM_PIPES);
ad7d0ff3
AD		 1014
1015 adev->gfx.config.max_tile_pipes =
1016 adev->gfx.config.gb_addr_config_fields.num_pipes;
1017
b1023571
KW		 1018 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1019 REG_GET_FIELD(
1020 adev->gfx.config.gb_addr_config,
1021 GB_ADDR_CONFIG,
1022 NUM_BANKS);
1023 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1024 REG_GET_FIELD(
1025 adev->gfx.config.gb_addr_config,
1026 GB_ADDR_CONFIG,
1027 MAX_COMPRESSED_FRAGS);
1028 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1029 REG_GET_FIELD(
1030 adev->gfx.config.gb_addr_config,
1031 GB_ADDR_CONFIG,
1032 NUM_RB_PER_SE);
1033 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1034 REG_GET_FIELD(
1035 adev->gfx.config.gb_addr_config,
1036 GB_ADDR_CONFIG,
1037 NUM_SHADER_ENGINES);
1038 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1039 REG_GET_FIELD(
1040 adev->gfx.config.gb_addr_config,
1041 GB_ADDR_CONFIG,
1042 PIPE_INTERLEAVE_SIZE));
1043}
1044
1045static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1046 struct amdgpu_ngg_buf *ngg_buf,
1047 int size_se,
1048 int default_size_se)
1049{
1050 int r;
1051
1052 if (size_se < 0) {
1053 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1054 return -EINVAL;
1055 }
1056 size_se = size_se ? size_se : default_size_se;
1057
42ce2243 1058 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 1059 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1060 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1061 &ngg_buf->bo,
1062 &ngg_buf->gpu_addr,
1063 NULL);
1064 if (r) {
1065 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1066 return r;
1067 }
1068 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1069
1070 return r;
1071}
1072
1073static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1074{
1075 int i;
1076
1077 for (i = 0; i < NGG_BUF_MAX; i++)
1078 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1079 &adev->gfx.ngg.buf[i].gpu_addr,
1080 NULL);
1081
1082 memset(&adev->gfx.ngg.buf[0], 0,
1083 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1084
1085 adev->gfx.ngg.init = false;
1086
1087 return 0;
1088}
1089
1090static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1091{
1092 int r;
1093
1094 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1095 return 0;
1096
1097 /* GDS reserve memory: 64 bytes alignment */
1098 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1099 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1100 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1101 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1102 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1103
1104 /* Primitive Buffer */
af8baf15 1105 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
b1023571
KW		 1106 amdgpu_prim_buf_per_se,
1107 64 * 1024);
1108 if (r) {
1109 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1110 goto err;
1111 }
1112
1113 /* Position Buffer */
af8baf15 1114 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
b1023571
KW		 1115 amdgpu_pos_buf_per_se,
1116 256 * 1024);
1117 if (r) {
1118 dev_err(adev->dev, "Failed to create Position Buffer\n");
1119 goto err;
1120 }
1121
1122 /* Control Sideband */
af8baf15 1123 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
b1023571
KW		 1124 amdgpu_cntl_sb_buf_per_se,
1125 256);
1126 if (r) {
1127 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1128 goto err;
1129 }
1130
1131 /* Parameter Cache, not created by default */
1132 if (amdgpu_param_buf_per_se <= 0)
1133 goto out;
1134
af8baf15 1135 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
b1023571
KW		 1136 amdgpu_param_buf_per_se,
1137 512 * 1024);
1138 if (r) {
1139 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1140 goto err;
1141 }
1142
1143out:
1144 adev->gfx.ngg.init = true;
1145 return 0;
1146err:
1147 gfx_v9_0_ngg_fini(adev);
1148 return r;
1149}
1150
1151static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1152{
1153 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1154 int r;
91629eff 1155 u32 data, base;
b1023571
KW		 1156
1157 if (!amdgpu_ngg)
1158 return 0;
1159
1160 /* Program buffer size */
91629eff
TSD		 1161 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1162 adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1163 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1164 adev->gfx.ngg.buf[NGG_POS].size >> 8);
5e78835a 1165 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571 1166
91629eff
TSD		 1167 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1168 adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1169 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1170 adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
5e78835a 1171 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 1172
1173 /* Program buffer base address */
af8baf15 1174 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1175 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 1176 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571 1177
af8baf15 1178 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1179 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 1180 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571 1181
af8baf15 1182 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1183 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 1184 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571 1185
af8baf15 1186 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1187 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 1188 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571 1189
af8baf15 1190 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1191 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 1192 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571 1193
af8baf15 1194 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1195 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 1196 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 1197
1198 /* Clear GDS reserved memory */
1199 r = amdgpu_ring_alloc(ring, 17);
1200 if (r) {
1201 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1202 ring->idx, r);
1203 return r;
1204 }
1205
1206 gfx_v9_0_write_data_to_reg(ring, 0, false,
1207 amdgpu_gds_reg_offset[0].mem_size,
1208 (adev->gds.mem.total_size +
1209 adev->gfx.ngg.gds_reserve_size) >>
1210 AMDGPU_GDS_SHIFT);
1211
1212 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1213 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1214 PACKET3_DMA_DATA_SRC_SEL(2)));
1215 amdgpu_ring_write(ring, 0);
1216 amdgpu_ring_write(ring, 0);
1217 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1218 amdgpu_ring_write(ring, 0);
1219 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1220
1221
1222 gfx_v9_0_write_data_to_reg(ring, 0, false,
1223 amdgpu_gds_reg_offset[0].mem_size, 0);
1224
1225 amdgpu_ring_commit(ring);
1226
1227 return 0;
1228}
1229
1361f455
AD		 1230static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1231 int mec, int pipe, int queue)
1232{
1233 int r;
1234 unsigned irq_type;
1235 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1236
1237 ring = &adev->gfx.compute_ring[ring_id];
1238
1239 /* mec0 is me1 */
1240 ring->me = mec + 1;
1241 ring->pipe = pipe;
1242 ring->queue = queue;
1243
1244 ring->ring_obj = NULL;
1245 ring->use_doorbell = true;
7366af81 1246 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1361f455
AD		 1247 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1248 + (ring_id * GFX9_MEC_HPD_SIZE);
1249 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1250
1251 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1252 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1253 + ring->pipe;
1254
1255 /* type-2 packets are deprecated on MEC, use type-3 instead */
1256 r = amdgpu_ring_init(adev, ring, 1024,
1257 &adev->gfx.eop_irq, irq_type);
1258 if (r)
1259 return r;
1260
1261
1262 return 0;
1263}
1264
b1023571
KW		 1265static int gfx_v9_0_sw_init(void *handle)
1266{
1361f455 1267 int i, j, k, r, ring_id;
b1023571 1268 struct amdgpu_ring *ring;
ac104e99 1269 struct amdgpu_kiq *kiq;
b1023571
KW		 1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1271
4853bbb6
AD		 1272 switch (adev->asic_type) {
1273 case CHIP_VEGA10:
1274 case CHIP_RAVEN:
1275 adev->gfx.mec.num_mec = 2;
1276 break;
1277 default:
1278 adev->gfx.mec.num_mec = 1;
1279 break;
1280 }
1281
1282 adev->gfx.mec.num_pipe_per_mec = 4;
1283 adev->gfx.mec.num_queue_per_pipe = 8;
1284
97031e25
XY		 1285 /* KIQ event */
1286 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1287 if (r)
1288 return r;
1289
b1023571
KW		 1290 /* EOP Event */
1291 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1292 if (r)
1293 return r;
1294
1295 /* Privileged reg */
1296 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1297 &adev->gfx.priv_reg_irq);
1298 if (r)
1299 return r;
1300
1301 /* Privileged inst */
1302 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1303 &adev->gfx.priv_inst_irq);
1304 if (r)
1305 return r;
1306
1307 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1308
1309 gfx_v9_0_scratch_init(adev);
1310
1311 r = gfx_v9_0_init_microcode(adev);
1312 if (r) {
1313 DRM_ERROR("Failed to load gfx firmware!\n");
1314 return r;
1315 }
1316
c9719c69
HZ		 1317 r = gfx_v9_0_rlc_init(adev);
1318 if (r) {
1319 DRM_ERROR("Failed to init rlc BOs!\n");
1320 return r;
1321 }
1322
b1023571
KW		 1323 r = gfx_v9_0_mec_init(adev);
1324 if (r) {
1325 DRM_ERROR("Failed to init MEC BOs!\n");
1326 return r;
1327 }
1328
1329 /* set up the gfx ring */
1330 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1331 ring = &adev->gfx.gfx_ring[i];
1332 ring->ring_obj = NULL;
1333 sprintf(ring->name, "gfx");
1334 ring->use_doorbell = true;
1335 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1336 r = amdgpu_ring_init(adev, ring, 1024,
1337 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1338 if (r)
1339 return r;
1340 }
1341
1361f455
AD		 1342 /* set up the compute queues - allocate horizontally across pipes */
1343 ring_id = 0;
1344 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1345 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1346 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2db0cdbe 1347 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1361f455
AD		 1348 continue;
1349
1350 r = gfx_v9_0_compute_ring_init(adev,
1351 ring_id,
1352 i, k, j);
1353 if (r)
1354 return r;
1355
1356 ring_id++;
1357 }
b1023571 1358 }
b1023571
KW		 1359 }
1360
71c37505 1361 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
e30a5223
AD		 1362 if (r) {
1363 DRM_ERROR("Failed to init KIQ BOs!\n");
1364 return r;
1365 }
ac104e99 1366
e30a5223 1367 kiq = &adev->gfx.kiq;
71c37505 1368 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
e30a5223
AD		 1369 if (r)
1370 return r;
464826d6 1371
e30a5223 1372 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
ffe6d881 1373 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
e30a5223
AD		 1374 if (r)
1375 return r;
ac104e99 1376
b1023571
KW		 1377 /* reserve GDS, GWS and OA resource for gfx */
1378 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1379 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1380 &adev->gds.gds_gfx_bo, NULL, NULL);
1381 if (r)
1382 return r;
1383
1384 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1385 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1386 &adev->gds.gws_gfx_bo, NULL, NULL);
1387 if (r)
1388 return r;
1389
1390 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1391 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1392 &adev->gds.oa_gfx_bo, NULL, NULL);
1393 if (r)
1394 return r;
1395
1396 adev->gfx.ce_ram_size = 0x8000;
1397
1398 gfx_v9_0_gpu_early_init(adev);
1399
1400 r = gfx_v9_0_ngg_init(adev);
1401 if (r)
1402 return r;
1403
1404 return 0;
1405}
1406
1407
1408static int gfx_v9_0_sw_fini(void *handle)
1409{
1410 int i;
1411 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1412
1413 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1414 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1415 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1416
1417 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1418 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1419 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1420 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1421
b9683c21 1422 amdgpu_gfx_compute_mqd_sw_fini(adev);
71c37505
AD		 1423 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1424 amdgpu_gfx_kiq_fini(adev);
ac104e99 1425
b1023571
KW		 1426 gfx_v9_0_mec_fini(adev);
1427 gfx_v9_0_ngg_fini(adev);
1428
1429 return 0;
1430}
1431
1432
1433static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1434{
1435 /* TODO */
1436}
1437
1438static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1439{
be448a4d 1440 u32 data;
b1023571 1441
be448a4d
NH		 1442 if (instance == 0xffffffff)
1443 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1444 else
1445 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1446
1447 if (se_num == 0xffffffff)
b1023571 1448 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
be448a4d 1449 else
b1023571 1450 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
be448a4d
NH		 1451
1452 if (sh_num == 0xffffffff)
1453 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1454 else
b1023571 1455 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
be448a4d 1456
5e78835a 1457 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1458}
1459
b1023571
KW		 1460static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1461{
1462 u32 data, mask;
1463
5e78835a
TSD		 1464 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1465 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1466
1467 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1468 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1469
378506a7
AD		 1470 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1471 adev->gfx.config.max_sh_per_se);
b1023571
KW		 1472
1473 return (~data) & mask;
1474}
1475
1476static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1477{
1478 int i, j;
2572c24c 1479 u32 data;
b1023571
KW		 1480 u32 active_rbs = 0;
1481 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1482 adev->gfx.config.max_sh_per_se;
1483
1484 mutex_lock(&adev->grbm_idx_mutex);
1485 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1486 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1487 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1488 data = gfx_v9_0_get_rb_active_bitmap(adev);
1489 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1490 rb_bitmap_width_per_sh);
1491 }
1492 }
1493 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1494 mutex_unlock(&adev->grbm_idx_mutex);
1495
1496 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1497 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1498}
1499
1500#define DEFAULT_SH_MEM_BASES (0x6000)
1501#define FIRST_COMPUTE_VMID (8)
1502#define LAST_COMPUTE_VMID (16)
1503static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1504{
1505 int i;
1506 uint32_t sh_mem_config;
1507 uint32_t sh_mem_bases;
1508
1509 /*
1510 * Configure apertures:
1511 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1512 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1513 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1514 */
1515 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1516
1517 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1518 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
eaa05d52 1519 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
b1023571
KW		 1520
1521 mutex_lock(&adev->srbm_mutex);
1522 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1523 soc15_grbm_select(adev, 0, 0, 0, i);
1524 /* CP and shaders */
5e78835a
TSD		 1525 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1526 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1527 }
1528 soc15_grbm_select(adev, 0, 0, 0, 0);
1529 mutex_unlock(&adev->srbm_mutex);
1530}
1531
1532static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1533{
1534 u32 tmp;
1535 int i;
1536
40f06773 1537 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1538
1539 gfx_v9_0_tiling_mode_table_init(adev);
1540
1541 gfx_v9_0_setup_rb(adev);
1542 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1543
1544 /* XXX SH_MEM regs */
1545 /* where to put LDS, scratch, GPUVM in FSA64 space */
1546 mutex_lock(&adev->srbm_mutex);
1547 for (i = 0; i < 16; i++) {
1548 soc15_grbm_select(adev, 0, 0, 0, i);
1549 /* CP and shaders */
1550 tmp = 0;
1551 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1552 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5e78835a
TSD		 1553 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1554 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
b1023571
KW		 1555 }
1556 soc15_grbm_select(adev, 0, 0, 0, 0);
1557
1558 mutex_unlock(&adev->srbm_mutex);
1559
1560 gfx_v9_0_init_compute_vmid(adev);
1561
1562 mutex_lock(&adev->grbm_idx_mutex);
1563 /*
1564 * making sure that the following register writes will be broadcasted
1565 * to all the shaders
1566 */
1567 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1568
5e78835a 1569 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1570 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1571 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1572 (adev->gfx.config.sc_prim_fifo_size_backend <<
1573 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1574 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1575 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1576 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1577 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1578 mutex_unlock(&adev->grbm_idx_mutex);
1579
1580}
1581
1582static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1583{
1584 u32 i, j, k;
1585 u32 mask;
1586
1587 mutex_lock(&adev->grbm_idx_mutex);
1588 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1589 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1590 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1591 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1592 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1593 break;
1594 udelay(1);
1595 }
1596 }
1597 }
1598 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1599 mutex_unlock(&adev->grbm_idx_mutex);
1600
1601 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1602 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1603 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1604 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1605 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1606 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1607 break;
1608 udelay(1);
1609 }
1610}
1611
1612static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1613 bool enable)
1614{
5e78835a 1615 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571 1616
b1023571
KW		 1617 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1618 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1619 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1620 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1621
5e78835a 1622 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1623}
1624
6bce4667
HZ		 1625static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1626{
1627 /* csib */
1628 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1629 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1630 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1631 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1632 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1633 adev->gfx.rlc.clear_state_size);
1634}
1635
1636static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1637 int indirect_offset,
1638 int list_size,
1639 int *unique_indirect_regs,
1640 int *unique_indirect_reg_count,
1641 int max_indirect_reg_count,
1642 int *indirect_start_offsets,
1643 int *indirect_start_offsets_count,
1644 int max_indirect_start_offsets_count)
1645{
1646 int idx;
1647 bool new_entry = true;
1648
1649 for (; indirect_offset < list_size; indirect_offset++) {
1650
1651 if (new_entry) {
1652 new_entry = false;
1653 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1654 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1655 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1656 }
1657
1658 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1659 new_entry = true;
1660 continue;
1661 }
1662
1663 indirect_offset += 2;
1664
1665 /* look for the matching indice */
1666 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1667 if (unique_indirect_regs[idx] ==
1668 register_list_format[indirect_offset])
1669 break;
1670 }
1671
1672 if (idx >= *unique_indirect_reg_count) {
1673 unique_indirect_regs[*unique_indirect_reg_count] =
1674 register_list_format[indirect_offset];
1675 idx = *unique_indirect_reg_count;
1676 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1677 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1678 }
1679
1680 register_list_format[indirect_offset] = idx;
1681 }
1682}
1683
1684static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1685{
1686 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1687 int unique_indirect_reg_count = 0;
1688
1689 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1690 int indirect_start_offsets_count = 0;
1691
1692 int list_size = 0;
1693 int i = 0;
1694 u32 tmp = 0;
1695
1696 u32 *register_list_format =
1697 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1698 if (!register_list_format)
1699 return -ENOMEM;
1700 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1701 adev->gfx.rlc.reg_list_format_size_bytes);
1702
1703 /* setup unique_indirect_regs array and indirect_start_offsets array */
1704 gfx_v9_0_parse_ind_reg_list(register_list_format,
1705 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1706 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1707 unique_indirect_regs,
1708 &unique_indirect_reg_count,
1709 sizeof(unique_indirect_regs)/sizeof(int),
1710 indirect_start_offsets,
1711 &indirect_start_offsets_count,
1712 sizeof(indirect_start_offsets)/sizeof(int));
1713
1714 /* enable auto inc in case it is disabled */
1715 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1716 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1717 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1718
1719 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1720 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1721 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1722 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1723 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1724 adev->gfx.rlc.register_restore[i]);
1725
1726 /* load direct register */
1727 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1728 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1729 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1730 adev->gfx.rlc.register_restore[i]);
1731
1732 /* load indirect register */
1733 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1734 adev->gfx.rlc.reg_list_format_start);
1735 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1736 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1737 register_list_format[i]);
1738
1739 /* set save/restore list size */
1740 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1741 list_size = list_size >> 1;
1742 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1743 adev->gfx.rlc.reg_restore_list_size);
1744 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1745
1746 /* write the starting offsets to RLC scratch ram */
1747 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1748 adev->gfx.rlc.starting_offsets_start);
1749 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1750 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1751 indirect_start_offsets[i]);
1752
1753 /* load unique indirect regs*/
1754 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1755 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1756 unique_indirect_regs[i] & 0x3FFFF);
1757 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1758 unique_indirect_regs[i] >> 20);
1759 }
1760
1761 kfree(register_list_format);
1762 return 0;
1763}
1764
1765static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1766{
0e5293d0 1767 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
6bce4667
HZ		 1768}
1769
91d3130a
HZ		 1770static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1771 bool enable)
1772{
1773 uint32_t data = 0;
1774 uint32_t default_data = 0;
1775
1776 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1777 if (enable == true) {
1778 /* enable GFXIP control over CGPG */
1779 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1780 if(default_data != data)
1781 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1782
1783 /* update status */
1784 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1785 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1786 if(default_data != data)
1787 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1788 } else {
1789 /* restore GFXIP control over GCPG */
1790 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1791 if(default_data != data)
1792 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1793 }
1794}
1795
1796static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1797{
1798 uint32_t data = 0;
1799
1800 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1801 AMD_PG_SUPPORT_GFX_SMG |
1802 AMD_PG_SUPPORT_GFX_DMG)) {
1803 /* init IDLE_POLL_COUNT = 60 */
1804 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1805 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1806 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1807 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1808
1809 /* init RLC PG Delay */
1810 data = 0;
1811 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1812 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1813 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1814 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1815 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1816
1817 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1818 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1819 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1820 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1821
1822 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1823 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1824 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1825 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1826
1827 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1828 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1829
1830 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1831 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1832 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1833
1834 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1835 }
1836}
1837
ed5ad1e4
HZ		 1838static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1839 bool enable)
1840{
1841 uint32_t data = 0;
1842 uint32_t default_data = 0;
1843
1844 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
e24c7f06
TSD		 1845 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1846 SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
1847 enable ? 1 : 0);
1848 if (default_data != data)
1849 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
ed5ad1e4
HZ		 1850}
1851
1852static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1853 bool enable)
1854{
1855 uint32_t data = 0;
1856 uint32_t default_data = 0;
1857
1858 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
b926fe8e
TSD		 1859 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1860 SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
1861 enable ? 1 : 0);
1862 if(default_data != data)
1863 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
ed5ad1e4
HZ		 1864}
1865
3a6cc477
HZ		 1866static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1867 bool enable)
1868{
1869 uint32_t data = 0;
1870 uint32_t default_data = 0;
1871
1872 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
54cfe0fc
TSD		 1873 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1874 CP_PG_DISABLE,
1875 enable ? 0 : 1);
1876 if(default_data != data)
1877 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
3a6cc477
HZ		 1878}
1879
197f95c8
HZ		 1880static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
1881 bool enable)
1882{
1883 uint32_t data, default_data;
1884
1885 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
f55ee212
TSD		 1886 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1887 GFX_POWER_GATING_ENABLE,
1888 enable ? 1 : 0);
197f95c8
HZ		 1889 if(default_data != data)
1890 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1891}
1892
1893static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
1894 bool enable)
1895{
1896 uint32_t data, default_data;
1897
1898 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
513f8133
TSD		 1899 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1900 GFX_PIPELINE_PG_ENABLE,
1901 enable ? 1 : 0);
197f95c8
HZ		 1902 if(default_data != data)
1903 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1904
1905 if (!enable)
1906 /* read any GFX register to wake up GFX */
1907 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
1908}
1909
552c8f76 1910static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
1911 bool enable)
18924c71
HZ		 1912{
1913 uint32_t data, default_data;
1914
1915 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
7915c8fd
TSD		 1916 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1917 STATIC_PER_CU_PG_ENABLE,
1918 enable ? 1 : 0);
18924c71
HZ		 1919 if(default_data != data)
1920 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1921}
1922
552c8f76 1923static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
18924c71
HZ		 1924 bool enable)
1925{
1926 uint32_t data, default_data;
1927
1928 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
e567fa69
TSD		 1929 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1930 DYN_PER_CU_PG_ENABLE,
1931 enable ? 1 : 0);
18924c71
HZ		 1932 if(default_data != data)
1933 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1934}
1935
6bce4667
HZ		 1936static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
1937{
1938 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1939 AMD_PG_SUPPORT_GFX_SMG |
1940 AMD_PG_SUPPORT_GFX_DMG |
1941 AMD_PG_SUPPORT_CP |
1942 AMD_PG_SUPPORT_GDS |
1943 AMD_PG_SUPPORT_RLC_SMU_HS)) {
1944 gfx_v9_0_init_csb(adev);
1945 gfx_v9_0_init_rlc_save_restore_list(adev);
1946 gfx_v9_0_enable_save_restore_machine(adev);
91d3130a
HZ		 1947
1948 if (adev->asic_type == CHIP_RAVEN) {
1949 WREG32(mmRLC_JUMP_TABLE_RESTORE,
1950 adev->gfx.rlc.cp_table_gpu_addr >> 8);
1951 gfx_v9_0_init_gfx_power_gating(adev);
3a6cc477 1952
ed5ad1e4
HZ		 1953 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
1954 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
1955 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
1956 } else {
1957 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
1958 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
1959 }
3a6cc477
HZ		 1960
1961 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
1962 gfx_v9_0_enable_cp_power_gating(adev, true);
1963 else
1964 gfx_v9_0_enable_cp_power_gating(adev, false);
91d3130a 1965 }
6bce4667
HZ		 1966 }
1967}
1968
b1023571
KW		 1969void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1970{
b08796ce 1971 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
b1023571 1972 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
b1023571
KW		 1973 gfx_v9_0_wait_for_rlc_serdes(adev);
1974}
1975
1976static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1977{
596c8e8b 1978 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 1979 udelay(50);
596c8e8b 1980 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 1981 udelay(50);
1982}
1983
1984static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1985{
1986#ifdef AMDGPU_RLC_DEBUG_RETRY
1987 u32 rlc_ucode_ver;
1988#endif
b1023571 1989
342cda25 1990 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 1991
1992 /* carrizo do enable cp interrupt after cp inited */
1993 if (!(adev->flags & AMD_IS_APU))
1994 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1995
1996 udelay(50);
1997
1998#ifdef AMDGPU_RLC_DEBUG_RETRY
1999 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 2000 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 2001 if(rlc_ucode_ver == 0x108) {
2002 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2003 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2004 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2005 * default is 0x9C4 to create a 100us interval */
5e78835a 2006 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571 2007 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
eaa05d52 2008 * to disable the page fault retry interrupts, default is
b1023571 2009 * 0x100 (256) */
5e78835a 2010 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 2011 }
2012#endif
2013}
2014
2015static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2016{
2017 const struct rlc_firmware_header_v2_0 *hdr;
2018 const __le32 *fw_data;
2019 unsigned i, fw_size;
2020
2021 if (!adev->gfx.rlc_fw)
2022 return -EINVAL;
2023
2024 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2025 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2026
2027 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2028 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2029 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2030
5e78835a 2031 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 2032 RLCG_UCODE_LOADING_START_ADDRESS);
2033 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2034 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2035 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 2036
2037 return 0;
2038}
2039
2040static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2041{
2042 int r;
2043
cfee05bc
ML		 2044 if (amdgpu_sriov_vf(adev))
2045 return 0;
2046
b1023571
KW		 2047 gfx_v9_0_rlc_stop(adev);
2048
2049 /* disable CG */
5e78835a 2050 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 2051
2052 /* disable PG */
5e78835a 2053 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 2054
2055 gfx_v9_0_rlc_reset(adev);
2056
6bce4667
HZ		 2057 gfx_v9_0_init_pg(adev);
2058
b1023571
KW		 2059 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2060 /* legacy rlc firmware loading */
2061 r = gfx_v9_0_rlc_load_microcode(adev);
2062 if (r)
2063 return r;
2064 }
2065
e8835e0e
HZ		 2066 if (adev->asic_type == CHIP_RAVEN) {
2067 if (amdgpu_lbpw != 0)
2068 gfx_v9_0_enable_lbpw(adev, true);
2069 else
2070 gfx_v9_0_enable_lbpw(adev, false);
2071 }
2072
b1023571
KW		 2073 gfx_v9_0_rlc_start(adev);
2074
2075 return 0;
2076}
2077
2078static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2079{
2080 int i;
5e78835a 2081 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 2082
ea64468e
TSD		 2083 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2084 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2085 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2086 if (!enable) {
b1023571
KW		 2087 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2088 adev->gfx.gfx_ring[i].ready = false;
2089 }
5e78835a 2090 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 2091 udelay(50);
2092}
2093
2094static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2095{
2096 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2097 const struct gfx_firmware_header_v1_0 *ce_hdr;
2098 const struct gfx_firmware_header_v1_0 *me_hdr;
2099 const __le32 *fw_data;
2100 unsigned i, fw_size;
2101
2102 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2103 return -EINVAL;
2104
2105 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2106 adev->gfx.pfp_fw->data;
2107 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2108 adev->gfx.ce_fw->data;
2109 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2110 adev->gfx.me_fw->data;
2111
2112 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2113 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2114 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2115
2116 gfx_v9_0_cp_gfx_enable(adev, false);
2117
2118 /* PFP */
2119 fw_data = (const __le32 *)
2120 (adev->gfx.pfp_fw->data +
2121 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2122 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 2123 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 2124 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2125 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2126 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 2127
2128 /* CE */
2129 fw_data = (const __le32 *)
2130 (adev->gfx.ce_fw->data +
2131 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2132 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 2133 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 2134 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2135 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2136 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 2137
2138 /* ME */
2139 fw_data = (const __le32 *)
2140 (adev->gfx.me_fw->data +
2141 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2142 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 2143 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 2144 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2145 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2146 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 2147
2148 return 0;
2149}
2150
b1023571
KW		 2151static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2152{
2153 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2154 const struct cs_section_def *sect = NULL;
2155 const struct cs_extent_def *ext = NULL;
d5de797f 2156 int r, i, tmp;
b1023571
KW		 2157
2158 /* init the CP */
5e78835a
TSD		 2159 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2160 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 2161
2162 gfx_v9_0_cp_gfx_enable(adev, true);
2163
d5de797f 2164 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
b1023571
KW		 2165 if (r) {
2166 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2167 return r;
2168 }
2169
2170 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2171 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2172
2173 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2174 amdgpu_ring_write(ring, 0x80000000);
2175 amdgpu_ring_write(ring, 0x80000000);
2176
2177 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2178 for (ext = sect->section; ext->extent != NULL; ++ext) {
2179 if (sect->id == SECT_CONTEXT) {
2180 amdgpu_ring_write(ring,
2181 PACKET3(PACKET3_SET_CONTEXT_REG,
2182 ext->reg_count));
2183 amdgpu_ring_write(ring,
2184 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2185 for (i = 0; i < ext->reg_count; i++)
2186 amdgpu_ring_write(ring, ext->extent[i]);
2187 }
2188 }
2189 }
2190
2191 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2192 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2193
2194 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2195 amdgpu_ring_write(ring, 0);
2196
2197 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2198 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2199 amdgpu_ring_write(ring, 0x8000);
2200 amdgpu_ring_write(ring, 0x8000);
2201
d5de797f
KW		 2202 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2203 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2204 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2205 amdgpu_ring_write(ring, tmp);
2206 amdgpu_ring_write(ring, 0);
2207
b1023571
KW		 2208 amdgpu_ring_commit(ring);
2209
2210 return 0;
2211}
2212
2213static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2214{
2215 struct amdgpu_ring *ring;
2216 u32 tmp;
2217 u32 rb_bufsz;
3fc08b61 2218 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 2219
2220 /* Set the write pointer delay */
5e78835a 2221 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 2222
2223 /* set the RB to use vmid 0 */
5e78835a 2224 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 2225
2226 /* Set ring buffer size */
2227 ring = &adev->gfx.gfx_ring[0];
2228 rb_bufsz = order_base_2(ring->ring_size / 8);
2229 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2230 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2231#ifdef __BIG_ENDIAN
2232 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2233#endif
5e78835a 2234 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2235
2236 /* Initialize the ring buffer's write pointers */
2237 ring->wptr = 0;
5e78835a
TSD		 2238 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2239 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2240
2241 /* set the wb address wether it's enabled or not */
2242 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 2243 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2244 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 2245
3fc08b61 2246 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 2247 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2248 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 2249
b1023571 2250 mdelay(1);
5e78835a 2251 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2252
2253 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 2254 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2255 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 2256
5e78835a 2257 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 2258 if (ring->use_doorbell) {
2259 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2260 DOORBELL_OFFSET, ring->doorbell_index);
2261 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2262 DOORBELL_EN, 1);
2263 } else {
2264 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2265 }
5e78835a 2266 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 2267
2268 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2269 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 2270 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 2271
5e78835a 2272 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 2273 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2274
2275
2276 /* start the ring */
2277 gfx_v9_0_cp_gfx_start(adev);
2278 ring->ready = true;
2279
2280 return 0;
2281}
2282
2283static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2284{
2285 int i;
2286
2287 if (enable) {
5e78835a 2288 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 2289 } else {
5e78835a 2290 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 2291 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2292 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2293 adev->gfx.compute_ring[i].ready = false;
ac104e99 2294 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 2295 }
2296 udelay(50);
2297}
2298
b1023571
KW		 2299static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2300{
2301 const struct gfx_firmware_header_v1_0 *mec_hdr;
2302 const __le32 *fw_data;
2303 unsigned i;
2304 u32 tmp;
2305
2306 if (!adev->gfx.mec_fw)
2307 return -EINVAL;
2308
2309 gfx_v9_0_cp_compute_enable(adev, false);
2310
2311 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2312 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2313
2314 fw_data = (const __le32 *)
2315 (adev->gfx.mec_fw->data +
2316 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2317 tmp = 0;
2318 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2319 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 2320 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 2321
5e78835a 2322 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 2323 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 2324 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571 2325 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
eaa05d52 2326
b1023571 2327 /* MEC1 */
5e78835a 2328 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2329 mec_hdr->jt_offset);
2330 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 2331 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 2332 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2333
5e78835a 2334 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2335 adev->gfx.mec_fw_version);
2336 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2337
2338 return 0;
2339}
2340
464826d6
XY		 2341/* KIQ functions */
2342static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
b1023571 2343{
464826d6
XY		 2344 uint32_t tmp;
2345 struct amdgpu_device *adev = ring->adev;
b1023571 2346
464826d6 2347 /* tell RLC which is KIQ queue */
5e78835a 2348 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 2349 tmp &= 0xffffff00;
2350 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 2351 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2352 tmp |= 0x80;
5e78835a 2353 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2354}
b1023571 2355
0f1dfd52 2356static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
464826d6 2357{
bd3402ea 2358 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2fdde9fa 2359 uint32_t scratch, tmp = 0;
de65513a 2360 uint64_t queue_mask = 0;
2fdde9fa 2361 int r, i;
b1023571 2362
de65513a
AR		 2363 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2364 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2365 continue;
b1023571 2366
de65513a
AR		 2367 /* This situation may be hit in the future if a new HW
2368 * generation exposes more than 64 queues. If so, the
2369 * definition of queue_mask needs updating */
1d11ee89 2370 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
de65513a
AR		 2371 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2372 break;
b1023571 2373 }
b1023571 2374
de65513a
AR		 2375 queue_mask |= (1ull << i);
2376 }
b1023571 2377
2fdde9fa
AD		 2378 r = amdgpu_gfx_scratch_get(adev, &scratch);
2379 if (r) {
2380 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2381 return r;
b1023571 2382 }
2fdde9fa 2383 WREG32(scratch, 0xCAFEDEAD);
b1023571 2384
0f1dfd52 2385 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2fdde9fa
AD		 2386 if (r) {
2387 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2388 amdgpu_gfx_scratch_free(adev, scratch);
b1023571 2389 return r;
2fdde9fa 2390 }
b1023571 2391
0f1dfd52
AD		 2392 /* set resources */
2393 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2394 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2395 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
de65513a
AR		 2396 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2397 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
0f1dfd52
AD		 2398 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2399 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2400 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2401 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
bd3402ea
AD		 2402 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2403 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2404 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2405 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2406
2407 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2408 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2409 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2410 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2411 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2412 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2413 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2414 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2415 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2416 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2417 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2418 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2419 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2420 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2421 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2422 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2423 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2424 }
2fdde9fa
AD		 2425 /* write to scratch for completion */
2426 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2427 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2428 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
464826d6 2429 amdgpu_ring_commit(kiq_ring);
b1023571 2430
2fdde9fa
AD		 2431 for (i = 0; i < adev->usec_timeout; i++) {
2432 tmp = RREG32(scratch);
2433 if (tmp == 0xDEADBEEF)
2434 break;
2435 DRM_UDELAY(1);
2436 }
2437 if (i >= adev->usec_timeout) {
2438 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2439 scratch, tmp);
2440 r = -EINVAL;
2441 }
2442 amdgpu_gfx_scratch_free(adev, scratch);
464826d6 2443
2fdde9fa 2444 return r;
464826d6
XY		 2445}
2446
e322edc3 2447static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 2448{
33fb8698 2449 struct amdgpu_device *adev = ring->adev;
e322edc3 2450 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2451 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2452 uint32_t tmp;
2453
2454 mqd->header = 0xC0310800;
2455 mqd->compute_pipelinestat_enable = 0x00000001;
2456 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2457 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2458 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2459 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2460 mqd->compute_misc_reserved = 0x00000003;
2461
ffe6d881
AD		 2462 mqd->dynamic_cu_mask_addr_lo =
2463 lower_32_bits(ring->mqd_gpu_addr
2464 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2465 mqd->dynamic_cu_mask_addr_hi =
2466 upper_32_bits(ring->mqd_gpu_addr
2467 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2468
d72f2f46 2469 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 2470 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2471 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2472
2473 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2474 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6 2475 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
268cb4c7 2476 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
464826d6
XY		 2477
2478 mqd->cp_hqd_eop_control = tmp;
2479
2480 /* enable doorbell? */
5e78835a 2481 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2482
2483 if (ring->use_doorbell) {
2484 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2485 DOORBELL_OFFSET, ring->doorbell_index);
2486 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2487 DOORBELL_EN, 1);
2488 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2489 DOORBELL_SOURCE, 0);
2490 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2491 DOORBELL_HIT, 0);
78888cff 2492 } else {
464826d6
XY		 2493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2494 DOORBELL_EN, 0);
78888cff 2495 }
464826d6
XY		 2496
2497 mqd->cp_hqd_pq_doorbell_control = tmp;
2498
2499 /* disable the queue if it's active */
2500 ring->wptr = 0;
2501 mqd->cp_hqd_dequeue_request = 0;
2502 mqd->cp_hqd_pq_rptr = 0;
2503 mqd->cp_hqd_pq_wptr_lo = 0;
2504 mqd->cp_hqd_pq_wptr_hi = 0;
2505
2506 /* set the pointer to the MQD */
33fb8698
AD		 2507 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2508 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 2509
2510 /* set MQD vmid to 0 */
5e78835a 2511 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 2512 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2513 mqd->cp_mqd_control = tmp;
2514
2515 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2516 hqd_gpu_addr = ring->gpu_addr >> 8;
2517 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2518 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2519
2520 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2521 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 2522 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2523 (order_base_2(ring->ring_size / 4) - 1));
2524 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2525 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2526#ifdef __BIG_ENDIAN
2527 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2528#endif
2529 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2530 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2531 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2532 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2533 mqd->cp_hqd_pq_control = tmp;
2534
2535 /* set the wb address whether it's enabled or not */
2536 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2537 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2538 mqd->cp_hqd_pq_rptr_report_addr_hi =
2539 upper_32_bits(wb_gpu_addr) & 0xffff;
2540
2541 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2542 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2543 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2544 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2545
2546 tmp = 0;
2547 /* enable the doorbell if requested */
2548 if (ring->use_doorbell) {
5e78835a 2549 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2550 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2551 DOORBELL_OFFSET, ring->doorbell_index);
2552
2553 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2554 DOORBELL_EN, 1);
2555 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2556 DOORBELL_SOURCE, 0);
2557 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2558 DOORBELL_HIT, 0);
2559 }
2560
2561 mqd->cp_hqd_pq_doorbell_control = tmp;
2562
2563 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2564 ring->wptr = 0;
0274a9c5 2565 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 2566
2567 /* set the vmid for the queue */
2568 mqd->cp_hqd_vmid = 0;
2569
0274a9c5 2570 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 2571 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2572 mqd->cp_hqd_persistent_state = tmp;
2573
fca4ce69
AD		 2574 /* set MIN_IB_AVAIL_SIZE */
2575 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2576 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2577 mqd->cp_hqd_ib_control = tmp;
2578
464826d6
XY		 2579 /* activate the queue */
2580 mqd->cp_hqd_active = 1;
2581
2582 return 0;
2583}
2584
e322edc3 2585static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2586{
33fb8698 2587 struct amdgpu_device *adev = ring->adev;
e322edc3 2588 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2589 int j;
2590
2591 /* disable wptr polling */
72edadd5 2592 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2593
5e78835a 2594 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2595 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2596 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2597 mqd->cp_hqd_eop_base_addr_hi);
2598
2599 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2600 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2601 mqd->cp_hqd_eop_control);
2602
2603 /* enable doorbell? */
5e78835a 2604 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2605 mqd->cp_hqd_pq_doorbell_control);
2606
2607 /* disable the queue if it's active */
5e78835a
TSD		 2608 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2609 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2610 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2611 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2612 break;
2613 udelay(1);
2614 }
5e78835a 2615 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2616 mqd->cp_hqd_dequeue_request);
5e78835a 2617 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2618 mqd->cp_hqd_pq_rptr);
5e78835a 2619 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2620 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2621 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2622 mqd->cp_hqd_pq_wptr_hi);
2623 }
2624
2625 /* set the pointer to the MQD */
5e78835a 2626 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2627 mqd->cp_mqd_base_addr_lo);
5e78835a 2628 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2629 mqd->cp_mqd_base_addr_hi);
2630
2631 /* set MQD vmid to 0 */
5e78835a 2632 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2633 mqd->cp_mqd_control);
2634
2635 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2636 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2637 mqd->cp_hqd_pq_base_lo);
5e78835a 2638 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2639 mqd->cp_hqd_pq_base_hi);
2640
2641 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2642 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2643 mqd->cp_hqd_pq_control);
2644
2645 /* set the wb address whether it's enabled or not */
5e78835a 2646 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2647 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2648 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2649 mqd->cp_hqd_pq_rptr_report_addr_hi);
2650
2651 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2652 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2653 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2654 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2655 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2656
2657 /* enable the doorbell if requested */
2658 if (ring->use_doorbell) {
5e78835a 2659 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2660 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2661 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2662 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2663 }
2664
5e78835a 2665 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2666 mqd->cp_hqd_pq_doorbell_control);
2667
2668 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2669 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2670 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2671 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2672 mqd->cp_hqd_pq_wptr_hi);
2673
2674 /* set the vmid for the queue */
5e78835a 2675 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2676
5e78835a 2677 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2678 mqd->cp_hqd_persistent_state);
2679
2680 /* activate the queue */
5e78835a 2681 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2682 mqd->cp_hqd_active);
2683
72edadd5
TSD		 2684 if (ring->use_doorbell)
2685 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2686
2687 return 0;
2688}
2689
e322edc3 2690static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2691{
2692 struct amdgpu_device *adev = ring->adev;
e322edc3 2693 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2694 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2695
898b7893 2696 gfx_v9_0_kiq_setting(ring);
464826d6 2697
ba0c19f5 2698 if (adev->gfx.in_reset) { /* for GPU_RESET case */
464826d6 2699 /* reset MQD to a clean status */
0ef376ca 2700 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2701 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2702
2703 /* reset ring buffer */
2704 ring->wptr = 0;
b98724db 2705 amdgpu_ring_clear_ring(ring);
464826d6 2706
898b7893
AD		 2707 mutex_lock(&adev->srbm_mutex);
2708 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2709 gfx_v9_0_kiq_init_register(ring);
2710 soc15_grbm_select(adev, 0, 0, 0, 0);
2711 mutex_unlock(&adev->srbm_mutex);
464826d6 2712 } else {
ffe6d881
AD		 2713 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2714 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2715 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
ba0c19f5
AD		 2716 mutex_lock(&adev->srbm_mutex);
2717 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2718 gfx_v9_0_mqd_init(ring);
2719 gfx_v9_0_kiq_init_register(ring);
2720 soc15_grbm_select(adev, 0, 0, 0, 0);
2721 mutex_unlock(&adev->srbm_mutex);
2722
2723 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2724 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
464826d6
XY		 2725 }
2726
0f1dfd52 2727 return 0;
898b7893
AD		 2728}
2729
2730static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2731{
2732 struct amdgpu_device *adev = ring->adev;
898b7893
AD		 2733 struct v9_mqd *mqd = ring->mqd_ptr;
2734 int mqd_idx = ring - &adev->gfx.compute_ring[0];
898b7893 2735
e30a5223 2736 if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
ffe6d881
AD		 2737 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2738 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2739 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
464826d6
XY		 2740 mutex_lock(&adev->srbm_mutex);
2741 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2742 gfx_v9_0_mqd_init(ring);
464826d6
XY		 2743 soc15_grbm_select(adev, 0, 0, 0, 0);
2744 mutex_unlock(&adev->srbm_mutex);
2745
898b7893 2746 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2747 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
ba0c19f5 2748 } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
464826d6 2749 /* reset MQD to a clean status */
898b7893 2750 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2751 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2752
2753 /* reset ring buffer */
2754 ring->wptr = 0;
898b7893 2755 amdgpu_ring_clear_ring(ring);
ba0c19f5
AD		 2756 } else {
2757 amdgpu_ring_clear_ring(ring);
464826d6
XY		 2758 }
2759
464826d6
XY		 2760 return 0;
2761}
2762
2763static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2764{
2765 struct amdgpu_ring *ring = NULL;
2766 int r = 0, i;
2767
2768 gfx_v9_0_cp_compute_enable(adev, true);
2769
2770 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2771
2772 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2773 if (unlikely(r != 0))
2774 goto done;
2775
2776 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2777 if (!r) {
e322edc3 2778 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2779 amdgpu_bo_kunmap(ring->mqd_obj);
2780 ring->mqd_ptr = NULL;
464826d6 2781 }
e1d53aa8
AD		 2782 amdgpu_bo_unreserve(ring->mqd_obj);
2783 if (r)
2784 goto done;
464826d6
XY		 2785
2786 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2787 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2788
2789 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2790 if (unlikely(r != 0))
2791 goto done;
2792 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2793 if (!r) {
898b7893 2794 r = gfx_v9_0_kcq_init_queue(ring);
464826d6
XY		 2795 amdgpu_bo_kunmap(ring->mqd_obj);
2796 ring->mqd_ptr = NULL;
464826d6 2797 }
e1d53aa8
AD		 2798 amdgpu_bo_unreserve(ring->mqd_obj);
2799 if (r)
2800 goto done;
464826d6
XY		 2801 }
2802
0f1dfd52 2803 r = gfx_v9_0_kiq_kcq_enable(adev);
e1d53aa8
AD		 2804done:
2805 return r;
464826d6
XY		 2806}
2807
b1023571
KW		 2808static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2809{
bd3402ea 2810 int r, i;
b1023571
KW		 2811 struct amdgpu_ring *ring;
2812
2813 if (!(adev->flags & AMD_IS_APU))
2814 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2815
2816 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2817 /* legacy firmware loading */
2818 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2819 if (r)
2820 return r;
2821
2822 r = gfx_v9_0_cp_compute_load_microcode(adev);
2823 if (r)
2824 return r;
2825 }
2826
2827 r = gfx_v9_0_cp_gfx_resume(adev);
2828 if (r)
2829 return r;
2830
e30a5223 2831 r = gfx_v9_0_kiq_resume(adev);
b1023571
KW		 2832 if (r)
2833 return r;
2834
2835 ring = &adev->gfx.gfx_ring[0];
2836 r = amdgpu_ring_test_ring(ring);
2837 if (r) {
2838 ring->ready = false;
2839 return r;
2840 }
e30a5223
AD		 2841
2842 ring = &adev->gfx.kiq.ring;
2843 ring->ready = true;
2844 r = amdgpu_ring_test_ring(ring);
2845 if (r)
2846 ring->ready = false;
2847
b1023571
KW		 2848 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2849 ring = &adev->gfx.compute_ring[i];
2850
2851 ring->ready = true;
2852 r = amdgpu_ring_test_ring(ring);
2853 if (r)
2854 ring->ready = false;
2855 }
2856
2857 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2858
2859 return 0;
2860}
2861
2862static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2863{
2864 gfx_v9_0_cp_gfx_enable(adev, enable);
2865 gfx_v9_0_cp_compute_enable(adev, enable);
2866}
2867
2868static int gfx_v9_0_hw_init(void *handle)
2869{
2870 int r;
2871 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2872
2873 gfx_v9_0_init_golden_registers(adev);
2874
2875 gfx_v9_0_gpu_init(adev);
2876
2877 r = gfx_v9_0_rlc_resume(adev);
2878 if (r)
2879 return r;
2880
2881 r = gfx_v9_0_cp_resume(adev);
2882 if (r)
2883 return r;
2884
2885 r = gfx_v9_0_ngg_en(adev);
2886 if (r)
2887 return r;
2888
2889 return r;
2890}
2891
2892static int gfx_v9_0_hw_fini(void *handle)
2893{
2894 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2895
2896 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2897 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
464826d6
XY		 2898 if (amdgpu_sriov_vf(adev)) {
2899 pr_debug("For SRIOV client, shouldn't do anything.\n");
2900 return 0;
2901 }
b1023571
KW		 2902 gfx_v9_0_cp_enable(adev, false);
2903 gfx_v9_0_rlc_stop(adev);
b1023571
KW		 2904
2905 return 0;
2906}
2907
2908static int gfx_v9_0_suspend(void *handle)
2909{
2910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2911
e30a5223 2912 adev->gfx.in_suspend = true;
b1023571
KW		 2913 return gfx_v9_0_hw_fini(adev);
2914}
2915
2916static int gfx_v9_0_resume(void *handle)
2917{
2918 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e30a5223 2919 int r;
b1023571 2920
e30a5223
AD		 2921 r = gfx_v9_0_hw_init(adev);
2922 adev->gfx.in_suspend = false;
2923 return r;
b1023571
KW		 2924}
2925
2926static bool gfx_v9_0_is_idle(void *handle)
2927{
2928 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2929
5e78835a 2930 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 2931 GRBM_STATUS, GUI_ACTIVE))
2932 return false;
2933 else
2934 return true;
2935}
2936
2937static int gfx_v9_0_wait_for_idle(void *handle)
2938{
2939 unsigned i;
2940 u32 tmp;
2941 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2942
2943 for (i = 0; i < adev->usec_timeout; i++) {
2944 /* read MC_STATUS */
5e78835a 2945 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
b1023571
KW		 2946 GRBM_STATUS__GUI_ACTIVE_MASK;
2947
2948 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
2949 return 0;
2950 udelay(1);
2951 }
2952 return -ETIMEDOUT;
2953}
2954
b1023571
KW		 2955static int gfx_v9_0_soft_reset(void *handle)
2956{
2957 u32 grbm_soft_reset = 0;
2958 u32 tmp;
2959 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2960
2961 /* GRBM_STATUS */
5e78835a 2962 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 2963 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2964 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2965 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2966 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2967 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2968 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2969 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2970 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2971 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2972 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2973 }
2974
2975 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2976 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2977 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2978 }
2979
2980 /* GRBM_STATUS2 */
5e78835a 2981 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 2982 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2983 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2984 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2985
2986
75bac5c6 2987 if (grbm_soft_reset) {
b1023571
KW		 2988 /* stop the rlc */
2989 gfx_v9_0_rlc_stop(adev);
2990
2991 /* Disable GFX parsing/prefetching */
2992 gfx_v9_0_cp_gfx_enable(adev, false);
2993
2994 /* Disable MEC parsing/prefetching */
2995 gfx_v9_0_cp_compute_enable(adev, false);
2996
2997 if (grbm_soft_reset) {
5e78835a 2998 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 2999 tmp |= grbm_soft_reset;
3000 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 3001 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3002 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3003
3004 udelay(50);
3005
3006 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 3007 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3008 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3009 }
3010
3011 /* Wait a little for things to settle down */
3012 udelay(50);
b1023571
KW		 3013 }
3014 return 0;
3015}
3016
3017static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3018{
3019 uint64_t clock;
3020
3021 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 3022 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3023 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3024 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 3025 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3026 return clock;
3027}
3028
3029static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3030 uint32_t vmid,
3031 uint32_t gds_base, uint32_t gds_size,
3032 uint32_t gws_base, uint32_t gws_size,
3033 uint32_t oa_base, uint32_t oa_size)
3034{
3035 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3036 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3037
3038 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3039 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3040
3041 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3042 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3043
3044 /* GDS Base */
3045 gfx_v9_0_write_data_to_reg(ring, 0, false,
3046 amdgpu_gds_reg_offset[vmid].mem_base,
3047 gds_base);
3048
3049 /* GDS Size */
3050 gfx_v9_0_write_data_to_reg(ring, 0, false,
3051 amdgpu_gds_reg_offset[vmid].mem_size,
3052 gds_size);
3053
3054 /* GWS */
3055 gfx_v9_0_write_data_to_reg(ring, 0, false,
3056 amdgpu_gds_reg_offset[vmid].gws,
3057 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3058
3059 /* OA */
3060 gfx_v9_0_write_data_to_reg(ring, 0, false,
3061 amdgpu_gds_reg_offset[vmid].oa,
3062 (1 << (oa_size + oa_base)) - (1 << oa_base));
3063}
3064
3065static int gfx_v9_0_early_init(void *handle)
3066{
3067 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3068
3069 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
78c16834 3070 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
b1023571
KW		 3071 gfx_v9_0_set_ring_funcs(adev);
3072 gfx_v9_0_set_irq_funcs(adev);
3073 gfx_v9_0_set_gds_init(adev);
3074 gfx_v9_0_set_rlc_funcs(adev);
3075
3076 return 0;
3077}
3078
3079static int gfx_v9_0_late_init(void *handle)
3080{
3081 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3082 int r;
3083
3084 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3085 if (r)
3086 return r;
3087
3088 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3089 if (r)
3090 return r;
3091
3092 return 0;
3093}
3094
3095static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3096{
3097 uint32_t rlc_setting, data;
3098 unsigned i;
3099
3100 if (adev->gfx.rlc.in_safe_mode)
3101 return;
3102
3103 /* if RLC is not enabled, do nothing */
5e78835a 3104 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3105 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3106 return;
3107
3108 if (adev->cg_flags &
3109 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3110 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3111 data = RLC_SAFE_MODE__CMD_MASK;
3112 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 3113 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3114
3115 /* wait for RLC_SAFE_MODE */
3116 for (i = 0; i < adev->usec_timeout; i++) {
3117 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3118 break;
3119 udelay(1);
3120 }
3121 adev->gfx.rlc.in_safe_mode = true;
3122 }
3123}
3124
3125static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3126{
3127 uint32_t rlc_setting, data;
3128
3129 if (!adev->gfx.rlc.in_safe_mode)
3130 return;
3131
3132 /* if RLC is not enabled, do nothing */
5e78835a 3133 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3134 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3135 return;
3136
3137 if (adev->cg_flags &
3138 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3139 /*
3140 * Try to exit safe mode only if it is already in safe
3141 * mode.
3142 */
3143 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 3144 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3145 adev->gfx.rlc.in_safe_mode = false;
3146 }
3147}
3148
197f95c8
HZ		 3149static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3150 bool enable)
3151{
3152 /* TODO: double check if we need to perform under safe mdoe */
3153 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3154
3155 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3156 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3157 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3158 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3159 } else {
3160 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3161 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3162 }
3163
3164 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3165}
3166
18924c71
HZ		 3167static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3168 bool enable)
3169{
3170 /* TODO: double check if we need to perform under safe mode */
3171 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3172
3173 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3174 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3175 else
3176 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3177
3178 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3179 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3180 else
3181 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3182
3183 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3184}
3185
b1023571
KW		 3186static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3187 bool enable)
3188{
3189 uint32_t data, def;
3190
3191 /* It is disabled by HW by default */
3192 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3193 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 3194 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3195 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3196 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3197 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3198 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3199
3200 /* only for Vega10 & Raven1 */
3201 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3202
3203 if (def != data)
5e78835a 3204 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3205
3206 /* MGLS is a global flag to control all MGLS in GFX */
3207 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3208 /* 2 - RLC memory Light sleep */
3209 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 3210 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3211 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3212 if (def != data)
5e78835a 3213 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3214 }
3215 /* 3 - CP memory Light sleep */
3216 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 3217 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3218 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3219 if (def != data)
5e78835a 3220 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3221 }
3222 }
3223 } else {
3224 /* 1 - MGCG_OVERRIDE */
5e78835a 3225 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3226 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3227 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3228 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3229 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3230 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3231 if (def != data)
5e78835a 3232 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3233
3234 /* 2 - disable MGLS in RLC */
5e78835a 3235 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3236 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3237 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 3238 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3239 }
3240
3241 /* 3 - disable MGLS in CP */
5e78835a 3242 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3243 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3244 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 3245 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3246 }
3247 }
3248}
3249
3250static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3251 bool enable)
3252{
3253 uint32_t data, def;
3254
3255 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3256
3257 /* Enable 3D CGCG/CGLS */
3258 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3259 /* write cmd to clear cgcg/cgls ov */
5e78835a 3260 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3261 /* unset CGCG override */
3262 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3263 /* update CGCG and CGLS override bits */
3264 if (def != data)
5e78835a 3265 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 3266 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 3267 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3268 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3269 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3270 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3271 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3272 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3273 if (def != data)
5e78835a 3274 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3275
3276 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3277 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3278 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3279 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3280 if (def != data)
5e78835a 3281 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 3282 } else {
3283 /* Disable CGCG/CGLS */
5e78835a 3284 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3285 /* disable cgcg, cgls should be disabled */
3286 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3287 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3288 /* disable cgcg and cgls in FSM */
3289 if (def != data)
5e78835a 3290 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3291 }
3292
3293 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3294}
3295
3296static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3297 bool enable)
3298{
3299 uint32_t def, data;
3300
3301 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3302
3303 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 3304 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3305 /* unset CGCG override */
3306 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3307 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3308 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3309 else
3310 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3311 /* update CGCG and CGLS override bits */
3312 if (def != data)
5e78835a 3313 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3314
3315 /* enable cgcg FSM(0x0020003F) */
5e78835a 3316 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3317 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3318 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3319 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3320 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3321 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3322 if (def != data)
5e78835a 3323 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3324
3325 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3326 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3327 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3328 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3329 if (def != data)
5e78835a 3330 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 3331 } else {
5e78835a 3332 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3333 /* reset CGCG/CGLS bits */
3334 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3335 /* disable cgcg and cgls in FSM */
3336 if (def != data)
5e78835a 3337 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3338 }
3339
3340 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3341}
3342
3343static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3344 bool enable)
3345{
3346 if (enable) {
3347 /* CGCG/CGLS should be enabled after MGCG/MGLS
3348 * === MGCG + MGLS ===
3349 */
3350 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3351 /* === CGCG /CGLS for GFX 3D Only === */
3352 gfx_v9_0_update_3d_clock_gating(adev, enable);
3353 /* === CGCG + CGLS === */
3354 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3355 } else {
3356 /* CGCG/CGLS should be disabled before MGCG/MGLS
3357 * === CGCG + CGLS ===
3358 */
3359 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3360 /* === CGCG /CGLS for GFX 3D Only === */
3361 gfx_v9_0_update_3d_clock_gating(adev, enable);
3362 /* === MGCG + MGLS === */
3363 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3364 }
3365 return 0;
3366}
3367
3368static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3369 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3370 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3371};
3372
3373static int gfx_v9_0_set_powergating_state(void *handle,
3374 enum amd_powergating_state state)
3375{
5897c99e 3376 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197f95c8 3377 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
5897c99e
HZ		 3378
3379 switch (adev->asic_type) {
3380 case CHIP_RAVEN:
3381 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3382 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3383 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3384 } else {
3385 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3386 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3387 }
3388
3389 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3390 gfx_v9_0_enable_cp_power_gating(adev, true);
3391 else
3392 gfx_v9_0_enable_cp_power_gating(adev, false);
197f95c8
HZ		 3393
3394 /* update gfx cgpg state */
3395 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
18924c71
HZ		 3396
3397 /* update mgcg state */
3398 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5897c99e
HZ		 3399 break;
3400 default:
3401 break;
3402 }
3403
b1023571
KW		 3404 return 0;
3405}
3406
3407static int gfx_v9_0_set_clockgating_state(void *handle,
3408 enum amd_clockgating_state state)
3409{
3410 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3411
fb82afab
XY		 3412 if (amdgpu_sriov_vf(adev))
3413 return 0;
3414
b1023571
KW		 3415 switch (adev->asic_type) {
3416 case CHIP_VEGA10:
a4dc61f5 3417 case CHIP_RAVEN:
b1023571
KW		 3418 gfx_v9_0_update_gfx_clock_gating(adev,
3419 state == AMD_CG_STATE_GATE ? true : false);
3420 break;
3421 default:
3422 break;
3423 }
3424 return 0;
3425}
3426
12ad27fa
HR		 3427static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3428{
3429 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3430 int data;
3431
3432 if (amdgpu_sriov_vf(adev))
3433 *flags = 0;
3434
3435 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 3436 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 3437 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3438 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3439
3440 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 3441 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 3442 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3443 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3444
3445 /* AMD_CG_SUPPORT_GFX_CGLS */
3446 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3447 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3448
3449 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 3450 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 3451 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3452 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3453
3454 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 3455 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 3456 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3457 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3458
3459 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 3460 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 3461 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3462 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3463
3464 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3465 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3466 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3467}
3468
b1023571
KW		 3469static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3470{
3471 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3472}
3473
3474static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3475{
3476 struct amdgpu_device *adev = ring->adev;
3477 u64 wptr;
3478
3479 /* XXX check if swapping is necessary on BE */
3480 if (ring->use_doorbell) {
3481 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3482 } else {
5e78835a
TSD		 3483 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3484 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 3485 }
3486
3487 return wptr;
3488}
3489
3490static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3491{
3492 struct amdgpu_device *adev = ring->adev;
3493
3494 if (ring->use_doorbell) {
3495 /* XXX check if swapping is necessary on BE */
3496 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3497 WDOORBELL64(ring->doorbell_index, ring->wptr);
3498 } else {
5e78835a
TSD		 3499 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3500 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 3501 }
3502}
3503
3504static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3505{
3506 u32 ref_and_mask, reg_mem_engine;
3507 struct nbio_hdp_flush_reg *nbio_hf_reg;
3508
3509 if (ring->adev->asic_type == CHIP_VEGA10)
3510 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3511
3512 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3513 switch (ring->me) {
3514 case 1:
3515 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3516 break;
3517 case 2:
3518 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3519 break;
3520 default:
3521 return;
3522 }
3523 reg_mem_engine = 0;
3524 } else {
3525 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3526 reg_mem_engine = 1; /* pfp */
3527 }
3528
3529 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3530 nbio_hf_reg->hdp_flush_req_offset,
3531 nbio_hf_reg->hdp_flush_done_offset,
3532 ref_and_mask, ref_and_mask, 0x20);
3533}
3534
3535static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3536{
3537 gfx_v9_0_write_data_to_reg(ring, 0, true,
3538 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3539}
3540
3541static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3542 struct amdgpu_ib *ib,
3543 unsigned vm_id, bool ctx_switch)
3544{
eaa05d52 3545 u32 header, control = 0;
b1023571 3546
eaa05d52
ML		 3547 if (ib->flags & AMDGPU_IB_FLAG_CE)
3548 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3549 else
3550 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
b1023571 3551
eaa05d52 3552 control |= ib->length_dw | (vm_id << 24);
b1023571 3553
635e7132 3554 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
eaa05d52 3555 control |= INDIRECT_BUFFER_PRE_ENB(1);
9ccd52eb 3556
635e7132
ML		 3557 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3558 gfx_v9_0_ring_emit_de_meta(ring);
3559 }
3560
eaa05d52
ML		 3561 amdgpu_ring_write(ring, header);
3562BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3563 amdgpu_ring_write(ring,
b1023571 3564#ifdef __BIG_ENDIAN
eaa05d52 3565 (2 << 0) |
b1023571 3566#endif
eaa05d52
ML		 3567 lower_32_bits(ib->gpu_addr));
3568 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3569 amdgpu_ring_write(ring, control);
b1023571
KW		 3570}
3571
b1023571
KW		 3572static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3573 struct amdgpu_ib *ib,
3574 unsigned vm_id, bool ctx_switch)
3575{
3576 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3577
3578 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3579 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3580 amdgpu_ring_write(ring,
3581#ifdef __BIG_ENDIAN
3582 (2 << 0) |
3583#endif
3584 lower_32_bits(ib->gpu_addr));
3585 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3586 amdgpu_ring_write(ring, control);
3587}
3588
3589static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3590 u64 seq, unsigned flags)
3591{
3592 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3593 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3594
3595 /* RELEASE_MEM - flush caches, send int */
3596 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3597 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3598 EOP_TC_ACTION_EN |
3599 EOP_TC_WB_ACTION_EN |
3600 EOP_TC_MD_ACTION_EN |
3601 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3602 EVENT_INDEX(5)));
3603 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3604
3605 /*
3606 * the address should be Qword aligned if 64bit write, Dword
3607 * aligned if only send 32bit data low (discard data high)
3608 */
3609 if (write64bit)
3610 BUG_ON(addr & 0x7);
3611 else
3612 BUG_ON(addr & 0x3);
3613 amdgpu_ring_write(ring, lower_32_bits(addr));
3614 amdgpu_ring_write(ring, upper_32_bits(addr));
3615 amdgpu_ring_write(ring, lower_32_bits(seq));
3616 amdgpu_ring_write(ring, upper_32_bits(seq));
3617 amdgpu_ring_write(ring, 0);
3618}
3619
3620static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3621{
3622 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3623 uint32_t seq = ring->fence_drv.sync_seq;
3624 uint64_t addr = ring->fence_drv.gpu_addr;
3625
3626 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3627 lower_32_bits(addr), upper_32_bits(addr),
3628 seq, 0xffffffff, 4);
3629}
3630
3631static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3632 unsigned vm_id, uint64_t pd_addr)
3633{
2e819849 3634 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
b1023571 3635 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 3636 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 3637 unsigned eng = ring->vm_inv_eng;
b1023571 3638
b1166325
CK		 3639 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3640 pd_addr |= AMDGPU_PTE_VALID;
b1023571 3641
2e819849
CK		 3642 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3643 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3644 lower_32_bits(pd_addr));
b1023571 3645
2e819849
CK		 3646 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3647 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3648 upper_32_bits(pd_addr));
b1023571 3649
2e819849
CK		 3650 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3651 hub->vm_inv_eng0_req + eng, req);
b1023571 3652
2e819849
CK		 3653 /* wait for the invalidate to complete */
3654 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3655 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
b1023571
KW		 3656
3657 /* compute doesn't have PFP */
3658 if (usepfp) {
3659 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3660 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3661 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3662 }
3663}
3664
3665static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3666{
3667 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3668}
3669
3670static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3671{
3672 u64 wptr;
3673
3674 /* XXX check if swapping is necessary on BE */
3675 if (ring->use_doorbell)
3676 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3677 else
3678 BUG();
3679 return wptr;
3680}
3681
3682static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3683{
3684 struct amdgpu_device *adev = ring->adev;
3685
3686 /* XXX check if swapping is necessary on BE */
3687 if (ring->use_doorbell) {
3688 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3689 WDOORBELL64(ring->doorbell_index, ring->wptr);
3690 } else{
3691 BUG(); /* only DOORBELL method supported on gfx9 now */
3692 }
3693}
3694
aa6faa44
XY		 3695static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3696 u64 seq, unsigned int flags)
3697{
3698 /* we only allocate 32bit for each seq wb address */
3699 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3700
3701 /* write fence seq to the "addr" */
3702 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3703 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3704 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3705 amdgpu_ring_write(ring, lower_32_bits(addr));
3706 amdgpu_ring_write(ring, upper_32_bits(addr));
3707 amdgpu_ring_write(ring, lower_32_bits(seq));
3708
3709 if (flags & AMDGPU_FENCE_FLAG_INT) {
3710 /* set register to trigger INT */
3711 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3712 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3713 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3714 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3715 amdgpu_ring_write(ring, 0);
3716 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3717 }
3718}
3719
b1023571
KW		 3720static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3721{
3722 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3723 amdgpu_ring_write(ring, 0);
3724}
3725
cca02cd3
XY		 3726static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3727{
3728 static struct v9_ce_ib_state ce_payload = {0};
3729 uint64_t csa_addr;
3730 int cnt;
3731
3732 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3733 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3734
3735 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3736 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3737 WRITE_DATA_DST_SEL(8) |
3738 WR_CONFIRM) |
3739 WRITE_DATA_CACHE_POLICY(0));
3740 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3741 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3742 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3743}
3744
3745static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3746{
3747 static struct v9_de_ib_state de_payload = {0};
3748 uint64_t csa_addr, gds_addr;
3749 int cnt;
3750
3751 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3752 gds_addr = csa_addr + 4096;
3753 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3754 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3755
3756 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3757 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3758 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3759 WRITE_DATA_DST_SEL(8) |
3760 WR_CONFIRM) |
3761 WRITE_DATA_CACHE_POLICY(0));
3762 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3763 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3764 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3765}
3766
b1023571
KW		 3767static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3768{
3769 uint32_t dw2 = 0;
3770
cca02cd3
XY		 3771 if (amdgpu_sriov_vf(ring->adev))
3772 gfx_v9_0_ring_emit_ce_meta(ring);
3773
b1023571
KW		 3774 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3775 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3776 /* set load_global_config & load_global_uconfig */
3777 dw2 |= 0x8001;
3778 /* set load_cs_sh_regs */
3779 dw2 |= 0x01000000;
3780 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3781 dw2 |= 0x10002;
3782
3783 /* set load_ce_ram if preamble presented */
3784 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3785 dw2 |= 0x10000000;
3786 } else {
3787 /* still load_ce_ram if this is the first time preamble presented
3788 * although there is no context switch happens.
3789 */
3790 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3791 dw2 |= 0x10000000;
3792 }
3793
3794 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3795 amdgpu_ring_write(ring, dw2);
3796 amdgpu_ring_write(ring, 0);
3797}
3798
9a5e02b5
ML		 3799static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3800{
3801 unsigned ret;
3802 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3803 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3804 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3805 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3806 ret = ring->wptr & ring->buf_mask;
3807 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3808 return ret;
3809}
3810
3811static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3812{
3813 unsigned cur;
3814 BUG_ON(offset > ring->buf_mask);
3815 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3816
3817 cur = (ring->wptr & ring->buf_mask) - 1;
3818 if (likely(cur > offset))
3819 ring->ring[offset] = cur - offset;
3820 else
3821 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3822}
3823
3b4d68e9
ML		 3824static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3825{
3826 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3827 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3828}
3829
aa6faa44
XY		 3830static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3831{
3832 struct amdgpu_device *adev = ring->adev;
3833
3834 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3835 amdgpu_ring_write(ring, 0 | /* src: register*/
3836 (5 << 8) | /* dst: memory */
3837 (1 << 20)); /* write confirm */
3838 amdgpu_ring_write(ring, reg);
3839 amdgpu_ring_write(ring, 0);
3840 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3841 adev->virt.reg_val_offs * 4));
3842 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3843 adev->virt.reg_val_offs * 4));
3844}
3845
3846static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3847 uint32_t val)
3848{
3849 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3850 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3851 amdgpu_ring_write(ring, reg);
3852 amdgpu_ring_write(ring, 0);
3853 amdgpu_ring_write(ring, val);
3854}
3855
b1023571
KW		 3856static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3857 enum amdgpu_interrupt_state state)
3858{
b1023571
KW		 3859 switch (state) {
3860 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3861 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 3862 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3863 TIME_STAMP_INT_ENABLE,
3864 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3865 break;
3866 default:
3867 break;
3868 }
3869}
3870
3871static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3872 int me, int pipe,
3873 enum amdgpu_interrupt_state state)
3874{
3875 u32 mec_int_cntl, mec_int_cntl_reg;
3876
3877 /*
d0c55cdf
AD		 3878 * amdgpu controls only the first MEC. That's why this function only
3879 * handles the setting of interrupts for this specific MEC. All other
b1023571
KW		 3880 * pipes' interrupts are set by amdkfd.
3881 */
3882
3883 if (me == 1) {
3884 switch (pipe) {
3885 case 0:
3886 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3887 break;
d0c55cdf
AD		 3888 case 1:
3889 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
3890 break;
3891 case 2:
3892 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
3893 break;
3894 case 3:
3895 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
3896 break;
b1023571
KW		 3897 default:
3898 DRM_DEBUG("invalid pipe %d\n", pipe);
3899 return;
3900 }
3901 } else {
3902 DRM_DEBUG("invalid me %d\n", me);
3903 return;
3904 }
3905
3906 switch (state) {
3907 case AMDGPU_IRQ_STATE_DISABLE:
3908 mec_int_cntl = RREG32(mec_int_cntl_reg);
3909 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3910 TIME_STAMP_INT_ENABLE, 0);
3911 WREG32(mec_int_cntl_reg, mec_int_cntl);
3912 break;
3913 case AMDGPU_IRQ_STATE_ENABLE:
3914 mec_int_cntl = RREG32(mec_int_cntl_reg);
3915 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3916 TIME_STAMP_INT_ENABLE, 1);
3917 WREG32(mec_int_cntl_reg, mec_int_cntl);
3918 break;
3919 default:
3920 break;
3921 }
3922}
3923
3924static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3925 struct amdgpu_irq_src *source,
3926 unsigned type,
3927 enum amdgpu_interrupt_state state)
3928{
b1023571
KW		 3929 switch (state) {
3930 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3931 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 3932 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3933 PRIV_REG_INT_ENABLE,
3934 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3935 break;
3936 default:
3937 break;
3938 }
3939
3940 return 0;
3941}
3942
3943static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3944 struct amdgpu_irq_src *source,
3945 unsigned type,
3946 enum amdgpu_interrupt_state state)
3947{
b1023571
KW		 3948 switch (state) {
3949 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3950 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 3951 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3952 PRIV_INSTR_INT_ENABLE,
3953 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3954 default:
3955 break;
3956 }
3957
3958 return 0;
3959}
3960
3961static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3962 struct amdgpu_irq_src *src,
3963 unsigned type,
3964 enum amdgpu_interrupt_state state)
3965{
3966 switch (type) {
3967 case AMDGPU_CP_IRQ_GFX_EOP:
3968 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
3969 break;
3970 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3971 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
3972 break;
3973 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3974 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
3975 break;
3976 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
3977 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
3978 break;
3979 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
3980 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
3981 break;
3982 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
3983 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
3984 break;
3985 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
3986 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
3987 break;
3988 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
3989 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
3990 break;
3991 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
3992 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
3993 break;
3994 default:
3995 break;
3996 }
3997 return 0;
3998}
3999
4000static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4001 struct amdgpu_irq_src *source,
4002 struct amdgpu_iv_entry *entry)
4003{
4004 int i;
4005 u8 me_id, pipe_id, queue_id;
4006 struct amdgpu_ring *ring;
4007
4008 DRM_DEBUG("IH: CP EOP\n");
4009 me_id = (entry->ring_id & 0x0c) >> 2;
4010 pipe_id = (entry->ring_id & 0x03) >> 0;
4011 queue_id = (entry->ring_id & 0x70) >> 4;
4012
4013 switch (me_id) {
4014 case 0:
4015 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4016 break;
4017 case 1:
4018 case 2:
4019 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4020 ring = &adev->gfx.compute_ring[i];
4021 /* Per-queue interrupt is supported for MEC starting from VI.
4022 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4023 */
4024 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4025 amdgpu_fence_process(ring);
4026 }
4027 break;
4028 }
4029 return 0;
4030}
4031
4032static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4033 struct amdgpu_irq_src *source,
4034 struct amdgpu_iv_entry *entry)
4035{
4036 DRM_ERROR("Illegal register access in command stream\n");
4037 schedule_work(&adev->reset_work);
4038 return 0;
4039}
4040
4041static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4042 struct amdgpu_irq_src *source,
4043 struct amdgpu_iv_entry *entry)
4044{
4045 DRM_ERROR("Illegal instruction in command stream\n");
4046 schedule_work(&adev->reset_work);
4047 return 0;
4048}
4049
97031e25
XY		 4050static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4051 struct amdgpu_irq_src *src,
4052 unsigned int type,
4053 enum amdgpu_interrupt_state state)
4054{
4055 uint32_t tmp, target;
1c4ecf48 4056 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4057
4058 if (ring->me == 1)
4059 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4060 else
4061 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4062 target += ring->pipe;
4063
4064 switch (type) {
4065 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4066 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 4067 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4068 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4069 GENERIC2_INT_ENABLE, 0);
5e78835a 4070 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4071
4072 tmp = RREG32(target);
4073 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4074 GENERIC2_INT_ENABLE, 0);
4075 WREG32(target, tmp);
4076 } else {
5e78835a 4077 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4078 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4079 GENERIC2_INT_ENABLE, 1);
5e78835a 4080 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4081
4082 tmp = RREG32(target);
4083 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4084 GENERIC2_INT_ENABLE, 1);
4085 WREG32(target, tmp);
4086 }
4087 break;
4088 default:
4089 BUG(); /* kiq only support GENERIC2_INT now */
4090 break;
4091 }
4092 return 0;
4093}
4094
4095static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4096 struct amdgpu_irq_src *source,
4097 struct amdgpu_iv_entry *entry)
4098{
4099 u8 me_id, pipe_id, queue_id;
1c4ecf48 4100 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4101
4102 me_id = (entry->ring_id & 0x0c) >> 2;
4103 pipe_id = (entry->ring_id & 0x03) >> 0;
4104 queue_id = (entry->ring_id & 0x70) >> 4;
4105 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4106 me_id, pipe_id, queue_id);
4107
4108 amdgpu_fence_process(ring);
4109 return 0;
4110}
4111
fa04b6ba 4112static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
b1023571
KW		 4113 .name = "gfx_v9_0",
4114 .early_init = gfx_v9_0_early_init,
4115 .late_init = gfx_v9_0_late_init,
4116 .sw_init = gfx_v9_0_sw_init,
4117 .sw_fini = gfx_v9_0_sw_fini,
4118 .hw_init = gfx_v9_0_hw_init,
4119 .hw_fini = gfx_v9_0_hw_fini,
4120 .suspend = gfx_v9_0_suspend,
4121 .resume = gfx_v9_0_resume,
4122 .is_idle = gfx_v9_0_is_idle,
4123 .wait_for_idle = gfx_v9_0_wait_for_idle,
4124 .soft_reset = gfx_v9_0_soft_reset,
4125 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4126 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 4127 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 4128};
4129
4130static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4131 .type = AMDGPU_RING_TYPE_GFX,
4132 .align_mask = 0xff,
4133 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4134 .support_64bit_ptrs = true,
0eeb68b3 4135 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4136 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4137 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4138 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 4139 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4140 5 + /* COND_EXEC */
4141 7 + /* PIPELINE_SYNC */
2e819849 4142 24 + /* VM_FLUSH */
e9d672b2
ML		 4143 8 + /* FENCE for VM_FLUSH */
4144 20 + /* GDS switch */
4145 4 + /* double SWITCH_BUFFER,
4146 the first COND_EXEC jump to the place just
4147 prior to this double SWITCH_BUFFER */
4148 5 + /* COND_EXEC */
4149 7 + /* HDP_flush */
4150 4 + /* VGT_flush */
4151 14 + /* CE_META */
4152 31 + /* DE_META */
4153 3 + /* CNTX_CTRL */
4154 5 + /* HDP_INVL */
4155 8 + 8 + /* FENCE x2 */
4156 2, /* SWITCH_BUFFER */
b1023571
KW		 4157 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4158 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4159 .emit_fence = gfx_v9_0_ring_emit_fence,
4160 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4161 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4162 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4163 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4164 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4165 .test_ring = gfx_v9_0_ring_test_ring,
4166 .test_ib = gfx_v9_0_ring_test_ib,
4167 .insert_nop = amdgpu_ring_insert_nop,
4168 .pad_ib = amdgpu_ring_generic_pad_ib,
4169 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4170 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 4171 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4172 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3b4d68e9 4173 .emit_tmz = gfx_v9_0_ring_emit_tmz,
b1023571
KW		 4174};
4175
4176static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4177 .type = AMDGPU_RING_TYPE_COMPUTE,
4178 .align_mask = 0xff,
4179 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4180 .support_64bit_ptrs = true,
0eeb68b3 4181 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4182 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4183 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4184 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4185 .emit_frame_size =
4186 20 + /* gfx_v9_0_ring_emit_gds_switch */
4187 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4188 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4189 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4190 24 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 4191 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4192 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4193 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4194 .emit_fence = gfx_v9_0_ring_emit_fence,
4195 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4196 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4197 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4198 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4199 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4200 .test_ring = gfx_v9_0_ring_test_ring,
4201 .test_ib = gfx_v9_0_ring_test_ib,
4202 .insert_nop = amdgpu_ring_insert_nop,
4203 .pad_ib = amdgpu_ring_generic_pad_ib,
4204};
4205
aa6faa44
XY		 4206static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4207 .type = AMDGPU_RING_TYPE_KIQ,
4208 .align_mask = 0xff,
4209 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4210 .support_64bit_ptrs = true,
0eeb68b3 4211 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 4212 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4213 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4214 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4215 .emit_frame_size =
4216 20 + /* gfx_v9_0_ring_emit_gds_switch */
4217 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4218 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4219 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4220 24 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 4221 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4222 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4223 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4224 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 4225 .test_ring = gfx_v9_0_ring_test_ring,
4226 .test_ib = gfx_v9_0_ring_test_ib,
4227 .insert_nop = amdgpu_ring_insert_nop,
4228 .pad_ib = amdgpu_ring_generic_pad_ib,
4229 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4230 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4231};
b1023571
KW		 4232
4233static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4234{
4235 int i;
4236
aa6faa44
XY		 4237 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4238
b1023571
KW		 4239 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4240 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4241
4242 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4243 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4244}
4245
97031e25
XY		 4246static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4247 .set = gfx_v9_0_kiq_set_interrupt_state,
4248 .process = gfx_v9_0_kiq_irq,
4249};
4250
b1023571
KW		 4251static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4252 .set = gfx_v9_0_set_eop_interrupt_state,
4253 .process = gfx_v9_0_eop_irq,
4254};
4255
4256static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4257 .set = gfx_v9_0_set_priv_reg_fault_state,
4258 .process = gfx_v9_0_priv_reg_irq,
4259};
4260
4261static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4262 .set = gfx_v9_0_set_priv_inst_fault_state,
4263 .process = gfx_v9_0_priv_inst_irq,
4264};
4265
4266static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4267{
4268 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4269 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4270
4271 adev->gfx.priv_reg_irq.num_types = 1;
4272 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4273
4274 adev->gfx.priv_inst_irq.num_types = 1;
4275 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 4276
4277 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4278 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 4279}
4280
4281static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4282{
4283 switch (adev->asic_type) {
4284 case CHIP_VEGA10:
a4dc61f5 4285 case CHIP_RAVEN:
b1023571
KW		 4286 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4287 break;
4288 default:
4289 break;
4290 }
4291}
4292
4293static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4294{
4295 /* init asci gds info */
5e78835a 4296 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 4297 adev->gds.gws.total_size = 64;
4298 adev->gds.oa.total_size = 16;
4299
4300 if (adev->gds.mem.total_size == 64 * 1024) {
4301 adev->gds.mem.gfx_partition_size = 4096;
4302 adev->gds.mem.cs_partition_size = 4096;
4303
4304 adev->gds.gws.gfx_partition_size = 4;
4305 adev->gds.gws.cs_partition_size = 4;
4306
4307 adev->gds.oa.gfx_partition_size = 4;
4308 adev->gds.oa.cs_partition_size = 1;
4309 } else {
4310 adev->gds.mem.gfx_partition_size = 1024;
4311 adev->gds.mem.cs_partition_size = 1024;
4312
4313 adev->gds.gws.gfx_partition_size = 16;
4314 adev->gds.gws.cs_partition_size = 16;
4315
4316 adev->gds.oa.gfx_partition_size = 4;
4317 adev->gds.oa.cs_partition_size = 4;
4318 }
4319}
4320
c94d38f0
NH		 4321static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4322 u32 bitmap)
4323{
4324 u32 data;
4325
4326 if (!bitmap)
4327 return;
4328
4329 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4330 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4331
4332 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4333}
4334
b1023571
KW		 4335static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4336{
4337 u32 data, mask;
4338
5e78835a
TSD		 4339 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4340 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 4341
4342 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4343 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4344
378506a7 4345 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
b1023571
KW		 4346
4347 return (~data) & mask;
4348}
4349
4350static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4351 struct amdgpu_cu_info *cu_info)
4352{
4353 int i, j, k, counter, active_cu_number = 0;
4354 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
c94d38f0 4355 unsigned disable_masks[4 * 2];
b1023571
KW		 4356
4357 if (!adev || !cu_info)
4358 return -EINVAL;
4359
c94d38f0
NH		 4360 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4361
b1023571
KW		 4362 mutex_lock(&adev->grbm_idx_mutex);
4363 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4364 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4365 mask = 1;
4366 ao_bitmap = 0;
4367 counter = 0;
4368 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
c94d38f0
NH		 4369 if (i < 4 && j < 2)
4370 gfx_v9_0_set_user_cu_inactive_bitmap(
4371 adev, disable_masks[i * 2 + j]);
b1023571
KW		 4372 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4373 cu_info->bitmap[i][j] = bitmap;
4374
fe723cd3 4375 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
b1023571 4376 if (bitmap & mask) {
fe723cd3 4377 if (counter < adev->gfx.config.max_cu_per_sh)
b1023571
KW		 4378 ao_bitmap |= mask;
4379 counter ++;
4380 }
4381 mask <<= 1;
4382 }
4383 active_cu_number += counter;
dbfe85ea
FC		 4384 if (i < 2 && j < 2)
4385 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4386 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
b1023571
KW		 4387 }
4388 }
4389 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4390 mutex_unlock(&adev->grbm_idx_mutex);
4391
4392 cu_info->number = active_cu_number;
4393 cu_info->ao_cu_mask = ao_cu_mask;
4394
4395 return 0;
4396}
4397
b1023571
KW		 4398const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4399{
4400 .type = AMD_IP_BLOCK_TYPE_GFX,
4401 .major = 9,
4402 .minor = 0,
4403 .rev = 0,
4404 .funcs = &gfx_v9_0_ip_funcs,
4405};
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