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drm/amdgpu/gfx9: fullfill kiq funcs (v2)
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
41#define GFX9_NUM_COMPUTE_RINGS 8
42#define GFX9_NUM_SE 4
43#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000
44
45MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
46MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
47MODULE_FIRMWARE("amdgpu/vega10_me.bin");
48MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
49MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
50MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
51
52static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
53{
54 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
55 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
56 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
57 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
58 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
59 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
60 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
61 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
62 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
63 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
64 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
65 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
66 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
67 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
68 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
69 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
70 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
72 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
73 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
74 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
76 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
77 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
78 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
80 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
81 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
82 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
84 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
85 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
86};
87
88static const u32 golden_settings_gc_9_0[] =
89{
90 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400,
91 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
92 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
93 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
94 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
95 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
96 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
97 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
98 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff
99};
100
101static const u32 golden_settings_gc_9_0_vg10[] =
102{
103 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
104 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
105 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
106 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
107 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
108 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
109 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800,
110 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007
111};
112
113#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
114
115static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
116static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
117static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
118static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
119static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
120 struct amdgpu_cu_info *cu_info);
121static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
122static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
123
124static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
125{
126 switch (adev->asic_type) {
127 case CHIP_VEGA10:
128 amdgpu_program_register_sequence(adev,
129 golden_settings_gc_9_0,
130 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
131 amdgpu_program_register_sequence(adev,
132 golden_settings_gc_9_0_vg10,
133 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
134 break;
135 default:
136 break;
137 }
138}
139
140static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
141{
142 adev->gfx.scratch.num_reg = 7;
143 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
144 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
145}
146
147static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
148 bool wc, uint32_t reg, uint32_t val)
149{
150 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
151 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
152 WRITE_DATA_DST_SEL(0) |
153 (wc ? WR_CONFIRM : 0));
154 amdgpu_ring_write(ring, reg);
155 amdgpu_ring_write(ring, 0);
156 amdgpu_ring_write(ring, val);
157}
158
159static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
160 int mem_space, int opt, uint32_t addr0,
161 uint32_t addr1, uint32_t ref, uint32_t mask,
162 uint32_t inv)
163{
164 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
165 amdgpu_ring_write(ring,
166 /* memory (1) or register (0) */
167 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
168 WAIT_REG_MEM_OPERATION(opt) | /* wait */
169 WAIT_REG_MEM_FUNCTION(3) | /* equal */
170 WAIT_REG_MEM_ENGINE(eng_sel)));
171
172 if (mem_space)
173 BUG_ON(addr0 & 0x3); /* Dword align */
174 amdgpu_ring_write(ring, addr0);
175 amdgpu_ring_write(ring, addr1);
176 amdgpu_ring_write(ring, ref);
177 amdgpu_ring_write(ring, mask);
178 amdgpu_ring_write(ring, inv); /* poll interval */
179}
180
181static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
182{
183 struct amdgpu_device *adev = ring->adev;
184 uint32_t scratch;
185 uint32_t tmp = 0;
186 unsigned i;
187 int r;
188
189 r = amdgpu_gfx_scratch_get(adev, &scratch);
190 if (r) {
191 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
192 return r;
193 }
194 WREG32(scratch, 0xCAFEDEAD);
195 r = amdgpu_ring_alloc(ring, 3);
196 if (r) {
197 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
198 ring->idx, r);
199 amdgpu_gfx_scratch_free(adev, scratch);
200 return r;
201 }
202 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
203 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
204 amdgpu_ring_write(ring, 0xDEADBEEF);
205 amdgpu_ring_commit(ring);
206
207 for (i = 0; i < adev->usec_timeout; i++) {
208 tmp = RREG32(scratch);
209 if (tmp == 0xDEADBEEF)
210 break;
211 DRM_UDELAY(1);
212 }
213 if (i < adev->usec_timeout) {
214 DRM_INFO("ring test on %d succeeded in %d usecs\n",
215 ring->idx, i);
216 } else {
217 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
218 ring->idx, scratch, tmp);
219 r = -EINVAL;
220 }
221 amdgpu_gfx_scratch_free(adev, scratch);
222 return r;
223}
224
225static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
226{
227 struct amdgpu_device *adev = ring->adev;
228 struct amdgpu_ib ib;
229 struct dma_fence *f = NULL;
230 uint32_t scratch;
231 uint32_t tmp = 0;
232 long r;
233
234 r = amdgpu_gfx_scratch_get(adev, &scratch);
235 if (r) {
236 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
237 return r;
238 }
239 WREG32(scratch, 0xCAFEDEAD);
240 memset(&ib, 0, sizeof(ib));
241 r = amdgpu_ib_get(adev, NULL, 256, &ib);
242 if (r) {
243 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
244 goto err1;
245 }
246 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
247 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
248 ib.ptr[2] = 0xDEADBEEF;
249 ib.length_dw = 3;
250
251 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
252 if (r)
253 goto err2;
254
255 r = dma_fence_wait_timeout(f, false, timeout);
256 if (r == 0) {
257 DRM_ERROR("amdgpu: IB test timed out.\n");
258 r = -ETIMEDOUT;
259 goto err2;
260 } else if (r < 0) {
261 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
262 goto err2;
263 }
264 tmp = RREG32(scratch);
265 if (tmp == 0xDEADBEEF) {
266 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
267 r = 0;
268 } else {
269 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
270 scratch, tmp);
271 r = -EINVAL;
272 }
273err2:
274 amdgpu_ib_free(adev, &ib, NULL);
275 dma_fence_put(f);
276err1:
277 amdgpu_gfx_scratch_free(adev, scratch);
278 return r;
279}
280
281static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
282{
283 const char *chip_name;
284 char fw_name[30];
285 int err;
286 struct amdgpu_firmware_info *info = NULL;
287 const struct common_firmware_header *header = NULL;
288 const struct gfx_firmware_header_v1_0 *cp_hdr;
289
290 DRM_DEBUG("\n");
291
292 switch (adev->asic_type) {
293 case CHIP_VEGA10:
294 chip_name = "vega10";
295 break;
296 default:
297 BUG();
298 }
299
300 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
301 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
302 if (err)
303 goto out;
304 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
305 if (err)
306 goto out;
307 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
308 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
309 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
310
311 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
312 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
313 if (err)
314 goto out;
315 err = amdgpu_ucode_validate(adev->gfx.me_fw);
316 if (err)
317 goto out;
318 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
319 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
320 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
321
322 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
323 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
324 if (err)
325 goto out;
326 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
327 if (err)
328 goto out;
329 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
330 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
331 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
332
333 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
334 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
335 if (err)
336 goto out;
337 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
338 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
339 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
340 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
341
342 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
343 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
344 if (err)
345 goto out;
346 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
347 if (err)
348 goto out;
349 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
350 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
351 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
352
353
354 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
355 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
356 if (!err) {
357 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
358 if (err)
359 goto out;
360 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
361 adev->gfx.mec2_fw->data;
362 adev->gfx.mec2_fw_version =
363 le32_to_cpu(cp_hdr->header.ucode_version);
364 adev->gfx.mec2_feature_version =
365 le32_to_cpu(cp_hdr->ucode_feature_version);
366 } else {
367 err = 0;
368 adev->gfx.mec2_fw = NULL;
369 }
370
371 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
372 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
373 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
374 info->fw = adev->gfx.pfp_fw;
375 header = (const struct common_firmware_header *)info->fw->data;
376 adev->firmware.fw_size +=
377 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
378
379 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
380 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
381 info->fw = adev->gfx.me_fw;
382 header = (const struct common_firmware_header *)info->fw->data;
383 adev->firmware.fw_size +=
384 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
385
386 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
387 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
388 info->fw = adev->gfx.ce_fw;
389 header = (const struct common_firmware_header *)info->fw->data;
390 adev->firmware.fw_size +=
391 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
392
393 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
394 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
395 info->fw = adev->gfx.rlc_fw;
396 header = (const struct common_firmware_header *)info->fw->data;
397 adev->firmware.fw_size +=
398 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
399
400 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
401 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
402 info->fw = adev->gfx.mec_fw;
403 header = (const struct common_firmware_header *)info->fw->data;
404 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
405 adev->firmware.fw_size +=
406 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
407
408 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
409 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
410 info->fw = adev->gfx.mec_fw;
411 adev->firmware.fw_size +=
412 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
413
414 if (adev->gfx.mec2_fw) {
415 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
416 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
417 info->fw = adev->gfx.mec2_fw;
418 header = (const struct common_firmware_header *)info->fw->data;
419 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
420 adev->firmware.fw_size +=
421 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
422 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
423 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
424 info->fw = adev->gfx.mec2_fw;
425 adev->firmware.fw_size +=
426 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
427 }
428
429 }
430
431out:
432 if (err) {
433 dev_err(adev->dev,
434 "gfx9: Failed to load firmware \"%s\"\n",
435 fw_name);
436 release_firmware(adev->gfx.pfp_fw);
437 adev->gfx.pfp_fw = NULL;
438 release_firmware(adev->gfx.me_fw);
439 adev->gfx.me_fw = NULL;
440 release_firmware(adev->gfx.ce_fw);
441 adev->gfx.ce_fw = NULL;
442 release_firmware(adev->gfx.rlc_fw);
443 adev->gfx.rlc_fw = NULL;
444 release_firmware(adev->gfx.mec_fw);
445 adev->gfx.mec_fw = NULL;
446 release_firmware(adev->gfx.mec2_fw);
447 adev->gfx.mec2_fw = NULL;
448 }
449 return err;
450}
451
452static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
453{
454 int r;
455
456 if (adev->gfx.mec.hpd_eop_obj) {
457 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
458 if (unlikely(r != 0))
459 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
460 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
461 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
462
463 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
464 adev->gfx.mec.hpd_eop_obj = NULL;
465 }
466 if (adev->gfx.mec.mec_fw_obj) {
467 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
468 if (unlikely(r != 0))
469 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
470 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
471 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
472
473 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
474 adev->gfx.mec.mec_fw_obj = NULL;
475 }
476}
477
478#define MEC_HPD_SIZE 2048
479
480static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
481{
482 int r;
483 u32 *hpd;
484 const __le32 *fw_data;
485 unsigned fw_size;
486 u32 *fw;
487
488 const struct gfx_firmware_header_v1_0 *mec_hdr;
489
490 /*
491 * we assign only 1 pipe because all other pipes will
492 * be handled by KFD
493 */
494 adev->gfx.mec.num_mec = 1;
495 adev->gfx.mec.num_pipe = 1;
496 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
497
498 if (adev->gfx.mec.hpd_eop_obj == NULL) {
499 r = amdgpu_bo_create(adev,
500 adev->gfx.mec.num_queue * MEC_HPD_SIZE,
501 PAGE_SIZE, true,
502 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
503 &adev->gfx.mec.hpd_eop_obj);
504 if (r) {
505 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
506 return r;
507 }
508 }
509
510 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
511 if (unlikely(r != 0)) {
512 gfx_v9_0_mec_fini(adev);
513 return r;
514 }
515 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
516 &adev->gfx.mec.hpd_eop_gpu_addr);
517 if (r) {
518 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
519 gfx_v9_0_mec_fini(adev);
520 return r;
521 }
522 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
523 if (r) {
524 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
525 gfx_v9_0_mec_fini(adev);
526 return r;
527 }
528
529 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
530
531 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
532 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
533
534 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
535
536 fw_data = (const __le32 *)
537 (adev->gfx.mec_fw->data +
538 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
539 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
540
541 if (adev->gfx.mec.mec_fw_obj == NULL) {
542 r = amdgpu_bo_create(adev,
543 mec_hdr->header.ucode_size_bytes,
544 PAGE_SIZE, true,
545 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
546 &adev->gfx.mec.mec_fw_obj);
547 if (r) {
548 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
549 return r;
550 }
551 }
552
553 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
554 if (unlikely(r != 0)) {
555 gfx_v9_0_mec_fini(adev);
556 return r;
557 }
558 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
559 &adev->gfx.mec.mec_fw_gpu_addr);
560 if (r) {
561 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
562 gfx_v9_0_mec_fini(adev);
563 return r;
564 }
565 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
566 if (r) {
567 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
568 gfx_v9_0_mec_fini(adev);
569 return r;
570 }
571 memcpy(fw, fw_data, fw_size);
572
573 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
574 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
575
576
577 return 0;
578}
579
ac104e99
XY		 580static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev)
581{
582 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
583
584 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
585}
586
587static int gfx_v9_0_kiq_init(struct amdgpu_device *adev)
588{
589 int r;
590 u32 *hpd;
591 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
592
593 r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE,
594 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
595 &kiq->eop_gpu_addr, (void **)&hpd);
596 if (r) {
597 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
598 return r;
599 }
600
601 memset(hpd, 0, MEC_HPD_SIZE);
602
603 amdgpu_bo_kunmap(kiq->eop_obj);
604
605 return 0;
606}
607
608static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
609 struct amdgpu_ring *ring,
610 struct amdgpu_irq_src *irq)
611{
612 int r = 0;
613
614 r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
615 if (r)
616 return r;
617
618 ring->adev = NULL;
619 ring->ring_obj = NULL;
620 ring->use_doorbell = true;
621 ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
622 if (adev->gfx.mec2_fw) {
623 ring->me = 2;
624 ring->pipe = 0;
625 } else {
626 ring->me = 1;
627 ring->pipe = 1;
628 }
629
630 irq->data = ring;
631 ring->queue = 0;
632 sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
633 r = amdgpu_ring_init(adev, ring, 1024,
634 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
635 if (r)
636 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
637
638 return r;
639}
640static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
641 struct amdgpu_irq_src *irq)
642{
643 amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
644 amdgpu_ring_fini(ring);
645 irq->data = NULL;
646}
647
b1023571
KW		 648static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
649{
650 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
651 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
652 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
653 (address << SQ_IND_INDEX__INDEX__SHIFT) |
654 (SQ_IND_INDEX__FORCE_READ_MASK));
655 return RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA));
656}
657
658static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
659 uint32_t wave, uint32_t thread,
660 uint32_t regno, uint32_t num, uint32_t *out)
661{
662 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
663 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
664 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
665 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
666 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
667 (SQ_IND_INDEX__FORCE_READ_MASK) |
668 (SQ_IND_INDEX__AUTO_INCR_MASK));
669 while (num--)
670 *(out++) = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA));
671}
672
673static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
674{
675 /* type 1 wave data */
676 dst[(*no_fields)++] = 1;
677 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
678 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
679 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
680 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
681 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
682 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
683 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
684 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
685 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
686 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
687 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
688 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
689 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
690 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
691}
692
693static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
694 uint32_t wave, uint32_t start,
695 uint32_t size, uint32_t *dst)
696{
697 wave_read_regs(
698 adev, simd, wave, 0,
699 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
700}
701
702
703static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
704 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
705 .select_se_sh = &gfx_v9_0_select_se_sh,
706 .read_wave_data = &gfx_v9_0_read_wave_data,
707 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
708};
709
710static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
711{
712 u32 gb_addr_config;
713
714 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
715
716 switch (adev->asic_type) {
717 case CHIP_VEGA10:
718 adev->gfx.config.max_shader_engines = 4;
719 adev->gfx.config.max_tile_pipes = 8; //??
720 adev->gfx.config.max_cu_per_sh = 16;
721 adev->gfx.config.max_sh_per_se = 1;
722 adev->gfx.config.max_backends_per_se = 4;
723 adev->gfx.config.max_texture_channel_caches = 16;
724 adev->gfx.config.max_gprs = 256;
725 adev->gfx.config.max_gs_threads = 32;
726 adev->gfx.config.max_hw_contexts = 8;
727
728 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
729 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
730 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
731 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
732 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
733 break;
734 default:
735 BUG();
736 break;
737 }
738
739 adev->gfx.config.gb_addr_config = gb_addr_config;
740
741 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
742 REG_GET_FIELD(
743 adev->gfx.config.gb_addr_config,
744 GB_ADDR_CONFIG,
745 NUM_PIPES);
746 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
747 REG_GET_FIELD(
748 adev->gfx.config.gb_addr_config,
749 GB_ADDR_CONFIG,
750 NUM_BANKS);
751 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
752 REG_GET_FIELD(
753 adev->gfx.config.gb_addr_config,
754 GB_ADDR_CONFIG,
755 MAX_COMPRESSED_FRAGS);
756 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
757 REG_GET_FIELD(
758 adev->gfx.config.gb_addr_config,
759 GB_ADDR_CONFIG,
760 NUM_RB_PER_SE);
761 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
762 REG_GET_FIELD(
763 adev->gfx.config.gb_addr_config,
764 GB_ADDR_CONFIG,
765 NUM_SHADER_ENGINES);
766 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
767 REG_GET_FIELD(
768 adev->gfx.config.gb_addr_config,
769 GB_ADDR_CONFIG,
770 PIPE_INTERLEAVE_SIZE));
771}
772
773static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
774 struct amdgpu_ngg_buf *ngg_buf,
775 int size_se,
776 int default_size_se)
777{
778 int r;
779
780 if (size_se < 0) {
781 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
782 return -EINVAL;
783 }
784 size_se = size_se ? size_se : default_size_se;
785
786 ngg_buf->size = size_se * GFX9_NUM_SE;
787 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
788 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
789 &ngg_buf->bo,
790 &ngg_buf->gpu_addr,
791 NULL);
792 if (r) {
793 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
794 return r;
795 }
796 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
797
798 return r;
799}
800
801static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
802{
803 int i;
804
805 for (i = 0; i < NGG_BUF_MAX; i++)
806 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
807 &adev->gfx.ngg.buf[i].gpu_addr,
808 NULL);
809
810 memset(&adev->gfx.ngg.buf[0], 0,
811 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
812
813 adev->gfx.ngg.init = false;
814
815 return 0;
816}
817
818static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
819{
820 int r;
821
822 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
823 return 0;
824
825 /* GDS reserve memory: 64 bytes alignment */
826 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
827 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
828 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
829 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
830 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
831
832 /* Primitive Buffer */
833 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PRIM],
834 amdgpu_prim_buf_per_se,
835 64 * 1024);
836 if (r) {
837 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
838 goto err;
839 }
840
841 /* Position Buffer */
842 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[POS],
843 amdgpu_pos_buf_per_se,
844 256 * 1024);
845 if (r) {
846 dev_err(adev->dev, "Failed to create Position Buffer\n");
847 goto err;
848 }
849
850 /* Control Sideband */
851 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[CNTL],
852 amdgpu_cntl_sb_buf_per_se,
853 256);
854 if (r) {
855 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
856 goto err;
857 }
858
859 /* Parameter Cache, not created by default */
860 if (amdgpu_param_buf_per_se <= 0)
861 goto out;
862
863 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PARAM],
864 amdgpu_param_buf_per_se,
865 512 * 1024);
866 if (r) {
867 dev_err(adev->dev, "Failed to create Parameter Cache\n");
868 goto err;
869 }
870
871out:
872 adev->gfx.ngg.init = true;
873 return 0;
874err:
875 gfx_v9_0_ngg_fini(adev);
876 return r;
877}
878
879static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
880{
881 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
882 int r;
883 u32 data;
884 u32 size;
885 u32 base;
886
887 if (!amdgpu_ngg)
888 return 0;
889
890 /* Program buffer size */
891 data = 0;
892 size = adev->gfx.ngg.buf[PRIM].size / 256;
893 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
894
895 size = adev->gfx.ngg.buf[POS].size / 256;
896 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
897
898 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_1), data);
899
900 data = 0;
901 size = adev->gfx.ngg.buf[CNTL].size / 256;
902 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
903
904 size = adev->gfx.ngg.buf[PARAM].size / 1024;
905 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
906
907 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_2), data);
908
909 /* Program buffer base address */
910 base = lower_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
911 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
912 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE), data);
913
914 base = upper_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
915 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
916 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE_HI), data);
917
918 base = lower_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
919 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
920 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE), data);
921
922 base = upper_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
923 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
924 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE_HI), data);
925
926 base = lower_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
927 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
928 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE), data);
929
930 base = upper_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
931 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
932 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI), data);
933
934 /* Clear GDS reserved memory */
935 r = amdgpu_ring_alloc(ring, 17);
936 if (r) {
937 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
938 ring->idx, r);
939 return r;
940 }
941
942 gfx_v9_0_write_data_to_reg(ring, 0, false,
943 amdgpu_gds_reg_offset[0].mem_size,
944 (adev->gds.mem.total_size +
945 adev->gfx.ngg.gds_reserve_size) >>
946 AMDGPU_GDS_SHIFT);
947
948 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
949 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
950 PACKET3_DMA_DATA_SRC_SEL(2)));
951 amdgpu_ring_write(ring, 0);
952 amdgpu_ring_write(ring, 0);
953 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
954 amdgpu_ring_write(ring, 0);
955 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
956
957
958 gfx_v9_0_write_data_to_reg(ring, 0, false,
959 amdgpu_gds_reg_offset[0].mem_size, 0);
960
961 amdgpu_ring_commit(ring);
962
963 return 0;
964}
965
966static int gfx_v9_0_sw_init(void *handle)
967{
968 int i, r;
969 struct amdgpu_ring *ring;
ac104e99 970 struct amdgpu_kiq *kiq;
b1023571
KW		 971 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
972
973 /* EOP Event */
974 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
975 if (r)
976 return r;
977
978 /* Privileged reg */
979 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
980 &adev->gfx.priv_reg_irq);
981 if (r)
982 return r;
983
984 /* Privileged inst */
985 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
986 &adev->gfx.priv_inst_irq);
987 if (r)
988 return r;
989
990 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
991
992 gfx_v9_0_scratch_init(adev);
993
994 r = gfx_v9_0_init_microcode(adev);
995 if (r) {
996 DRM_ERROR("Failed to load gfx firmware!\n");
997 return r;
998 }
999
1000 r = gfx_v9_0_mec_init(adev);
1001 if (r) {
1002 DRM_ERROR("Failed to init MEC BOs!\n");
1003 return r;
1004 }
1005
1006 /* set up the gfx ring */
1007 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1008 ring = &adev->gfx.gfx_ring[i];
1009 ring->ring_obj = NULL;
1010 sprintf(ring->name, "gfx");
1011 ring->use_doorbell = true;
1012 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1013 r = amdgpu_ring_init(adev, ring, 1024,
1014 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1015 if (r)
1016 return r;
1017 }
1018
1019 /* set up the compute queues */
1020 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1021 unsigned irq_type;
1022
1023 /* max 32 queues per MEC */
1024 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1025 DRM_ERROR("Too many (%d) compute rings!\n", i);
1026 break;
1027 }
1028 ring = &adev->gfx.compute_ring[i];
1029 ring->ring_obj = NULL;
1030 ring->use_doorbell = true;
1031 ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1;
1032 ring->me = 1; /* first MEC */
1033 ring->pipe = i / 8;
1034 ring->queue = i % 8;
1035 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
1036 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1037 /* type-2 packets are deprecated on MEC, use type-3 instead */
1038 r = amdgpu_ring_init(adev, ring, 1024,
1039 &adev->gfx.eop_irq, irq_type);
1040 if (r)
1041 return r;
1042 }
1043
ac104e99
XY		 1044 if (amdgpu_sriov_vf(adev)) {
1045 r = gfx_v9_0_kiq_init(adev);
1046 if (r) {
1047 DRM_ERROR("Failed to init KIQ BOs!\n");
1048 return r;
1049 }
1050
1051 kiq = &adev->gfx.kiq;
1052 r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1053 if (r)
1054 return r;
1055 }
1056
b1023571
KW		 1057 /* reserve GDS, GWS and OA resource for gfx */
1058 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1059 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1060 &adev->gds.gds_gfx_bo, NULL, NULL);
1061 if (r)
1062 return r;
1063
1064 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1065 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1066 &adev->gds.gws_gfx_bo, NULL, NULL);
1067 if (r)
1068 return r;
1069
1070 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1071 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1072 &adev->gds.oa_gfx_bo, NULL, NULL);
1073 if (r)
1074 return r;
1075
1076 adev->gfx.ce_ram_size = 0x8000;
1077
1078 gfx_v9_0_gpu_early_init(adev);
1079
1080 r = gfx_v9_0_ngg_init(adev);
1081 if (r)
1082 return r;
1083
1084 return 0;
1085}
1086
1087
1088static int gfx_v9_0_sw_fini(void *handle)
1089{
1090 int i;
1091 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1092
1093 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1094 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1095 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1096
1097 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1098 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1099 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1100 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1101
ac104e99
XY		 1102 if (amdgpu_sriov_vf(adev)) {
1103 gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1104 gfx_v9_0_kiq_fini(adev);
1105 }
1106
b1023571
KW		 1107 gfx_v9_0_mec_fini(adev);
1108 gfx_v9_0_ngg_fini(adev);
1109
1110 return 0;
1111}
1112
1113
1114static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1115{
1116 /* TODO */
1117}
1118
1119static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1120{
1121 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1122
1123 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1124 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1125 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1126 } else if (se_num == 0xffffffff) {
1127 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1128 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1129 } else if (sh_num == 0xffffffff) {
1130 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1131 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1132 } else {
1133 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1134 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1135 }
1136 WREG32( SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
1137}
1138
1139static u32 gfx_v9_0_create_bitmask(u32 bit_width)
1140{
1141 return (u32)((1ULL << bit_width) - 1);
1142}
1143
1144static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1145{
1146 u32 data, mask;
1147
1148 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE));
1149 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE));
1150
1151 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1152 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1153
1154 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1155 adev->gfx.config.max_sh_per_se);
1156
1157 return (~data) & mask;
1158}
1159
1160static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1161{
1162 int i, j;
1163 u32 data, tmp, num_rbs = 0;
1164 u32 active_rbs = 0;
1165 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1166 adev->gfx.config.max_sh_per_se;
1167
1168 mutex_lock(&adev->grbm_idx_mutex);
1169 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1170 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1171 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1172 data = gfx_v9_0_get_rb_active_bitmap(adev);
1173 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1174 rb_bitmap_width_per_sh);
1175 }
1176 }
1177 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1178 mutex_unlock(&adev->grbm_idx_mutex);
1179
1180 adev->gfx.config.backend_enable_mask = active_rbs;
1181 tmp = active_rbs;
1182 while (tmp >>= 1)
1183 num_rbs++;
1184 adev->gfx.config.num_rbs = num_rbs;
1185}
1186
1187#define DEFAULT_SH_MEM_BASES (0x6000)
1188#define FIRST_COMPUTE_VMID (8)
1189#define LAST_COMPUTE_VMID (16)
1190static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1191{
1192 int i;
1193 uint32_t sh_mem_config;
1194 uint32_t sh_mem_bases;
1195
1196 /*
1197 * Configure apertures:
1198 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1199 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1200 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1201 */
1202 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1203
1204 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1205 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1206 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1207
1208 mutex_lock(&adev->srbm_mutex);
1209 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1210 soc15_grbm_select(adev, 0, 0, 0, i);
1211 /* CP and shaders */
1212 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
1213 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
1214 }
1215 soc15_grbm_select(adev, 0, 0, 0, 0);
1216 mutex_unlock(&adev->srbm_mutex);
1217}
1218
1219static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1220{
1221 u32 tmp;
1222 int i;
1223
1224 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL));
1225 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
1226 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp);
1227
1228 gfx_v9_0_tiling_mode_table_init(adev);
1229
1230 gfx_v9_0_setup_rb(adev);
1231 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1232
1233 /* XXX SH_MEM regs */
1234 /* where to put LDS, scratch, GPUVM in FSA64 space */
1235 mutex_lock(&adev->srbm_mutex);
1236 for (i = 0; i < 16; i++) {
1237 soc15_grbm_select(adev, 0, 0, 0, i);
1238 /* CP and shaders */
1239 tmp = 0;
1240 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1241 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1242 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), tmp);
1243 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), 0);
1244 }
1245 soc15_grbm_select(adev, 0, 0, 0, 0);
1246
1247 mutex_unlock(&adev->srbm_mutex);
1248
1249 gfx_v9_0_init_compute_vmid(adev);
1250
1251 mutex_lock(&adev->grbm_idx_mutex);
1252 /*
1253 * making sure that the following register writes will be broadcasted
1254 * to all the shaders
1255 */
1256 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1257
1258 WREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE),
1259 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1260 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1261 (adev->gfx.config.sc_prim_fifo_size_backend <<
1262 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1263 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1264 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1265 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1266 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1267 mutex_unlock(&adev->grbm_idx_mutex);
1268
1269}
1270
1271static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1272{
1273 u32 i, j, k;
1274 u32 mask;
1275
1276 mutex_lock(&adev->grbm_idx_mutex);
1277 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1278 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1279 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1280 for (k = 0; k < adev->usec_timeout; k++) {
1281 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY)) == 0)
1282 break;
1283 udelay(1);
1284 }
1285 }
1286 }
1287 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1288 mutex_unlock(&adev->grbm_idx_mutex);
1289
1290 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1291 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1292 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1293 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1294 for (k = 0; k < adev->usec_timeout; k++) {
1295 if ((RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY)) & mask) == 0)
1296 break;
1297 udelay(1);
1298 }
1299}
1300
1301static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1302 bool enable)
1303{
1304 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
1305
1306 if (enable)
1307 return;
1308
1309 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1310 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1311 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1312 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1313
1314 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), tmp);
1315}
1316
1317void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1318{
1319 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
1320
1321 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1322 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp);
1323
1324 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1325
1326 gfx_v9_0_wait_for_rlc_serdes(adev);
1327}
1328
1329static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1330{
1331 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
1332
1333 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1334 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
1335 udelay(50);
1336 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1337 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
1338 udelay(50);
1339}
1340
1341static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1342{
1343#ifdef AMDGPU_RLC_DEBUG_RETRY
1344 u32 rlc_ucode_ver;
1345#endif
1346 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
1347
1348 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
1349 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp);
1350
1351 /* carrizo do enable cp interrupt after cp inited */
1352 if (!(adev->flags & AMD_IS_APU))
1353 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1354
1355 udelay(50);
1356
1357#ifdef AMDGPU_RLC_DEBUG_RETRY
1358 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1359 rlc_ucode_ver = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6));
1360 if(rlc_ucode_ver == 0x108) {
1361 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1362 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1363 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1364 * default is 0x9C4 to create a 100us interval */
1365 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3), 0x9C4);
1366 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1367 * to disable the page fault retry interrupts, default is
1368 * 0x100 (256) */
1369 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12), 0x100);
1370 }
1371#endif
1372}
1373
1374static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
1375{
1376 const struct rlc_firmware_header_v2_0 *hdr;
1377 const __le32 *fw_data;
1378 unsigned i, fw_size;
1379
1380 if (!adev->gfx.rlc_fw)
1381 return -EINVAL;
1382
1383 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1384 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1385
1386 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1387 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1388 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1389
1390 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR),
1391 RLCG_UCODE_LOADING_START_ADDRESS);
1392 for (i = 0; i < fw_size; i++)
1393 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA), le32_to_cpup(fw_data++));
1394 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR), adev->gfx.rlc_fw_version);
1395
1396 return 0;
1397}
1398
1399static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
1400{
1401 int r;
1402
1403 gfx_v9_0_rlc_stop(adev);
1404
1405 /* disable CG */
1406 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), 0);
1407
1408 /* disable PG */
1409 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), 0);
1410
1411 gfx_v9_0_rlc_reset(adev);
1412
1413 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1414 /* legacy rlc firmware loading */
1415 r = gfx_v9_0_rlc_load_microcode(adev);
1416 if (r)
1417 return r;
1418 }
1419
1420 gfx_v9_0_rlc_start(adev);
1421
1422 return 0;
1423}
1424
1425static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1426{
1427 int i;
1428 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL));
1429
1430 if (enable) {
1431 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
1432 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
1433 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
1434 } else {
1435 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
1436 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
1437 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
1438 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1439 adev->gfx.gfx_ring[i].ready = false;
1440 }
1441 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL), tmp);
1442 udelay(50);
1443}
1444
1445static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1446{
1447 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1448 const struct gfx_firmware_header_v1_0 *ce_hdr;
1449 const struct gfx_firmware_header_v1_0 *me_hdr;
1450 const __le32 *fw_data;
1451 unsigned i, fw_size;
1452
1453 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1454 return -EINVAL;
1455
1456 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
1457 adev->gfx.pfp_fw->data;
1458 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
1459 adev->gfx.ce_fw->data;
1460 me_hdr = (const struct gfx_firmware_header_v1_0 *)
1461 adev->gfx.me_fw->data;
1462
1463 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1464 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1465 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1466
1467 gfx_v9_0_cp_gfx_enable(adev, false);
1468
1469 /* PFP */
1470 fw_data = (const __le32 *)
1471 (adev->gfx.pfp_fw->data +
1472 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1473 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1474 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), 0);
1475 for (i = 0; i < fw_size; i++)
1476 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA), le32_to_cpup(fw_data++));
1477 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), adev->gfx.pfp_fw_version);
1478
1479 /* CE */
1480 fw_data = (const __le32 *)
1481 (adev->gfx.ce_fw->data +
1482 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1483 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1484 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), 0);
1485 for (i = 0; i < fw_size; i++)
1486 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA), le32_to_cpup(fw_data++));
1487 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), adev->gfx.ce_fw_version);
1488
1489 /* ME */
1490 fw_data = (const __le32 *)
1491 (adev->gfx.me_fw->data +
1492 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1493 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1494 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), 0);
1495 for (i = 0; i < fw_size; i++)
1496 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_DATA), le32_to_cpup(fw_data++));
1497 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), adev->gfx.me_fw_version);
1498
1499 return 0;
1500}
1501
1502static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1503{
1504 u32 count = 0;
1505 const struct cs_section_def *sect = NULL;
1506 const struct cs_extent_def *ext = NULL;
1507
1508 /* begin clear state */
1509 count += 2;
1510 /* context control state */
1511 count += 3;
1512
1513 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1514 for (ext = sect->section; ext->extent != NULL; ++ext) {
1515 if (sect->id == SECT_CONTEXT)
1516 count += 2 + ext->reg_count;
1517 else
1518 return 0;
1519 }
1520 }
1521 /* pa_sc_raster_config/pa_sc_raster_config1 */
1522 count += 4;
1523 /* end clear state */
1524 count += 2;
1525 /* clear state */
1526 count += 2;
1527
1528 return count;
1529}
1530
1531static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
1532{
1533 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1534 const struct cs_section_def *sect = NULL;
1535 const struct cs_extent_def *ext = NULL;
1536 int r, i;
1537
1538 /* init the CP */
1539 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT), adev->gfx.config.max_hw_contexts - 1);
1540 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID), 1);
1541
1542 gfx_v9_0_cp_gfx_enable(adev, true);
1543
1544 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
1545 if (r) {
1546 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1547 return r;
1548 }
1549
1550 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1551 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1552
1553 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1554 amdgpu_ring_write(ring, 0x80000000);
1555 amdgpu_ring_write(ring, 0x80000000);
1556
1557 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1558 for (ext = sect->section; ext->extent != NULL; ++ext) {
1559 if (sect->id == SECT_CONTEXT) {
1560 amdgpu_ring_write(ring,
1561 PACKET3(PACKET3_SET_CONTEXT_REG,
1562 ext->reg_count));
1563 amdgpu_ring_write(ring,
1564 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1565 for (i = 0; i < ext->reg_count; i++)
1566 amdgpu_ring_write(ring, ext->extent[i]);
1567 }
1568 }
1569 }
1570
1571 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1572 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1573
1574 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1575 amdgpu_ring_write(ring, 0);
1576
1577 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1578 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1579 amdgpu_ring_write(ring, 0x8000);
1580 amdgpu_ring_write(ring, 0x8000);
1581
1582 amdgpu_ring_commit(ring);
1583
1584 return 0;
1585}
1586
1587static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
1588{
1589 struct amdgpu_ring *ring;
1590 u32 tmp;
1591 u32 rb_bufsz;
3fc08b61 1592 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 1593
1594 /* Set the write pointer delay */
1595 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0);
1596
1597 /* set the RB to use vmid 0 */
1598 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID), 0);
1599
1600 /* Set ring buffer size */
1601 ring = &adev->gfx.gfx_ring[0];
1602 rb_bufsz = order_base_2(ring->ring_size / 8);
1603 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
1604 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
1605#ifdef __BIG_ENDIAN
1606 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
1607#endif
1608 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
1609
1610 /* Initialize the ring buffer's write pointers */
1611 ring->wptr = 0;
1612 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr));
1613 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr));
1614
1615 /* set the wb address wether it's enabled or not */
1616 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1617 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR), lower_32_bits(rptr_addr));
1618 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI), upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
1619
3fc08b61
ML		 1620 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1621 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr));
1622 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr));
1623
b1023571
KW		 1624 mdelay(1);
1625 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
1626
1627 rb_addr = ring->gpu_addr >> 8;
1628 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE), rb_addr);
1629 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI), upper_32_bits(rb_addr));
1630
1631 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL));
1632 if (ring->use_doorbell) {
1633 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1634 DOORBELL_OFFSET, ring->doorbell_index);
1635 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1636 DOORBELL_EN, 1);
1637 } else {
1638 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
1639 }
1640 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL), tmp);
1641
1642 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
1643 DOORBELL_RANGE_LOWER, ring->doorbell_index);
1644 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER), tmp);
1645
1646 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER),
1647 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
1648
1649
1650 /* start the ring */
1651 gfx_v9_0_cp_gfx_start(adev);
1652 ring->ready = true;
1653
1654 return 0;
1655}
1656
1657static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
1658{
1659 int i;
1660
1661 if (enable) {
1662 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL), 0);
1663 } else {
1664 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL),
1665 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1666 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1667 adev->gfx.compute_ring[i].ready = false;
ac104e99 1668 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 1669 }
1670 udelay(50);
1671}
1672
1673static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
1674{
1675 gfx_v9_0_cp_compute_enable(adev, true);
1676
1677 return 0;
1678}
1679
1680static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
1681{
1682 const struct gfx_firmware_header_v1_0 *mec_hdr;
1683 const __le32 *fw_data;
1684 unsigned i;
1685 u32 tmp;
1686
1687 if (!adev->gfx.mec_fw)
1688 return -EINVAL;
1689
1690 gfx_v9_0_cp_compute_enable(adev, false);
1691
1692 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1693 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1694
1695 fw_data = (const __le32 *)
1696 (adev->gfx.mec_fw->data +
1697 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1698 tmp = 0;
1699 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1700 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1701 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_CNTL), tmp);
1702
1703 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_LO),
1704 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1705 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_HI),
1706 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1707
1708 /* MEC1 */
1709 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR),
1710 mec_hdr->jt_offset);
1711 for (i = 0; i < mec_hdr->jt_size; i++)
1712 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA),
1713 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1714
1715 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR),
1716 adev->gfx.mec_fw_version);
1717 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1718
1719 return 0;
1720}
1721
1722static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
1723{
1724 int i, r;
1725
1726 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1727 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1728
1729 if (ring->mqd_obj) {
1730 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1731 if (unlikely(r != 0))
1732 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
1733
1734 amdgpu_bo_unpin(ring->mqd_obj);
1735 amdgpu_bo_unreserve(ring->mqd_obj);
1736
1737 amdgpu_bo_unref(&ring->mqd_obj);
1738 ring->mqd_obj = NULL;
1739 }
1740 }
1741}
1742
1743static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
1744
1745static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
1746{
1747 int i, r;
1748 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1749 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1750 if (gfx_v9_0_init_queue(ring))
1751 dev_warn(adev->dev, "compute queue %d init failed!\n", i);
1752 }
1753
1754 r = gfx_v9_0_cp_compute_start(adev);
1755 if (r)
1756 return r;
1757
1758 return 0;
1759}
1760
1761static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
1762{
1763 int r,i;
1764 struct amdgpu_ring *ring;
1765
1766 if (!(adev->flags & AMD_IS_APU))
1767 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1768
1769 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1770 /* legacy firmware loading */
1771 r = gfx_v9_0_cp_gfx_load_microcode(adev);
1772 if (r)
1773 return r;
1774
1775 r = gfx_v9_0_cp_compute_load_microcode(adev);
1776 if (r)
1777 return r;
1778 }
1779
1780 r = gfx_v9_0_cp_gfx_resume(adev);
1781 if (r)
1782 return r;
1783
1784 r = gfx_v9_0_cp_compute_resume(adev);
1785 if (r)
1786 return r;
1787
1788 ring = &adev->gfx.gfx_ring[0];
1789 r = amdgpu_ring_test_ring(ring);
1790 if (r) {
1791 ring->ready = false;
1792 return r;
1793 }
1794 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1795 ring = &adev->gfx.compute_ring[i];
1796
1797 ring->ready = true;
1798 r = amdgpu_ring_test_ring(ring);
1799 if (r)
1800 ring->ready = false;
1801 }
1802
1803 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1804
1805 return 0;
1806}
1807
1808static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
1809{
1810 gfx_v9_0_cp_gfx_enable(adev, enable);
1811 gfx_v9_0_cp_compute_enable(adev, enable);
1812}
1813
1814static int gfx_v9_0_hw_init(void *handle)
1815{
1816 int r;
1817 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1818
1819 gfx_v9_0_init_golden_registers(adev);
1820
1821 gfx_v9_0_gpu_init(adev);
1822
1823 r = gfx_v9_0_rlc_resume(adev);
1824 if (r)
1825 return r;
1826
1827 r = gfx_v9_0_cp_resume(adev);
1828 if (r)
1829 return r;
1830
1831 r = gfx_v9_0_ngg_en(adev);
1832 if (r)
1833 return r;
1834
1835 return r;
1836}
1837
1838static int gfx_v9_0_hw_fini(void *handle)
1839{
1840 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1841
1842 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
1843 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
1844 gfx_v9_0_cp_enable(adev, false);
1845 gfx_v9_0_rlc_stop(adev);
1846 gfx_v9_0_cp_compute_fini(adev);
1847
1848 return 0;
1849}
1850
1851static int gfx_v9_0_suspend(void *handle)
1852{
1853 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1854
1855 return gfx_v9_0_hw_fini(adev);
1856}
1857
1858static int gfx_v9_0_resume(void *handle)
1859{
1860 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1861
1862 return gfx_v9_0_hw_init(adev);
1863}
1864
1865static bool gfx_v9_0_is_idle(void *handle)
1866{
1867 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1868
1869 if (REG_GET_FIELD(RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)),
1870 GRBM_STATUS, GUI_ACTIVE))
1871 return false;
1872 else
1873 return true;
1874}
1875
1876static int gfx_v9_0_wait_for_idle(void *handle)
1877{
1878 unsigned i;
1879 u32 tmp;
1880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1881
1882 for (i = 0; i < adev->usec_timeout; i++) {
1883 /* read MC_STATUS */
1884 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)) &
1885 GRBM_STATUS__GUI_ACTIVE_MASK;
1886
1887 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
1888 return 0;
1889 udelay(1);
1890 }
1891 return -ETIMEDOUT;
1892}
1893
1894static void gfx_v9_0_print_status(void *handle)
1895{
1896 int i;
1897 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1898
1899 dev_info(adev->dev, "GFX 9.x registers\n");
1900 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
1901 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)));
1902 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
1903 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)));
1904 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1905 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)));
1906 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1907 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)));
1908 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
1909 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)));
1910 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
1911 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)));
1912 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STAT)));
1913 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
1914 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)));
1915 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
1916 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)));
1917 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
1918 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)));
1919 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
1920 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)));
1921 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
1922 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)));
1923 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)));
1924 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_BUSY_STAT)));
1925 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
1926 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)));
1927 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)));
1928
1929 for (i = 0; i < 32; i++) {
1930 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
1931 i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_TILE_MODE0 ) + i*4));
1932 }
1933 for (i = 0; i < 16; i++) {
1934 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
1935 i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_MACROTILE_MODE0) + i*4));
1936 }
1937 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1938 dev_info(adev->dev, " se: %d\n", i);
1939 gfx_v9_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1940 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
1941 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG)));
1942 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
1943 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG_1)));
1944 }
1945 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1946
1947 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
1948 RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)));
1949
1950 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
1951 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEQ_THRESHOLDS)));
1952 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
1953 RREG32(SOC15_REG_OFFSET(GC, 0, mmSX_DEBUG_1)));
1954 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
1955 RREG32(SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX)));
1956 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
1957 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL)));
1958 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
1959 RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG)));
1960 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
1961 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG)));
1962 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
1963 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)));
1964 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
1965 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG3)));
1966 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
1967 RREG32(SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL)));
1968 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
1969 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1)));
1970 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
1971 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE)));
1972 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
1973 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_NUM_INSTANCES)));
1974 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
1975 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL)));
1976 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
1977 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FORCE_EOV_MAX_CNTS)));
1978 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
1979 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION)));
1980 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
1981 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_GS_VERTEX_REUSE)));
1982 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
1983 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE)));
1984 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
1985 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_CL_ENHANCE)));
1986 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
1987 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE)));
1988
1989 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
1990 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)));
1991 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
1992 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT)));
1993 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
1994 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID)));
1995
1996 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
1997 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_SEM_WAIT_TIMER)));
1998
1999 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
2000 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY)));
2001 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
2002 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID)));
2003 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
2004 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL)));
2005 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
2006 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR)));
2007 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
2008 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR)));
2009 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
2010 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI)));
2011 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
2012 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL)));
2013 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
2014 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE)));
2015 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
2016 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI)));
2017 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
2018 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL)));
2019
2020 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
2021 RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_ADDR)));
2022 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
2023 RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_UMSK)));
2024
2025 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
2026 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)));
2027 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
2028 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL)));
2029 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
2030 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)));
2031 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
2032 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)));
2033 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
2034 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_INIT)));
2035 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
2036 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_MAX)));
2037 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
2038 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_INIT_CU_MASK)));
2039 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
2040 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_PARAMS)));
2041 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
2042 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL)));
2043 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
2044 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_UCODE_CNTL)));
2045
2046 dev_info(adev->dev, " RLC_GPM_GENERAL_6=0x%08X\n",
2047 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6)));
2048 dev_info(adev->dev, " RLC_GPM_GENERAL_12=0x%08X\n",
2049 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12)));
2050 dev_info(adev->dev, " RLC_GPM_TIMER_INT_3=0x%08X\n",
2051 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3)));
2052 mutex_lock(&adev->srbm_mutex);
2053 for (i = 0; i < 16; i++) {
2054 soc15_grbm_select(adev, 0, 0, 0, i);
2055 dev_info(adev->dev, " VM %d:\n", i);
2056 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
2057 RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)));
2058 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
2059 RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES)));
2060 }
2061 soc15_grbm_select(adev, 0, 0, 0, 0);
2062 mutex_unlock(&adev->srbm_mutex);
2063}
2064
2065static int gfx_v9_0_soft_reset(void *handle)
2066{
2067 u32 grbm_soft_reset = 0;
2068 u32 tmp;
2069 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2070
2071 /* GRBM_STATUS */
2072 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS));
2073 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2074 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2075 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2076 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2077 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2078 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2079 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2080 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2081 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2082 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2083 }
2084
2085 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2086 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2087 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2088 }
2089
2090 /* GRBM_STATUS2 */
2091 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2));
2092 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2093 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2094 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2095
2096
2097 if (grbm_soft_reset ) {
2098 gfx_v9_0_print_status((void *)adev);
2099 /* stop the rlc */
2100 gfx_v9_0_rlc_stop(adev);
2101
2102 /* Disable GFX parsing/prefetching */
2103 gfx_v9_0_cp_gfx_enable(adev, false);
2104
2105 /* Disable MEC parsing/prefetching */
2106 gfx_v9_0_cp_compute_enable(adev, false);
2107
2108 if (grbm_soft_reset) {
2109 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2110 tmp |= grbm_soft_reset;
2111 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2112 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
2113 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2114
2115 udelay(50);
2116
2117 tmp &= ~grbm_soft_reset;
2118 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
2119 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2120 }
2121
2122 /* Wait a little for things to settle down */
2123 udelay(50);
2124 gfx_v9_0_print_status((void *)adev);
2125 }
2126 return 0;
2127}
2128
2129static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2130{
2131 uint64_t clock;
2132
2133 mutex_lock(&adev->gfx.gpu_clock_mutex);
2134 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT), 1);
2135 clock = (uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB)) |
2136 ((uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB)) << 32ULL);
2137 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2138 return clock;
2139}
2140
2141static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
2142 uint32_t vmid,
2143 uint32_t gds_base, uint32_t gds_size,
2144 uint32_t gws_base, uint32_t gws_size,
2145 uint32_t oa_base, uint32_t oa_size)
2146{
2147 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
2148 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
2149
2150 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
2151 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
2152
2153 oa_base = oa_base >> AMDGPU_OA_SHIFT;
2154 oa_size = oa_size >> AMDGPU_OA_SHIFT;
2155
2156 /* GDS Base */
2157 gfx_v9_0_write_data_to_reg(ring, 0, false,
2158 amdgpu_gds_reg_offset[vmid].mem_base,
2159 gds_base);
2160
2161 /* GDS Size */
2162 gfx_v9_0_write_data_to_reg(ring, 0, false,
2163 amdgpu_gds_reg_offset[vmid].mem_size,
2164 gds_size);
2165
2166 /* GWS */
2167 gfx_v9_0_write_data_to_reg(ring, 0, false,
2168 amdgpu_gds_reg_offset[vmid].gws,
2169 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2170
2171 /* OA */
2172 gfx_v9_0_write_data_to_reg(ring, 0, false,
2173 amdgpu_gds_reg_offset[vmid].oa,
2174 (1 << (oa_size + oa_base)) - (1 << oa_base));
2175}
2176
2177static int gfx_v9_0_early_init(void *handle)
2178{
2179 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2180
2181 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
2182 adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS;
2183 gfx_v9_0_set_ring_funcs(adev);
2184 gfx_v9_0_set_irq_funcs(adev);
2185 gfx_v9_0_set_gds_init(adev);
2186 gfx_v9_0_set_rlc_funcs(adev);
2187
2188 return 0;
2189}
2190
2191static int gfx_v9_0_late_init(void *handle)
2192{
2193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2194 int r;
2195
2196 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2197 if (r)
2198 return r;
2199
2200 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2201 if (r)
2202 return r;
2203
2204 return 0;
2205}
2206
2207static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
2208{
2209 uint32_t rlc_setting, data;
2210 unsigned i;
2211
2212 if (adev->gfx.rlc.in_safe_mode)
2213 return;
2214
2215 /* if RLC is not enabled, do nothing */
2216 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
2217 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2218 return;
2219
2220 if (adev->cg_flags &
2221 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
2222 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2223 data = RLC_SAFE_MODE__CMD_MASK;
2224 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
2225 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data);
2226
2227 /* wait for RLC_SAFE_MODE */
2228 for (i = 0; i < adev->usec_timeout; i++) {
2229 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
2230 break;
2231 udelay(1);
2232 }
2233 adev->gfx.rlc.in_safe_mode = true;
2234 }
2235}
2236
2237static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
2238{
2239 uint32_t rlc_setting, data;
2240
2241 if (!adev->gfx.rlc.in_safe_mode)
2242 return;
2243
2244 /* if RLC is not enabled, do nothing */
2245 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
2246 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2247 return;
2248
2249 if (adev->cg_flags &
2250 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
2251 /*
2252 * Try to exit safe mode only if it is already in safe
2253 * mode.
2254 */
2255 data = RLC_SAFE_MODE__CMD_MASK;
2256 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data);
2257 adev->gfx.rlc.in_safe_mode = false;
2258 }
2259}
2260
2261static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2262 bool enable)
2263{
2264 uint32_t data, def;
2265
2266 /* It is disabled by HW by default */
2267 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2268 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2269 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2270 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2271 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2272 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2273 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2274
2275 /* only for Vega10 & Raven1 */
2276 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
2277
2278 if (def != data)
2279 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2280
2281 /* MGLS is a global flag to control all MGLS in GFX */
2282 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2283 /* 2 - RLC memory Light sleep */
2284 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2285 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2286 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2287 if (def != data)
2288 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data);
2289 }
2290 /* 3 - CP memory Light sleep */
2291 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2292 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2293 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2294 if (def != data)
2295 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data);
2296 }
2297 }
2298 } else {
2299 /* 1 - MGCG_OVERRIDE */
2300 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2301 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2302 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2303 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2304 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2305 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2306 if (def != data)
2307 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2308
2309 /* 2 - disable MGLS in RLC */
2310 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2311 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2312 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2313 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data);
2314 }
2315
2316 /* 3 - disable MGLS in CP */
2317 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2318 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2319 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2320 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data);
2321 }
2322 }
2323}
2324
2325static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
2326 bool enable)
2327{
2328 uint32_t data, def;
2329
2330 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2331
2332 /* Enable 3D CGCG/CGLS */
2333 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2334 /* write cmd to clear cgcg/cgls ov */
2335 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2336 /* unset CGCG override */
2337 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
2338 /* update CGCG and CGLS override bits */
2339 if (def != data)
2340 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2341 /* enable 3Dcgcg FSM(0x0020003f) */
2342 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2343 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2344 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
2345 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
2346 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2347 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
2348 if (def != data)
2349 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data);
2350
2351 /* set IDLE_POLL_COUNT(0x00900100) */
2352 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2353 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2354 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2355 if (def != data)
2356 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2357 } else {
2358 /* Disable CGCG/CGLS */
2359 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2360 /* disable cgcg, cgls should be disabled */
2361 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
2362 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
2363 /* disable cgcg and cgls in FSM */
2364 if (def != data)
2365 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data);
2366 }
2367
2368 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2369}
2370
2371static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2372 bool enable)
2373{
2374 uint32_t def, data;
2375
2376 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2377
2378 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2379 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2380 /* unset CGCG override */
2381 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2382 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2383 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2384 else
2385 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2386 /* update CGCG and CGLS override bits */
2387 if (def != data)
2388 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2389
2390 /* enable cgcg FSM(0x0020003F) */
2391 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2392 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2393 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2394 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2395 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2396 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2397 if (def != data)
2398 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data);
2399
2400 /* set IDLE_POLL_COUNT(0x00900100) */
2401 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2402 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2403 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2404 if (def != data)
2405 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2406 } else {
2407 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2408 /* reset CGCG/CGLS bits */
2409 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2410 /* disable cgcg and cgls in FSM */
2411 if (def != data)
2412 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data);
2413 }
2414
2415 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2416}
2417
2418static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
2419 bool enable)
2420{
2421 if (enable) {
2422 /* CGCG/CGLS should be enabled after MGCG/MGLS
2423 * === MGCG + MGLS ===
2424 */
2425 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2426 /* === CGCG /CGLS for GFX 3D Only === */
2427 gfx_v9_0_update_3d_clock_gating(adev, enable);
2428 /* === CGCG + CGLS === */
2429 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2430 } else {
2431 /* CGCG/CGLS should be disabled before MGCG/MGLS
2432 * === CGCG + CGLS ===
2433 */
2434 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2435 /* === CGCG /CGLS for GFX 3D Only === */
2436 gfx_v9_0_update_3d_clock_gating(adev, enable);
2437 /* === MGCG + MGLS === */
2438 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2439 }
2440 return 0;
2441}
2442
2443static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
2444 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
2445 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
2446};
2447
2448static int gfx_v9_0_set_powergating_state(void *handle,
2449 enum amd_powergating_state state)
2450{
2451 return 0;
2452}
2453
2454static int gfx_v9_0_set_clockgating_state(void *handle,
2455 enum amd_clockgating_state state)
2456{
2457 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2458
2459 switch (adev->asic_type) {
2460 case CHIP_VEGA10:
2461 gfx_v9_0_update_gfx_clock_gating(adev,
2462 state == AMD_CG_STATE_GATE ? true : false);
2463 break;
2464 default:
2465 break;
2466 }
2467 return 0;
2468}
2469
2470static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2471{
2472 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
2473}
2474
2475static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2476{
2477 struct amdgpu_device *adev = ring->adev;
2478 u64 wptr;
2479
2480 /* XXX check if swapping is necessary on BE */
2481 if (ring->use_doorbell) {
2482 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
2483 } else {
2484 wptr = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR));
2485 wptr += (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI)) << 32;
2486 }
2487
2488 return wptr;
2489}
2490
2491static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2492{
2493 struct amdgpu_device *adev = ring->adev;
2494
2495 if (ring->use_doorbell) {
2496 /* XXX check if swapping is necessary on BE */
2497 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2498 WDOORBELL64(ring->doorbell_index, ring->wptr);
2499 } else {
2500 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr));
2501 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr));
2502 }
2503}
2504
2505static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2506{
2507 u32 ref_and_mask, reg_mem_engine;
2508 struct nbio_hdp_flush_reg *nbio_hf_reg;
2509
2510 if (ring->adev->asic_type == CHIP_VEGA10)
2511 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
2512
2513 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2514 switch (ring->me) {
2515 case 1:
2516 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2517 break;
2518 case 2:
2519 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2520 break;
2521 default:
2522 return;
2523 }
2524 reg_mem_engine = 0;
2525 } else {
2526 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2527 reg_mem_engine = 1; /* pfp */
2528 }
2529
2530 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2531 nbio_hf_reg->hdp_flush_req_offset,
2532 nbio_hf_reg->hdp_flush_done_offset,
2533 ref_and_mask, ref_and_mask, 0x20);
2534}
2535
2536static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2537{
2538 gfx_v9_0_write_data_to_reg(ring, 0, true,
2539 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
2540}
2541
2542static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2543 struct amdgpu_ib *ib,
2544 unsigned vm_id, bool ctx_switch)
2545{
2546 u32 header, control = 0;
2547
2548 if (ib->flags & AMDGPU_IB_FLAG_CE)
2549 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2550 else
2551 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2552
2553 control |= ib->length_dw | (vm_id << 24);
2554
2555 amdgpu_ring_write(ring, header);
2556 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2557 amdgpu_ring_write(ring,
2558#ifdef __BIG_ENDIAN
2559 (2 << 0) |
2560#endif
2561 lower_32_bits(ib->gpu_addr));
2562 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2563 amdgpu_ring_write(ring, control);
2564}
2565
2566#define INDIRECT_BUFFER_VALID (1 << 23)
2567
2568static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2569 struct amdgpu_ib *ib,
2570 unsigned vm_id, bool ctx_switch)
2571{
2572 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2573
2574 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2575 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2576 amdgpu_ring_write(ring,
2577#ifdef __BIG_ENDIAN
2578 (2 << 0) |
2579#endif
2580 lower_32_bits(ib->gpu_addr));
2581 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2582 amdgpu_ring_write(ring, control);
2583}
2584
2585static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2586 u64 seq, unsigned flags)
2587{
2588 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2589 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2590
2591 /* RELEASE_MEM - flush caches, send int */
2592 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2593 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2594 EOP_TC_ACTION_EN |
2595 EOP_TC_WB_ACTION_EN |
2596 EOP_TC_MD_ACTION_EN |
2597 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2598 EVENT_INDEX(5)));
2599 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2600
2601 /*
2602 * the address should be Qword aligned if 64bit write, Dword
2603 * aligned if only send 32bit data low (discard data high)
2604 */
2605 if (write64bit)
2606 BUG_ON(addr & 0x7);
2607 else
2608 BUG_ON(addr & 0x3);
2609 amdgpu_ring_write(ring, lower_32_bits(addr));
2610 amdgpu_ring_write(ring, upper_32_bits(addr));
2611 amdgpu_ring_write(ring, lower_32_bits(seq));
2612 amdgpu_ring_write(ring, upper_32_bits(seq));
2613 amdgpu_ring_write(ring, 0);
2614}
2615
2616static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2617{
2618 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2619 uint32_t seq = ring->fence_drv.sync_seq;
2620 uint64_t addr = ring->fence_drv.gpu_addr;
2621
2622 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
2623 lower_32_bits(addr), upper_32_bits(addr),
2624 seq, 0xffffffff, 4);
2625}
2626
2627static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2628 unsigned vm_id, uint64_t pd_addr)
2629{
2630 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2631 unsigned eng = ring->idx;
2632 unsigned i;
2633
2634 pd_addr = pd_addr | 0x1; /* valid bit */
2635 /* now only use physical base address of PDE and valid */
2636 BUG_ON(pd_addr & 0xFFFF00000000003EULL);
2637
2638 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2639 struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
2640 uint32_t req = hub->get_invalidate_req(vm_id);
2641
2642 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2643 hub->ctx0_ptb_addr_lo32
2644 + (2 * vm_id),
2645 lower_32_bits(pd_addr));
2646
2647 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2648 hub->ctx0_ptb_addr_hi32
2649 + (2 * vm_id),
2650 upper_32_bits(pd_addr));
2651
2652 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2653 hub->vm_inv_eng0_req + eng, req);
2654
2655 /* wait for the invalidate to complete */
2656 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
2657 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
2658 }
2659
2660 /* compute doesn't have PFP */
2661 if (usepfp) {
2662 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2663 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2664 amdgpu_ring_write(ring, 0x0);
2665 /* Emits 128 dw nop to prevent CE access VM before vm_flush finish */
2666 amdgpu_ring_insert_nop(ring, 128);
2667 }
2668}
2669
2670static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2671{
2672 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2673}
2674
2675static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2676{
2677 u64 wptr;
2678
2679 /* XXX check if swapping is necessary on BE */
2680 if (ring->use_doorbell)
2681 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
2682 else
2683 BUG();
2684 return wptr;
2685}
2686
2687static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2688{
2689 struct amdgpu_device *adev = ring->adev;
2690
2691 /* XXX check if swapping is necessary on BE */
2692 if (ring->use_doorbell) {
2693 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2694 WDOORBELL64(ring->doorbell_index, ring->wptr);
2695 } else{
2696 BUG(); /* only DOORBELL method supported on gfx9 now */
2697 }
2698}
2699
aa6faa44
XY		 2700static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
2701 u64 seq, unsigned int flags)
2702{
2703 /* we only allocate 32bit for each seq wb address */
2704 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
2705
2706 /* write fence seq to the "addr" */
2707 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2708 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2709 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
2710 amdgpu_ring_write(ring, lower_32_bits(addr));
2711 amdgpu_ring_write(ring, upper_32_bits(addr));
2712 amdgpu_ring_write(ring, lower_32_bits(seq));
2713
2714 if (flags & AMDGPU_FENCE_FLAG_INT) {
2715 /* set register to trigger INT */
2716 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2717 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2718 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
2719 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
2720 amdgpu_ring_write(ring, 0);
2721 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
2722 }
2723}
2724
b1023571
KW		 2725static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
2726{
2727 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2728 amdgpu_ring_write(ring, 0);
2729}
2730
2731static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2732{
2733 uint32_t dw2 = 0;
2734
2735 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2736 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2737 /* set load_global_config & load_global_uconfig */
2738 dw2 |= 0x8001;
2739 /* set load_cs_sh_regs */
2740 dw2 |= 0x01000000;
2741 /* set load_per_context_state & load_gfx_sh_regs for GFX */
2742 dw2 |= 0x10002;
2743
2744 /* set load_ce_ram if preamble presented */
2745 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
2746 dw2 |= 0x10000000;
2747 } else {
2748 /* still load_ce_ram if this is the first time preamble presented
2749 * although there is no context switch happens.
2750 */
2751 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
2752 dw2 |= 0x10000000;
2753 }
2754
2755 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2756 amdgpu_ring_write(ring, dw2);
2757 amdgpu_ring_write(ring, 0);
2758}
2759
aa6faa44
XY		 2760static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
2761{
2762 struct amdgpu_device *adev = ring->adev;
2763
2764 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
2765 amdgpu_ring_write(ring, 0 | /* src: register*/
2766 (5 << 8) | /* dst: memory */
2767 (1 << 20)); /* write confirm */
2768 amdgpu_ring_write(ring, reg);
2769 amdgpu_ring_write(ring, 0);
2770 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
2771 adev->virt.reg_val_offs * 4));
2772 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
2773 adev->virt.reg_val_offs * 4));
2774}
2775
2776static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
2777 uint32_t val)
2778{
2779 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2780 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
2781 amdgpu_ring_write(ring, reg);
2782 amdgpu_ring_write(ring, 0);
2783 amdgpu_ring_write(ring, val);
2784}
2785
b1023571
KW		 2786static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
2787 enum amdgpu_interrupt_state state)
2788{
2789 u32 cp_int_cntl;
2790
2791 switch (state) {
2792 case AMDGPU_IRQ_STATE_DISABLE:
2793 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2794 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2795 TIME_STAMP_INT_ENABLE, 0);
2796 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2797 break;
2798 case AMDGPU_IRQ_STATE_ENABLE:
2799 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2800 cp_int_cntl =
2801 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2802 TIME_STAMP_INT_ENABLE, 1);
2803 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2804 break;
2805 default:
2806 break;
2807 }
2808}
2809
2810static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
2811 int me, int pipe,
2812 enum amdgpu_interrupt_state state)
2813{
2814 u32 mec_int_cntl, mec_int_cntl_reg;
2815
2816 /*
2817 * amdgpu controls only pipe 0 of MEC1. That's why this function only
2818 * handles the setting of interrupts for this specific pipe. All other
2819 * pipes' interrupts are set by amdkfd.
2820 */
2821
2822 if (me == 1) {
2823 switch (pipe) {
2824 case 0:
2825 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
2826 break;
2827 default:
2828 DRM_DEBUG("invalid pipe %d\n", pipe);
2829 return;
2830 }
2831 } else {
2832 DRM_DEBUG("invalid me %d\n", me);
2833 return;
2834 }
2835
2836 switch (state) {
2837 case AMDGPU_IRQ_STATE_DISABLE:
2838 mec_int_cntl = RREG32(mec_int_cntl_reg);
2839 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2840 TIME_STAMP_INT_ENABLE, 0);
2841 WREG32(mec_int_cntl_reg, mec_int_cntl);
2842 break;
2843 case AMDGPU_IRQ_STATE_ENABLE:
2844 mec_int_cntl = RREG32(mec_int_cntl_reg);
2845 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2846 TIME_STAMP_INT_ENABLE, 1);
2847 WREG32(mec_int_cntl_reg, mec_int_cntl);
2848 break;
2849 default:
2850 break;
2851 }
2852}
2853
2854static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
2855 struct amdgpu_irq_src *source,
2856 unsigned type,
2857 enum amdgpu_interrupt_state state)
2858{
2859 u32 cp_int_cntl;
2860
2861 switch (state) {
2862 case AMDGPU_IRQ_STATE_DISABLE:
2863 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2864 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2865 PRIV_REG_INT_ENABLE, 0);
2866 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2867 break;
2868 case AMDGPU_IRQ_STATE_ENABLE:
2869 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2870 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2871 PRIV_REG_INT_ENABLE, 1);
2872 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2873 break;
2874 default:
2875 break;
2876 }
2877
2878 return 0;
2879}
2880
2881static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
2882 struct amdgpu_irq_src *source,
2883 unsigned type,
2884 enum amdgpu_interrupt_state state)
2885{
2886 u32 cp_int_cntl;
2887
2888 switch (state) {
2889 case AMDGPU_IRQ_STATE_DISABLE:
2890 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2891 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2892 PRIV_INSTR_INT_ENABLE, 0);
2893 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2894 break;
2895 case AMDGPU_IRQ_STATE_ENABLE:
2896 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2897 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2898 PRIV_INSTR_INT_ENABLE, 1);
2899 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2900 break;
2901 default:
2902 break;
2903 }
2904
2905 return 0;
2906}
2907
2908static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
2909 struct amdgpu_irq_src *src,
2910 unsigned type,
2911 enum amdgpu_interrupt_state state)
2912{
2913 switch (type) {
2914 case AMDGPU_CP_IRQ_GFX_EOP:
2915 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
2916 break;
2917 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
2918 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
2919 break;
2920 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
2921 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
2922 break;
2923 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
2924 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
2925 break;
2926 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
2927 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
2928 break;
2929 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
2930 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
2931 break;
2932 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
2933 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
2934 break;
2935 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
2936 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
2937 break;
2938 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
2939 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
2940 break;
2941 default:
2942 break;
2943 }
2944 return 0;
2945}
2946
2947static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
2948 struct amdgpu_irq_src *source,
2949 struct amdgpu_iv_entry *entry)
2950{
2951 int i;
2952 u8 me_id, pipe_id, queue_id;
2953 struct amdgpu_ring *ring;
2954
2955 DRM_DEBUG("IH: CP EOP\n");
2956 me_id = (entry->ring_id & 0x0c) >> 2;
2957 pipe_id = (entry->ring_id & 0x03) >> 0;
2958 queue_id = (entry->ring_id & 0x70) >> 4;
2959
2960 switch (me_id) {
2961 case 0:
2962 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
2963 break;
2964 case 1:
2965 case 2:
2966 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2967 ring = &adev->gfx.compute_ring[i];
2968 /* Per-queue interrupt is supported for MEC starting from VI.
2969 * The interrupt can only be enabled/disabled per pipe instead of per queue.
2970 */
2971 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
2972 amdgpu_fence_process(ring);
2973 }
2974 break;
2975 }
2976 return 0;
2977}
2978
2979static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
2980 struct amdgpu_irq_src *source,
2981 struct amdgpu_iv_entry *entry)
2982{
2983 DRM_ERROR("Illegal register access in command stream\n");
2984 schedule_work(&adev->reset_work);
2985 return 0;
2986}
2987
2988static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
2989 struct amdgpu_irq_src *source,
2990 struct amdgpu_iv_entry *entry)
2991{
2992 DRM_ERROR("Illegal instruction in command stream\n");
2993 schedule_work(&adev->reset_work);
2994 return 0;
2995}
2996
2997const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
2998 .name = "gfx_v9_0",
2999 .early_init = gfx_v9_0_early_init,
3000 .late_init = gfx_v9_0_late_init,
3001 .sw_init = gfx_v9_0_sw_init,
3002 .sw_fini = gfx_v9_0_sw_fini,
3003 .hw_init = gfx_v9_0_hw_init,
3004 .hw_fini = gfx_v9_0_hw_fini,
3005 .suspend = gfx_v9_0_suspend,
3006 .resume = gfx_v9_0_resume,
3007 .is_idle = gfx_v9_0_is_idle,
3008 .wait_for_idle = gfx_v9_0_wait_for_idle,
3009 .soft_reset = gfx_v9_0_soft_reset,
3010 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
3011 .set_powergating_state = gfx_v9_0_set_powergating_state,
3012};
3013
3014static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
3015 .type = AMDGPU_RING_TYPE_GFX,
3016 .align_mask = 0xff,
3017 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3018 .support_64bit_ptrs = true,
3019 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
3020 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
3021 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
3022 .emit_frame_size =
3023 20 + /* gfx_v9_0_ring_emit_gds_switch */
3024 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3025 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3026 8 + 8 + 8 +/* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
3027 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3028 128 + 66 + /* gfx_v9_0_ring_emit_vm_flush */
3029 2 + /* gfx_v9_ring_emit_sb */
3030 3, /* gfx_v9_ring_emit_cntxcntl */
3031 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
3032 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
3033 .emit_fence = gfx_v9_0_ring_emit_fence,
3034 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3035 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3036 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3037 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3038 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3039 .test_ring = gfx_v9_0_ring_test_ring,
3040 .test_ib = gfx_v9_0_ring_test_ib,
3041 .insert_nop = amdgpu_ring_insert_nop,
3042 .pad_ib = amdgpu_ring_generic_pad_ib,
3043 .emit_switch_buffer = gfx_v9_ring_emit_sb,
3044 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
3045};
3046
3047static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
3048 .type = AMDGPU_RING_TYPE_COMPUTE,
3049 .align_mask = 0xff,
3050 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3051 .support_64bit_ptrs = true,
3052 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3053 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3054 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3055 .emit_frame_size =
3056 20 + /* gfx_v9_0_ring_emit_gds_switch */
3057 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3058 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3059 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3060 64 + /* gfx_v9_0_ring_emit_vm_flush */
3061 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
3062 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3063 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3064 .emit_fence = gfx_v9_0_ring_emit_fence,
3065 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3066 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3067 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3068 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3069 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3070 .test_ring = gfx_v9_0_ring_test_ring,
3071 .test_ib = gfx_v9_0_ring_test_ib,
3072 .insert_nop = amdgpu_ring_insert_nop,
3073 .pad_ib = amdgpu_ring_generic_pad_ib,
3074};
3075
aa6faa44
XY		 3076static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
3077 .type = AMDGPU_RING_TYPE_KIQ,
3078 .align_mask = 0xff,
3079 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3080 .support_64bit_ptrs = true,
3081 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3082 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3083 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3084 .emit_frame_size =
3085 20 + /* gfx_v9_0_ring_emit_gds_switch */
3086 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3087 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3088 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3089 64 + /* gfx_v9_0_ring_emit_vm_flush */
3090 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
3091 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3092 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3093 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
3094 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3095 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3096 .test_ring = gfx_v9_0_ring_test_ring,
3097 .test_ib = gfx_v9_0_ring_test_ib,
3098 .insert_nop = amdgpu_ring_insert_nop,
3099 .pad_ib = amdgpu_ring_generic_pad_ib,
3100 .emit_rreg = gfx_v9_0_ring_emit_rreg,
3101 .emit_wreg = gfx_v9_0_ring_emit_wreg,
3102};
b1023571
KW		 3103
3104static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
3105{
3106 int i;
3107
aa6faa44
XY		 3108 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
3109
b1023571
KW		 3110 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3111 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
3112
3113 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3114 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
3115}
3116
3117static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
3118 .set = gfx_v9_0_set_eop_interrupt_state,
3119 .process = gfx_v9_0_eop_irq,
3120};
3121
3122static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
3123 .set = gfx_v9_0_set_priv_reg_fault_state,
3124 .process = gfx_v9_0_priv_reg_irq,
3125};
3126
3127static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
3128 .set = gfx_v9_0_set_priv_inst_fault_state,
3129 .process = gfx_v9_0_priv_inst_irq,
3130};
3131
3132static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
3133{
3134 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3135 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
3136
3137 adev->gfx.priv_reg_irq.num_types = 1;
3138 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
3139
3140 adev->gfx.priv_inst_irq.num_types = 1;
3141 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
3142}
3143
3144static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
3145{
3146 switch (adev->asic_type) {
3147 case CHIP_VEGA10:
3148 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
3149 break;
3150 default:
3151 break;
3152 }
3153}
3154
3155static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
3156{
3157 /* init asci gds info */
3158 adev->gds.mem.total_size = RREG32(SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
3159 adev->gds.gws.total_size = 64;
3160 adev->gds.oa.total_size = 16;
3161
3162 if (adev->gds.mem.total_size == 64 * 1024) {
3163 adev->gds.mem.gfx_partition_size = 4096;
3164 adev->gds.mem.cs_partition_size = 4096;
3165
3166 adev->gds.gws.gfx_partition_size = 4;
3167 adev->gds.gws.cs_partition_size = 4;
3168
3169 adev->gds.oa.gfx_partition_size = 4;
3170 adev->gds.oa.cs_partition_size = 1;
3171 } else {
3172 adev->gds.mem.gfx_partition_size = 1024;
3173 adev->gds.mem.cs_partition_size = 1024;
3174
3175 adev->gds.gws.gfx_partition_size = 16;
3176 adev->gds.gws.cs_partition_size = 16;
3177
3178 adev->gds.oa.gfx_partition_size = 4;
3179 adev->gds.oa.cs_partition_size = 4;
3180 }
3181}
3182
3183static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3184{
3185 u32 data, mask;
3186
3187 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG));
3188 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG));
3189
3190 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3191 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3192
3193 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3194
3195 return (~data) & mask;
3196}
3197
3198static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
3199 struct amdgpu_cu_info *cu_info)
3200{
3201 int i, j, k, counter, active_cu_number = 0;
3202 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3203
3204 if (!adev || !cu_info)
3205 return -EINVAL;
3206
3207 memset(cu_info, 0, sizeof(*cu_info));
3208
3209 mutex_lock(&adev->grbm_idx_mutex);
3210 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3211 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3212 mask = 1;
3213 ao_bitmap = 0;
3214 counter = 0;
3215 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
3216 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
3217 cu_info->bitmap[i][j] = bitmap;
3218
3219 for (k = 0; k < 16; k ++) {
3220 if (bitmap & mask) {
3221 if (counter < 2)
3222 ao_bitmap |= mask;
3223 counter ++;
3224 }
3225 mask <<= 1;
3226 }
3227 active_cu_number += counter;
3228 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3229 }
3230 }
3231 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3232 mutex_unlock(&adev->grbm_idx_mutex);
3233
3234 cu_info->number = active_cu_number;
3235 cu_info->ao_cu_mask = ao_cu_mask;
3236
3237 return 0;
3238}
3239
3240static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
3241{
3242 int r, j;
3243 u32 tmp;
3244 bool use_doorbell = true;
3245 u64 hqd_gpu_addr;
3246 u64 mqd_gpu_addr;
3247 u64 eop_gpu_addr;
3248 u64 wb_gpu_addr;
3249 u32 *buf;
3250 struct v9_mqd *mqd;
3251 struct amdgpu_device *adev;
3252
3253 adev = ring->adev;
3254 if (ring->mqd_obj == NULL) {
3255 r = amdgpu_bo_create(adev,
3256 sizeof(struct v9_mqd),
3257 PAGE_SIZE,true,
3258 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3259 NULL, &ring->mqd_obj);
3260 if (r) {
3261 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3262 return r;
3263 }
3264 }
3265
3266 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3267 if (unlikely(r != 0)) {
3268 gfx_v9_0_cp_compute_fini(adev);
3269 return r;
3270 }
3271
3272 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3273 &mqd_gpu_addr);
3274 if (r) {
3275 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3276 gfx_v9_0_cp_compute_fini(adev);
3277 return r;
3278 }
3279 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3280 if (r) {
3281 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3282 gfx_v9_0_cp_compute_fini(adev);
3283 return r;
3284 }
3285
3286 /* init the mqd struct */
3287 memset(buf, 0, sizeof(struct v9_mqd));
3288
3289 mqd = (struct v9_mqd *)buf;
3290 mqd->header = 0xC0310800;
3291 mqd->compute_pipelinestat_enable = 0x00000001;
3292 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3293 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3294 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3295 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3296 mqd->compute_misc_reserved = 0x00000003;
3297 mutex_lock(&adev->srbm_mutex);
3298 soc15_grbm_select(adev, ring->me,
3299 ring->pipe,
3300 ring->queue, 0);
3301 /* disable wptr polling */
3302 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));
3303 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3304 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
3305
3306 /* write the EOP addr */
3307 BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
3308 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
3309 eop_gpu_addr >>= 8;
3310
3311 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR), lower_32_bits(eop_gpu_addr));
3312 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), upper_32_bits(eop_gpu_addr));
3313 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
3314 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
3315
3316 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3317 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL));
3318 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3319 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3320 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL), tmp);
3321
3322 /* enable doorbell? */
3323 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
3324 if (use_doorbell)
3325 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3326 else
3327 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3328
3329 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), tmp);
3330 mqd->cp_hqd_pq_doorbell_control = tmp;
3331
3332 /* disable the queue if it's active */
3333 ring->wptr = 0;
3334 mqd->cp_hqd_dequeue_request = 0;
3335 mqd->cp_hqd_pq_rptr = 0;
3336 mqd->cp_hqd_pq_wptr_lo = 0;
3337 mqd->cp_hqd_pq_wptr_hi = 0;
3338 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) {
3339 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1);
3340 for (j = 0; j < adev->usec_timeout; j++) {
3341 if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1))
3342 break;
3343 udelay(1);
3344 }
3345 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), mqd->cp_hqd_dequeue_request);
3346 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR), mqd->cp_hqd_pq_rptr);
3347 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo);
3348 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi);
3349 }
3350
3351 /* set the pointer to the MQD */
3352 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3353 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3354 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR), mqd->cp_mqd_base_addr_lo);
3355 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI), mqd->cp_mqd_base_addr_hi);
3356
3357 /* set MQD vmid to 0 */
3358 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL));
3359 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3360 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL), tmp);
3361 mqd->cp_mqd_control = tmp;
3362
3363 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3364 hqd_gpu_addr = ring->gpu_addr >> 8;
3365 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3366 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3367 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE), mqd->cp_hqd_pq_base_lo);
3368 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI), mqd->cp_hqd_pq_base_hi);
3369
3370 /* set up the HQD, this is similar to CP_RB0_CNTL */
3371 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL));
3372 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3373 (order_base_2(ring->ring_size / 4) - 1));
3374 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3375 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3376#ifdef __BIG_ENDIAN
3377 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3378#endif
3379 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3380 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3381 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3382 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3383 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL), tmp);
3384 mqd->cp_hqd_pq_control = tmp;
3385
3386 /* set the wb address wether it's enabled or not */
3387 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3388 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3389 mqd->cp_hqd_pq_rptr_report_addr_hi =
3390 upper_32_bits(wb_gpu_addr) & 0xffff;
3391 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR),
3392 mqd->cp_hqd_pq_rptr_report_addr_lo);
3393 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI),
3394 mqd->cp_hqd_pq_rptr_report_addr_hi);
3395
3396 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3397 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3398 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3399 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3400 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
3401 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3402 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
3403 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3404
3405 /* enable the doorbell if requested */
3406 if (use_doorbell) {
3407 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER),
3408 (AMDGPU_DOORBELL64_KIQ * 2) << 2);
3409 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER),
3410 (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
3411 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
3412 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3413 DOORBELL_OFFSET, ring->doorbell_index);
3414 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3415 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3416 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3417 mqd->cp_hqd_pq_doorbell_control = tmp;
3418
3419 } else {
3420 mqd->cp_hqd_pq_doorbell_control = 0;
3421 }
3422 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
3423 mqd->cp_hqd_pq_doorbell_control);
3424
3425 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3426 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo);
3427 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi);
3428
3429 /* set the vmid for the queue */
3430 mqd->cp_hqd_vmid = 0;
3431 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid);
3432
3433 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE));
3434 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3435 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE), tmp);
3436 mqd->cp_hqd_persistent_state = tmp;
3437
3438 /* activate the queue */
3439 mqd->cp_hqd_active = 1;
3440 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), mqd->cp_hqd_active);
3441
3442 soc15_grbm_select(adev, 0, 0, 0, 0);
3443 mutex_unlock(&adev->srbm_mutex);
3444
3445 amdgpu_bo_kunmap(ring->mqd_obj);
3446 amdgpu_bo_unreserve(ring->mqd_obj);
3447
3448 if (use_doorbell) {
3449 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));
3450 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3451 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
3452 }
3453
3454 return 0;
3455}
3456
3457const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
3458{
3459 .type = AMD_IP_BLOCK_TYPE_GFX,
3460 .major = 9,
3461 .minor = 0,
3462 .rev = 0,
3463 .funcs = &gfx_v9_0_ip_funcs,
3464};
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